1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
280 dag Outs, dag NonTiedIns, string OpcodeStr,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_common<O, F, _, Outs,
284 !con((ins _.RC:$src1), NonTiedIns),
285 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
288 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
290 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
293 string AttSrcAsm, string IntelSrcAsm,
295 AVX512_maskable_custom<O, F, Outs, Ins,
296 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
297 !con((ins _.KRCWM:$mask), Ins),
298 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
302 // Instruction with mask that puts result in mask register,
303 // like "compare" and "vptest"
304 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
306 dag Ins, dag MaskingIns,
308 string AttSrcAsm, string IntelSrcAsm,
310 list<dag> MaskingPattern,
312 InstrItinClass itin = NoItinerary> {
313 def NAME: AVX512<O, F, Outs, Ins,
314 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
315 "$dst "#Round#", "#IntelSrcAsm#"}",
318 def NAME#k: AVX512<O, F, Outs, MaskingIns,
319 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
320 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
321 MaskingPattern, itin>, EVEX_K;
324 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
326 dag Ins, dag MaskingIns,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, dag MaskingRHS,
331 InstrItinClass itin = NoItinerary> :
332 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
333 AttSrcAsm, IntelSrcAsm,
334 [(set _.KRC:$dst, RHS)],
335 [(set _.KRC:$dst, MaskingRHS)],
338 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
339 dag Outs, dag Ins, string OpcodeStr,
340 string AttSrcAsm, string IntelSrcAsm,
341 dag RHS, string Round = "",
342 InstrItinClass itin = NoItinerary> :
343 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
344 !con((ins _.KRCWM:$mask), Ins),
345 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
346 (and _.KRCWM:$mask, RHS),
349 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
350 dag Outs, dag Ins, string OpcodeStr,
351 string AttSrcAsm, string IntelSrcAsm> :
352 AVX512_maskable_custom_cmp<O, F, Outs,
353 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
354 AttSrcAsm, IntelSrcAsm,
355 [],[],"", NoItinerary>;
357 // Bitcasts between 512-bit vector types. Return the original type since
358 // no instruction is needed for the conversion
359 let Predicates = [HasAVX512] in {
360 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
364 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
369 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
374 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
379 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
385 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
389 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
396 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
401 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
406 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
411 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
416 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
420 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
421 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
423 // Bitcasts between 256-bit vector types. Return the original type since
424 // no instruction is needed for the conversion
425 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
429 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
434 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
439 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
444 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
449 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
453 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
454 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
458 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
461 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
462 isPseudo = 1, Predicates = [HasAVX512] in {
463 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
464 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
467 let Predicates = [HasAVX512] in {
468 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
469 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
470 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
473 //===----------------------------------------------------------------------===//
474 // AVX-512 - VECTOR INSERT
476 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert> {
478 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
479 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
480 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
481 "vinsert" # From.EltTypeName # "x" # From.NumElts,
482 "$src3, $src2, $src1", "$src1, $src2, $src3",
483 (vinsert_insert:$src3 (To.VT To.RC:$src1),
484 (From.VT From.RC:$src2),
485 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
488 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
489 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
490 "vinsert" # From.EltTypeName # "x" # From.NumElts,
491 "$src3, $src2, $src1", "$src1, $src2, $src3",
492 (vinsert_insert:$src3 (To.VT To.RC:$src1),
493 (From.VT (bitconvert (From.LdFrag addr:$src2))),
494 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
495 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
499 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
500 X86VectorVTInfo To, PatFrag vinsert_insert,
501 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
502 let Predicates = p in {
503 def : Pat<(vinsert_insert:$ins
504 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
505 (To.VT (!cast<Instruction>(InstrStr#"rr")
506 To.RC:$src1, From.RC:$src2,
507 (INSERT_get_vinsert_imm To.RC:$ins)))>;
509 def : Pat<(vinsert_insert:$ins
511 (From.VT (bitconvert (From.LdFrag addr:$src2))),
513 (To.VT (!cast<Instruction>(InstrStr#"rm")
514 To.RC:$src1, addr:$src2,
515 (INSERT_get_vinsert_imm To.RC:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
522 let Predicates = [HasVLX] in
523 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
524 X86VectorVTInfo< 4, EltVT32, VR128X>,
525 X86VectorVTInfo< 8, EltVT32, VR256X>,
526 vinsert128_insert>, EVEX_V256;
528 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
529 X86VectorVTInfo< 4, EltVT32, VR128X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 vinsert128_insert>, EVEX_V512;
533 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
534 X86VectorVTInfo< 4, EltVT64, VR256X>,
535 X86VectorVTInfo< 8, EltVT64, VR512>,
536 vinsert256_insert>, VEX_W, EVEX_V512;
538 let Predicates = [HasVLX, HasDQI] in
539 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 2, EltVT64, VR128X>,
541 X86VectorVTInfo< 4, EltVT64, VR256X>,
542 vinsert128_insert>, VEX_W, EVEX_V256;
544 let Predicates = [HasDQI] in {
545 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
546 X86VectorVTInfo< 2, EltVT64, VR128X>,
547 X86VectorVTInfo< 8, EltVT64, VR512>,
548 vinsert128_insert>, VEX_W, EVEX_V512;
550 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
551 X86VectorVTInfo< 8, EltVT32, VR256X>,
552 X86VectorVTInfo<16, EltVT32, VR512>,
553 vinsert256_insert>, EVEX_V512;
557 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
558 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
560 // Codegen pattern with the alternative types,
561 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
562 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
563 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
564 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
565 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
567 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
568 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
569 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
570 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
572 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
573 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
574 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
575 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
577 // Codegen pattern with the alternative types insert VEC128 into VEC256
578 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
582 // Codegen pattern with the alternative types insert VEC128 into VEC512
583 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
587 // Codegen pattern with the alternative types insert VEC256 into VEC512
588 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
593 // vinsertps - insert f32 to XMM
594 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
595 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
596 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
597 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
599 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
600 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
601 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
602 [(set VR128X:$dst, (X86insertps VR128X:$src1,
603 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
604 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
606 //===----------------------------------------------------------------------===//
607 // AVX-512 VECTOR EXTRACT
610 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
611 X86VectorVTInfo To> {
612 // A subvector extract from the first vector position is
613 // a subregister copy that needs no instruction.
614 def NAME # To.NumElts:
615 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
616 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
619 multiclass vextract_for_size<int Opcode,
620 X86VectorVTInfo From, X86VectorVTInfo To,
621 PatFrag vextract_extract> :
622 vextract_for_size_first_position_lowering<From, To> {
624 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
625 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
626 // vextract_extract), we interesting only in patterns without mask,
627 // intrinsics pattern match generated bellow.
628 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
629 (ins From.RC:$src1, i32u8imm:$idx),
630 "vextract" # To.EltTypeName # "x" # To.NumElts,
631 "$idx, $src1", "$src1, $idx",
632 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
634 AVX512AIi8Base, EVEX;
635 let mayStore = 1 in {
636 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
637 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
638 "vextract" # To.EltTypeName # "x" # To.NumElts #
639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
643 (ins To.MemOp:$dst, To.KRCWM:$mask,
644 From.RC:$src1, i32u8imm:$src2),
645 "vextract" # To.EltTypeName # "x" # To.NumElts #
646 "\t{$src2, $src1, $dst {${mask}}|"
647 "$dst {${mask}}, $src1, $src2}",
652 // Intrinsic call with masking.
653 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
654 "x" # To.NumElts # "_" # From.Size)
655 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
656 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
657 From.ZSuffix # "rrk")
659 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
660 From.RC:$src1, imm:$idx)>;
662 // Intrinsic call with zero-masking.
663 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
664 "x" # To.NumElts # "_" # From.Size)
665 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
666 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
667 From.ZSuffix # "rrkz")
668 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
669 From.RC:$src1, imm:$idx)>;
671 // Intrinsic call without masking.
672 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
673 "x" # To.NumElts # "_" # From.Size)
674 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
675 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
677 From.RC:$src1, imm:$idx)>;
680 // This multiclass generates patterns for matching vextract with common types
681 // (X86VectorVTInfo From , X86VectorVTInfo To) and alternative types
682 // (X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo)
683 multiclass vextract_for_size_all<int Opcode,
684 X86VectorVTInfo From, X86VectorVTInfo To,
685 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
686 PatFrag vextract_extract,
687 SDNodeXForm EXTRACT_get_vextract_imm> :
688 vextract_for_size<Opcode, From, To, vextract_extract>,
689 vextract_for_size_first_position_lowering<AltFrom, AltTo> {
691 // Codegen pattern with the alternative types.
692 // Only add this if operation not supported natively via AVX512DQ
693 let Predicates = [NoDQI] in
694 def : Pat<(vextract_extract:$ext (AltFrom.VT AltFrom.RC:$src1), (iPTR imm)),
695 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x" #
696 To.NumElts # From.ZSuffix # "rr")
698 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
701 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
702 ValueType EltVT64, int Opcode256> {
703 defm NAME # "32x4Z" : vextract_for_size_all<Opcode128,
704 X86VectorVTInfo<16, EltVT32, VR512>,
705 X86VectorVTInfo< 4, EltVT32, VR128X>,
706 X86VectorVTInfo< 8, EltVT64, VR512>,
707 X86VectorVTInfo< 2, EltVT64, VR128X>,
709 EXTRACT_get_vextract128_imm>,
710 EVEX_V512, EVEX_CD8<32, CD8VT4>;
711 defm NAME # "64x4Z" : vextract_for_size_all<Opcode256,
712 X86VectorVTInfo< 8, EltVT64, VR512>,
713 X86VectorVTInfo< 4, EltVT64, VR256X>,
714 X86VectorVTInfo<16, EltVT32, VR512>,
715 X86VectorVTInfo< 8, EltVT32, VR256>,
717 EXTRACT_get_vextract256_imm>,
718 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
719 let Predicates = [HasVLX] in
720 defm NAME # "32x4Z256" : vextract_for_size_all<Opcode128,
721 X86VectorVTInfo< 8, EltVT32, VR256X>,
722 X86VectorVTInfo< 4, EltVT32, VR128X>,
723 X86VectorVTInfo< 4, EltVT64, VR256X>,
724 X86VectorVTInfo< 2, EltVT64, VR128X>,
726 EXTRACT_get_vextract128_imm>,
727 EVEX_V256, EVEX_CD8<32, CD8VT4>;
728 let Predicates = [HasVLX, HasDQI] in
729 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
730 X86VectorVTInfo< 4, EltVT64, VR256X>,
731 X86VectorVTInfo< 2, EltVT64, VR128X>,
732 vextract128_extract>,
733 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
734 let Predicates = [HasDQI] in {
735 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
736 X86VectorVTInfo< 8, EltVT64, VR512>,
737 X86VectorVTInfo< 2, EltVT64, VR128X>,
738 vextract128_extract>,
739 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
740 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
741 X86VectorVTInfo<16, EltVT32, VR512>,
742 X86VectorVTInfo< 8, EltVT32, VR256X>,
743 vextract256_extract>,
744 EVEX_V512, EVEX_CD8<32, CD8VT8>;
748 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
749 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
751 // A 128-bit subvector insert to the first 512-bit vector position
752 // is a subregister copy that needs no instruction.
753 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
754 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
755 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
757 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
758 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
759 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
761 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
762 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
763 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
765 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
766 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
767 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
770 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
771 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
772 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
773 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
774 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
775 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
776 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
777 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
779 // vextractps - extract 32 bits from XMM
780 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
781 (ins VR128X:$src1, u8imm:$src2),
782 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
783 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
786 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
787 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
788 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
789 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
790 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
792 //===---------------------------------------------------------------------===//
795 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
796 ValueType svt, X86VectorVTInfo _> {
797 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
798 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
799 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
803 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
804 (ins _.ScalarMemOp:$src),
805 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
806 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
811 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
812 AVX512VLVectorVTInfo _> {
813 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
816 let Predicates = [HasVLX] in {
817 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
822 let ExeDomain = SSEPackedSingle in {
823 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
824 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
825 let Predicates = [HasVLX] in {
826 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
827 v4f32, v4f32x_info>, EVEX_V128,
828 EVEX_CD8<32, CD8VT1>;
832 let ExeDomain = SSEPackedDouble in {
833 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
834 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
837 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
838 // Later, we can canonize broadcast instructions before ISel phase and
839 // eliminate additional patterns on ISel.
840 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
841 // representations of source
842 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
843 X86VectorVTInfo _, RegisterClass SrcRC_v,
844 RegisterClass SrcRC_s> {
845 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
846 (!cast<Instruction>(InstName##"r")
847 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
849 let AddedComplexity = 30 in {
850 def : Pat<(_.VT (vselect _.KRCWM:$mask,
851 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
852 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
853 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
855 def : Pat<(_.VT(vselect _.KRCWM:$mask,
856 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
857 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
858 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
862 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
864 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
867 let Predicates = [HasVLX] in {
868 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
869 v8f32x_info, VR128X, FR32X>;
870 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
871 v4f32x_info, VR128X, FR32X>;
872 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
873 v4f64x_info, VR128X, FR64X>;
876 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
877 (VBROADCASTSSZm addr:$src)>;
878 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
879 (VBROADCASTSDZm addr:$src)>;
881 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
882 (VBROADCASTSSZm addr:$src)>;
883 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
884 (VBROADCASTSDZm addr:$src)>;
886 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
887 RegisterClass SrcRC> {
888 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
889 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
890 "$src", "$src", []>, T8PD, EVEX;
893 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
894 RegisterClass SrcRC, Predicate prd> {
895 let Predicates = [prd] in
896 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
897 let Predicates = [prd, HasVLX] in {
898 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
899 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
903 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
905 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
907 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
909 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
912 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
913 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
915 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
916 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
918 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
919 (VPBROADCASTDrZr GR32:$src)>;
920 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
921 (VPBROADCASTQrZr GR64:$src)>;
923 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
924 (VPBROADCASTDrZr GR32:$src)>;
925 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
926 (VPBROADCASTQrZr GR64:$src)>;
928 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
929 (v16i32 immAllZerosV), (i16 GR16:$mask))),
930 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
931 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
932 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
933 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
935 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
936 X86MemOperand x86memop, PatFrag ld_frag,
937 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
939 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
940 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
942 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
943 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
945 !strconcat(OpcodeStr,
946 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
948 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
950 !strconcat(OpcodeStr,
951 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
954 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
957 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
958 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
960 !strconcat(OpcodeStr,
961 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
963 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
965 !strconcat(OpcodeStr,
966 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
967 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
968 (X86VBroadcast (ld_frag addr:$src)),
969 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
973 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
974 loadi32, VR512, v16i32, v4i32, VK16WM>,
975 EVEX_V512, EVEX_CD8<32, CD8VT1>;
976 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
977 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
978 EVEX_CD8<64, CD8VT1>;
980 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
981 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
983 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
984 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
986 (_Dst.VT (X86SubVBroadcast
987 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
988 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
990 !strconcat(OpcodeStr,
991 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
993 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
995 !strconcat(OpcodeStr,
996 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1001 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1002 v16i32_info, v4i32x_info>,
1003 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1004 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1005 v16f32_info, v4f32x_info>,
1006 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1007 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1008 v8i64_info, v4i64x_info>, VEX_W,
1009 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1010 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1011 v8f64_info, v4f64x_info>, VEX_W,
1012 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1014 let Predicates = [HasVLX] in {
1015 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1016 v8i32x_info, v4i32x_info>,
1017 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1018 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1019 v8f32x_info, v4f32x_info>,
1020 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1022 let Predicates = [HasVLX, HasDQI] in {
1023 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1024 v4i64x_info, v2i64x_info>, VEX_W,
1025 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1026 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1027 v4f64x_info, v2f64x_info>, VEX_W,
1028 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1030 let Predicates = [HasDQI] in {
1031 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1032 v8i64_info, v2i64x_info>, VEX_W,
1033 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1034 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1035 v16i32_info, v8i32x_info>,
1036 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1037 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1038 v8f64_info, v2f64x_info>, VEX_W,
1039 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1040 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1041 v16f32_info, v8f32x_info>,
1042 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1045 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
1046 (VPBROADCASTDZrr VR128X:$src)>;
1047 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
1048 (VPBROADCASTQZrr VR128X:$src)>;
1050 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1051 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1052 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1053 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1055 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1056 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1057 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1058 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1060 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
1061 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
1062 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
1063 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
1065 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
1066 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
1067 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
1068 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
1070 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1071 (VBROADCASTSSZr VR128X:$src)>;
1072 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1073 (VBROADCASTSDZr VR128X:$src)>;
1075 // Provide fallback in case the load node that is used in the patterns above
1076 // is used by additional users, which prevents the pattern selection.
1077 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1078 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1079 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1080 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1083 //===----------------------------------------------------------------------===//
1084 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1087 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1088 RegisterClass KRC> {
1089 let Predicates = [HasCDI] in
1090 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
1091 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1092 []>, EVEX, EVEX_V512;
1094 let Predicates = [HasCDI, HasVLX] in {
1095 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
1096 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1097 []>, EVEX, EVEX_V128;
1098 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
1099 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1100 []>, EVEX, EVEX_V256;
1104 let Predicates = [HasCDI] in {
1105 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1107 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1111 //===----------------------------------------------------------------------===//
1112 // -- VPERM2I - 3 source operands form --
1113 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1114 SDNode OpNode, X86VectorVTInfo _> {
1115 let Constraints = "$src1 = $dst" in {
1116 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1117 (ins _.RC:$src2, _.RC:$src3),
1118 OpcodeStr, "$src3, $src2", "$src2, $src3",
1119 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1123 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1124 (ins _.RC:$src2, _.MemOp:$src3),
1125 OpcodeStr, "$src3, $src2", "$src2, $src3",
1126 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1127 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1128 EVEX_4V, AVX5128IBase;
1131 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1132 SDNode OpNode, X86VectorVTInfo _> {
1133 let mayLoad = 1, Constraints = "$src1 = $dst" in
1134 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1135 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1136 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1137 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1138 (_.VT (OpNode _.RC:$src1,
1139 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1140 AVX5128IBase, EVEX_4V, EVEX_B;
1143 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1144 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1145 let Predicates = [HasAVX512] in
1146 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1147 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1148 let Predicates = [HasVLX] in {
1149 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1150 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1152 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1153 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1157 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1158 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1159 let Predicates = [HasBWI] in
1160 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1161 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1163 let Predicates = [HasBWI, HasVLX] in {
1164 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1165 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1167 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1168 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1172 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1173 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1174 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1175 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1176 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1177 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1178 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1179 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1181 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1182 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1183 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1184 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1185 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1186 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1187 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1188 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1190 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1191 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1192 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1193 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1195 //===----------------------------------------------------------------------===//
1196 // AVX-512 - BLEND using mask
1198 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1199 let ExeDomain = _.ExeDomain in {
1200 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1201 (ins _.RC:$src1, _.RC:$src2),
1202 !strconcat(OpcodeStr,
1203 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1205 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1206 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1207 !strconcat(OpcodeStr,
1208 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1209 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1210 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1211 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1212 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1213 !strconcat(OpcodeStr,
1214 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1215 []>, EVEX_4V, EVEX_KZ;
1216 let mayLoad = 1 in {
1217 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1218 (ins _.RC:$src1, _.MemOp:$src2),
1219 !strconcat(OpcodeStr,
1220 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1221 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1222 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1223 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1224 !strconcat(OpcodeStr,
1225 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1226 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1227 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1228 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1229 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1230 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1231 !strconcat(OpcodeStr,
1232 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1233 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1237 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1239 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1240 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1241 !strconcat(OpcodeStr,
1242 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1243 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1244 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1245 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1246 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1248 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1249 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1250 !strconcat(OpcodeStr,
1251 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1252 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1253 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1257 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1258 AVX512VLVectorVTInfo VTInfo> {
1259 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1260 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1262 let Predicates = [HasVLX] in {
1263 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1264 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1265 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1266 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1270 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1271 AVX512VLVectorVTInfo VTInfo> {
1272 let Predicates = [HasBWI] in
1273 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1275 let Predicates = [HasBWI, HasVLX] in {
1276 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1277 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1282 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1283 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1284 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1285 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1286 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1287 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1290 let Predicates = [HasAVX512] in {
1291 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1292 (v8f32 VR256X:$src2))),
1294 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1295 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1296 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1298 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1299 (v8i32 VR256X:$src2))),
1301 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1302 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1303 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1305 //===----------------------------------------------------------------------===//
1306 // Compare Instructions
1307 //===----------------------------------------------------------------------===//
1309 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1311 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1313 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1315 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1316 "vcmp${cc}"#_.Suffix,
1317 "$src2, $src1", "$src1, $src2",
1318 (OpNode (_.VT _.RC:$src1),
1322 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1324 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1325 "vcmp${cc}"#_.Suffix,
1326 "$src2, $src1", "$src1, $src2",
1327 (OpNode (_.VT _.RC:$src1),
1328 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1329 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1331 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1333 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1334 "vcmp${cc}"#_.Suffix,
1335 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1336 (OpNodeRnd (_.VT _.RC:$src1),
1339 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1340 // Accept explicit immediate argument form instead of comparison code.
1341 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1342 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1344 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1346 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1347 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1349 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1351 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1352 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1354 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1356 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1358 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1360 }// let isAsmParserOnly = 1, hasSideEffects = 0
1362 let isCodeGenOnly = 1 in {
1363 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1364 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1365 !strconcat("vcmp${cc}", _.Suffix,
1366 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1367 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1370 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1372 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1374 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1375 !strconcat("vcmp${cc}", _.Suffix,
1376 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1377 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1378 (_.ScalarLdFrag addr:$src2),
1380 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1384 let Predicates = [HasAVX512] in {
1385 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1387 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1388 AVX512XDIi8Base, VEX_W;
1391 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1392 X86VectorVTInfo _> {
1393 def rr : AVX512BI<opc, MRMSrcReg,
1394 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1395 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1396 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1397 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1399 def rm : AVX512BI<opc, MRMSrcMem,
1400 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1401 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1402 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1403 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1404 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1405 def rrk : AVX512BI<opc, MRMSrcReg,
1406 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1407 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1408 "$dst {${mask}}, $src1, $src2}"),
1409 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1410 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1411 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1413 def rmk : AVX512BI<opc, MRMSrcMem,
1414 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1415 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1416 "$dst {${mask}}, $src1, $src2}"),
1417 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1418 (OpNode (_.VT _.RC:$src1),
1420 (_.LdFrag addr:$src2))))))],
1421 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1424 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1425 X86VectorVTInfo _> :
1426 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1427 let mayLoad = 1 in {
1428 def rmb : AVX512BI<opc, MRMSrcMem,
1429 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1430 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1431 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1432 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1433 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1434 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1435 def rmbk : AVX512BI<opc, MRMSrcMem,
1436 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1437 _.ScalarMemOp:$src2),
1438 !strconcat(OpcodeStr,
1439 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1440 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1441 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1442 (OpNode (_.VT _.RC:$src1),
1444 (_.ScalarLdFrag addr:$src2)))))],
1445 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1449 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1450 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1451 let Predicates = [prd] in
1452 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1455 let Predicates = [prd, HasVLX] in {
1456 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1458 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1463 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1464 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1466 let Predicates = [prd] in
1467 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1470 let Predicates = [prd, HasVLX] in {
1471 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1473 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1478 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1479 avx512vl_i8_info, HasBWI>,
1482 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1483 avx512vl_i16_info, HasBWI>,
1484 EVEX_CD8<16, CD8VF>;
1486 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1487 avx512vl_i32_info, HasAVX512>,
1488 EVEX_CD8<32, CD8VF>;
1490 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1491 avx512vl_i64_info, HasAVX512>,
1492 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1494 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1495 avx512vl_i8_info, HasBWI>,
1498 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1499 avx512vl_i16_info, HasBWI>,
1500 EVEX_CD8<16, CD8VF>;
1502 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1503 avx512vl_i32_info, HasAVX512>,
1504 EVEX_CD8<32, CD8VF>;
1506 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1507 avx512vl_i64_info, HasAVX512>,
1508 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1510 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1511 (COPY_TO_REGCLASS (VPCMPGTDZrr
1512 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1513 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1515 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1516 (COPY_TO_REGCLASS (VPCMPEQDZrr
1517 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1518 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1520 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1521 X86VectorVTInfo _> {
1522 def rri : AVX512AIi8<opc, MRMSrcReg,
1523 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1524 !strconcat("vpcmp${cc}", Suffix,
1525 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1526 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1528 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1530 def rmi : AVX512AIi8<opc, MRMSrcMem,
1531 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1532 !strconcat("vpcmp${cc}", Suffix,
1533 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1534 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1535 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1537 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1538 def rrik : AVX512AIi8<opc, MRMSrcReg,
1539 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1541 !strconcat("vpcmp${cc}", Suffix,
1542 "\t{$src2, $src1, $dst {${mask}}|",
1543 "$dst {${mask}}, $src1, $src2}"),
1544 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1545 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1547 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1549 def rmik : AVX512AIi8<opc, MRMSrcMem,
1550 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1552 !strconcat("vpcmp${cc}", Suffix,
1553 "\t{$src2, $src1, $dst {${mask}}|",
1554 "$dst {${mask}}, $src1, $src2}"),
1555 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1556 (OpNode (_.VT _.RC:$src1),
1557 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1559 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1561 // Accept explicit immediate argument form instead of comparison code.
1562 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1563 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1564 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1565 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1566 "$dst, $src1, $src2, $cc}"),
1567 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1569 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1570 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1571 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1572 "$dst, $src1, $src2, $cc}"),
1573 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1574 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1575 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1577 !strconcat("vpcmp", Suffix,
1578 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1579 "$dst {${mask}}, $src1, $src2, $cc}"),
1580 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1582 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1583 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1585 !strconcat("vpcmp", Suffix,
1586 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1587 "$dst {${mask}}, $src1, $src2, $cc}"),
1588 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1592 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1593 X86VectorVTInfo _> :
1594 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1595 def rmib : AVX512AIi8<opc, MRMSrcMem,
1596 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1598 !strconcat("vpcmp${cc}", Suffix,
1599 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1600 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1601 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1602 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1604 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1605 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1606 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1607 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1608 !strconcat("vpcmp${cc}", Suffix,
1609 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1610 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1611 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1612 (OpNode (_.VT _.RC:$src1),
1613 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1615 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1617 // Accept explicit immediate argument form instead of comparison code.
1618 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1619 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1620 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1622 !strconcat("vpcmp", Suffix,
1623 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1624 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1625 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1626 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1627 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1628 _.ScalarMemOp:$src2, u8imm:$cc),
1629 !strconcat("vpcmp", Suffix,
1630 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1631 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1632 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1636 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1637 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1638 let Predicates = [prd] in
1639 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1641 let Predicates = [prd, HasVLX] in {
1642 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1643 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1647 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1648 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1649 let Predicates = [prd] in
1650 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1653 let Predicates = [prd, HasVLX] in {
1654 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1656 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1661 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1662 HasBWI>, EVEX_CD8<8, CD8VF>;
1663 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1664 HasBWI>, EVEX_CD8<8, CD8VF>;
1666 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1667 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1668 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1669 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1671 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1672 HasAVX512>, EVEX_CD8<32, CD8VF>;
1673 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1674 HasAVX512>, EVEX_CD8<32, CD8VF>;
1676 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1677 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1678 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1679 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1681 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1683 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1684 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1685 "vcmp${cc}"#_.Suffix,
1686 "$src2, $src1", "$src1, $src2",
1687 (X86cmpm (_.VT _.RC:$src1),
1691 let mayLoad = 1 in {
1692 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1693 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1694 "vcmp${cc}"#_.Suffix,
1695 "$src2, $src1", "$src1, $src2",
1696 (X86cmpm (_.VT _.RC:$src1),
1697 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1700 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1702 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1703 "vcmp${cc}"#_.Suffix,
1704 "${src2}"##_.BroadcastStr##", $src1",
1705 "$src1, ${src2}"##_.BroadcastStr,
1706 (X86cmpm (_.VT _.RC:$src1),
1707 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1710 // Accept explicit immediate argument form instead of comparison code.
1711 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1712 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1714 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1716 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1718 let mayLoad = 1 in {
1719 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1721 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1723 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1725 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1727 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1729 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1730 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1735 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1736 // comparison code form (VCMP[EQ/LT/LE/...]
1737 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1738 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1739 "vcmp${cc}"#_.Suffix,
1740 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1741 (X86cmpmRnd (_.VT _.RC:$src1),
1744 (i32 FROUND_NO_EXC))>, EVEX_B;
1746 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1747 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1749 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1751 "$cc,{sae}, $src2, $src1",
1752 "$src1, $src2,{sae}, $cc">, EVEX_B;
1756 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1757 let Predicates = [HasAVX512] in {
1758 defm Z : avx512_vcmp_common<_.info512>,
1759 avx512_vcmp_sae<_.info512>, EVEX_V512;
1762 let Predicates = [HasAVX512,HasVLX] in {
1763 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1764 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1768 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1769 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1770 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1771 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1773 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1774 (COPY_TO_REGCLASS (VCMPPSZrri
1775 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1776 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1778 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1779 (COPY_TO_REGCLASS (VPCMPDZrri
1780 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1781 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1783 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1784 (COPY_TO_REGCLASS (VPCMPUDZrri
1785 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1786 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1789 // ----------------------------------------------------------------
1791 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1792 // fpclass(reg_vec, mem_vec, imm)
1793 // fpclass(reg_vec, broadcast(eltVt), imm)
1794 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1795 X86VectorVTInfo _, string mem, string broadcast>{
1796 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1797 (ins _.RC:$src1, i32u8imm:$src2),
1798 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1799 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1800 (i32 imm:$src2)))], NoItinerary>;
1801 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1802 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1803 OpcodeStr##_.Suffix#
1804 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1805 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1806 (OpNode (_.VT _.RC:$src1),
1807 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1808 let mayLoad = 1 in {
1809 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1810 (ins _.MemOp:$src1, i32u8imm:$src2),
1811 OpcodeStr##_.Suffix##mem#
1812 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1813 [(set _.KRC:$dst,(OpNode
1814 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1815 (i32 imm:$src2)))], NoItinerary>;
1816 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1817 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1818 OpcodeStr##_.Suffix##mem#
1819 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1820 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1821 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1822 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1823 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1824 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1825 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1826 _.BroadcastStr##", $dst | $dst, ${src1}"
1827 ##_.BroadcastStr##", $src2}",
1828 [(set _.KRC:$dst,(OpNode
1829 (_.VT (X86VBroadcast
1830 (_.ScalarLdFrag addr:$src1))),
1831 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1832 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1833 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1834 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1835 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1836 _.BroadcastStr##", $src2}",
1837 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1838 (_.VT (X86VBroadcast
1839 (_.ScalarLdFrag addr:$src1))),
1840 (i32 imm:$src2))))], NoItinerary>,
1845 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1846 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1848 let Predicates = [prd] in {
1849 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1850 broadcast>, EVEX_V512;
1852 let Predicates = [prd, HasVLX] in {
1853 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1854 broadcast>, EVEX_V128;
1855 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1856 broadcast>, EVEX_V256;
1860 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1861 SDNode OpNode, Predicate prd>{
1862 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1863 OpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1864 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1865 OpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1868 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, X86Vfpclass, HasDQI>,
1869 AVX512AIi8Base,EVEX;
1871 //-----------------------------------------------------------------
1872 // Mask register copy, including
1873 // - copy between mask registers
1874 // - load/store mask registers
1875 // - copy from GPR to mask register and vice versa
1877 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1878 string OpcodeStr, RegisterClass KRC,
1879 ValueType vvt, X86MemOperand x86memop> {
1880 let hasSideEffects = 0 in {
1881 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1882 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1884 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1885 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1886 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1888 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1889 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1890 [(store KRC:$src, addr:$dst)]>;
1894 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1896 RegisterClass KRC, RegisterClass GRC> {
1897 let hasSideEffects = 0 in {
1898 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1899 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1900 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1901 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1905 let Predicates = [HasDQI] in
1906 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1907 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1910 let Predicates = [HasAVX512] in
1911 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1912 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1915 let Predicates = [HasBWI] in {
1916 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1918 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1922 let Predicates = [HasBWI] in {
1923 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1925 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1929 // GR from/to mask register
1930 let Predicates = [HasDQI] in {
1931 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1932 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1933 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1934 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1936 let Predicates = [HasAVX512] in {
1937 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1938 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1939 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1940 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1942 let Predicates = [HasBWI] in {
1943 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1944 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1946 let Predicates = [HasBWI] in {
1947 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1948 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1952 let Predicates = [HasDQI] in {
1953 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1954 (KMOVBmk addr:$dst, VK8:$src)>;
1955 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1956 (KMOVBkm addr:$src)>;
1958 def : Pat<(store VK4:$src, addr:$dst),
1959 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
1960 def : Pat<(store VK2:$src, addr:$dst),
1961 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
1963 let Predicates = [HasAVX512, NoDQI] in {
1964 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1965 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1966 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1967 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1969 let Predicates = [HasAVX512] in {
1970 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1971 (KMOVWmk addr:$dst, VK16:$src)>;
1972 def : Pat<(i1 (load addr:$src)),
1973 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
1974 (MOV8rm addr:$src), sub_8bit)),
1976 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1977 (KMOVWkm addr:$src)>;
1979 let Predicates = [HasBWI] in {
1980 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1981 (KMOVDmk addr:$dst, VK32:$src)>;
1982 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1983 (KMOVDkm addr:$src)>;
1985 let Predicates = [HasBWI] in {
1986 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1987 (KMOVQmk addr:$dst, VK64:$src)>;
1988 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1989 (KMOVQkm addr:$src)>;
1992 let Predicates = [HasAVX512] in {
1993 def : Pat<(i1 (trunc (i64 GR64:$src))),
1994 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1997 def : Pat<(i1 (trunc (i32 GR32:$src))),
1998 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2000 def : Pat<(i1 (trunc (i8 GR8:$src))),
2002 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2004 def : Pat<(i1 (trunc (i16 GR16:$src))),
2006 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2009 def : Pat<(i32 (zext VK1:$src)),
2010 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2011 def : Pat<(i32 (anyext VK1:$src)),
2012 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2014 def : Pat<(i8 (zext VK1:$src)),
2017 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2018 def : Pat<(i8 (anyext VK1:$src)),
2020 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2022 def : Pat<(i64 (zext VK1:$src)),
2023 (AND64ri8 (SUBREG_TO_REG (i64 0),
2024 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2025 def : Pat<(i16 (zext VK1:$src)),
2027 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2029 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2030 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2031 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2032 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2034 let Predicates = [HasBWI] in {
2035 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2036 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2037 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2038 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2042 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2043 let Predicates = [HasAVX512, NoDQI] in {
2044 // GR from/to 8-bit mask without native support
2045 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2047 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2048 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2050 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2054 let Predicates = [HasAVX512] in {
2055 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2056 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2057 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2058 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2060 let Predicates = [HasBWI] in {
2061 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2062 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2063 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2064 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2067 // Mask unary operation
2069 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2070 RegisterClass KRC, SDPatternOperator OpNode,
2072 let Predicates = [prd] in
2073 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2074 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2075 [(set KRC:$dst, (OpNode KRC:$src))]>;
2078 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2079 SDPatternOperator OpNode> {
2080 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2082 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2083 HasAVX512>, VEX, PS;
2084 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2085 HasBWI>, VEX, PD, VEX_W;
2086 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2087 HasBWI>, VEX, PS, VEX_W;
2090 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2092 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2093 let Predicates = [HasAVX512] in
2094 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2096 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2097 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2099 defm : avx512_mask_unop_int<"knot", "KNOT">;
2101 let Predicates = [HasDQI] in
2102 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2103 let Predicates = [HasAVX512] in
2104 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2105 let Predicates = [HasBWI] in
2106 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2107 let Predicates = [HasBWI] in
2108 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2110 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2111 let Predicates = [HasAVX512, NoDQI] in {
2112 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2113 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2114 def : Pat<(not VK8:$src),
2116 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2118 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2119 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2120 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2121 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2123 // Mask binary operation
2124 // - KAND, KANDN, KOR, KXNOR, KXOR
2125 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2126 RegisterClass KRC, SDPatternOperator OpNode,
2127 Predicate prd, bit IsCommutable> {
2128 let Predicates = [prd], isCommutable = IsCommutable in
2129 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2130 !strconcat(OpcodeStr,
2131 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2132 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2135 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2136 SDPatternOperator OpNode, bit IsCommutable,
2137 Predicate prdW = HasAVX512> {
2138 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2139 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2140 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2141 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2142 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2143 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2144 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2145 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2148 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2149 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2151 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2152 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2153 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2154 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2155 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2156 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2158 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2159 let Predicates = [HasAVX512] in
2160 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2161 (i16 GR16:$src1), (i16 GR16:$src2)),
2162 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2163 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2164 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2167 defm : avx512_mask_binop_int<"kand", "KAND">;
2168 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2169 defm : avx512_mask_binop_int<"kor", "KOR">;
2170 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2171 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2173 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2174 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2175 // for the DQI set, this type is legal and KxxxB instruction is used
2176 let Predicates = [NoDQI] in
2177 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2179 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2180 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2182 // All types smaller than 8 bits require conversion anyway
2183 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2184 (COPY_TO_REGCLASS (Inst
2185 (COPY_TO_REGCLASS VK1:$src1, VK16),
2186 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2187 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2188 (COPY_TO_REGCLASS (Inst
2189 (COPY_TO_REGCLASS VK2:$src1, VK16),
2190 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2191 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2192 (COPY_TO_REGCLASS (Inst
2193 (COPY_TO_REGCLASS VK4:$src1, VK16),
2194 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2197 defm : avx512_binop_pat<and, KANDWrr>;
2198 defm : avx512_binop_pat<andn, KANDNWrr>;
2199 defm : avx512_binop_pat<or, KORWrr>;
2200 defm : avx512_binop_pat<xnor, KXNORWrr>;
2201 defm : avx512_binop_pat<xor, KXORWrr>;
2203 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2204 (KXNORWrr VK16:$src1, VK16:$src2)>;
2205 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2206 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2207 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2208 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2209 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2210 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2212 let Predicates = [NoDQI] in
2213 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2214 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2215 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2217 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2218 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2219 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2221 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2222 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2223 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2225 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2226 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2227 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2230 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2231 RegisterClass KRCSrc, Predicate prd> {
2232 let Predicates = [prd] in {
2233 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2234 (ins KRC:$src1, KRC:$src2),
2235 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2238 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2239 (!cast<Instruction>(NAME##rr)
2240 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2241 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2245 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2246 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2247 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2249 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2250 let Predicates = [HasAVX512] in
2251 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2252 (i16 GR16:$src1), (i16 GR16:$src2)),
2253 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2254 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2255 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2257 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2260 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2261 SDNode OpNode, Predicate prd> {
2262 let Predicates = [prd], Defs = [EFLAGS] in
2263 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2264 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2265 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2268 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2269 Predicate prdW = HasAVX512> {
2270 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2272 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2274 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2276 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2280 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2281 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2284 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2286 let Predicates = [HasAVX512] in
2287 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2288 !strconcat(OpcodeStr,
2289 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2290 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2293 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2295 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2297 let Predicates = [HasDQI] in
2298 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2300 let Predicates = [HasBWI] in {
2301 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2303 let Predicates = [HasDQI] in
2304 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2309 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2310 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2312 // Mask setting all 0s or 1s
2313 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2314 let Predicates = [HasAVX512] in
2315 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2316 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2317 [(set KRC:$dst, (VT Val))]>;
2320 multiclass avx512_mask_setop_w<PatFrag Val> {
2321 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2322 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2323 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2324 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2327 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2328 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2330 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2331 let Predicates = [HasAVX512] in {
2332 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2333 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2334 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2335 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2336 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2337 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2338 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2340 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2341 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2343 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2344 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2346 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2347 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2349 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2350 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2352 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2353 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2355 let Predicates = [HasVLX] in {
2356 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2357 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2358 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2359 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2360 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2361 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2362 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2363 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2364 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2365 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2368 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2369 (v8i1 (COPY_TO_REGCLASS
2370 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2371 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2373 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2374 (v8i1 (COPY_TO_REGCLASS
2375 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2376 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2378 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2379 (v4i1 (COPY_TO_REGCLASS
2380 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2381 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2383 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2384 (v4i1 (COPY_TO_REGCLASS
2385 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2386 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2388 //===----------------------------------------------------------------------===//
2389 // AVX-512 - Aligned and unaligned load and store
2393 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2394 PatFrag ld_frag, PatFrag mload,
2395 bit IsReMaterializable = 1> {
2396 let hasSideEffects = 0 in {
2397 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2398 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2400 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2401 (ins _.KRCWM:$mask, _.RC:$src),
2402 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2403 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2406 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2407 SchedRW = [WriteLoad] in
2408 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2409 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2410 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2413 let Constraints = "$src0 = $dst" in {
2414 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2415 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2416 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2417 "${dst} {${mask}}, $src1}"),
2418 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2420 (_.VT _.RC:$src0))))], _.ExeDomain>,
2422 let mayLoad = 1, SchedRW = [WriteLoad] in
2423 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2424 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2425 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2426 "${dst} {${mask}}, $src1}"),
2427 [(set _.RC:$dst, (_.VT
2428 (vselect _.KRCWM:$mask,
2429 (_.VT (bitconvert (ld_frag addr:$src1))),
2430 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2432 let mayLoad = 1, SchedRW = [WriteLoad] in
2433 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2434 (ins _.KRCWM:$mask, _.MemOp:$src),
2435 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2436 "${dst} {${mask}} {z}, $src}",
2437 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2438 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2439 _.ExeDomain>, EVEX, EVEX_KZ;
2441 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2442 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2444 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2445 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2447 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2448 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2449 _.KRCWM:$mask, addr:$ptr)>;
2452 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2453 AVX512VLVectorVTInfo _,
2455 bit IsReMaterializable = 1> {
2456 let Predicates = [prd] in
2457 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2458 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2460 let Predicates = [prd, HasVLX] in {
2461 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2462 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2463 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2464 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2468 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2469 AVX512VLVectorVTInfo _,
2471 bit IsReMaterializable = 1> {
2472 let Predicates = [prd] in
2473 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2474 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2476 let Predicates = [prd, HasVLX] in {
2477 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2478 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2479 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2480 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2484 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2485 PatFrag st_frag, PatFrag mstore> {
2486 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2487 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2488 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2490 let Constraints = "$src1 = $dst" in
2491 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2492 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2494 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2495 [], _.ExeDomain>, EVEX, EVEX_K;
2496 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2497 (ins _.KRCWM:$mask, _.RC:$src),
2499 "\t{$src, ${dst} {${mask}} {z}|" #
2500 "${dst} {${mask}} {z}, $src}",
2501 [], _.ExeDomain>, EVEX, EVEX_KZ;
2503 let mayStore = 1 in {
2504 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2505 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2506 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2507 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2508 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2509 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2510 [], _.ExeDomain>, EVEX, EVEX_K;
2513 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2514 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2515 _.KRCWM:$mask, _.RC:$src)>;
2519 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2520 AVX512VLVectorVTInfo _, Predicate prd> {
2521 let Predicates = [prd] in
2522 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2523 masked_store_unaligned>, EVEX_V512;
2525 let Predicates = [prd, HasVLX] in {
2526 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2527 masked_store_unaligned>, EVEX_V256;
2528 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2529 masked_store_unaligned>, EVEX_V128;
2533 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2534 AVX512VLVectorVTInfo _, Predicate prd> {
2535 let Predicates = [prd] in
2536 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2537 masked_store_aligned512>, EVEX_V512;
2539 let Predicates = [prd, HasVLX] in {
2540 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2541 masked_store_aligned256>, EVEX_V256;
2542 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2543 masked_store_aligned128>, EVEX_V128;
2547 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2549 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2550 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2552 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2554 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2555 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2557 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2558 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2559 PS, EVEX_CD8<32, CD8VF>;
2561 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2562 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2563 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2565 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2566 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2567 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2569 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2570 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2571 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2573 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2574 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2575 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2577 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2578 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2579 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2581 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2582 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2583 (VMOVAPDZrm addr:$ptr)>;
2585 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2586 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2587 (VMOVAPSZrm addr:$ptr)>;
2589 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2591 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2593 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2595 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2598 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2600 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2602 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2604 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2607 let Predicates = [HasAVX512, NoVLX] in {
2608 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2609 (VMOVUPSZmrk addr:$ptr,
2610 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2611 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2613 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2614 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2615 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2617 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2618 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2619 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2620 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2623 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2625 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2626 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2628 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2630 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2631 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2633 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2634 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2635 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2637 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2638 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2639 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2641 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2642 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2643 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2645 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2646 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2647 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2649 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2650 (v16i32 immAllZerosV), GR16:$mask)),
2651 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2653 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2654 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2655 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2657 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2659 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2661 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2663 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2666 let AddedComplexity = 20 in {
2667 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2668 (bc_v8i64 (v16i32 immAllZerosV)))),
2669 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2671 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2672 (v8i64 VR512:$src))),
2673 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2676 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2677 (v16i32 immAllZerosV))),
2678 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2680 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2681 (v16i32 VR512:$src))),
2682 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2685 let Predicates = [HasAVX512, NoVLX] in {
2686 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2687 (VMOVDQU32Zmrk addr:$ptr,
2688 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2689 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2691 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2692 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2693 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2696 // Move Int Doubleword to Packed Double Int
2698 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2699 "vmovd\t{$src, $dst|$dst, $src}",
2701 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2703 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2704 "vmovd\t{$src, $dst|$dst, $src}",
2706 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2707 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2708 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2709 "vmovq\t{$src, $dst|$dst, $src}",
2711 (v2i64 (scalar_to_vector GR64:$src)))],
2712 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2713 let isCodeGenOnly = 1 in {
2714 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2715 "vmovq\t{$src, $dst|$dst, $src}",
2716 [(set FR64:$dst, (bitconvert GR64:$src))],
2717 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2718 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2719 "vmovq\t{$src, $dst|$dst, $src}",
2720 [(set GR64:$dst, (bitconvert FR64:$src))],
2721 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2723 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2724 "vmovq\t{$src, $dst|$dst, $src}",
2725 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2726 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2727 EVEX_CD8<64, CD8VT1>;
2729 // Move Int Doubleword to Single Scalar
2731 let isCodeGenOnly = 1 in {
2732 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2733 "vmovd\t{$src, $dst|$dst, $src}",
2734 [(set FR32X:$dst, (bitconvert GR32:$src))],
2735 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2737 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2738 "vmovd\t{$src, $dst|$dst, $src}",
2739 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2740 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2743 // Move doubleword from xmm register to r/m32
2745 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2746 "vmovd\t{$src, $dst|$dst, $src}",
2747 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2748 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2750 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2751 (ins i32mem:$dst, VR128X:$src),
2752 "vmovd\t{$src, $dst|$dst, $src}",
2753 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2754 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2755 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2757 // Move quadword from xmm1 register to r/m64
2759 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2760 "vmovq\t{$src, $dst|$dst, $src}",
2761 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2763 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2764 Requires<[HasAVX512, In64BitMode]>;
2766 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2767 (ins i64mem:$dst, VR128X:$src),
2768 "vmovq\t{$src, $dst|$dst, $src}",
2769 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2770 addr:$dst)], IIC_SSE_MOVDQ>,
2771 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2772 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2774 // Move Scalar Single to Double Int
2776 let isCodeGenOnly = 1 in {
2777 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2779 "vmovd\t{$src, $dst|$dst, $src}",
2780 [(set GR32:$dst, (bitconvert FR32X:$src))],
2781 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2782 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2783 (ins i32mem:$dst, FR32X:$src),
2784 "vmovd\t{$src, $dst|$dst, $src}",
2785 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2786 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2789 // Move Quadword Int to Packed Quadword Int
2791 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2793 "vmovq\t{$src, $dst|$dst, $src}",
2795 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2796 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2798 //===----------------------------------------------------------------------===//
2799 // AVX-512 MOVSS, MOVSD
2800 //===----------------------------------------------------------------------===//
2802 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2803 SDNode OpNode, ValueType vt,
2804 X86MemOperand x86memop, PatFrag mem_pat> {
2805 let hasSideEffects = 0 in {
2806 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2807 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2808 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2809 (scalar_to_vector RC:$src2))))],
2810 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2811 let Constraints = "$src1 = $dst" in
2812 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2813 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2815 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2816 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2817 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2818 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2819 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2821 let mayStore = 1 in {
2822 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2823 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2824 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2826 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2827 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2828 [], IIC_SSE_MOV_S_MR>,
2829 EVEX, VEX_LIG, EVEX_K;
2831 } //hasSideEffects = 0
2834 let ExeDomain = SSEPackedSingle in
2835 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2836 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2838 let ExeDomain = SSEPackedDouble in
2839 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2840 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2842 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2843 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2844 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2846 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2847 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2848 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2850 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2851 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2852 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2854 // For the disassembler
2855 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2856 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2857 (ins VR128X:$src1, FR32X:$src2),
2858 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2860 XS, EVEX_4V, VEX_LIG;
2861 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2862 (ins VR128X:$src1, FR64X:$src2),
2863 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2865 XD, EVEX_4V, VEX_LIG, VEX_W;
2868 let Predicates = [HasAVX512] in {
2869 let AddedComplexity = 15 in {
2870 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2871 // MOVS{S,D} to the lower bits.
2872 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2873 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2874 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2875 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2876 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2877 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2878 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2879 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2881 // Move low f32 and clear high bits.
2882 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2883 (SUBREG_TO_REG (i32 0),
2884 (VMOVSSZrr (v4f32 (V_SET0)),
2885 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2886 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2887 (SUBREG_TO_REG (i32 0),
2888 (VMOVSSZrr (v4i32 (V_SET0)),
2889 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2892 let AddedComplexity = 20 in {
2893 // MOVSSrm zeros the high parts of the register; represent this
2894 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2895 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2896 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2897 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2898 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2899 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2900 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2902 // MOVSDrm zeros the high parts of the register; represent this
2903 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2904 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2905 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2906 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2907 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2908 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2909 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2910 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2911 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2912 def : Pat<(v2f64 (X86vzload addr:$src)),
2913 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2915 // Represent the same patterns above but in the form they appear for
2917 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2918 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2919 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2920 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2921 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2922 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2923 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2924 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2925 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2927 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2928 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2929 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2930 FR32X:$src)), sub_xmm)>;
2931 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2932 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2933 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2934 FR64X:$src)), sub_xmm)>;
2935 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2936 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2937 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2939 // Move low f64 and clear high bits.
2940 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2941 (SUBREG_TO_REG (i32 0),
2942 (VMOVSDZrr (v2f64 (V_SET0)),
2943 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2945 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2946 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2947 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2949 // Extract and store.
2950 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2952 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2953 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2955 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2957 // Shuffle with VMOVSS
2958 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2959 (VMOVSSZrr (v4i32 VR128X:$src1),
2960 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2961 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2962 (VMOVSSZrr (v4f32 VR128X:$src1),
2963 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2966 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2967 (SUBREG_TO_REG (i32 0),
2968 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2969 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2971 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2972 (SUBREG_TO_REG (i32 0),
2973 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2974 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2977 // Shuffle with VMOVSD
2978 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2979 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2980 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2981 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2982 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2983 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2984 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2985 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2988 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2989 (SUBREG_TO_REG (i32 0),
2990 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2991 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2993 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2994 (SUBREG_TO_REG (i32 0),
2995 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2996 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2999 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3000 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3001 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3002 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3003 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3004 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3005 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3006 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3009 let AddedComplexity = 15 in
3010 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3012 "vmovq\t{$src, $dst|$dst, $src}",
3013 [(set VR128X:$dst, (v2i64 (X86vzmovl
3014 (v2i64 VR128X:$src))))],
3015 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3017 let AddedComplexity = 20 in
3018 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3020 "vmovq\t{$src, $dst|$dst, $src}",
3021 [(set VR128X:$dst, (v2i64 (X86vzmovl
3022 (loadv2i64 addr:$src))))],
3023 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3024 EVEX_CD8<8, CD8VT8>;
3026 let Predicates = [HasAVX512] in {
3027 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3028 let AddedComplexity = 20 in {
3029 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3030 (VMOVDI2PDIZrm addr:$src)>;
3031 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3032 (VMOV64toPQIZrr GR64:$src)>;
3033 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3034 (VMOVDI2PDIZrr GR32:$src)>;
3036 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3037 (VMOVDI2PDIZrm addr:$src)>;
3038 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3039 (VMOVDI2PDIZrm addr:$src)>;
3040 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3041 (VMOVZPQILo2PQIZrm addr:$src)>;
3042 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3043 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3044 def : Pat<(v2i64 (X86vzload addr:$src)),
3045 (VMOVZPQILo2PQIZrm addr:$src)>;
3048 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3049 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3050 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3051 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3052 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3053 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3054 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3057 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3058 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3060 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3061 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3063 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3064 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3066 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3067 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3069 //===----------------------------------------------------------------------===//
3070 // AVX-512 - Non-temporals
3071 //===----------------------------------------------------------------------===//
3072 let SchedRW = [WriteLoad] in {
3073 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3074 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3075 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3076 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3077 EVEX_CD8<64, CD8VF>;
3079 let Predicates = [HasAVX512, HasVLX] in {
3080 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3082 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3083 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3084 EVEX_CD8<64, CD8VF>;
3086 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3088 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3089 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3090 EVEX_CD8<64, CD8VF>;
3094 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3095 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3096 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3097 let SchedRW = [WriteStore], mayStore = 1,
3098 AddedComplexity = 400 in
3099 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3100 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3101 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3104 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3105 string elty, string elsz, string vsz512,
3106 string vsz256, string vsz128, Domain d,
3107 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3108 let Predicates = [prd] in
3109 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3110 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3111 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3114 let Predicates = [prd, HasVLX] in {
3115 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3116 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3117 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3120 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3121 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3122 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3127 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3128 "i", "64", "8", "4", "2", SSEPackedInt,
3129 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3131 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3132 "f", "64", "8", "4", "2", SSEPackedDouble,
3133 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3135 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3136 "f", "32", "16", "8", "4", SSEPackedSingle,
3137 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3139 //===----------------------------------------------------------------------===//
3140 // AVX-512 - Integer arithmetic
3142 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3143 X86VectorVTInfo _, OpndItins itins,
3144 bit IsCommutable = 0> {
3145 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3146 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3147 "$src2, $src1", "$src1, $src2",
3148 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3149 itins.rr, IsCommutable>,
3150 AVX512BIBase, EVEX_4V;
3153 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3154 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3155 "$src2, $src1", "$src1, $src2",
3156 (_.VT (OpNode _.RC:$src1,
3157 (bitconvert (_.LdFrag addr:$src2)))),
3159 AVX512BIBase, EVEX_4V;
3162 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3163 X86VectorVTInfo _, OpndItins itins,
3164 bit IsCommutable = 0> :
3165 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3167 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3168 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3169 "${src2}"##_.BroadcastStr##", $src1",
3170 "$src1, ${src2}"##_.BroadcastStr,
3171 (_.VT (OpNode _.RC:$src1,
3173 (_.ScalarLdFrag addr:$src2)))),
3175 AVX512BIBase, EVEX_4V, EVEX_B;
3178 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3179 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3180 Predicate prd, bit IsCommutable = 0> {
3181 let Predicates = [prd] in
3182 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3183 IsCommutable>, EVEX_V512;
3185 let Predicates = [prd, HasVLX] in {
3186 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3187 IsCommutable>, EVEX_V256;
3188 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3189 IsCommutable>, EVEX_V128;
3193 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3194 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3195 Predicate prd, bit IsCommutable = 0> {
3196 let Predicates = [prd] in
3197 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3198 IsCommutable>, EVEX_V512;
3200 let Predicates = [prd, HasVLX] in {
3201 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3202 IsCommutable>, EVEX_V256;
3203 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3204 IsCommutable>, EVEX_V128;
3208 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3209 OpndItins itins, Predicate prd,
3210 bit IsCommutable = 0> {
3211 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3212 itins, prd, IsCommutable>,
3213 VEX_W, EVEX_CD8<64, CD8VF>;
3216 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3217 OpndItins itins, Predicate prd,
3218 bit IsCommutable = 0> {
3219 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3220 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3223 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3224 OpndItins itins, Predicate prd,
3225 bit IsCommutable = 0> {
3226 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3227 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3230 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3231 OpndItins itins, Predicate prd,
3232 bit IsCommutable = 0> {
3233 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3234 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3237 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3238 SDNode OpNode, OpndItins itins, Predicate prd,
3239 bit IsCommutable = 0> {
3240 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3243 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3247 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3248 SDNode OpNode, OpndItins itins, Predicate prd,
3249 bit IsCommutable = 0> {
3250 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3253 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3257 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3258 bits<8> opc_d, bits<8> opc_q,
3259 string OpcodeStr, SDNode OpNode,
3260 OpndItins itins, bit IsCommutable = 0> {
3261 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3262 itins, HasAVX512, IsCommutable>,
3263 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3264 itins, HasBWI, IsCommutable>;
3267 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3268 SDNode OpNode,X86VectorVTInfo _Src,
3269 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3270 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3271 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3272 "$src2, $src1","$src1, $src2",
3274 (_Src.VT _Src.RC:$src1),
3275 (_Src.VT _Src.RC:$src2))),
3276 itins.rr, IsCommutable>,
3277 AVX512BIBase, EVEX_4V;
3278 let mayLoad = 1 in {
3279 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3280 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3281 "$src2, $src1", "$src1, $src2",
3282 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3283 (bitconvert (_Src.LdFrag addr:$src2)))),
3285 AVX512BIBase, EVEX_4V;
3287 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3288 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3290 "${src2}"##_Dst.BroadcastStr##", $src1",
3291 "$src1, ${src2}"##_Dst.BroadcastStr,
3292 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3293 (_Dst.VT (X86VBroadcast
3294 (_Dst.ScalarLdFrag addr:$src2)))))),
3296 AVX512BIBase, EVEX_4V, EVEX_B;
3300 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3301 SSE_INTALU_ITINS_P, 1>;
3302 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3303 SSE_INTALU_ITINS_P, 0>;
3304 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3305 SSE_INTALU_ITINS_P, HasBWI, 1>;
3306 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3307 SSE_INTALU_ITINS_P, HasBWI, 0>;
3308 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3309 SSE_INTALU_ITINS_P, HasBWI, 1>;
3310 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3311 SSE_INTALU_ITINS_P, HasBWI, 0>;
3312 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3313 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3314 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3315 SSE_INTALU_ITINS_P, HasBWI, 1>;
3316 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3317 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3318 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3320 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3322 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3324 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3325 SSE_INTALU_ITINS_P, HasBWI, 1>;
3327 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3328 SDNode OpNode, bit IsCommutable = 0> {
3330 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3331 v16i32_info, v8i64_info, IsCommutable>,
3332 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3333 let Predicates = [HasVLX] in {
3334 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3335 v8i32x_info, v4i64x_info, IsCommutable>,
3336 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3337 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3338 v4i32x_info, v2i64x_info, IsCommutable>,
3339 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3343 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3345 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3348 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3349 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3350 let mayLoad = 1 in {
3351 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3352 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3354 "${src2}"##_Src.BroadcastStr##", $src1",
3355 "$src1, ${src2}"##_Src.BroadcastStr,
3356 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3357 (_Src.VT (X86VBroadcast
3358 (_Src.ScalarLdFrag addr:$src2))))))>,
3359 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3363 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3364 SDNode OpNode,X86VectorVTInfo _Src,
3365 X86VectorVTInfo _Dst> {
3366 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3367 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3368 "$src2, $src1","$src1, $src2",
3370 (_Src.VT _Src.RC:$src1),
3371 (_Src.VT _Src.RC:$src2)))>,
3372 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3373 let mayLoad = 1 in {
3374 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3375 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3376 "$src2, $src1", "$src1, $src2",
3377 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3378 (bitconvert (_Src.LdFrag addr:$src2))))>,
3379 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3383 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3385 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3387 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3388 v32i16_info>, EVEX_V512;
3389 let Predicates = [HasVLX] in {
3390 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3392 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3393 v16i16x_info>, EVEX_V256;
3394 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3396 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3397 v8i16x_info>, EVEX_V128;
3400 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3402 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3403 v64i8_info>, EVEX_V512;
3404 let Predicates = [HasVLX] in {
3405 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3406 v32i8x_info>, EVEX_V256;
3407 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3408 v16i8x_info>, EVEX_V128;
3412 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3413 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3414 AVX512VLVectorVTInfo _Dst> {
3415 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3416 _Dst.info512>, EVEX_V512;
3417 let Predicates = [HasVLX] in {
3418 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3419 _Dst.info256>, EVEX_V256;
3420 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3421 _Dst.info128>, EVEX_V128;
3425 let Predicates = [HasBWI] in {
3426 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3427 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3428 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3429 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3431 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3432 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3433 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3434 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3437 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3438 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3439 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3440 SSE_INTALU_ITINS_P, HasBWI, 1>;
3441 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3442 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3444 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3445 SSE_INTALU_ITINS_P, HasBWI, 1>;
3446 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3447 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3448 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3449 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3451 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3452 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3453 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3454 SSE_INTALU_ITINS_P, HasBWI, 1>;
3455 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3456 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3458 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3459 SSE_INTALU_ITINS_P, HasBWI, 1>;
3460 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3461 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3462 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3463 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3464 //===----------------------------------------------------------------------===//
3465 // AVX-512 Logical Instructions
3466 //===----------------------------------------------------------------------===//
3468 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3469 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3470 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3471 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3472 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3473 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3474 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3475 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3477 //===----------------------------------------------------------------------===//
3478 // AVX-512 FP arithmetic
3479 //===----------------------------------------------------------------------===//
3480 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3481 SDNode OpNode, SDNode VecNode, OpndItins itins,
3484 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3485 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3486 "$src2, $src1", "$src1, $src2",
3487 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3488 (i32 FROUND_CURRENT)),
3489 itins.rr, IsCommutable>;
3491 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3492 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3493 "$src2, $src1", "$src1, $src2",
3494 (VecNode (_.VT _.RC:$src1),
3495 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3496 (i32 FROUND_CURRENT)),
3497 itins.rm, IsCommutable>;
3498 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3499 Predicates = [HasAVX512] in {
3500 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3501 (ins _.FRC:$src1, _.FRC:$src2),
3502 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3503 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3505 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3506 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3507 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3508 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3509 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3513 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3514 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3516 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3517 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3518 "$rc, $src2, $src1", "$src1, $src2, $rc",
3519 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3520 (i32 imm:$rc)), itins.rr, IsCommutable>,
3523 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3524 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3526 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3527 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3528 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3529 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3530 (i32 FROUND_NO_EXC))>, EVEX_B;
3533 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3535 SizeItins itins, bit IsCommutable> {
3536 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3537 itins.s, IsCommutable>,
3538 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3539 itins.s, IsCommutable>,
3540 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3541 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3542 itins.d, IsCommutable>,
3543 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3544 itins.d, IsCommutable>,
3545 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3548 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3550 SizeItins itins, bit IsCommutable> {
3551 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3552 itins.s, IsCommutable>,
3553 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3554 itins.s, IsCommutable>,
3555 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3556 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3557 itins.d, IsCommutable>,
3558 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3559 itins.d, IsCommutable>,
3560 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3562 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3563 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3564 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3565 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3566 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3567 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3569 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3570 X86VectorVTInfo _, bit IsCommutable> {
3571 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3572 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3573 "$src2, $src1", "$src1, $src2",
3574 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3575 let mayLoad = 1 in {
3576 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3577 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3578 "$src2, $src1", "$src1, $src2",
3579 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3580 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3581 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3582 "${src2}"##_.BroadcastStr##", $src1",
3583 "$src1, ${src2}"##_.BroadcastStr,
3584 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3585 (_.ScalarLdFrag addr:$src2))))>,
3590 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3591 X86VectorVTInfo _> {
3592 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3593 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3594 "$rc, $src2, $src1", "$src1, $src2, $rc",
3595 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3596 EVEX_4V, EVEX_B, EVEX_RC;
3600 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3601 X86VectorVTInfo _> {
3602 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3603 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3604 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3605 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3609 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3610 bit IsCommutable = 0> {
3611 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3612 IsCommutable>, EVEX_V512, PS,
3613 EVEX_CD8<32, CD8VF>;
3614 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3615 IsCommutable>, EVEX_V512, PD, VEX_W,
3616 EVEX_CD8<64, CD8VF>;
3618 // Define only if AVX512VL feature is present.
3619 let Predicates = [HasVLX] in {
3620 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3621 IsCommutable>, EVEX_V128, PS,
3622 EVEX_CD8<32, CD8VF>;
3623 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3624 IsCommutable>, EVEX_V256, PS,
3625 EVEX_CD8<32, CD8VF>;
3626 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3627 IsCommutable>, EVEX_V128, PD, VEX_W,
3628 EVEX_CD8<64, CD8VF>;
3629 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3630 IsCommutable>, EVEX_V256, PD, VEX_W,
3631 EVEX_CD8<64, CD8VF>;
3635 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3636 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3637 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3638 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3639 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3642 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3643 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3644 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3645 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3646 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3649 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3650 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3651 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3652 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3653 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3654 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3655 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3656 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3657 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3658 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3659 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3660 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3661 let Predicates = [HasDQI] in {
3662 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3663 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3664 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3665 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3668 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3669 X86VectorVTInfo _> {
3670 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3671 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3672 "$src2, $src1", "$src1, $src2",
3673 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3674 let mayLoad = 1 in {
3675 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3676 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3677 "$src2, $src1", "$src1, $src2",
3678 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3679 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3680 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3681 "${src2}"##_.BroadcastStr##", $src1",
3682 "$src1, ${src2}"##_.BroadcastStr,
3683 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3684 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3689 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3690 X86VectorVTInfo _> {
3691 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3692 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3693 "$src2, $src1", "$src1, $src2",
3694 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3695 let mayLoad = 1 in {
3696 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3697 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3698 "$src2, $src1", "$src1, $src2",
3699 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3703 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3704 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3705 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3706 EVEX_V512, EVEX_CD8<32, CD8VF>;
3707 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3708 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3709 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3710 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3711 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3712 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3713 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3714 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3715 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3717 // Define only if AVX512VL feature is present.
3718 let Predicates = [HasVLX] in {
3719 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3720 EVEX_V128, EVEX_CD8<32, CD8VF>;
3721 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3722 EVEX_V256, EVEX_CD8<32, CD8VF>;
3723 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3724 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3725 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3726 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3729 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3731 //===----------------------------------------------------------------------===//
3732 // AVX-512 VPTESTM instructions
3733 //===----------------------------------------------------------------------===//
3735 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3736 X86VectorVTInfo _> {
3737 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3738 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3739 "$src2, $src1", "$src1, $src2",
3740 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3743 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3744 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3745 "$src2, $src1", "$src1, $src2",
3746 (OpNode (_.VT _.RC:$src1),
3747 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3749 EVEX_CD8<_.EltSize, CD8VF>;
3752 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3753 X86VectorVTInfo _> {
3755 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3756 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3757 "${src2}"##_.BroadcastStr##", $src1",
3758 "$src1, ${src2}"##_.BroadcastStr,
3759 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3760 (_.ScalarLdFrag addr:$src2))))>,
3761 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3763 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3764 AVX512VLVectorVTInfo _> {
3765 let Predicates = [HasAVX512] in
3766 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3767 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3769 let Predicates = [HasAVX512, HasVLX] in {
3770 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3771 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3772 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3773 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3777 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3778 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3780 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3781 avx512vl_i64_info>, VEX_W;
3784 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3786 let Predicates = [HasBWI] in {
3787 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3789 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3792 let Predicates = [HasVLX, HasBWI] in {
3794 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3796 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3798 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3800 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3805 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3807 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3808 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3810 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3811 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3813 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3814 (v16i32 VR512:$src2), (i16 -1))),
3815 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3817 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3818 (v8i64 VR512:$src2), (i8 -1))),
3819 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3821 //===----------------------------------------------------------------------===//
3822 // AVX-512 Shift instructions
3823 //===----------------------------------------------------------------------===//
3824 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3825 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3826 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3827 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3828 "$src2, $src1", "$src1, $src2",
3829 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3830 SSE_INTSHIFT_ITINS_P.rr>;
3832 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3833 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3834 "$src2, $src1", "$src1, $src2",
3835 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3837 SSE_INTSHIFT_ITINS_P.rm>;
3840 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3841 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3843 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3844 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3845 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3846 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3847 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3850 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3851 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3852 // src2 is always 128-bit
3853 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3854 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3855 "$src2, $src1", "$src1, $src2",
3856 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3857 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3858 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3859 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3860 "$src2, $src1", "$src1, $src2",
3861 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3862 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3866 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3867 ValueType SrcVT, PatFrag bc_frag,
3868 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3869 let Predicates = [prd] in
3870 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3871 VTInfo.info512>, EVEX_V512,
3872 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3873 let Predicates = [prd, HasVLX] in {
3874 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3875 VTInfo.info256>, EVEX_V256,
3876 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3877 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3878 VTInfo.info128>, EVEX_V128,
3879 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3883 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3884 string OpcodeStr, SDNode OpNode> {
3885 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3886 avx512vl_i32_info, HasAVX512>;
3887 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3888 avx512vl_i64_info, HasAVX512>, VEX_W;
3889 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3890 avx512vl_i16_info, HasBWI>;
3893 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3894 string OpcodeStr, SDNode OpNode,
3895 AVX512VLVectorVTInfo VTInfo> {
3896 let Predicates = [HasAVX512] in
3897 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3899 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3900 VTInfo.info512>, EVEX_V512;
3901 let Predicates = [HasAVX512, HasVLX] in {
3902 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3904 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3905 VTInfo.info256>, EVEX_V256;
3906 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3908 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3909 VTInfo.info128>, EVEX_V128;
3913 multiclass avx512_shift_rmi_w<bits<8> opcw,
3914 Format ImmFormR, Format ImmFormM,
3915 string OpcodeStr, SDNode OpNode> {
3916 let Predicates = [HasBWI] in
3917 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3918 v32i16_info>, EVEX_V512;
3919 let Predicates = [HasVLX, HasBWI] in {
3920 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3921 v16i16x_info>, EVEX_V256;
3922 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3923 v8i16x_info>, EVEX_V128;
3927 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3928 Format ImmFormR, Format ImmFormM,
3929 string OpcodeStr, SDNode OpNode> {
3930 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3931 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3932 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3933 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3936 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3937 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3939 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3940 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3942 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3943 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
3945 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
3946 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
3948 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3949 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3950 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3952 //===-------------------------------------------------------------------===//
3953 // Variable Bit Shifts
3954 //===-------------------------------------------------------------------===//
3955 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3956 X86VectorVTInfo _> {
3957 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3958 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3959 "$src2, $src1", "$src1, $src2",
3960 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3961 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3963 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3964 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3965 "$src2, $src1", "$src1, $src2",
3966 (_.VT (OpNode _.RC:$src1,
3967 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
3968 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3969 EVEX_CD8<_.EltSize, CD8VF>;
3972 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3973 X86VectorVTInfo _> {
3975 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3976 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3977 "${src2}"##_.BroadcastStr##", $src1",
3978 "$src1, ${src2}"##_.BroadcastStr,
3979 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3980 (_.ScalarLdFrag addr:$src2))))),
3981 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3982 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3984 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3985 AVX512VLVectorVTInfo _> {
3986 let Predicates = [HasAVX512] in
3987 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3988 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3990 let Predicates = [HasAVX512, HasVLX] in {
3991 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3992 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3993 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3994 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3998 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4000 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4002 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4003 avx512vl_i64_info>, VEX_W;
4006 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4008 let Predicates = [HasBWI] in
4009 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4011 let Predicates = [HasVLX, HasBWI] in {
4013 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4015 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4020 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4021 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4022 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4023 avx512_var_shift_w<0x11, "vpsravw", sra>;
4024 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4025 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4026 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4027 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4029 //===-------------------------------------------------------------------===//
4030 // 1-src variable permutation VPERMW/D/Q
4031 //===-------------------------------------------------------------------===//
4032 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4033 AVX512VLVectorVTInfo _> {
4034 let Predicates = [HasAVX512] in
4035 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4036 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4038 let Predicates = [HasAVX512, HasVLX] in
4039 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4040 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4043 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4044 string OpcodeStr, SDNode OpNode,
4045 AVX512VLVectorVTInfo VTInfo> {
4046 let Predicates = [HasAVX512] in
4047 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4049 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4050 VTInfo.info512>, EVEX_V512;
4051 let Predicates = [HasAVX512, HasVLX] in
4052 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4054 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4055 VTInfo.info256>, EVEX_V256;
4059 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4061 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4063 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4064 avx512vl_i64_info>, VEX_W;
4065 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4067 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4068 avx512vl_f64_info>, VEX_W;
4070 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4071 X86VPermi, avx512vl_i64_info>,
4072 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4073 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4074 X86VPermi, avx512vl_f64_info>,
4075 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4076 //===----------------------------------------------------------------------===//
4077 // AVX-512 - VPERMIL
4078 //===----------------------------------------------------------------------===//
4080 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4081 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4082 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4083 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4084 "$src2, $src1", "$src1, $src2",
4085 (_.VT (OpNode _.RC:$src1,
4086 (Ctrl.VT Ctrl.RC:$src2)))>,
4088 let mayLoad = 1 in {
4089 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4090 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4091 "$src2, $src1", "$src1, $src2",
4094 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4095 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4096 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4097 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4098 "${src2}"##_.BroadcastStr##", $src1",
4099 "$src1, ${src2}"##_.BroadcastStr,
4102 (Ctrl.VT (X86VBroadcast
4103 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4104 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4108 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4109 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4110 let Predicates = [HasAVX512] in {
4111 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4112 Ctrl.info512>, EVEX_V512;
4114 let Predicates = [HasAVX512, HasVLX] in {
4115 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4116 Ctrl.info128>, EVEX_V128;
4117 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4118 Ctrl.info256>, EVEX_V256;
4122 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4123 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4125 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4126 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4128 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4130 let isCodeGenOnly = 1 in {
4131 // lowering implementation with the alternative types
4132 defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
4133 defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
4134 OpcodeStr, X86VPermilpi, Ctrl>,
4135 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4139 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4141 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4142 avx512vl_i64_info>, VEX_W;
4143 //===----------------------------------------------------------------------===//
4144 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4145 //===----------------------------------------------------------------------===//
4147 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4148 X86PShufd, avx512vl_i32_info>,
4149 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4150 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4151 X86PShufhw>, EVEX, AVX512XSIi8Base;
4152 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4153 X86PShuflw>, EVEX, AVX512XDIi8Base;
4155 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4156 let Predicates = [HasBWI] in
4157 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4159 let Predicates = [HasVLX, HasBWI] in {
4160 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4161 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4165 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4167 //===----------------------------------------------------------------------===//
4168 // AVX-512 - MOVDDUP
4169 //===----------------------------------------------------------------------===//
4171 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
4172 X86MemOperand x86memop, PatFrag memop_frag> {
4173 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4174 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4175 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
4176 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4177 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4179 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
4182 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
4183 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4184 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
4185 (VMOVDDUPZrm addr:$src)>;
4187 //===---------------------------------------------------------------------===//
4188 // Replicate Single FP - MOVSHDUP and MOVSLDUP
4189 //===---------------------------------------------------------------------===//
4190 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4191 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4192 X86MemOperand x86memop> {
4193 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4194 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4195 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
4197 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4198 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4199 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
4202 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4203 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4204 EVEX_CD8<32, CD8VF>;
4205 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4206 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4207 EVEX_CD8<32, CD8VF>;
4209 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
4210 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
4211 (VMOVSHDUPZrm addr:$src)>;
4212 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
4213 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
4214 (VMOVSLDUPZrm addr:$src)>;
4216 //===----------------------------------------------------------------------===//
4217 // Move Low to High and High to Low packed FP Instructions
4218 //===----------------------------------------------------------------------===//
4219 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4220 (ins VR128X:$src1, VR128X:$src2),
4221 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4222 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4223 IIC_SSE_MOV_LH>, EVEX_4V;
4224 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4225 (ins VR128X:$src1, VR128X:$src2),
4226 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4227 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4228 IIC_SSE_MOV_LH>, EVEX_4V;
4230 let Predicates = [HasAVX512] in {
4232 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4233 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4234 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4235 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4238 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4239 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4242 //===----------------------------------------------------------------------===//
4243 // FMA - Fused Multiply Operations
4246 let Constraints = "$src1 = $dst" in {
4247 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4248 X86VectorVTInfo _> {
4249 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4250 (ins _.RC:$src2, _.RC:$src3),
4251 OpcodeStr, "$src3, $src2", "$src2, $src3",
4252 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4255 let mayLoad = 1 in {
4256 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4257 (ins _.RC:$src2, _.MemOp:$src3),
4258 OpcodeStr, "$src3, $src2", "$src2, $src3",
4259 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4262 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4263 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4264 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4265 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4267 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4268 AVX512FMA3Base, EVEX_B;
4272 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4273 X86VectorVTInfo _> {
4274 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4275 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4276 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4277 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4278 AVX512FMA3Base, EVEX_B, EVEX_RC;
4280 } // Constraints = "$src1 = $dst"
4282 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4283 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4284 let Predicates = [HasAVX512] in {
4285 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4286 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4287 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4289 let Predicates = [HasVLX, HasAVX512] in {
4290 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4291 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4292 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4293 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4297 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4298 SDNode OpNodeRnd > {
4299 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4301 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4302 avx512vl_f64_info>, VEX_W;
4305 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4306 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4307 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4308 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4309 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4310 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4313 let Constraints = "$src1 = $dst" in {
4314 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4315 X86VectorVTInfo _> {
4316 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4317 (ins _.RC:$src2, _.RC:$src3),
4318 OpcodeStr, "$src3, $src2", "$src2, $src3",
4319 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4322 let mayLoad = 1 in {
4323 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4324 (ins _.RC:$src2, _.MemOp:$src3),
4325 OpcodeStr, "$src3, $src2", "$src2, $src3",
4326 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4329 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4330 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4331 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4332 "$src2, ${src3}"##_.BroadcastStr,
4333 (_.VT (OpNode _.RC:$src2,
4334 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4335 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4339 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4340 X86VectorVTInfo _> {
4341 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4342 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4343 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4344 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4345 AVX512FMA3Base, EVEX_B, EVEX_RC;
4347 } // Constraints = "$src1 = $dst"
4349 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4350 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4351 let Predicates = [HasAVX512] in {
4352 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4353 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4354 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4356 let Predicates = [HasVLX, HasAVX512] in {
4357 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4358 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4359 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4360 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4364 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4365 SDNode OpNodeRnd > {
4366 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4368 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4369 avx512vl_f64_info>, VEX_W;
4372 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4373 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4374 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4375 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4376 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4377 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4379 let Constraints = "$src1 = $dst" in {
4380 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4381 X86VectorVTInfo _> {
4382 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4383 (ins _.RC:$src3, _.RC:$src2),
4384 OpcodeStr, "$src2, $src3", "$src3, $src2",
4385 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4388 let mayLoad = 1 in {
4389 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4390 (ins _.RC:$src3, _.MemOp:$src2),
4391 OpcodeStr, "$src2, $src3", "$src3, $src2",
4392 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4395 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4396 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4397 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4398 "$src3, ${src2}"##_.BroadcastStr,
4399 (_.VT (OpNode _.RC:$src1,
4400 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4401 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4405 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4406 X86VectorVTInfo _> {
4407 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4408 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4409 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4410 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4411 AVX512FMA3Base, EVEX_B, EVEX_RC;
4413 } // Constraints = "$src1 = $dst"
4415 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4416 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4417 let Predicates = [HasAVX512] in {
4418 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4419 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4420 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4422 let Predicates = [HasVLX, HasAVX512] in {
4423 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4424 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4425 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4426 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4430 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4431 SDNode OpNodeRnd > {
4432 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4434 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4435 avx512vl_f64_info>, VEX_W;
4438 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4439 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4440 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4441 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4442 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4443 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4446 let Constraints = "$src1 = $dst" in {
4447 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4448 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4449 dag RHS_r, dag RHS_m > {
4450 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4451 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4452 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4455 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4456 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4457 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4459 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4460 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4461 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4462 AVX512FMA3Base, EVEX_B, EVEX_RC;
4464 let isCodeGenOnly = 1 in {
4465 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4466 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4467 !strconcat(OpcodeStr,
4468 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4471 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4472 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4473 !strconcat(OpcodeStr,
4474 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4476 }// isCodeGenOnly = 1
4478 }// Constraints = "$src1 = $dst"
4480 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4481 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4484 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4485 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4486 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4487 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4488 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4490 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4492 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4493 (_.ScalarLdFrag addr:$src3))))>;
4495 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4496 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4497 (_.VT (OpNode _.RC:$src2,
4498 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4500 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4502 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4504 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4505 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4507 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4508 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4509 (_.VT (OpNode _.RC:$src1,
4510 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4512 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4514 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4516 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4517 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4520 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4521 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4522 let Predicates = [HasAVX512] in {
4523 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4524 OpNodeRnd, f32x_info, "SS">,
4525 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4526 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4527 OpNodeRnd, f64x_info, "SD">,
4528 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4532 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4533 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4534 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4535 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4537 //===----------------------------------------------------------------------===//
4538 // AVX-512 Scalar convert from sign integer to float/double
4539 //===----------------------------------------------------------------------===//
4541 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4542 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4543 PatFrag ld_frag, string asm> {
4544 let hasSideEffects = 0 in {
4545 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4546 (ins DstVT.FRC:$src1, SrcRC:$src),
4547 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4550 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4551 (ins DstVT.FRC:$src1, x86memop:$src),
4552 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4554 } // hasSideEffects = 0
4555 let isCodeGenOnly = 1 in {
4556 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4557 (ins DstVT.RC:$src1, SrcRC:$src2),
4558 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4559 [(set DstVT.RC:$dst,
4560 (OpNode (DstVT.VT DstVT.RC:$src1),
4562 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4564 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4565 (ins DstVT.RC:$src1, x86memop:$src2),
4566 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4567 [(set DstVT.RC:$dst,
4568 (OpNode (DstVT.VT DstVT.RC:$src1),
4569 (ld_frag addr:$src2),
4570 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4571 }//isCodeGenOnly = 1
4574 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4575 X86VectorVTInfo DstVT, string asm> {
4576 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4577 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4579 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4580 [(set DstVT.RC:$dst,
4581 (OpNode (DstVT.VT DstVT.RC:$src1),
4583 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4586 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4587 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4588 PatFrag ld_frag, string asm> {
4589 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4590 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4594 let Predicates = [HasAVX512] in {
4595 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4596 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4597 XS, EVEX_CD8<32, CD8VT1>;
4598 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4599 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4600 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4601 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4602 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4603 XD, EVEX_CD8<32, CD8VT1>;
4604 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4605 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4606 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4608 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4609 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4610 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4611 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4612 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4613 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4614 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4615 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4617 def : Pat<(f32 (sint_to_fp GR32:$src)),
4618 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4619 def : Pat<(f32 (sint_to_fp GR64:$src)),
4620 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4621 def : Pat<(f64 (sint_to_fp GR32:$src)),
4622 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4623 def : Pat<(f64 (sint_to_fp GR64:$src)),
4624 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4626 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4627 v4f32x_info, i32mem, loadi32,
4628 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4629 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4630 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4631 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4632 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4633 i32mem, loadi32, "cvtusi2sd{l}">,
4634 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4635 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4636 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4637 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4639 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4640 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4641 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4642 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4643 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4644 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4645 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4646 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4648 def : Pat<(f32 (uint_to_fp GR32:$src)),
4649 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4650 def : Pat<(f32 (uint_to_fp GR64:$src)),
4651 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4652 def : Pat<(f64 (uint_to_fp GR32:$src)),
4653 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4654 def : Pat<(f64 (uint_to_fp GR64:$src)),
4655 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4658 //===----------------------------------------------------------------------===//
4659 // AVX-512 Scalar convert from float/double to integer
4660 //===----------------------------------------------------------------------===//
4661 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4662 RegisterClass DstRC, Intrinsic Int,
4663 Operand memop, ComplexPattern mem_cpat, string asm> {
4664 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4665 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4666 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4667 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4668 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4669 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4670 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4672 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4673 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4674 } // hasSideEffects = 0, Predicates = [HasAVX512]
4677 // Convert float/double to signed/unsigned int 32/64
4678 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4679 ssmem, sse_load_f32, "cvtss2si">,
4680 XS, EVEX_CD8<32, CD8VT1>;
4681 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4682 int_x86_sse_cvtss2si64,
4683 ssmem, sse_load_f32, "cvtss2si">,
4684 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4685 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4686 int_x86_avx512_cvtss2usi,
4687 ssmem, sse_load_f32, "cvtss2usi">,
4688 XS, EVEX_CD8<32, CD8VT1>;
4689 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4690 int_x86_avx512_cvtss2usi64, ssmem,
4691 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4692 EVEX_CD8<32, CD8VT1>;
4693 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4694 sdmem, sse_load_f64, "cvtsd2si">,
4695 XD, EVEX_CD8<64, CD8VT1>;
4696 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4697 int_x86_sse2_cvtsd2si64,
4698 sdmem, sse_load_f64, "cvtsd2si">,
4699 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4700 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4701 int_x86_avx512_cvtsd2usi,
4702 sdmem, sse_load_f64, "cvtsd2usi">,
4703 XD, EVEX_CD8<64, CD8VT1>;
4704 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4705 int_x86_avx512_cvtsd2usi64, sdmem,
4706 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4707 EVEX_CD8<64, CD8VT1>;
4709 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4710 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4711 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4712 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4713 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4714 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4715 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4716 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4717 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4718 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4719 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4720 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4721 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4723 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4724 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4725 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4726 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4728 // Convert float/double to signed/unsigned int 32/64 with truncation
4729 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4730 X86VectorVTInfo _DstRC, SDNode OpNode,
4732 let Predicates = [HasAVX512] in {
4733 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4734 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4735 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4736 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4737 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4739 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4740 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4741 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4744 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4745 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4746 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4747 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4748 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4749 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4750 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4751 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4752 (i32 FROUND_NO_EXC)))]>,
4753 EVEX,VEX_LIG , EVEX_B;
4755 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4756 (ins _SrcRC.MemOp:$src),
4757 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4760 } // isCodeGenOnly = 1, hasSideEffects = 0
4765 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4766 fp_to_sint,X86cvttss2IntRnd>,
4767 XS, EVEX_CD8<32, CD8VT1>;
4768 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4769 fp_to_sint,X86cvttss2IntRnd>,
4770 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4771 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4772 fp_to_sint,X86cvttsd2IntRnd>,
4773 XD, EVEX_CD8<64, CD8VT1>;
4774 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4775 fp_to_sint,X86cvttsd2IntRnd>,
4776 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4778 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
4779 fp_to_uint,X86cvttss2UIntRnd>,
4780 XS, EVEX_CD8<32, CD8VT1>;
4781 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
4782 fp_to_uint,X86cvttss2UIntRnd>,
4783 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
4784 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
4785 fp_to_uint,X86cvttsd2UIntRnd>,
4786 XD, EVEX_CD8<64, CD8VT1>;
4787 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
4788 fp_to_uint,X86cvttsd2UIntRnd>,
4789 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4790 let Predicates = [HasAVX512] in {
4791 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
4792 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4793 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
4794 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4795 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
4796 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4797 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
4798 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4801 //===----------------------------------------------------------------------===//
4802 // AVX-512 Convert form float to double and back
4803 //===----------------------------------------------------------------------===//
4804 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4805 X86VectorVTInfo _Src, SDNode OpNode> {
4806 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4807 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4808 "$src2, $src1", "$src1, $src2",
4809 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4810 (_Src.VT _Src.RC:$src2)))>,
4811 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4812 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4813 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4814 "$src2, $src1", "$src1, $src2",
4815 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4816 (_Src.VT (scalar_to_vector
4817 (_Src.ScalarLdFrag addr:$src2)))))>,
4818 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
4821 // Scalar Coversion with SAE - suppress all exceptions
4822 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4823 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4824 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4825 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4826 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4827 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4828 (_Src.VT _Src.RC:$src2),
4829 (i32 FROUND_NO_EXC)))>,
4830 EVEX_4V, VEX_LIG, EVEX_B;
4833 // Scalar Conversion with rounding control (RC)
4834 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4835 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4836 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4837 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
4838 "$rc, $src2, $src1", "$src1, $src2, $rc",
4839 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4840 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
4841 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4844 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
4845 SDNode OpNodeRnd, X86VectorVTInfo _src,
4846 X86VectorVTInfo _dst> {
4847 let Predicates = [HasAVX512] in {
4848 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4849 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
4850 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
4855 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4856 SDNode OpNodeRnd, X86VectorVTInfo _src,
4857 X86VectorVTInfo _dst> {
4858 let Predicates = [HasAVX512] in {
4859 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4860 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
4861 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
4864 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
4865 X86froundRnd, f64x_info, f32x_info>;
4866 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
4867 X86fpextRnd,f32x_info, f64x_info >;
4869 def : Pat<(f64 (fextend FR32X:$src)),
4870 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
4871 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
4872 Requires<[HasAVX512]>;
4873 def : Pat<(f64 (fextend (loadf32 addr:$src))),
4874 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4875 Requires<[HasAVX512]>;
4877 def : Pat<(f64 (extloadf32 addr:$src)),
4878 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4879 Requires<[HasAVX512, OptForSize]>;
4881 def : Pat<(f64 (extloadf32 addr:$src)),
4882 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
4883 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
4884 Requires<[HasAVX512, OptForSpeed]>;
4886 def : Pat<(f32 (fround FR64X:$src)),
4887 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
4888 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
4889 Requires<[HasAVX512]>;
4890 //===----------------------------------------------------------------------===//
4891 // AVX-512 Vector convert from signed/unsigned integer to float/double
4892 // and from float/double to signed/unsigned integer
4893 //===----------------------------------------------------------------------===//
4895 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4896 X86VectorVTInfo _Src, SDNode OpNode,
4897 string Broadcast = _.BroadcastStr,
4898 string Alias = ""> {
4900 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4901 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
4902 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
4904 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4905 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
4906 (_.VT (OpNode (_Src.VT
4907 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
4909 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4910 (ins _Src.MemOp:$src), OpcodeStr,
4911 "${src}"##Broadcast, "${src}"##Broadcast,
4912 (_.VT (OpNode (_Src.VT
4913 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
4916 // Coversion with SAE - suppress all exceptions
4917 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4918 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4919 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4920 (ins _Src.RC:$src), OpcodeStr,
4921 "{sae}, $src", "$src, {sae}",
4922 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
4923 (i32 FROUND_NO_EXC)))>,
4927 // Conversion with rounding control (RC)
4928 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4929 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4930 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4931 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
4932 "$rc, $src", "$src, $rc",
4933 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
4934 EVEX, EVEX_B, EVEX_RC;
4937 // Extend Float to Double
4938 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
4939 let Predicates = [HasAVX512] in {
4940 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
4941 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
4942 X86vfpextRnd>, EVEX_V512;
4944 let Predicates = [HasVLX] in {
4945 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
4946 X86vfpext, "{1to2}">, EVEX_V128;
4947 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
4952 // Truncate Double to Float
4953 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
4954 let Predicates = [HasAVX512] in {
4955 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
4956 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
4957 X86vfproundRnd>, EVEX_V512;
4959 let Predicates = [HasVLX] in {
4960 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
4961 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
4962 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
4963 "{1to4}", "{y}">, EVEX_V256;
4967 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
4968 VEX_W, PD, EVEX_CD8<64, CD8VF>;
4969 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
4970 PS, EVEX_CD8<32, CD8VH>;
4972 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4973 (VCVTPS2PDZrm addr:$src)>;
4975 let Predicates = [HasVLX] in {
4976 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
4977 (VCVTPS2PDZ256rm addr:$src)>;
4980 // Convert Signed/Unsigned Doubleword to Double
4981 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4983 // No rounding in this op
4984 let Predicates = [HasAVX512] in
4985 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
4988 let Predicates = [HasVLX] in {
4989 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
4990 OpNode128, "{1to2}">, EVEX_V128;
4991 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
4996 // Convert Signed/Unsigned Doubleword to Float
4997 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
4999 let Predicates = [HasAVX512] in
5000 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5001 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5002 OpNodeRnd>, EVEX_V512;
5004 let Predicates = [HasVLX] in {
5005 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5007 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5012 // Convert Float to Signed/Unsigned Doubleword with truncation
5013 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5014 SDNode OpNode, SDNode OpNodeRnd> {
5015 let Predicates = [HasAVX512] in {
5016 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5017 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5018 OpNodeRnd>, EVEX_V512;
5020 let Predicates = [HasVLX] in {
5021 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5023 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5028 // Convert Float to Signed/Unsigned Doubleword
5029 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5030 SDNode OpNode, SDNode OpNodeRnd> {
5031 let Predicates = [HasAVX512] in {
5032 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5033 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5034 OpNodeRnd>, EVEX_V512;
5036 let Predicates = [HasVLX] in {
5037 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5039 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5044 // Convert Double to Signed/Unsigned Doubleword with truncation
5045 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5046 SDNode OpNode, SDNode OpNodeRnd> {
5047 let Predicates = [HasAVX512] in {
5048 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5049 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5050 OpNodeRnd>, EVEX_V512;
5052 let Predicates = [HasVLX] in {
5053 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5054 // memory forms of these instructions in Asm Parcer. They have the same
5055 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5056 // due to the same reason.
5057 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5058 "{1to2}", "{x}">, EVEX_V128;
5059 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5060 "{1to4}", "{y}">, EVEX_V256;
5064 // Convert Double to Signed/Unsigned Doubleword
5065 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5066 SDNode OpNode, SDNode OpNodeRnd> {
5067 let Predicates = [HasAVX512] in {
5068 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5069 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5070 OpNodeRnd>, EVEX_V512;
5072 let Predicates = [HasVLX] in {
5073 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5074 // memory forms of these instructions in Asm Parcer. They have the same
5075 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5076 // due to the same reason.
5077 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5078 "{1to2}", "{x}">, EVEX_V128;
5079 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5080 "{1to4}", "{y}">, EVEX_V256;
5084 // Convert Double to Signed/Unsigned Quardword
5085 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5086 SDNode OpNode, SDNode OpNodeRnd> {
5087 let Predicates = [HasDQI] in {
5088 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5089 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5090 OpNodeRnd>, EVEX_V512;
5092 let Predicates = [HasDQI, HasVLX] in {
5093 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5095 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5100 // Convert Double to Signed/Unsigned Quardword with truncation
5101 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5102 SDNode OpNode, SDNode OpNodeRnd> {
5103 let Predicates = [HasDQI] in {
5104 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5105 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5106 OpNodeRnd>, EVEX_V512;
5108 let Predicates = [HasDQI, HasVLX] in {
5109 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5111 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5116 // Convert Signed/Unsigned Quardword to Double
5117 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5118 SDNode OpNode, SDNode OpNodeRnd> {
5119 let Predicates = [HasDQI] in {
5120 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5121 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5122 OpNodeRnd>, EVEX_V512;
5124 let Predicates = [HasDQI, HasVLX] in {
5125 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5127 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5132 // Convert Float to Signed/Unsigned Quardword
5133 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5134 SDNode OpNode, SDNode OpNodeRnd> {
5135 let Predicates = [HasDQI] in {
5136 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5137 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5138 OpNodeRnd>, EVEX_V512;
5140 let Predicates = [HasDQI, HasVLX] in {
5141 // Explicitly specified broadcast string, since we take only 2 elements
5142 // from v4f32x_info source
5143 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5144 "{1to2}">, EVEX_V128;
5145 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5150 // Convert Float to Signed/Unsigned Quardword with truncation
5151 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5152 SDNode OpNode, SDNode OpNodeRnd> {
5153 let Predicates = [HasDQI] in {
5154 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5155 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5156 OpNodeRnd>, EVEX_V512;
5158 let Predicates = [HasDQI, HasVLX] in {
5159 // Explicitly specified broadcast string, since we take only 2 elements
5160 // from v4f32x_info source
5161 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5162 "{1to2}">, EVEX_V128;
5163 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5168 // Convert Signed/Unsigned Quardword to Float
5169 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5170 SDNode OpNode, SDNode OpNodeRnd> {
5171 let Predicates = [HasDQI] in {
5172 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5173 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5174 OpNodeRnd>, EVEX_V512;
5176 let Predicates = [HasDQI, HasVLX] in {
5177 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5178 // memory forms of these instructions in Asm Parcer. They have the same
5179 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5180 // due to the same reason.
5181 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5182 "{1to2}", "{x}">, EVEX_V128;
5183 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5184 "{1to4}", "{y}">, EVEX_V256;
5188 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5189 EVEX_CD8<32, CD8VH>;
5191 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5193 PS, EVEX_CD8<32, CD8VF>;
5195 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5197 XS, EVEX_CD8<32, CD8VF>;
5199 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5201 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5203 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5204 X86VFpToUintRnd>, PS,
5205 EVEX_CD8<32, CD8VF>;
5207 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5208 X86VFpToUintRnd>, PS, VEX_W,
5209 EVEX_CD8<64, CD8VF>;
5211 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5212 XS, EVEX_CD8<32, CD8VH>;
5214 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5215 X86VUintToFpRnd>, XD,
5216 EVEX_CD8<32, CD8VF>;
5218 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5219 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5221 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5222 X86cvtpd2IntRnd>, XD, VEX_W,
5223 EVEX_CD8<64, CD8VF>;
5225 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5227 PS, EVEX_CD8<32, CD8VF>;
5228 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5229 X86cvtpd2UIntRnd>, VEX_W,
5230 PS, EVEX_CD8<64, CD8VF>;
5232 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5233 X86cvtpd2IntRnd>, VEX_W,
5234 PD, EVEX_CD8<64, CD8VF>;
5236 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5237 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5239 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5240 X86cvtpd2UIntRnd>, VEX_W,
5241 PD, EVEX_CD8<64, CD8VF>;
5243 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5244 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5246 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5247 X86VFpToSlongRnd>, VEX_W,
5248 PD, EVEX_CD8<64, CD8VF>;
5250 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5251 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5253 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5254 X86VFpToUlongRnd>, VEX_W,
5255 PD, EVEX_CD8<64, CD8VF>;
5257 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5258 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5260 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5261 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5263 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5264 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5266 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5267 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5269 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5270 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5272 let Predicates = [NoVLX] in {
5273 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5274 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5275 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5277 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5278 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5279 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5281 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5282 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5283 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5285 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5286 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5287 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5289 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5290 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5291 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5294 let Predicates = [HasAVX512] in {
5295 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5296 (VCVTPD2PSZrm addr:$src)>;
5297 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5298 (VCVTPS2PDZrm addr:$src)>;
5301 //===----------------------------------------------------------------------===//
5302 // Half precision conversion instructions
5303 //===----------------------------------------------------------------------===//
5304 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
5305 X86MemOperand x86memop> {
5306 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
5307 "vcvtph2ps\t{$src, $dst|$dst, $src}",
5309 let hasSideEffects = 0, mayLoad = 1 in
5310 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
5311 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
5314 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
5315 X86MemOperand x86memop> {
5316 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
5317 (ins srcRC:$src1, i32u8imm:$src2),
5318 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5320 let hasSideEffects = 0, mayStore = 1 in
5321 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5322 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
5323 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
5326 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
5327 EVEX_CD8<32, CD8VH>;
5328 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
5329 EVEX_CD8<32, CD8VH>;
5331 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
5332 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
5333 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
5335 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
5336 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
5337 (VCVTPH2PSZrr VR256X:$src)>;
5339 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5340 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5341 "ucomiss">, PS, EVEX, VEX_LIG,
5342 EVEX_CD8<32, CD8VT1>;
5343 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5344 "ucomisd">, PD, EVEX,
5345 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5346 let Pattern = []<dag> in {
5347 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5348 "comiss">, PS, EVEX, VEX_LIG,
5349 EVEX_CD8<32, CD8VT1>;
5350 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5351 "comisd">, PD, EVEX,
5352 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5354 let isCodeGenOnly = 1 in {
5355 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5356 load, "ucomiss">, PS, EVEX, VEX_LIG,
5357 EVEX_CD8<32, CD8VT1>;
5358 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5359 load, "ucomisd">, PD, EVEX,
5360 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5362 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5363 load, "comiss">, PS, EVEX, VEX_LIG,
5364 EVEX_CD8<32, CD8VT1>;
5365 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5366 load, "comisd">, PD, EVEX,
5367 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5371 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5372 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5373 X86VectorVTInfo _> {
5374 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5375 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5376 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5377 "$src2, $src1", "$src1, $src2",
5378 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5379 let mayLoad = 1 in {
5380 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5381 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5382 "$src2, $src1", "$src1, $src2",
5383 (OpNode (_.VT _.RC:$src1),
5384 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5389 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5390 EVEX_CD8<32, CD8VT1>, T8PD;
5391 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5392 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5393 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5394 EVEX_CD8<32, CD8VT1>, T8PD;
5395 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5396 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5398 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5399 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5400 X86VectorVTInfo _> {
5401 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5402 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5403 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5404 let mayLoad = 1 in {
5405 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5406 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5408 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5409 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5410 (ins _.ScalarMemOp:$src), OpcodeStr,
5411 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5413 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5418 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5419 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5420 EVEX_V512, EVEX_CD8<32, CD8VF>;
5421 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5422 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5424 // Define only if AVX512VL feature is present.
5425 let Predicates = [HasVLX] in {
5426 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5427 OpNode, v4f32x_info>,
5428 EVEX_V128, EVEX_CD8<32, CD8VF>;
5429 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5430 OpNode, v8f32x_info>,
5431 EVEX_V256, EVEX_CD8<32, CD8VF>;
5432 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5433 OpNode, v2f64x_info>,
5434 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5435 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5436 OpNode, v4f64x_info>,
5437 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5441 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5442 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5444 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5445 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5446 (VRSQRT14PSZr VR512:$src)>;
5447 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5448 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5449 (VRSQRT14PDZr VR512:$src)>;
5451 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5452 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5453 (VRCP14PSZr VR512:$src)>;
5454 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5455 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5456 (VRCP14PDZr VR512:$src)>;
5458 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5459 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5462 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5463 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5464 "$src2, $src1", "$src1, $src2",
5465 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5466 (i32 FROUND_CURRENT))>;
5468 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5469 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5470 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5471 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5472 (i32 FROUND_NO_EXC))>, EVEX_B;
5474 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5475 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5476 "$src2, $src1", "$src1, $src2",
5477 (OpNode (_.VT _.RC:$src1),
5478 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5479 (i32 FROUND_CURRENT))>;
5482 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5483 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5484 EVEX_CD8<32, CD8VT1>;
5485 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5486 EVEX_CD8<64, CD8VT1>, VEX_W;
5489 let hasSideEffects = 0, Predicates = [HasERI] in {
5490 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5491 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5494 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5495 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5497 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5500 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5501 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5502 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5504 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5505 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5507 (bitconvert (_.LdFrag addr:$src))),
5508 (i32 FROUND_CURRENT))>;
5510 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5511 (ins _.MemOp:$src), OpcodeStr,
5512 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5514 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5515 (i32 FROUND_CURRENT))>, EVEX_B;
5517 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5519 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5520 (ins _.RC:$src), OpcodeStr,
5521 "{sae}, $src", "$src, {sae}",
5522 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5525 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5526 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5527 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5528 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5529 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5530 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5531 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5534 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5536 // Define only if AVX512VL feature is present.
5537 let Predicates = [HasVLX] in {
5538 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5539 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5540 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5541 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5542 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5543 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5544 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5545 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5548 let Predicates = [HasERI], hasSideEffects = 0 in {
5550 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5551 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5552 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5554 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5555 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5557 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5558 SDNode OpNodeRnd, X86VectorVTInfo _>{
5559 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5560 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5561 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5562 EVEX, EVEX_B, EVEX_RC;
5565 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5566 SDNode OpNode, X86VectorVTInfo _>{
5567 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5568 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5569 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5570 let mayLoad = 1 in {
5571 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5572 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5574 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5576 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5577 (ins _.ScalarMemOp:$src), OpcodeStr,
5578 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5580 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5585 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5587 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5589 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5590 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5592 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5593 // Define only if AVX512VL feature is present.
5594 let Predicates = [HasVLX] in {
5595 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5596 OpNode, v4f32x_info>,
5597 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5598 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5599 OpNode, v8f32x_info>,
5600 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5601 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5602 OpNode, v2f64x_info>,
5603 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5604 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5605 OpNode, v4f64x_info>,
5606 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5610 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5612 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5613 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5614 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5615 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5618 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5619 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5621 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5622 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5623 "$src2, $src1", "$src1, $src2",
5624 (OpNodeRnd (_.VT _.RC:$src1),
5626 (i32 FROUND_CURRENT))>;
5628 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5629 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5630 "$src2, $src1", "$src1, $src2",
5631 (OpNodeRnd (_.VT _.RC:$src1),
5632 (_.VT (scalar_to_vector
5633 (_.ScalarLdFrag addr:$src2))),
5634 (i32 FROUND_CURRENT))>;
5636 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5637 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5638 "$rc, $src2, $src1", "$src1, $src2, $rc",
5639 (OpNodeRnd (_.VT _.RC:$src1),
5644 let isCodeGenOnly = 1 in {
5645 def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst),
5646 (ins _.FRC:$src1, _.FRC:$src2),
5647 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5650 def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst),
5651 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5652 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5655 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5656 (!cast<Instruction>(NAME#SUFF#Zr)
5657 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5659 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5660 (!cast<Instruction>(NAME#SUFF#Zm)
5661 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5664 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5665 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5666 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5667 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5668 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5671 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5672 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5674 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5676 let Predicates = [HasAVX512] in {
5677 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5678 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5679 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5680 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5681 Requires<[OptForSize]>;
5682 def : Pat<(f32 (X86frcp FR32X:$src)),
5683 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5684 def : Pat<(f32 (X86frcp (load addr:$src))),
5685 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5686 Requires<[OptForSize]>;
5690 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5692 let ExeDomain = _.ExeDomain in {
5693 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5694 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5695 "$src3, $src2, $src1", "$src1, $src2, $src3",
5696 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5697 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5699 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5700 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5701 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5702 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5703 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5706 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5707 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5708 "$src3, $src2, $src1", "$src1, $src2, $src3",
5709 (_.VT (X86RndScales (_.VT _.RC:$src1),
5710 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5711 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5713 let Predicates = [HasAVX512] in {
5714 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5715 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5716 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5717 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5718 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5719 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5720 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5721 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5722 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5723 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5724 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5725 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5726 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5727 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5728 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5730 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5731 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5732 addr:$src, (i32 0x1))), _.FRC)>;
5733 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5734 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5735 addr:$src, (i32 0x2))), _.FRC)>;
5736 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5737 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5738 addr:$src, (i32 0x3))), _.FRC)>;
5739 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5740 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5741 addr:$src, (i32 0x4))), _.FRC)>;
5742 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5743 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5744 addr:$src, (i32 0xc))), _.FRC)>;
5748 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5749 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5751 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5752 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5754 //-------------------------------------------------
5755 // Integer truncate and extend operations
5756 //-------------------------------------------------
5758 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5759 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5760 X86MemOperand x86memop> {
5762 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5763 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5764 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5767 // for intrinsic patter match
5768 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5769 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5771 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5774 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5775 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5776 DestInfo.ImmAllZerosV)),
5777 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5780 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5781 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5782 DestInfo.RC:$src0)),
5783 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5784 DestInfo.KRCWM:$mask ,
5787 let mayStore = 1 in {
5788 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5789 (ins x86memop:$dst, SrcInfo.RC:$src),
5790 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5793 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5794 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5795 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5800 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5801 X86VectorVTInfo DestInfo,
5802 PatFrag truncFrag, PatFrag mtruncFrag > {
5804 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5805 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5806 addr:$dst, SrcInfo.RC:$src)>;
5808 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5809 (SrcInfo.VT SrcInfo.RC:$src)),
5810 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5811 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
5814 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
5815 X86VectorVTInfo DestInfo, string sat > {
5817 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5818 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5819 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
5820 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
5821 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
5822 (SrcInfo.VT SrcInfo.RC:$src))>;
5824 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5825 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5826 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
5827 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
5828 (SrcInfo.VT SrcInfo.RC:$src))>;
5831 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
5832 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5833 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5834 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5835 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
5836 Predicate prd = HasAVX512>{
5838 let Predicates = [HasVLX, prd] in {
5839 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5840 DestInfoZ128, x86memopZ128>,
5841 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5842 truncFrag, mtruncFrag>, EVEX_V128;
5844 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5845 DestInfoZ256, x86memopZ256>,
5846 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5847 truncFrag, mtruncFrag>, EVEX_V256;
5849 let Predicates = [prd] in
5850 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5851 DestInfoZ, x86memopZ>,
5852 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5853 truncFrag, mtruncFrag>, EVEX_V512;
5856 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
5857 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5858 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5859 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5860 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
5862 let Predicates = [HasVLX, prd] in {
5863 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5864 DestInfoZ128, x86memopZ128>,
5865 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5868 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5869 DestInfoZ256, x86memopZ256>,
5870 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5873 let Predicates = [prd] in
5874 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5875 DestInfoZ, x86memopZ>,
5876 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5880 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5881 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5882 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5883 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
5885 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
5886 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
5887 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5888 sat>, EVEX_CD8<8, CD8VO>;
5891 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5892 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5893 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5894 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
5896 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
5897 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
5898 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5899 sat>, EVEX_CD8<16, CD8VQ>;
5902 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5903 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5904 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5905 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
5907 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
5908 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
5909 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5910 sat>, EVEX_CD8<32, CD8VH>;
5913 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5914 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5915 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5916 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
5918 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
5919 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
5920 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5921 sat>, EVEX_CD8<8, CD8VQ>;
5924 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5925 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5926 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5927 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
5929 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
5930 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
5931 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5932 sat>, EVEX_CD8<16, CD8VH>;
5935 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5936 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
5937 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5938 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
5940 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
5941 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
5942 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5943 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
5946 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
5947 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
5948 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
5950 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
5951 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
5952 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
5954 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
5955 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
5956 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
5958 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
5959 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
5960 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
5962 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
5963 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
5964 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
5966 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
5967 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
5968 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
5970 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
5971 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
5972 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
5974 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
5975 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
5976 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
5979 let mayLoad = 1 in {
5980 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
5981 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
5982 (DestInfo.VT (LdFrag addr:$src))>,
5987 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
5988 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5989 let Predicates = [HasVLX, HasBWI] in {
5990 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
5991 v16i8x_info, i64mem, LdFrag, OpNode>,
5992 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
5994 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
5995 v16i8x_info, i128mem, LdFrag, OpNode>,
5996 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
5998 let Predicates = [HasBWI] in {
5999 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6000 v32i8x_info, i256mem, LdFrag, OpNode>,
6001 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6005 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6006 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6007 let Predicates = [HasVLX, HasAVX512] in {
6008 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6009 v16i8x_info, i32mem, LdFrag, OpNode>,
6010 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6012 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6013 v16i8x_info, i64mem, LdFrag, OpNode>,
6014 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6016 let Predicates = [HasAVX512] in {
6017 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6018 v16i8x_info, i128mem, LdFrag, OpNode>,
6019 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6023 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6024 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6025 let Predicates = [HasVLX, HasAVX512] in {
6026 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6027 v16i8x_info, i16mem, LdFrag, OpNode>,
6028 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6030 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6031 v16i8x_info, i32mem, LdFrag, OpNode>,
6032 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6034 let Predicates = [HasAVX512] in {
6035 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6036 v16i8x_info, i64mem, LdFrag, OpNode>,
6037 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6041 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6042 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6043 let Predicates = [HasVLX, HasAVX512] in {
6044 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6045 v8i16x_info, i64mem, LdFrag, OpNode>,
6046 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6048 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6049 v8i16x_info, i128mem, LdFrag, OpNode>,
6050 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6052 let Predicates = [HasAVX512] in {
6053 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6054 v16i16x_info, i256mem, LdFrag, OpNode>,
6055 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6059 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6060 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6061 let Predicates = [HasVLX, HasAVX512] in {
6062 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6063 v8i16x_info, i32mem, LdFrag, OpNode>,
6064 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6066 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6067 v8i16x_info, i64mem, LdFrag, OpNode>,
6068 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6070 let Predicates = [HasAVX512] in {
6071 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6072 v8i16x_info, i128mem, LdFrag, OpNode>,
6073 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6077 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6078 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6080 let Predicates = [HasVLX, HasAVX512] in {
6081 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6082 v4i32x_info, i64mem, LdFrag, OpNode>,
6083 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6085 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6086 v4i32x_info, i128mem, LdFrag, OpNode>,
6087 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6089 let Predicates = [HasAVX512] in {
6090 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6091 v8i32x_info, i256mem, LdFrag, OpNode>,
6092 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6096 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6097 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6098 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6099 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6100 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6101 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6104 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6105 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6106 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6107 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6108 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6109 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6111 //===----------------------------------------------------------------------===//
6112 // GATHER - SCATTER Operations
6114 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6115 X86MemOperand memop, PatFrag GatherNode> {
6116 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6117 ExeDomain = _.ExeDomain in
6118 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6119 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6120 !strconcat(OpcodeStr#_.Suffix,
6121 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6122 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6123 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6124 vectoraddr:$src2))]>, EVEX, EVEX_K,
6125 EVEX_CD8<_.EltSize, CD8VT1>;
6128 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6129 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6130 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6131 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6132 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6133 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6134 let Predicates = [HasVLX] in {
6135 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6136 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6137 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6138 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6139 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6140 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6141 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6142 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6146 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6147 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6148 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6149 mgatherv16i32>, EVEX_V512;
6150 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6151 mgatherv8i64>, EVEX_V512;
6152 let Predicates = [HasVLX] in {
6153 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6154 vy32xmem, mgatherv8i32>, EVEX_V256;
6155 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6156 vy64xmem, mgatherv4i64>, EVEX_V256;
6157 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6158 vx32xmem, mgatherv4i32>, EVEX_V128;
6159 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6160 vx64xmem, mgatherv2i64>, EVEX_V128;
6165 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6166 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6168 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6169 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6171 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6172 X86MemOperand memop, PatFrag ScatterNode> {
6174 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6176 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6177 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6178 !strconcat(OpcodeStr#_.Suffix,
6179 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6180 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6181 _.KRCWM:$mask, vectoraddr:$dst))]>,
6182 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6185 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6186 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6187 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6188 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6189 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6190 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6191 let Predicates = [HasVLX] in {
6192 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6193 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6194 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6195 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6196 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6197 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6198 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6199 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6203 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6204 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6205 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6206 mscatterv16i32>, EVEX_V512;
6207 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6208 mscatterv8i64>, EVEX_V512;
6209 let Predicates = [HasVLX] in {
6210 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6211 vy32xmem, mscatterv8i32>, EVEX_V256;
6212 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6213 vy64xmem, mscatterv4i64>, EVEX_V256;
6214 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6215 vx32xmem, mscatterv4i32>, EVEX_V128;
6216 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6217 vx64xmem, mscatterv2i64>, EVEX_V128;
6221 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6222 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6224 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6225 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6228 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6229 RegisterClass KRC, X86MemOperand memop> {
6230 let Predicates = [HasPFI], hasSideEffects = 1 in
6231 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6232 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6236 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6237 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6239 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6240 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6242 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6243 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6245 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6246 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6248 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6249 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6251 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6252 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6254 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6255 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6257 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6258 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6260 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6261 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6263 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6264 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6266 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6267 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6269 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6270 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6272 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6273 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6275 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6276 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6278 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6279 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6281 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6282 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6284 // Helper fragments to match sext vXi1 to vXiY.
6285 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6286 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6288 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6289 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6290 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6292 def : Pat<(store VK1:$src, addr:$dst),
6294 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6295 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6297 def : Pat<(store VK8:$src, addr:$dst),
6299 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6300 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6302 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6303 (truncstore node:$val, node:$ptr), [{
6304 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6307 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6308 (MOV8mr addr:$dst, GR8:$src)>;
6310 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6311 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6312 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6313 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6316 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6317 string OpcodeStr, Predicate prd> {
6318 let Predicates = [prd] in
6319 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6321 let Predicates = [prd, HasVLX] in {
6322 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6323 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6327 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6328 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6330 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6332 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6334 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6338 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6340 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6341 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6342 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6343 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6346 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6347 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6348 let Predicates = [prd] in
6349 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6352 let Predicates = [prd, HasVLX] in {
6353 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6355 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6360 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6361 avx512vl_i8_info, HasBWI>;
6362 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6363 avx512vl_i16_info, HasBWI>, VEX_W;
6364 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6365 avx512vl_i32_info, HasDQI>;
6366 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6367 avx512vl_i64_info, HasDQI>, VEX_W;
6369 //===----------------------------------------------------------------------===//
6370 // AVX-512 - COMPRESS and EXPAND
6373 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6375 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6376 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6377 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6379 let mayStore = 1 in {
6380 def mr : AVX5128I<opc, MRMDestMem, (outs),
6381 (ins _.MemOp:$dst, _.RC:$src),
6382 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6383 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6385 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6386 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6387 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6388 [(store (_.VT (vselect _.KRCWM:$mask,
6389 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6391 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6395 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6396 AVX512VLVectorVTInfo VTInfo> {
6397 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6399 let Predicates = [HasVLX] in {
6400 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6401 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6405 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6407 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6409 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6411 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6415 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6417 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6418 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6419 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6422 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6423 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6424 (_.VT (X86expand (_.VT (bitconvert
6425 (_.LdFrag addr:$src1)))))>,
6426 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6429 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6430 AVX512VLVectorVTInfo VTInfo> {
6431 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6433 let Predicates = [HasVLX] in {
6434 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6435 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6439 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6441 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6443 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6445 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6448 //handle instruction reg_vec1 = op(reg_vec,imm)
6450 // op(broadcast(eltVt),imm)
6451 //all instruction created with FROUND_CURRENT
6452 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6454 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6455 (ins _.RC:$src1, i32u8imm:$src2),
6456 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6457 (OpNode (_.VT _.RC:$src1),
6459 (i32 FROUND_CURRENT))>;
6460 let mayLoad = 1 in {
6461 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6462 (ins _.MemOp:$src1, i32u8imm:$src2),
6463 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6464 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6466 (i32 FROUND_CURRENT))>;
6467 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6468 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6469 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6470 "${src1}"##_.BroadcastStr##", $src2",
6471 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6473 (i32 FROUND_CURRENT))>, EVEX_B;
6477 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6478 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6479 SDNode OpNode, X86VectorVTInfo _>{
6480 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6481 (ins _.RC:$src1, i32u8imm:$src2),
6482 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6483 "$src1, {sae}, $src2",
6484 (OpNode (_.VT _.RC:$src1),
6486 (i32 FROUND_NO_EXC))>, EVEX_B;
6489 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6490 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6491 let Predicates = [prd] in {
6492 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6493 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6496 let Predicates = [prd, HasVLX] in {
6497 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6499 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6504 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6505 // op(reg_vec2,mem_vec,imm)
6506 // op(reg_vec2,broadcast(eltVt),imm)
6507 //all instruction created with FROUND_CURRENT
6508 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6510 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6511 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6512 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6513 (OpNode (_.VT _.RC:$src1),
6516 (i32 FROUND_CURRENT))>;
6517 let mayLoad = 1 in {
6518 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6519 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6520 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6521 (OpNode (_.VT _.RC:$src1),
6522 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6524 (i32 FROUND_CURRENT))>;
6525 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6526 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6527 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6528 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6529 (OpNode (_.VT _.RC:$src1),
6530 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6532 (i32 FROUND_CURRENT))>, EVEX_B;
6536 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6537 // op(reg_vec2,mem_vec,imm)
6538 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6539 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6541 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6542 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6543 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6544 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6545 (SrcInfo.VT SrcInfo.RC:$src2),
6548 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6549 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6550 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6551 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6552 (SrcInfo.VT (bitconvert
6553 (SrcInfo.LdFrag addr:$src2))),
6557 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6558 // op(reg_vec2,mem_vec,imm)
6559 // op(reg_vec2,broadcast(eltVt),imm)
6560 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6562 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6565 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6566 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6567 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6568 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6569 (OpNode (_.VT _.RC:$src1),
6570 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6571 (i8 imm:$src3))>, EVEX_B;
6574 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6575 // op(reg_vec2,mem_scalar,imm)
6576 //all instruction created with FROUND_CURRENT
6577 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6578 X86VectorVTInfo _> {
6580 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6581 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6582 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6583 (OpNode (_.VT _.RC:$src1),
6586 (i32 FROUND_CURRENT))>;
6587 let mayLoad = 1 in {
6588 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6589 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6590 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6591 (OpNode (_.VT _.RC:$src1),
6592 (_.VT (scalar_to_vector
6593 (_.ScalarLdFrag addr:$src2))),
6595 (i32 FROUND_CURRENT))>;
6597 let isAsmParserOnly = 1 in {
6598 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6599 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6600 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6606 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6607 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6608 SDNode OpNode, X86VectorVTInfo _>{
6609 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6610 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6611 OpcodeStr, "$src3,{sae}, $src2, $src1",
6612 "$src1, $src2,{sae}, $src3",
6613 (OpNode (_.VT _.RC:$src1),
6616 (i32 FROUND_NO_EXC))>, EVEX_B;
6618 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6619 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6620 SDNode OpNode, X86VectorVTInfo _> {
6621 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6622 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6623 OpcodeStr, "$src3,{sae}, $src2, $src1",
6624 "$src1, $src2,{sae}, $src3",
6625 (OpNode (_.VT _.RC:$src1),
6628 (i32 FROUND_NO_EXC))>, EVEX_B;
6631 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6632 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6633 let Predicates = [prd] in {
6634 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6635 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6639 let Predicates = [prd, HasVLX] in {
6640 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6642 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6647 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6648 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6649 let Predicates = [HasBWI] in {
6650 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6651 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6653 let Predicates = [HasBWI, HasVLX] in {
6654 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6655 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6656 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6657 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6661 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6662 bits<8> opc, SDNode OpNode>{
6663 let Predicates = [HasAVX512] in {
6664 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6666 let Predicates = [HasAVX512, HasVLX] in {
6667 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6668 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6672 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6673 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6674 let Predicates = [prd] in {
6675 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6676 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6680 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6681 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6682 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6683 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6684 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6685 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6688 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6689 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6690 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6691 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6692 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6693 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6695 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6696 0x55, X86VFixupimm, HasAVX512>,
6697 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6698 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6699 0x55, X86VFixupimm, HasAVX512>,
6700 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6702 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6703 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6704 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6705 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6706 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6707 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6710 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6711 0x50, X86VRange, HasDQI>,
6712 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6713 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6714 0x50, X86VRange, HasDQI>,
6715 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6717 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6718 0x51, X86VRange, HasDQI>,
6719 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6720 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6721 0x51, X86VRange, HasDQI>,
6722 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6724 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6725 0x57, X86Reduces, HasDQI>,
6726 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6727 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6728 0x57, X86Reduces, HasDQI>,
6729 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6731 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
6732 0x27, X86GetMants, HasAVX512>,
6733 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6734 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
6735 0x27, X86GetMants, HasAVX512>,
6736 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6738 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6739 bits<8> opc, SDNode OpNode = X86Shuf128>{
6740 let Predicates = [HasAVX512] in {
6741 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6744 let Predicates = [HasAVX512, HasVLX] in {
6745 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6748 let Predicates = [HasAVX512] in {
6749 def : Pat<(v16f32 (ffloor VR512:$src)),
6750 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6751 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6752 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6753 def : Pat<(v16f32 (fceil VR512:$src)),
6754 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6755 def : Pat<(v16f32 (frint VR512:$src)),
6756 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6757 def : Pat<(v16f32 (ftrunc VR512:$src)),
6758 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6760 def : Pat<(v8f64 (ffloor VR512:$src)),
6761 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6762 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6763 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6764 def : Pat<(v8f64 (fceil VR512:$src)),
6765 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6766 def : Pat<(v8f64 (frint VR512:$src)),
6767 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6768 def : Pat<(v8f64 (ftrunc VR512:$src)),
6769 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6772 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6773 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6774 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6775 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6776 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6777 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6778 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6779 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6781 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6782 AVX512VLVectorVTInfo VTInfo_FP>{
6783 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6784 AVX512AIi8Base, EVEX_4V;
6785 let isCodeGenOnly = 1 in {
6786 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6787 AVX512AIi8Base, EVEX_4V;
6791 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6792 EVEX_CD8<32, CD8VF>;
6793 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6794 EVEX_CD8<64, CD8VF>, VEX_W;
6796 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
6797 let Predicates = p in
6798 def NAME#_.VTName#rri:
6799 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
6800 (!cast<Instruction>(NAME#_.ZSuffix#rri)
6801 _.RC:$src1, _.RC:$src2, imm:$imm)>;
6804 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
6805 avx512_vpalign_lowering<_.info512, [HasBWI]>,
6806 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
6807 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
6809 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
6810 avx512vl_i8_info, avx512vl_i8_info>,
6811 avx512_vpalign_lowering_common<avx512vl_i16_info>,
6812 avx512_vpalign_lowering_common<avx512vl_i32_info>,
6813 avx512_vpalign_lowering_common<avx512vl_f32_info>,
6814 avx512_vpalign_lowering_common<avx512vl_i64_info>,
6815 avx512_vpalign_lowering_common<avx512vl_f64_info>,
6818 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
6819 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
6821 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6822 X86VectorVTInfo _> {
6823 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6824 (ins _.RC:$src1), OpcodeStr##_.Suffix,
6826 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
6829 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6830 (ins _.MemOp:$src1), OpcodeStr##_.Suffix,
6832 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
6833 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
6836 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
6837 X86VectorVTInfo _> :
6838 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
6840 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6841 (ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
6842 "${src1}"##_.BroadcastStr,
6843 "${src1}"##_.BroadcastStr,
6844 (_.VT (OpNode (X86VBroadcast
6845 (_.ScalarLdFrag addr:$src1))))>,
6846 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
6849 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6850 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6851 let Predicates = [prd] in
6852 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
6854 let Predicates = [prd, HasVLX] in {
6855 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
6857 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
6862 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6863 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6864 let Predicates = [prd] in
6865 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
6868 let Predicates = [prd, HasVLX] in {
6869 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
6871 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
6876 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
6877 SDNode OpNode, Predicate prd> {
6878 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
6880 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
6883 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
6884 SDNode OpNode, Predicate prd> {
6885 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
6886 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
6889 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
6890 bits<8> opc_d, bits<8> opc_q,
6891 string OpcodeStr, SDNode OpNode> {
6892 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
6894 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
6898 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
6901 (bc_v16i32 (v16i1sextv16i32)),
6902 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
6903 (VPABSDZrr VR512:$src)>;
6905 (bc_v8i64 (v8i1sextv8i64)),
6906 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
6907 (VPABSQZrr VR512:$src)>;
6909 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
6911 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
6912 let isCodeGenOnly = 1 in
6913 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
6914 ctlz_zero_undef, prd>;
6917 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
6918 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
6920 //===----------------------------------------------------------------------===//
6921 // AVX-512 - Unpack Instructions
6922 //===----------------------------------------------------------------------===//
6923 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
6924 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
6926 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
6927 SSE_INTALU_ITINS_P, HasBWI>;
6928 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
6929 SSE_INTALU_ITINS_P, HasBWI>;
6930 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
6931 SSE_INTALU_ITINS_P, HasBWI>;
6932 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
6933 SSE_INTALU_ITINS_P, HasBWI>;
6935 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
6936 SSE_INTALU_ITINS_P, HasAVX512>;
6937 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
6938 SSE_INTALU_ITINS_P, HasAVX512>;
6939 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
6940 SSE_INTALU_ITINS_P, HasAVX512>;
6941 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
6942 SSE_INTALU_ITINS_P, HasAVX512>;
6943 //===----------------------------------------------------------------------===//
6944 // VSHUFPS - VSHUFPD Operations
6945 //===----------------------------------------------------------------------===//
6946 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6947 AVX512VLVectorVTInfo VTInfo_FP>{
6948 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
6949 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
6950 AVX512AIi8Base, EVEX_4V;
6951 let isCodeGenOnly = 1 in {
6952 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
6953 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
6954 AVX512AIi8Base, EVEX_4V;
6958 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
6959 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
6960 //===----------------------------------------------------------------------===//
6961 // AVX-512 - Byte shift Left/Right
6962 //===----------------------------------------------------------------------===//
6964 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
6965 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
6966 def rr : AVX512<opc, MRMr,
6967 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
6968 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6969 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
6971 def rm : AVX512<opc, MRMm,
6972 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
6973 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6974 [(set _.RC:$dst,(_.VT (OpNode
6975 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
6978 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
6979 Format MRMm, string OpcodeStr, Predicate prd>{
6980 let Predicates = [prd] in
6981 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
6982 OpcodeStr, v8i64_info>, EVEX_V512;
6983 let Predicates = [prd, HasVLX] in {
6984 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
6985 OpcodeStr, v4i64x_info>, EVEX_V256;
6986 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
6987 OpcodeStr, v2i64x_info>, EVEX_V128;
6990 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
6991 HasBWI>, AVX512PDIi8Base, EVEX_4V;
6992 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
6993 HasBWI>, AVX512PDIi8Base, EVEX_4V;
6996 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
6997 string OpcodeStr, X86VectorVTInfo _src>{
6998 def rr : AVX512BI<opc, MRMSrcReg,
6999 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7000 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7001 [(set _src.RC:$dst,(_src.VT
7002 (OpNode _src.RC:$src1, _src.RC:$src2)))]>;
7004 def rm : AVX512BI<opc, MRMSrcMem,
7005 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7006 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7007 [(set _src.RC:$dst,(_src.VT
7008 (OpNode _src.RC:$src1,
7009 (_src.VT (bitconvert
7010 (_src.LdFrag addr:$src2))))))]>;
7013 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7014 string OpcodeStr, Predicate prd> {
7015 let Predicates = [prd] in
7016 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v64i8_info>,
7018 let Predicates = [prd, HasVLX] in {
7019 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v32i8x_info>,
7021 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v16i8x_info>,
7026 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",