1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERM2D : avx512_perm_3src<0x7E, "vperm2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERM2Q : avx512_perm_3src<0x7E, "vperm2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERM2PS : avx512_perm_3src<0x7F, "vperm2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERM2PD : avx512_perm_3src<0x7F, "vperm2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
624 //===----------------------------------------------------------------------===//
625 // AVX-512 - BLEND using mask
627 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
628 RegisterClass KRC, RegisterClass RC,
629 X86MemOperand x86memop, PatFrag mem_frag,
630 SDNode OpNode, ValueType vt> {
631 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
632 (ins KRC:$mask, RC:$src1, RC:$src2),
633 !strconcat(OpcodeStr,
634 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
635 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
636 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 []>, EVEX_4V, EVEX_K;
645 let ExeDomain = SSEPackedSingle in
646 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
647 VK16WM, VR512, f512mem,
648 memopv16f32, vselect, v16f32>,
649 EVEX_CD8<32, CD8VF>, EVEX_V512;
650 let ExeDomain = SSEPackedDouble in
651 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
652 VK8WM, VR512, f512mem,
653 memopv8f64, vselect, v8f64>,
654 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
656 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
657 (v16f32 VR512:$src2), (i16 GR16:$mask))),
658 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
659 VR512:$src1, VR512:$src2)>;
661 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
662 (v8f64 VR512:$src2), (i8 GR8:$mask))),
663 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
664 VR512:$src1, VR512:$src2)>;
666 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
667 VK16WM, VR512, f512mem,
668 memopv16i32, vselect, v16i32>,
669 EVEX_CD8<32, CD8VF>, EVEX_V512;
671 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
672 VK8WM, VR512, f512mem,
673 memopv8i64, vselect, v8i64>,
674 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
676 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
677 (v16i32 VR512:$src2), (i16 GR16:$mask))),
678 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
679 VR512:$src1, VR512:$src2)>;
681 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
682 (v8i64 VR512:$src2), (i8 GR8:$mask))),
683 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
684 VR512:$src1, VR512:$src2)>;
686 let Predicates = [HasAVX512] in {
687 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
688 (v8f32 VR256X:$src2))),
690 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
692 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
694 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
695 (v8i32 VR256X:$src2))),
697 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
701 //===----------------------------------------------------------------------===//
702 // Compare Instructions
703 //===----------------------------------------------------------------------===//
705 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
706 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
707 Operand CC, SDNode OpNode, ValueType VT,
708 PatFrag ld_frag, string asm, string asm_alt> {
709 def rr : AVX512Ii8<0xC2, MRMSrcReg,
710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
711 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
712 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
713 def rm : AVX512Ii8<0xC2, MRMSrcMem,
714 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
715 [(set VK1:$dst, (OpNode (VT RC:$src1),
716 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
717 let isAsmParserOnly = 1, hasSideEffects = 0 in {
718 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
719 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
720 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
721 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
722 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
723 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
727 let Predicates = [HasAVX512] in {
728 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
729 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
730 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
732 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
733 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
738 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
739 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
740 SDNode OpNode, ValueType vt> {
741 def rr : AVX512BI<opc, MRMSrcReg,
742 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
744 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
745 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
746 def rm : AVX512BI<opc, MRMSrcMem,
747 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
749 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
750 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
753 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
754 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
755 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
756 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512, VEX_W;
758 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
759 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
760 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
761 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512, VEX_W;
763 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
764 (COPY_TO_REGCLASS (VPCMPGTDZrr
765 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
766 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
768 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
769 (COPY_TO_REGCLASS (VPCMPEQDZrr
770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
771 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
773 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
774 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
775 SDNode OpNode, ValueType vt, Operand CC, string asm,
777 def rri : AVX512AIi8<opc, MRMSrcReg,
778 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
779 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
780 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
781 def rmi : AVX512AIi8<opc, MRMSrcMem,
782 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
783 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
784 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
785 // Accept explicit immediate argument form instead of comparison code.
786 let isAsmParserOnly = 1, hasSideEffects = 0 in {
787 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
788 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
789 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
790 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
791 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
792 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
796 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
797 X86cmpm, v16i32, AVXCC,
798 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
799 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
800 EVEX_V512, EVEX_CD8<32, CD8VF>;
801 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
802 X86cmpmu, v16i32, AVXCC,
803 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
805 EVEX_V512, EVEX_CD8<32, CD8VF>;
807 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
808 X86cmpm, v8i64, AVXCC,
809 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
810 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
811 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
812 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
813 X86cmpmu, v8i64, AVXCC,
814 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
815 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
816 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
818 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
819 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
820 X86MemOperand x86memop, ValueType vt,
821 string suffix, Domain d> {
822 def rri : AVX512PIi8<0xC2, MRMSrcReg,
823 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
824 !strconcat("vcmp${cc}", suffix,
825 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
826 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
827 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
828 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
829 !strconcat("vcmp${cc}", suffix,
830 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
832 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
833 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
834 !strconcat("vcmp${cc}", suffix,
835 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
837 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
839 // Accept explicit immediate argument form instead of comparison code.
840 let isAsmParserOnly = 1, hasSideEffects = 0 in {
841 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
842 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
843 !strconcat("vcmp", suffix,
844 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
845 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
846 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
847 !strconcat("vcmp", suffix,
848 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
852 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
853 "ps", SSEPackedSingle>, TB, EVEX_4V, EVEX_V512,
855 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
856 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
859 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
860 (COPY_TO_REGCLASS (VCMPPSZrri
861 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
862 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
864 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
865 (COPY_TO_REGCLASS (VPCMPDZrri
866 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
867 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
869 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
870 (COPY_TO_REGCLASS (VPCMPUDZrri
871 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
872 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
875 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
876 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
878 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
879 (I8Imm imm:$cc)), GR16)>;
881 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
882 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
884 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
885 (I8Imm imm:$cc)), GR8)>;
887 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
888 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
890 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
891 (I8Imm imm:$cc)), GR16)>;
893 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
894 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
896 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
897 (I8Imm imm:$cc)), GR8)>;
899 // Mask register copy, including
900 // - copy between mask registers
901 // - load/store mask registers
902 // - copy from GPR to mask register and vice versa
904 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
905 string OpcodeStr, RegisterClass KRC,
906 ValueType vt, X86MemOperand x86memop> {
907 let hasSideEffects = 0 in {
908 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
909 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
911 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
912 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
913 [(set KRC:$dst, (vt (load addr:$src)))]>;
915 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
916 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
920 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
922 RegisterClass KRC, RegisterClass GRC> {
923 let hasSideEffects = 0 in {
924 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
925 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
926 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
927 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
931 let Predicates = [HasAVX512] in {
932 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
934 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
938 let Predicates = [HasAVX512] in {
939 // GR16 from/to 16-bit mask
940 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
941 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
942 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
943 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
945 // Store kreg in memory
946 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
947 (KMOVWmk addr:$dst, VK16:$src)>;
949 def : Pat<(store VK8:$src, addr:$dst),
950 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
952 def : Pat<(i1 (load addr:$src)),
953 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
955 def : Pat<(v8i1 (load addr:$src)),
956 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
958 def : Pat<(i1 (trunc (i32 GR32:$src))),
959 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
961 def : Pat<(i1 (trunc (i8 GR8:$src))),
963 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
965 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
966 def : Pat<(i8 (zext VK1:$src)),
968 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
969 def : Pat<(i64 (zext VK1:$src)),
970 (SUBREG_TO_REG (i64 0),
971 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit)>;
974 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
975 let Predicates = [HasAVX512] in {
976 // GR from/to 8-bit mask without native support
977 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
979 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
981 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
983 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
986 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
987 (COPY_TO_REGCLASS VK16:$src, VK1)>;
988 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
989 (COPY_TO_REGCLASS VK8:$src, VK1)>;
993 // Mask unary operation
995 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
996 RegisterClass KRC, SDPatternOperator OpNode> {
997 let Predicates = [HasAVX512] in
998 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
999 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1000 [(set KRC:$dst, (OpNode KRC:$src))]>;
1003 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1004 SDPatternOperator OpNode> {
1005 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1009 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1011 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1012 let Predicates = [HasAVX512] in
1013 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1015 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1016 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1018 defm : avx512_mask_unop_int<"knot", "KNOT">;
1020 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1021 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1022 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1024 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1025 def : Pat<(not VK8:$src),
1027 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1029 // Mask binary operation
1030 // - KAND, KANDN, KOR, KXNOR, KXOR
1031 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1032 RegisterClass KRC, SDPatternOperator OpNode> {
1033 let Predicates = [HasAVX512] in
1034 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1035 !strconcat(OpcodeStr,
1036 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1037 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1040 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1041 SDPatternOperator OpNode> {
1042 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1046 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1047 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1049 let isCommutable = 1 in {
1050 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1051 let isCommutable = 0 in
1052 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1053 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1054 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1055 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1058 def : Pat<(xor VK1:$src1, VK1:$src2),
1059 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1060 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1062 def : Pat<(or VK1:$src1, VK1:$src2),
1063 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1064 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1066 def : Pat<(not VK1:$src),
1067 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1068 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1069 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1071 def : Pat<(and VK1:$src1, VK1:$src2),
1072 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1073 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1075 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1076 let Predicates = [HasAVX512] in
1077 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1078 (i16 GR16:$src1), (i16 GR16:$src2)),
1079 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1080 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1081 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1084 defm : avx512_mask_binop_int<"kand", "KAND">;
1085 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1086 defm : avx512_mask_binop_int<"kor", "KOR">;
1087 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1088 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1090 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1091 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1092 let Predicates = [HasAVX512] in
1093 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1095 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1096 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1099 defm : avx512_binop_pat<and, KANDWrr>;
1100 defm : avx512_binop_pat<andn, KANDNWrr>;
1101 defm : avx512_binop_pat<or, KORWrr>;
1102 defm : avx512_binop_pat<xnor, KXNORWrr>;
1103 defm : avx512_binop_pat<xor, KXORWrr>;
1106 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1107 RegisterClass KRC> {
1108 let Predicates = [HasAVX512] in
1109 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1110 !strconcat(OpcodeStr,
1111 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1114 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1115 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1119 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1120 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1121 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1122 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1125 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1126 let Predicates = [HasAVX512] in
1127 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1128 (i16 GR16:$src1), (i16 GR16:$src2)),
1129 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1130 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1131 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1133 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1136 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1138 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1139 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1140 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1141 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1144 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1145 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1149 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1151 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1152 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1153 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1156 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1158 let Predicates = [HasAVX512] in
1159 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1160 !strconcat(OpcodeStr,
1161 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1162 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1165 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1167 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1171 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1172 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1174 // Mask setting all 0s or 1s
1175 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1176 let Predicates = [HasAVX512] in
1177 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1178 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1179 [(set KRC:$dst, (VT Val))]>;
1182 multiclass avx512_mask_setop_w<PatFrag Val> {
1183 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1184 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1187 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1188 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1190 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1191 let Predicates = [HasAVX512] in {
1192 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1193 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1194 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1195 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1196 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1198 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1199 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1201 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1202 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1204 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1205 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1207 //===----------------------------------------------------------------------===//
1208 // AVX-512 - Aligned and unaligned load and store
1211 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1212 X86MemOperand x86memop, PatFrag ld_frag,
1213 string asm, Domain d, bit IsReMaterializable = 1> {
1214 let hasSideEffects = 0 in
1215 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1216 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1218 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1219 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1220 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1221 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1222 let Constraints = "$src1 = $dst" in {
1223 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1224 (ins RC:$src1, KRC:$mask, RC:$src2),
1226 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1228 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1229 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1231 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1232 [], d>, EVEX, EVEX_K;
1236 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1237 "vmovaps", SSEPackedSingle>,
1238 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1239 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1240 "vmovapd", SSEPackedDouble>,
1241 PD, EVEX_V512, VEX_W,
1242 EVEX_CD8<64, CD8VF>;
1243 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1244 "vmovups", SSEPackedSingle>,
1245 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1246 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1247 "vmovupd", SSEPackedDouble, 0>,
1248 PD, EVEX_V512, VEX_W,
1249 EVEX_CD8<64, CD8VF>;
1250 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1251 "vmovaps\t{$src, $dst|$dst, $src}",
1252 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1253 SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
1254 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1255 "vmovapd\t{$src, $dst|$dst, $src}",
1256 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1257 SSEPackedDouble>, EVEX, EVEX_V512,
1258 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1259 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1260 "vmovups\t{$src, $dst|$dst, $src}",
1261 [(store (v16f32 VR512:$src), addr:$dst)],
1262 SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
1263 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1264 "vmovupd\t{$src, $dst|$dst, $src}",
1265 [(store (v8f64 VR512:$src), addr:$dst)],
1266 SSEPackedDouble>, EVEX, EVEX_V512,
1267 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1269 let hasSideEffects = 0 in {
1270 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1272 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1274 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1276 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1277 EVEX, EVEX_V512, VEX_W;
1278 let mayStore = 1 in {
1279 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1280 (ins i512mem:$dst, VR512:$src),
1281 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1282 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1283 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1284 (ins i512mem:$dst, VR512:$src),
1285 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1286 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1288 let mayLoad = 1 in {
1289 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1291 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1292 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1293 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1295 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1296 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1300 // 512-bit aligned load/store
1301 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1302 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1304 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1305 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1306 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1307 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1309 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1310 RegisterClass RC, RegisterClass KRC,
1311 PatFrag ld_frag, X86MemOperand x86memop> {
1312 let hasSideEffects = 0 in
1313 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1314 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1315 let canFoldAsLoad = 1 in
1316 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1317 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1318 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1320 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1321 (ins x86memop:$dst, VR512:$src),
1322 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1323 let Constraints = "$src1 = $dst" in {
1324 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1325 (ins RC:$src1, KRC:$mask, RC:$src2),
1327 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1329 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1330 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1332 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1337 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1338 memopv16i32, i512mem>,
1339 EVEX_V512, EVEX_CD8<32, CD8VF>;
1340 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1341 memopv8i64, i512mem>,
1342 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1344 // 512-bit unaligned load/store
1345 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1346 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1348 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1349 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1350 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1351 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1353 let AddedComplexity = 20 in {
1354 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1355 (v16f32 VR512:$src2))),
1356 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1357 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1358 (v8f64 VR512:$src2))),
1359 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1360 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1361 (v16i32 VR512:$src2))),
1362 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1363 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1364 (v8i64 VR512:$src2))),
1365 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1367 // Move Int Doubleword to Packed Double Int
1369 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1370 "vmovd\t{$src, $dst|$dst, $src}",
1372 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1374 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1375 "vmovd\t{$src, $dst|$dst, $src}",
1377 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1378 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1379 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1380 "vmovq\t{$src, $dst|$dst, $src}",
1382 (v2i64 (scalar_to_vector GR64:$src)))],
1383 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1384 let isCodeGenOnly = 1 in {
1385 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1386 "vmovq\t{$src, $dst|$dst, $src}",
1387 [(set FR64:$dst, (bitconvert GR64:$src))],
1388 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1389 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1390 "vmovq\t{$src, $dst|$dst, $src}",
1391 [(set GR64:$dst, (bitconvert FR64:$src))],
1392 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1394 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1395 "vmovq\t{$src, $dst|$dst, $src}",
1396 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1397 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1398 EVEX_CD8<64, CD8VT1>;
1400 // Move Int Doubleword to Single Scalar
1402 let isCodeGenOnly = 1 in {
1403 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1404 "vmovd\t{$src, $dst|$dst, $src}",
1405 [(set FR32X:$dst, (bitconvert GR32:$src))],
1406 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1408 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1409 "vmovd\t{$src, $dst|$dst, $src}",
1410 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1411 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1414 // Move doubleword from xmm register to r/m32
1416 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1417 "vmovd\t{$src, $dst|$dst, $src}",
1418 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1419 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1421 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1422 (ins i32mem:$dst, VR128X:$src),
1423 "vmovd\t{$src, $dst|$dst, $src}",
1424 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1425 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1426 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1428 // Move quadword from xmm1 register to r/m64
1430 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1431 "vmovq\t{$src, $dst|$dst, $src}",
1432 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1434 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1435 Requires<[HasAVX512, In64BitMode]>;
1437 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1438 (ins i64mem:$dst, VR128X:$src),
1439 "vmovq\t{$src, $dst|$dst, $src}",
1440 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1441 addr:$dst)], IIC_SSE_MOVDQ>,
1442 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1443 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1445 // Move Scalar Single to Double Int
1447 let isCodeGenOnly = 1 in {
1448 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1450 "vmovd\t{$src, $dst|$dst, $src}",
1451 [(set GR32:$dst, (bitconvert FR32X:$src))],
1452 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1453 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1454 (ins i32mem:$dst, FR32X:$src),
1455 "vmovd\t{$src, $dst|$dst, $src}",
1456 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1457 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1460 // Move Quadword Int to Packed Quadword Int
1462 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1464 "vmovq\t{$src, $dst|$dst, $src}",
1466 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1467 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1469 //===----------------------------------------------------------------------===//
1470 // AVX-512 MOVSS, MOVSD
1471 //===----------------------------------------------------------------------===//
1473 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1474 SDNode OpNode, ValueType vt,
1475 X86MemOperand x86memop, PatFrag mem_pat> {
1476 let hasSideEffects = 0 in {
1477 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1478 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1479 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1480 (scalar_to_vector RC:$src2))))],
1481 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1482 let Constraints = "$src1 = $dst" in
1483 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1484 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1486 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1487 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1488 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1489 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1490 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1492 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1493 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1494 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1496 } //hasSideEffects = 0
1499 let ExeDomain = SSEPackedSingle in
1500 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1501 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1503 let ExeDomain = SSEPackedDouble in
1504 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1505 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1507 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1508 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1509 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1511 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1512 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1513 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1515 // For the disassembler
1516 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1517 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1518 (ins VR128X:$src1, FR32X:$src2),
1519 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1521 XS, EVEX_4V, VEX_LIG;
1522 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1523 (ins VR128X:$src1, FR64X:$src2),
1524 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1526 XD, EVEX_4V, VEX_LIG, VEX_W;
1529 let Predicates = [HasAVX512] in {
1530 let AddedComplexity = 15 in {
1531 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1532 // MOVS{S,D} to the lower bits.
1533 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1534 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1535 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1536 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1537 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1538 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1539 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1540 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1542 // Move low f32 and clear high bits.
1543 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1544 (SUBREG_TO_REG (i32 0),
1545 (VMOVSSZrr (v4f32 (V_SET0)),
1546 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1547 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1548 (SUBREG_TO_REG (i32 0),
1549 (VMOVSSZrr (v4i32 (V_SET0)),
1550 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1553 let AddedComplexity = 20 in {
1554 // MOVSSrm zeros the high parts of the register; represent this
1555 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1556 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1557 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1558 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1559 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1560 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1561 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1563 // MOVSDrm zeros the high parts of the register; represent this
1564 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1565 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1566 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1567 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1568 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1569 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1570 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1571 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1572 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1573 def : Pat<(v2f64 (X86vzload addr:$src)),
1574 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1576 // Represent the same patterns above but in the form they appear for
1578 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1579 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1580 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1581 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1582 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1583 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1584 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1585 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1586 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1588 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1589 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1590 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1591 FR32X:$src)), sub_xmm)>;
1592 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1593 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1594 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1595 FR64X:$src)), sub_xmm)>;
1596 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1597 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1598 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1600 // Move low f64 and clear high bits.
1601 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1602 (SUBREG_TO_REG (i32 0),
1603 (VMOVSDZrr (v2f64 (V_SET0)),
1604 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1606 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1607 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1608 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1610 // Extract and store.
1611 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1613 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1614 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1616 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1618 // Shuffle with VMOVSS
1619 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1620 (VMOVSSZrr (v4i32 VR128X:$src1),
1621 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1622 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1623 (VMOVSSZrr (v4f32 VR128X:$src1),
1624 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1627 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1628 (SUBREG_TO_REG (i32 0),
1629 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1630 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1632 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1633 (SUBREG_TO_REG (i32 0),
1634 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1635 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1638 // Shuffle with VMOVSD
1639 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1640 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1641 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1642 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1643 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1644 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1645 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1646 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1649 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1650 (SUBREG_TO_REG (i32 0),
1651 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1652 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1654 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1655 (SUBREG_TO_REG (i32 0),
1656 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1657 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1660 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1661 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1662 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1663 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1664 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1665 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1666 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1667 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1670 let AddedComplexity = 15 in
1671 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1673 "vmovq\t{$src, $dst|$dst, $src}",
1674 [(set VR128X:$dst, (v2i64 (X86vzmovl
1675 (v2i64 VR128X:$src))))],
1676 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1678 let AddedComplexity = 20 in
1679 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1681 "vmovq\t{$src, $dst|$dst, $src}",
1682 [(set VR128X:$dst, (v2i64 (X86vzmovl
1683 (loadv2i64 addr:$src))))],
1684 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1685 EVEX_CD8<8, CD8VT8>;
1687 let Predicates = [HasAVX512] in {
1688 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1689 let AddedComplexity = 20 in {
1690 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1691 (VMOVDI2PDIZrm addr:$src)>;
1692 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1693 (VMOV64toPQIZrr GR64:$src)>;
1694 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1695 (VMOVDI2PDIZrr GR32:$src)>;
1697 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1698 (VMOVDI2PDIZrm addr:$src)>;
1699 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1700 (VMOVDI2PDIZrm addr:$src)>;
1701 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1702 (VMOVZPQILo2PQIZrm addr:$src)>;
1703 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1704 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1705 def : Pat<(v2i64 (X86vzload addr:$src)),
1706 (VMOVZPQILo2PQIZrm addr:$src)>;
1709 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1710 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1711 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1712 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1713 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1714 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1715 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1718 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1719 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1721 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1722 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1724 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1725 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1727 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1728 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1730 //===----------------------------------------------------------------------===//
1731 // AVX-512 - Integer arithmetic
1733 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1734 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1735 X86MemOperand x86memop, PatFrag scalar_mfrag,
1736 X86MemOperand x86scalar_mop, string BrdcstStr,
1737 OpndItins itins, bit IsCommutable = 0> {
1738 let isCommutable = IsCommutable in
1739 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1740 (ins RC:$src1, RC:$src2),
1741 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1742 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1744 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1745 (ins RC:$src1, x86memop:$src2),
1746 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1747 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1749 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1750 (ins RC:$src1, x86scalar_mop:$src2),
1751 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1752 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1753 [(set RC:$dst, (OpNode RC:$src1,
1754 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1755 itins.rm>, EVEX_4V, EVEX_B;
1757 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1758 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1759 PatFrag memop_frag, X86MemOperand x86memop,
1761 bit IsCommutable = 0> {
1762 let isCommutable = IsCommutable in
1763 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1764 (ins RC:$src1, RC:$src2),
1765 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1766 []>, EVEX_4V, VEX_W;
1767 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1768 (ins RC:$src1, x86memop:$src2),
1769 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1770 []>, EVEX_4V, VEX_W;
1773 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1774 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1775 EVEX_V512, EVEX_CD8<32, CD8VF>;
1777 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1778 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1779 EVEX_V512, EVEX_CD8<32, CD8VF>;
1781 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1782 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1783 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1785 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1786 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1787 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1789 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1790 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1791 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1793 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1794 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
1795 EVEX_V512, EVEX_CD8<64, CD8VF>;
1797 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1798 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1799 EVEX_CD8<64, CD8VF>;
1801 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1802 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1804 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1805 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1806 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1807 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1808 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1809 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1811 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1812 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1813 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1814 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1815 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1816 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1818 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1819 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1820 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1821 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1822 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1823 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1825 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1826 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1827 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1828 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1829 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1830 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1832 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1833 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1834 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1835 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1836 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1837 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1839 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1840 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1841 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1842 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1843 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1844 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1845 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1846 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1847 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1848 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1849 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1850 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1851 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1852 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1853 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1854 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1855 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1856 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1857 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1858 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1859 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1860 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1861 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1862 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1863 //===----------------------------------------------------------------------===//
1864 // AVX-512 - Unpack Instructions
1865 //===----------------------------------------------------------------------===//
1867 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1868 PatFrag mem_frag, RegisterClass RC,
1869 X86MemOperand x86memop, string asm,
1871 def rr : AVX512PI<opc, MRMSrcReg,
1872 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1874 (vt (OpNode RC:$src1, RC:$src2)))],
1876 def rm : AVX512PI<opc, MRMSrcMem,
1877 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1879 (vt (OpNode RC:$src1,
1880 (bitconvert (mem_frag addr:$src2)))))],
1884 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1885 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1886 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1887 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1888 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1889 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1890 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1891 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1892 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1893 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1894 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1895 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1897 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1898 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1899 X86MemOperand x86memop> {
1900 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1901 (ins RC:$src1, RC:$src2),
1902 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1903 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1904 IIC_SSE_UNPCK>, EVEX_4V;
1905 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1906 (ins RC:$src1, x86memop:$src2),
1907 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1908 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1909 (bitconvert (memop_frag addr:$src2)))))],
1910 IIC_SSE_UNPCK>, EVEX_4V;
1912 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1913 VR512, memopv16i32, i512mem>, EVEX_V512,
1914 EVEX_CD8<32, CD8VF>;
1915 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1916 VR512, memopv8i64, i512mem>, EVEX_V512,
1917 VEX_W, EVEX_CD8<64, CD8VF>;
1918 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1919 VR512, memopv16i32, i512mem>, EVEX_V512,
1920 EVEX_CD8<32, CD8VF>;
1921 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1922 VR512, memopv8i64, i512mem>, EVEX_V512,
1923 VEX_W, EVEX_CD8<64, CD8VF>;
1924 //===----------------------------------------------------------------------===//
1928 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1929 SDNode OpNode, PatFrag mem_frag,
1930 X86MemOperand x86memop, ValueType OpVT> {
1931 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1932 (ins RC:$src1, i8imm:$src2),
1933 !strconcat(OpcodeStr,
1934 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1936 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1938 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1939 (ins x86memop:$src1, i8imm:$src2),
1940 !strconcat(OpcodeStr,
1941 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1943 (OpVT (OpNode (mem_frag addr:$src1),
1944 (i8 imm:$src2))))]>, EVEX;
1947 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1948 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1950 let ExeDomain = SSEPackedSingle in
1951 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1952 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
1953 EVEX_CD8<32, CD8VF>;
1954 let ExeDomain = SSEPackedDouble in
1955 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1956 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
1957 VEX_W, EVEX_CD8<32, CD8VF>;
1959 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1960 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1961 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1962 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1964 //===----------------------------------------------------------------------===//
1965 // AVX-512 Logical Instructions
1966 //===----------------------------------------------------------------------===//
1968 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1969 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1970 EVEX_V512, EVEX_CD8<32, CD8VF>;
1971 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1972 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1973 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1974 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1975 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1976 EVEX_V512, EVEX_CD8<32, CD8VF>;
1977 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1978 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1979 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1980 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1981 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1982 EVEX_V512, EVEX_CD8<32, CD8VF>;
1983 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1984 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1985 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1986 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1987 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1988 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1989 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1990 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1991 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1993 //===----------------------------------------------------------------------===//
1994 // AVX-512 FP arithmetic
1995 //===----------------------------------------------------------------------===//
1997 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1999 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2000 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2001 EVEX_CD8<32, CD8VT1>;
2002 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2003 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2004 EVEX_CD8<64, CD8VT1>;
2007 let isCommutable = 1 in {
2008 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2009 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2010 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2011 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2013 let isCommutable = 0 in {
2014 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2015 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2018 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2019 RegisterClass RC, ValueType vt,
2020 X86MemOperand x86memop, PatFrag mem_frag,
2021 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2023 Domain d, OpndItins itins, bit commutable> {
2024 let isCommutable = commutable in
2025 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2026 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2027 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2029 let mayLoad = 1 in {
2030 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2031 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2032 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2033 itins.rm, d>, EVEX_4V;
2034 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2035 (ins RC:$src1, x86scalar_mop:$src2),
2036 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2037 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2038 [(set RC:$dst, (OpNode RC:$src1,
2039 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2040 itins.rm, d>, EVEX_4V, EVEX_B;
2044 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
2045 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2046 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2048 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
2049 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2050 SSE_ALU_ITINS_P.d, 1>,
2051 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2053 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2054 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2055 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2056 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2057 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2058 SSE_ALU_ITINS_P.d, 1>,
2059 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2061 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2062 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2063 SSE_ALU_ITINS_P.s, 1>,
2064 EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2065 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2066 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2067 SSE_ALU_ITINS_P.s, 1>,
2068 EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2070 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2071 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2072 SSE_ALU_ITINS_P.d, 1>,
2073 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2074 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2075 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2076 SSE_ALU_ITINS_P.d, 1>,
2077 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2079 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2080 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2081 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2082 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2083 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2084 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2086 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2087 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2088 SSE_ALU_ITINS_P.d, 0>,
2089 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2090 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2091 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2092 SSE_ALU_ITINS_P.d, 0>,
2093 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2095 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2096 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2097 (i16 -1), FROUND_CURRENT)),
2098 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2100 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2101 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2102 (i8 -1), FROUND_CURRENT)),
2103 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2105 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2106 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2107 (i16 -1), FROUND_CURRENT)),
2108 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2110 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2111 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2112 (i8 -1), FROUND_CURRENT)),
2113 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2114 //===----------------------------------------------------------------------===//
2115 // AVX-512 VPTESTM instructions
2116 //===----------------------------------------------------------------------===//
2118 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2119 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2120 SDNode OpNode, ValueType vt> {
2121 def rr : AVX5128I<opc, MRMSrcReg,
2122 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2123 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2124 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2125 def rm : AVX5128I<opc, MRMSrcMem,
2126 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2127 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2128 [(set KRC:$dst, (OpNode (vt RC:$src1),
2129 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2132 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2133 memopv16i32, X86testm, v16i32>, EVEX_V512,
2134 EVEX_CD8<32, CD8VF>;
2135 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2136 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2137 EVEX_CD8<64, CD8VF>;
2139 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2140 (v16i32 VR512:$src2), (i16 -1))),
2141 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2143 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2144 (v8i64 VR512:$src2), (i8 -1))),
2145 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR8)>;
2146 //===----------------------------------------------------------------------===//
2147 // AVX-512 Shift instructions
2148 //===----------------------------------------------------------------------===//
2149 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2150 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2151 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2152 RegisterClass KRC> {
2153 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2154 (ins RC:$src1, i8imm:$src2),
2155 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2156 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2157 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2158 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2159 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2160 !strconcat(OpcodeStr,
2161 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2162 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2163 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2164 (ins x86memop:$src1, i8imm:$src2),
2165 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2166 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2167 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2168 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2169 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2170 !strconcat(OpcodeStr,
2171 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2172 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2175 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2176 RegisterClass RC, ValueType vt, ValueType SrcVT,
2177 PatFrag bc_frag, RegisterClass KRC> {
2178 // src2 is always 128-bit
2179 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2180 (ins RC:$src1, VR128X:$src2),
2181 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2182 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2183 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2184 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2185 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2186 !strconcat(OpcodeStr,
2187 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2188 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2189 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2190 (ins RC:$src1, i128mem:$src2),
2191 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2192 [(set RC:$dst, (vt (OpNode RC:$src1,
2193 (bc_frag (memopv2i64 addr:$src2)))))],
2194 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2195 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2196 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2197 !strconcat(OpcodeStr,
2198 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2199 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2202 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2203 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2204 EVEX_V512, EVEX_CD8<32, CD8VF>;
2205 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2206 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2207 EVEX_CD8<32, CD8VQ>;
2209 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2210 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2211 EVEX_CD8<64, CD8VF>, VEX_W;
2212 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2213 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2214 EVEX_CD8<64, CD8VQ>, VEX_W;
2216 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2217 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2218 EVEX_CD8<32, CD8VF>;
2219 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2220 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2221 EVEX_CD8<32, CD8VQ>;
2223 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2224 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2225 EVEX_CD8<64, CD8VF>, VEX_W;
2226 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2227 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2228 EVEX_CD8<64, CD8VQ>, VEX_W;
2230 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2231 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2232 EVEX_V512, EVEX_CD8<32, CD8VF>;
2233 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2234 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2235 EVEX_CD8<32, CD8VQ>;
2237 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2238 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2239 EVEX_CD8<64, CD8VF>, VEX_W;
2240 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2241 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2242 EVEX_CD8<64, CD8VQ>, VEX_W;
2244 //===-------------------------------------------------------------------===//
2245 // Variable Bit Shifts
2246 //===-------------------------------------------------------------------===//
2247 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2248 RegisterClass RC, ValueType vt,
2249 X86MemOperand x86memop, PatFrag mem_frag> {
2250 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2251 (ins RC:$src1, RC:$src2),
2252 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2254 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2256 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2257 (ins RC:$src1, x86memop:$src2),
2258 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2260 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2264 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2265 i512mem, memopv16i32>, EVEX_V512,
2266 EVEX_CD8<32, CD8VF>;
2267 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2268 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2269 EVEX_CD8<64, CD8VF>;
2270 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2271 i512mem, memopv16i32>, EVEX_V512,
2272 EVEX_CD8<32, CD8VF>;
2273 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2274 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2275 EVEX_CD8<64, CD8VF>;
2276 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2277 i512mem, memopv16i32>, EVEX_V512,
2278 EVEX_CD8<32, CD8VF>;
2279 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2280 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2281 EVEX_CD8<64, CD8VF>;
2283 //===----------------------------------------------------------------------===//
2284 // AVX-512 - MOVDDUP
2285 //===----------------------------------------------------------------------===//
2287 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2288 X86MemOperand x86memop, PatFrag memop_frag> {
2289 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2290 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2291 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2292 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2293 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2295 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2298 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2299 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2300 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2301 (VMOVDDUPZrm addr:$src)>;
2303 //===---------------------------------------------------------------------===//
2304 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2305 //===---------------------------------------------------------------------===//
2306 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2307 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2308 X86MemOperand x86memop> {
2309 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2310 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2311 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2313 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2314 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2315 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2318 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2319 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2320 EVEX_CD8<32, CD8VF>;
2321 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2322 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2323 EVEX_CD8<32, CD8VF>;
2325 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2326 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2327 (VMOVSHDUPZrm addr:$src)>;
2328 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2329 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2330 (VMOVSLDUPZrm addr:$src)>;
2332 //===----------------------------------------------------------------------===//
2333 // Move Low to High and High to Low packed FP Instructions
2334 //===----------------------------------------------------------------------===//
2335 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2336 (ins VR128X:$src1, VR128X:$src2),
2337 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2338 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2339 IIC_SSE_MOV_LH>, EVEX_4V;
2340 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2341 (ins VR128X:$src1, VR128X:$src2),
2342 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2343 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2344 IIC_SSE_MOV_LH>, EVEX_4V;
2346 let Predicates = [HasAVX512] in {
2348 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2349 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2350 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2351 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2354 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2355 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2358 //===----------------------------------------------------------------------===//
2359 // FMA - Fused Multiply Operations
2361 let Constraints = "$src1 = $dst" in {
2362 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2363 RegisterClass RC, X86MemOperand x86memop,
2364 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2365 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2366 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2367 (ins RC:$src1, RC:$src2, RC:$src3),
2368 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2369 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2372 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2373 (ins RC:$src1, RC:$src2, x86memop:$src3),
2374 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2375 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2376 (mem_frag addr:$src3))))]>;
2377 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2378 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2379 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2380 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2381 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2382 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2384 } // Constraints = "$src1 = $dst"
2386 let ExeDomain = SSEPackedSingle in {
2387 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2388 memopv16f32, f32mem, loadf32, "{1to16}",
2389 X86Fmadd, v16f32>, EVEX_V512,
2390 EVEX_CD8<32, CD8VF>;
2391 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2392 memopv16f32, f32mem, loadf32, "{1to16}",
2393 X86Fmsub, v16f32>, EVEX_V512,
2394 EVEX_CD8<32, CD8VF>;
2395 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2396 memopv16f32, f32mem, loadf32, "{1to16}",
2397 X86Fmaddsub, v16f32>,
2398 EVEX_V512, EVEX_CD8<32, CD8VF>;
2399 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2400 memopv16f32, f32mem, loadf32, "{1to16}",
2401 X86Fmsubadd, v16f32>,
2402 EVEX_V512, EVEX_CD8<32, CD8VF>;
2403 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2404 memopv16f32, f32mem, loadf32, "{1to16}",
2405 X86Fnmadd, v16f32>, EVEX_V512,
2406 EVEX_CD8<32, CD8VF>;
2407 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2408 memopv16f32, f32mem, loadf32, "{1to16}",
2409 X86Fnmsub, v16f32>, EVEX_V512,
2410 EVEX_CD8<32, CD8VF>;
2412 let ExeDomain = SSEPackedDouble in {
2413 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2414 memopv8f64, f64mem, loadf64, "{1to8}",
2415 X86Fmadd, v8f64>, EVEX_V512,
2416 VEX_W, EVEX_CD8<64, CD8VF>;
2417 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2418 memopv8f64, f64mem, loadf64, "{1to8}",
2419 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2420 EVEX_CD8<64, CD8VF>;
2421 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2422 memopv8f64, f64mem, loadf64, "{1to8}",
2423 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2424 EVEX_CD8<64, CD8VF>;
2425 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2426 memopv8f64, f64mem, loadf64, "{1to8}",
2427 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2428 EVEX_CD8<64, CD8VF>;
2429 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2430 memopv8f64, f64mem, loadf64, "{1to8}",
2431 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2432 EVEX_CD8<64, CD8VF>;
2433 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2434 memopv8f64, f64mem, loadf64, "{1to8}",
2435 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2436 EVEX_CD8<64, CD8VF>;
2439 let Constraints = "$src1 = $dst" in {
2440 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2441 RegisterClass RC, X86MemOperand x86memop,
2442 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2443 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2445 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2446 (ins RC:$src1, RC:$src3, x86memop:$src2),
2447 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2448 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2449 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2450 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2451 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2452 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2453 [(set RC:$dst, (OpNode RC:$src1,
2454 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2456 } // Constraints = "$src1 = $dst"
2459 let ExeDomain = SSEPackedSingle in {
2460 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2461 memopv16f32, f32mem, loadf32, "{1to16}",
2462 X86Fmadd, v16f32>, EVEX_V512,
2463 EVEX_CD8<32, CD8VF>;
2464 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2465 memopv16f32, f32mem, loadf32, "{1to16}",
2466 X86Fmsub, v16f32>, EVEX_V512,
2467 EVEX_CD8<32, CD8VF>;
2468 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2469 memopv16f32, f32mem, loadf32, "{1to16}",
2470 X86Fmaddsub, v16f32>,
2471 EVEX_V512, EVEX_CD8<32, CD8VF>;
2472 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2473 memopv16f32, f32mem, loadf32, "{1to16}",
2474 X86Fmsubadd, v16f32>,
2475 EVEX_V512, EVEX_CD8<32, CD8VF>;
2476 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2477 memopv16f32, f32mem, loadf32, "{1to16}",
2478 X86Fnmadd, v16f32>, EVEX_V512,
2479 EVEX_CD8<32, CD8VF>;
2480 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2481 memopv16f32, f32mem, loadf32, "{1to16}",
2482 X86Fnmsub, v16f32>, EVEX_V512,
2483 EVEX_CD8<32, CD8VF>;
2485 let ExeDomain = SSEPackedDouble in {
2486 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2487 memopv8f64, f64mem, loadf64, "{1to8}",
2488 X86Fmadd, v8f64>, EVEX_V512,
2489 VEX_W, EVEX_CD8<64, CD8VF>;
2490 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2491 memopv8f64, f64mem, loadf64, "{1to8}",
2492 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2493 EVEX_CD8<64, CD8VF>;
2494 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2495 memopv8f64, f64mem, loadf64, "{1to8}",
2496 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2497 EVEX_CD8<64, CD8VF>;
2498 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2499 memopv8f64, f64mem, loadf64, "{1to8}",
2500 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2501 EVEX_CD8<64, CD8VF>;
2502 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2503 memopv8f64, f64mem, loadf64, "{1to8}",
2504 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2505 EVEX_CD8<64, CD8VF>;
2506 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2507 memopv8f64, f64mem, loadf64, "{1to8}",
2508 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2509 EVEX_CD8<64, CD8VF>;
2513 let Constraints = "$src1 = $dst" in {
2514 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2515 RegisterClass RC, ValueType OpVT,
2516 X86MemOperand x86memop, Operand memop,
2518 let isCommutable = 1 in
2519 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2520 (ins RC:$src1, RC:$src2, RC:$src3),
2521 !strconcat(OpcodeStr,
2522 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2524 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2526 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2527 (ins RC:$src1, RC:$src2, f128mem:$src3),
2528 !strconcat(OpcodeStr,
2529 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2531 (OpVT (OpNode RC:$src2, RC:$src1,
2532 (mem_frag addr:$src3))))]>;
2535 } // Constraints = "$src1 = $dst"
2537 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2538 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2539 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2540 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2541 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2542 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2543 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2544 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2545 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2546 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2547 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2548 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2549 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2550 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2551 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2552 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2554 //===----------------------------------------------------------------------===//
2555 // AVX-512 Scalar convert from sign integer to float/double
2556 //===----------------------------------------------------------------------===//
2558 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2559 X86MemOperand x86memop, string asm> {
2560 let hasSideEffects = 0 in {
2561 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2562 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2565 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2566 (ins DstRC:$src1, x86memop:$src),
2567 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2569 } // hasSideEffects = 0
2571 let Predicates = [HasAVX512] in {
2572 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2573 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2574 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2575 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2576 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2577 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2578 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2579 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2581 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2582 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2583 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2584 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2585 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2586 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2587 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2588 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2590 def : Pat<(f32 (sint_to_fp GR32:$src)),
2591 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2592 def : Pat<(f32 (sint_to_fp GR64:$src)),
2593 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2594 def : Pat<(f64 (sint_to_fp GR32:$src)),
2595 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2596 def : Pat<(f64 (sint_to_fp GR64:$src)),
2597 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2599 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2600 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2601 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2602 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2603 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2604 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2605 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2606 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2608 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2609 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2610 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2611 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2612 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2613 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2614 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2615 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2617 def : Pat<(f32 (uint_to_fp GR32:$src)),
2618 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2619 def : Pat<(f32 (uint_to_fp GR64:$src)),
2620 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2621 def : Pat<(f64 (uint_to_fp GR32:$src)),
2622 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2623 def : Pat<(f64 (uint_to_fp GR64:$src)),
2624 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2627 //===----------------------------------------------------------------------===//
2628 // AVX-512 Scalar convert from float/double to integer
2629 //===----------------------------------------------------------------------===//
2630 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2631 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2633 let hasSideEffects = 0 in {
2634 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2635 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2636 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2637 Requires<[HasAVX512]>;
2639 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2640 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2641 Requires<[HasAVX512]>;
2642 } // hasSideEffects = 0
2644 let Predicates = [HasAVX512] in {
2645 // Convert float/double to signed/unsigned int 32/64
2646 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2647 ssmem, sse_load_f32, "cvtss2si">,
2648 XS, EVEX_CD8<32, CD8VT1>;
2649 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2650 ssmem, sse_load_f32, "cvtss2si">,
2651 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2652 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2653 ssmem, sse_load_f32, "cvtss2usi">,
2654 XS, EVEX_CD8<32, CD8VT1>;
2655 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2656 int_x86_avx512_cvtss2usi64, ssmem,
2657 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2658 EVEX_CD8<32, CD8VT1>;
2659 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2660 sdmem, sse_load_f64, "cvtsd2si">,
2661 XD, EVEX_CD8<64, CD8VT1>;
2662 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2663 sdmem, sse_load_f64, "cvtsd2si">,
2664 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2665 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2666 sdmem, sse_load_f64, "cvtsd2usi">,
2667 XD, EVEX_CD8<64, CD8VT1>;
2668 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2669 int_x86_avx512_cvtsd2usi64, sdmem,
2670 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2671 EVEX_CD8<64, CD8VT1>;
2673 let isCodeGenOnly = 1 in {
2674 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2675 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2676 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2677 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2678 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2679 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2680 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2681 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2682 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2683 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2684 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2685 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2687 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2688 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2689 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2690 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2691 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2692 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2693 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2694 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2695 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2696 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2697 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2698 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2699 } // isCodeGenOnly = 1
2701 // Convert float/double to signed/unsigned int 32/64 with truncation
2702 let isCodeGenOnly = 1 in {
2703 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2704 ssmem, sse_load_f32, "cvttss2si">,
2705 XS, EVEX_CD8<32, CD8VT1>;
2706 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2707 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2708 "cvttss2si">, XS, VEX_W,
2709 EVEX_CD8<32, CD8VT1>;
2710 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2711 sdmem, sse_load_f64, "cvttsd2si">, XD,
2712 EVEX_CD8<64, CD8VT1>;
2713 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2714 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2715 "cvttsd2si">, XD, VEX_W,
2716 EVEX_CD8<64, CD8VT1>;
2717 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2718 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2719 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2720 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2721 int_x86_avx512_cvttss2usi64, ssmem,
2722 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2723 EVEX_CD8<32, CD8VT1>;
2724 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2725 int_x86_avx512_cvttsd2usi,
2726 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2727 EVEX_CD8<64, CD8VT1>;
2728 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2729 int_x86_avx512_cvttsd2usi64, sdmem,
2730 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2731 EVEX_CD8<64, CD8VT1>;
2732 } // isCodeGenOnly = 1
2734 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2735 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2737 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2738 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2739 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2740 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2741 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2742 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2745 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2746 loadf32, "cvttss2si">, XS,
2747 EVEX_CD8<32, CD8VT1>;
2748 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2749 loadf32, "cvttss2usi">, XS,
2750 EVEX_CD8<32, CD8VT1>;
2751 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2752 loadf32, "cvttss2si">, XS, VEX_W,
2753 EVEX_CD8<32, CD8VT1>;
2754 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2755 loadf32, "cvttss2usi">, XS, VEX_W,
2756 EVEX_CD8<32, CD8VT1>;
2757 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2758 loadf64, "cvttsd2si">, XD,
2759 EVEX_CD8<64, CD8VT1>;
2760 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2761 loadf64, "cvttsd2usi">, XD,
2762 EVEX_CD8<64, CD8VT1>;
2763 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2764 loadf64, "cvttsd2si">, XD, VEX_W,
2765 EVEX_CD8<64, CD8VT1>;
2766 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2767 loadf64, "cvttsd2usi">, XD, VEX_W,
2768 EVEX_CD8<64, CD8VT1>;
2770 //===----------------------------------------------------------------------===//
2771 // AVX-512 Convert form float to double and back
2772 //===----------------------------------------------------------------------===//
2773 let hasSideEffects = 0 in {
2774 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2775 (ins FR32X:$src1, FR32X:$src2),
2776 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2777 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2779 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2780 (ins FR32X:$src1, f32mem:$src2),
2781 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2782 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2783 EVEX_CD8<32, CD8VT1>;
2785 // Convert scalar double to scalar single
2786 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2787 (ins FR64X:$src1, FR64X:$src2),
2788 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2789 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2791 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2792 (ins FR64X:$src1, f64mem:$src2),
2793 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2794 []>, EVEX_4V, VEX_LIG, VEX_W,
2795 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2798 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2799 Requires<[HasAVX512]>;
2800 def : Pat<(fextend (loadf32 addr:$src)),
2801 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2803 def : Pat<(extloadf32 addr:$src),
2804 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2805 Requires<[HasAVX512, OptForSize]>;
2807 def : Pat<(extloadf32 addr:$src),
2808 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2809 Requires<[HasAVX512, OptForSpeed]>;
2811 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2812 Requires<[HasAVX512]>;
2814 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2815 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2816 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2818 let hasSideEffects = 0 in {
2819 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2820 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2822 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2823 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2824 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2825 [], d>, EVEX, EVEX_B, EVEX_RC;
2827 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2828 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2830 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2831 } // hasSideEffects = 0
2834 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2835 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2836 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2838 let hasSideEffects = 0 in {
2839 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2840 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2842 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2844 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2845 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2847 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2848 } // hasSideEffects = 0
2851 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2852 memopv8f64, f512mem, v8f32, v8f64,
2853 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
2854 EVEX_CD8<64, CD8VF>;
2856 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2857 memopv4f64, f256mem, v8f64, v8f32,
2858 SSEPackedDouble>, EVEX_V512, TB,
2859 EVEX_CD8<32, CD8VH>;
2860 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2861 (VCVTPS2PDZrm addr:$src)>;
2863 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2864 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2865 (VCVTPD2PSZrr VR512:$src)>;
2867 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2868 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2869 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2871 //===----------------------------------------------------------------------===//
2872 // AVX-512 Vector convert from sign integer to float/double
2873 //===----------------------------------------------------------------------===//
2875 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2876 memopv8i64, i512mem, v16f32, v16i32,
2877 SSEPackedSingle>, EVEX_V512, TB,
2878 EVEX_CD8<32, CD8VF>;
2880 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2881 memopv4i64, i256mem, v8f64, v8i32,
2882 SSEPackedDouble>, EVEX_V512, XS,
2883 EVEX_CD8<32, CD8VH>;
2885 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2886 memopv16f32, f512mem, v16i32, v16f32,
2887 SSEPackedSingle>, EVEX_V512, XS,
2888 EVEX_CD8<32, CD8VF>;
2890 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2891 memopv8f64, f512mem, v8i32, v8f64,
2892 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
2893 EVEX_CD8<64, CD8VF>;
2895 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2896 memopv16f32, f512mem, v16i32, v16f32,
2897 SSEPackedSingle>, EVEX_V512, TB,
2898 EVEX_CD8<32, CD8VF>;
2900 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2901 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2902 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2903 (VCVTTPS2UDQZrr VR512:$src)>;
2905 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2906 memopv8f64, f512mem, v8i32, v8f64,
2907 SSEPackedDouble>, EVEX_V512, TB, VEX_W,
2908 EVEX_CD8<64, CD8VF>;
2910 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2911 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2912 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2913 (VCVTTPD2UDQZrr VR512:$src)>;
2915 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2916 memopv4i64, f256mem, v8f64, v8i32,
2917 SSEPackedDouble>, EVEX_V512, XS,
2918 EVEX_CD8<32, CD8VH>;
2920 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2921 memopv16i32, f512mem, v16f32, v16i32,
2922 SSEPackedSingle>, EVEX_V512, XD,
2923 EVEX_CD8<32, CD8VF>;
2925 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2926 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2927 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2930 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2931 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2932 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2933 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2934 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2935 (VCVTDQ2PDZrr VR256X:$src)>;
2936 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2937 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2938 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2939 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2940 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2941 (VCVTUDQ2PDZrr VR256X:$src)>;
2943 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2944 RegisterClass DstRC, PatFrag mem_frag,
2945 X86MemOperand x86memop, Domain d> {
2946 let hasSideEffects = 0 in {
2947 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2948 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2950 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2951 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2952 [], d>, EVEX, EVEX_B, EVEX_RC;
2954 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2955 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2957 } // hasSideEffects = 0
2960 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
2961 memopv16f32, f512mem, SSEPackedSingle>, PD,
2962 EVEX_V512, EVEX_CD8<32, CD8VF>;
2963 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
2964 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
2965 EVEX_V512, EVEX_CD8<64, CD8VF>;
2967 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
2968 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2969 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
2971 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
2972 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2973 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
2975 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
2976 memopv16f32, f512mem, SSEPackedSingle>,
2977 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
2978 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
2979 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
2980 TB, EVEX_V512, EVEX_CD8<64, CD8VF>;
2982 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
2983 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
2984 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
2986 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
2987 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
2988 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
2990 let Predicates = [HasAVX512] in {
2991 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2992 (VCVTPD2PSZrm addr:$src)>;
2993 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2994 (VCVTPS2PDZrm addr:$src)>;
2997 //===----------------------------------------------------------------------===//
2998 // Half precision conversion instructions
2999 //===----------------------------------------------------------------------===//
3000 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
3001 X86MemOperand x86memop, Intrinsic Int> {
3002 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3003 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3004 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
3005 let hasSideEffects = 0, mayLoad = 1 in
3006 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3007 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3010 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
3011 X86MemOperand x86memop, Intrinsic Int> {
3012 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3013 (ins srcRC:$src1, i32i8imm:$src2),
3014 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3015 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
3016 let hasSideEffects = 0, mayStore = 1 in
3017 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3018 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3019 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3022 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
3023 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
3024 EVEX_CD8<32, CD8VH>;
3025 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
3026 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
3027 EVEX_CD8<32, CD8VH>;
3029 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3030 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3031 "ucomiss">, TB, EVEX, VEX_LIG,
3032 EVEX_CD8<32, CD8VT1>;
3033 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3034 "ucomisd">, PD, EVEX,
3035 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3036 let Pattern = []<dag> in {
3037 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3038 "comiss">, TB, EVEX, VEX_LIG,
3039 EVEX_CD8<32, CD8VT1>;
3040 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3041 "comisd">, PD, EVEX,
3042 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3044 let isCodeGenOnly = 1 in {
3045 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3046 load, "ucomiss">, TB, EVEX, VEX_LIG,
3047 EVEX_CD8<32, CD8VT1>;
3048 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3049 load, "ucomisd">, PD, EVEX,
3050 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3052 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3053 load, "comiss">, TB, EVEX, VEX_LIG,
3054 EVEX_CD8<32, CD8VT1>;
3055 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3056 load, "comisd">, PD, EVEX,
3057 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3061 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3062 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3063 X86MemOperand x86memop> {
3064 let hasSideEffects = 0 in {
3065 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3066 (ins RC:$src1, RC:$src2),
3067 !strconcat(OpcodeStr,
3068 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3069 let mayLoad = 1 in {
3070 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3071 (ins RC:$src1, x86memop:$src2),
3072 !strconcat(OpcodeStr,
3073 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3078 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3079 EVEX_CD8<32, CD8VT1>;
3080 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3081 VEX_W, EVEX_CD8<64, CD8VT1>;
3082 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3083 EVEX_CD8<32, CD8VT1>;
3084 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3085 VEX_W, EVEX_CD8<64, CD8VT1>;
3087 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3088 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3089 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3090 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3092 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3093 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3094 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3095 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3097 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3098 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3099 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3100 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3102 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3103 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3104 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3105 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3107 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3108 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3109 RegisterClass RC, X86MemOperand x86memop,
3110 PatFrag mem_frag, ValueType OpVt> {
3111 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3112 !strconcat(OpcodeStr,
3113 " \t{$src, $dst|$dst, $src}"),
3114 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3116 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3117 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3118 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3121 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3122 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3123 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3124 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3125 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3126 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3127 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3128 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3130 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3131 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3132 (VRSQRT14PSZr VR512:$src)>;
3133 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3134 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3135 (VRSQRT14PDZr VR512:$src)>;
3137 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3138 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3139 (VRCP14PSZr VR512:$src)>;
3140 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3141 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3142 (VRCP14PDZr VR512:$src)>;
3144 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3145 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3146 X86MemOperand x86memop> {
3147 let hasSideEffects = 0, Predicates = [HasERI] in {
3148 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3149 (ins RC:$src1, RC:$src2),
3150 !strconcat(OpcodeStr,
3151 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3152 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3153 (ins RC:$src1, RC:$src2),
3154 !strconcat(OpcodeStr,
3155 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3156 []>, EVEX_4V, EVEX_B;
3157 let mayLoad = 1 in {
3158 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3159 (ins RC:$src1, x86memop:$src2),
3160 !strconcat(OpcodeStr,
3161 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3166 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3167 EVEX_CD8<32, CD8VT1>;
3168 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3169 VEX_W, EVEX_CD8<64, CD8VT1>;
3170 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3171 EVEX_CD8<32, CD8VT1>;
3172 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3173 VEX_W, EVEX_CD8<64, CD8VT1>;
3175 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3176 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3178 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3179 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3181 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3182 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3184 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3185 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3187 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3188 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3190 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3191 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3193 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3194 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3196 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3197 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3199 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3200 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3201 RegisterClass RC, X86MemOperand x86memop> {
3202 let hasSideEffects = 0, Predicates = [HasERI] in {
3203 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3204 !strconcat(OpcodeStr,
3205 " \t{$src, $dst|$dst, $src}"),
3207 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3208 !strconcat(OpcodeStr,
3209 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3211 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3212 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3216 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3217 EVEX_V512, EVEX_CD8<32, CD8VF>;
3218 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3219 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3220 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3221 EVEX_V512, EVEX_CD8<32, CD8VF>;
3222 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3223 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3225 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3226 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3227 (VRSQRT28PSZrb VR512:$src)>;
3228 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3229 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3230 (VRSQRT28PDZrb VR512:$src)>;
3232 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3233 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3234 (VRCP28PSZrb VR512:$src)>;
3235 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3236 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3237 (VRCP28PDZrb VR512:$src)>;
3239 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3240 Intrinsic V16F32Int, Intrinsic V8F64Int,
3241 OpndItins itins_s, OpndItins itins_d> {
3242 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3243 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3244 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3248 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3249 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3251 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3252 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3254 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3255 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3256 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3260 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3261 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3262 [(set VR512:$dst, (OpNode
3263 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3264 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3266 let isCodeGenOnly = 1 in {
3267 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3268 !strconcat(OpcodeStr,
3269 "ps\t{$src, $dst|$dst, $src}"),
3270 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3272 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3273 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3275 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3276 EVEX_V512, EVEX_CD8<32, CD8VF>;
3277 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3278 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3279 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3280 EVEX, EVEX_V512, VEX_W;
3281 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3282 !strconcat(OpcodeStr,
3283 "pd\t{$src, $dst|$dst, $src}"),
3284 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3285 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3286 } // isCodeGenOnly = 1
3289 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3290 Intrinsic F32Int, Intrinsic F64Int,
3291 OpndItins itins_s, OpndItins itins_d> {
3292 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3293 (ins FR32X:$src1, FR32X:$src2),
3294 !strconcat(OpcodeStr,
3295 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3296 [], itins_s.rr>, XS, EVEX_4V;
3297 let isCodeGenOnly = 1 in
3298 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3299 (ins VR128X:$src1, VR128X:$src2),
3300 !strconcat(OpcodeStr,
3301 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3303 (F32Int VR128X:$src1, VR128X:$src2))],
3304 itins_s.rr>, XS, EVEX_4V;
3305 let mayLoad = 1 in {
3306 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3307 (ins FR32X:$src1, f32mem:$src2),
3308 !strconcat(OpcodeStr,
3309 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3310 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3311 let isCodeGenOnly = 1 in
3312 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3313 (ins VR128X:$src1, ssmem:$src2),
3314 !strconcat(OpcodeStr,
3315 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3317 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3318 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3320 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3321 (ins FR64X:$src1, FR64X:$src2),
3322 !strconcat(OpcodeStr,
3323 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3325 let isCodeGenOnly = 1 in
3326 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3327 (ins VR128X:$src1, VR128X:$src2),
3328 !strconcat(OpcodeStr,
3329 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3331 (F64Int VR128X:$src1, VR128X:$src2))],
3332 itins_s.rr>, XD, EVEX_4V, VEX_W;
3333 let mayLoad = 1 in {
3334 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3335 (ins FR64X:$src1, f64mem:$src2),
3336 !strconcat(OpcodeStr,
3337 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3338 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3339 let isCodeGenOnly = 1 in
3340 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3341 (ins VR128X:$src1, sdmem:$src2),
3342 !strconcat(OpcodeStr,
3343 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3345 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3346 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3351 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3352 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3353 SSE_SQRTSS, SSE_SQRTSD>,
3354 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3355 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3356 SSE_SQRTPS, SSE_SQRTPD>;
3358 let Predicates = [HasAVX512] in {
3359 def : Pat<(f32 (fsqrt FR32X:$src)),
3360 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3361 def : Pat<(f32 (fsqrt (load addr:$src))),
3362 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3363 Requires<[OptForSize]>;
3364 def : Pat<(f64 (fsqrt FR64X:$src)),
3365 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3366 def : Pat<(f64 (fsqrt (load addr:$src))),
3367 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3368 Requires<[OptForSize]>;
3370 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3371 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3372 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3373 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3374 Requires<[OptForSize]>;
3376 def : Pat<(f32 (X86frcp FR32X:$src)),
3377 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3378 def : Pat<(f32 (X86frcp (load addr:$src))),
3379 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3380 Requires<[OptForSize]>;
3382 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3383 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3384 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3386 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3387 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3389 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3390 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3391 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3393 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3394 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3398 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3399 X86MemOperand x86memop, RegisterClass RC,
3400 PatFrag mem_frag32, PatFrag mem_frag64,
3401 Intrinsic V4F32Int, Intrinsic V2F64Int,
3403 let ExeDomain = SSEPackedSingle in {
3404 // Intrinsic operation, reg.
3405 // Vector intrinsic operation, reg
3406 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3407 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3408 !strconcat(OpcodeStr,
3409 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3410 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3412 // Vector intrinsic operation, mem
3413 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3414 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3415 !strconcat(OpcodeStr,
3416 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3418 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3419 EVEX_CD8<32, VForm>;
3420 } // ExeDomain = SSEPackedSingle
3422 let ExeDomain = SSEPackedDouble in {
3423 // Vector intrinsic operation, reg
3424 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3425 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3426 !strconcat(OpcodeStr,
3427 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3428 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3430 // Vector intrinsic operation, mem
3431 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3432 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3433 !strconcat(OpcodeStr,
3434 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3436 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3437 EVEX_CD8<64, VForm>;
3438 } // ExeDomain = SSEPackedDouble
3441 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3445 let ExeDomain = GenericDomain in {
3447 let hasSideEffects = 0 in
3448 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3449 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3450 !strconcat(OpcodeStr,
3451 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3454 // Intrinsic operation, reg.
3455 let isCodeGenOnly = 1 in
3456 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3457 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3458 !strconcat(OpcodeStr,
3459 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3460 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3462 // Intrinsic operation, mem.
3463 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3464 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3465 !strconcat(OpcodeStr,
3466 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3467 [(set VR128X:$dst, (F32Int VR128X:$src1,
3468 sse_load_f32:$src2, imm:$src3))]>,
3469 EVEX_CD8<32, CD8VT1>;
3472 let hasSideEffects = 0 in
3473 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3474 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3475 !strconcat(OpcodeStr,
3476 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3479 // Intrinsic operation, reg.
3480 let isCodeGenOnly = 1 in
3481 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3482 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3483 !strconcat(OpcodeStr,
3484 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3485 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3488 // Intrinsic operation, mem.
3489 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3490 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3491 !strconcat(OpcodeStr,
3492 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3494 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3495 VEX_W, EVEX_CD8<64, CD8VT1>;
3496 } // ExeDomain = GenericDomain
3499 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3500 X86MemOperand x86memop, RegisterClass RC,
3501 PatFrag mem_frag, Domain d> {
3502 let ExeDomain = d in {
3503 // Intrinsic operation, reg.
3504 // Vector intrinsic operation, reg
3505 def r : AVX512AIi8<opc, MRMSrcReg,
3506 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3507 !strconcat(OpcodeStr,
3508 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3511 // Vector intrinsic operation, mem
3512 def m : AVX512AIi8<opc, MRMSrcMem,
3513 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3514 !strconcat(OpcodeStr,
3515 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3521 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3522 memopv16f32, SSEPackedSingle>, EVEX_V512,
3523 EVEX_CD8<32, CD8VF>;
3525 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3526 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3528 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3531 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3532 memopv8f64, SSEPackedDouble>, EVEX_V512,
3533 VEX_W, EVEX_CD8<64, CD8VF>;
3535 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3536 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3538 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3540 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3541 Operand x86memop, RegisterClass RC, Domain d> {
3542 let ExeDomain = d in {
3543 def r : AVX512AIi8<opc, MRMSrcReg,
3544 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3545 !strconcat(OpcodeStr,
3546 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3549 def m : AVX512AIi8<opc, MRMSrcMem,
3550 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3551 !strconcat(OpcodeStr,
3552 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3557 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3558 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3560 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3561 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3563 def : Pat<(ffloor FR32X:$src),
3564 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3565 def : Pat<(f64 (ffloor FR64X:$src)),
3566 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3567 def : Pat<(f32 (fnearbyint FR32X:$src)),
3568 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3569 def : Pat<(f64 (fnearbyint FR64X:$src)),
3570 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3571 def : Pat<(f32 (fceil FR32X:$src)),
3572 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3573 def : Pat<(f64 (fceil FR64X:$src)),
3574 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3575 def : Pat<(f32 (frint FR32X:$src)),
3576 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3577 def : Pat<(f64 (frint FR64X:$src)),
3578 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3579 def : Pat<(f32 (ftrunc FR32X:$src)),
3580 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3581 def : Pat<(f64 (ftrunc FR64X:$src)),
3582 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3584 def : Pat<(v16f32 (ffloor VR512:$src)),
3585 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3586 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3587 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3588 def : Pat<(v16f32 (fceil VR512:$src)),
3589 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3590 def : Pat<(v16f32 (frint VR512:$src)),
3591 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3592 def : Pat<(v16f32 (ftrunc VR512:$src)),
3593 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3595 def : Pat<(v8f64 (ffloor VR512:$src)),
3596 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3597 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3598 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3599 def : Pat<(v8f64 (fceil VR512:$src)),
3600 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3601 def : Pat<(v8f64 (frint VR512:$src)),
3602 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3603 def : Pat<(v8f64 (ftrunc VR512:$src)),
3604 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3606 //-------------------------------------------------
3607 // Integer truncate and extend operations
3608 //-------------------------------------------------
3610 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3611 RegisterClass dstRC, RegisterClass srcRC,
3612 RegisterClass KRC, X86MemOperand x86memop> {
3613 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3615 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3618 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3619 (ins KRC:$mask, srcRC:$src),
3620 !strconcat(OpcodeStr,
3621 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3624 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3625 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3628 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3629 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3630 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3631 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3632 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3633 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3634 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3635 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3636 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3637 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3638 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3639 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3640 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3641 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3642 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3643 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3644 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3645 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3646 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3647 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3648 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3649 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3650 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3651 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3652 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3653 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3654 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3655 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3656 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3657 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3659 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3660 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3661 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3662 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3663 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3665 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3666 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3667 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3668 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3669 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3670 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3671 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3672 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3675 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3676 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3677 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3679 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3681 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3682 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3683 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3684 (ins x86memop:$src),
3685 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3687 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3691 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3692 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3694 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3695 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3697 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3698 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3699 EVEX_CD8<16, CD8VH>;
3700 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3701 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3702 EVEX_CD8<16, CD8VQ>;
3703 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3704 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3705 EVEX_CD8<32, CD8VH>;
3707 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3708 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3710 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3711 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3713 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3714 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3715 EVEX_CD8<16, CD8VH>;
3716 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3717 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3718 EVEX_CD8<16, CD8VQ>;
3719 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3720 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3721 EVEX_CD8<32, CD8VH>;
3723 //===----------------------------------------------------------------------===//
3724 // GATHER - SCATTER Operations
3726 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3727 RegisterClass RC, X86MemOperand memop> {
3729 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3730 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3731 (ins RC:$src1, KRC:$mask, memop:$src2),
3732 !strconcat(OpcodeStr,
3733 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3736 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3737 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3738 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3739 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3741 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3742 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3743 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3744 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3746 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3747 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3748 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3749 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3751 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3752 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3753 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3754 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3756 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3757 RegisterClass RC, X86MemOperand memop> {
3758 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3759 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3760 (ins memop:$dst, KRC:$mask, RC:$src2),
3761 !strconcat(OpcodeStr,
3762 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3766 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3767 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3768 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3769 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3771 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3772 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3773 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3774 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3776 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3777 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3778 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3779 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3781 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3782 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3783 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3784 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3786 //===----------------------------------------------------------------------===//
3787 // VSHUFPS - VSHUFPD Operations
3789 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3790 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3792 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3793 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3794 !strconcat(OpcodeStr,
3795 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3796 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3797 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3798 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3799 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3800 (ins RC:$src1, RC:$src2, i8imm:$src3),
3801 !strconcat(OpcodeStr,
3802 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3803 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3804 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3805 EVEX_4V, Sched<[WriteShuffle]>;
3808 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3809 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
3810 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3811 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3813 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3814 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3815 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3816 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3817 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3819 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3820 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3821 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3822 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3823 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3825 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3826 X86MemOperand x86memop> {
3827 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3828 (ins RC:$src1, RC:$src2, i8imm:$src3),
3829 !strconcat(OpcodeStr,
3830 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3833 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3834 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3835 !strconcat(OpcodeStr,
3836 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3839 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3840 EVEX_V512, EVEX_CD8<32, CD8VF>;
3841 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3842 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3844 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3845 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3846 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3847 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3848 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3849 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3850 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3851 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3853 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3854 X86MemOperand x86memop> {
3855 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3856 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3858 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3859 (ins x86memop:$src),
3860 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3864 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3865 EVEX_CD8<32, CD8VF>;
3866 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3867 EVEX_CD8<64, CD8VF>;
3869 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3870 (v16i32 immAllZerosV), (i16 -1))),
3871 (VPABSDrr VR512:$src)>;
3872 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3873 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3874 (VPABSQrr VR512:$src)>;
3876 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3877 RegisterClass RC, RegisterClass KRC,
3878 X86MemOperand x86memop,
3879 X86MemOperand x86scalar_mop, string BrdcstStr> {
3880 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3882 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
3884 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3885 (ins x86memop:$src),
3886 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
3888 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3889 (ins x86scalar_mop:$src),
3890 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3891 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3893 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3894 (ins KRC:$mask, RC:$src),
3895 !strconcat(OpcodeStr,
3896 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3898 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3899 (ins KRC:$mask, x86memop:$src),
3900 !strconcat(OpcodeStr,
3901 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3903 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3904 (ins KRC:$mask, x86scalar_mop:$src),
3905 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3906 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3908 []>, EVEX, EVEX_KZ, EVEX_B;
3910 let Constraints = "$src1 = $dst" in {
3911 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3912 (ins RC:$src1, KRC:$mask, RC:$src2),
3913 !strconcat(OpcodeStr,
3914 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3916 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3917 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3918 !strconcat(OpcodeStr,
3919 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3921 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3922 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3923 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3924 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3925 []>, EVEX, EVEX_K, EVEX_B;
3929 let Predicates = [HasCDI] in {
3930 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3931 i512mem, i32mem, "{1to16}">,
3932 EVEX_V512, EVEX_CD8<32, CD8VF>;
3935 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3936 i512mem, i64mem, "{1to8}">,
3937 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3941 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3943 (VPCONFLICTDrrk VR512:$src1,
3944 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3946 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3948 (VPCONFLICTQrrk VR512:$src1,
3949 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;