1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
621 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
622 (ins KRC:$mask, RC:$src1, RC:$src2),
623 !strconcat(OpcodeStr,
624 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
625 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
626 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
629 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
630 (ins KRC:$mask, RC:$src1, x86memop:$src2),
631 !strconcat(OpcodeStr,
632 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
636 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
637 (ins KRC:$mask, RC:$src1, x86memop:$src2),
638 !strconcat(OpcodeStr,
639 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
640 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
641 (mem_frag addr:$src2)))]>,
646 let ExeDomain = SSEPackedSingle in
647 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
648 int_x86_avx512_mask_blend_ps_512,
649 VK16WM, VR512, f512mem,
650 memopv16f32, vselect, v16f32>,
651 EVEX_CD8<32, CD8VF>, EVEX_V512;
652 let ExeDomain = SSEPackedDouble in
653 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
654 int_x86_avx512_mask_blend_pd_512,
655 VK8WM, VR512, f512mem,
656 memopv8f64, vselect, v8f64>,
657 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
659 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
660 int_x86_avx512_mask_blend_d_512,
661 VK16WM, VR512, f512mem,
662 memopv16i32, vselect, v16i32>,
663 EVEX_CD8<32, CD8VF>, EVEX_V512;
665 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
666 int_x86_avx512_mask_blend_q_512,
667 VK8WM, VR512, f512mem,
668 memopv8i64, vselect, v8i64>,
669 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
671 let Predicates = [HasAVX512] in {
672 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
673 (v8f32 VR256X:$src2))),
675 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
676 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
677 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
679 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
680 (v8i32 VR256X:$src2))),
682 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
687 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
688 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
689 SDNode OpNode, ValueType vt> {
690 def rr : AVX512BI<opc, MRMSrcReg,
691 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
692 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
693 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
694 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
695 def rm : AVX512BI<opc, MRMSrcMem,
696 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
697 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
698 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
699 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
702 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
703 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
704 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
705 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
707 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
708 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
709 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
710 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
712 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
713 (COPY_TO_REGCLASS (VPCMPGTDZrr
714 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
715 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
717 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
718 (COPY_TO_REGCLASS (VPCMPEQDZrr
719 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
720 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
722 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
723 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
724 SDNode OpNode, ValueType vt, Operand CC, string asm,
726 def rri : AVX512AIi8<opc, MRMSrcReg,
727 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
728 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
729 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
730 def rmi : AVX512AIi8<opc, MRMSrcMem,
731 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
732 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
733 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
734 // Accept explicit immediate argument form instead of comparison code.
735 let neverHasSideEffects = 1 in {
736 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
737 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
738 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
739 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
740 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
741 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
745 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
746 X86cmpm, v16i32, AVXCC,
747 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
749 EVEX_V512, EVEX_CD8<32, CD8VF>;
750 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
751 X86cmpmu, v16i32, AVXCC,
752 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
753 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
754 EVEX_V512, EVEX_CD8<32, CD8VF>;
756 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
757 X86cmpm, v8i64, AVXCC,
758 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
759 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
760 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
761 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
762 X86cmpmu, v8i64, AVXCC,
763 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
764 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
765 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
767 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
768 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
769 X86MemOperand x86memop, Operand CC,
770 SDNode OpNode, ValueType vt, string asm,
771 string asm_alt, Domain d> {
772 def rri : AVX512PIi8<0xC2, MRMSrcReg,
773 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
774 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
775 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
776 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
778 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
780 // Accept explicit immediate argument form instead of comparison code.
781 let neverHasSideEffects = 1 in {
782 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
783 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
785 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
786 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
791 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
792 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
793 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
794 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
795 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
796 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
797 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
798 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
801 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
802 (COPY_TO_REGCLASS (VCMPPSZrri
803 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
804 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
806 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
807 (COPY_TO_REGCLASS (VPCMPDZrri
808 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
809 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
811 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
812 (COPY_TO_REGCLASS (VPCMPUDZrri
813 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
814 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
817 // Mask register copy, including
818 // - copy between mask registers
819 // - load/store mask registers
820 // - copy from GPR to mask register and vice versa
822 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
823 string OpcodeStr, RegisterClass KRC,
824 ValueType vt, X86MemOperand x86memop> {
825 let neverHasSideEffects = 1 in {
826 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
827 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
829 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
830 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
831 [(set KRC:$dst, (vt (load addr:$src)))]>;
833 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
834 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
838 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
840 RegisterClass KRC, RegisterClass GRC> {
841 let neverHasSideEffects = 1 in {
842 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
844 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
845 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
849 let Predicates = [HasAVX512] in {
850 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
852 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
856 let Predicates = [HasAVX512] in {
857 // GR16 from/to 16-bit mask
858 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
859 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
860 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
861 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
863 // Store kreg in memory
864 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
865 (KMOVWmk addr:$dst, VK16:$src)>;
867 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
868 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
870 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
871 let Predicates = [HasAVX512] in {
872 // GR from/to 8-bit mask without native support
873 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
875 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
877 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
879 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
883 // Mask unary operation
885 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
886 RegisterClass KRC, SDPatternOperator OpNode> {
887 let Predicates = [HasAVX512] in
888 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
889 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
890 [(set KRC:$dst, (OpNode KRC:$src))]>;
893 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
894 SDPatternOperator OpNode> {
895 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
899 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
901 multiclass avx512_mask_unop_int<string IntName, string InstName> {
902 let Predicates = [HasAVX512] in
903 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
905 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
906 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
908 defm : avx512_mask_unop_int<"knot", "KNOT">;
910 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
911 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
912 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
914 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
915 def : Pat<(not VK8:$src),
917 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
919 // Mask binary operation
920 // - KAND, KANDN, KOR, KXNOR, KXOR
921 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
922 RegisterClass KRC, SDPatternOperator OpNode> {
923 let Predicates = [HasAVX512] in
924 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
925 !strconcat(OpcodeStr,
926 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
927 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
930 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
931 SDPatternOperator OpNode> {
932 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
936 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
937 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
939 let isCommutable = 1 in {
940 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
941 let isCommutable = 0 in
942 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
943 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
944 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
945 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
948 multiclass avx512_mask_binop_int<string IntName, string InstName> {
949 let Predicates = [HasAVX512] in
950 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
951 (i16 GR16:$src1), (i16 GR16:$src2)),
952 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
953 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
954 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
957 defm : avx512_mask_binop_int<"kand", "KAND">;
958 defm : avx512_mask_binop_int<"kandn", "KANDN">;
959 defm : avx512_mask_binop_int<"kor", "KOR">;
960 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
961 defm : avx512_mask_binop_int<"kxor", "KXOR">;
963 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
964 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
965 let Predicates = [HasAVX512] in
966 def : Pat<(OpNode VK8:$src1, VK8:$src2),
968 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
969 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
972 defm : avx512_binop_pat<and, KANDWrr>;
973 defm : avx512_binop_pat<andn, KANDNWrr>;
974 defm : avx512_binop_pat<or, KORWrr>;
975 defm : avx512_binop_pat<xnor, KXNORWrr>;
976 defm : avx512_binop_pat<xor, KXORWrr>;
979 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
981 let Predicates = [HasAVX512] in
982 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
983 !strconcat(OpcodeStr,
984 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
987 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
988 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
989 VEX_4V, VEX_L, OpSize, TB;
992 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
994 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
995 let Predicates = [HasAVX512] in
996 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
997 (i16 GR16:$src1), (i16 GR16:$src2)),
998 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
999 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1000 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1002 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1005 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1007 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1008 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1009 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1010 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1013 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1014 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1018 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1019 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
1022 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1024 let Predicates = [HasAVX512] in
1025 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1026 !strconcat(OpcodeStr,
1027 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1028 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1031 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1033 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1034 VEX, OpSize, TA, VEX_W;
1037 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
1038 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
1040 // Mask setting all 0s or 1s
1041 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1042 let Predicates = [HasAVX512] in
1043 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1044 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1045 [(set KRC:$dst, (VT Val))]>;
1048 multiclass avx512_mask_setop_w<PatFrag Val> {
1049 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1050 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1053 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1054 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1056 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1057 let Predicates = [HasAVX512] in {
1058 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1059 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1061 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1062 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1064 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1065 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1067 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1068 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1070 //===----------------------------------------------------------------------===//
1071 // AVX-512 - Aligned and unaligned load and store
1074 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1075 X86MemOperand x86memop, PatFrag ld_frag,
1076 string asm, Domain d> {
1077 let neverHasSideEffects = 1 in
1078 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1079 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1081 let canFoldAsLoad = 1 in
1082 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1083 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1084 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1085 let Constraints = "$src1 = $dst" in {
1086 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1087 (ins RC:$src1, KRC:$mask, RC:$src2),
1089 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1091 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1092 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1094 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1095 [], d>, EVEX, EVEX_K;
1099 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1100 "vmovaps", SSEPackedSingle>,
1101 EVEX_V512, EVEX_CD8<32, CD8VF>;
1102 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1103 "vmovapd", SSEPackedDouble>,
1104 OpSize, EVEX_V512, VEX_W,
1105 EVEX_CD8<64, CD8VF>;
1106 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1107 "vmovups", SSEPackedSingle>,
1108 EVEX_V512, EVEX_CD8<32, CD8VF>;
1109 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1110 "vmovupd", SSEPackedDouble>,
1111 OpSize, EVEX_V512, VEX_W,
1112 EVEX_CD8<64, CD8VF>;
1113 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1114 "vmovaps\t{$src, $dst|$dst, $src}",
1115 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1116 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1117 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1118 "vmovapd\t{$src, $dst|$dst, $src}",
1119 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1120 SSEPackedDouble>, EVEX, EVEX_V512,
1121 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1122 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1123 "vmovups\t{$src, $dst|$dst, $src}",
1124 [(store (v16f32 VR512:$src), addr:$dst)],
1125 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1126 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1127 "vmovupd\t{$src, $dst|$dst, $src}",
1128 [(store (v8f64 VR512:$src), addr:$dst)],
1129 SSEPackedDouble>, EVEX, EVEX_V512,
1130 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1132 let neverHasSideEffects = 1 in {
1133 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1135 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1137 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1139 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1140 EVEX, EVEX_V512, VEX_W;
1141 let mayStore = 1 in {
1142 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1143 (ins i512mem:$dst, VR512:$src),
1144 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1145 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1146 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1147 (ins i512mem:$dst, VR512:$src),
1148 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1149 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1151 let mayLoad = 1 in {
1152 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1154 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1155 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1156 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1158 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1159 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1163 // 512-bit aligned load/store
1164 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1165 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1167 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1168 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1169 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1170 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1172 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1173 RegisterClass RC, RegisterClass KRC,
1174 PatFrag ld_frag, X86MemOperand x86memop> {
1175 let neverHasSideEffects = 1 in
1176 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1177 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1178 let canFoldAsLoad = 1 in
1179 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1180 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1181 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1183 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1184 (ins x86memop:$dst, VR512:$src),
1185 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1186 let Constraints = "$src1 = $dst" in {
1187 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1188 (ins RC:$src1, KRC:$mask, RC:$src2),
1190 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1192 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1193 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1195 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1200 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1201 memopv16i32, i512mem>,
1202 EVEX_V512, EVEX_CD8<32, CD8VF>;
1203 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1204 memopv8i64, i512mem>,
1205 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1207 // 512-bit unaligned load/store
1208 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1209 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1211 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1212 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1213 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1214 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1216 let AddedComplexity = 20 in {
1217 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1218 (v16f32 VR512:$src2))),
1219 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1220 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1221 (v8f64 VR512:$src2))),
1222 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1223 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1224 (v16i32 VR512:$src2))),
1225 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1226 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1227 (v8i64 VR512:$src2))),
1228 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1230 // Move Int Doubleword to Packed Double Int
1232 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1233 "vmovd\t{$src, $dst|$dst, $src}",
1235 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1237 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1238 "vmovd\t{$src, $dst|$dst, $src}",
1240 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1241 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1242 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1243 "vmovq\t{$src, $dst|$dst, $src}",
1245 (v2i64 (scalar_to_vector GR64:$src)))],
1246 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1247 let isCodeGenOnly = 1 in {
1248 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1249 "vmovq\t{$src, $dst|$dst, $src}",
1250 [(set FR64:$dst, (bitconvert GR64:$src))],
1251 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1252 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1253 "vmovq\t{$src, $dst|$dst, $src}",
1254 [(set GR64:$dst, (bitconvert FR64:$src))],
1255 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1257 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1258 "vmovq\t{$src, $dst|$dst, $src}",
1259 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1260 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1261 EVEX_CD8<64, CD8VT1>;
1263 // Move Int Doubleword to Single Scalar
1265 let isCodeGenOnly = 1 in {
1266 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1267 "vmovd\t{$src, $dst|$dst, $src}",
1268 [(set FR32X:$dst, (bitconvert GR32:$src))],
1269 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1271 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1272 "vmovd\t{$src, $dst|$dst, $src}",
1273 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1274 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1277 // Move Packed Doubleword Int to Packed Double Int
1279 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1280 "vmovd\t{$src, $dst|$dst, $src}",
1281 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1282 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1284 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1285 (ins i32mem:$dst, VR128X:$src),
1286 "vmovd\t{$src, $dst|$dst, $src}",
1287 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1288 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1289 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1291 // Move Packed Doubleword Int first element to Doubleword Int
1293 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1294 "vmovq\t{$src, $dst|$dst, $src}",
1295 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1297 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1298 Requires<[HasAVX512, In64BitMode]>;
1300 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1301 (ins i64mem:$dst, VR128X:$src),
1302 "vmovq\t{$src, $dst|$dst, $src}",
1303 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1304 addr:$dst)], IIC_SSE_MOVDQ>,
1305 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1306 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1308 // Move Scalar Single to Double Int
1310 let isCodeGenOnly = 1 in {
1311 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1313 "vmovd\t{$src, $dst|$dst, $src}",
1314 [(set GR32:$dst, (bitconvert FR32X:$src))],
1315 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1316 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1317 (ins i32mem:$dst, FR32X:$src),
1318 "vmovd\t{$src, $dst|$dst, $src}",
1319 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1320 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1323 // Move Quadword Int to Packed Quadword Int
1325 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1327 "vmovq\t{$src, $dst|$dst, $src}",
1329 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1330 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1332 //===----------------------------------------------------------------------===//
1333 // AVX-512 MOVSS, MOVSD
1334 //===----------------------------------------------------------------------===//
1336 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1337 SDNode OpNode, ValueType vt,
1338 X86MemOperand x86memop, PatFrag mem_pat> {
1339 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1340 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1341 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1342 (scalar_to_vector RC:$src2))))],
1343 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1344 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1345 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1346 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1348 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1349 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1350 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1354 let ExeDomain = SSEPackedSingle in
1355 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1356 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1358 let ExeDomain = SSEPackedDouble in
1359 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1360 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1363 // For the disassembler
1364 let isCodeGenOnly = 1 in {
1365 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1366 (ins VR128X:$src1, FR32X:$src2),
1367 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1369 XS, EVEX_4V, VEX_LIG;
1370 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1371 (ins VR128X:$src1, FR64X:$src2),
1372 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1374 XD, EVEX_4V, VEX_LIG, VEX_W;
1377 let Predicates = [HasAVX512] in {
1378 let AddedComplexity = 15 in {
1379 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1380 // MOVS{S,D} to the lower bits.
1381 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1382 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1383 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1384 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1385 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1386 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1387 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1388 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1390 // Move low f32 and clear high bits.
1391 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1392 (SUBREG_TO_REG (i32 0),
1393 (VMOVSSZrr (v4f32 (V_SET0)),
1394 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1395 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1396 (SUBREG_TO_REG (i32 0),
1397 (VMOVSSZrr (v4i32 (V_SET0)),
1398 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1401 let AddedComplexity = 20 in {
1402 // MOVSSrm zeros the high parts of the register; represent this
1403 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1404 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1405 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1406 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1407 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1408 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1409 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1411 // MOVSDrm zeros the high parts of the register; represent this
1412 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1413 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1414 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1415 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1416 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1417 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1418 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1419 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1420 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1421 def : Pat<(v2f64 (X86vzload addr:$src)),
1422 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1424 // Represent the same patterns above but in the form they appear for
1426 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1427 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1428 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1429 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1430 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1431 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1432 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1433 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1434 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1436 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1437 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1438 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1439 FR32X:$src)), sub_xmm)>;
1440 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1441 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1442 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1443 FR64X:$src)), sub_xmm)>;
1444 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1445 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1446 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1448 // Move low f64 and clear high bits.
1449 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1450 (SUBREG_TO_REG (i32 0),
1451 (VMOVSDZrr (v2f64 (V_SET0)),
1452 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1454 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1455 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1456 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1458 // Extract and store.
1459 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1461 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1462 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1464 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1466 // Shuffle with VMOVSS
1467 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1468 (VMOVSSZrr (v4i32 VR128X:$src1),
1469 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1470 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1471 (VMOVSSZrr (v4f32 VR128X:$src1),
1472 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1475 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1476 (SUBREG_TO_REG (i32 0),
1477 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1478 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1480 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1481 (SUBREG_TO_REG (i32 0),
1482 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1483 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1486 // Shuffle with VMOVSD
1487 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1488 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1489 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1490 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1491 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1492 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1493 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1494 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1497 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1498 (SUBREG_TO_REG (i32 0),
1499 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1500 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1502 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1503 (SUBREG_TO_REG (i32 0),
1504 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1505 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1508 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1509 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1510 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1511 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1512 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1513 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1514 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1515 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1518 let AddedComplexity = 15 in
1519 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1521 "vmovq\t{$src, $dst|$dst, $src}",
1522 [(set VR128X:$dst, (v2i64 (X86vzmovl
1523 (v2i64 VR128X:$src))))],
1524 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1526 let AddedComplexity = 20 in
1527 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1529 "vmovq\t{$src, $dst|$dst, $src}",
1530 [(set VR128X:$dst, (v2i64 (X86vzmovl
1531 (loadv2i64 addr:$src))))],
1532 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1533 EVEX_CD8<8, CD8VT8>;
1535 let Predicates = [HasAVX512] in {
1536 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1537 let AddedComplexity = 20 in {
1538 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1539 (VMOVDI2PDIZrm addr:$src)>;
1540 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1541 (VMOV64toPQIZrr GR64:$src)>;
1542 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1543 (VMOVDI2PDIZrr GR32:$src)>;
1545 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1546 (VMOVDI2PDIZrm addr:$src)>;
1547 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1548 (VMOVDI2PDIZrm addr:$src)>;
1549 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1550 (VMOVZPQILo2PQIZrm addr:$src)>;
1551 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1552 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1553 def : Pat<(v2i64 (X86vzload addr:$src)),
1554 (VMOVZPQILo2PQIZrm addr:$src)>;
1557 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1558 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1559 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1560 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1561 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1562 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1563 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1566 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1567 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1569 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1570 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1572 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1573 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1575 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1576 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1578 //===----------------------------------------------------------------------===//
1579 // AVX-512 - Integer arithmetic
1581 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1582 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1583 X86MemOperand x86memop, PatFrag scalar_mfrag,
1584 X86MemOperand x86scalar_mop, string BrdcstStr,
1585 OpndItins itins, bit IsCommutable = 0> {
1586 let isCommutable = IsCommutable in
1587 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1588 (ins RC:$src1, RC:$src2),
1589 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1590 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1592 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1593 (ins RC:$src1, x86memop:$src2),
1594 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1595 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1597 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1598 (ins RC:$src1, x86scalar_mop:$src2),
1599 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1600 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1601 [(set RC:$dst, (OpNode RC:$src1,
1602 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1603 itins.rm>, EVEX_4V, EVEX_B;
1605 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1606 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1607 PatFrag memop_frag, X86MemOperand x86memop,
1609 bit IsCommutable = 0> {
1610 let isCommutable = IsCommutable in
1611 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1612 (ins RC:$src1, RC:$src2),
1613 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1614 []>, EVEX_4V, VEX_W;
1615 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1616 (ins RC:$src1, x86memop:$src2),
1617 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1618 []>, EVEX_4V, VEX_W;
1621 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1622 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1623 EVEX_V512, EVEX_CD8<32, CD8VF>;
1625 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1626 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1627 EVEX_V512, EVEX_CD8<32, CD8VF>;
1629 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1630 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1631 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1633 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1634 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1635 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1637 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1638 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1639 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1641 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1642 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1643 EVEX_V512, EVEX_CD8<64, CD8VF>;
1645 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1646 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1647 EVEX_CD8<64, CD8VF>;
1649 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1650 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1652 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1653 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1654 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1655 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1656 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1657 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1659 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1660 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1661 EVEX_V512, EVEX_CD8<32, CD8VF>;
1662 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1663 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1664 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1666 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1667 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1668 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1669 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1670 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1671 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1673 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1674 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1675 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1676 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1677 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1678 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1680 //===----------------------------------------------------------------------===//
1681 // AVX-512 - Unpack Instructions
1682 //===----------------------------------------------------------------------===//
1684 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1685 PatFrag mem_frag, RegisterClass RC,
1686 X86MemOperand x86memop, string asm,
1688 def rr : AVX512PI<opc, MRMSrcReg,
1689 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1691 (vt (OpNode RC:$src1, RC:$src2)))],
1693 def rm : AVX512PI<opc, MRMSrcMem,
1694 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1696 (vt (OpNode RC:$src1,
1697 (bitconvert (mem_frag addr:$src2)))))],
1701 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1702 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1703 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1704 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1705 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1706 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1707 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1708 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1709 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1710 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1711 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1712 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1714 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1715 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1716 X86MemOperand x86memop> {
1717 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1718 (ins RC:$src1, RC:$src2),
1719 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1720 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1721 IIC_SSE_UNPCK>, EVEX_4V;
1722 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1723 (ins RC:$src1, x86memop:$src2),
1724 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1725 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1726 (bitconvert (memop_frag addr:$src2)))))],
1727 IIC_SSE_UNPCK>, EVEX_4V;
1729 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1730 VR512, memopv16i32, i512mem>, EVEX_V512,
1731 EVEX_CD8<32, CD8VF>;
1732 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1733 VR512, memopv8i64, i512mem>, EVEX_V512,
1734 VEX_W, EVEX_CD8<64, CD8VF>;
1735 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1736 VR512, memopv16i32, i512mem>, EVEX_V512,
1737 EVEX_CD8<32, CD8VF>;
1738 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1739 VR512, memopv8i64, i512mem>, EVEX_V512,
1740 VEX_W, EVEX_CD8<64, CD8VF>;
1741 //===----------------------------------------------------------------------===//
1745 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1746 SDNode OpNode, PatFrag mem_frag,
1747 X86MemOperand x86memop, ValueType OpVT> {
1748 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1749 (ins RC:$src1, i8imm:$src2),
1750 !strconcat(OpcodeStr,
1751 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1753 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1755 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1756 (ins x86memop:$src1, i8imm:$src2),
1757 !strconcat(OpcodeStr,
1758 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1760 (OpVT (OpNode (mem_frag addr:$src1),
1761 (i8 imm:$src2))))]>, EVEX;
1764 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1765 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1767 let ExeDomain = SSEPackedSingle in
1768 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1769 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1770 EVEX_CD8<32, CD8VF>;
1771 let ExeDomain = SSEPackedDouble in
1772 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1773 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1774 VEX_W, EVEX_CD8<32, CD8VF>;
1776 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1777 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1778 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1779 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1781 //===----------------------------------------------------------------------===//
1782 // AVX-512 Logical Instructions
1783 //===----------------------------------------------------------------------===//
1785 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1786 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1787 EVEX_V512, EVEX_CD8<32, CD8VF>;
1788 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1789 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1790 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1791 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1792 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1793 EVEX_V512, EVEX_CD8<32, CD8VF>;
1794 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1795 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1796 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1797 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1798 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1799 EVEX_V512, EVEX_CD8<32, CD8VF>;
1800 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1801 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1802 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1803 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1804 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1805 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1806 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1807 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1808 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1810 //===----------------------------------------------------------------------===//
1811 // AVX-512 FP arithmetic
1812 //===----------------------------------------------------------------------===//
1814 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1816 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1817 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1818 EVEX_CD8<32, CD8VT1>;
1819 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1820 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1821 EVEX_CD8<64, CD8VT1>;
1824 let isCommutable = 1 in {
1825 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1826 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1827 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1828 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1830 let isCommutable = 0 in {
1831 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1832 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1835 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1836 RegisterClass RC, ValueType vt,
1837 X86MemOperand x86memop, PatFrag mem_frag,
1838 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1840 Domain d, OpndItins itins, bit commutable> {
1841 let isCommutable = commutable in
1842 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1843 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1844 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1846 let mayLoad = 1 in {
1847 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1848 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1849 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1850 itins.rm, d>, EVEX_4V, TB;
1851 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1852 (ins RC:$src1, x86scalar_mop:$src2),
1853 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1854 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1855 [(set RC:$dst, (OpNode RC:$src1,
1856 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1857 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1861 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1862 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1863 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1865 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1866 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1867 SSE_ALU_ITINS_P.d, 1>,
1868 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1870 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1871 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1872 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1873 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1874 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1875 SSE_ALU_ITINS_P.d, 1>,
1876 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1878 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1879 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1880 SSE_ALU_ITINS_P.s, 1>,
1881 EVEX_V512, EVEX_CD8<32, CD8VF>;
1882 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1883 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1884 SSE_ALU_ITINS_P.s, 1>,
1885 EVEX_V512, EVEX_CD8<32, CD8VF>;
1887 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1888 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1889 SSE_ALU_ITINS_P.d, 1>,
1890 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1891 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1892 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1893 SSE_ALU_ITINS_P.d, 1>,
1894 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1896 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1897 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1898 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1899 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1900 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1901 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1903 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1904 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1905 SSE_ALU_ITINS_P.d, 0>,
1906 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1907 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1908 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1909 SSE_ALU_ITINS_P.d, 0>,
1910 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1912 //===----------------------------------------------------------------------===//
1913 // AVX-512 VPTESTM instructions
1914 //===----------------------------------------------------------------------===//
1916 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1917 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1918 SDNode OpNode, ValueType vt> {
1919 def rr : AVX5128I<opc, MRMSrcReg,
1920 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1921 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1922 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1923 def rm : AVX5128I<opc, MRMSrcMem,
1924 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1925 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1926 [(set KRC:$dst, (OpNode (vt RC:$src1),
1927 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1930 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1931 memopv16i32, X86testm, v16i32>, EVEX_V512,
1932 EVEX_CD8<32, CD8VF>;
1933 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1934 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1935 EVEX_CD8<64, CD8VF>;
1937 //===----------------------------------------------------------------------===//
1938 // AVX-512 Shift instructions
1939 //===----------------------------------------------------------------------===//
1940 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1941 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1942 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1943 RegisterClass KRC> {
1944 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1945 (ins RC:$src1, i8imm:$src2),
1946 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1947 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
1948 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1949 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1950 (ins KRC:$mask, RC:$src1, i8imm:$src2),
1951 !strconcat(OpcodeStr,
1952 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1953 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1954 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1955 (ins x86memop:$src1, i8imm:$src2),
1956 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1957 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
1958 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1959 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1960 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
1961 !strconcat(OpcodeStr,
1962 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1963 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1966 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1967 RegisterClass RC, ValueType vt, ValueType SrcVT,
1968 PatFrag bc_frag, RegisterClass KRC> {
1969 // src2 is always 128-bit
1970 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1971 (ins RC:$src1, VR128X:$src2),
1972 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1973 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1974 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1975 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1976 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1977 !strconcat(OpcodeStr,
1978 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1979 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1980 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1981 (ins RC:$src1, i128mem:$src2),
1982 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1983 [(set RC:$dst, (vt (OpNode RC:$src1,
1984 (bc_frag (memopv2i64 addr:$src2)))))],
1985 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1986 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1987 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1988 !strconcat(OpcodeStr,
1989 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1990 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1993 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1994 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1995 EVEX_V512, EVEX_CD8<32, CD8VF>;
1996 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1997 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1998 EVEX_CD8<32, CD8VQ>;
2000 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2001 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2002 EVEX_CD8<64, CD8VF>, VEX_W;
2003 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2004 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2005 EVEX_CD8<64, CD8VQ>, VEX_W;
2007 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2008 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2009 EVEX_CD8<32, CD8VF>;
2010 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2011 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2012 EVEX_CD8<32, CD8VQ>;
2014 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2015 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2016 EVEX_CD8<64, CD8VF>, VEX_W;
2017 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2018 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2019 EVEX_CD8<64, CD8VQ>, VEX_W;
2021 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2022 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2023 EVEX_V512, EVEX_CD8<32, CD8VF>;
2024 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2025 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2026 EVEX_CD8<32, CD8VQ>;
2028 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2029 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2030 EVEX_CD8<64, CD8VF>, VEX_W;
2031 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2032 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2033 EVEX_CD8<64, CD8VQ>, VEX_W;
2035 //===-------------------------------------------------------------------===//
2036 // Variable Bit Shifts
2037 //===-------------------------------------------------------------------===//
2038 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2039 RegisterClass RC, ValueType vt,
2040 X86MemOperand x86memop, PatFrag mem_frag> {
2041 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2042 (ins RC:$src1, RC:$src2),
2043 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2045 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2047 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2048 (ins RC:$src1, x86memop:$src2),
2049 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2051 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2055 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2056 i512mem, memopv16i32>, EVEX_V512,
2057 EVEX_CD8<32, CD8VF>;
2058 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2059 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2060 EVEX_CD8<64, CD8VF>;
2061 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2062 i512mem, memopv16i32>, EVEX_V512,
2063 EVEX_CD8<32, CD8VF>;
2064 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2065 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2066 EVEX_CD8<64, CD8VF>;
2067 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2068 i512mem, memopv16i32>, EVEX_V512,
2069 EVEX_CD8<32, CD8VF>;
2070 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2071 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2072 EVEX_CD8<64, CD8VF>;
2074 //===----------------------------------------------------------------------===//
2075 // AVX-512 - MOVDDUP
2076 //===----------------------------------------------------------------------===//
2078 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2079 X86MemOperand x86memop, PatFrag memop_frag> {
2080 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2081 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2082 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2083 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2084 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2086 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2089 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2090 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2091 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2092 (VMOVDDUPZrm addr:$src)>;
2094 //===---------------------------------------------------------------------===//
2095 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2096 //===---------------------------------------------------------------------===//
2097 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2098 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2099 X86MemOperand x86memop> {
2100 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2101 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2102 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2104 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2105 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2106 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2109 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2110 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2111 EVEX_CD8<32, CD8VF>;
2112 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2113 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2114 EVEX_CD8<32, CD8VF>;
2116 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2117 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2118 (VMOVSHDUPZrm addr:$src)>;
2119 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2120 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2121 (VMOVSLDUPZrm addr:$src)>;
2123 //===----------------------------------------------------------------------===//
2124 // Move Low to High and High to Low packed FP Instructions
2125 //===----------------------------------------------------------------------===//
2126 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2127 (ins VR128X:$src1, VR128X:$src2),
2128 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2129 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2130 IIC_SSE_MOV_LH>, EVEX_4V;
2131 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2132 (ins VR128X:$src1, VR128X:$src2),
2133 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2134 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2135 IIC_SSE_MOV_LH>, EVEX_4V;
2137 let Predicates = [HasAVX512] in {
2139 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2140 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2141 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2142 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2145 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2146 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2149 //===----------------------------------------------------------------------===//
2150 // FMA - Fused Multiply Operations
2152 let Constraints = "$src1 = $dst" in {
2153 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2154 RegisterClass RC, X86MemOperand x86memop,
2155 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2156 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2157 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2158 (ins RC:$src1, RC:$src2, RC:$src3),
2159 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2160 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2163 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2164 (ins RC:$src1, RC:$src2, x86memop:$src3),
2165 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2166 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2167 (mem_frag addr:$src3))))]>;
2168 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2169 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2170 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2171 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2172 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2173 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2175 } // Constraints = "$src1 = $dst"
2177 let ExeDomain = SSEPackedSingle in {
2178 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2179 memopv16f32, f32mem, loadf32, "{1to16}",
2180 X86Fmadd, v16f32>, EVEX_V512,
2181 EVEX_CD8<32, CD8VF>;
2182 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2183 memopv16f32, f32mem, loadf32, "{1to16}",
2184 X86Fmsub, v16f32>, EVEX_V512,
2185 EVEX_CD8<32, CD8VF>;
2186 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2187 memopv16f32, f32mem, loadf32, "{1to16}",
2188 X86Fmaddsub, v16f32>,
2189 EVEX_V512, EVEX_CD8<32, CD8VF>;
2190 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2191 memopv16f32, f32mem, loadf32, "{1to16}",
2192 X86Fmsubadd, v16f32>,
2193 EVEX_V512, EVEX_CD8<32, CD8VF>;
2194 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2195 memopv16f32, f32mem, loadf32, "{1to16}",
2196 X86Fnmadd, v16f32>, EVEX_V512,
2197 EVEX_CD8<32, CD8VF>;
2198 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2199 memopv16f32, f32mem, loadf32, "{1to16}",
2200 X86Fnmsub, v16f32>, EVEX_V512,
2201 EVEX_CD8<32, CD8VF>;
2203 let ExeDomain = SSEPackedDouble in {
2204 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2205 memopv8f64, f64mem, loadf64, "{1to8}",
2206 X86Fmadd, v8f64>, EVEX_V512,
2207 VEX_W, EVEX_CD8<64, CD8VF>;
2208 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2209 memopv8f64, f64mem, loadf64, "{1to8}",
2210 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2211 EVEX_CD8<64, CD8VF>;
2212 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2213 memopv8f64, f64mem, loadf64, "{1to8}",
2214 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2215 EVEX_CD8<64, CD8VF>;
2216 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2217 memopv8f64, f64mem, loadf64, "{1to8}",
2218 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2219 EVEX_CD8<64, CD8VF>;
2220 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2221 memopv8f64, f64mem, loadf64, "{1to8}",
2222 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2223 EVEX_CD8<64, CD8VF>;
2224 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2225 memopv8f64, f64mem, loadf64, "{1to8}",
2226 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2227 EVEX_CD8<64, CD8VF>;
2230 let Constraints = "$src1 = $dst" in {
2231 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2232 RegisterClass RC, X86MemOperand x86memop,
2233 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2234 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2236 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2237 (ins RC:$src1, RC:$src3, x86memop:$src2),
2238 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2239 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2240 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2241 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2242 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2243 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2244 [(set RC:$dst, (OpNode RC:$src1,
2245 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2247 } // Constraints = "$src1 = $dst"
2250 let ExeDomain = SSEPackedSingle in {
2251 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2252 memopv16f32, f32mem, loadf32, "{1to16}",
2253 X86Fmadd, v16f32>, EVEX_V512,
2254 EVEX_CD8<32, CD8VF>;
2255 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2256 memopv16f32, f32mem, loadf32, "{1to16}",
2257 X86Fmsub, v16f32>, EVEX_V512,
2258 EVEX_CD8<32, CD8VF>;
2259 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2260 memopv16f32, f32mem, loadf32, "{1to16}",
2261 X86Fmaddsub, v16f32>,
2262 EVEX_V512, EVEX_CD8<32, CD8VF>;
2263 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2264 memopv16f32, f32mem, loadf32, "{1to16}",
2265 X86Fmsubadd, v16f32>,
2266 EVEX_V512, EVEX_CD8<32, CD8VF>;
2267 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2268 memopv16f32, f32mem, loadf32, "{1to16}",
2269 X86Fnmadd, v16f32>, EVEX_V512,
2270 EVEX_CD8<32, CD8VF>;
2271 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2272 memopv16f32, f32mem, loadf32, "{1to16}",
2273 X86Fnmsub, v16f32>, EVEX_V512,
2274 EVEX_CD8<32, CD8VF>;
2276 let ExeDomain = SSEPackedDouble in {
2277 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2278 memopv8f64, f64mem, loadf64, "{1to8}",
2279 X86Fmadd, v8f64>, EVEX_V512,
2280 VEX_W, EVEX_CD8<64, CD8VF>;
2281 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2282 memopv8f64, f64mem, loadf64, "{1to8}",
2283 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2284 EVEX_CD8<64, CD8VF>;
2285 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2286 memopv8f64, f64mem, loadf64, "{1to8}",
2287 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2288 EVEX_CD8<64, CD8VF>;
2289 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2290 memopv8f64, f64mem, loadf64, "{1to8}",
2291 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2292 EVEX_CD8<64, CD8VF>;
2293 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2294 memopv8f64, f64mem, loadf64, "{1to8}",
2295 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2296 EVEX_CD8<64, CD8VF>;
2297 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2298 memopv8f64, f64mem, loadf64, "{1to8}",
2299 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2300 EVEX_CD8<64, CD8VF>;
2304 let Constraints = "$src1 = $dst" in {
2305 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2306 RegisterClass RC, ValueType OpVT,
2307 X86MemOperand x86memop, Operand memop,
2309 let isCommutable = 1 in
2310 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2311 (ins RC:$src1, RC:$src2, RC:$src3),
2312 !strconcat(OpcodeStr,
2313 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2315 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2317 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2318 (ins RC:$src1, RC:$src2, f128mem:$src3),
2319 !strconcat(OpcodeStr,
2320 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2322 (OpVT (OpNode RC:$src2, RC:$src1,
2323 (mem_frag addr:$src3))))]>;
2326 } // Constraints = "$src1 = $dst"
2328 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2329 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2330 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2331 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2332 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2333 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2334 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2335 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2336 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2337 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2338 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2339 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2340 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2341 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2342 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2343 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2345 //===----------------------------------------------------------------------===//
2346 // AVX-512 Scalar convert from sign integer to float/double
2347 //===----------------------------------------------------------------------===//
2349 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2350 X86MemOperand x86memop, string asm> {
2351 let neverHasSideEffects = 1 in {
2352 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2353 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2356 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2357 (ins DstRC:$src1, x86memop:$src),
2358 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2360 } // neverHasSideEffects = 1
2362 let Predicates = [HasAVX512] in {
2363 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2364 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2365 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2366 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2367 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2368 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2369 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2370 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2372 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2373 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2374 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2375 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2376 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2377 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2378 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2379 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2381 def : Pat<(f32 (sint_to_fp GR32:$src)),
2382 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2383 def : Pat<(f32 (sint_to_fp GR64:$src)),
2384 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2385 def : Pat<(f64 (sint_to_fp GR32:$src)),
2386 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2387 def : Pat<(f64 (sint_to_fp GR64:$src)),
2388 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2390 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2391 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2392 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2393 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2394 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2395 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2396 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2397 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2399 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2400 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2401 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2402 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2403 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2404 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2405 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2406 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2408 def : Pat<(f32 (uint_to_fp GR32:$src)),
2409 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2410 def : Pat<(f32 (uint_to_fp GR64:$src)),
2411 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2412 def : Pat<(f64 (uint_to_fp GR32:$src)),
2413 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2414 def : Pat<(f64 (uint_to_fp GR64:$src)),
2415 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2418 //===----------------------------------------------------------------------===//
2419 // AVX-512 Scalar convert from float/double to integer
2420 //===----------------------------------------------------------------------===//
2421 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2422 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2424 let neverHasSideEffects = 1 in {
2425 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2426 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2427 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2428 Requires<[HasAVX512]>;
2430 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2431 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2432 Requires<[HasAVX512]>;
2433 } // neverHasSideEffects = 1
2435 let Predicates = [HasAVX512] in {
2436 // Convert float/double to signed/unsigned int 32/64
2437 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2438 ssmem, sse_load_f32, "cvtss2si">,
2439 XS, EVEX_CD8<32, CD8VT1>;
2440 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2441 ssmem, sse_load_f32, "cvtss2si">,
2442 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2443 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2444 ssmem, sse_load_f32, "cvtss2usi">,
2445 XS, EVEX_CD8<32, CD8VT1>;
2446 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2447 int_x86_avx512_cvtss2usi64, ssmem,
2448 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2449 EVEX_CD8<32, CD8VT1>;
2450 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2451 sdmem, sse_load_f64, "cvtsd2si">,
2452 XD, EVEX_CD8<64, CD8VT1>;
2453 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2454 sdmem, sse_load_f64, "cvtsd2si">,
2455 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2456 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2457 sdmem, sse_load_f64, "cvtsd2usi">,
2458 XD, EVEX_CD8<64, CD8VT1>;
2459 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2460 int_x86_avx512_cvtsd2usi64, sdmem,
2461 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2462 EVEX_CD8<64, CD8VT1>;
2464 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2465 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2466 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2467 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2468 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2469 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2470 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2471 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2472 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2473 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2474 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2475 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2477 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2478 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2479 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2480 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2481 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2482 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2483 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2484 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2485 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2486 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2487 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2488 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2490 // Convert float/double to signed/unsigned int 32/64 with truncation
2491 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2492 ssmem, sse_load_f32, "cvttss2si">,
2493 XS, EVEX_CD8<32, CD8VT1>;
2494 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2495 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2496 "cvttss2si">, XS, VEX_W,
2497 EVEX_CD8<32, CD8VT1>;
2498 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2499 sdmem, sse_load_f64, "cvttsd2si">, XD,
2500 EVEX_CD8<64, CD8VT1>;
2501 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2502 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2503 "cvttsd2si">, XD, VEX_W,
2504 EVEX_CD8<64, CD8VT1>;
2505 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2506 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2507 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2508 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2509 int_x86_avx512_cvttss2usi64, ssmem,
2510 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2511 EVEX_CD8<32, CD8VT1>;
2512 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2513 int_x86_avx512_cvttsd2usi,
2514 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2515 EVEX_CD8<64, CD8VT1>;
2516 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2517 int_x86_avx512_cvttsd2usi64, sdmem,
2518 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2519 EVEX_CD8<64, CD8VT1>;
2521 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2522 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2524 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2525 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2526 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2527 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2528 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2529 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2532 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2533 loadf32, "cvttss2si">, XS,
2534 EVEX_CD8<32, CD8VT1>;
2535 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2536 loadf32, "cvttss2usi">, XS,
2537 EVEX_CD8<32, CD8VT1>;
2538 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2539 loadf32, "cvttss2si">, XS, VEX_W,
2540 EVEX_CD8<32, CD8VT1>;
2541 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2542 loadf32, "cvttss2usi">, XS, VEX_W,
2543 EVEX_CD8<32, CD8VT1>;
2544 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2545 loadf64, "cvttsd2si">, XD,
2546 EVEX_CD8<64, CD8VT1>;
2547 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2548 loadf64, "cvttsd2usi">, XD,
2549 EVEX_CD8<64, CD8VT1>;
2550 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2551 loadf64, "cvttsd2si">, XD, VEX_W,
2552 EVEX_CD8<64, CD8VT1>;
2553 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2554 loadf64, "cvttsd2usi">, XD, VEX_W,
2555 EVEX_CD8<64, CD8VT1>;
2557 //===----------------------------------------------------------------------===//
2558 // AVX-512 Convert form float to double and back
2559 //===----------------------------------------------------------------------===//
2560 let neverHasSideEffects = 1 in {
2561 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2562 (ins FR32X:$src1, FR32X:$src2),
2563 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2564 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2566 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2567 (ins FR32X:$src1, f32mem:$src2),
2568 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2569 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2570 EVEX_CD8<32, CD8VT1>;
2572 // Convert scalar double to scalar single
2573 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2574 (ins FR64X:$src1, FR64X:$src2),
2575 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2576 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2578 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2579 (ins FR64X:$src1, f64mem:$src2),
2580 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2581 []>, EVEX_4V, VEX_LIG, VEX_W,
2582 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2585 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2586 Requires<[HasAVX512]>;
2587 def : Pat<(fextend (loadf32 addr:$src)),
2588 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2590 def : Pat<(extloadf32 addr:$src),
2591 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2592 Requires<[HasAVX512, OptForSize]>;
2594 def : Pat<(extloadf32 addr:$src),
2595 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2596 Requires<[HasAVX512, OptForSpeed]>;
2598 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2599 Requires<[HasAVX512]>;
2601 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2602 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2603 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2605 let neverHasSideEffects = 1 in {
2606 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2607 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2609 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2611 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2612 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2614 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2615 } // neverHasSideEffects = 1
2618 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2619 memopv8f64, f512mem, v8f32, v8f64,
2620 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2621 EVEX_CD8<64, CD8VF>;
2623 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2624 memopv4f64, f256mem, v8f64, v8f32,
2625 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2626 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2627 (VCVTPS2PDZrm addr:$src)>;
2629 //===----------------------------------------------------------------------===//
2630 // AVX-512 Vector convert from sign integer to float/double
2631 //===----------------------------------------------------------------------===//
2633 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2634 memopv8i64, i512mem, v16f32, v16i32,
2635 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2637 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2638 memopv4i64, i256mem, v8f64, v8i32,
2639 SSEPackedDouble>, EVEX_V512, XS,
2640 EVEX_CD8<32, CD8VH>;
2642 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2643 memopv16f32, f512mem, v16i32, v16f32,
2644 SSEPackedSingle>, EVEX_V512, XS,
2645 EVEX_CD8<32, CD8VF>;
2647 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2648 memopv8f64, f512mem, v8i32, v8f64,
2649 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2650 EVEX_CD8<64, CD8VF>;
2652 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2653 memopv16f32, f512mem, v16i32, v16f32,
2654 SSEPackedSingle>, EVEX_V512,
2655 EVEX_CD8<32, CD8VF>;
2657 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2658 memopv8f64, f512mem, v8i32, v8f64,
2659 SSEPackedDouble>, EVEX_V512, VEX_W,
2660 EVEX_CD8<64, CD8VF>;
2662 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2663 memopv4i64, f256mem, v8f64, v8i32,
2664 SSEPackedDouble>, EVEX_V512, XS,
2665 EVEX_CD8<32, CD8VH>;
2667 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2668 memopv16i32, f512mem, v16f32, v16i32,
2669 SSEPackedSingle>, EVEX_V512, XD,
2670 EVEX_CD8<32, CD8VF>;
2672 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2673 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2674 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2677 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2678 (VCVTDQ2PSZrr VR512:$src)>;
2679 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2680 (VCVTDQ2PSZrm addr:$src)>;
2682 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2683 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2685 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2686 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2687 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2688 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2690 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2691 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2694 let Predicates = [HasAVX512] in {
2695 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2696 (VCVTPD2PSZrm addr:$src)>;
2697 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2698 (VCVTPS2PDZrm addr:$src)>;
2701 //===----------------------------------------------------------------------===//
2702 // Half precision conversion instructions
2703 //===----------------------------------------------------------------------===//
2704 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2705 X86MemOperand x86memop, Intrinsic Int> {
2706 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2707 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2708 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2709 let neverHasSideEffects = 1, mayLoad = 1 in
2710 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2711 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2714 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2715 X86MemOperand x86memop, Intrinsic Int> {
2716 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2717 (ins srcRC:$src1, i32i8imm:$src2),
2718 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2719 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2720 let neverHasSideEffects = 1, mayStore = 1 in
2721 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2722 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2723 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2726 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2727 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2728 EVEX_CD8<32, CD8VH>;
2729 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2730 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2731 EVEX_CD8<32, CD8VH>;
2733 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2734 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2735 "ucomiss">, TB, EVEX, VEX_LIG,
2736 EVEX_CD8<32, CD8VT1>;
2737 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2738 "ucomisd">, TB, OpSize, EVEX,
2739 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2740 let Pattern = []<dag> in {
2741 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2742 "comiss">, TB, EVEX, VEX_LIG,
2743 EVEX_CD8<32, CD8VT1>;
2744 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2745 "comisd">, TB, OpSize, EVEX,
2746 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2748 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2749 load, "ucomiss">, TB, EVEX, VEX_LIG,
2750 EVEX_CD8<32, CD8VT1>;
2751 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2752 load, "ucomisd">, TB, OpSize, EVEX,
2753 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2755 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2756 load, "comiss">, TB, EVEX, VEX_LIG,
2757 EVEX_CD8<32, CD8VT1>;
2758 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2759 load, "comisd">, TB, OpSize, EVEX,
2760 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2763 /// avx512_unop_p - AVX-512 unops in packed form.
2764 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2765 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2766 !strconcat(OpcodeStr,
2767 "ps\t{$src, $dst|$dst, $src}"),
2768 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2770 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2771 !strconcat(OpcodeStr,
2772 "ps\t{$src, $dst|$dst, $src}"),
2773 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2774 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2775 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2776 !strconcat(OpcodeStr,
2777 "pd\t{$src, $dst|$dst, $src}"),
2778 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2779 EVEX, EVEX_V512, VEX_W;
2780 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2781 !strconcat(OpcodeStr,
2782 "pd\t{$src, $dst|$dst, $src}"),
2783 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2784 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2787 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2788 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2789 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2790 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2791 !strconcat(OpcodeStr,
2792 "ps\t{$src, $dst|$dst, $src}"),
2793 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2795 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2796 !strconcat(OpcodeStr,
2797 "ps\t{$src, $dst|$dst, $src}"),
2799 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2800 EVEX_V512, EVEX_CD8<32, CD8VF>;
2801 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2802 !strconcat(OpcodeStr,
2803 "pd\t{$src, $dst|$dst, $src}"),
2804 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2805 EVEX, EVEX_V512, VEX_W;
2806 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2807 !strconcat(OpcodeStr,
2808 "pd\t{$src, $dst|$dst, $src}"),
2810 (V8F64Int (memopv8f64 addr:$src)))]>,
2811 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2814 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
2815 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
2816 let hasSideEffects = 0 in {
2817 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2818 (ins FR32X:$src1, FR32X:$src2),
2819 !strconcat(OpcodeStr,
2820 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2822 let mayLoad = 1 in {
2823 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2824 (ins FR32X:$src1, f32mem:$src2),
2825 !strconcat(OpcodeStr,
2826 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2827 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2828 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2829 (ins VR128X:$src1, ssmem:$src2),
2830 !strconcat(OpcodeStr,
2831 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2832 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2834 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2835 (ins FR64X:$src1, FR64X:$src2),
2836 !strconcat(OpcodeStr,
2837 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2839 let mayLoad = 1 in {
2840 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2841 (ins FR64X:$src1, f64mem:$src2),
2842 !strconcat(OpcodeStr,
2843 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2844 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2845 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2846 (ins VR128X:$src1, sdmem:$src2),
2847 !strconcat(OpcodeStr,
2848 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2849 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2854 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
2855 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2856 avx512_fp_unop_p_int<0x4C, "vrcp14",
2857 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2859 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
2860 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2861 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2862 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2864 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2865 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2866 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2868 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2869 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2871 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2872 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2873 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2875 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2876 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2878 let AddedComplexity = 20, Predicates = [HasERI] in {
2879 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2880 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2881 avx512_fp_unop_p_int<0xCA, "vrcp28",
2882 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2884 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2885 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2886 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2887 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2890 let Predicates = [HasERI] in {
2891 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2892 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2893 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2895 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2896 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2898 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2899 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2900 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2902 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2903 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2905 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2906 Intrinsic V16F32Int, Intrinsic V8F64Int,
2907 OpndItins itins_s, OpndItins itins_d> {
2908 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2909 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2910 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2914 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2915 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2917 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2918 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2920 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2921 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2922 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2926 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2927 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2928 [(set VR512:$dst, (OpNode
2929 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2930 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2932 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2933 !strconcat(OpcodeStr,
2934 "ps\t{$src, $dst|$dst, $src}"),
2935 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2937 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2938 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2940 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2941 EVEX_V512, EVEX_CD8<32, CD8VF>;
2942 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2943 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2944 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2945 EVEX, EVEX_V512, VEX_W;
2946 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2947 !strconcat(OpcodeStr,
2948 "pd\t{$src, $dst|$dst, $src}"),
2949 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2950 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2953 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2954 Intrinsic F32Int, Intrinsic F64Int,
2955 OpndItins itins_s, OpndItins itins_d> {
2956 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2957 (ins FR32X:$src1, FR32X:$src2),
2958 !strconcat(OpcodeStr,
2959 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2960 [], itins_s.rr>, XS, EVEX_4V;
2961 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2962 (ins VR128X:$src1, VR128X:$src2),
2963 !strconcat(OpcodeStr,
2964 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2966 (F32Int VR128X:$src1, VR128X:$src2))],
2967 itins_s.rr>, XS, EVEX_4V;
2968 let mayLoad = 1 in {
2969 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2970 (ins FR32X:$src1, f32mem:$src2),
2971 !strconcat(OpcodeStr,
2972 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2973 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2974 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2975 (ins VR128X:$src1, ssmem:$src2),
2976 !strconcat(OpcodeStr,
2977 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2979 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2980 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2982 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2983 (ins FR64X:$src1, FR64X:$src2),
2984 !strconcat(OpcodeStr,
2985 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2987 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2988 (ins VR128X:$src1, VR128X:$src2),
2989 !strconcat(OpcodeStr,
2990 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2992 (F64Int VR128X:$src1, VR128X:$src2))],
2993 itins_s.rr>, XD, EVEX_4V, VEX_W;
2994 let mayLoad = 1 in {
2995 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2996 (ins FR64X:$src1, f64mem:$src2),
2997 !strconcat(OpcodeStr,
2998 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2999 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3000 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3001 (ins VR128X:$src1, sdmem:$src2),
3002 !strconcat(OpcodeStr,
3003 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3005 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3006 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3011 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3012 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3013 SSE_SQRTSS, SSE_SQRTSD>,
3014 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3015 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3016 SSE_SQRTPS, SSE_SQRTPD>;
3018 let Predicates = [HasAVX512] in {
3019 def : Pat<(f32 (fsqrt FR32X:$src)),
3020 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3021 def : Pat<(f32 (fsqrt (load addr:$src))),
3022 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3023 Requires<[OptForSize]>;
3024 def : Pat<(f64 (fsqrt FR64X:$src)),
3025 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3026 def : Pat<(f64 (fsqrt (load addr:$src))),
3027 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3028 Requires<[OptForSize]>;
3030 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3031 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3032 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3033 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3034 Requires<[OptForSize]>;
3036 def : Pat<(f32 (X86frcp FR32X:$src)),
3037 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3038 def : Pat<(f32 (X86frcp (load addr:$src))),
3039 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3040 Requires<[OptForSize]>;
3042 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3043 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3044 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3046 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3047 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3049 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3050 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3051 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3053 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3054 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3058 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3059 X86MemOperand x86memop, RegisterClass RC,
3060 PatFrag mem_frag32, PatFrag mem_frag64,
3061 Intrinsic V4F32Int, Intrinsic V2F64Int,
3063 let ExeDomain = SSEPackedSingle in {
3064 // Intrinsic operation, reg.
3065 // Vector intrinsic operation, reg
3066 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3067 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3068 !strconcat(OpcodeStr,
3069 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3070 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3072 // Vector intrinsic operation, mem
3073 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3074 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3075 !strconcat(OpcodeStr,
3076 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3078 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3079 EVEX_CD8<32, VForm>;
3080 } // ExeDomain = SSEPackedSingle
3082 let ExeDomain = SSEPackedDouble in {
3083 // Vector intrinsic operation, reg
3084 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3085 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3086 !strconcat(OpcodeStr,
3087 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3088 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3090 // Vector intrinsic operation, mem
3091 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3092 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3093 !strconcat(OpcodeStr,
3094 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3096 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3097 EVEX_CD8<64, VForm>;
3098 } // ExeDomain = SSEPackedDouble
3101 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3105 let ExeDomain = GenericDomain in {
3107 let hasSideEffects = 0 in
3108 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3109 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3110 !strconcat(OpcodeStr,
3111 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3114 // Intrinsic operation, reg.
3115 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3116 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3117 !strconcat(OpcodeStr,
3118 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3119 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3121 // Intrinsic operation, mem.
3122 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3123 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3124 !strconcat(OpcodeStr,
3125 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3126 [(set VR128X:$dst, (F32Int VR128X:$src1,
3127 sse_load_f32:$src2, imm:$src3))]>,
3128 EVEX_CD8<32, CD8VT1>;
3131 let hasSideEffects = 0 in
3132 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3133 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3134 !strconcat(OpcodeStr,
3135 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3138 // Intrinsic operation, reg.
3139 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3140 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3141 !strconcat(OpcodeStr,
3142 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3143 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3146 // Intrinsic operation, mem.
3147 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3148 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3149 !strconcat(OpcodeStr,
3150 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3152 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3153 VEX_W, EVEX_CD8<64, CD8VT1>;
3154 } // ExeDomain = GenericDomain
3157 let Predicates = [HasAVX512] in {
3158 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3159 int_x86_avx512_rndscale_ss,
3160 int_x86_avx512_rndscale_sd>, EVEX_4V;
3162 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3163 memopv16f32, memopv8f64,
3164 int_x86_avx512_rndscale_ps_512,
3165 int_x86_avx512_rndscale_pd_512, CD8VF>,
3169 def : Pat<(ffloor FR32X:$src),
3170 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3171 def : Pat<(f64 (ffloor FR64X:$src)),
3172 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3173 def : Pat<(f32 (fnearbyint FR32X:$src)),
3174 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3175 def : Pat<(f64 (fnearbyint FR64X:$src)),
3176 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3177 def : Pat<(f32 (fceil FR32X:$src)),
3178 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3179 def : Pat<(f64 (fceil FR64X:$src)),
3180 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3181 def : Pat<(f32 (frint FR32X:$src)),
3182 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3183 def : Pat<(f64 (frint FR64X:$src)),
3184 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3185 def : Pat<(f32 (ftrunc FR32X:$src)),
3186 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3187 def : Pat<(f64 (ftrunc FR64X:$src)),
3188 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3190 def : Pat<(v16f32 (ffloor VR512:$src)),
3191 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3192 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3193 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3194 def : Pat<(v16f32 (fceil VR512:$src)),
3195 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3196 def : Pat<(v16f32 (frint VR512:$src)),
3197 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3198 def : Pat<(v16f32 (ftrunc VR512:$src)),
3199 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3201 def : Pat<(v8f64 (ffloor VR512:$src)),
3202 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3203 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3204 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3205 def : Pat<(v8f64 (fceil VR512:$src)),
3206 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3207 def : Pat<(v8f64 (frint VR512:$src)),
3208 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3209 def : Pat<(v8f64 (ftrunc VR512:$src)),
3210 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3212 //-------------------------------------------------
3213 // Integer truncate and extend operations
3214 //-------------------------------------------------
3216 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3217 RegisterClass dstRC, RegisterClass srcRC,
3218 RegisterClass KRC, X86MemOperand x86memop> {
3219 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3221 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3224 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3225 (ins KRC:$mask, srcRC:$src),
3226 !strconcat(OpcodeStr,
3227 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3230 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3231 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3234 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3235 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3236 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3237 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3238 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3239 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3240 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3241 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3242 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3243 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3244 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3245 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3246 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3247 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3248 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3249 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3250 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3251 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3252 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3253 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3254 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3255 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3256 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3257 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3258 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3259 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3260 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3261 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3262 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3263 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3265 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3266 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3267 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3268 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3269 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3271 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3272 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3273 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3274 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3275 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3276 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3277 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3278 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3281 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3282 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3283 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3285 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3287 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3288 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3289 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3290 (ins x86memop:$src),
3291 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3293 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3297 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3298 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3300 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3301 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3303 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3304 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3305 EVEX_CD8<16, CD8VH>;
3306 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3307 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3308 EVEX_CD8<16, CD8VQ>;
3309 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3310 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3311 EVEX_CD8<32, CD8VH>;
3313 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3314 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3316 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3317 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3319 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3320 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3321 EVEX_CD8<16, CD8VH>;
3322 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3323 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3324 EVEX_CD8<16, CD8VQ>;
3325 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3326 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3327 EVEX_CD8<32, CD8VH>;
3329 //===----------------------------------------------------------------------===//
3330 // GATHER - SCATTER Operations
3332 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3333 RegisterClass RC, X86MemOperand memop> {
3335 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3336 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3337 (ins RC:$src1, KRC:$mask, memop:$src2),
3338 !strconcat(OpcodeStr,
3339 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3342 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3343 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3344 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3345 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3347 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3348 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3349 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3350 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3352 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3353 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3354 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3355 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3357 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3358 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3359 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3360 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3362 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3363 RegisterClass RC, X86MemOperand memop> {
3364 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3365 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3366 (ins memop:$dst, KRC:$mask, RC:$src2),
3367 !strconcat(OpcodeStr,
3368 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3372 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3373 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3374 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3375 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3377 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3378 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3379 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3382 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3383 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3384 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3385 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3387 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3388 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3389 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3390 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3392 //===----------------------------------------------------------------------===//
3393 // VSHUFPS - VSHUFPD Operations
3395 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3396 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3398 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3399 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3400 !strconcat(OpcodeStr,
3401 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3402 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3403 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3404 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3405 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3406 (ins RC:$src1, RC:$src2, i8imm:$src3),
3407 !strconcat(OpcodeStr,
3408 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3409 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3410 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3411 EVEX_4V, Sched<[WriteShuffle]>;
3414 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3415 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3416 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3417 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3419 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3420 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3421 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3422 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3423 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3425 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3426 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3427 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3428 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3429 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3431 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3432 X86MemOperand x86memop> {
3433 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3434 (ins RC:$src1, RC:$src2, i8imm:$src3),
3435 !strconcat(OpcodeStr,
3436 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3439 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3440 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3441 !strconcat(OpcodeStr,
3442 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3445 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3446 EVEX_V512, EVEX_CD8<32, CD8VF>;
3447 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3448 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3450 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3451 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3452 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3453 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3454 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3455 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3456 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3457 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3459 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3460 X86MemOperand x86memop> {
3461 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3462 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3464 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3465 (ins x86memop:$src),
3466 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3470 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3471 EVEX_CD8<32, CD8VF>;
3472 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3473 EVEX_CD8<64, CD8VF>;
3475 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3476 RegisterClass RC, RegisterClass KRC,
3477 X86MemOperand x86memop,
3478 X86MemOperand x86scalar_mop, string BrdcstStr> {
3479 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3481 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3483 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3484 (ins x86memop:$src),
3485 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3487 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3488 (ins x86scalar_mop:$src),
3489 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3490 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3492 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3493 (ins KRC:$mask, RC:$src),
3494 !strconcat(OpcodeStr,
3495 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3497 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3498 (ins KRC:$mask, x86memop:$src),
3499 !strconcat(OpcodeStr,
3500 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3502 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3503 (ins KRC:$mask, x86scalar_mop:$src),
3504 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3505 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3507 []>, EVEX, EVEX_KZ, EVEX_B;
3509 let Constraints = "$src1 = $dst" in {
3510 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3511 (ins RC:$src1, KRC:$mask, RC:$src2),
3512 !strconcat(OpcodeStr,
3513 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3515 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3516 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3517 !strconcat(OpcodeStr,
3518 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3520 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3521 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3522 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3523 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3524 []>, EVEX, EVEX_K, EVEX_B;
3528 let Predicates = [HasCDI] in {
3529 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3530 i512mem, i32mem, "{1to16}">,
3531 EVEX_V512, EVEX_CD8<32, CD8VF>;
3534 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3535 i512mem, i64mem, "{1to8}">,
3536 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3540 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3542 (VPCONFLICTDrrk VR512:$src1,
3543 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3545 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3547 (VPCONFLICTQrrk VR512:$src1,
3548 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;