1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
9 ValueType EltVT = eltvt;
10 int NumElts = numelts;
12 // Corresponding mask register class.
13 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
15 // Corresponding write-mask register class.
16 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
18 // The GPR register class that can hold the write mask. Use GR8 for fewer
19 // than 8 elements. Use shift-right and equal to work around the lack of
22 !cast<RegisterClass>("GR" #
23 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
25 // Suffix used in the instruction mnemonic.
26 string Suffix = suffix;
28 // VTName is a string name for vector VT. For vector types it will be
29 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
30 // It is a little bit complex for scalar types, where NumElts = 1.
31 // In this case we build v4f32 or v2f64
32 string VTName = "v" # !if (!eq (NumElts, 1),
33 !if (!eq (EltVT.Size, 32), 4,
34 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
37 ValueType VT = !cast<ValueType>(VTName);
39 string EltTypeName = !cast<string>(EltVT);
40 // Size of the element type in bits, e.g. 32 for v16i32.
41 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
42 int EltSize = EltVT.Size;
44 // "i" for integer types and "f" for floating-point types
45 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
47 // Size of RC in bits, e.g. 512 for VR512.
50 // The corresponding memory operand, e.g. i512mem for VR512.
51 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
52 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
55 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
56 // due to load promotion during legalization
57 PatFrag LdFrag = !cast<PatFrag>("load" #
58 !if (!eq (TypeVariantName, "i"),
59 !if (!eq (Size, 128), "v2i64",
60 !if (!eq (Size, 256), "v4i64",
62 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
64 // Load patterns used for memory operands. We only have this defined in
65 // case of i64 element types for sub-512 integer vectors. For now, keep
66 // MemOpFrag undefined in these cases.
68 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
69 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
70 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
71 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
72 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
74 // The corresponding float type, e.g. v16f32 for v16i32
75 // Note: For EltSize < 32, FloatVT is illegal and TableGen
76 // fails to compile, so we choose FloatVT = VT
77 ValueType FloatVT = !cast<ValueType>(
78 !if (!eq (!srl(EltSize,5),0),
80 !if (!eq(TypeVariantName, "i"),
81 "v" # NumElts # "f" # EltSize,
84 // The string to specify embedded broadcast in assembly.
85 string BroadcastStr = "{1to" # NumElts # "}";
87 // 8-bit compressed displacement tuple/subvector format. This is only
88 // defined for NumElts <= 8.
89 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
90 !cast<CD8VForm>("CD8VT" # NumElts), ?);
92 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
93 !if (!eq (Size, 256), sub_ymm, ?));
95 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
96 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
99 // A vector type of the same width with element type i32. This is used to
100 // create the canonical constant zero node ImmAllZerosV.
101 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
102 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
105 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
106 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
107 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
108 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
109 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
110 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
112 // "x" in v32i8x_info means RC = VR256X
113 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
114 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
115 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
116 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
117 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
118 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
120 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
121 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
122 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
123 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
124 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
125 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
127 // We map scalar types to the smallest (128-bit) vector type
128 // with the appropriate element type. This allows to use the same masking logic.
129 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
130 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
132 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
133 X86VectorVTInfo i128> {
134 X86VectorVTInfo info512 = i512;
135 X86VectorVTInfo info256 = i256;
136 X86VectorVTInfo info128 = i128;
139 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
141 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
143 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
145 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
147 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
149 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
152 // This multiclass generates the masking variants from the non-masking
153 // variant. It only provides the assembly pieces for the masking variants.
154 // It assumes custom ISel patterns for masking which can be provided as
155 // template arguments.
156 multiclass AVX512_maskable_custom<bits<8> O, Format F,
158 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
160 string AttSrcAsm, string IntelSrcAsm,
162 list<dag> MaskingPattern,
163 list<dag> ZeroMaskingPattern,
165 string MaskingConstraint = "",
166 InstrItinClass itin = NoItinerary,
167 bit IsCommutable = 0> {
168 let isCommutable = IsCommutable in
169 def NAME: AVX512<O, F, Outs, Ins,
170 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
171 "$dst "#Round#", "#IntelSrcAsm#"}",
174 // Prefer over VMOV*rrk Pat<>
175 let AddedComplexity = 20 in
176 def NAME#k: AVX512<O, F, Outs, MaskingIns,
177 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
178 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
179 MaskingPattern, itin>,
181 // In case of the 3src subclass this is overridden with a let.
182 string Constraints = MaskingConstraint;
184 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
185 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
186 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
187 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
194 // Common base class of AVX512_maskable and AVX512_maskable_3src.
195 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
197 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
199 string AttSrcAsm, string IntelSrcAsm,
200 dag RHS, dag MaskingRHS,
201 SDNode Select = vselect, string Round = "",
202 string MaskingConstraint = "",
203 InstrItinClass itin = NoItinerary,
204 bit IsCommutable = 0> :
205 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
206 AttSrcAsm, IntelSrcAsm,
207 [(set _.RC:$dst, RHS)],
208 [(set _.RC:$dst, MaskingRHS)],
210 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
211 Round, MaskingConstraint, NoItinerary, IsCommutable>;
213 // This multiclass generates the unconditional/non-masking, the masking and
214 // the zero-masking variant of the vector instruction. In the masking case, the
215 // perserved vector elements come from a new dummy input operand tied to $dst.
216 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Outs, dag Ins, string OpcodeStr,
218 string AttSrcAsm, string IntelSrcAsm,
219 dag RHS, string Round = "",
220 InstrItinClass itin = NoItinerary,
221 bit IsCommutable = 0> :
222 AVX512_maskable_common<O, F, _, Outs, Ins,
223 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
224 !con((ins _.KRCWM:$mask), Ins),
225 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
226 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
227 Round, "$src0 = $dst", itin, IsCommutable>;
229 // This multiclass generates the unconditional/non-masking, the masking and
230 // the zero-masking variant of the scalar instruction.
231 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
232 dag Outs, dag Ins, string OpcodeStr,
233 string AttSrcAsm, string IntelSrcAsm,
234 dag RHS, string Round = "",
235 InstrItinClass itin = NoItinerary,
236 bit IsCommutable = 0> :
237 AVX512_maskable_common<O, F, _, Outs, Ins,
238 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
239 !con((ins _.KRCWM:$mask), Ins),
240 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
241 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
242 Round, "$src0 = $dst", itin, IsCommutable>;
244 // Similar to AVX512_maskable but in this case one of the source operands
245 // ($src1) is already tied to $dst so we just use that for the preserved
246 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
248 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
249 dag Outs, dag NonTiedIns, string OpcodeStr,
250 string AttSrcAsm, string IntelSrcAsm,
252 AVX512_maskable_common<O, F, _, Outs,
253 !con((ins _.RC:$src1), NonTiedIns),
254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
255 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
256 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
257 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
260 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
263 string AttSrcAsm, string IntelSrcAsm,
265 AVX512_maskable_custom<O, F, Outs, Ins,
266 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
267 !con((ins _.KRCWM:$mask), Ins),
268 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
271 // Bitcasts between 512-bit vector types. Return the original type since
272 // no instruction is needed for the conversion
273 let Predicates = [HasAVX512] in {
274 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
275 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
276 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
277 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
278 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
279 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
280 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
281 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
282 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
283 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
284 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
285 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
286 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
287 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
288 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
289 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
290 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
291 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
292 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
293 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
296 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
297 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
299 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
300 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
302 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
303 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
304 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
306 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
307 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
308 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
309 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
310 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
311 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
312 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
313 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
314 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
315 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
316 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
317 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
318 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
319 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
320 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
321 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
322 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
323 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
324 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
325 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
326 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
327 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
328 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
329 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
330 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
331 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
332 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
333 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
334 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
335 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
337 // Bitcasts between 256-bit vector types. Return the original type since
338 // no instruction is needed for the conversion
339 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
340 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
341 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
342 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
343 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
344 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
346 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
347 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
348 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
350 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
351 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
352 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
353 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
355 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
357 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
358 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
359 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
360 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
361 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
363 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
365 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
367 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
368 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
372 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
375 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
376 isPseudo = 1, Predicates = [HasAVX512] in {
377 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
378 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
381 let Predicates = [HasAVX512] in {
382 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
383 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
384 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
387 //===----------------------------------------------------------------------===//
388 // AVX-512 - VECTOR INSERT
391 multiclass vinsert_for_size_no_alt<int Opcode,
392 X86VectorVTInfo From, X86VectorVTInfo To,
393 PatFrag vinsert_insert,
394 SDNodeXForm INSERT_get_vinsert_imm> {
395 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
396 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
397 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
398 "vinsert" # From.EltTypeName # "x" # From.NumElts #
399 "\t{$src3, $src2, $src1, $dst|"
400 "$dst, $src1, $src2, $src3}",
401 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
402 (From.VT From.RC:$src2),
407 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
408 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
409 "vinsert" # From.EltTypeName # "x" # From.NumElts #
410 "\t{$src3, $src2, $src1, $dst|"
411 "$dst, $src1, $src2, $src3}",
413 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
417 multiclass vinsert_for_size<int Opcode,
418 X86VectorVTInfo From, X86VectorVTInfo To,
419 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
420 PatFrag vinsert_insert,
421 SDNodeXForm INSERT_get_vinsert_imm> :
422 vinsert_for_size_no_alt<Opcode, From, To,
423 vinsert_insert, INSERT_get_vinsert_imm> {
424 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
425 // vinserti32x4. Only add this if 64x2 and friends are not supported
426 // natively via AVX512DQ.
427 let Predicates = [NoDQI] in
428 def : Pat<(vinsert_insert:$ins
429 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
430 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
431 VR512:$src1, From.RC:$src2,
432 (INSERT_get_vinsert_imm VR512:$ins)))>;
435 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
436 ValueType EltVT64, int Opcode256> {
437 defm NAME # "32x4" : vinsert_for_size<Opcode128,
438 X86VectorVTInfo< 4, EltVT32, VR128X>,
439 X86VectorVTInfo<16, EltVT32, VR512>,
440 X86VectorVTInfo< 2, EltVT64, VR128X>,
441 X86VectorVTInfo< 8, EltVT64, VR512>,
443 INSERT_get_vinsert128_imm>;
444 let Predicates = [HasDQI] in
445 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
446 X86VectorVTInfo< 2, EltVT64, VR128X>,
447 X86VectorVTInfo< 8, EltVT64, VR512>,
449 INSERT_get_vinsert128_imm>, VEX_W;
450 defm NAME # "64x4" : vinsert_for_size<Opcode256,
451 X86VectorVTInfo< 4, EltVT64, VR256X>,
452 X86VectorVTInfo< 8, EltVT64, VR512>,
453 X86VectorVTInfo< 8, EltVT32, VR256>,
454 X86VectorVTInfo<16, EltVT32, VR512>,
456 INSERT_get_vinsert256_imm>, VEX_W;
457 let Predicates = [HasDQI] in
458 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
459 X86VectorVTInfo< 8, EltVT32, VR256X>,
460 X86VectorVTInfo<16, EltVT32, VR512>,
462 INSERT_get_vinsert256_imm>;
465 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
466 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
468 // vinsertps - insert f32 to XMM
469 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
470 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
471 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
472 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
474 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
475 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
476 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
477 [(set VR128X:$dst, (X86insertps VR128X:$src1,
478 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
479 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
481 //===----------------------------------------------------------------------===//
482 // AVX-512 VECTOR EXTRACT
485 multiclass vextract_for_size<int Opcode,
486 X86VectorVTInfo From, X86VectorVTInfo To,
487 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
488 PatFrag vextract_extract,
489 SDNodeXForm EXTRACT_get_vextract_imm> {
490 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
491 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
492 (ins VR512:$src1, i8imm:$idx),
493 "vextract" # To.EltTypeName # "x4",
494 "$idx, $src1", "$src1, $idx",
495 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
497 AVX512AIi8Base, EVEX, EVEX_V512;
499 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
500 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
501 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
502 "$dst, $src1, $src2}",
503 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
506 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
508 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
509 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
511 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
513 // A 128/256-bit subvector extract from the first 512-bit vector position is
514 // a subregister copy that needs no instruction.
515 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
517 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
519 // And for the alternative types.
520 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
522 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
524 // Intrinsic call with masking.
525 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
527 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
528 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
529 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
530 VR512:$src1, imm:$idx)>;
532 // Intrinsic call with zero-masking.
533 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
535 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
536 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
537 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
538 VR512:$src1, imm:$idx)>;
540 // Intrinsic call without masking.
541 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
543 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
544 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
545 VR512:$src1, imm:$idx)>;
548 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
549 ValueType EltVT64, int Opcode64> {
550 defm NAME # "32x4" : vextract_for_size<Opcode32,
551 X86VectorVTInfo<16, EltVT32, VR512>,
552 X86VectorVTInfo< 4, EltVT32, VR128X>,
553 X86VectorVTInfo< 8, EltVT64, VR512>,
554 X86VectorVTInfo< 2, EltVT64, VR128X>,
556 EXTRACT_get_vextract128_imm>;
557 defm NAME # "64x4" : vextract_for_size<Opcode64,
558 X86VectorVTInfo< 8, EltVT64, VR512>,
559 X86VectorVTInfo< 4, EltVT64, VR256X>,
560 X86VectorVTInfo<16, EltVT32, VR512>,
561 X86VectorVTInfo< 8, EltVT32, VR256>,
563 EXTRACT_get_vextract256_imm>, VEX_W;
566 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
567 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
569 // A 128-bit subvector insert to the first 512-bit vector position
570 // is a subregister copy that needs no instruction.
571 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
572 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
573 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
575 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
576 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
577 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
579 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
580 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
581 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
583 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
584 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
585 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
588 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
589 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
590 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
591 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
592 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
593 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
594 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
595 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
597 // vextractps - extract 32 bits from XMM
598 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
599 (ins VR128X:$src1, i32i8imm:$src2),
600 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
601 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
604 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
605 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
606 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
607 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
608 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
610 //===---------------------------------------------------------------------===//
613 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
614 ValueType svt, X86VectorVTInfo _> {
615 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
616 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
617 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
621 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
622 (ins _.ScalarMemOp:$src),
623 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
624 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
629 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
630 AVX512VLVectorVTInfo _> {
631 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
634 let Predicates = [HasVLX] in {
635 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
640 let ExeDomain = SSEPackedSingle in {
641 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
642 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
643 let Predicates = [HasVLX] in {
644 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
645 v4f32, v4f32x_info>, EVEX_V128,
646 EVEX_CD8<32, CD8VT1>;
650 let ExeDomain = SSEPackedDouble in {
651 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
652 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
655 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
656 // Later, we can canonize broadcast instructions before ISel phase and
657 // eliminate additional patterns on ISel.
658 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
659 // representations of source
660 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
661 X86VectorVTInfo _, RegisterClass SrcRC_v,
662 RegisterClass SrcRC_s> {
663 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
664 (!cast<Instruction>(InstName##"r")
665 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
667 let AddedComplexity = 30 in {
668 def : Pat<(_.VT (vselect _.KRCWM:$mask,
669 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
670 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
671 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
673 def : Pat<(_.VT(vselect _.KRCWM:$mask,
674 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
675 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
676 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
680 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
682 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
685 let Predicates = [HasVLX] in {
686 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
687 v8f32x_info, VR128X, FR32X>;
688 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
689 v4f32x_info, VR128X, FR32X>;
690 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
691 v4f64x_info, VR128X, FR64X>;
694 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
695 (VBROADCASTSSZm addr:$src)>;
696 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
697 (VBROADCASTSDZm addr:$src)>;
699 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
700 (VBROADCASTSSZm addr:$src)>;
701 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
702 (VBROADCASTSDZm addr:$src)>;
704 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
705 RegisterClass SrcRC> {
706 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
707 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
708 "$src", "$src", []>, T8PD, EVEX;
711 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
712 RegisterClass SrcRC, Predicate prd> {
713 let Predicates = [prd] in
714 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
715 let Predicates = [prd, HasVLX] in {
716 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
717 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
721 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
723 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
725 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
727 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
730 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
731 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
733 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
734 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
736 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
737 (VPBROADCASTDrZr GR32:$src)>;
738 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
739 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
740 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
741 (VPBROADCASTQrZr GR64:$src)>;
742 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
743 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
745 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
746 (VPBROADCASTDrZr GR32:$src)>;
747 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
748 (VPBROADCASTQrZr GR64:$src)>;
750 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
751 (v16i32 immAllZerosV), (i16 GR16:$mask))),
752 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
753 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
754 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
755 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
757 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
758 X86MemOperand x86memop, PatFrag ld_frag,
759 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
761 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
764 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
765 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
767 !strconcat(OpcodeStr,
768 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
770 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
773 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
774 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
776 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
777 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
779 !strconcat(OpcodeStr,
780 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
781 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
782 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
786 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
787 loadi32, VR512, v16i32, v4i32, VK16WM>,
788 EVEX_V512, EVEX_CD8<32, CD8VT1>;
789 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
790 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
791 EVEX_CD8<64, CD8VT1>;
793 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
794 X86MemOperand x86memop, PatFrag ld_frag,
797 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
800 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
802 !strconcat(OpcodeStr,
803 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
808 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
809 i128mem, loadv2i64, VK16WM>,
810 EVEX_V512, EVEX_CD8<32, CD8VT4>;
811 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
812 i256mem, loadv4i64, VK16WM>, VEX_W,
813 EVEX_V512, EVEX_CD8<64, CD8VT4>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
816 (VPBROADCASTDZrr VR128X:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
818 (VPBROADCASTQZrr VR128X:$src)>;
820 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
821 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
822 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
823 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
825 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
826 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
827 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
828 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
830 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
831 (VBROADCASTSSZr VR128X:$src)>;
832 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
833 (VBROADCASTSDZr VR128X:$src)>;
835 // Provide fallback in case the load node that is used in the patterns above
836 // is used by additional users, which prevents the pattern selection.
837 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
838 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
839 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
840 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
843 let Predicates = [HasAVX512] in {
844 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
846 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
847 addr:$src)), sub_ymm)>;
849 //===----------------------------------------------------------------------===//
850 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
853 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
855 let Predicates = [HasCDI] in
856 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
858 []>, EVEX, EVEX_V512;
860 let Predicates = [HasCDI, HasVLX] in {
861 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
862 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
863 []>, EVEX, EVEX_V128;
864 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
865 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
866 []>, EVEX, EVEX_V256;
870 let Predicates = [HasCDI] in {
871 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
873 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
877 //===----------------------------------------------------------------------===//
880 // -- immediate form --
881 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
883 let ExeDomain = _.ExeDomain in {
884 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
885 (ins _.RC:$src1, i8imm:$src2),
886 !strconcat(OpcodeStr,
887 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
889 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
891 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
892 (ins _.MemOp:$src1, i8imm:$src2),
893 !strconcat(OpcodeStr,
894 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
896 (_.VT (OpNode (_.MemOpFrag addr:$src1),
898 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
902 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
903 X86VectorVTInfo Ctrl> :
904 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
905 let ExeDomain = _.ExeDomain in {
906 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
907 (ins _.RC:$src1, _.RC:$src2),
908 !strconcat("vpermil" # _.Suffix,
909 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
911 (_.VT (X86VPermilpv _.RC:$src1,
912 (Ctrl.VT Ctrl.RC:$src2))))]>,
914 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
915 (ins _.RC:$src1, Ctrl.MemOp:$src2),
916 !strconcat("vpermil" # _.Suffix,
917 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
919 (_.VT (X86VPermilpv _.RC:$src1,
920 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
925 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
927 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
930 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
932 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
935 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
936 (VPERMILPSZri VR512:$src1, imm:$imm)>;
937 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
938 (VPERMILPDZri VR512:$src1, imm:$imm)>;
940 // -- VPERM - register form --
941 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
942 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
944 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
945 (ins RC:$src1, RC:$src2),
946 !strconcat(OpcodeStr,
947 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
949 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
951 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
952 (ins RC:$src1, x86memop:$src2),
953 !strconcat(OpcodeStr,
954 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
956 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
960 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
961 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
962 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
963 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
964 let ExeDomain = SSEPackedSingle in
965 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
966 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
967 let ExeDomain = SSEPackedDouble in
968 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
969 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
971 // -- VPERM2I - 3 source operands form --
972 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
973 PatFrag mem_frag, X86MemOperand x86memop,
974 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
975 let Constraints = "$src1 = $dst" in {
976 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
977 (ins RC:$src1, RC:$src2, RC:$src3),
978 !strconcat(OpcodeStr,
979 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
981 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
984 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
985 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
986 !strconcat(OpcodeStr,
987 "\t{$src3, $src2, $dst {${mask}}|"
988 "$dst {${mask}}, $src2, $src3}"),
989 [(set RC:$dst, (OpVT (vselect KRC:$mask,
990 (OpNode RC:$src1, RC:$src2,
995 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
996 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
997 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
998 !strconcat(OpcodeStr,
999 "\t{$src3, $src2, $dst {${mask}} {z} |",
1000 "$dst {${mask}} {z}, $src2, $src3}"),
1001 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1002 (OpNode RC:$src1, RC:$src2,
1005 (v16i32 immAllZerosV))))))]>,
1008 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1009 (ins RC:$src1, RC:$src2, x86memop:$src3),
1010 !strconcat(OpcodeStr,
1011 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1013 (OpVT (OpNode RC:$src1, RC:$src2,
1014 (mem_frag addr:$src3))))]>, EVEX_4V;
1016 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1017 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1018 !strconcat(OpcodeStr,
1019 "\t{$src3, $src2, $dst {${mask}}|"
1020 "$dst {${mask}}, $src2, $src3}"),
1022 (OpVT (vselect KRC:$mask,
1023 (OpNode RC:$src1, RC:$src2,
1024 (mem_frag addr:$src3)),
1028 let AddedComplexity = 10 in // Prefer over the rrkz variant
1029 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1030 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1031 !strconcat(OpcodeStr,
1032 "\t{$src3, $src2, $dst {${mask}} {z}|"
1033 "$dst {${mask}} {z}, $src2, $src3}"),
1035 (OpVT (vselect KRC:$mask,
1036 (OpNode RC:$src1, RC:$src2,
1037 (mem_frag addr:$src3)),
1039 (v16i32 immAllZerosV))))))]>,
1043 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
1044 i512mem, X86VPermiv3, v16i32, VK16WM>,
1045 EVEX_V512, EVEX_CD8<32, CD8VF>;
1046 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
1047 i512mem, X86VPermiv3, v8i64, VK8WM>,
1048 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1049 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
1050 i512mem, X86VPermiv3, v16f32, VK16WM>,
1051 EVEX_V512, EVEX_CD8<32, CD8VF>;
1052 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
1053 i512mem, X86VPermiv3, v8f64, VK8WM>,
1054 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1056 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1057 PatFrag mem_frag, X86MemOperand x86memop,
1058 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1059 ValueType MaskVT, RegisterClass MRC> :
1060 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1062 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1063 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1064 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1066 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1067 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1068 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1069 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1072 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1073 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1074 EVEX_V512, EVEX_CD8<32, CD8VF>;
1075 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1076 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1077 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1078 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1079 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1080 EVEX_V512, EVEX_CD8<32, CD8VF>;
1081 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1082 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1083 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1085 //===----------------------------------------------------------------------===//
1086 // AVX-512 - BLEND using mask
1088 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
1089 RegisterClass KRC, RegisterClass RC,
1090 X86MemOperand x86memop, PatFrag mem_frag,
1091 SDNode OpNode, ValueType vt> {
1092 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1093 (ins KRC:$mask, RC:$src1, RC:$src2),
1094 !strconcat(OpcodeStr,
1095 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1096 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
1097 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
1099 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1100 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1101 !strconcat(OpcodeStr,
1102 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1103 []>, EVEX_4V, EVEX_K;
1106 let ExeDomain = SSEPackedSingle in
1107 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1108 VK16WM, VR512, f512mem,
1109 memopv16f32, vselect, v16f32>,
1110 EVEX_CD8<32, CD8VF>, EVEX_V512;
1111 let ExeDomain = SSEPackedDouble in
1112 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1113 VK8WM, VR512, f512mem,
1114 memopv8f64, vselect, v8f64>,
1115 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1117 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1118 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1119 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1120 VR512:$src1, VR512:$src2)>;
1122 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1123 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1124 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1125 VR512:$src1, VR512:$src2)>;
1127 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1128 VK16WM, VR512, f512mem,
1129 memopv16i32, vselect, v16i32>,
1130 EVEX_CD8<32, CD8VF>, EVEX_V512;
1132 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1133 VK8WM, VR512, f512mem,
1134 memopv8i64, vselect, v8i64>,
1135 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1137 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1138 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1139 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1140 VR512:$src1, VR512:$src2)>;
1142 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1143 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1144 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1145 VR512:$src1, VR512:$src2)>;
1147 let Predicates = [HasAVX512] in {
1148 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1149 (v8f32 VR256X:$src2))),
1151 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1152 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1153 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1155 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1156 (v8i32 VR256X:$src2))),
1158 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1159 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1160 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1162 //===----------------------------------------------------------------------===//
1163 // Compare Instructions
1164 //===----------------------------------------------------------------------===//
1166 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1167 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1168 Operand CC, SDNode OpNode, ValueType VT,
1169 PatFrag ld_frag, string asm, string asm_alt> {
1170 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1171 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1172 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1173 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1174 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1175 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1176 [(set VK1:$dst, (OpNode (VT RC:$src1),
1177 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1178 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1179 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1180 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1181 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1182 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1183 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1184 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1188 let Predicates = [HasAVX512] in {
1189 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1190 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1191 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1193 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1194 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1195 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1199 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1200 X86VectorVTInfo _> {
1201 def rr : AVX512BI<opc, MRMSrcReg,
1202 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1203 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1204 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1205 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1207 def rm : AVX512BI<opc, MRMSrcMem,
1208 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1209 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1210 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1211 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1212 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1213 def rrk : AVX512BI<opc, MRMSrcReg,
1214 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1215 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1216 "$dst {${mask}}, $src1, $src2}"),
1217 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1218 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1219 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1221 def rmk : AVX512BI<opc, MRMSrcMem,
1222 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1223 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1224 "$dst {${mask}}, $src1, $src2}"),
1225 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1226 (OpNode (_.VT _.RC:$src1),
1228 (_.LdFrag addr:$src2))))))],
1229 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1232 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1233 X86VectorVTInfo _> :
1234 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1235 let mayLoad = 1 in {
1236 def rmb : AVX512BI<opc, MRMSrcMem,
1237 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1238 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1239 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1240 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1241 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1242 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1243 def rmbk : AVX512BI<opc, MRMSrcMem,
1244 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1245 _.ScalarMemOp:$src2),
1246 !strconcat(OpcodeStr,
1247 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1248 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1249 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1250 (OpNode (_.VT _.RC:$src1),
1252 (_.ScalarLdFrag addr:$src2)))))],
1253 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1257 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1258 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1259 let Predicates = [prd] in
1260 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1263 let Predicates = [prd, HasVLX] in {
1264 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1266 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1271 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1272 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1274 let Predicates = [prd] in
1275 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1278 let Predicates = [prd, HasVLX] in {
1279 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1281 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1286 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1287 avx512vl_i8_info, HasBWI>,
1290 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1291 avx512vl_i16_info, HasBWI>,
1292 EVEX_CD8<16, CD8VF>;
1294 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1295 avx512vl_i32_info, HasAVX512>,
1296 EVEX_CD8<32, CD8VF>;
1298 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1299 avx512vl_i64_info, HasAVX512>,
1300 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1302 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1303 avx512vl_i8_info, HasBWI>,
1306 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1307 avx512vl_i16_info, HasBWI>,
1308 EVEX_CD8<16, CD8VF>;
1310 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1311 avx512vl_i32_info, HasAVX512>,
1312 EVEX_CD8<32, CD8VF>;
1314 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1315 avx512vl_i64_info, HasAVX512>,
1316 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1318 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1319 (COPY_TO_REGCLASS (VPCMPGTDZrr
1320 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1321 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1323 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1324 (COPY_TO_REGCLASS (VPCMPEQDZrr
1325 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1326 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1328 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1329 X86VectorVTInfo _> {
1330 def rri : AVX512AIi8<opc, MRMSrcReg,
1331 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1332 !strconcat("vpcmp${cc}", Suffix,
1333 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1334 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1336 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1338 def rmi : AVX512AIi8<opc, MRMSrcMem,
1339 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1340 !strconcat("vpcmp${cc}", Suffix,
1341 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1342 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1343 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1345 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1346 def rrik : AVX512AIi8<opc, MRMSrcReg,
1347 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1349 !strconcat("vpcmp${cc}", Suffix,
1350 "\t{$src2, $src1, $dst {${mask}}|",
1351 "$dst {${mask}}, $src1, $src2}"),
1352 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1353 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1355 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1357 def rmik : AVX512AIi8<opc, MRMSrcMem,
1358 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1360 !strconcat("vpcmp${cc}", Suffix,
1361 "\t{$src2, $src1, $dst {${mask}}|",
1362 "$dst {${mask}}, $src1, $src2}"),
1363 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1364 (OpNode (_.VT _.RC:$src1),
1365 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1367 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1369 // Accept explicit immediate argument form instead of comparison code.
1370 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1371 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1372 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1373 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1374 "$dst, $src1, $src2, $cc}"),
1375 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1376 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1377 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1378 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1379 "$dst, $src1, $src2, $cc}"),
1380 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1381 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1382 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1384 !strconcat("vpcmp", Suffix,
1385 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1386 "$dst {${mask}}, $src1, $src2, $cc}"),
1387 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1388 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1389 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1391 !strconcat("vpcmp", Suffix,
1392 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1393 "$dst {${mask}}, $src1, $src2, $cc}"),
1394 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1398 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1399 X86VectorVTInfo _> :
1400 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1401 let mayLoad = 1 in {
1402 def rmib : AVX512AIi8<opc, MRMSrcMem,
1403 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1405 !strconcat("vpcmp${cc}", Suffix,
1406 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1407 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1408 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1409 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1411 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1412 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1413 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1414 _.ScalarMemOp:$src2, AVXCC:$cc),
1415 !strconcat("vpcmp${cc}", Suffix,
1416 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1417 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1418 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1419 (OpNode (_.VT _.RC:$src1),
1420 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1422 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1425 // Accept explicit immediate argument form instead of comparison code.
1426 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1427 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1428 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1430 !strconcat("vpcmp", Suffix,
1431 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1432 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1433 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1434 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1435 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1436 _.ScalarMemOp:$src2, i8imm:$cc),
1437 !strconcat("vpcmp", Suffix,
1438 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1439 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1440 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1444 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1445 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1446 let Predicates = [prd] in
1447 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1449 let Predicates = [prd, HasVLX] in {
1450 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1451 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1455 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1456 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1457 let Predicates = [prd] in
1458 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1461 let Predicates = [prd, HasVLX] in {
1462 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1464 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1469 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1470 HasBWI>, EVEX_CD8<8, CD8VF>;
1471 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1472 HasBWI>, EVEX_CD8<8, CD8VF>;
1474 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1475 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1476 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1477 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1479 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1480 HasAVX512>, EVEX_CD8<32, CD8VF>;
1481 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1482 HasAVX512>, EVEX_CD8<32, CD8VF>;
1484 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1485 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1486 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1487 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1489 // avx512_cmp_packed - compare packed instructions
1490 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1491 X86MemOperand x86memop, ValueType vt,
1492 string suffix, Domain d> {
1493 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1494 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1495 !strconcat("vcmp${cc}", suffix,
1496 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1497 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1498 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1499 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1500 !strconcat("vcmp${cc}", suffix,
1501 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1503 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1504 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1505 !strconcat("vcmp${cc}", suffix,
1506 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1508 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1510 // Accept explicit immediate argument form instead of comparison code.
1511 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1512 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1513 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1514 !strconcat("vcmp", suffix,
1515 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1516 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1517 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1518 !strconcat("vcmp", suffix,
1519 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1523 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1524 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1525 EVEX_CD8<32, CD8VF>;
1526 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1527 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1528 EVEX_CD8<64, CD8VF>;
1530 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1531 (COPY_TO_REGCLASS (VCMPPSZrri
1532 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1533 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1535 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1536 (COPY_TO_REGCLASS (VPCMPDZrri
1537 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1538 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1540 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1541 (COPY_TO_REGCLASS (VPCMPUDZrri
1542 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1543 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1546 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1547 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1549 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1550 (I8Imm imm:$cc)), GR16)>;
1552 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1553 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1555 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1556 (I8Imm imm:$cc)), GR8)>;
1558 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1559 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1561 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1562 (I8Imm imm:$cc)), GR16)>;
1564 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1565 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1567 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1568 (I8Imm imm:$cc)), GR8)>;
1570 // Mask register copy, including
1571 // - copy between mask registers
1572 // - load/store mask registers
1573 // - copy from GPR to mask register and vice versa
1575 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1576 string OpcodeStr, RegisterClass KRC,
1577 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1578 let hasSideEffects = 0 in {
1579 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1582 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1583 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1584 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1586 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1587 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1591 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1593 RegisterClass KRC, RegisterClass GRC> {
1594 let hasSideEffects = 0 in {
1595 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1597 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1602 let Predicates = [HasDQI] in
1603 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1605 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1608 let Predicates = [HasAVX512] in
1609 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1611 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1614 let Predicates = [HasBWI] in {
1615 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1616 i32mem>, VEX, PD, VEX_W;
1617 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1621 let Predicates = [HasBWI] in {
1622 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1623 i64mem>, VEX, PS, VEX_W;
1624 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1628 // GR from/to mask register
1629 let Predicates = [HasDQI] in {
1630 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1631 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1632 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1633 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1635 let Predicates = [HasAVX512] in {
1636 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1637 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1638 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1639 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1641 let Predicates = [HasBWI] in {
1642 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1643 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1645 let Predicates = [HasBWI] in {
1646 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1647 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1651 let Predicates = [HasDQI] in {
1652 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1653 (KMOVBmk addr:$dst, VK8:$src)>;
1655 let Predicates = [HasAVX512] in {
1656 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1657 (KMOVWmk addr:$dst, VK16:$src)>;
1658 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1659 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1660 def : Pat<(i1 (load addr:$src)),
1661 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1662 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1663 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1665 let Predicates = [HasBWI] in {
1666 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1667 (KMOVDmk addr:$dst, VK32:$src)>;
1669 let Predicates = [HasBWI] in {
1670 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1671 (KMOVQmk addr:$dst, VK64:$src)>;
1674 let Predicates = [HasAVX512] in {
1675 def : Pat<(i1 (trunc (i64 GR64:$src))),
1676 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1679 def : Pat<(i1 (trunc (i32 GR32:$src))),
1680 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1682 def : Pat<(i1 (trunc (i8 GR8:$src))),
1684 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1686 def : Pat<(i1 (trunc (i16 GR16:$src))),
1688 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1691 def : Pat<(i32 (zext VK1:$src)),
1692 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1693 def : Pat<(i8 (zext VK1:$src)),
1696 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1697 def : Pat<(i64 (zext VK1:$src)),
1698 (AND64ri8 (SUBREG_TO_REG (i64 0),
1699 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1700 def : Pat<(i16 (zext VK1:$src)),
1702 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1704 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1705 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1706 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1707 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1709 let Predicates = [HasBWI] in {
1710 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1711 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1712 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1713 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1717 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1718 let Predicates = [HasAVX512] in {
1719 // GR from/to 8-bit mask without native support
1720 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1722 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1724 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1726 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1729 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1730 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1731 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1732 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1734 let Predicates = [HasBWI] in {
1735 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1736 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1737 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1738 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1741 // Mask unary operation
1743 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1744 RegisterClass KRC, SDPatternOperator OpNode,
1746 let Predicates = [prd] in
1747 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1748 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1749 [(set KRC:$dst, (OpNode KRC:$src))]>;
1752 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1753 SDPatternOperator OpNode> {
1754 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1756 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1757 HasAVX512>, VEX, PS;
1758 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1759 HasBWI>, VEX, PD, VEX_W;
1760 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1761 HasBWI>, VEX, PS, VEX_W;
1764 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1766 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1767 let Predicates = [HasAVX512] in
1768 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1770 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1771 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1773 defm : avx512_mask_unop_int<"knot", "KNOT">;
1775 let Predicates = [HasDQI] in
1776 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1777 let Predicates = [HasAVX512] in
1778 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1779 let Predicates = [HasBWI] in
1780 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1781 let Predicates = [HasBWI] in
1782 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1784 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1785 let Predicates = [HasAVX512] in {
1786 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1787 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1789 def : Pat<(not VK8:$src),
1791 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1794 // Mask binary operation
1795 // - KAND, KANDN, KOR, KXNOR, KXOR
1796 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1797 RegisterClass KRC, SDPatternOperator OpNode,
1799 let Predicates = [prd] in
1800 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1801 !strconcat(OpcodeStr,
1802 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1803 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1806 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1807 SDPatternOperator OpNode> {
1808 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1809 HasDQI>, VEX_4V, VEX_L, PD;
1810 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1811 HasAVX512>, VEX_4V, VEX_L, PS;
1812 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1813 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1814 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1815 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1818 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1819 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1821 let isCommutable = 1 in {
1822 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1823 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1824 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1825 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1827 let isCommutable = 0 in
1828 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1830 def : Pat<(xor VK1:$src1, VK1:$src2),
1831 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1832 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1834 def : Pat<(or VK1:$src1, VK1:$src2),
1835 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1836 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1838 def : Pat<(and VK1:$src1, VK1:$src2),
1839 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1840 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1842 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1843 let Predicates = [HasAVX512] in
1844 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1845 (i16 GR16:$src1), (i16 GR16:$src2)),
1846 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1847 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1848 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1851 defm : avx512_mask_binop_int<"kand", "KAND">;
1852 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1853 defm : avx512_mask_binop_int<"kor", "KOR">;
1854 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1855 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1857 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1858 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1859 let Predicates = [HasAVX512] in
1860 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1862 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1863 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1866 defm : avx512_binop_pat<and, KANDWrr>;
1867 defm : avx512_binop_pat<andn, KANDNWrr>;
1868 defm : avx512_binop_pat<or, KORWrr>;
1869 defm : avx512_binop_pat<xnor, KXNORWrr>;
1870 defm : avx512_binop_pat<xor, KXORWrr>;
1873 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1874 RegisterClass KRC> {
1875 let Predicates = [HasAVX512] in
1876 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1877 !strconcat(OpcodeStr,
1878 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1881 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1882 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1886 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1887 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1888 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1889 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1892 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1893 let Predicates = [HasAVX512] in
1894 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1895 (i16 GR16:$src1), (i16 GR16:$src2)),
1896 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1897 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1898 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1900 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1903 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1905 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1906 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1907 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1908 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1911 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1912 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1916 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1918 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1919 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1920 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1923 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1925 let Predicates = [HasAVX512] in
1926 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1927 !strconcat(OpcodeStr,
1928 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1929 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1932 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1934 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1938 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1939 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1941 // Mask setting all 0s or 1s
1942 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1943 let Predicates = [HasAVX512] in
1944 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1945 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1946 [(set KRC:$dst, (VT Val))]>;
1949 multiclass avx512_mask_setop_w<PatFrag Val> {
1950 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1951 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1954 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1955 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1957 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1958 let Predicates = [HasAVX512] in {
1959 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1960 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1961 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1962 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1963 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1965 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1966 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1968 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1969 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1971 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1972 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1974 let Predicates = [HasVLX] in {
1975 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1976 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1977 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1978 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1979 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1980 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1981 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1982 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1985 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1986 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1988 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1989 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1990 //===----------------------------------------------------------------------===//
1991 // AVX-512 - Aligned and unaligned load and store
1994 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1995 RegisterClass KRC, RegisterClass RC,
1996 ValueType vt, ValueType zvt, X86MemOperand memop,
1997 Domain d, bit IsReMaterializable = 1> {
1998 let hasSideEffects = 0 in {
1999 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2000 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2002 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2003 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2004 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2006 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2007 SchedRW = [WriteLoad] in
2008 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2009 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2010 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2013 let AddedComplexity = 20 in {
2014 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2015 let hasSideEffects = 0 in
2016 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2017 (ins RC:$src0, KRC:$mask, RC:$src1),
2018 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2019 "${dst} {${mask}}, $src1}"),
2020 [(set RC:$dst, (vt (vselect KRC:$mask,
2024 let mayLoad = 1, SchedRW = [WriteLoad] in
2025 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2026 (ins RC:$src0, KRC:$mask, memop:$src1),
2027 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2028 "${dst} {${mask}}, $src1}"),
2031 (vt (bitconvert (ld_frag addr:$src1))),
2035 let mayLoad = 1, SchedRW = [WriteLoad] in
2036 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2037 (ins KRC:$mask, memop:$src),
2038 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2039 "${dst} {${mask}} {z}, $src}"),
2042 (vt (bitconvert (ld_frag addr:$src))),
2043 (vt (bitconvert (zvt immAllZerosV))))))],
2048 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2049 string elty, string elsz, string vsz512,
2050 string vsz256, string vsz128, Domain d,
2051 Predicate prd, bit IsReMaterializable = 1> {
2052 let Predicates = [prd] in
2053 defm Z : avx512_load<opc, OpcodeStr,
2054 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2055 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2056 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2057 !cast<X86MemOperand>(elty##"512mem"), d,
2058 IsReMaterializable>, EVEX_V512;
2060 let Predicates = [prd, HasVLX] in {
2061 defm Z256 : avx512_load<opc, OpcodeStr,
2062 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2063 "v"##vsz256##elty##elsz, "v4i64")),
2064 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2065 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2066 !cast<X86MemOperand>(elty##"256mem"), d,
2067 IsReMaterializable>, EVEX_V256;
2069 defm Z128 : avx512_load<opc, OpcodeStr,
2070 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2071 "v"##vsz128##elty##elsz, "v2i64")),
2072 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2073 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2074 !cast<X86MemOperand>(elty##"128mem"), d,
2075 IsReMaterializable>, EVEX_V128;
2080 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2081 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2082 X86MemOperand memop, Domain d> {
2083 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2084 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2085 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2087 let Constraints = "$src1 = $dst" in
2088 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2089 (ins RC:$src1, KRC:$mask, RC:$src2),
2090 !strconcat(OpcodeStr,
2091 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2093 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2094 (ins KRC:$mask, RC:$src),
2095 !strconcat(OpcodeStr,
2096 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2097 [], d>, EVEX, EVEX_KZ;
2099 let mayStore = 1 in {
2100 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2101 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2102 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2103 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2104 (ins memop:$dst, KRC:$mask, RC:$src),
2105 !strconcat(OpcodeStr,
2106 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2107 [], d>, EVEX, EVEX_K;
2112 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2113 string st_suff_512, string st_suff_256,
2114 string st_suff_128, string elty, string elsz,
2115 string vsz512, string vsz256, string vsz128,
2116 Domain d, Predicate prd> {
2117 let Predicates = [prd] in
2118 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2119 !cast<ValueType>("v"##vsz512##elty##elsz),
2120 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2121 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2123 let Predicates = [prd, HasVLX] in {
2124 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2125 !cast<ValueType>("v"##vsz256##elty##elsz),
2126 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2127 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2129 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2130 !cast<ValueType>("v"##vsz128##elty##elsz),
2131 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2132 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2136 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2137 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2138 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2139 "512", "256", "", "f", "32", "16", "8", "4",
2140 SSEPackedSingle, HasAVX512>,
2141 PS, EVEX_CD8<32, CD8VF>;
2143 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2144 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2145 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2146 "512", "256", "", "f", "64", "8", "4", "2",
2147 SSEPackedDouble, HasAVX512>,
2148 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2150 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2151 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2152 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2153 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2154 PS, EVEX_CD8<32, CD8VF>;
2156 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2157 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2158 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2159 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2160 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2162 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2163 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2164 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2166 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2167 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2168 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2170 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2172 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2174 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2176 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2179 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2180 (VMOVUPSZmrk addr:$ptr,
2181 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2182 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2184 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2185 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2186 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2188 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2189 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2191 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2192 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2194 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2195 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2197 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2198 (bc_v16f32 (v16i32 immAllZerosV)))),
2199 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2201 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2202 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2204 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2205 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2207 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2208 (bc_v8f64 (v16i32 immAllZerosV)))),
2209 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2211 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2212 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2214 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2215 "16", "8", "4", SSEPackedInt, HasAVX512>,
2216 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2217 "512", "256", "", "i", "32", "16", "8", "4",
2218 SSEPackedInt, HasAVX512>,
2219 PD, EVEX_CD8<32, CD8VF>;
2221 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2222 "8", "4", "2", SSEPackedInt, HasAVX512>,
2223 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2224 "512", "256", "", "i", "64", "8", "4", "2",
2225 SSEPackedInt, HasAVX512>,
2226 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2228 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2229 "64", "32", "16", SSEPackedInt, HasBWI>,
2230 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2231 "i", "8", "64", "32", "16", SSEPackedInt,
2232 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2234 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2235 "32", "16", "8", SSEPackedInt, HasBWI>,
2236 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2237 "i", "16", "32", "16", "8", SSEPackedInt,
2238 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2240 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2241 "16", "8", "4", SSEPackedInt, HasAVX512>,
2242 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2243 "i", "32", "16", "8", "4", SSEPackedInt,
2244 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2246 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2247 "8", "4", "2", SSEPackedInt, HasAVX512>,
2248 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2249 "i", "64", "8", "4", "2", SSEPackedInt,
2250 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2252 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2253 (v16i32 immAllZerosV), GR16:$mask)),
2254 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2256 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2257 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2258 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2260 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2262 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2264 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2266 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2269 let AddedComplexity = 20 in {
2270 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2271 (bc_v8i64 (v16i32 immAllZerosV)))),
2272 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2274 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2275 (v8i64 VR512:$src))),
2276 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2279 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2280 (v16i32 immAllZerosV))),
2281 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2283 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2284 (v16i32 VR512:$src))),
2285 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2288 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2289 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2291 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2292 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2294 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2295 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2297 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2298 (bc_v8i64 (v16i32 immAllZerosV)))),
2299 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2301 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2302 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2304 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2305 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2307 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2308 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2310 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2311 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2314 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2315 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2318 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2319 (VMOVDQU32Zmrk addr:$ptr,
2320 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2321 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2323 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2324 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2325 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2328 // Move Int Doubleword to Packed Double Int
2330 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2331 "vmovd\t{$src, $dst|$dst, $src}",
2333 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2335 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2336 "vmovd\t{$src, $dst|$dst, $src}",
2338 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2339 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2340 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2341 "vmovq\t{$src, $dst|$dst, $src}",
2343 (v2i64 (scalar_to_vector GR64:$src)))],
2344 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2345 let isCodeGenOnly = 1 in {
2346 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2347 "vmovq\t{$src, $dst|$dst, $src}",
2348 [(set FR64:$dst, (bitconvert GR64:$src))],
2349 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2350 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2351 "vmovq\t{$src, $dst|$dst, $src}",
2352 [(set GR64:$dst, (bitconvert FR64:$src))],
2353 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2355 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2356 "vmovq\t{$src, $dst|$dst, $src}",
2357 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2358 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2359 EVEX_CD8<64, CD8VT1>;
2361 // Move Int Doubleword to Single Scalar
2363 let isCodeGenOnly = 1 in {
2364 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2365 "vmovd\t{$src, $dst|$dst, $src}",
2366 [(set FR32X:$dst, (bitconvert GR32:$src))],
2367 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2369 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2370 "vmovd\t{$src, $dst|$dst, $src}",
2371 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2372 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2375 // Move doubleword from xmm register to r/m32
2377 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2378 "vmovd\t{$src, $dst|$dst, $src}",
2379 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2380 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2382 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2383 (ins i32mem:$dst, VR128X:$src),
2384 "vmovd\t{$src, $dst|$dst, $src}",
2385 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2386 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2387 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2389 // Move quadword from xmm1 register to r/m64
2391 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2392 "vmovq\t{$src, $dst|$dst, $src}",
2393 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2395 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2396 Requires<[HasAVX512, In64BitMode]>;
2398 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2399 (ins i64mem:$dst, VR128X:$src),
2400 "vmovq\t{$src, $dst|$dst, $src}",
2401 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2402 addr:$dst)], IIC_SSE_MOVDQ>,
2403 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2404 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2406 // Move Scalar Single to Double Int
2408 let isCodeGenOnly = 1 in {
2409 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2411 "vmovd\t{$src, $dst|$dst, $src}",
2412 [(set GR32:$dst, (bitconvert FR32X:$src))],
2413 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2414 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2415 (ins i32mem:$dst, FR32X:$src),
2416 "vmovd\t{$src, $dst|$dst, $src}",
2417 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2418 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2421 // Move Quadword Int to Packed Quadword Int
2423 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2425 "vmovq\t{$src, $dst|$dst, $src}",
2427 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2428 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2430 //===----------------------------------------------------------------------===//
2431 // AVX-512 MOVSS, MOVSD
2432 //===----------------------------------------------------------------------===//
2434 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2435 SDNode OpNode, ValueType vt,
2436 X86MemOperand x86memop, PatFrag mem_pat> {
2437 let hasSideEffects = 0 in {
2438 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2439 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2440 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2441 (scalar_to_vector RC:$src2))))],
2442 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2443 let Constraints = "$src1 = $dst" in
2444 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2445 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2447 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2448 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2449 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2450 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2451 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2453 let mayStore = 1 in {
2454 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2455 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2456 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2458 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2459 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2460 [], IIC_SSE_MOV_S_MR>,
2461 EVEX, VEX_LIG, EVEX_K;
2463 } //hasSideEffects = 0
2466 let ExeDomain = SSEPackedSingle in
2467 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2468 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2470 let ExeDomain = SSEPackedDouble in
2471 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2472 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2474 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2475 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2476 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2478 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2479 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2480 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2482 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2483 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2484 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2486 // For the disassembler
2487 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2488 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2489 (ins VR128X:$src1, FR32X:$src2),
2490 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2492 XS, EVEX_4V, VEX_LIG;
2493 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2494 (ins VR128X:$src1, FR64X:$src2),
2495 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2497 XD, EVEX_4V, VEX_LIG, VEX_W;
2500 let Predicates = [HasAVX512] in {
2501 let AddedComplexity = 15 in {
2502 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2503 // MOVS{S,D} to the lower bits.
2504 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2505 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2506 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2507 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2508 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2509 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2510 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2511 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2513 // Move low f32 and clear high bits.
2514 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2515 (SUBREG_TO_REG (i32 0),
2516 (VMOVSSZrr (v4f32 (V_SET0)),
2517 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2518 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2519 (SUBREG_TO_REG (i32 0),
2520 (VMOVSSZrr (v4i32 (V_SET0)),
2521 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2524 let AddedComplexity = 20 in {
2525 // MOVSSrm zeros the high parts of the register; represent this
2526 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2527 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2528 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2529 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2530 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2531 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2532 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2534 // MOVSDrm zeros the high parts of the register; represent this
2535 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2536 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2537 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2538 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2539 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2540 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2541 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2542 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2543 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2544 def : Pat<(v2f64 (X86vzload addr:$src)),
2545 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2547 // Represent the same patterns above but in the form they appear for
2549 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2550 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2551 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2552 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2553 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2554 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2555 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2556 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2557 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2559 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2560 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2561 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2562 FR32X:$src)), sub_xmm)>;
2563 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2564 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2565 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2566 FR64X:$src)), sub_xmm)>;
2567 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2568 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2569 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2571 // Move low f64 and clear high bits.
2572 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2573 (SUBREG_TO_REG (i32 0),
2574 (VMOVSDZrr (v2f64 (V_SET0)),
2575 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2577 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2578 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2579 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2581 // Extract and store.
2582 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2584 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2585 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2587 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2589 // Shuffle with VMOVSS
2590 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2591 (VMOVSSZrr (v4i32 VR128X:$src1),
2592 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2593 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2594 (VMOVSSZrr (v4f32 VR128X:$src1),
2595 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2598 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2599 (SUBREG_TO_REG (i32 0),
2600 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2601 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2603 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2604 (SUBREG_TO_REG (i32 0),
2605 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2606 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2609 // Shuffle with VMOVSD
2610 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2611 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2612 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2613 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2614 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2615 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2616 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2617 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2620 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2621 (SUBREG_TO_REG (i32 0),
2622 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2623 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2625 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2626 (SUBREG_TO_REG (i32 0),
2627 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2628 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2631 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2632 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2633 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2634 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2635 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2636 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2637 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2638 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2641 let AddedComplexity = 15 in
2642 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2644 "vmovq\t{$src, $dst|$dst, $src}",
2645 [(set VR128X:$dst, (v2i64 (X86vzmovl
2646 (v2i64 VR128X:$src))))],
2647 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2649 let AddedComplexity = 20 in
2650 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2652 "vmovq\t{$src, $dst|$dst, $src}",
2653 [(set VR128X:$dst, (v2i64 (X86vzmovl
2654 (loadv2i64 addr:$src))))],
2655 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2656 EVEX_CD8<8, CD8VT8>;
2658 let Predicates = [HasAVX512] in {
2659 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2660 let AddedComplexity = 20 in {
2661 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2662 (VMOVDI2PDIZrm addr:$src)>;
2663 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2664 (VMOV64toPQIZrr GR64:$src)>;
2665 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2666 (VMOVDI2PDIZrr GR32:$src)>;
2668 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2669 (VMOVDI2PDIZrm addr:$src)>;
2670 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2671 (VMOVDI2PDIZrm addr:$src)>;
2672 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2673 (VMOVZPQILo2PQIZrm addr:$src)>;
2674 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2675 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2676 def : Pat<(v2i64 (X86vzload addr:$src)),
2677 (VMOVZPQILo2PQIZrm addr:$src)>;
2680 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2681 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2682 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2683 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2684 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2685 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2686 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2689 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2690 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2692 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2693 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2695 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2696 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2698 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2699 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2701 //===----------------------------------------------------------------------===//
2702 // AVX-512 - Non-temporals
2703 //===----------------------------------------------------------------------===//
2704 let SchedRW = [WriteLoad] in {
2705 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2706 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2707 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2708 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2709 EVEX_CD8<64, CD8VF>;
2711 let Predicates = [HasAVX512, HasVLX] in {
2712 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2714 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2715 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2716 EVEX_CD8<64, CD8VF>;
2718 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2720 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2721 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2722 EVEX_CD8<64, CD8VF>;
2726 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2727 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2728 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2729 let SchedRW = [WriteStore], mayStore = 1,
2730 AddedComplexity = 400 in
2731 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2732 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2733 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2736 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2737 string elty, string elsz, string vsz512,
2738 string vsz256, string vsz128, Domain d,
2739 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2740 let Predicates = [prd] in
2741 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2742 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2743 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2746 let Predicates = [prd, HasVLX] in {
2747 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2748 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2749 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2752 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2753 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2754 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2759 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2760 "i", "64", "8", "4", "2", SSEPackedInt,
2761 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2763 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2764 "f", "64", "8", "4", "2", SSEPackedDouble,
2765 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2767 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2768 "f", "32", "16", "8", "4", SSEPackedSingle,
2769 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2771 //===----------------------------------------------------------------------===//
2772 // AVX-512 - Integer arithmetic
2774 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2775 X86VectorVTInfo _, OpndItins itins,
2776 bit IsCommutable = 0> {
2777 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2778 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2779 "$src2, $src1", "$src1, $src2",
2780 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2781 "", itins.rr, IsCommutable>,
2782 AVX512BIBase, EVEX_4V;
2785 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2786 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2787 "$src2, $src1", "$src1, $src2",
2788 (_.VT (OpNode _.RC:$src1,
2789 (bitconvert (_.LdFrag addr:$src2)))),
2791 AVX512BIBase, EVEX_4V;
2794 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2795 X86VectorVTInfo _, OpndItins itins,
2796 bit IsCommutable = 0> :
2797 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2799 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2800 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2801 "${src2}"##_.BroadcastStr##", $src1",
2802 "$src1, ${src2}"##_.BroadcastStr,
2803 (_.VT (OpNode _.RC:$src1,
2805 (_.ScalarLdFrag addr:$src2)))),
2807 AVX512BIBase, EVEX_4V, EVEX_B;
2810 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2811 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2812 Predicate prd, bit IsCommutable = 0> {
2813 let Predicates = [prd] in
2814 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2815 IsCommutable>, EVEX_V512;
2817 let Predicates = [prd, HasVLX] in {
2818 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2819 IsCommutable>, EVEX_V256;
2820 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2821 IsCommutable>, EVEX_V128;
2825 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2826 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2827 Predicate prd, bit IsCommutable = 0> {
2828 let Predicates = [prd] in
2829 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2830 IsCommutable>, EVEX_V512;
2832 let Predicates = [prd, HasVLX] in {
2833 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2834 IsCommutable>, EVEX_V256;
2835 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2836 IsCommutable>, EVEX_V128;
2840 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2841 OpndItins itins, Predicate prd,
2842 bit IsCommutable = 0> {
2843 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2844 itins, prd, IsCommutable>,
2845 VEX_W, EVEX_CD8<64, CD8VF>;
2848 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2849 OpndItins itins, Predicate prd,
2850 bit IsCommutable = 0> {
2851 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2852 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2855 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2856 OpndItins itins, Predicate prd,
2857 bit IsCommutable = 0> {
2858 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2859 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2862 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2863 OpndItins itins, Predicate prd,
2864 bit IsCommutable = 0> {
2865 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2866 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2869 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2870 SDNode OpNode, OpndItins itins, Predicate prd,
2871 bit IsCommutable = 0> {
2872 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2875 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2879 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2880 SDNode OpNode, OpndItins itins, Predicate prd,
2881 bit IsCommutable = 0> {
2882 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2885 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2889 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2890 bits<8> opc_d, bits<8> opc_q,
2891 string OpcodeStr, SDNode OpNode,
2892 OpndItins itins, bit IsCommutable = 0> {
2893 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2894 itins, HasAVX512, IsCommutable>,
2895 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2896 itins, HasBWI, IsCommutable>;
2899 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2900 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2901 PatFrag memop_frag, X86MemOperand x86memop,
2902 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2903 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2904 let isCommutable = IsCommutable in
2906 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2907 (ins RC:$src1, RC:$src2),
2908 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2910 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2911 (ins KRC:$mask, RC:$src1, RC:$src2),
2912 !strconcat(OpcodeStr,
2913 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2914 [], itins.rr>, EVEX_4V, EVEX_K;
2915 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2916 (ins KRC:$mask, RC:$src1, RC:$src2),
2917 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
2918 "|$dst {${mask}} {z}, $src1, $src2}"),
2919 [], itins.rr>, EVEX_4V, EVEX_KZ;
2921 let mayLoad = 1 in {
2922 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2923 (ins RC:$src1, x86memop:$src2),
2924 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2926 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2927 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2928 !strconcat(OpcodeStr,
2929 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2930 [], itins.rm>, EVEX_4V, EVEX_K;
2931 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2932 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2933 !strconcat(OpcodeStr,
2934 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2935 [], itins.rm>, EVEX_4V, EVEX_KZ;
2936 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2937 (ins RC:$src1, x86scalar_mop:$src2),
2938 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2939 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2940 [], itins.rm>, EVEX_4V, EVEX_B;
2941 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2942 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2943 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2944 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2946 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2947 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2948 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2949 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2950 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2952 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2956 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2957 SSE_INTALU_ITINS_P, 1>;
2958 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2959 SSE_INTALU_ITINS_P, 0>;
2960 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2961 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2962 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2963 SSE_INTALU_ITINS_P, HasBWI, 1>;
2964 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2965 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2967 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2968 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2969 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2970 EVEX_CD8<64, CD8VF>, VEX_W;
2972 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2973 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2974 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2976 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2977 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2979 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2980 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2981 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2982 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2983 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2984 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2986 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2987 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2988 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2989 SSE_INTALU_ITINS_P, HasBWI, 1>;
2990 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2991 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2993 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2994 SSE_INTALU_ITINS_P, HasBWI, 1>;
2995 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2996 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2997 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2998 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3000 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3001 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3002 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3003 SSE_INTALU_ITINS_P, HasBWI, 1>;
3004 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3005 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3007 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3008 SSE_INTALU_ITINS_P, HasBWI, 1>;
3009 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3010 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3011 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3012 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3014 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3015 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3016 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3017 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3018 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3019 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3020 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3021 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3022 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3023 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3024 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3025 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3026 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3027 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3028 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3029 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3030 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3031 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3032 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3033 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3034 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3035 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3036 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3037 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3038 //===----------------------------------------------------------------------===//
3039 // AVX-512 - Unpack Instructions
3040 //===----------------------------------------------------------------------===//
3042 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3043 PatFrag mem_frag, RegisterClass RC,
3044 X86MemOperand x86memop, string asm,
3046 def rr : AVX512PI<opc, MRMSrcReg,
3047 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3049 (vt (OpNode RC:$src1, RC:$src2)))],
3051 def rm : AVX512PI<opc, MRMSrcMem,
3052 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3054 (vt (OpNode RC:$src1,
3055 (bitconvert (mem_frag addr:$src2)))))],
3059 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3060 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3061 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3062 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3063 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3064 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3065 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3066 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3067 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3068 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3069 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3070 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3072 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3073 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3074 X86MemOperand x86memop> {
3075 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3076 (ins RC:$src1, RC:$src2),
3077 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3078 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3079 IIC_SSE_UNPCK>, EVEX_4V;
3080 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3081 (ins RC:$src1, x86memop:$src2),
3082 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3083 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3084 (bitconvert (memop_frag addr:$src2)))))],
3085 IIC_SSE_UNPCK>, EVEX_4V;
3087 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3088 VR512, memopv16i32, i512mem>, EVEX_V512,
3089 EVEX_CD8<32, CD8VF>;
3090 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3091 VR512, memopv8i64, i512mem>, EVEX_V512,
3092 VEX_W, EVEX_CD8<64, CD8VF>;
3093 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3094 VR512, memopv16i32, i512mem>, EVEX_V512,
3095 EVEX_CD8<32, CD8VF>;
3096 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3097 VR512, memopv8i64, i512mem>, EVEX_V512,
3098 VEX_W, EVEX_CD8<64, CD8VF>;
3099 //===----------------------------------------------------------------------===//
3103 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3104 SDNode OpNode, PatFrag mem_frag,
3105 X86MemOperand x86memop, ValueType OpVT> {
3106 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3107 (ins RC:$src1, i8imm:$src2),
3108 !strconcat(OpcodeStr,
3109 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3111 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3113 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3114 (ins x86memop:$src1, i8imm:$src2),
3115 !strconcat(OpcodeStr,
3116 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3118 (OpVT (OpNode (mem_frag addr:$src1),
3119 (i8 imm:$src2))))]>, EVEX;
3122 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3123 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3125 //===----------------------------------------------------------------------===//
3126 // AVX-512 Logical Instructions
3127 //===----------------------------------------------------------------------===//
3129 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3130 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3131 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3132 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3133 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3134 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3135 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3136 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3138 //===----------------------------------------------------------------------===//
3139 // AVX-512 FP arithmetic
3140 //===----------------------------------------------------------------------===//
3142 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3144 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3145 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3146 EVEX_CD8<32, CD8VT1>;
3147 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3148 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3149 EVEX_CD8<64, CD8VT1>;
3152 let isCommutable = 1 in {
3153 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3154 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3155 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3156 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3158 let isCommutable = 0 in {
3159 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3160 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3163 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3164 X86VectorVTInfo _, bit IsCommutable> {
3165 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3166 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3167 "$src2, $src1", "$src1, $src2",
3168 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3169 let mayLoad = 1 in {
3170 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3171 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3172 "$src2, $src1", "$src1, $src2",
3173 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3174 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3175 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3176 "${src2}"##_.BroadcastStr##", $src1",
3177 "$src1, ${src2}"##_.BroadcastStr,
3178 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3179 (_.ScalarLdFrag addr:$src2))))>,
3184 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3185 bit IsCommutable = 0> {
3186 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3187 IsCommutable>, EVEX_V512, PS,
3188 EVEX_CD8<32, CD8VF>;
3189 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3190 IsCommutable>, EVEX_V512, PD, VEX_W,
3191 EVEX_CD8<64, CD8VF>;
3193 // Define only if AVX512VL feature is present.
3194 let Predicates = [HasVLX] in {
3195 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3196 IsCommutable>, EVEX_V128, PS,
3197 EVEX_CD8<32, CD8VF>;
3198 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3199 IsCommutable>, EVEX_V256, PS,
3200 EVEX_CD8<32, CD8VF>;
3201 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3202 IsCommutable>, EVEX_V128, PD, VEX_W,
3203 EVEX_CD8<64, CD8VF>;
3204 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3205 IsCommutable>, EVEX_V256, PD, VEX_W,
3206 EVEX_CD8<64, CD8VF>;
3210 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3211 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3212 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3213 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3214 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3215 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3217 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3218 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3219 (i16 -1), FROUND_CURRENT)),
3220 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3222 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3223 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3224 (i8 -1), FROUND_CURRENT)),
3225 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3227 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3228 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3229 (i16 -1), FROUND_CURRENT)),
3230 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3232 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3233 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3234 (i8 -1), FROUND_CURRENT)),
3235 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3236 //===----------------------------------------------------------------------===//
3237 // AVX-512 VPTESTM instructions
3238 //===----------------------------------------------------------------------===//
3240 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3241 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3242 SDNode OpNode, ValueType vt> {
3243 def rr : AVX512PI<opc, MRMSrcReg,
3244 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3245 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3246 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3247 SSEPackedInt>, EVEX_4V;
3248 def rm : AVX512PI<opc, MRMSrcMem,
3249 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3251 [(set KRC:$dst, (OpNode (vt RC:$src1),
3252 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3255 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3256 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3257 EVEX_CD8<32, CD8VF>;
3258 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3259 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3260 EVEX_CD8<64, CD8VF>;
3262 let Predicates = [HasCDI] in {
3263 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3264 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3265 EVEX_CD8<32, CD8VF>;
3266 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3267 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3268 EVEX_CD8<64, CD8VF>;
3271 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3272 (v16i32 VR512:$src2), (i16 -1))),
3273 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3275 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3276 (v8i64 VR512:$src2), (i8 -1))),
3277 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3279 //===----------------------------------------------------------------------===//
3280 // AVX-512 Shift instructions
3281 //===----------------------------------------------------------------------===//
3282 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3283 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3284 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3285 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3286 "$src2, $src1", "$src1, $src2",
3287 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3288 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3289 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3290 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3291 "$src2, $src1", "$src1, $src2",
3292 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3293 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3296 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3297 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3298 // src2 is always 128-bit
3299 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3300 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3301 "$src2, $src1", "$src1, $src2",
3302 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3303 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3304 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3305 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3306 "$src2, $src1", "$src1, $src2",
3307 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3308 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3311 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3312 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3313 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3316 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3318 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3319 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3320 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3321 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3324 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3326 EVEX_V512, EVEX_CD8<32, CD8VF>;
3327 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3328 v8i64_info>, EVEX_V512,
3329 EVEX_CD8<64, CD8VF>, VEX_W;
3331 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3332 v16i32_info>, EVEX_V512,
3333 EVEX_CD8<32, CD8VF>;
3334 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3335 v8i64_info>, EVEX_V512,
3336 EVEX_CD8<64, CD8VF>, VEX_W;
3338 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3340 EVEX_V512, EVEX_CD8<32, CD8VF>;
3341 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3342 v8i64_info>, EVEX_V512,
3343 EVEX_CD8<64, CD8VF>, VEX_W;
3345 defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3346 defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3347 defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3349 //===-------------------------------------------------------------------===//
3350 // Variable Bit Shifts
3351 //===-------------------------------------------------------------------===//
3352 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3353 X86VectorVTInfo _> {
3354 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3355 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3356 "$src2, $src1", "$src1, $src2",
3357 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3358 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3359 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3360 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3361 "$src2, $src1", "$src1, $src2",
3362 (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2))),
3363 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
3366 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3367 AVX512VLVectorVTInfo _> {
3368 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3371 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3373 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3374 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
3375 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3376 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3379 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
3380 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
3381 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
3383 //===----------------------------------------------------------------------===//
3384 // AVX-512 - MOVDDUP
3385 //===----------------------------------------------------------------------===//
3387 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3388 X86MemOperand x86memop, PatFrag memop_frag> {
3389 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3390 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3391 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3392 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3393 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3395 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3398 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3399 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3400 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3401 (VMOVDDUPZrm addr:$src)>;
3403 //===---------------------------------------------------------------------===//
3404 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3405 //===---------------------------------------------------------------------===//
3406 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3407 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3408 X86MemOperand x86memop> {
3409 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3410 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3411 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3413 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3414 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3415 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3418 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3419 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3420 EVEX_CD8<32, CD8VF>;
3421 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3422 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3423 EVEX_CD8<32, CD8VF>;
3425 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3426 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3427 (VMOVSHDUPZrm addr:$src)>;
3428 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3429 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3430 (VMOVSLDUPZrm addr:$src)>;
3432 //===----------------------------------------------------------------------===//
3433 // Move Low to High and High to Low packed FP Instructions
3434 //===----------------------------------------------------------------------===//
3435 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3436 (ins VR128X:$src1, VR128X:$src2),
3437 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3438 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3439 IIC_SSE_MOV_LH>, EVEX_4V;
3440 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3441 (ins VR128X:$src1, VR128X:$src2),
3442 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3443 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3444 IIC_SSE_MOV_LH>, EVEX_4V;
3446 let Predicates = [HasAVX512] in {
3448 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3449 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3450 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3451 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3454 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3455 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3458 //===----------------------------------------------------------------------===//
3459 // FMA - Fused Multiply Operations
3462 let Constraints = "$src1 = $dst" in {
3463 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3464 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3465 SDPatternOperator OpNode = null_frag> {
3466 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3467 (ins _.RC:$src2, _.RC:$src3),
3468 OpcodeStr, "$src3, $src2", "$src2, $src3",
3469 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3473 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3474 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3475 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3476 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3477 (_.MemOpFrag addr:$src3))))]>;
3478 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3479 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3480 !strconcat(OpcodeStr, "\t{${src3}", _.BroadcastStr,
3481 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3482 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3483 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3485 } // Constraints = "$src1 = $dst"
3487 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3488 string OpcodeStr, X86VectorVTInfo VTI,
3489 SDPatternOperator OpNode> {
3490 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3492 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3494 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3496 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3499 let ExeDomain = SSEPackedSingle in {
3500 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3501 v16f32_info, X86Fmadd>;
3502 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3503 v16f32_info, X86Fmsub>;
3504 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3505 v16f32_info, X86Fmaddsub>;
3506 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3507 v16f32_info, X86Fmsubadd>;
3508 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3509 v16f32_info, X86Fnmadd>;
3510 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3511 v16f32_info, X86Fnmsub>;
3513 let ExeDomain = SSEPackedDouble in {
3514 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3515 v8f64_info, X86Fmadd>, VEX_W;
3516 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3517 v8f64_info, X86Fmsub>, VEX_W;
3518 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3519 v8f64_info, X86Fmaddsub>, VEX_W;
3520 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3521 v8f64_info, X86Fmsubadd>, VEX_W;
3522 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3523 v8f64_info, X86Fnmadd>, VEX_W;
3524 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3525 v8f64_info, X86Fnmsub>, VEX_W;
3528 let Constraints = "$src1 = $dst" in {
3529 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3530 X86VectorVTInfo _> {
3532 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3533 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3534 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3535 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3537 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3538 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3539 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3540 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3542 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3543 (_.ScalarLdFrag addr:$src2))),
3544 _.RC:$src3))]>, EVEX_B;
3546 } // Constraints = "$src1 = $dst"
3549 let ExeDomain = SSEPackedSingle in {
3550 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3552 EVEX_V512, EVEX_CD8<32, CD8VF>;
3553 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3555 EVEX_V512, EVEX_CD8<32, CD8VF>;
3556 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3558 EVEX_V512, EVEX_CD8<32, CD8VF>;
3559 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3561 EVEX_V512, EVEX_CD8<32, CD8VF>;
3562 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3564 EVEX_V512, EVEX_CD8<32, CD8VF>;
3565 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3567 EVEX_V512, EVEX_CD8<32, CD8VF>;
3569 let ExeDomain = SSEPackedDouble in {
3570 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3572 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3573 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3575 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3576 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3578 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3579 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3581 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3582 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3584 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3585 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3587 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3591 let Constraints = "$src1 = $dst" in {
3592 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3593 RegisterClass RC, ValueType OpVT,
3594 X86MemOperand x86memop, Operand memop,
3596 let isCommutable = 1 in
3597 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3598 (ins RC:$src1, RC:$src2, RC:$src3),
3599 !strconcat(OpcodeStr,
3600 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3602 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3604 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3605 (ins RC:$src1, RC:$src2, f128mem:$src3),
3606 !strconcat(OpcodeStr,
3607 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3609 (OpVT (OpNode RC:$src2, RC:$src1,
3610 (mem_frag addr:$src3))))]>;
3613 } // Constraints = "$src1 = $dst"
3615 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3616 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3617 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3618 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3619 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3620 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3621 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3622 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3623 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3624 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3625 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3626 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3627 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3628 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3629 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3630 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3632 //===----------------------------------------------------------------------===//
3633 // AVX-512 Scalar convert from sign integer to float/double
3634 //===----------------------------------------------------------------------===//
3636 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3637 X86MemOperand x86memop, string asm> {
3638 let hasSideEffects = 0 in {
3639 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3640 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3643 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3644 (ins DstRC:$src1, x86memop:$src),
3645 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3647 } // hasSideEffects = 0
3649 let Predicates = [HasAVX512] in {
3650 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3651 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3652 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3653 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3654 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3655 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3656 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3657 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3659 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3660 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3661 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3662 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3663 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3664 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3665 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3666 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3668 def : Pat<(f32 (sint_to_fp GR32:$src)),
3669 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3670 def : Pat<(f32 (sint_to_fp GR64:$src)),
3671 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3672 def : Pat<(f64 (sint_to_fp GR32:$src)),
3673 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3674 def : Pat<(f64 (sint_to_fp GR64:$src)),
3675 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3677 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3678 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3679 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3680 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3681 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3682 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3683 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3684 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3686 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3687 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3688 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3689 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3690 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3691 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3692 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3693 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3695 def : Pat<(f32 (uint_to_fp GR32:$src)),
3696 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3697 def : Pat<(f32 (uint_to_fp GR64:$src)),
3698 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3699 def : Pat<(f64 (uint_to_fp GR32:$src)),
3700 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3701 def : Pat<(f64 (uint_to_fp GR64:$src)),
3702 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3705 //===----------------------------------------------------------------------===//
3706 // AVX-512 Scalar convert from float/double to integer
3707 //===----------------------------------------------------------------------===//
3708 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3709 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3711 let hasSideEffects = 0 in {
3712 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3713 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3714 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3715 Requires<[HasAVX512]>;
3717 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3718 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3719 Requires<[HasAVX512]>;
3720 } // hasSideEffects = 0
3722 let Predicates = [HasAVX512] in {
3723 // Convert float/double to signed/unsigned int 32/64
3724 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3725 ssmem, sse_load_f32, "cvtss2si">,
3726 XS, EVEX_CD8<32, CD8VT1>;
3727 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3728 ssmem, sse_load_f32, "cvtss2si">,
3729 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3730 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3731 ssmem, sse_load_f32, "cvtss2usi">,
3732 XS, EVEX_CD8<32, CD8VT1>;
3733 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3734 int_x86_avx512_cvtss2usi64, ssmem,
3735 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3736 EVEX_CD8<32, CD8VT1>;
3737 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3738 sdmem, sse_load_f64, "cvtsd2si">,
3739 XD, EVEX_CD8<64, CD8VT1>;
3740 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3741 sdmem, sse_load_f64, "cvtsd2si">,
3742 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3743 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3744 sdmem, sse_load_f64, "cvtsd2usi">,
3745 XD, EVEX_CD8<64, CD8VT1>;
3746 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3747 int_x86_avx512_cvtsd2usi64, sdmem,
3748 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3749 EVEX_CD8<64, CD8VT1>;
3751 let isCodeGenOnly = 1 in {
3752 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3753 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3754 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3755 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3756 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3757 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3758 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3759 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3760 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3761 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3762 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3763 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3765 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3766 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3767 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3768 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3769 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3770 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3771 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3772 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3773 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3774 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3775 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3776 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3777 } // isCodeGenOnly = 1
3779 // Convert float/double to signed/unsigned int 32/64 with truncation
3780 let isCodeGenOnly = 1 in {
3781 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3782 ssmem, sse_load_f32, "cvttss2si">,
3783 XS, EVEX_CD8<32, CD8VT1>;
3784 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3785 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3786 "cvttss2si">, XS, VEX_W,
3787 EVEX_CD8<32, CD8VT1>;
3788 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3789 sdmem, sse_load_f64, "cvttsd2si">, XD,
3790 EVEX_CD8<64, CD8VT1>;
3791 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3792 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3793 "cvttsd2si">, XD, VEX_W,
3794 EVEX_CD8<64, CD8VT1>;
3795 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3796 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3797 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3798 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3799 int_x86_avx512_cvttss2usi64, ssmem,
3800 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3801 EVEX_CD8<32, CD8VT1>;
3802 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3803 int_x86_avx512_cvttsd2usi,
3804 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3805 EVEX_CD8<64, CD8VT1>;
3806 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3807 int_x86_avx512_cvttsd2usi64, sdmem,
3808 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3809 EVEX_CD8<64, CD8VT1>;
3810 } // isCodeGenOnly = 1
3812 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3813 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3815 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3816 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3817 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3818 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3819 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3820 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3823 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3824 loadf32, "cvttss2si">, XS,
3825 EVEX_CD8<32, CD8VT1>;
3826 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3827 loadf32, "cvttss2usi">, XS,
3828 EVEX_CD8<32, CD8VT1>;
3829 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3830 loadf32, "cvttss2si">, XS, VEX_W,
3831 EVEX_CD8<32, CD8VT1>;
3832 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3833 loadf32, "cvttss2usi">, XS, VEX_W,
3834 EVEX_CD8<32, CD8VT1>;
3835 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3836 loadf64, "cvttsd2si">, XD,
3837 EVEX_CD8<64, CD8VT1>;
3838 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3839 loadf64, "cvttsd2usi">, XD,
3840 EVEX_CD8<64, CD8VT1>;
3841 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3842 loadf64, "cvttsd2si">, XD, VEX_W,
3843 EVEX_CD8<64, CD8VT1>;
3844 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3845 loadf64, "cvttsd2usi">, XD, VEX_W,
3846 EVEX_CD8<64, CD8VT1>;
3848 //===----------------------------------------------------------------------===//
3849 // AVX-512 Convert form float to double and back
3850 //===----------------------------------------------------------------------===//
3851 let hasSideEffects = 0 in {
3852 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3853 (ins FR32X:$src1, FR32X:$src2),
3854 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3855 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3857 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3858 (ins FR32X:$src1, f32mem:$src2),
3859 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3860 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3861 EVEX_CD8<32, CD8VT1>;
3863 // Convert scalar double to scalar single
3864 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3865 (ins FR64X:$src1, FR64X:$src2),
3866 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3867 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3869 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3870 (ins FR64X:$src1, f64mem:$src2),
3871 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3872 []>, EVEX_4V, VEX_LIG, VEX_W,
3873 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3876 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3877 Requires<[HasAVX512]>;
3878 def : Pat<(fextend (loadf32 addr:$src)),
3879 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3881 def : Pat<(extloadf32 addr:$src),
3882 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3883 Requires<[HasAVX512, OptForSize]>;
3885 def : Pat<(extloadf32 addr:$src),
3886 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3887 Requires<[HasAVX512, OptForSpeed]>;
3889 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3890 Requires<[HasAVX512]>;
3892 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3893 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3894 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3896 let hasSideEffects = 0 in {
3897 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3898 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3900 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3901 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3902 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3903 [], d>, EVEX, EVEX_B, EVEX_RC;
3905 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3906 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3908 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3909 } // hasSideEffects = 0
3912 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3913 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3914 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3916 let hasSideEffects = 0 in {
3917 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3918 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3920 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3922 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3923 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3925 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3926 } // hasSideEffects = 0
3929 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3930 memopv8f64, f512mem, v8f32, v8f64,
3931 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3932 EVEX_CD8<64, CD8VF>;
3934 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3935 memopv4f64, f256mem, v8f64, v8f32,
3936 SSEPackedDouble>, EVEX_V512, PS,
3937 EVEX_CD8<32, CD8VH>;
3938 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3939 (VCVTPS2PDZrm addr:$src)>;
3941 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3942 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3943 (VCVTPD2PSZrr VR512:$src)>;
3945 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3946 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3947 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3949 //===----------------------------------------------------------------------===//
3950 // AVX-512 Vector convert from sign integer to float/double
3951 //===----------------------------------------------------------------------===//
3953 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3954 memopv8i64, i512mem, v16f32, v16i32,
3955 SSEPackedSingle>, EVEX_V512, PS,
3956 EVEX_CD8<32, CD8VF>;
3958 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3959 memopv4i64, i256mem, v8f64, v8i32,
3960 SSEPackedDouble>, EVEX_V512, XS,
3961 EVEX_CD8<32, CD8VH>;
3963 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3964 memopv16f32, f512mem, v16i32, v16f32,
3965 SSEPackedSingle>, EVEX_V512, XS,
3966 EVEX_CD8<32, CD8VF>;
3968 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3969 memopv8f64, f512mem, v8i32, v8f64,
3970 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3971 EVEX_CD8<64, CD8VF>;
3973 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3974 memopv16f32, f512mem, v16i32, v16f32,
3975 SSEPackedSingle>, EVEX_V512, PS,
3976 EVEX_CD8<32, CD8VF>;
3978 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3979 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3980 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3981 (VCVTTPS2UDQZrr VR512:$src)>;
3983 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3984 memopv8f64, f512mem, v8i32, v8f64,
3985 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3986 EVEX_CD8<64, CD8VF>;
3988 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3989 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3990 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3991 (VCVTTPD2UDQZrr VR512:$src)>;
3993 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3994 memopv4i64, f256mem, v8f64, v8i32,
3995 SSEPackedDouble>, EVEX_V512, XS,
3996 EVEX_CD8<32, CD8VH>;
3998 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3999 memopv16i32, f512mem, v16f32, v16i32,
4000 SSEPackedSingle>, EVEX_V512, XD,
4001 EVEX_CD8<32, CD8VF>;
4003 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4004 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4005 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4007 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4008 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4009 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4011 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4012 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4013 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4015 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4016 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4017 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4019 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4020 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4021 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4023 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4024 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4025 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4026 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4027 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4028 (VCVTDQ2PDZrr VR256X:$src)>;
4029 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4030 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4031 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4032 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4033 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4034 (VCVTUDQ2PDZrr VR256X:$src)>;
4036 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4037 RegisterClass DstRC, PatFrag mem_frag,
4038 X86MemOperand x86memop, Domain d> {
4039 let hasSideEffects = 0 in {
4040 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4041 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4043 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4044 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4045 [], d>, EVEX, EVEX_B, EVEX_RC;
4047 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4048 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4050 } // hasSideEffects = 0
4053 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4054 memopv16f32, f512mem, SSEPackedSingle>, PD,
4055 EVEX_V512, EVEX_CD8<32, CD8VF>;
4056 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4057 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4058 EVEX_V512, EVEX_CD8<64, CD8VF>;
4060 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4061 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4062 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4064 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4065 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4066 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4068 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4069 memopv16f32, f512mem, SSEPackedSingle>,
4070 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4071 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4072 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4073 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4075 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4076 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4077 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4079 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4080 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4081 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4083 let Predicates = [HasAVX512] in {
4084 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4085 (VCVTPD2PSZrm addr:$src)>;
4086 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4087 (VCVTPS2PDZrm addr:$src)>;
4090 //===----------------------------------------------------------------------===//
4091 // Half precision conversion instructions
4092 //===----------------------------------------------------------------------===//
4093 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4094 X86MemOperand x86memop> {
4095 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4096 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4098 let hasSideEffects = 0, mayLoad = 1 in
4099 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4100 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4103 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4104 X86MemOperand x86memop> {
4105 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4106 (ins srcRC:$src1, i32i8imm:$src2),
4107 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4109 let hasSideEffects = 0, mayStore = 1 in
4110 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4111 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
4112 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4115 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4116 EVEX_CD8<32, CD8VH>;
4117 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4118 EVEX_CD8<32, CD8VH>;
4120 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4121 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4122 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4124 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4125 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4126 (VCVTPH2PSZrr VR256X:$src)>;
4128 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4129 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4130 "ucomiss">, PS, EVEX, VEX_LIG,
4131 EVEX_CD8<32, CD8VT1>;
4132 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4133 "ucomisd">, PD, EVEX,
4134 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4135 let Pattern = []<dag> in {
4136 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4137 "comiss">, PS, EVEX, VEX_LIG,
4138 EVEX_CD8<32, CD8VT1>;
4139 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4140 "comisd">, PD, EVEX,
4141 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4143 let isCodeGenOnly = 1 in {
4144 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4145 load, "ucomiss">, PS, EVEX, VEX_LIG,
4146 EVEX_CD8<32, CD8VT1>;
4147 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4148 load, "ucomisd">, PD, EVEX,
4149 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4151 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4152 load, "comiss">, PS, EVEX, VEX_LIG,
4153 EVEX_CD8<32, CD8VT1>;
4154 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4155 load, "comisd">, PD, EVEX,
4156 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4160 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4161 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4162 X86MemOperand x86memop> {
4163 let hasSideEffects = 0 in {
4164 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4165 (ins RC:$src1, RC:$src2),
4166 !strconcat(OpcodeStr,
4167 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4168 let mayLoad = 1 in {
4169 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4170 (ins RC:$src1, x86memop:$src2),
4171 !strconcat(OpcodeStr,
4172 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4177 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4178 EVEX_CD8<32, CD8VT1>;
4179 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4180 VEX_W, EVEX_CD8<64, CD8VT1>;
4181 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4182 EVEX_CD8<32, CD8VT1>;
4183 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4184 VEX_W, EVEX_CD8<64, CD8VT1>;
4186 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4187 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4188 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4189 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4191 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4192 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4193 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4194 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4196 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4197 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4198 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4199 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4201 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4202 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4203 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4204 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4206 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4207 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4208 X86VectorVTInfo _> {
4209 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4210 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4211 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4212 let mayLoad = 1 in {
4213 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4214 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4216 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4217 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4218 (ins _.ScalarMemOp:$src), OpcodeStr,
4219 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4221 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4226 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4227 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4228 EVEX_V512, EVEX_CD8<32, CD8VF>;
4229 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4230 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4232 // Define only if AVX512VL feature is present.
4233 let Predicates = [HasVLX] in {
4234 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4235 OpNode, v4f32x_info>,
4236 EVEX_V128, EVEX_CD8<32, CD8VF>;
4237 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4238 OpNode, v8f32x_info>,
4239 EVEX_V256, EVEX_CD8<32, CD8VF>;
4240 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4241 OpNode, v2f64x_info>,
4242 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4243 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4244 OpNode, v4f64x_info>,
4245 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4249 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4250 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4252 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4253 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4254 (VRSQRT14PSZr VR512:$src)>;
4255 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4256 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4257 (VRSQRT14PDZr VR512:$src)>;
4259 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4260 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4261 (VRCP14PSZr VR512:$src)>;
4262 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4263 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4264 (VRCP14PDZr VR512:$src)>;
4266 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4267 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4270 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4271 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4272 "$src2, $src1", "$src1, $src2",
4273 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4274 (i32 FROUND_CURRENT))>;
4276 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4277 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4278 "$src2, $src1", "$src1, $src2",
4279 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4280 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4282 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4283 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4284 "$src2, $src1", "$src1, $src2",
4285 (OpNode (_.VT _.RC:$src1),
4286 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4287 (i32 FROUND_CURRENT))>;
4290 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4291 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4292 EVEX_CD8<32, CD8VT1>;
4293 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4294 EVEX_CD8<64, CD8VT1>, VEX_W;
4297 let hasSideEffects = 0, Predicates = [HasERI] in {
4298 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4299 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4301 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4303 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4306 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4307 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4308 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4310 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4311 (ins _.RC:$src), OpcodeStr,
4313 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4316 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4317 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4319 (bitconvert (_.LdFrag addr:$src))),
4320 (i32 FROUND_CURRENT))>;
4322 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4323 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4325 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4326 (i32 FROUND_CURRENT))>, EVEX_B;
4329 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4330 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4331 EVEX_CD8<32, CD8VF>;
4332 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4333 VEX_W, EVEX_CD8<32, CD8VF>;
4336 let Predicates = [HasERI], hasSideEffects = 0 in {
4338 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4339 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4340 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4343 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4344 SDNode OpNode, X86VectorVTInfo _>{
4345 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4346 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4347 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4348 let mayLoad = 1 in {
4349 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4350 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4352 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4354 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4355 (ins _.ScalarMemOp:$src), OpcodeStr,
4356 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4358 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4363 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4364 Intrinsic F32Int, Intrinsic F64Int,
4365 OpndItins itins_s, OpndItins itins_d> {
4366 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4367 (ins FR32X:$src1, FR32X:$src2),
4368 !strconcat(OpcodeStr,
4369 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4370 [], itins_s.rr>, XS, EVEX_4V;
4371 let isCodeGenOnly = 1 in
4372 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4373 (ins VR128X:$src1, VR128X:$src2),
4374 !strconcat(OpcodeStr,
4375 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4377 (F32Int VR128X:$src1, VR128X:$src2))],
4378 itins_s.rr>, XS, EVEX_4V;
4379 let mayLoad = 1 in {
4380 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4381 (ins FR32X:$src1, f32mem:$src2),
4382 !strconcat(OpcodeStr,
4383 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4384 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4385 let isCodeGenOnly = 1 in
4386 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4387 (ins VR128X:$src1, ssmem:$src2),
4388 !strconcat(OpcodeStr,
4389 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4391 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4392 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4394 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4395 (ins FR64X:$src1, FR64X:$src2),
4396 !strconcat(OpcodeStr,
4397 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4399 let isCodeGenOnly = 1 in
4400 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4401 (ins VR128X:$src1, VR128X:$src2),
4402 !strconcat(OpcodeStr,
4403 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4405 (F64Int VR128X:$src1, VR128X:$src2))],
4406 itins_s.rr>, XD, EVEX_4V, VEX_W;
4407 let mayLoad = 1 in {
4408 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4409 (ins FR64X:$src1, f64mem:$src2),
4410 !strconcat(OpcodeStr,
4411 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4412 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4413 let isCodeGenOnly = 1 in
4414 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4415 (ins VR128X:$src1, sdmem:$src2),
4416 !strconcat(OpcodeStr,
4417 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4419 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4420 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4424 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4426 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4428 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4429 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4431 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4432 // Define only if AVX512VL feature is present.
4433 let Predicates = [HasVLX] in {
4434 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4435 OpNode, v4f32x_info>,
4436 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4437 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4438 OpNode, v8f32x_info>,
4439 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4440 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4441 OpNode, v2f64x_info>,
4442 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4443 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4444 OpNode, v4f64x_info>,
4445 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4449 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4451 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4452 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4453 SSE_SQRTSS, SSE_SQRTSD>;
4455 let Predicates = [HasAVX512] in {
4456 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4457 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4458 (VSQRTPSZr VR512:$src1)>;
4459 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4460 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4461 (VSQRTPDZr VR512:$src1)>;
4463 def : Pat<(f32 (fsqrt FR32X:$src)),
4464 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4465 def : Pat<(f32 (fsqrt (load addr:$src))),
4466 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4467 Requires<[OptForSize]>;
4468 def : Pat<(f64 (fsqrt FR64X:$src)),
4469 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4470 def : Pat<(f64 (fsqrt (load addr:$src))),
4471 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4472 Requires<[OptForSize]>;
4474 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4475 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4476 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4477 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4478 Requires<[OptForSize]>;
4480 def : Pat<(f32 (X86frcp FR32X:$src)),
4481 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4482 def : Pat<(f32 (X86frcp (load addr:$src))),
4483 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4484 Requires<[OptForSize]>;
4486 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4487 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4488 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4490 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4491 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4493 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4494 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4495 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4497 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4498 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4502 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4503 X86MemOperand x86memop, RegisterClass RC,
4504 PatFrag mem_frag32, PatFrag mem_frag64,
4505 Intrinsic V4F32Int, Intrinsic V2F64Int,
4507 let ExeDomain = SSEPackedSingle in {
4508 // Intrinsic operation, reg.
4509 // Vector intrinsic operation, reg
4510 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4511 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4512 !strconcat(OpcodeStr,
4513 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4514 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4516 // Vector intrinsic operation, mem
4517 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4518 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4519 !strconcat(OpcodeStr,
4520 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4522 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4523 EVEX_CD8<32, VForm>;
4524 } // ExeDomain = SSEPackedSingle
4526 let ExeDomain = SSEPackedDouble in {
4527 // Vector intrinsic operation, reg
4528 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4529 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4530 !strconcat(OpcodeStr,
4531 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4532 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4534 // Vector intrinsic operation, mem
4535 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4536 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4537 !strconcat(OpcodeStr,
4538 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4540 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4541 EVEX_CD8<64, VForm>;
4542 } // ExeDomain = SSEPackedDouble
4545 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4549 let ExeDomain = GenericDomain in {
4551 let hasSideEffects = 0 in
4552 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4553 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4554 !strconcat(OpcodeStr,
4555 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4558 // Intrinsic operation, reg.
4559 let isCodeGenOnly = 1 in
4560 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4561 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4562 !strconcat(OpcodeStr,
4563 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4564 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4566 // Intrinsic operation, mem.
4567 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4568 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4569 !strconcat(OpcodeStr,
4570 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4571 [(set VR128X:$dst, (F32Int VR128X:$src1,
4572 sse_load_f32:$src2, imm:$src3))]>,
4573 EVEX_CD8<32, CD8VT1>;
4576 let hasSideEffects = 0 in
4577 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4578 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4579 !strconcat(OpcodeStr,
4580 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4583 // Intrinsic operation, reg.
4584 let isCodeGenOnly = 1 in
4585 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4586 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4587 !strconcat(OpcodeStr,
4588 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4589 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4592 // Intrinsic operation, mem.
4593 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4594 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4595 !strconcat(OpcodeStr,
4596 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4598 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4599 VEX_W, EVEX_CD8<64, CD8VT1>;
4600 } // ExeDomain = GenericDomain
4603 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4604 X86MemOperand x86memop, RegisterClass RC,
4605 PatFrag mem_frag, Domain d> {
4606 let ExeDomain = d in {
4607 // Intrinsic operation, reg.
4608 // Vector intrinsic operation, reg
4609 def r : AVX512AIi8<opc, MRMSrcReg,
4610 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4611 !strconcat(OpcodeStr,
4612 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4615 // Vector intrinsic operation, mem
4616 def m : AVX512AIi8<opc, MRMSrcMem,
4617 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4618 !strconcat(OpcodeStr,
4619 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4625 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4626 memopv16f32, SSEPackedSingle>, EVEX_V512,
4627 EVEX_CD8<32, CD8VF>;
4629 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4630 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4632 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4635 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4636 memopv8f64, SSEPackedDouble>, EVEX_V512,
4637 VEX_W, EVEX_CD8<64, CD8VF>;
4639 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4640 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4642 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4644 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4645 Operand x86memop, RegisterClass RC, Domain d> {
4646 let ExeDomain = d in {
4647 def r : AVX512AIi8<opc, MRMSrcReg,
4648 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4649 !strconcat(OpcodeStr,
4650 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4653 def m : AVX512AIi8<opc, MRMSrcMem,
4654 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4655 !strconcat(OpcodeStr,
4656 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4661 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4662 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4664 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4665 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4667 def : Pat<(ffloor FR32X:$src),
4668 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4669 def : Pat<(f64 (ffloor FR64X:$src)),
4670 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4671 def : Pat<(f32 (fnearbyint FR32X:$src)),
4672 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4673 def : Pat<(f64 (fnearbyint FR64X:$src)),
4674 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4675 def : Pat<(f32 (fceil FR32X:$src)),
4676 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4677 def : Pat<(f64 (fceil FR64X:$src)),
4678 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4679 def : Pat<(f32 (frint FR32X:$src)),
4680 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4681 def : Pat<(f64 (frint FR64X:$src)),
4682 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4683 def : Pat<(f32 (ftrunc FR32X:$src)),
4684 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4685 def : Pat<(f64 (ftrunc FR64X:$src)),
4686 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4688 def : Pat<(v16f32 (ffloor VR512:$src)),
4689 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4690 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4691 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4692 def : Pat<(v16f32 (fceil VR512:$src)),
4693 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4694 def : Pat<(v16f32 (frint VR512:$src)),
4695 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4696 def : Pat<(v16f32 (ftrunc VR512:$src)),
4697 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4699 def : Pat<(v8f64 (ffloor VR512:$src)),
4700 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4701 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4702 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4703 def : Pat<(v8f64 (fceil VR512:$src)),
4704 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4705 def : Pat<(v8f64 (frint VR512:$src)),
4706 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4707 def : Pat<(v8f64 (ftrunc VR512:$src)),
4708 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4710 //-------------------------------------------------
4711 // Integer truncate and extend operations
4712 //-------------------------------------------------
4714 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4715 RegisterClass dstRC, RegisterClass srcRC,
4716 RegisterClass KRC, X86MemOperand x86memop> {
4717 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4719 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4722 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4723 (ins KRC:$mask, srcRC:$src),
4724 !strconcat(OpcodeStr,
4725 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4728 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4729 (ins KRC:$mask, srcRC:$src),
4730 !strconcat(OpcodeStr,
4731 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4734 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4735 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4738 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4739 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4740 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4744 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4745 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4746 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4747 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4748 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4749 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4750 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4751 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4752 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4753 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4754 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4755 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4756 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4757 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4758 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4759 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4760 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4761 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4762 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4763 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4764 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4765 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4766 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4767 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4768 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4769 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4770 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4771 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4772 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4773 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4775 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4776 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4777 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4778 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4779 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4781 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4782 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4783 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4784 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4785 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4786 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4787 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4788 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4791 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4792 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4793 PatFrag mem_frag, X86MemOperand x86memop,
4794 ValueType OpVT, ValueType InVT> {
4796 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4799 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4801 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4802 (ins KRC:$mask, SrcRC:$src),
4803 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4806 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4807 (ins KRC:$mask, SrcRC:$src),
4808 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4811 let mayLoad = 1 in {
4812 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4813 (ins x86memop:$src),
4814 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4816 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4819 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4820 (ins KRC:$mask, x86memop:$src),
4821 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4825 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4826 (ins KRC:$mask, x86memop:$src),
4827 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4833 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4834 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4836 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4837 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4839 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4840 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4841 EVEX_CD8<16, CD8VH>;
4842 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4843 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4844 EVEX_CD8<16, CD8VQ>;
4845 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4846 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4847 EVEX_CD8<32, CD8VH>;
4849 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4850 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4852 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4853 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4855 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4856 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4857 EVEX_CD8<16, CD8VH>;
4858 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4859 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4860 EVEX_CD8<16, CD8VQ>;
4861 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4862 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4863 EVEX_CD8<32, CD8VH>;
4865 //===----------------------------------------------------------------------===//
4866 // GATHER - SCATTER Operations
4868 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4869 RegisterClass RC, X86MemOperand memop> {
4871 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4872 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4873 (ins RC:$src1, KRC:$mask, memop:$src2),
4874 !strconcat(OpcodeStr,
4875 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4879 let ExeDomain = SSEPackedDouble in {
4880 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4881 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4882 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4883 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4886 let ExeDomain = SSEPackedSingle in {
4887 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4888 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4889 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4890 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4893 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4894 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4895 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4896 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4898 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4899 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4900 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4901 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4903 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4904 RegisterClass RC, X86MemOperand memop> {
4905 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4906 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4907 (ins memop:$dst, KRC:$mask, RC:$src2),
4908 !strconcat(OpcodeStr,
4909 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4913 let ExeDomain = SSEPackedDouble in {
4914 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4915 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4916 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4917 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4920 let ExeDomain = SSEPackedSingle in {
4921 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4922 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4923 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4924 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4927 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4928 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4929 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4930 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4932 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4933 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4934 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4935 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4938 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4939 RegisterClass KRC, X86MemOperand memop> {
4940 let Predicates = [HasPFI], hasSideEffects = 1 in
4941 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4942 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4946 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4947 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4949 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4950 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4952 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4953 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4955 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4956 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4958 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4959 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4961 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4962 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4964 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4965 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4967 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4968 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4970 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4971 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4973 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4974 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4976 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4977 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4979 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4980 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4982 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4983 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4985 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4986 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4988 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4989 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4991 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4992 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4993 //===----------------------------------------------------------------------===//
4994 // VSHUFPS - VSHUFPD Operations
4996 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4997 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4999 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5000 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
5001 !strconcat(OpcodeStr,
5002 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5003 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5004 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5005 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5006 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5007 (ins RC:$src1, RC:$src2, i8imm:$src3),
5008 !strconcat(OpcodeStr,
5009 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5010 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5011 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5012 EVEX_4V, Sched<[WriteShuffle]>;
5015 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
5016 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5017 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
5018 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5020 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5021 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5022 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5023 (memopv16i32 addr:$src2), (i8 imm:$imm))),
5024 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5026 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5027 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5028 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5029 (memopv8i64 addr:$src2), (i8 imm:$imm))),
5030 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5032 multiclass avx512_valign<X86VectorVTInfo _> {
5033 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5034 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
5036 "$src3, $src2, $src1", "$src1, $src2, $src3",
5037 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5039 AVX512AIi8Base, EVEX_4V;
5041 // Also match valign of packed floats.
5042 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5043 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5046 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5047 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
5048 !strconcat("valign"##_.Suffix,
5049 "\t{$src3, $src2, $src1, $dst|"
5050 "$dst, $src1, $src2, $src3}"),
5053 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5054 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5056 // Helper fragments to match sext vXi1 to vXiY.
5057 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5058 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5060 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5061 RegisterClass KRC, RegisterClass RC,
5062 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5064 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5065 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5067 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5068 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5070 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5071 !strconcat(OpcodeStr,
5072 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5074 let mayLoad = 1 in {
5075 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5076 (ins x86memop:$src),
5077 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5079 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5080 (ins KRC:$mask, x86memop:$src),
5081 !strconcat(OpcodeStr,
5082 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5084 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5085 (ins KRC:$mask, x86memop:$src),
5086 !strconcat(OpcodeStr,
5087 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5089 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5090 (ins x86scalar_mop:$src),
5091 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5092 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5094 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5095 (ins KRC:$mask, x86scalar_mop:$src),
5096 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5097 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5098 []>, EVEX, EVEX_B, EVEX_K;
5099 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5100 (ins KRC:$mask, x86scalar_mop:$src),
5101 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5102 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5104 []>, EVEX, EVEX_B, EVEX_KZ;
5108 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5109 i512mem, i32mem, "{1to16}">, EVEX_V512,
5110 EVEX_CD8<32, CD8VF>;
5111 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5112 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5113 EVEX_CD8<64, CD8VF>;
5116 (bc_v16i32 (v16i1sextv16i32)),
5117 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5118 (VPABSDZrr VR512:$src)>;
5120 (bc_v8i64 (v8i1sextv8i64)),
5121 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5122 (VPABSQZrr VR512:$src)>;
5124 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5125 (v16i32 immAllZerosV), (i16 -1))),
5126 (VPABSDZrr VR512:$src)>;
5127 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5128 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5129 (VPABSQZrr VR512:$src)>;
5131 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5132 RegisterClass RC, RegisterClass KRC,
5133 X86MemOperand x86memop,
5134 X86MemOperand x86scalar_mop, string BrdcstStr> {
5135 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5137 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5139 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5140 (ins x86memop:$src),
5141 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5143 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5144 (ins x86scalar_mop:$src),
5145 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5146 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5148 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5149 (ins KRC:$mask, RC:$src),
5150 !strconcat(OpcodeStr,
5151 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5153 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5154 (ins KRC:$mask, x86memop:$src),
5155 !strconcat(OpcodeStr,
5156 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5158 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5159 (ins KRC:$mask, x86scalar_mop:$src),
5160 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5161 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5163 []>, EVEX, EVEX_KZ, EVEX_B;
5165 let Constraints = "$src1 = $dst" in {
5166 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5167 (ins RC:$src1, KRC:$mask, RC:$src2),
5168 !strconcat(OpcodeStr,
5169 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5171 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5172 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5173 !strconcat(OpcodeStr,
5174 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5176 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5177 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5178 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5179 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5180 []>, EVEX, EVEX_K, EVEX_B;
5184 let Predicates = [HasCDI] in {
5185 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5186 i512mem, i32mem, "{1to16}">,
5187 EVEX_V512, EVEX_CD8<32, CD8VF>;
5190 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5191 i512mem, i64mem, "{1to8}">,
5192 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5196 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5198 (VPCONFLICTDrrk VR512:$src1,
5199 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5201 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5203 (VPCONFLICTQrrk VR512:$src1,
5204 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5206 let Predicates = [HasCDI] in {
5207 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5208 i512mem, i32mem, "{1to16}">,
5209 EVEX_V512, EVEX_CD8<32, CD8VF>;
5212 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5213 i512mem, i64mem, "{1to8}">,
5214 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5218 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5220 (VPLZCNTDrrk VR512:$src1,
5221 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5223 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5225 (VPLZCNTQrrk VR512:$src1,
5226 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5228 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5229 (VPLZCNTDrm addr:$src)>;
5230 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5231 (VPLZCNTDrr VR512:$src)>;
5232 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5233 (VPLZCNTQrm addr:$src)>;
5234 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5235 (VPLZCNTQrr VR512:$src)>;
5237 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5238 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5239 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5241 def : Pat<(store VK1:$src, addr:$dst),
5242 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5244 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5245 (truncstore node:$val, node:$ptr), [{
5246 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5249 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5250 (MOV8mr addr:$dst, GR8:$src)>;
5252 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5253 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5254 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5255 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5258 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5259 string OpcodeStr, Predicate prd> {
5260 let Predicates = [prd] in
5261 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5263 let Predicates = [prd, HasVLX] in {
5264 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5265 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5269 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5270 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5272 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5274 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5276 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5280 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5282 //===----------------------------------------------------------------------===//
5283 // AVX-512 - COMPRESS and EXPAND
5285 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5287 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5288 (ins _.KRCWM:$mask, _.RC:$src),
5289 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5290 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5291 _.ImmAllZerosV)))]>, EVEX_KZ;
5293 let Constraints = "$src0 = $dst" in
5294 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5295 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5296 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5297 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5298 _.RC:$src0)))]>, EVEX_K;
5300 let mayStore = 1 in {
5301 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5302 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5303 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5304 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5306 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5310 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5311 AVX512VLVectorVTInfo VTInfo> {
5312 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5314 let Predicates = [HasVLX] in {
5315 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5316 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5320 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5322 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5324 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5326 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5330 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5332 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5333 (ins _.KRCWM:$mask, _.RC:$src),
5334 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5335 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5336 _.ImmAllZerosV)))]>, EVEX_KZ;
5338 let Constraints = "$src0 = $dst" in
5339 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5340 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5341 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5342 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5343 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5345 let mayLoad = 1, Constraints = "$src0 = $dst" in
5346 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5347 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5348 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5349 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5351 (_.LdFrag addr:$src))),
5353 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5356 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5357 (ins _.KRCWM:$mask, _.MemOp:$src),
5358 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5359 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5360 (_.VT (bitconvert (_.LdFrag addr:$src))),
5361 _.ImmAllZerosV)))]>,
5362 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5366 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5367 AVX512VLVectorVTInfo VTInfo> {
5368 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5370 let Predicates = [HasVLX] in {
5371 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5372 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5376 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5378 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5380 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5382 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,