1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
280 dag Outs, dag NonTiedIns, string OpcodeStr,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_common<O, F, _, Outs,
284 !con((ins _.RC:$src1), NonTiedIns),
285 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
288 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
290 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
293 string AttSrcAsm, string IntelSrcAsm,
295 AVX512_maskable_custom<O, F, Outs, Ins,
296 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
297 !con((ins _.KRCWM:$mask), Ins),
298 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
302 // Instruction with mask that puts result in mask register,
303 // like "compare" and "vptest"
304 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
306 dag Ins, dag MaskingIns,
308 string AttSrcAsm, string IntelSrcAsm,
310 list<dag> MaskingPattern,
312 InstrItinClass itin = NoItinerary> {
313 def NAME: AVX512<O, F, Outs, Ins,
314 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
315 "$dst "#Round#", "#IntelSrcAsm#"}",
318 def NAME#k: AVX512<O, F, Outs, MaskingIns,
319 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
320 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
321 MaskingPattern, itin>, EVEX_K;
324 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
326 dag Ins, dag MaskingIns,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, dag MaskingRHS,
331 InstrItinClass itin = NoItinerary> :
332 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
333 AttSrcAsm, IntelSrcAsm,
334 [(set _.KRC:$dst, RHS)],
335 [(set _.KRC:$dst, MaskingRHS)],
338 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
339 dag Outs, dag Ins, string OpcodeStr,
340 string AttSrcAsm, string IntelSrcAsm,
341 dag RHS, string Round = "",
342 InstrItinClass itin = NoItinerary> :
343 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
344 !con((ins _.KRCWM:$mask), Ins),
345 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
346 (and _.KRCWM:$mask, RHS),
349 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
350 dag Outs, dag Ins, string OpcodeStr,
351 string AttSrcAsm, string IntelSrcAsm> :
352 AVX512_maskable_custom_cmp<O, F, Outs,
353 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
354 AttSrcAsm, IntelSrcAsm,
355 [],[],"", NoItinerary>;
357 // Bitcasts between 512-bit vector types. Return the original type since
358 // no instruction is needed for the conversion
359 let Predicates = [HasAVX512] in {
360 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
364 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
369 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
374 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
379 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
385 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
389 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
396 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
401 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
406 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
411 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
416 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
420 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
421 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
423 // Bitcasts between 256-bit vector types. Return the original type since
424 // no instruction is needed for the conversion
425 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
429 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
434 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
439 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
444 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
449 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
453 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
454 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
458 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
461 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
462 isPseudo = 1, Predicates = [HasAVX512] in {
463 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
464 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
467 let Predicates = [HasAVX512] in {
468 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
469 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
470 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
473 //===----------------------------------------------------------------------===//
474 // AVX-512 - VECTOR INSERT
476 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert> {
478 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
479 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
480 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
481 "vinsert" # From.EltTypeName # "x" # From.NumElts,
482 "$src3, $src2, $src1", "$src1, $src2, $src3",
483 (vinsert_insert:$src3 (To.VT To.RC:$src1),
484 (From.VT From.RC:$src2),
485 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
488 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
489 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
490 "vinsert" # From.EltTypeName # "x" # From.NumElts,
491 "$src3, $src2, $src1", "$src1, $src2, $src3",
492 (vinsert_insert:$src3 (To.VT To.RC:$src1),
493 (From.VT (bitconvert (From.LdFrag addr:$src2))),
494 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
495 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
499 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
500 X86VectorVTInfo To, PatFrag vinsert_insert,
501 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
502 let Predicates = p in {
503 def : Pat<(vinsert_insert:$ins
504 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
505 (To.VT (!cast<Instruction>(InstrStr#"rr")
506 To.RC:$src1, From.RC:$src2,
507 (INSERT_get_vinsert_imm To.RC:$ins)))>;
509 def : Pat<(vinsert_insert:$ins
511 (From.VT (bitconvert (From.LdFrag addr:$src2))),
513 (To.VT (!cast<Instruction>(InstrStr#"rm")
514 To.RC:$src1, addr:$src2,
515 (INSERT_get_vinsert_imm To.RC:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
522 let Predicates = [HasVLX] in
523 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
524 X86VectorVTInfo< 4, EltVT32, VR128X>,
525 X86VectorVTInfo< 8, EltVT32, VR256X>,
526 vinsert128_insert>, EVEX_V256;
528 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
529 X86VectorVTInfo< 4, EltVT32, VR128X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 vinsert128_insert>, EVEX_V512;
533 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
534 X86VectorVTInfo< 4, EltVT64, VR256X>,
535 X86VectorVTInfo< 8, EltVT64, VR512>,
536 vinsert256_insert>, VEX_W, EVEX_V512;
538 let Predicates = [HasVLX, HasDQI] in
539 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 2, EltVT64, VR128X>,
541 X86VectorVTInfo< 4, EltVT64, VR256X>,
542 vinsert128_insert>, VEX_W, EVEX_V256;
544 let Predicates = [HasDQI] in {
545 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
546 X86VectorVTInfo< 2, EltVT64, VR128X>,
547 X86VectorVTInfo< 8, EltVT64, VR512>,
548 vinsert128_insert>, VEX_W, EVEX_V512;
550 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
551 X86VectorVTInfo< 8, EltVT32, VR256X>,
552 X86VectorVTInfo<16, EltVT32, VR512>,
553 vinsert256_insert>, EVEX_V512;
557 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
558 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
560 // Codegen pattern with the alternative types,
561 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
562 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
563 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
564 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
565 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
567 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
568 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
569 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
570 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
572 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
573 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
574 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
575 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
577 // Codegen pattern with the alternative types insert VEC128 into VEC256
578 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
582 // Codegen pattern with the alternative types insert VEC128 into VEC512
583 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
587 // Codegen pattern with the alternative types insert VEC256 into VEC512
588 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
593 // vinsertps - insert f32 to XMM
594 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
595 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
596 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
597 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
599 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
600 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
601 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
602 [(set VR128X:$dst, (X86insertps VR128X:$src1,
603 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
604 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
606 //===----------------------------------------------------------------------===//
607 // AVX-512 VECTOR EXTRACT
610 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
611 X86VectorVTInfo To> {
612 // A subvector extract from the first vector position is
613 // a subregister copy that needs no instruction.
614 def NAME # To.NumElts:
615 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
616 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
619 multiclass vextract_for_size<int Opcode,
620 X86VectorVTInfo From, X86VectorVTInfo To,
621 PatFrag vextract_extract> :
622 vextract_for_size_first_position_lowering<From, To> {
624 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
625 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
626 // vextract_extract), we interesting only in patterns without mask,
627 // intrinsics pattern match generated bellow.
628 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
629 (ins From.RC:$src1, i32u8imm:$idx),
630 "vextract" # To.EltTypeName # "x" # To.NumElts,
631 "$idx, $src1", "$src1, $idx",
632 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
634 AVX512AIi8Base, EVEX;
635 let mayStore = 1 in {
636 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
637 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
638 "vextract" # To.EltTypeName # "x" # To.NumElts #
639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
643 (ins To.MemOp:$dst, To.KRCWM:$mask,
644 From.RC:$src1, i32u8imm:$src2),
645 "vextract" # To.EltTypeName # "x" # To.NumElts #
646 "\t{$src2, $src1, $dst {${mask}}|"
647 "$dst {${mask}}, $src1, $src2}",
652 // Intrinsic call with masking.
653 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
654 "x" # To.NumElts # "_" # From.Size)
655 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
656 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
657 From.ZSuffix # "rrk")
659 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
660 From.RC:$src1, imm:$idx)>;
662 // Intrinsic call with zero-masking.
663 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
664 "x" # To.NumElts # "_" # From.Size)
665 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
666 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
667 From.ZSuffix # "rrkz")
668 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
669 From.RC:$src1, imm:$idx)>;
671 // Intrinsic call without masking.
672 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
673 "x" # To.NumElts # "_" # From.Size)
674 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
675 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
677 From.RC:$src1, imm:$idx)>;
680 // Codegen pattern for the alternative types
681 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
682 X86VectorVTInfo To, PatFrag vextract_extract,
683 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
684 vextract_for_size_first_position_lowering<From, To> {
686 let Predicates = p in
687 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
688 (To.VT (!cast<Instruction>(InstrStr#"rr")
690 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
693 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
694 ValueType EltVT64, int Opcode256> {
695 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
696 X86VectorVTInfo<16, EltVT32, VR512>,
697 X86VectorVTInfo< 4, EltVT32, VR128X>,
698 vextract128_extract>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
701 X86VectorVTInfo< 8, EltVT64, VR512>,
702 X86VectorVTInfo< 4, EltVT64, VR256X>,
703 vextract256_extract>,
704 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
705 let Predicates = [HasVLX] in
706 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
707 X86VectorVTInfo< 8, EltVT32, VR256X>,
708 X86VectorVTInfo< 4, EltVT32, VR128X>,
709 vextract128_extract>,
710 EVEX_V256, EVEX_CD8<32, CD8VT4>;
711 let Predicates = [HasVLX, HasDQI] in
712 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
713 X86VectorVTInfo< 4, EltVT64, VR256X>,
714 X86VectorVTInfo< 2, EltVT64, VR128X>,
715 vextract128_extract>,
716 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
717 let Predicates = [HasDQI] in {
718 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
719 X86VectorVTInfo< 8, EltVT64, VR512>,
720 X86VectorVTInfo< 2, EltVT64, VR128X>,
721 vextract128_extract>,
722 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
723 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
724 X86VectorVTInfo<16, EltVT32, VR512>,
725 X86VectorVTInfo< 8, EltVT32, VR256X>,
726 vextract256_extract>,
727 EVEX_V512, EVEX_CD8<32, CD8VT8>;
731 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
732 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
734 // extract_subvector codegen patterns with the alternative types.
735 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
736 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
737 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
738 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
739 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
741 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
742 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
743 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
744 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
746 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
747 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
748 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
749 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
751 // Codegen pattern with the alternative types extract VEC128 from VEC512
752 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
756 // Codegen pattern with the alternative types extract VEC256 from VEC512
757 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
762 // A 128-bit subvector insert to the first 512-bit vector position
763 // is a subregister copy that needs no instruction.
764 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
765 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
766 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
768 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
769 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
770 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
772 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
773 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
774 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
776 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
777 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
778 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
781 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
782 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
783 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
784 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
785 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
786 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
787 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
788 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
789 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
790 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
791 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
792 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
794 // vextractps - extract 32 bits from XMM
795 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
796 (ins VR128X:$src1, u8imm:$src2),
797 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
798 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
801 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
802 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
803 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
805 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
807 //===---------------------------------------------------------------------===//
811 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
812 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
814 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
815 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
816 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
819 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
820 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
821 (DestInfo.VT (X86VBroadcast
822 (SrcInfo.ScalarLdFrag addr:$src)))>,
823 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
826 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
827 AVX512VLVectorVTInfo _> {
828 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
831 let Predicates = [HasVLX] in {
832 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
837 let ExeDomain = SSEPackedSingle in {
838 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
840 let Predicates = [HasVLX] in {
841 defm VBROADCASTSSZ128 : avx512_broadcast_rm<0x18, "vbroadcastss",
842 v4f32x_info, v4f32x_info>, EVEX_V128;
846 let ExeDomain = SSEPackedDouble in {
847 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, "vbroadcastsd",
848 avx512vl_f64_info>, VEX_W;
851 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
852 // Later, we can canonize broadcast instructions before ISel phase and
853 // eliminate additional patterns on ISel.
854 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
855 // representations of source
856 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
857 X86VectorVTInfo _, RegisterClass SrcRC_v,
858 RegisterClass SrcRC_s> {
859 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
860 (!cast<Instruction>(InstName##"r")
861 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
863 let AddedComplexity = 30 in {
864 def : Pat<(_.VT (vselect _.KRCWM:$mask,
865 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
866 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
867 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
869 def : Pat<(_.VT(vselect _.KRCWM:$mask,
870 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
871 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
872 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
876 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
878 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
881 let Predicates = [HasVLX] in {
882 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
883 v8f32x_info, VR128X, FR32X>;
884 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
885 v4f32x_info, VR128X, FR32X>;
886 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
887 v4f64x_info, VR128X, FR64X>;
890 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
891 (VBROADCASTSSZm addr:$src)>;
892 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
893 (VBROADCASTSDZm addr:$src)>;
895 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
896 (VBROADCASTSSZm addr:$src)>;
897 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
898 (VBROADCASTSDZm addr:$src)>;
900 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
901 RegisterClass SrcRC> {
902 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
903 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
904 "$src", "$src", []>, T8PD, EVEX;
907 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
908 RegisterClass SrcRC, Predicate prd> {
909 let Predicates = [prd] in
910 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
911 let Predicates = [prd, HasVLX] in {
912 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
913 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
917 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
919 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
921 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
923 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
926 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
927 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
929 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
930 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
932 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
933 (VPBROADCASTDrZr GR32:$src)>;
934 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
935 (VPBROADCASTQrZr GR64:$src)>;
937 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
938 (VPBROADCASTDrZr GR32:$src)>;
939 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
940 (VPBROADCASTQrZr GR64:$src)>;
942 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
943 (v16i32 immAllZerosV), (i16 GR16:$mask))),
944 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
945 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
946 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
947 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
949 // Provide aliases for broadcast from the same register class that
950 // automatically does the extract.
951 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
952 X86VectorVTInfo SrcInfo> {
953 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
954 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
955 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
958 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
959 AVX512VLVectorVTInfo _, Predicate prd> {
960 let Predicates = [prd] in {
961 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
962 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
964 // Defined separately to avoid redefinition.
965 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
967 let Predicates = [prd, HasVLX] in {
968 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
969 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
971 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
976 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
977 avx512vl_i8_info, HasBWI>;
978 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
979 avx512vl_i16_info, HasBWI>;
980 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
981 avx512vl_i32_info, HasAVX512>;
982 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
983 avx512vl_i64_info, HasAVX512>, VEX_W;
985 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
986 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
988 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
989 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
991 (_Dst.VT (X86SubVBroadcast
992 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
993 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
995 !strconcat(OpcodeStr,
996 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
998 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1000 !strconcat(OpcodeStr,
1001 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1006 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1007 v16i32_info, v4i32x_info>,
1008 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1009 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1010 v16f32_info, v4f32x_info>,
1011 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1012 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1013 v8i64_info, v4i64x_info>, VEX_W,
1014 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1015 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1016 v8f64_info, v4f64x_info>, VEX_W,
1017 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1019 let Predicates = [HasVLX] in {
1020 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1021 v8i32x_info, v4i32x_info>,
1022 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1023 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1024 v8f32x_info, v4f32x_info>,
1025 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1027 let Predicates = [HasVLX, HasDQI] in {
1028 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1029 v4i64x_info, v2i64x_info>, VEX_W,
1030 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1031 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1032 v4f64x_info, v2f64x_info>, VEX_W,
1033 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1035 let Predicates = [HasDQI] in {
1036 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1037 v8i64_info, v2i64x_info>, VEX_W,
1038 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1039 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1040 v16i32_info, v8i32x_info>,
1041 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1042 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1043 v8f64_info, v2f64x_info>, VEX_W,
1044 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1045 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1046 v16f32_info, v8f32x_info>,
1047 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1050 multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
1051 X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
1052 SDNode OpNode = X86SubVBroadcast> {
1054 defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
1055 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
1056 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1059 defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1060 (ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
1062 (_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
1063 T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
1066 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1067 AVX512VLVectorVTInfo _> {
1068 let Predicates = [HasDQI] in
1069 defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
1071 let Predicates = [HasDQI, HasVLX] in
1072 defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
1076 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1077 AVX512VLVectorVTInfo _> :
1078 avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
1080 let Predicates = [HasDQI, HasVLX] in
1081 defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
1082 X86SubV32x2Broadcast>, EVEX_V128;
1085 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1087 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1090 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1091 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1092 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1093 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1095 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1096 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1097 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1098 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1100 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1101 (VBROADCASTSSZr VR128X:$src)>;
1102 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1103 (VBROADCASTSDZr VR128X:$src)>;
1105 // Provide fallback in case the load node that is used in the patterns above
1106 // is used by additional users, which prevents the pattern selection.
1107 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1108 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1109 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1110 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1113 //===----------------------------------------------------------------------===//
1114 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1116 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1117 X86VectorVTInfo _, RegisterClass KRC> {
1118 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1120 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1123 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1124 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1125 let Predicates = [HasCDI] in
1126 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1127 let Predicates = [HasCDI, HasVLX] in {
1128 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1129 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1133 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1134 avx512vl_i32_info, VK16>;
1135 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1136 avx512vl_i64_info, VK8>, VEX_W;
1138 //===----------------------------------------------------------------------===//
1139 // -- VPERM2I - 3 source operands form --
1140 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1141 SDNode OpNode, X86VectorVTInfo _> {
1142 let Constraints = "$src1 = $dst" in {
1143 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1144 (ins _.RC:$src2, _.RC:$src3),
1145 OpcodeStr, "$src3, $src2", "$src2, $src3",
1146 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1150 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1151 (ins _.RC:$src2, _.MemOp:$src3),
1152 OpcodeStr, "$src3, $src2", "$src2, $src3",
1153 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1154 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1155 EVEX_4V, AVX5128IBase;
1158 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1159 SDNode OpNode, X86VectorVTInfo _> {
1160 let mayLoad = 1, Constraints = "$src1 = $dst" in
1161 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1162 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1163 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1164 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1165 (_.VT (OpNode _.RC:$src1,
1166 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1167 AVX5128IBase, EVEX_4V, EVEX_B;
1170 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1171 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1172 let Predicates = [HasAVX512] in
1173 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1174 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1175 let Predicates = [HasVLX] in {
1176 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1177 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1179 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1180 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1184 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1185 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1186 let Predicates = [HasBWI] in
1187 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1188 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1190 let Predicates = [HasBWI, HasVLX] in {
1191 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1192 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1194 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1195 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1199 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1200 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1201 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1202 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1203 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1204 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1205 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1206 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1208 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1209 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1210 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1211 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1212 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1213 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1214 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1215 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1217 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1218 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1219 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1220 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1222 //===----------------------------------------------------------------------===//
1223 // AVX-512 - BLEND using mask
1225 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1226 let ExeDomain = _.ExeDomain in {
1227 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1228 (ins _.RC:$src1, _.RC:$src2),
1229 !strconcat(OpcodeStr,
1230 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1232 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1233 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1234 !strconcat(OpcodeStr,
1235 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1236 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1237 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1238 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1239 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1240 !strconcat(OpcodeStr,
1241 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1242 []>, EVEX_4V, EVEX_KZ;
1243 let mayLoad = 1 in {
1244 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1245 (ins _.RC:$src1, _.MemOp:$src2),
1246 !strconcat(OpcodeStr,
1247 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1248 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1249 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1250 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1251 !strconcat(OpcodeStr,
1252 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1253 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1254 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1255 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1256 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1257 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1258 !strconcat(OpcodeStr,
1259 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1260 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1264 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1266 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1267 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1268 !strconcat(OpcodeStr,
1269 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1270 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1271 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1272 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1273 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1275 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1276 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1277 !strconcat(OpcodeStr,
1278 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1279 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1280 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1284 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1285 AVX512VLVectorVTInfo VTInfo> {
1286 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1287 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1289 let Predicates = [HasVLX] in {
1290 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1291 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1292 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1293 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1297 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1298 AVX512VLVectorVTInfo VTInfo> {
1299 let Predicates = [HasBWI] in
1300 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1302 let Predicates = [HasBWI, HasVLX] in {
1303 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1304 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1309 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1310 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1311 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1312 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1313 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1314 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1317 let Predicates = [HasAVX512] in {
1318 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1319 (v8f32 VR256X:$src2))),
1321 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1322 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1323 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1325 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1326 (v8i32 VR256X:$src2))),
1328 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1329 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1330 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1332 //===----------------------------------------------------------------------===//
1333 // Compare Instructions
1334 //===----------------------------------------------------------------------===//
1336 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1338 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1340 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1342 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1343 "vcmp${cc}"#_.Suffix,
1344 "$src2, $src1", "$src1, $src2",
1345 (OpNode (_.VT _.RC:$src1),
1349 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1351 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1352 "vcmp${cc}"#_.Suffix,
1353 "$src2, $src1", "$src1, $src2",
1354 (OpNode (_.VT _.RC:$src1),
1355 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1356 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1358 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1360 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1361 "vcmp${cc}"#_.Suffix,
1362 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1363 (OpNodeRnd (_.VT _.RC:$src1),
1366 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1367 // Accept explicit immediate argument form instead of comparison code.
1368 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1369 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1371 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1373 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1374 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1376 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1378 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1379 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1381 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1383 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1385 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1387 }// let isAsmParserOnly = 1, hasSideEffects = 0
1389 let isCodeGenOnly = 1 in {
1390 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1391 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1392 !strconcat("vcmp${cc}", _.Suffix,
1393 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1394 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1397 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1399 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1401 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1402 !strconcat("vcmp${cc}", _.Suffix,
1403 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1404 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1405 (_.ScalarLdFrag addr:$src2),
1407 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1411 let Predicates = [HasAVX512] in {
1412 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1414 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1415 AVX512XDIi8Base, VEX_W;
1418 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1419 X86VectorVTInfo _> {
1420 def rr : AVX512BI<opc, MRMSrcReg,
1421 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1422 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1423 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1424 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1426 def rm : AVX512BI<opc, MRMSrcMem,
1427 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1428 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1429 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1430 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1431 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1432 def rrk : AVX512BI<opc, MRMSrcReg,
1433 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1434 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1435 "$dst {${mask}}, $src1, $src2}"),
1436 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1437 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1438 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1440 def rmk : AVX512BI<opc, MRMSrcMem,
1441 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1442 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1443 "$dst {${mask}}, $src1, $src2}"),
1444 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1445 (OpNode (_.VT _.RC:$src1),
1447 (_.LdFrag addr:$src2))))))],
1448 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1451 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1452 X86VectorVTInfo _> :
1453 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1454 let mayLoad = 1 in {
1455 def rmb : AVX512BI<opc, MRMSrcMem,
1456 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1457 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1458 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1459 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1460 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1461 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1462 def rmbk : AVX512BI<opc, MRMSrcMem,
1463 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1464 _.ScalarMemOp:$src2),
1465 !strconcat(OpcodeStr,
1466 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1467 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1468 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1469 (OpNode (_.VT _.RC:$src1),
1471 (_.ScalarLdFrag addr:$src2)))))],
1472 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1476 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1477 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1478 let Predicates = [prd] in
1479 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1482 let Predicates = [prd, HasVLX] in {
1483 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1485 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1490 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1491 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1493 let Predicates = [prd] in
1494 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1497 let Predicates = [prd, HasVLX] in {
1498 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1500 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1505 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1506 avx512vl_i8_info, HasBWI>,
1509 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1510 avx512vl_i16_info, HasBWI>,
1511 EVEX_CD8<16, CD8VF>;
1513 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1514 avx512vl_i32_info, HasAVX512>,
1515 EVEX_CD8<32, CD8VF>;
1517 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1518 avx512vl_i64_info, HasAVX512>,
1519 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1521 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1522 avx512vl_i8_info, HasBWI>,
1525 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1526 avx512vl_i16_info, HasBWI>,
1527 EVEX_CD8<16, CD8VF>;
1529 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1530 avx512vl_i32_info, HasAVX512>,
1531 EVEX_CD8<32, CD8VF>;
1533 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1534 avx512vl_i64_info, HasAVX512>,
1535 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1537 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1538 (COPY_TO_REGCLASS (VPCMPGTDZrr
1539 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1540 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1542 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1543 (COPY_TO_REGCLASS (VPCMPEQDZrr
1544 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1545 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1547 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1548 X86VectorVTInfo _> {
1549 def rri : AVX512AIi8<opc, MRMSrcReg,
1550 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1551 !strconcat("vpcmp${cc}", Suffix,
1552 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1553 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1555 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1557 def rmi : AVX512AIi8<opc, MRMSrcMem,
1558 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1559 !strconcat("vpcmp${cc}", Suffix,
1560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1561 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1562 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1564 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1565 def rrik : AVX512AIi8<opc, MRMSrcReg,
1566 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1568 !strconcat("vpcmp${cc}", Suffix,
1569 "\t{$src2, $src1, $dst {${mask}}|",
1570 "$dst {${mask}}, $src1, $src2}"),
1571 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1572 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1574 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1576 def rmik : AVX512AIi8<opc, MRMSrcMem,
1577 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1579 !strconcat("vpcmp${cc}", Suffix,
1580 "\t{$src2, $src1, $dst {${mask}}|",
1581 "$dst {${mask}}, $src1, $src2}"),
1582 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1583 (OpNode (_.VT _.RC:$src1),
1584 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1586 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1588 // Accept explicit immediate argument form instead of comparison code.
1589 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1590 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1591 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1592 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1593 "$dst, $src1, $src2, $cc}"),
1594 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1596 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1597 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1598 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1599 "$dst, $src1, $src2, $cc}"),
1600 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1601 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1602 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1604 !strconcat("vpcmp", Suffix,
1605 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1606 "$dst {${mask}}, $src1, $src2, $cc}"),
1607 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1609 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1610 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1612 !strconcat("vpcmp", Suffix,
1613 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1614 "$dst {${mask}}, $src1, $src2, $cc}"),
1615 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1619 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1620 X86VectorVTInfo _> :
1621 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1622 def rmib : AVX512AIi8<opc, MRMSrcMem,
1623 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1625 !strconcat("vpcmp${cc}", Suffix,
1626 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1627 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1628 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1629 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1631 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1632 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1633 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1634 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1635 !strconcat("vpcmp${cc}", Suffix,
1636 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1637 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1638 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1639 (OpNode (_.VT _.RC:$src1),
1640 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1642 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1644 // Accept explicit immediate argument form instead of comparison code.
1645 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1646 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1647 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1649 !strconcat("vpcmp", Suffix,
1650 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1651 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1652 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1653 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1654 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1655 _.ScalarMemOp:$src2, u8imm:$cc),
1656 !strconcat("vpcmp", Suffix,
1657 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1658 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1659 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1663 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1664 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1665 let Predicates = [prd] in
1666 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1668 let Predicates = [prd, HasVLX] in {
1669 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1670 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1674 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1675 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1676 let Predicates = [prd] in
1677 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1680 let Predicates = [prd, HasVLX] in {
1681 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1683 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1688 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1689 HasBWI>, EVEX_CD8<8, CD8VF>;
1690 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1691 HasBWI>, EVEX_CD8<8, CD8VF>;
1693 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1694 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1695 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1696 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1698 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1699 HasAVX512>, EVEX_CD8<32, CD8VF>;
1700 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1701 HasAVX512>, EVEX_CD8<32, CD8VF>;
1703 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1704 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1705 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1706 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1708 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1710 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1711 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1712 "vcmp${cc}"#_.Suffix,
1713 "$src2, $src1", "$src1, $src2",
1714 (X86cmpm (_.VT _.RC:$src1),
1718 let mayLoad = 1 in {
1719 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1720 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1721 "vcmp${cc}"#_.Suffix,
1722 "$src2, $src1", "$src1, $src2",
1723 (X86cmpm (_.VT _.RC:$src1),
1724 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1727 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1729 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1730 "vcmp${cc}"#_.Suffix,
1731 "${src2}"##_.BroadcastStr##", $src1",
1732 "$src1, ${src2}"##_.BroadcastStr,
1733 (X86cmpm (_.VT _.RC:$src1),
1734 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1737 // Accept explicit immediate argument form instead of comparison code.
1738 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1739 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1741 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1743 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1745 let mayLoad = 1 in {
1746 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1748 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1750 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1752 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1754 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1756 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1757 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1762 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1763 // comparison code form (VCMP[EQ/LT/LE/...]
1764 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1765 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1766 "vcmp${cc}"#_.Suffix,
1767 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1768 (X86cmpmRnd (_.VT _.RC:$src1),
1771 (i32 FROUND_NO_EXC))>, EVEX_B;
1773 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1774 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1776 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1778 "$cc,{sae}, $src2, $src1",
1779 "$src1, $src2,{sae}, $cc">, EVEX_B;
1783 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1784 let Predicates = [HasAVX512] in {
1785 defm Z : avx512_vcmp_common<_.info512>,
1786 avx512_vcmp_sae<_.info512>, EVEX_V512;
1789 let Predicates = [HasAVX512,HasVLX] in {
1790 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1791 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1795 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1796 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1797 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1798 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1800 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1801 (COPY_TO_REGCLASS (VCMPPSZrri
1802 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1803 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1805 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1806 (COPY_TO_REGCLASS (VPCMPDZrri
1807 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1808 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1810 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1811 (COPY_TO_REGCLASS (VPCMPUDZrri
1812 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1813 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1816 // ----------------------------------------------------------------
1818 //handle fpclass instruction mask = op(reg_scalar,imm)
1819 // op(mem_scalar,imm)
1820 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1821 X86VectorVTInfo _, Predicate prd> {
1822 let Predicates = [prd] in {
1823 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1824 (ins _.RC:$src1, i32u8imm:$src2),
1825 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1826 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1827 (i32 imm:$src2)))], NoItinerary>;
1828 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1829 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1830 OpcodeStr##_.Suffix#
1831 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1832 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1833 (OpNode (_.VT _.RC:$src1),
1834 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1835 let mayLoad = 1, AddedComplexity = 20 in {
1836 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1837 (ins _.MemOp:$src1, i32u8imm:$src2),
1838 OpcodeStr##_.Suffix##
1839 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1841 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1842 (i32 imm:$src2)))], NoItinerary>;
1843 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1844 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1845 OpcodeStr##_.Suffix##
1846 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1847 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1848 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1849 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1854 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1855 // fpclass(reg_vec, mem_vec, imm)
1856 // fpclass(reg_vec, broadcast(eltVt), imm)
1857 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1858 X86VectorVTInfo _, string mem, string broadcast>{
1859 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1860 (ins _.RC:$src1, i32u8imm:$src2),
1861 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1862 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1863 (i32 imm:$src2)))], NoItinerary>;
1864 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1865 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1866 OpcodeStr##_.Suffix#
1867 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1868 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1869 (OpNode (_.VT _.RC:$src1),
1870 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1871 let mayLoad = 1 in {
1872 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1873 (ins _.MemOp:$src1, i32u8imm:$src2),
1874 OpcodeStr##_.Suffix##mem#
1875 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1876 [(set _.KRC:$dst,(OpNode
1877 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1878 (i32 imm:$src2)))], NoItinerary>;
1879 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1880 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1881 OpcodeStr##_.Suffix##mem#
1882 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1883 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1884 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1885 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1886 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1887 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1888 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1889 _.BroadcastStr##", $dst | $dst, ${src1}"
1890 ##_.BroadcastStr##", $src2}",
1891 [(set _.KRC:$dst,(OpNode
1892 (_.VT (X86VBroadcast
1893 (_.ScalarLdFrag addr:$src1))),
1894 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1895 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1896 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1897 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1898 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1899 _.BroadcastStr##", $src2}",
1900 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1901 (_.VT (X86VBroadcast
1902 (_.ScalarLdFrag addr:$src1))),
1903 (i32 imm:$src2))))], NoItinerary>,
1908 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1909 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1911 let Predicates = [prd] in {
1912 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1913 broadcast>, EVEX_V512;
1915 let Predicates = [prd, HasVLX] in {
1916 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1917 broadcast>, EVEX_V128;
1918 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1919 broadcast>, EVEX_V256;
1923 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1924 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
1925 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1926 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1927 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1928 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1929 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1930 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
1931 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1932 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
1935 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
1936 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
1938 //-----------------------------------------------------------------
1939 // Mask register copy, including
1940 // - copy between mask registers
1941 // - load/store mask registers
1942 // - copy from GPR to mask register and vice versa
1944 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1945 string OpcodeStr, RegisterClass KRC,
1946 ValueType vvt, X86MemOperand x86memop> {
1947 let hasSideEffects = 0 in {
1948 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1949 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1951 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1952 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1953 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1955 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1956 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1957 [(store KRC:$src, addr:$dst)]>;
1961 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1963 RegisterClass KRC, RegisterClass GRC> {
1964 let hasSideEffects = 0 in {
1965 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1966 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1967 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1968 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1972 let Predicates = [HasDQI] in
1973 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1974 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1977 let Predicates = [HasAVX512] in
1978 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1979 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1982 let Predicates = [HasBWI] in {
1983 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1985 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1989 let Predicates = [HasBWI] in {
1990 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1992 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1996 // GR from/to mask register
1997 let Predicates = [HasDQI] in {
1998 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1999 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2000 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2001 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2003 let Predicates = [HasAVX512] in {
2004 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2005 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2006 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2007 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2009 let Predicates = [HasBWI] in {
2010 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2011 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2013 let Predicates = [HasBWI] in {
2014 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2015 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2019 let Predicates = [HasDQI] in {
2020 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2021 (KMOVBmk addr:$dst, VK8:$src)>;
2022 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2023 (KMOVBkm addr:$src)>;
2025 def : Pat<(store VK4:$src, addr:$dst),
2026 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2027 def : Pat<(store VK2:$src, addr:$dst),
2028 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2030 let Predicates = [HasAVX512, NoDQI] in {
2031 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2032 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2033 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2034 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2036 let Predicates = [HasAVX512] in {
2037 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2038 (KMOVWmk addr:$dst, VK16:$src)>;
2039 def : Pat<(i1 (load addr:$src)),
2040 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2041 (MOV8rm addr:$src), sub_8bit)),
2043 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2044 (KMOVWkm addr:$src)>;
2046 let Predicates = [HasBWI] in {
2047 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2048 (KMOVDmk addr:$dst, VK32:$src)>;
2049 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2050 (KMOVDkm addr:$src)>;
2052 let Predicates = [HasBWI] in {
2053 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2054 (KMOVQmk addr:$dst, VK64:$src)>;
2055 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2056 (KMOVQkm addr:$src)>;
2059 let Predicates = [HasAVX512] in {
2060 def : Pat<(i1 (trunc (i64 GR64:$src))),
2061 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2064 def : Pat<(i1 (trunc (i32 GR32:$src))),
2065 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2067 def : Pat<(i1 (trunc (i8 GR8:$src))),
2069 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2071 def : Pat<(i1 (trunc (i16 GR16:$src))),
2073 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2076 def : Pat<(i32 (zext VK1:$src)),
2077 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2078 def : Pat<(i32 (anyext VK1:$src)),
2079 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2081 def : Pat<(i8 (zext VK1:$src)),
2084 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2085 def : Pat<(i8 (anyext VK1:$src)),
2087 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2089 def : Pat<(i64 (zext VK1:$src)),
2090 (AND64ri8 (SUBREG_TO_REG (i64 0),
2091 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2092 def : Pat<(i16 (zext VK1:$src)),
2094 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2096 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2097 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2098 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2099 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2101 let Predicates = [HasBWI] in {
2102 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2103 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2104 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2105 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2109 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2110 let Predicates = [HasAVX512, NoDQI] in {
2111 // GR from/to 8-bit mask without native support
2112 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2114 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2115 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2117 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2121 let Predicates = [HasAVX512] in {
2122 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2123 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2124 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2125 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2127 let Predicates = [HasBWI] in {
2128 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2129 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2130 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2131 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2134 // Mask unary operation
2136 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2137 RegisterClass KRC, SDPatternOperator OpNode,
2139 let Predicates = [prd] in
2140 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2141 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2142 [(set KRC:$dst, (OpNode KRC:$src))]>;
2145 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2146 SDPatternOperator OpNode> {
2147 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2149 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2150 HasAVX512>, VEX, PS;
2151 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2152 HasBWI>, VEX, PD, VEX_W;
2153 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2154 HasBWI>, VEX, PS, VEX_W;
2157 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2159 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2160 let Predicates = [HasAVX512] in
2161 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2163 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2164 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2166 defm : avx512_mask_unop_int<"knot", "KNOT">;
2168 let Predicates = [HasDQI] in
2169 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2170 let Predicates = [HasAVX512] in
2171 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2172 let Predicates = [HasBWI] in
2173 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2174 let Predicates = [HasBWI] in
2175 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2177 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2178 let Predicates = [HasAVX512, NoDQI] in {
2179 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2180 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2181 def : Pat<(not VK8:$src),
2183 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2185 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2186 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2187 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2188 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2190 // Mask binary operation
2191 // - KAND, KANDN, KOR, KXNOR, KXOR
2192 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2193 RegisterClass KRC, SDPatternOperator OpNode,
2194 Predicate prd, bit IsCommutable> {
2195 let Predicates = [prd], isCommutable = IsCommutable in
2196 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2197 !strconcat(OpcodeStr,
2198 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2199 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2202 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2203 SDPatternOperator OpNode, bit IsCommutable,
2204 Predicate prdW = HasAVX512> {
2205 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2206 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2207 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2208 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2209 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2210 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2211 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2212 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2215 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2216 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2218 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2219 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2220 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2221 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2222 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2223 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2225 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2226 let Predicates = [HasAVX512] in
2227 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2228 (i16 GR16:$src1), (i16 GR16:$src2)),
2229 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2230 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2231 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2234 defm : avx512_mask_binop_int<"kand", "KAND">;
2235 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2236 defm : avx512_mask_binop_int<"kor", "KOR">;
2237 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2238 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2240 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2241 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2242 // for the DQI set, this type is legal and KxxxB instruction is used
2243 let Predicates = [NoDQI] in
2244 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2246 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2247 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2249 // All types smaller than 8 bits require conversion anyway
2250 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2251 (COPY_TO_REGCLASS (Inst
2252 (COPY_TO_REGCLASS VK1:$src1, VK16),
2253 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2254 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2255 (COPY_TO_REGCLASS (Inst
2256 (COPY_TO_REGCLASS VK2:$src1, VK16),
2257 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2258 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2259 (COPY_TO_REGCLASS (Inst
2260 (COPY_TO_REGCLASS VK4:$src1, VK16),
2261 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2264 defm : avx512_binop_pat<and, KANDWrr>;
2265 defm : avx512_binop_pat<andn, KANDNWrr>;
2266 defm : avx512_binop_pat<or, KORWrr>;
2267 defm : avx512_binop_pat<xnor, KXNORWrr>;
2268 defm : avx512_binop_pat<xor, KXORWrr>;
2270 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2271 (KXNORWrr VK16:$src1, VK16:$src2)>;
2272 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2273 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2274 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2275 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2276 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2277 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2279 let Predicates = [NoDQI] in
2280 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2281 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2282 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2284 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2285 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2286 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2288 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2289 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2290 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2292 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2293 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2294 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2297 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2298 RegisterClass KRCSrc, Predicate prd> {
2299 let Predicates = [prd] in {
2300 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2301 (ins KRC:$src1, KRC:$src2),
2302 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2305 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2306 (!cast<Instruction>(NAME##rr)
2307 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2308 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2312 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2313 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2314 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2316 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2317 let Predicates = [HasAVX512] in
2318 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2319 (i16 GR16:$src1), (i16 GR16:$src2)),
2320 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2321 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2322 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2324 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2327 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2328 SDNode OpNode, Predicate prd> {
2329 let Predicates = [prd], Defs = [EFLAGS] in
2330 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2331 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2332 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2335 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2336 Predicate prdW = HasAVX512> {
2337 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2339 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2341 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2343 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2347 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2348 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2351 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2353 let Predicates = [HasAVX512] in
2354 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2355 !strconcat(OpcodeStr,
2356 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2357 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2360 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2362 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2364 let Predicates = [HasDQI] in
2365 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2367 let Predicates = [HasBWI] in {
2368 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2370 let Predicates = [HasDQI] in
2371 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2376 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2377 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2379 // Mask setting all 0s or 1s
2380 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2381 let Predicates = [HasAVX512] in
2382 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2383 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2384 [(set KRC:$dst, (VT Val))]>;
2387 multiclass avx512_mask_setop_w<PatFrag Val> {
2388 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2389 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2390 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2391 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2394 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2395 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2397 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2398 let Predicates = [HasAVX512] in {
2399 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2400 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2401 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2402 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2403 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2404 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2405 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2407 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2408 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2410 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2411 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2413 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2414 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2416 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2417 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2419 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2420 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2422 let Predicates = [HasVLX] in {
2423 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2424 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2425 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2426 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2427 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2428 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2429 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2430 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2431 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2432 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2435 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2436 (v8i1 (COPY_TO_REGCLASS
2437 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2438 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2440 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2441 (v8i1 (COPY_TO_REGCLASS
2442 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2443 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2445 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2446 (v4i1 (COPY_TO_REGCLASS
2447 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2448 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2450 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2451 (v4i1 (COPY_TO_REGCLASS
2452 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2453 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2455 //===----------------------------------------------------------------------===//
2456 // AVX-512 - Aligned and unaligned load and store
2460 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2461 PatFrag ld_frag, PatFrag mload,
2462 bit IsReMaterializable = 1> {
2463 let hasSideEffects = 0 in {
2464 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2465 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2467 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2468 (ins _.KRCWM:$mask, _.RC:$src),
2469 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2470 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2473 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2474 SchedRW = [WriteLoad] in
2475 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2476 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2477 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2480 let Constraints = "$src0 = $dst" in {
2481 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2482 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2483 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2484 "${dst} {${mask}}, $src1}"),
2485 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2487 (_.VT _.RC:$src0))))], _.ExeDomain>,
2489 let mayLoad = 1, SchedRW = [WriteLoad] in
2490 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2491 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2492 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2493 "${dst} {${mask}}, $src1}"),
2494 [(set _.RC:$dst, (_.VT
2495 (vselect _.KRCWM:$mask,
2496 (_.VT (bitconvert (ld_frag addr:$src1))),
2497 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2499 let mayLoad = 1, SchedRW = [WriteLoad] in
2500 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2501 (ins _.KRCWM:$mask, _.MemOp:$src),
2502 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2503 "${dst} {${mask}} {z}, $src}",
2504 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2505 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2506 _.ExeDomain>, EVEX, EVEX_KZ;
2508 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2509 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2511 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2512 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2514 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2515 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2516 _.KRCWM:$mask, addr:$ptr)>;
2519 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2520 AVX512VLVectorVTInfo _,
2522 bit IsReMaterializable = 1> {
2523 let Predicates = [prd] in
2524 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2525 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2527 let Predicates = [prd, HasVLX] in {
2528 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2529 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2530 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2531 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2535 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2536 AVX512VLVectorVTInfo _,
2538 bit IsReMaterializable = 1> {
2539 let Predicates = [prd] in
2540 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2541 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2543 let Predicates = [prd, HasVLX] in {
2544 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2545 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2546 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2547 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2551 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2552 PatFrag st_frag, PatFrag mstore> {
2553 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2554 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2555 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2557 let Constraints = "$src1 = $dst" in
2558 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2559 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2561 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2562 [], _.ExeDomain>, EVEX, EVEX_K;
2563 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2564 (ins _.KRCWM:$mask, _.RC:$src),
2566 "\t{$src, ${dst} {${mask}} {z}|" #
2567 "${dst} {${mask}} {z}, $src}",
2568 [], _.ExeDomain>, EVEX, EVEX_KZ;
2570 let mayStore = 1 in {
2571 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2572 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2573 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2574 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2575 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2576 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2577 [], _.ExeDomain>, EVEX, EVEX_K;
2580 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2581 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2582 _.KRCWM:$mask, _.RC:$src)>;
2586 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2587 AVX512VLVectorVTInfo _, Predicate prd> {
2588 let Predicates = [prd] in
2589 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2590 masked_store_unaligned>, EVEX_V512;
2592 let Predicates = [prd, HasVLX] in {
2593 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2594 masked_store_unaligned>, EVEX_V256;
2595 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2596 masked_store_unaligned>, EVEX_V128;
2600 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2601 AVX512VLVectorVTInfo _, Predicate prd> {
2602 let Predicates = [prd] in
2603 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2604 masked_store_aligned512>, EVEX_V512;
2606 let Predicates = [prd, HasVLX] in {
2607 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2608 masked_store_aligned256>, EVEX_V256;
2609 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2610 masked_store_aligned128>, EVEX_V128;
2614 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2616 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2617 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2619 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2621 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2622 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2624 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2625 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2626 PS, EVEX_CD8<32, CD8VF>;
2628 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2629 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2630 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2632 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2633 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2634 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2636 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2637 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2638 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2640 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2641 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2642 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2644 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2645 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2646 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2648 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2649 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2650 (VMOVAPDZrm addr:$ptr)>;
2652 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2653 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2654 (VMOVAPSZrm addr:$ptr)>;
2656 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2658 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2660 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2662 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2665 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2667 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2669 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2671 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2674 let Predicates = [HasAVX512, NoVLX] in {
2675 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2676 (VMOVUPSZmrk addr:$ptr,
2677 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2678 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2680 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2681 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2682 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2684 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2685 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2686 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2687 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2690 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2692 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2693 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2695 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2697 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2698 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2700 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2701 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2702 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2704 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2705 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2706 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2708 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2709 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2710 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2712 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2713 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2714 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2716 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2717 (v16i32 immAllZerosV), GR16:$mask)),
2718 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2720 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2721 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2722 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2724 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2726 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2728 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2730 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2733 let AddedComplexity = 20 in {
2734 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2735 (bc_v8i64 (v16i32 immAllZerosV)))),
2736 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2738 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2739 (v8i64 VR512:$src))),
2740 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2743 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2744 (v16i32 immAllZerosV))),
2745 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2747 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2748 (v16i32 VR512:$src))),
2749 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2752 let Predicates = [HasAVX512, NoVLX] in {
2753 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2754 (VMOVDQU32Zmrk addr:$ptr,
2755 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2756 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2758 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2759 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2760 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2763 // Move Int Doubleword to Packed Double Int
2765 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2766 "vmovd\t{$src, $dst|$dst, $src}",
2768 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2770 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2771 "vmovd\t{$src, $dst|$dst, $src}",
2773 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2774 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2775 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2776 "vmovq\t{$src, $dst|$dst, $src}",
2778 (v2i64 (scalar_to_vector GR64:$src)))],
2779 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2780 let isCodeGenOnly = 1 in {
2781 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2782 "vmovq\t{$src, $dst|$dst, $src}",
2783 [(set FR64:$dst, (bitconvert GR64:$src))],
2784 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2785 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2786 "vmovq\t{$src, $dst|$dst, $src}",
2787 [(set GR64:$dst, (bitconvert FR64:$src))],
2788 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2790 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2791 "vmovq\t{$src, $dst|$dst, $src}",
2792 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2793 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2794 EVEX_CD8<64, CD8VT1>;
2796 // Move Int Doubleword to Single Scalar
2798 let isCodeGenOnly = 1 in {
2799 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2800 "vmovd\t{$src, $dst|$dst, $src}",
2801 [(set FR32X:$dst, (bitconvert GR32:$src))],
2802 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2804 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2805 "vmovd\t{$src, $dst|$dst, $src}",
2806 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2807 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2810 // Move doubleword from xmm register to r/m32
2812 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2813 "vmovd\t{$src, $dst|$dst, $src}",
2814 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2815 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2817 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2818 (ins i32mem:$dst, VR128X:$src),
2819 "vmovd\t{$src, $dst|$dst, $src}",
2820 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2821 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2822 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2824 // Move quadword from xmm1 register to r/m64
2826 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2827 "vmovq\t{$src, $dst|$dst, $src}",
2828 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2830 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2831 Requires<[HasAVX512, In64BitMode]>;
2833 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2834 (ins i64mem:$dst, VR128X:$src),
2835 "vmovq\t{$src, $dst|$dst, $src}",
2836 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2837 addr:$dst)], IIC_SSE_MOVDQ>,
2838 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2839 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2841 // Move Scalar Single to Double Int
2843 let isCodeGenOnly = 1 in {
2844 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2846 "vmovd\t{$src, $dst|$dst, $src}",
2847 [(set GR32:$dst, (bitconvert FR32X:$src))],
2848 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2849 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2850 (ins i32mem:$dst, FR32X:$src),
2851 "vmovd\t{$src, $dst|$dst, $src}",
2852 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2853 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2856 // Move Quadword Int to Packed Quadword Int
2858 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2860 "vmovq\t{$src, $dst|$dst, $src}",
2862 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2863 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2865 //===----------------------------------------------------------------------===//
2866 // AVX-512 MOVSS, MOVSD
2867 //===----------------------------------------------------------------------===//
2869 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2870 SDNode OpNode, ValueType vt,
2871 X86MemOperand x86memop, PatFrag mem_pat> {
2872 let hasSideEffects = 0 in {
2873 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2874 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2875 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2876 (scalar_to_vector RC:$src2))))],
2877 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2878 let Constraints = "$src1 = $dst" in
2879 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2880 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2882 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2883 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2884 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2885 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2886 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2888 let mayStore = 1 in {
2889 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2890 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2891 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2893 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2894 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2895 [], IIC_SSE_MOV_S_MR>,
2896 EVEX, VEX_LIG, EVEX_K;
2898 } //hasSideEffects = 0
2901 let ExeDomain = SSEPackedSingle in
2902 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2903 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2905 let ExeDomain = SSEPackedDouble in
2906 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2907 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2909 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2910 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2911 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2913 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2914 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2915 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2917 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2918 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2919 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2921 // For the disassembler
2922 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2923 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2924 (ins VR128X:$src1, FR32X:$src2),
2925 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2927 XS, EVEX_4V, VEX_LIG;
2928 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2929 (ins VR128X:$src1, FR64X:$src2),
2930 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2932 XD, EVEX_4V, VEX_LIG, VEX_W;
2935 let Predicates = [HasAVX512] in {
2936 let AddedComplexity = 15 in {
2937 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2938 // MOVS{S,D} to the lower bits.
2939 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2940 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2941 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2942 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2943 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2944 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2945 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2946 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2948 // Move low f32 and clear high bits.
2949 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2950 (SUBREG_TO_REG (i32 0),
2951 (VMOVSSZrr (v4f32 (V_SET0)),
2952 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2953 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2954 (SUBREG_TO_REG (i32 0),
2955 (VMOVSSZrr (v4i32 (V_SET0)),
2956 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2959 let AddedComplexity = 20 in {
2960 // MOVSSrm zeros the high parts of the register; represent this
2961 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2962 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2963 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2964 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2965 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2966 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2967 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2969 // MOVSDrm zeros the high parts of the register; represent this
2970 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2971 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2972 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2973 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2974 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2975 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2976 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2977 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2978 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2979 def : Pat<(v2f64 (X86vzload addr:$src)),
2980 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2982 // Represent the same patterns above but in the form they appear for
2984 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2985 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2986 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2987 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2988 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2989 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2990 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2991 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2992 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2994 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2995 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2996 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2997 FR32X:$src)), sub_xmm)>;
2998 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2999 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3000 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
3001 FR64X:$src)), sub_xmm)>;
3002 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3003 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3004 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3006 // Move low f64 and clear high bits.
3007 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3008 (SUBREG_TO_REG (i32 0),
3009 (VMOVSDZrr (v2f64 (V_SET0)),
3010 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3012 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3013 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3014 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3016 // Extract and store.
3017 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
3019 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3020 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
3022 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3024 // Shuffle with VMOVSS
3025 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3026 (VMOVSSZrr (v4i32 VR128X:$src1),
3027 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3028 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3029 (VMOVSSZrr (v4f32 VR128X:$src1),
3030 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3033 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3034 (SUBREG_TO_REG (i32 0),
3035 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3036 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3038 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3039 (SUBREG_TO_REG (i32 0),
3040 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3041 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3044 // Shuffle with VMOVSD
3045 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3046 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3047 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3048 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3049 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3050 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3051 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3052 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3055 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3056 (SUBREG_TO_REG (i32 0),
3057 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3058 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3060 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3061 (SUBREG_TO_REG (i32 0),
3062 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3063 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3066 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3067 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3068 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3069 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3070 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3071 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3072 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3073 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3076 let AddedComplexity = 15 in
3077 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3079 "vmovq\t{$src, $dst|$dst, $src}",
3080 [(set VR128X:$dst, (v2i64 (X86vzmovl
3081 (v2i64 VR128X:$src))))],
3082 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3084 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3085 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3087 "vmovq\t{$src, $dst|$dst, $src}",
3088 [(set VR128X:$dst, (v2i64 (X86vzmovl
3089 (loadv2i64 addr:$src))))],
3090 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3091 EVEX_CD8<8, CD8VT8>;
3093 let Predicates = [HasAVX512] in {
3094 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3095 let AddedComplexity = 20 in {
3096 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3097 (VMOVDI2PDIZrm addr:$src)>;
3098 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3099 (VMOV64toPQIZrr GR64:$src)>;
3100 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3101 (VMOVDI2PDIZrr GR32:$src)>;
3103 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3104 (VMOVDI2PDIZrm addr:$src)>;
3105 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3106 (VMOVDI2PDIZrm addr:$src)>;
3107 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3108 (VMOVZPQILo2PQIZrm addr:$src)>;
3109 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3110 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3111 def : Pat<(v2i64 (X86vzload addr:$src)),
3112 (VMOVZPQILo2PQIZrm addr:$src)>;
3115 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3116 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3117 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3118 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3119 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3120 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3121 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3124 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3125 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3127 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3128 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3130 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3131 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3133 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3134 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3136 //===----------------------------------------------------------------------===//
3137 // AVX-512 - Non-temporals
3138 //===----------------------------------------------------------------------===//
3139 let SchedRW = [WriteLoad] in {
3140 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3141 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3142 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3143 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3144 EVEX_CD8<64, CD8VF>;
3146 let Predicates = [HasAVX512, HasVLX] in {
3147 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3149 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3150 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3151 EVEX_CD8<64, CD8VF>;
3153 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3155 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3156 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3157 EVEX_CD8<64, CD8VF>;
3161 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3162 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3163 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3164 let SchedRW = [WriteStore], mayStore = 1,
3165 AddedComplexity = 400 in
3166 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3167 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3168 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3171 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3172 string elty, string elsz, string vsz512,
3173 string vsz256, string vsz128, Domain d,
3174 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3175 let Predicates = [prd] in
3176 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3177 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3178 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3181 let Predicates = [prd, HasVLX] in {
3182 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3183 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3184 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3187 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3188 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3189 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3194 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3195 "i", "64", "8", "4", "2", SSEPackedInt,
3196 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3198 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3199 "f", "64", "8", "4", "2", SSEPackedDouble,
3200 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3202 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3203 "f", "32", "16", "8", "4", SSEPackedSingle,
3204 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3206 //===----------------------------------------------------------------------===//
3207 // AVX-512 - Integer arithmetic
3209 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3210 X86VectorVTInfo _, OpndItins itins,
3211 bit IsCommutable = 0> {
3212 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3213 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3214 "$src2, $src1", "$src1, $src2",
3215 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3216 itins.rr, IsCommutable>,
3217 AVX512BIBase, EVEX_4V;
3220 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3221 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3222 "$src2, $src1", "$src1, $src2",
3223 (_.VT (OpNode _.RC:$src1,
3224 (bitconvert (_.LdFrag addr:$src2)))),
3226 AVX512BIBase, EVEX_4V;
3229 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3230 X86VectorVTInfo _, OpndItins itins,
3231 bit IsCommutable = 0> :
3232 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3234 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3235 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3236 "${src2}"##_.BroadcastStr##", $src1",
3237 "$src1, ${src2}"##_.BroadcastStr,
3238 (_.VT (OpNode _.RC:$src1,
3240 (_.ScalarLdFrag addr:$src2)))),
3242 AVX512BIBase, EVEX_4V, EVEX_B;
3245 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3246 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3247 Predicate prd, bit IsCommutable = 0> {
3248 let Predicates = [prd] in
3249 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3250 IsCommutable>, EVEX_V512;
3252 let Predicates = [prd, HasVLX] in {
3253 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3254 IsCommutable>, EVEX_V256;
3255 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3256 IsCommutable>, EVEX_V128;
3260 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3261 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3262 Predicate prd, bit IsCommutable = 0> {
3263 let Predicates = [prd] in
3264 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3265 IsCommutable>, EVEX_V512;
3267 let Predicates = [prd, HasVLX] in {
3268 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3269 IsCommutable>, EVEX_V256;
3270 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3271 IsCommutable>, EVEX_V128;
3275 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3276 OpndItins itins, Predicate prd,
3277 bit IsCommutable = 0> {
3278 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3279 itins, prd, IsCommutable>,
3280 VEX_W, EVEX_CD8<64, CD8VF>;
3283 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3284 OpndItins itins, Predicate prd,
3285 bit IsCommutable = 0> {
3286 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3287 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3290 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3291 OpndItins itins, Predicate prd,
3292 bit IsCommutable = 0> {
3293 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3294 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3297 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3298 OpndItins itins, Predicate prd,
3299 bit IsCommutable = 0> {
3300 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3301 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3304 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3305 SDNode OpNode, OpndItins itins, Predicate prd,
3306 bit IsCommutable = 0> {
3307 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3310 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3314 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3315 SDNode OpNode, OpndItins itins, Predicate prd,
3316 bit IsCommutable = 0> {
3317 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3320 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3324 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3325 bits<8> opc_d, bits<8> opc_q,
3326 string OpcodeStr, SDNode OpNode,
3327 OpndItins itins, bit IsCommutable = 0> {
3328 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3329 itins, HasAVX512, IsCommutable>,
3330 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3331 itins, HasBWI, IsCommutable>;
3334 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3335 SDNode OpNode,X86VectorVTInfo _Src,
3336 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3337 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3338 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3339 "$src2, $src1","$src1, $src2",
3341 (_Src.VT _Src.RC:$src1),
3342 (_Src.VT _Src.RC:$src2))),
3343 itins.rr, IsCommutable>,
3344 AVX512BIBase, EVEX_4V;
3345 let mayLoad = 1 in {
3346 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3347 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3348 "$src2, $src1", "$src1, $src2",
3349 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3350 (bitconvert (_Src.LdFrag addr:$src2)))),
3352 AVX512BIBase, EVEX_4V;
3354 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3355 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3357 "${src2}"##_Dst.BroadcastStr##", $src1",
3358 "$src1, ${src2}"##_Dst.BroadcastStr,
3359 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3360 (_Dst.VT (X86VBroadcast
3361 (_Dst.ScalarLdFrag addr:$src2)))))),
3363 AVX512BIBase, EVEX_4V, EVEX_B;
3367 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3368 SSE_INTALU_ITINS_P, 1>;
3369 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3370 SSE_INTALU_ITINS_P, 0>;
3371 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3372 SSE_INTALU_ITINS_P, HasBWI, 1>;
3373 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3374 SSE_INTALU_ITINS_P, HasBWI, 0>;
3375 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3376 SSE_INTALU_ITINS_P, HasBWI, 1>;
3377 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3378 SSE_INTALU_ITINS_P, HasBWI, 0>;
3379 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3380 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3381 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3382 SSE_INTALU_ITINS_P, HasBWI, 1>;
3383 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3384 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3385 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3387 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3389 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3391 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3392 SSE_INTALU_ITINS_P, HasBWI, 1>;
3394 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3395 SDNode OpNode, bit IsCommutable = 0> {
3397 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3398 v16i32_info, v8i64_info, IsCommutable>,
3399 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3400 let Predicates = [HasVLX] in {
3401 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3402 v8i32x_info, v4i64x_info, IsCommutable>,
3403 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3404 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3405 v4i32x_info, v2i64x_info, IsCommutable>,
3406 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3410 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3412 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3415 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3416 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3417 let mayLoad = 1 in {
3418 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3419 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3421 "${src2}"##_Src.BroadcastStr##", $src1",
3422 "$src1, ${src2}"##_Src.BroadcastStr,
3423 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3424 (_Src.VT (X86VBroadcast
3425 (_Src.ScalarLdFrag addr:$src2))))))>,
3426 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3430 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3431 SDNode OpNode,X86VectorVTInfo _Src,
3432 X86VectorVTInfo _Dst> {
3433 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3434 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3435 "$src2, $src1","$src1, $src2",
3437 (_Src.VT _Src.RC:$src1),
3438 (_Src.VT _Src.RC:$src2)))>,
3439 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3440 let mayLoad = 1 in {
3441 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3442 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3443 "$src2, $src1", "$src1, $src2",
3444 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3445 (bitconvert (_Src.LdFrag addr:$src2))))>,
3446 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3450 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3452 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3454 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3455 v32i16_info>, EVEX_V512;
3456 let Predicates = [HasVLX] in {
3457 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3459 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3460 v16i16x_info>, EVEX_V256;
3461 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3463 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3464 v8i16x_info>, EVEX_V128;
3467 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3469 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3470 v64i8_info>, EVEX_V512;
3471 let Predicates = [HasVLX] in {
3472 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3473 v32i8x_info>, EVEX_V256;
3474 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3475 v16i8x_info>, EVEX_V128;
3479 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3480 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3481 AVX512VLVectorVTInfo _Dst> {
3482 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3483 _Dst.info512>, EVEX_V512;
3484 let Predicates = [HasVLX] in {
3485 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3486 _Dst.info256>, EVEX_V256;
3487 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3488 _Dst.info128>, EVEX_V128;
3492 let Predicates = [HasBWI] in {
3493 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3494 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3495 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3496 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3498 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3499 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3500 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3501 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3504 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3505 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3506 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3507 SSE_INTALU_ITINS_P, HasBWI, 1>;
3508 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3509 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3511 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3512 SSE_INTALU_ITINS_P, HasBWI, 1>;
3513 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3514 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3515 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3516 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3518 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3519 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3520 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3521 SSE_INTALU_ITINS_P, HasBWI, 1>;
3522 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3523 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3525 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3526 SSE_INTALU_ITINS_P, HasBWI, 1>;
3527 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3528 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3529 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3530 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3531 //===----------------------------------------------------------------------===//
3532 // AVX-512 Logical Instructions
3533 //===----------------------------------------------------------------------===//
3535 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3536 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3537 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3538 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3539 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3540 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3541 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3542 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3544 //===----------------------------------------------------------------------===//
3545 // AVX-512 FP arithmetic
3546 //===----------------------------------------------------------------------===//
3547 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3548 SDNode OpNode, SDNode VecNode, OpndItins itins,
3551 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3552 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3553 "$src2, $src1", "$src1, $src2",
3554 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3555 (i32 FROUND_CURRENT)),
3556 itins.rr, IsCommutable>;
3558 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3559 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3560 "$src2, $src1", "$src1, $src2",
3561 (VecNode (_.VT _.RC:$src1),
3562 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3563 (i32 FROUND_CURRENT)),
3564 itins.rm, IsCommutable>;
3565 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3566 Predicates = [HasAVX512] in {
3567 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3568 (ins _.FRC:$src1, _.FRC:$src2),
3569 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3570 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3572 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3573 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3574 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3575 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3576 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3580 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3581 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3583 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3584 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3585 "$rc, $src2, $src1", "$src1, $src2, $rc",
3586 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3587 (i32 imm:$rc)), itins.rr, IsCommutable>,
3590 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3591 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3593 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3594 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3595 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3596 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3597 (i32 FROUND_NO_EXC))>, EVEX_B;
3600 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3602 SizeItins itins, bit IsCommutable> {
3603 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3604 itins.s, IsCommutable>,
3605 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3606 itins.s, IsCommutable>,
3607 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3608 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3609 itins.d, IsCommutable>,
3610 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3611 itins.d, IsCommutable>,
3612 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3615 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3617 SizeItins itins, bit IsCommutable> {
3618 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3619 itins.s, IsCommutable>,
3620 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3621 itins.s, IsCommutable>,
3622 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3623 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3624 itins.d, IsCommutable>,
3625 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3626 itins.d, IsCommutable>,
3627 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3629 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3630 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3631 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3632 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3633 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3634 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3636 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3637 X86VectorVTInfo _, bit IsCommutable> {
3638 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3639 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3640 "$src2, $src1", "$src1, $src2",
3641 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3642 let mayLoad = 1 in {
3643 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3644 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3645 "$src2, $src1", "$src1, $src2",
3646 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3647 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3648 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3649 "${src2}"##_.BroadcastStr##", $src1",
3650 "$src1, ${src2}"##_.BroadcastStr,
3651 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3652 (_.ScalarLdFrag addr:$src2))))>,
3657 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3658 X86VectorVTInfo _> {
3659 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3660 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3661 "$rc, $src2, $src1", "$src1, $src2, $rc",
3662 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3663 EVEX_4V, EVEX_B, EVEX_RC;
3667 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3668 X86VectorVTInfo _> {
3669 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3670 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3671 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3672 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3676 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3677 bit IsCommutable = 0> {
3678 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3679 IsCommutable>, EVEX_V512, PS,
3680 EVEX_CD8<32, CD8VF>;
3681 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3682 IsCommutable>, EVEX_V512, PD, VEX_W,
3683 EVEX_CD8<64, CD8VF>;
3685 // Define only if AVX512VL feature is present.
3686 let Predicates = [HasVLX] in {
3687 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3688 IsCommutable>, EVEX_V128, PS,
3689 EVEX_CD8<32, CD8VF>;
3690 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3691 IsCommutable>, EVEX_V256, PS,
3692 EVEX_CD8<32, CD8VF>;
3693 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3694 IsCommutable>, EVEX_V128, PD, VEX_W,
3695 EVEX_CD8<64, CD8VF>;
3696 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3697 IsCommutable>, EVEX_V256, PD, VEX_W,
3698 EVEX_CD8<64, CD8VF>;
3702 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3703 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3704 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3705 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3706 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3709 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3710 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3711 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3712 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3713 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3716 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3717 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3718 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3719 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3720 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3721 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3722 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3723 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3724 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3725 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3726 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3727 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3728 let Predicates = [HasDQI] in {
3729 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3730 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3731 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3732 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3735 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3736 X86VectorVTInfo _> {
3737 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3738 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3739 "$src2, $src1", "$src1, $src2",
3740 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3741 let mayLoad = 1 in {
3742 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3743 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3744 "$src2, $src1", "$src1, $src2",
3745 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3746 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3747 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3748 "${src2}"##_.BroadcastStr##", $src1",
3749 "$src1, ${src2}"##_.BroadcastStr,
3750 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3751 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3756 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3757 X86VectorVTInfo _> {
3758 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3759 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3760 "$src2, $src1", "$src1, $src2",
3761 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3762 let mayLoad = 1 in {
3763 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3764 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3765 "$src2, $src1", "$src1, $src2",
3766 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3770 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3771 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3772 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3773 EVEX_V512, EVEX_CD8<32, CD8VF>;
3774 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3775 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3776 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3777 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3778 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3779 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3780 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3781 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3782 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3784 // Define only if AVX512VL feature is present.
3785 let Predicates = [HasVLX] in {
3786 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3787 EVEX_V128, EVEX_CD8<32, CD8VF>;
3788 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3789 EVEX_V256, EVEX_CD8<32, CD8VF>;
3790 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3791 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3792 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3793 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3796 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3798 //===----------------------------------------------------------------------===//
3799 // AVX-512 VPTESTM instructions
3800 //===----------------------------------------------------------------------===//
3802 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3803 X86VectorVTInfo _> {
3804 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3805 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3806 "$src2, $src1", "$src1, $src2",
3807 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3810 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3811 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3812 "$src2, $src1", "$src1, $src2",
3813 (OpNode (_.VT _.RC:$src1),
3814 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3816 EVEX_CD8<_.EltSize, CD8VF>;
3819 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3820 X86VectorVTInfo _> {
3822 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3823 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3824 "${src2}"##_.BroadcastStr##", $src1",
3825 "$src1, ${src2}"##_.BroadcastStr,
3826 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3827 (_.ScalarLdFrag addr:$src2))))>,
3828 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3830 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3831 AVX512VLVectorVTInfo _> {
3832 let Predicates = [HasAVX512] in
3833 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3834 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3836 let Predicates = [HasAVX512, HasVLX] in {
3837 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3838 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3839 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3840 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3844 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3845 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3847 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3848 avx512vl_i64_info>, VEX_W;
3851 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3853 let Predicates = [HasBWI] in {
3854 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3856 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3859 let Predicates = [HasVLX, HasBWI] in {
3861 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3863 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3865 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3867 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3872 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3874 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3875 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3877 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3878 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3880 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3881 (v16i32 VR512:$src2), (i16 -1))),
3882 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3884 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3885 (v8i64 VR512:$src2), (i8 -1))),
3886 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3888 //===----------------------------------------------------------------------===//
3889 // AVX-512 Shift instructions
3890 //===----------------------------------------------------------------------===//
3891 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3892 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3893 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3894 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3895 "$src2, $src1", "$src1, $src2",
3896 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3897 SSE_INTSHIFT_ITINS_P.rr>;
3899 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3900 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3901 "$src2, $src1", "$src1, $src2",
3902 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3904 SSE_INTSHIFT_ITINS_P.rm>;
3907 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3908 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3910 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3911 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3912 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3913 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3914 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3917 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3918 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3919 // src2 is always 128-bit
3920 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3921 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3922 "$src2, $src1", "$src1, $src2",
3923 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3924 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3925 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3926 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3927 "$src2, $src1", "$src1, $src2",
3928 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3929 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3933 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3934 ValueType SrcVT, PatFrag bc_frag,
3935 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3936 let Predicates = [prd] in
3937 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3938 VTInfo.info512>, EVEX_V512,
3939 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3940 let Predicates = [prd, HasVLX] in {
3941 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3942 VTInfo.info256>, EVEX_V256,
3943 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3944 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3945 VTInfo.info128>, EVEX_V128,
3946 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3950 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3951 string OpcodeStr, SDNode OpNode> {
3952 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3953 avx512vl_i32_info, HasAVX512>;
3954 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3955 avx512vl_i64_info, HasAVX512>, VEX_W;
3956 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3957 avx512vl_i16_info, HasBWI>;
3960 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3961 string OpcodeStr, SDNode OpNode,
3962 AVX512VLVectorVTInfo VTInfo> {
3963 let Predicates = [HasAVX512] in
3964 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3966 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3967 VTInfo.info512>, EVEX_V512;
3968 let Predicates = [HasAVX512, HasVLX] in {
3969 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3971 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3972 VTInfo.info256>, EVEX_V256;
3973 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3975 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3976 VTInfo.info128>, EVEX_V128;
3980 multiclass avx512_shift_rmi_w<bits<8> opcw,
3981 Format ImmFormR, Format ImmFormM,
3982 string OpcodeStr, SDNode OpNode> {
3983 let Predicates = [HasBWI] in
3984 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3985 v32i16_info>, EVEX_V512;
3986 let Predicates = [HasVLX, HasBWI] in {
3987 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3988 v16i16x_info>, EVEX_V256;
3989 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3990 v8i16x_info>, EVEX_V128;
3994 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3995 Format ImmFormR, Format ImmFormM,
3996 string OpcodeStr, SDNode OpNode> {
3997 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3998 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3999 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4000 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4003 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4004 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4006 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4007 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4009 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4010 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4012 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4013 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4015 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4016 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4017 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4019 //===-------------------------------------------------------------------===//
4020 // Variable Bit Shifts
4021 //===-------------------------------------------------------------------===//
4022 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4023 X86VectorVTInfo _> {
4024 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4025 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4026 "$src2, $src1", "$src1, $src2",
4027 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4028 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4030 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4031 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4032 "$src2, $src1", "$src1, $src2",
4033 (_.VT (OpNode _.RC:$src1,
4034 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4035 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4036 EVEX_CD8<_.EltSize, CD8VF>;
4039 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4040 X86VectorVTInfo _> {
4042 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4043 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4044 "${src2}"##_.BroadcastStr##", $src1",
4045 "$src1, ${src2}"##_.BroadcastStr,
4046 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4047 (_.ScalarLdFrag addr:$src2))))),
4048 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4049 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4051 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4052 AVX512VLVectorVTInfo _> {
4053 let Predicates = [HasAVX512] in
4054 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4055 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4057 let Predicates = [HasAVX512, HasVLX] in {
4058 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4059 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4060 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4061 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4065 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4067 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4069 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4070 avx512vl_i64_info>, VEX_W;
4073 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4075 let Predicates = [HasBWI] in
4076 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4078 let Predicates = [HasVLX, HasBWI] in {
4080 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4082 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4087 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4088 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4089 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4090 avx512_var_shift_w<0x11, "vpsravw", sra>;
4091 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4092 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4093 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4094 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4096 //===-------------------------------------------------------------------===//
4097 // 1-src variable permutation VPERMW/D/Q
4098 //===-------------------------------------------------------------------===//
4099 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4100 AVX512VLVectorVTInfo _> {
4101 let Predicates = [HasAVX512] in
4102 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4103 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4105 let Predicates = [HasAVX512, HasVLX] in
4106 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4107 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4110 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4111 string OpcodeStr, SDNode OpNode,
4112 AVX512VLVectorVTInfo VTInfo> {
4113 let Predicates = [HasAVX512] in
4114 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4116 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4117 VTInfo.info512>, EVEX_V512;
4118 let Predicates = [HasAVX512, HasVLX] in
4119 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4121 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4122 VTInfo.info256>, EVEX_V256;
4126 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4128 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4130 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4131 avx512vl_i64_info>, VEX_W;
4132 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4134 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4135 avx512vl_f64_info>, VEX_W;
4137 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4138 X86VPermi, avx512vl_i64_info>,
4139 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4140 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4141 X86VPermi, avx512vl_f64_info>,
4142 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4143 //===----------------------------------------------------------------------===//
4144 // AVX-512 - VPERMIL
4145 //===----------------------------------------------------------------------===//
4147 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4148 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4149 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4150 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4151 "$src2, $src1", "$src1, $src2",
4152 (_.VT (OpNode _.RC:$src1,
4153 (Ctrl.VT Ctrl.RC:$src2)))>,
4155 let mayLoad = 1 in {
4156 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4157 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4158 "$src2, $src1", "$src1, $src2",
4161 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4162 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4163 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4164 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4165 "${src2}"##_.BroadcastStr##", $src1",
4166 "$src1, ${src2}"##_.BroadcastStr,
4169 (Ctrl.VT (X86VBroadcast
4170 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4171 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4175 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4176 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4177 let Predicates = [HasAVX512] in {
4178 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4179 Ctrl.info512>, EVEX_V512;
4181 let Predicates = [HasAVX512, HasVLX] in {
4182 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4183 Ctrl.info128>, EVEX_V128;
4184 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4185 Ctrl.info256>, EVEX_V256;
4189 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4190 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4192 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4193 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4195 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4197 let isCodeGenOnly = 1 in {
4198 // lowering implementation with the alternative types
4199 defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
4200 defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
4201 OpcodeStr, X86VPermilpi, Ctrl>,
4202 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4206 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4208 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4209 avx512vl_i64_info>, VEX_W;
4210 //===----------------------------------------------------------------------===//
4211 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4212 //===----------------------------------------------------------------------===//
4214 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4215 X86PShufd, avx512vl_i32_info>,
4216 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4217 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4218 X86PShufhw>, EVEX, AVX512XSIi8Base;
4219 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4220 X86PShuflw>, EVEX, AVX512XDIi8Base;
4222 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4223 let Predicates = [HasBWI] in
4224 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4226 let Predicates = [HasVLX, HasBWI] in {
4227 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4228 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4232 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4234 //===----------------------------------------------------------------------===//
4235 // AVX-512 - MOVDDUP
4236 //===----------------------------------------------------------------------===//
4238 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
4239 X86MemOperand x86memop, PatFrag memop_frag> {
4240 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4241 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4242 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
4243 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4244 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4246 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
4249 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
4250 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4251 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
4252 (VMOVDDUPZrm addr:$src)>;
4254 //===----------------------------------------------------------------------===//
4255 // Move Low to High and High to Low packed FP Instructions
4256 //===----------------------------------------------------------------------===//
4257 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4258 (ins VR128X:$src1, VR128X:$src2),
4259 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4260 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4261 IIC_SSE_MOV_LH>, EVEX_4V;
4262 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4263 (ins VR128X:$src1, VR128X:$src2),
4264 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4265 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4266 IIC_SSE_MOV_LH>, EVEX_4V;
4268 let Predicates = [HasAVX512] in {
4270 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4271 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4272 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4273 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4276 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4277 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4280 //===----------------------------------------------------------------------===//
4281 // VMOVHPS/PD VMOVLPS Instructions
4282 // All patterns was taken from SSS implementation.
4283 //===----------------------------------------------------------------------===//
4284 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4285 X86VectorVTInfo _> {
4287 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
4288 (ins _.RC:$src1, f64mem:$src2),
4289 !strconcat(OpcodeStr,
4290 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4294 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
4295 IIC_SSE_MOV_LH>, EVEX_4V;
4298 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
4299 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4300 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
4301 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4302 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
4303 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4304 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
4305 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4307 let Predicates = [HasAVX512] in {
4309 def : Pat<(X86Movlhps VR128X:$src1,
4310 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
4311 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4312 def : Pat<(X86Movlhps VR128X:$src1,
4313 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
4314 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4316 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4317 (scalar_to_vector (loadf64 addr:$src2)))),
4318 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4319 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4320 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
4321 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4323 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4324 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4325 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4326 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4328 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4329 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4330 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4331 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4332 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
4333 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
4334 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4337 let mayStore = 1 in {
4338 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
4339 (ins f64mem:$dst, VR128X:$src),
4340 "vmovhps\t{$src, $dst|$dst, $src}",
4341 [(store (f64 (vector_extract
4342 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
4343 (bc_v2f64 (v4f32 VR128X:$src))),
4344 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4345 EVEX, EVEX_CD8<32, CD8VT2>;
4346 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
4347 (ins f64mem:$dst, VR128X:$src),
4348 "vmovhpd\t{$src, $dst|$dst, $src}",
4349 [(store (f64 (vector_extract
4350 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
4351 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4352 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4353 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
4354 (ins f64mem:$dst, VR128X:$src),
4355 "vmovlps\t{$src, $dst|$dst, $src}",
4356 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128X:$src)),
4357 (iPTR 0))), addr:$dst)],
4359 EVEX, EVEX_CD8<32, CD8VT2>;
4360 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
4361 (ins f64mem:$dst, VR128X:$src),
4362 "vmovlpd\t{$src, $dst|$dst, $src}",
4363 [(store (f64 (vector_extract (v2f64 VR128X:$src),
4364 (iPTR 0))), addr:$dst)],
4366 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4368 let Predicates = [HasAVX512] in {
4370 def : Pat<(store (f64 (vector_extract
4371 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
4372 (iPTR 0))), addr:$dst),
4373 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
4375 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
4377 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4378 def : Pat<(store (v4i32 (X86Movlps
4379 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
4380 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4382 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4384 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4385 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4387 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4389 //===----------------------------------------------------------------------===//
4390 // FMA - Fused Multiply Operations
4393 let Constraints = "$src1 = $dst" in {
4394 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4395 X86VectorVTInfo _> {
4396 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4397 (ins _.RC:$src2, _.RC:$src3),
4398 OpcodeStr, "$src3, $src2", "$src2, $src3",
4399 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4402 let mayLoad = 1 in {
4403 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4404 (ins _.RC:$src2, _.MemOp:$src3),
4405 OpcodeStr, "$src3, $src2", "$src2, $src3",
4406 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4409 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4410 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4411 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4412 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4414 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4415 AVX512FMA3Base, EVEX_B;
4419 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4420 X86VectorVTInfo _> {
4421 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4422 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4423 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4424 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4425 AVX512FMA3Base, EVEX_B, EVEX_RC;
4427 } // Constraints = "$src1 = $dst"
4429 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4430 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4431 let Predicates = [HasAVX512] in {
4432 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4433 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4434 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4436 let Predicates = [HasVLX, HasAVX512] in {
4437 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4438 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4439 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4440 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4444 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4445 SDNode OpNodeRnd > {
4446 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4448 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4449 avx512vl_f64_info>, VEX_W;
4452 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4453 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4454 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4455 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4456 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4457 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4460 let Constraints = "$src1 = $dst" in {
4461 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4462 X86VectorVTInfo _> {
4463 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4464 (ins _.RC:$src2, _.RC:$src3),
4465 OpcodeStr, "$src3, $src2", "$src2, $src3",
4466 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4469 let mayLoad = 1 in {
4470 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4471 (ins _.RC:$src2, _.MemOp:$src3),
4472 OpcodeStr, "$src3, $src2", "$src2, $src3",
4473 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4476 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4477 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4478 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4479 "$src2, ${src3}"##_.BroadcastStr,
4480 (_.VT (OpNode _.RC:$src2,
4481 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4482 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4486 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4487 X86VectorVTInfo _> {
4488 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4489 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4490 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4491 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4492 AVX512FMA3Base, EVEX_B, EVEX_RC;
4494 } // Constraints = "$src1 = $dst"
4496 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4497 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4498 let Predicates = [HasAVX512] in {
4499 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4500 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4501 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4503 let Predicates = [HasVLX, HasAVX512] in {
4504 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4505 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4506 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4507 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4511 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4512 SDNode OpNodeRnd > {
4513 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4515 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4516 avx512vl_f64_info>, VEX_W;
4519 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4520 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4521 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4522 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4523 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4524 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4526 let Constraints = "$src1 = $dst" in {
4527 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4528 X86VectorVTInfo _> {
4529 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4530 (ins _.RC:$src3, _.RC:$src2),
4531 OpcodeStr, "$src2, $src3", "$src3, $src2",
4532 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4535 let mayLoad = 1 in {
4536 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4537 (ins _.RC:$src3, _.MemOp:$src2),
4538 OpcodeStr, "$src2, $src3", "$src3, $src2",
4539 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4542 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4543 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4544 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4545 "$src3, ${src2}"##_.BroadcastStr,
4546 (_.VT (OpNode _.RC:$src1,
4547 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4548 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4552 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4553 X86VectorVTInfo _> {
4554 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4555 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4556 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4557 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4558 AVX512FMA3Base, EVEX_B, EVEX_RC;
4560 } // Constraints = "$src1 = $dst"
4562 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4563 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4564 let Predicates = [HasAVX512] in {
4565 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4566 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4567 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4569 let Predicates = [HasVLX, HasAVX512] in {
4570 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4571 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4572 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4573 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4577 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4578 SDNode OpNodeRnd > {
4579 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4581 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4582 avx512vl_f64_info>, VEX_W;
4585 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4586 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4587 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4588 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4589 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4590 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4593 let Constraints = "$src1 = $dst" in {
4594 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4595 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4596 dag RHS_r, dag RHS_m > {
4597 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4598 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4599 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4602 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4603 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4604 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4606 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4607 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4608 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4609 AVX512FMA3Base, EVEX_B, EVEX_RC;
4611 let isCodeGenOnly = 1 in {
4612 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4613 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4614 !strconcat(OpcodeStr,
4615 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4618 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4619 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4620 !strconcat(OpcodeStr,
4621 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4623 }// isCodeGenOnly = 1
4625 }// Constraints = "$src1 = $dst"
4627 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4628 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4631 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4632 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4633 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4634 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4635 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4637 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4639 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4640 (_.ScalarLdFrag addr:$src3))))>;
4642 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4643 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4644 (_.VT (OpNode _.RC:$src2,
4645 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4647 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4649 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4651 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4652 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4654 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4655 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4656 (_.VT (OpNode _.RC:$src1,
4657 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4659 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4661 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4663 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4664 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4667 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4668 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4669 let Predicates = [HasAVX512] in {
4670 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4671 OpNodeRnd, f32x_info, "SS">,
4672 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4673 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4674 OpNodeRnd, f64x_info, "SD">,
4675 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4679 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4680 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4681 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4682 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4684 //===----------------------------------------------------------------------===//
4685 // AVX-512 Scalar convert from sign integer to float/double
4686 //===----------------------------------------------------------------------===//
4688 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4689 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4690 PatFrag ld_frag, string asm> {
4691 let hasSideEffects = 0 in {
4692 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4693 (ins DstVT.FRC:$src1, SrcRC:$src),
4694 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4697 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4698 (ins DstVT.FRC:$src1, x86memop:$src),
4699 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4701 } // hasSideEffects = 0
4702 let isCodeGenOnly = 1 in {
4703 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4704 (ins DstVT.RC:$src1, SrcRC:$src2),
4705 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4706 [(set DstVT.RC:$dst,
4707 (OpNode (DstVT.VT DstVT.RC:$src1),
4709 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4711 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4712 (ins DstVT.RC:$src1, x86memop:$src2),
4713 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4714 [(set DstVT.RC:$dst,
4715 (OpNode (DstVT.VT DstVT.RC:$src1),
4716 (ld_frag addr:$src2),
4717 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4718 }//isCodeGenOnly = 1
4721 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4722 X86VectorVTInfo DstVT, string asm> {
4723 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4724 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4726 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4727 [(set DstVT.RC:$dst,
4728 (OpNode (DstVT.VT DstVT.RC:$src1),
4730 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4733 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4734 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4735 PatFrag ld_frag, string asm> {
4736 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4737 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4741 let Predicates = [HasAVX512] in {
4742 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4743 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4744 XS, EVEX_CD8<32, CD8VT1>;
4745 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4746 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4747 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4748 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4749 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4750 XD, EVEX_CD8<32, CD8VT1>;
4751 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4752 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4753 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4755 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4756 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4757 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4758 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4759 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4760 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4761 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4762 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4764 def : Pat<(f32 (sint_to_fp GR32:$src)),
4765 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4766 def : Pat<(f32 (sint_to_fp GR64:$src)),
4767 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4768 def : Pat<(f64 (sint_to_fp GR32:$src)),
4769 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4770 def : Pat<(f64 (sint_to_fp GR64:$src)),
4771 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4773 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4774 v4f32x_info, i32mem, loadi32,
4775 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4776 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4777 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4778 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4779 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4780 i32mem, loadi32, "cvtusi2sd{l}">,
4781 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4782 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4783 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4784 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4786 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4787 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4788 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4789 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4790 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4791 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4792 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4793 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4795 def : Pat<(f32 (uint_to_fp GR32:$src)),
4796 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4797 def : Pat<(f32 (uint_to_fp GR64:$src)),
4798 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4799 def : Pat<(f64 (uint_to_fp GR32:$src)),
4800 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4801 def : Pat<(f64 (uint_to_fp GR64:$src)),
4802 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4805 //===----------------------------------------------------------------------===//
4806 // AVX-512 Scalar convert from float/double to integer
4807 //===----------------------------------------------------------------------===//
4808 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4809 RegisterClass DstRC, Intrinsic Int,
4810 Operand memop, ComplexPattern mem_cpat, string asm> {
4811 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4812 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4813 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4814 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4815 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4816 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4817 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4819 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4820 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4821 } // hasSideEffects = 0, Predicates = [HasAVX512]
4824 // Convert float/double to signed/unsigned int 32/64
4825 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4826 ssmem, sse_load_f32, "cvtss2si">,
4827 XS, EVEX_CD8<32, CD8VT1>;
4828 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4829 int_x86_sse_cvtss2si64,
4830 ssmem, sse_load_f32, "cvtss2si">,
4831 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4832 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4833 int_x86_avx512_cvtss2usi,
4834 ssmem, sse_load_f32, "cvtss2usi">,
4835 XS, EVEX_CD8<32, CD8VT1>;
4836 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4837 int_x86_avx512_cvtss2usi64, ssmem,
4838 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4839 EVEX_CD8<32, CD8VT1>;
4840 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4841 sdmem, sse_load_f64, "cvtsd2si">,
4842 XD, EVEX_CD8<64, CD8VT1>;
4843 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4844 int_x86_sse2_cvtsd2si64,
4845 sdmem, sse_load_f64, "cvtsd2si">,
4846 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4847 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4848 int_x86_avx512_cvtsd2usi,
4849 sdmem, sse_load_f64, "cvtsd2usi">,
4850 XD, EVEX_CD8<64, CD8VT1>;
4851 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4852 int_x86_avx512_cvtsd2usi64, sdmem,
4853 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4854 EVEX_CD8<64, CD8VT1>;
4856 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4857 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4858 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4859 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4860 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4861 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4862 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4863 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4864 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4865 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4866 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4867 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4868 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4870 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4871 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4872 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4873 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4875 // Convert float/double to signed/unsigned int 32/64 with truncation
4876 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4877 X86VectorVTInfo _DstRC, SDNode OpNode,
4879 let Predicates = [HasAVX512] in {
4880 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4881 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4882 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4883 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4884 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4886 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4887 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4888 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4891 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4892 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4893 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4894 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4895 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4896 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4897 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4898 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4899 (i32 FROUND_NO_EXC)))]>,
4900 EVEX,VEX_LIG , EVEX_B;
4902 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4903 (ins _SrcRC.MemOp:$src),
4904 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4907 } // isCodeGenOnly = 1, hasSideEffects = 0
4912 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4913 fp_to_sint,X86cvttss2IntRnd>,
4914 XS, EVEX_CD8<32, CD8VT1>;
4915 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4916 fp_to_sint,X86cvttss2IntRnd>,
4917 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4918 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4919 fp_to_sint,X86cvttsd2IntRnd>,
4920 XD, EVEX_CD8<64, CD8VT1>;
4921 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4922 fp_to_sint,X86cvttsd2IntRnd>,
4923 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4925 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
4926 fp_to_uint,X86cvttss2UIntRnd>,
4927 XS, EVEX_CD8<32, CD8VT1>;
4928 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
4929 fp_to_uint,X86cvttss2UIntRnd>,
4930 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
4931 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
4932 fp_to_uint,X86cvttsd2UIntRnd>,
4933 XD, EVEX_CD8<64, CD8VT1>;
4934 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
4935 fp_to_uint,X86cvttsd2UIntRnd>,
4936 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4937 let Predicates = [HasAVX512] in {
4938 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
4939 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4940 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
4941 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4942 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
4943 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4944 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
4945 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4948 //===----------------------------------------------------------------------===//
4949 // AVX-512 Convert form float to double and back
4950 //===----------------------------------------------------------------------===//
4951 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4952 X86VectorVTInfo _Src, SDNode OpNode> {
4953 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4954 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4955 "$src2, $src1", "$src1, $src2",
4956 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4957 (_Src.VT _Src.RC:$src2)))>,
4958 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4959 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4960 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4961 "$src2, $src1", "$src1, $src2",
4962 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4963 (_Src.VT (scalar_to_vector
4964 (_Src.ScalarLdFrag addr:$src2)))))>,
4965 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
4968 // Scalar Coversion with SAE - suppress all exceptions
4969 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4970 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4971 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4972 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4973 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4974 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4975 (_Src.VT _Src.RC:$src2),
4976 (i32 FROUND_NO_EXC)))>,
4977 EVEX_4V, VEX_LIG, EVEX_B;
4980 // Scalar Conversion with rounding control (RC)
4981 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4982 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4983 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4984 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
4985 "$rc, $src2, $src1", "$src1, $src2, $rc",
4986 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4987 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
4988 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4991 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
4992 SDNode OpNodeRnd, X86VectorVTInfo _src,
4993 X86VectorVTInfo _dst> {
4994 let Predicates = [HasAVX512] in {
4995 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4996 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
4997 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
5002 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5003 SDNode OpNodeRnd, X86VectorVTInfo _src,
5004 X86VectorVTInfo _dst> {
5005 let Predicates = [HasAVX512] in {
5006 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5007 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
5008 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
5011 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
5012 X86froundRnd, f64x_info, f32x_info>;
5013 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
5014 X86fpextRnd,f32x_info, f64x_info >;
5016 def : Pat<(f64 (fextend FR32X:$src)),
5017 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
5018 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
5019 Requires<[HasAVX512]>;
5020 def : Pat<(f64 (fextend (loadf32 addr:$src))),
5021 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5022 Requires<[HasAVX512]>;
5024 def : Pat<(f64 (extloadf32 addr:$src)),
5025 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5026 Requires<[HasAVX512, OptForSize]>;
5028 def : Pat<(f64 (extloadf32 addr:$src)),
5029 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
5030 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
5031 Requires<[HasAVX512, OptForSpeed]>;
5033 def : Pat<(f32 (fround FR64X:$src)),
5034 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
5035 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
5036 Requires<[HasAVX512]>;
5037 //===----------------------------------------------------------------------===//
5038 // AVX-512 Vector convert from signed/unsigned integer to float/double
5039 // and from float/double to signed/unsigned integer
5040 //===----------------------------------------------------------------------===//
5042 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5043 X86VectorVTInfo _Src, SDNode OpNode,
5044 string Broadcast = _.BroadcastStr,
5045 string Alias = ""> {
5047 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5048 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
5049 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
5051 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5052 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
5053 (_.VT (OpNode (_Src.VT
5054 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
5056 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5057 (ins _Src.MemOp:$src), OpcodeStr,
5058 "${src}"##Broadcast, "${src}"##Broadcast,
5059 (_.VT (OpNode (_Src.VT
5060 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
5063 // Coversion with SAE - suppress all exceptions
5064 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5065 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5066 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5067 (ins _Src.RC:$src), OpcodeStr,
5068 "{sae}, $src", "$src, {sae}",
5069 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
5070 (i32 FROUND_NO_EXC)))>,
5074 // Conversion with rounding control (RC)
5075 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5076 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5077 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5078 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5079 "$rc, $src", "$src, $rc",
5080 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5081 EVEX, EVEX_B, EVEX_RC;
5084 // Extend Float to Double
5085 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5086 let Predicates = [HasAVX512] in {
5087 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5088 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5089 X86vfpextRnd>, EVEX_V512;
5091 let Predicates = [HasVLX] in {
5092 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5093 X86vfpext, "{1to2}">, EVEX_V128;
5094 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5099 // Truncate Double to Float
5100 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5101 let Predicates = [HasAVX512] in {
5102 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5103 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5104 X86vfproundRnd>, EVEX_V512;
5106 let Predicates = [HasVLX] in {
5107 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5108 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5109 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5110 "{1to4}", "{y}">, EVEX_V256;
5114 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5115 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5116 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5117 PS, EVEX_CD8<32, CD8VH>;
5119 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5120 (VCVTPS2PDZrm addr:$src)>;
5122 let Predicates = [HasVLX] in {
5123 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5124 (VCVTPS2PDZ256rm addr:$src)>;
5127 // Convert Signed/Unsigned Doubleword to Double
5128 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5130 // No rounding in this op
5131 let Predicates = [HasAVX512] in
5132 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5135 let Predicates = [HasVLX] in {
5136 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5137 OpNode128, "{1to2}">, EVEX_V128;
5138 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5143 // Convert Signed/Unsigned Doubleword to Float
5144 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5146 let Predicates = [HasAVX512] in
5147 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5148 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5149 OpNodeRnd>, EVEX_V512;
5151 let Predicates = [HasVLX] in {
5152 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5154 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5159 // Convert Float to Signed/Unsigned Doubleword with truncation
5160 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5161 SDNode OpNode, SDNode OpNodeRnd> {
5162 let Predicates = [HasAVX512] in {
5163 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5164 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5165 OpNodeRnd>, EVEX_V512;
5167 let Predicates = [HasVLX] in {
5168 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5170 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5175 // Convert Float to Signed/Unsigned Doubleword
5176 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5177 SDNode OpNode, SDNode OpNodeRnd> {
5178 let Predicates = [HasAVX512] in {
5179 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5180 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5181 OpNodeRnd>, EVEX_V512;
5183 let Predicates = [HasVLX] in {
5184 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5186 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5191 // Convert Double to Signed/Unsigned Doubleword with truncation
5192 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5193 SDNode OpNode, SDNode OpNodeRnd> {
5194 let Predicates = [HasAVX512] in {
5195 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5196 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5197 OpNodeRnd>, EVEX_V512;
5199 let Predicates = [HasVLX] in {
5200 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5201 // memory forms of these instructions in Asm Parcer. They have the same
5202 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5203 // due to the same reason.
5204 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5205 "{1to2}", "{x}">, EVEX_V128;
5206 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5207 "{1to4}", "{y}">, EVEX_V256;
5211 // Convert Double to Signed/Unsigned Doubleword
5212 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5213 SDNode OpNode, SDNode OpNodeRnd> {
5214 let Predicates = [HasAVX512] in {
5215 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5216 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5217 OpNodeRnd>, EVEX_V512;
5219 let Predicates = [HasVLX] in {
5220 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5221 // memory forms of these instructions in Asm Parcer. They have the same
5222 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5223 // due to the same reason.
5224 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5225 "{1to2}", "{x}">, EVEX_V128;
5226 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5227 "{1to4}", "{y}">, EVEX_V256;
5231 // Convert Double to Signed/Unsigned Quardword
5232 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5233 SDNode OpNode, SDNode OpNodeRnd> {
5234 let Predicates = [HasDQI] in {
5235 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5236 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5237 OpNodeRnd>, EVEX_V512;
5239 let Predicates = [HasDQI, HasVLX] in {
5240 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5242 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5247 // Convert Double to Signed/Unsigned Quardword with truncation
5248 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5249 SDNode OpNode, SDNode OpNodeRnd> {
5250 let Predicates = [HasDQI] in {
5251 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5252 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5253 OpNodeRnd>, EVEX_V512;
5255 let Predicates = [HasDQI, HasVLX] in {
5256 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5258 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5263 // Convert Signed/Unsigned Quardword to Double
5264 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5265 SDNode OpNode, SDNode OpNodeRnd> {
5266 let Predicates = [HasDQI] in {
5267 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5268 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5269 OpNodeRnd>, EVEX_V512;
5271 let Predicates = [HasDQI, HasVLX] in {
5272 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5274 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5279 // Convert Float to Signed/Unsigned Quardword
5280 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5281 SDNode OpNode, SDNode OpNodeRnd> {
5282 let Predicates = [HasDQI] in {
5283 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5284 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5285 OpNodeRnd>, EVEX_V512;
5287 let Predicates = [HasDQI, HasVLX] in {
5288 // Explicitly specified broadcast string, since we take only 2 elements
5289 // from v4f32x_info source
5290 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5291 "{1to2}">, EVEX_V128;
5292 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5297 // Convert Float to Signed/Unsigned Quardword with truncation
5298 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5299 SDNode OpNode, SDNode OpNodeRnd> {
5300 let Predicates = [HasDQI] in {
5301 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5302 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5303 OpNodeRnd>, EVEX_V512;
5305 let Predicates = [HasDQI, HasVLX] in {
5306 // Explicitly specified broadcast string, since we take only 2 elements
5307 // from v4f32x_info source
5308 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5309 "{1to2}">, EVEX_V128;
5310 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5315 // Convert Signed/Unsigned Quardword to Float
5316 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5317 SDNode OpNode, SDNode OpNodeRnd> {
5318 let Predicates = [HasDQI] in {
5319 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5320 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5321 OpNodeRnd>, EVEX_V512;
5323 let Predicates = [HasDQI, HasVLX] in {
5324 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5325 // memory forms of these instructions in Asm Parcer. They have the same
5326 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5327 // due to the same reason.
5328 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5329 "{1to2}", "{x}">, EVEX_V128;
5330 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5331 "{1to4}", "{y}">, EVEX_V256;
5335 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5336 EVEX_CD8<32, CD8VH>;
5338 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5340 PS, EVEX_CD8<32, CD8VF>;
5342 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5344 XS, EVEX_CD8<32, CD8VF>;
5346 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5348 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5350 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5351 X86VFpToUintRnd>, PS,
5352 EVEX_CD8<32, CD8VF>;
5354 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5355 X86VFpToUintRnd>, PS, VEX_W,
5356 EVEX_CD8<64, CD8VF>;
5358 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5359 XS, EVEX_CD8<32, CD8VH>;
5361 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5362 X86VUintToFpRnd>, XD,
5363 EVEX_CD8<32, CD8VF>;
5365 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5366 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5368 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5369 X86cvtpd2IntRnd>, XD, VEX_W,
5370 EVEX_CD8<64, CD8VF>;
5372 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5374 PS, EVEX_CD8<32, CD8VF>;
5375 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5376 X86cvtpd2UIntRnd>, VEX_W,
5377 PS, EVEX_CD8<64, CD8VF>;
5379 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5380 X86cvtpd2IntRnd>, VEX_W,
5381 PD, EVEX_CD8<64, CD8VF>;
5383 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5384 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5386 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5387 X86cvtpd2UIntRnd>, VEX_W,
5388 PD, EVEX_CD8<64, CD8VF>;
5390 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5391 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5393 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5394 X86VFpToSlongRnd>, VEX_W,
5395 PD, EVEX_CD8<64, CD8VF>;
5397 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5398 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5400 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5401 X86VFpToUlongRnd>, VEX_W,
5402 PD, EVEX_CD8<64, CD8VF>;
5404 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5405 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5407 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5408 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5410 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5411 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5413 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5414 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5416 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5417 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5419 let Predicates = [NoVLX] in {
5420 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5421 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5422 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5424 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5425 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5426 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5428 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5429 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5430 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5432 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5433 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5434 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5436 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5437 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5438 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5441 let Predicates = [HasAVX512] in {
5442 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5443 (VCVTPD2PSZrm addr:$src)>;
5444 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5445 (VCVTPS2PDZrm addr:$src)>;
5448 //===----------------------------------------------------------------------===//
5449 // Half precision conversion instructions
5450 //===----------------------------------------------------------------------===//
5451 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5452 X86MemOperand x86memop, PatFrag ld_frag> {
5453 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5454 "vcvtph2ps", "$src", "$src",
5455 (X86cvtph2ps (_src.VT _src.RC:$src),
5456 (i32 FROUND_CURRENT))>, T8PD;
5457 let hasSideEffects = 0, mayLoad = 1 in {
5458 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5459 "vcvtph2ps", "$src", "$src",
5460 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5461 (i32 FROUND_CURRENT))>, T8PD;
5465 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5466 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5467 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5468 (X86cvtph2ps (_src.VT _src.RC:$src),
5469 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5473 let Predicates = [HasAVX512] in {
5474 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5475 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5476 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5477 let Predicates = [HasVLX] in {
5478 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5479 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5480 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5481 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5485 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5486 X86MemOperand x86memop> {
5487 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5488 (ins _src.RC:$src1, i32u8imm:$src2),
5489 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5490 (X86cvtps2ph (_src.VT _src.RC:$src1),
5492 (i32 FROUND_CURRENT))>, AVX512AIi8Base;
5493 let hasSideEffects = 0, mayStore = 1 in {
5494 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5495 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5496 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5497 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5498 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5500 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5501 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5502 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5506 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5507 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5508 (ins _src.RC:$src1, i32u8imm:$src2),
5509 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, $src2, {sae}",
5510 (X86cvtps2ph (_src.VT _src.RC:$src1),
5512 (i32 FROUND_NO_EXC))>, EVEX_B, AVX512AIi8Base;
5514 let Predicates = [HasAVX512] in {
5515 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5516 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5517 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5518 let Predicates = [HasVLX] in {
5519 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5520 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5521 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5522 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5525 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5526 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5527 "ucomiss">, PS, EVEX, VEX_LIG,
5528 EVEX_CD8<32, CD8VT1>;
5529 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5530 "ucomisd">, PD, EVEX,
5531 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5532 let Pattern = []<dag> in {
5533 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5534 "comiss">, PS, EVEX, VEX_LIG,
5535 EVEX_CD8<32, CD8VT1>;
5536 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5537 "comisd">, PD, EVEX,
5538 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5540 let isCodeGenOnly = 1 in {
5541 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5542 load, "ucomiss">, PS, EVEX, VEX_LIG,
5543 EVEX_CD8<32, CD8VT1>;
5544 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5545 load, "ucomisd">, PD, EVEX,
5546 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5548 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5549 load, "comiss">, PS, EVEX, VEX_LIG,
5550 EVEX_CD8<32, CD8VT1>;
5551 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5552 load, "comisd">, PD, EVEX,
5553 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5557 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5558 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5559 X86VectorVTInfo _> {
5560 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5561 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5562 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5563 "$src2, $src1", "$src1, $src2",
5564 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5565 let mayLoad = 1 in {
5566 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5567 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5568 "$src2, $src1", "$src1, $src2",
5569 (OpNode (_.VT _.RC:$src1),
5570 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5575 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5576 EVEX_CD8<32, CD8VT1>, T8PD;
5577 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5578 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5579 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5580 EVEX_CD8<32, CD8VT1>, T8PD;
5581 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5582 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5584 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5585 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5586 X86VectorVTInfo _> {
5587 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5588 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5589 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5590 let mayLoad = 1 in {
5591 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5592 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5594 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5595 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5596 (ins _.ScalarMemOp:$src), OpcodeStr,
5597 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5599 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5604 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5605 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5606 EVEX_V512, EVEX_CD8<32, CD8VF>;
5607 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5608 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5610 // Define only if AVX512VL feature is present.
5611 let Predicates = [HasVLX] in {
5612 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5613 OpNode, v4f32x_info>,
5614 EVEX_V128, EVEX_CD8<32, CD8VF>;
5615 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5616 OpNode, v8f32x_info>,
5617 EVEX_V256, EVEX_CD8<32, CD8VF>;
5618 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5619 OpNode, v2f64x_info>,
5620 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5621 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5622 OpNode, v4f64x_info>,
5623 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5627 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5628 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5630 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5631 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5632 (VRSQRT14PSZr VR512:$src)>;
5633 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5634 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5635 (VRSQRT14PDZr VR512:$src)>;
5637 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5638 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5639 (VRCP14PSZr VR512:$src)>;
5640 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5641 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5642 (VRCP14PDZr VR512:$src)>;
5644 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5645 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5648 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5649 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5650 "$src2, $src1", "$src1, $src2",
5651 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5652 (i32 FROUND_CURRENT))>;
5654 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5655 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5656 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5657 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5658 (i32 FROUND_NO_EXC))>, EVEX_B;
5660 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5661 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5662 "$src2, $src1", "$src1, $src2",
5663 (OpNode (_.VT _.RC:$src1),
5664 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5665 (i32 FROUND_CURRENT))>;
5668 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5669 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5670 EVEX_CD8<32, CD8VT1>;
5671 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5672 EVEX_CD8<64, CD8VT1>, VEX_W;
5675 let hasSideEffects = 0, Predicates = [HasERI] in {
5676 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5677 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5680 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5681 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5683 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5686 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5687 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5688 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5690 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5691 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5693 (bitconvert (_.LdFrag addr:$src))),
5694 (i32 FROUND_CURRENT))>;
5696 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5697 (ins _.MemOp:$src), OpcodeStr,
5698 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5700 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5701 (i32 FROUND_CURRENT))>, EVEX_B;
5703 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5705 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5706 (ins _.RC:$src), OpcodeStr,
5707 "{sae}, $src", "$src, {sae}",
5708 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5711 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5712 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5713 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5714 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5715 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5716 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5717 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5720 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5722 // Define only if AVX512VL feature is present.
5723 let Predicates = [HasVLX] in {
5724 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5725 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5726 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5727 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5728 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5729 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5730 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5731 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5734 let Predicates = [HasERI], hasSideEffects = 0 in {
5736 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5737 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5738 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5740 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5741 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5743 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5744 SDNode OpNodeRnd, X86VectorVTInfo _>{
5745 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5746 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5747 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5748 EVEX, EVEX_B, EVEX_RC;
5751 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5752 SDNode OpNode, X86VectorVTInfo _>{
5753 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5754 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5755 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5756 let mayLoad = 1 in {
5757 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5758 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5760 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5762 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5763 (ins _.ScalarMemOp:$src), OpcodeStr,
5764 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5766 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5771 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5773 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5775 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5776 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5778 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5779 // Define only if AVX512VL feature is present.
5780 let Predicates = [HasVLX] in {
5781 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5782 OpNode, v4f32x_info>,
5783 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5784 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5785 OpNode, v8f32x_info>,
5786 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5787 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5788 OpNode, v2f64x_info>,
5789 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5790 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5791 OpNode, v4f64x_info>,
5792 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5796 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5798 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5799 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5800 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5801 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5804 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5805 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5807 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5808 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5809 "$src2, $src1", "$src1, $src2",
5810 (OpNodeRnd (_.VT _.RC:$src1),
5812 (i32 FROUND_CURRENT))>;
5814 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5815 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5816 "$src2, $src1", "$src1, $src2",
5817 (OpNodeRnd (_.VT _.RC:$src1),
5818 (_.VT (scalar_to_vector
5819 (_.ScalarLdFrag addr:$src2))),
5820 (i32 FROUND_CURRENT))>;
5822 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5823 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5824 "$rc, $src2, $src1", "$src1, $src2, $rc",
5825 (OpNodeRnd (_.VT _.RC:$src1),
5830 let isCodeGenOnly = 1 in {
5831 def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst),
5832 (ins _.FRC:$src1, _.FRC:$src2),
5833 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5836 def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst),
5837 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5838 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5841 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5842 (!cast<Instruction>(NAME#SUFF#Zr)
5843 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5845 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5846 (!cast<Instruction>(NAME#SUFF#Zm)
5847 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5850 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5851 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5852 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5853 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5854 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5857 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5858 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5860 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5862 let Predicates = [HasAVX512] in {
5863 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5864 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5865 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5866 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5867 Requires<[OptForSize]>;
5868 def : Pat<(f32 (X86frcp FR32X:$src)),
5869 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5870 def : Pat<(f32 (X86frcp (load addr:$src))),
5871 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5872 Requires<[OptForSize]>;
5876 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5878 let ExeDomain = _.ExeDomain in {
5879 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5880 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5881 "$src3, $src2, $src1", "$src1, $src2, $src3",
5882 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5883 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5885 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5886 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5887 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5888 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5889 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5892 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5893 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5894 "$src3, $src2, $src1", "$src1, $src2, $src3",
5895 (_.VT (X86RndScales (_.VT _.RC:$src1),
5896 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5897 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5899 let Predicates = [HasAVX512] in {
5900 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5901 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5902 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5903 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5904 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5905 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5906 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5907 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5908 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5909 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5910 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5911 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5912 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5913 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5914 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5916 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5917 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5918 addr:$src, (i32 0x1))), _.FRC)>;
5919 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5920 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5921 addr:$src, (i32 0x2))), _.FRC)>;
5922 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5923 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5924 addr:$src, (i32 0x3))), _.FRC)>;
5925 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5926 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5927 addr:$src, (i32 0x4))), _.FRC)>;
5928 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5929 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5930 addr:$src, (i32 0xc))), _.FRC)>;
5934 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5935 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5937 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5938 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5940 //-------------------------------------------------
5941 // Integer truncate and extend operations
5942 //-------------------------------------------------
5944 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5945 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5946 X86MemOperand x86memop> {
5948 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5949 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5950 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5953 // for intrinsic patter match
5954 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5955 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5957 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5960 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5961 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5962 DestInfo.ImmAllZerosV)),
5963 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5966 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5967 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5968 DestInfo.RC:$src0)),
5969 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5970 DestInfo.KRCWM:$mask ,
5973 let mayStore = 1 in {
5974 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5975 (ins x86memop:$dst, SrcInfo.RC:$src),
5976 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5979 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5980 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5981 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5986 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5987 X86VectorVTInfo DestInfo,
5988 PatFrag truncFrag, PatFrag mtruncFrag > {
5990 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5991 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5992 addr:$dst, SrcInfo.RC:$src)>;
5994 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5995 (SrcInfo.VT SrcInfo.RC:$src)),
5996 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5997 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
6000 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
6001 X86VectorVTInfo DestInfo, string sat > {
6003 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6004 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6005 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
6006 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
6007 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
6008 (SrcInfo.VT SrcInfo.RC:$src))>;
6010 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6011 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6012 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
6013 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
6014 (SrcInfo.VT SrcInfo.RC:$src))>;
6017 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
6018 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6019 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6020 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6021 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
6022 Predicate prd = HasAVX512>{
6024 let Predicates = [HasVLX, prd] in {
6025 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6026 DestInfoZ128, x86memopZ128>,
6027 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6028 truncFrag, mtruncFrag>, EVEX_V128;
6030 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6031 DestInfoZ256, x86memopZ256>,
6032 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6033 truncFrag, mtruncFrag>, EVEX_V256;
6035 let Predicates = [prd] in
6036 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6037 DestInfoZ, x86memopZ>,
6038 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6039 truncFrag, mtruncFrag>, EVEX_V512;
6042 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
6043 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6044 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6045 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6046 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
6048 let Predicates = [HasVLX, prd] in {
6049 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6050 DestInfoZ128, x86memopZ128>,
6051 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6054 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6055 DestInfoZ256, x86memopZ256>,
6056 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6059 let Predicates = [prd] in
6060 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6061 DestInfoZ, x86memopZ>,
6062 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6066 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6067 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6068 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6069 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
6071 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
6072 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
6073 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6074 sat>, EVEX_CD8<8, CD8VO>;
6077 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6078 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6079 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6080 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6082 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6083 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6084 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6085 sat>, EVEX_CD8<16, CD8VQ>;
6088 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6089 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6090 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6091 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6093 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6094 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6095 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6096 sat>, EVEX_CD8<32, CD8VH>;
6099 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6100 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6101 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6102 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6104 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6105 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6106 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6107 sat>, EVEX_CD8<8, CD8VQ>;
6110 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6111 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6112 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6113 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6115 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6116 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6117 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6118 sat>, EVEX_CD8<16, CD8VH>;
6121 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6122 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6123 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6124 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6126 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6127 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6128 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6129 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6132 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6133 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6134 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6136 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6137 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6138 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6140 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6141 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6142 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6144 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6145 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6146 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6148 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6149 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6150 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6152 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6153 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6154 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6156 let Predicates = [HasAVX512, NoVLX] in {
6157 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6158 (v8i16 (EXTRACT_SUBREG
6159 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6160 VR256X:$src, sub_ymm)))), sub_xmm))>;
6161 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6162 (v4i32 (EXTRACT_SUBREG
6163 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6164 VR256X:$src, sub_ymm)))), sub_xmm))>;
6167 let Predicates = [HasBWI, NoVLX] in {
6168 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6169 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6170 VR256X:$src, sub_ymm))), sub_xmm))>;
6173 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6174 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6175 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6177 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6178 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6179 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6182 let mayLoad = 1 in {
6183 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6184 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6185 (DestInfo.VT (LdFrag addr:$src))>,
6190 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6191 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6192 let Predicates = [HasVLX, HasBWI] in {
6193 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6194 v16i8x_info, i64mem, LdFrag, OpNode>,
6195 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6197 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6198 v16i8x_info, i128mem, LdFrag, OpNode>,
6199 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6201 let Predicates = [HasBWI] in {
6202 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6203 v32i8x_info, i256mem, LdFrag, OpNode>,
6204 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6208 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6209 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6210 let Predicates = [HasVLX, HasAVX512] in {
6211 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6212 v16i8x_info, i32mem, LdFrag, OpNode>,
6213 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6215 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6216 v16i8x_info, i64mem, LdFrag, OpNode>,
6217 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6219 let Predicates = [HasAVX512] in {
6220 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6221 v16i8x_info, i128mem, LdFrag, OpNode>,
6222 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6226 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6227 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6228 let Predicates = [HasVLX, HasAVX512] in {
6229 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6230 v16i8x_info, i16mem, LdFrag, OpNode>,
6231 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6233 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6234 v16i8x_info, i32mem, LdFrag, OpNode>,
6235 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6237 let Predicates = [HasAVX512] in {
6238 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6239 v16i8x_info, i64mem, LdFrag, OpNode>,
6240 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6244 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6245 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6246 let Predicates = [HasVLX, HasAVX512] in {
6247 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6248 v8i16x_info, i64mem, LdFrag, OpNode>,
6249 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6251 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6252 v8i16x_info, i128mem, LdFrag, OpNode>,
6253 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6255 let Predicates = [HasAVX512] in {
6256 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6257 v16i16x_info, i256mem, LdFrag, OpNode>,
6258 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6262 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6263 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6264 let Predicates = [HasVLX, HasAVX512] in {
6265 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6266 v8i16x_info, i32mem, LdFrag, OpNode>,
6267 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6269 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6270 v8i16x_info, i64mem, LdFrag, OpNode>,
6271 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6273 let Predicates = [HasAVX512] in {
6274 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6275 v8i16x_info, i128mem, LdFrag, OpNode>,
6276 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6280 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6281 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6283 let Predicates = [HasVLX, HasAVX512] in {
6284 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6285 v4i32x_info, i64mem, LdFrag, OpNode>,
6286 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6288 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6289 v4i32x_info, i128mem, LdFrag, OpNode>,
6290 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6292 let Predicates = [HasAVX512] in {
6293 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6294 v8i32x_info, i256mem, LdFrag, OpNode>,
6295 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6299 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6300 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6301 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6302 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6303 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6304 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6307 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6308 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6309 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6310 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6311 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6312 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6314 //===----------------------------------------------------------------------===//
6315 // GATHER - SCATTER Operations
6317 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6318 X86MemOperand memop, PatFrag GatherNode> {
6319 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6320 ExeDomain = _.ExeDomain in
6321 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6322 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6323 !strconcat(OpcodeStr#_.Suffix,
6324 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6325 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6326 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6327 vectoraddr:$src2))]>, EVEX, EVEX_K,
6328 EVEX_CD8<_.EltSize, CD8VT1>;
6331 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6332 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6333 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6334 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6335 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6336 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6337 let Predicates = [HasVLX] in {
6338 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6339 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6340 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6341 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6342 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6343 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6344 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6345 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6349 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6350 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6351 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6352 mgatherv16i32>, EVEX_V512;
6353 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6354 mgatherv8i64>, EVEX_V512;
6355 let Predicates = [HasVLX] in {
6356 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6357 vy32xmem, mgatherv8i32>, EVEX_V256;
6358 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6359 vy64xmem, mgatherv4i64>, EVEX_V256;
6360 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6361 vx32xmem, mgatherv4i32>, EVEX_V128;
6362 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6363 vx64xmem, mgatherv2i64>, EVEX_V128;
6368 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6369 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6371 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6372 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6374 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6375 X86MemOperand memop, PatFrag ScatterNode> {
6377 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6379 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6380 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6381 !strconcat(OpcodeStr#_.Suffix,
6382 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6383 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6384 _.KRCWM:$mask, vectoraddr:$dst))]>,
6385 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6388 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6389 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6390 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6391 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6392 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6393 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6394 let Predicates = [HasVLX] in {
6395 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6396 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6397 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6398 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6399 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6400 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6401 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6402 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6406 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6407 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6408 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6409 mscatterv16i32>, EVEX_V512;
6410 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6411 mscatterv8i64>, EVEX_V512;
6412 let Predicates = [HasVLX] in {
6413 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6414 vy32xmem, mscatterv8i32>, EVEX_V256;
6415 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6416 vy64xmem, mscatterv4i64>, EVEX_V256;
6417 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6418 vx32xmem, mscatterv4i32>, EVEX_V128;
6419 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6420 vx64xmem, mscatterv2i64>, EVEX_V128;
6424 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6425 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6427 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6428 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6431 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6432 RegisterClass KRC, X86MemOperand memop> {
6433 let Predicates = [HasPFI], hasSideEffects = 1 in
6434 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6435 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6439 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6440 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6442 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6443 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6445 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6446 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6448 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6449 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6451 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6452 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6454 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6455 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6457 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6458 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6460 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6461 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6463 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6464 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6466 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6467 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6469 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6470 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6472 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6473 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6475 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6476 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6478 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6479 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6481 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6482 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6484 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6485 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6487 // Helper fragments to match sext vXi1 to vXiY.
6488 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6489 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6491 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6492 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6493 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6495 def : Pat<(store VK1:$src, addr:$dst),
6497 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6498 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6500 def : Pat<(store VK8:$src, addr:$dst),
6502 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6503 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6505 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6506 (truncstore node:$val, node:$ptr), [{
6507 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6510 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6511 (MOV8mr addr:$dst, GR8:$src)>;
6513 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6514 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6515 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6516 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6519 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6520 string OpcodeStr, Predicate prd> {
6521 let Predicates = [prd] in
6522 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6524 let Predicates = [prd, HasVLX] in {
6525 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6526 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6530 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6531 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6533 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6535 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6537 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6541 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6543 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6544 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6545 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6546 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6549 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6550 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6551 let Predicates = [prd] in
6552 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6555 let Predicates = [prd, HasVLX] in {
6556 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6558 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6563 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6564 avx512vl_i8_info, HasBWI>;
6565 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6566 avx512vl_i16_info, HasBWI>, VEX_W;
6567 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6568 avx512vl_i32_info, HasDQI>;
6569 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6570 avx512vl_i64_info, HasDQI>, VEX_W;
6572 //===----------------------------------------------------------------------===//
6573 // AVX-512 - COMPRESS and EXPAND
6576 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6578 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6579 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6580 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6582 let mayStore = 1 in {
6583 def mr : AVX5128I<opc, MRMDestMem, (outs),
6584 (ins _.MemOp:$dst, _.RC:$src),
6585 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6586 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6588 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6589 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6590 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6591 [(store (_.VT (vselect _.KRCWM:$mask,
6592 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6594 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6598 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6599 AVX512VLVectorVTInfo VTInfo> {
6600 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6602 let Predicates = [HasVLX] in {
6603 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6604 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6608 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6610 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6612 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6614 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6618 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6620 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6621 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6622 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6625 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6626 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6627 (_.VT (X86expand (_.VT (bitconvert
6628 (_.LdFrag addr:$src1)))))>,
6629 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6632 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6633 AVX512VLVectorVTInfo VTInfo> {
6634 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6636 let Predicates = [HasVLX] in {
6637 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6638 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6642 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6644 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6646 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6648 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6651 //handle instruction reg_vec1 = op(reg_vec,imm)
6653 // op(broadcast(eltVt),imm)
6654 //all instruction created with FROUND_CURRENT
6655 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6657 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6658 (ins _.RC:$src1, i32u8imm:$src2),
6659 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6660 (OpNode (_.VT _.RC:$src1),
6662 (i32 FROUND_CURRENT))>;
6663 let mayLoad = 1 in {
6664 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6665 (ins _.MemOp:$src1, i32u8imm:$src2),
6666 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6667 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6669 (i32 FROUND_CURRENT))>;
6670 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6671 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6672 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6673 "${src1}"##_.BroadcastStr##", $src2",
6674 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6676 (i32 FROUND_CURRENT))>, EVEX_B;
6680 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6681 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6682 SDNode OpNode, X86VectorVTInfo _>{
6683 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6684 (ins _.RC:$src1, i32u8imm:$src2),
6685 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6686 "$src1, {sae}, $src2",
6687 (OpNode (_.VT _.RC:$src1),
6689 (i32 FROUND_NO_EXC))>, EVEX_B;
6692 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6693 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6694 let Predicates = [prd] in {
6695 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6696 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6699 let Predicates = [prd, HasVLX] in {
6700 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6702 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6707 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6708 // op(reg_vec2,mem_vec,imm)
6709 // op(reg_vec2,broadcast(eltVt),imm)
6710 //all instruction created with FROUND_CURRENT
6711 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6713 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6714 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6715 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6716 (OpNode (_.VT _.RC:$src1),
6719 (i32 FROUND_CURRENT))>;
6720 let mayLoad = 1 in {
6721 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6722 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6723 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6724 (OpNode (_.VT _.RC:$src1),
6725 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6727 (i32 FROUND_CURRENT))>;
6728 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6729 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6730 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6731 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6732 (OpNode (_.VT _.RC:$src1),
6733 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6735 (i32 FROUND_CURRENT))>, EVEX_B;
6739 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6740 // op(reg_vec2,mem_vec,imm)
6741 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6742 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6744 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6745 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6746 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6747 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6748 (SrcInfo.VT SrcInfo.RC:$src2),
6751 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6752 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6753 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6754 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6755 (SrcInfo.VT (bitconvert
6756 (SrcInfo.LdFrag addr:$src2))),
6760 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6761 // op(reg_vec2,mem_vec,imm)
6762 // op(reg_vec2,broadcast(eltVt),imm)
6763 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6765 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6768 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6769 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6770 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6771 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6772 (OpNode (_.VT _.RC:$src1),
6773 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6774 (i8 imm:$src3))>, EVEX_B;
6777 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6778 // op(reg_vec2,mem_scalar,imm)
6779 //all instruction created with FROUND_CURRENT
6780 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6781 X86VectorVTInfo _> {
6783 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6784 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6785 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6786 (OpNode (_.VT _.RC:$src1),
6789 (i32 FROUND_CURRENT))>;
6790 let mayLoad = 1 in {
6791 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6792 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6793 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6794 (OpNode (_.VT _.RC:$src1),
6795 (_.VT (scalar_to_vector
6796 (_.ScalarLdFrag addr:$src2))),
6798 (i32 FROUND_CURRENT))>;
6800 let isAsmParserOnly = 1 in {
6801 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6802 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6803 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6809 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6810 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6811 SDNode OpNode, X86VectorVTInfo _>{
6812 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6813 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6814 OpcodeStr, "$src3,{sae}, $src2, $src1",
6815 "$src1, $src2,{sae}, $src3",
6816 (OpNode (_.VT _.RC:$src1),
6819 (i32 FROUND_NO_EXC))>, EVEX_B;
6821 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6822 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6823 SDNode OpNode, X86VectorVTInfo _> {
6824 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6825 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6826 OpcodeStr, "$src3,{sae}, $src2, $src1",
6827 "$src1, $src2,{sae}, $src3",
6828 (OpNode (_.VT _.RC:$src1),
6831 (i32 FROUND_NO_EXC))>, EVEX_B;
6834 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6835 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6836 let Predicates = [prd] in {
6837 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6838 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6842 let Predicates = [prd, HasVLX] in {
6843 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6845 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6850 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6851 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6852 let Predicates = [HasBWI] in {
6853 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6854 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6856 let Predicates = [HasBWI, HasVLX] in {
6857 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6858 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6859 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6860 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6864 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6865 bits<8> opc, SDNode OpNode>{
6866 let Predicates = [HasAVX512] in {
6867 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6869 let Predicates = [HasAVX512, HasVLX] in {
6870 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6871 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6875 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6876 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6877 let Predicates = [prd] in {
6878 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6879 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6883 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6884 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6885 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6886 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6887 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6888 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6891 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6892 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6893 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6894 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6895 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6896 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6898 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6899 0x55, X86VFixupimm, HasAVX512>,
6900 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6901 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6902 0x55, X86VFixupimm, HasAVX512>,
6903 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6905 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6906 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6907 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6908 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6909 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6910 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6913 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6914 0x50, X86VRange, HasDQI>,
6915 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6916 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6917 0x50, X86VRange, HasDQI>,
6918 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6920 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6921 0x51, X86VRange, HasDQI>,
6922 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6923 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6924 0x51, X86VRange, HasDQI>,
6925 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6927 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6928 0x57, X86Reduces, HasDQI>,
6929 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6930 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6931 0x57, X86Reduces, HasDQI>,
6932 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6934 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
6935 0x27, X86GetMants, HasAVX512>,
6936 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6937 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
6938 0x27, X86GetMants, HasAVX512>,
6939 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6941 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6942 bits<8> opc, SDNode OpNode = X86Shuf128>{
6943 let Predicates = [HasAVX512] in {
6944 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6947 let Predicates = [HasAVX512, HasVLX] in {
6948 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6951 let Predicates = [HasAVX512] in {
6952 def : Pat<(v16f32 (ffloor VR512:$src)),
6953 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6954 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6955 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6956 def : Pat<(v16f32 (fceil VR512:$src)),
6957 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6958 def : Pat<(v16f32 (frint VR512:$src)),
6959 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6960 def : Pat<(v16f32 (ftrunc VR512:$src)),
6961 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6963 def : Pat<(v8f64 (ffloor VR512:$src)),
6964 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6965 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6966 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6967 def : Pat<(v8f64 (fceil VR512:$src)),
6968 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6969 def : Pat<(v8f64 (frint VR512:$src)),
6970 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6971 def : Pat<(v8f64 (ftrunc VR512:$src)),
6972 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6975 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6976 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6977 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6978 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6979 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6980 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6981 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6982 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6984 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6985 AVX512VLVectorVTInfo VTInfo_FP>{
6986 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6987 AVX512AIi8Base, EVEX_4V;
6988 let isCodeGenOnly = 1 in {
6989 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6990 AVX512AIi8Base, EVEX_4V;
6994 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6995 EVEX_CD8<32, CD8VF>;
6996 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6997 EVEX_CD8<64, CD8VF>, VEX_W;
6999 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
7000 let Predicates = p in
7001 def NAME#_.VTName#rri:
7002 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
7003 (!cast<Instruction>(NAME#_.ZSuffix#rri)
7004 _.RC:$src1, _.RC:$src2, imm:$imm)>;
7007 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
7008 avx512_vpalign_lowering<_.info512, [HasBWI]>,
7009 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
7010 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
7012 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
7013 avx512vl_i8_info, avx512vl_i8_info>,
7014 avx512_vpalign_lowering_common<avx512vl_i16_info>,
7015 avx512_vpalign_lowering_common<avx512vl_i32_info>,
7016 avx512_vpalign_lowering_common<avx512vl_f32_info>,
7017 avx512_vpalign_lowering_common<avx512vl_i64_info>,
7018 avx512_vpalign_lowering_common<avx512vl_f64_info>,
7021 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
7022 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
7024 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7025 X86VectorVTInfo _> {
7026 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7027 (ins _.RC:$src1), OpcodeStr,
7029 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
7032 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7033 (ins _.MemOp:$src1), OpcodeStr,
7035 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
7036 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
7039 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7040 X86VectorVTInfo _> :
7041 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
7043 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7044 (ins _.ScalarMemOp:$src1), OpcodeStr,
7045 "${src1}"##_.BroadcastStr,
7046 "${src1}"##_.BroadcastStr,
7047 (_.VT (OpNode (X86VBroadcast
7048 (_.ScalarLdFrag addr:$src1))))>,
7049 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
7052 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7053 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7054 let Predicates = [prd] in
7055 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7057 let Predicates = [prd, HasVLX] in {
7058 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7060 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
7065 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7066 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7067 let Predicates = [prd] in
7068 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
7071 let Predicates = [prd, HasVLX] in {
7072 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
7074 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7079 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7080 SDNode OpNode, Predicate prd> {
7081 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
7083 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
7087 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7088 SDNode OpNode, Predicate prd> {
7089 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
7090 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
7093 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7094 bits<8> opc_d, bits<8> opc_q,
7095 string OpcodeStr, SDNode OpNode> {
7096 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7098 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7102 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7105 (bc_v16i32 (v16i1sextv16i32)),
7106 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7107 (VPABSDZrr VR512:$src)>;
7109 (bc_v8i64 (v8i1sextv8i64)),
7110 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7111 (VPABSQZrr VR512:$src)>;
7113 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7115 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7116 let isCodeGenOnly = 1 in
7117 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
7118 ctlz_zero_undef, prd>;
7121 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7122 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7124 //===---------------------------------------------------------------------===//
7125 // Replicate Single FP - MOVSHDUP and MOVSLDUP
7126 //===---------------------------------------------------------------------===//
7127 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7128 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
7130 let isCodeGenOnly = 1 in
7131 defm NAME#_I: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
7135 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
7136 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
7137 //===----------------------------------------------------------------------===//
7138 // AVX-512 - Unpack Instructions
7139 //===----------------------------------------------------------------------===//
7140 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
7141 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
7143 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7144 SSE_INTALU_ITINS_P, HasBWI>;
7145 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7146 SSE_INTALU_ITINS_P, HasBWI>;
7147 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7148 SSE_INTALU_ITINS_P, HasBWI>;
7149 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7150 SSE_INTALU_ITINS_P, HasBWI>;
7152 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7153 SSE_INTALU_ITINS_P, HasAVX512>;
7154 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7155 SSE_INTALU_ITINS_P, HasAVX512>;
7156 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7157 SSE_INTALU_ITINS_P, HasAVX512>;
7158 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7159 SSE_INTALU_ITINS_P, HasAVX512>;
7161 //===----------------------------------------------------------------------===//
7162 // AVX-512 - Extract & Insert Integer Instructions
7163 //===----------------------------------------------------------------------===//
7165 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7166 X86VectorVTInfo _> {
7168 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7169 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7170 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7171 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7174 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7177 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7178 let Predicates = [HasBWI] in {
7179 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7180 (ins _.RC:$src1, u8imm:$src2),
7181 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7182 [(set GR32orGR64:$dst,
7183 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7186 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7190 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7191 let Predicates = [HasBWI] in {
7192 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7193 (ins _.RC:$src1, u8imm:$src2),
7194 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7195 [(set GR32orGR64:$dst,
7196 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7199 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
7200 (ins _.RC:$src1, u8imm:$src2),
7201 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7204 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7208 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7209 RegisterClass GRC> {
7210 let Predicates = [HasDQI] in {
7211 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7212 (ins _.RC:$src1, u8imm:$src2),
7213 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7215 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7219 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7220 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7221 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7222 [(store (extractelt (_.VT _.RC:$src1),
7223 imm:$src2),addr:$dst)]>,
7224 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7228 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7229 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7230 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7231 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7233 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7234 X86VectorVTInfo _, PatFrag LdFrag> {
7235 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7236 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7237 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7239 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7240 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7243 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7244 X86VectorVTInfo _, PatFrag LdFrag> {
7245 let Predicates = [HasBWI] in {
7246 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7247 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7248 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7250 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7252 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7256 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7257 X86VectorVTInfo _, RegisterClass GRC> {
7258 let Predicates = [HasDQI] in {
7259 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7260 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7261 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7263 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7266 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7267 _.ScalarLdFrag>, TAPD;
7271 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7273 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7275 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7276 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7277 //===----------------------------------------------------------------------===//
7278 // VSHUFPS - VSHUFPD Operations
7279 //===----------------------------------------------------------------------===//
7280 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7281 AVX512VLVectorVTInfo VTInfo_FP>{
7282 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7283 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7284 AVX512AIi8Base, EVEX_4V;
7285 let isCodeGenOnly = 1 in {
7286 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
7287 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
7288 AVX512AIi8Base, EVEX_4V;
7292 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7293 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7294 //===----------------------------------------------------------------------===//
7295 // AVX-512 - Byte shift Left/Right
7296 //===----------------------------------------------------------------------===//
7298 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7299 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7300 def rr : AVX512<opc, MRMr,
7301 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7303 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7305 def rm : AVX512<opc, MRMm,
7306 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7307 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7308 [(set _.RC:$dst,(_.VT (OpNode
7309 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7312 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7313 Format MRMm, string OpcodeStr, Predicate prd>{
7314 let Predicates = [prd] in
7315 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7316 OpcodeStr, v8i64_info>, EVEX_V512;
7317 let Predicates = [prd, HasVLX] in {
7318 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7319 OpcodeStr, v4i64x_info>, EVEX_V256;
7320 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7321 OpcodeStr, v2i64x_info>, EVEX_V128;
7324 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7325 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7326 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7327 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7330 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7331 string OpcodeStr, X86VectorVTInfo _src>{
7332 def rr : AVX512BI<opc, MRMSrcReg,
7333 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7334 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7335 [(set _src.RC:$dst,(_src.VT
7336 (OpNode _src.RC:$src1, _src.RC:$src2)))]>;
7338 def rm : AVX512BI<opc, MRMSrcMem,
7339 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7340 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7341 [(set _src.RC:$dst,(_src.VT
7342 (OpNode _src.RC:$src1,
7343 (_src.VT (bitconvert
7344 (_src.LdFrag addr:$src2))))))]>;
7347 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7348 string OpcodeStr, Predicate prd> {
7349 let Predicates = [prd] in
7350 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v64i8_info>,
7352 let Predicates = [prd, HasVLX] in {
7353 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v32i8x_info>,
7355 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v16i8x_info>,
7360 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7363 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7365 let Constraints = "$src1 = $dst" in {
7366 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7367 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7368 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7369 (OpNode (_.VT _.RC:$src1),
7372 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7373 let mayLoad = 1 in {
7374 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7375 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7376 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7377 (OpNode (_.VT _.RC:$src1),
7379 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7381 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7382 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7383 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7384 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7385 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7386 (OpNode (_.VT _.RC:$src1),
7388 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7389 (i8 imm:$src4))>, EVEX_B,
7390 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7392 }// Constraints = "$src1 = $dst"
7395 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7396 let Predicates = [HasAVX512] in
7397 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7398 let Predicates = [HasAVX512, HasVLX] in {
7399 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7400 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7404 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7405 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;