1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
9 ValueType EltVT = eltvt;
10 int NumElts = numelts;
12 // Corresponding mask register class.
13 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
15 // Corresponding write-mask register class.
16 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
18 // The GPR register class that can hold the write mask. Use GR8 for fewer
19 // than 8 elements. Use shift-right and equal to work around the lack of
22 !cast<RegisterClass>("GR" #
23 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
25 // Suffix used in the instruction mnemonic.
26 string Suffix = suffix;
28 // VTName is a string name for vector VT. For vector types it will be
29 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
30 // It is a little bit complex for scalar types, where NumElts = 1.
31 // In this case we build v4f32 or v2f64
32 string VTName = "v" # !if (!eq (NumElts, 1),
33 !if (!eq (EltVT.Size, 32), 4,
34 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
37 ValueType VT = !cast<ValueType>(VTName);
39 string EltTypeName = !cast<string>(EltVT);
40 // Size of the element type in bits, e.g. 32 for v16i32.
41 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
42 int EltSize = EltVT.Size;
44 // "i" for integer types and "f" for floating-point types
45 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
47 // Size of RC in bits, e.g. 512 for VR512.
50 // The corresponding memory operand, e.g. i512mem for VR512.
51 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
52 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
55 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
56 // due to load promotion during legalization
57 PatFrag LdFrag = !cast<PatFrag>("load" #
58 !if (!eq (TypeVariantName, "i"),
59 !if (!eq (Size, 128), "v2i64",
60 !if (!eq (Size, 256), "v4i64",
62 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
64 // The corresponding float type, e.g. v16f32 for v16i32
65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
89 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
91 // A vector type of the same width with element type i32. This is used to
92 // create the canonical constant zero node ImmAllZerosV.
93 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
94 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
97 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
98 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
99 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
100 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
101 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
102 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
104 // "x" in v32i8x_info means RC = VR256X
105 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
106 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
107 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
108 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
109 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
110 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
112 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
113 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
114 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
115 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
116 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
117 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
119 // We map scalar types to the smallest (128-bit) vector type
120 // with the appropriate element type. This allows to use the same masking logic.
121 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
122 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
124 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
125 X86VectorVTInfo i128> {
126 X86VectorVTInfo info512 = i512;
127 X86VectorVTInfo info256 = i256;
128 X86VectorVTInfo info128 = i128;
131 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
133 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
135 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
137 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
139 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
141 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
144 // This multiclass generates the masking variants from the non-masking
145 // variant. It only provides the assembly pieces for the masking variants.
146 // It assumes custom ISel patterns for masking which can be provided as
147 // template arguments.
148 multiclass AVX512_maskable_custom<bits<8> O, Format F,
150 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
152 string AttSrcAsm, string IntelSrcAsm,
154 list<dag> MaskingPattern,
155 list<dag> ZeroMaskingPattern,
157 string MaskingConstraint = "",
158 InstrItinClass itin = NoItinerary,
159 bit IsCommutable = 0> {
160 let isCommutable = IsCommutable in
161 def NAME: AVX512<O, F, Outs, Ins,
162 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
163 "$dst "#Round#", "#IntelSrcAsm#"}",
166 // Prefer over VMOV*rrk Pat<>
167 let AddedComplexity = 20 in
168 def NAME#k: AVX512<O, F, Outs, MaskingIns,
169 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
170 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
171 MaskingPattern, itin>,
173 // In case of the 3src subclass this is overridden with a let.
174 string Constraints = MaskingConstraint;
176 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
177 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
178 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
179 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
186 // Common base class of AVX512_maskable and AVX512_maskable_3src.
187 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
189 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
191 string AttSrcAsm, string IntelSrcAsm,
192 dag RHS, dag MaskingRHS,
193 SDNode Select = vselect, string Round = "",
194 string MaskingConstraint = "",
195 InstrItinClass itin = NoItinerary,
196 bit IsCommutable = 0> :
197 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
198 AttSrcAsm, IntelSrcAsm,
199 [(set _.RC:$dst, RHS)],
200 [(set _.RC:$dst, MaskingRHS)],
202 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
203 Round, MaskingConstraint, NoItinerary, IsCommutable>;
205 // This multiclass generates the unconditional/non-masking, the masking and
206 // the zero-masking variant of the vector instruction. In the masking case, the
207 // perserved vector elements come from a new dummy input operand tied to $dst.
208 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
209 dag Outs, dag Ins, string OpcodeStr,
210 string AttSrcAsm, string IntelSrcAsm,
211 dag RHS, string Round = "",
212 InstrItinClass itin = NoItinerary,
213 bit IsCommutable = 0> :
214 AVX512_maskable_common<O, F, _, Outs, Ins,
215 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
216 !con((ins _.KRCWM:$mask), Ins),
217 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
218 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
219 Round, "$src0 = $dst", itin, IsCommutable>;
221 // This multiclass generates the unconditional/non-masking, the masking and
222 // the zero-masking variant of the scalar instruction.
223 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
224 dag Outs, dag Ins, string OpcodeStr,
225 string AttSrcAsm, string IntelSrcAsm,
226 dag RHS, string Round = "",
227 InstrItinClass itin = NoItinerary,
228 bit IsCommutable = 0> :
229 AVX512_maskable_common<O, F, _, Outs, Ins,
230 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
231 !con((ins _.KRCWM:$mask), Ins),
232 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
233 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
234 Round, "$src0 = $dst", itin, IsCommutable>;
236 // Similar to AVX512_maskable but in this case one of the source operands
237 // ($src1) is already tied to $dst so we just use that for the preserved
238 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
240 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
241 dag Outs, dag NonTiedIns, string OpcodeStr,
242 string AttSrcAsm, string IntelSrcAsm,
244 AVX512_maskable_common<O, F, _, Outs,
245 !con((ins _.RC:$src1), NonTiedIns),
246 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
247 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
248 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
249 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
252 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
255 string AttSrcAsm, string IntelSrcAsm,
257 AVX512_maskable_custom<O, F, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
263 // Bitcasts between 512-bit vector types. Return the original type since
264 // no instruction is needed for the conversion
265 let Predicates = [HasAVX512] in {
266 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
267 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
268 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
269 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
270 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
271 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
272 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
273 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
274 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
275 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
276 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
277 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
278 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
279 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
280 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
281 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
282 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
283 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
284 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
285 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
286 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
287 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
288 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
289 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
290 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
291 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
292 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
293 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
294 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
295 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
296 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
329 // Bitcasts between 256-bit vector types. Return the original type since
330 // no instruction is needed for the conversion
331 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
332 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
333 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
334 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
335 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
336 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
337 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
338 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
339 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
340 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
341 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
342 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
343 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
344 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
345 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
346 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
347 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
348 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
349 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
350 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
351 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
352 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
353 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
354 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
355 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
356 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
357 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
358 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
359 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
360 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
364 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
368 isPseudo = 1, Predicates = [HasAVX512] in {
369 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
370 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
373 let Predicates = [HasAVX512] in {
374 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
375 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
376 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
379 //===----------------------------------------------------------------------===//
380 // AVX-512 - VECTOR INSERT
383 multiclass vinsert_for_size_no_alt<int Opcode,
384 X86VectorVTInfo From, X86VectorVTInfo To,
385 PatFrag vinsert_insert,
386 SDNodeXForm INSERT_get_vinsert_imm> {
387 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
388 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
389 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
390 "vinsert" # From.EltTypeName # "x" # From.NumElts #
391 "\t{$src3, $src2, $src1, $dst|"
392 "$dst, $src1, $src2, $src3}",
393 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
394 (From.VT From.RC:$src2),
399 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
400 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
401 "vinsert" # From.EltTypeName # "x" # From.NumElts #
402 "\t{$src3, $src2, $src1, $dst|"
403 "$dst, $src1, $src2, $src3}",
405 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
409 multiclass vinsert_for_size<int Opcode,
410 X86VectorVTInfo From, X86VectorVTInfo To,
411 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
412 PatFrag vinsert_insert,
413 SDNodeXForm INSERT_get_vinsert_imm> :
414 vinsert_for_size_no_alt<Opcode, From, To,
415 vinsert_insert, INSERT_get_vinsert_imm> {
416 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
417 // vinserti32x4. Only add this if 64x2 and friends are not supported
418 // natively via AVX512DQ.
419 let Predicates = [NoDQI] in
420 def : Pat<(vinsert_insert:$ins
421 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
422 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
423 VR512:$src1, From.RC:$src2,
424 (INSERT_get_vinsert_imm VR512:$ins)))>;
427 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
428 ValueType EltVT64, int Opcode256> {
429 defm NAME # "32x4" : vinsert_for_size<Opcode128,
430 X86VectorVTInfo< 4, EltVT32, VR128X>,
431 X86VectorVTInfo<16, EltVT32, VR512>,
432 X86VectorVTInfo< 2, EltVT64, VR128X>,
433 X86VectorVTInfo< 8, EltVT64, VR512>,
435 INSERT_get_vinsert128_imm>;
436 let Predicates = [HasDQI] in
437 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
438 X86VectorVTInfo< 2, EltVT64, VR128X>,
439 X86VectorVTInfo< 8, EltVT64, VR512>,
441 INSERT_get_vinsert128_imm>, VEX_W;
442 defm NAME # "64x4" : vinsert_for_size<Opcode256,
443 X86VectorVTInfo< 4, EltVT64, VR256X>,
444 X86VectorVTInfo< 8, EltVT64, VR512>,
445 X86VectorVTInfo< 8, EltVT32, VR256>,
446 X86VectorVTInfo<16, EltVT32, VR512>,
448 INSERT_get_vinsert256_imm>, VEX_W;
449 let Predicates = [HasDQI] in
450 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
451 X86VectorVTInfo< 8, EltVT32, VR256X>,
452 X86VectorVTInfo<16, EltVT32, VR512>,
454 INSERT_get_vinsert256_imm>;
457 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
458 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
460 // vinsertps - insert f32 to XMM
461 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
462 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
463 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
464 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
466 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
467 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
468 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
469 [(set VR128X:$dst, (X86insertps VR128X:$src1,
470 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
471 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
473 //===----------------------------------------------------------------------===//
474 // AVX-512 VECTOR EXTRACT
477 multiclass vextract_for_size<int Opcode,
478 X86VectorVTInfo From, X86VectorVTInfo To,
479 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
480 PatFrag vextract_extract,
481 SDNodeXForm EXTRACT_get_vextract_imm> {
482 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
483 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
484 (ins VR512:$src1, u8imm:$idx),
485 "vextract" # To.EltTypeName # "x4",
486 "$idx, $src1", "$src1, $idx",
487 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
489 AVX512AIi8Base, EVEX, EVEX_V512;
491 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
492 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
493 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
494 "$dst, $src1, $src2}",
495 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
498 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
500 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
501 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
503 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
505 // A 128/256-bit subvector extract from the first 512-bit vector position is
506 // a subregister copy that needs no instruction.
507 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
509 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
511 // And for the alternative types.
512 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
514 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
516 // Intrinsic call with masking.
517 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
519 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
520 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
521 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
522 VR512:$src1, imm:$idx)>;
524 // Intrinsic call with zero-masking.
525 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
527 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
528 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
529 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
530 VR512:$src1, imm:$idx)>;
532 // Intrinsic call without masking.
533 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
535 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
536 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
537 VR512:$src1, imm:$idx)>;
540 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
541 ValueType EltVT64, int Opcode64> {
542 defm NAME # "32x4" : vextract_for_size<Opcode32,
543 X86VectorVTInfo<16, EltVT32, VR512>,
544 X86VectorVTInfo< 4, EltVT32, VR128X>,
545 X86VectorVTInfo< 8, EltVT64, VR512>,
546 X86VectorVTInfo< 2, EltVT64, VR128X>,
548 EXTRACT_get_vextract128_imm>;
549 defm NAME # "64x4" : vextract_for_size<Opcode64,
550 X86VectorVTInfo< 8, EltVT64, VR512>,
551 X86VectorVTInfo< 4, EltVT64, VR256X>,
552 X86VectorVTInfo<16, EltVT32, VR512>,
553 X86VectorVTInfo< 8, EltVT32, VR256>,
555 EXTRACT_get_vextract256_imm>, VEX_W;
558 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
559 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
561 // A 128-bit subvector insert to the first 512-bit vector position
562 // is a subregister copy that needs no instruction.
563 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
564 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
565 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
567 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
568 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
569 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
571 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
572 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
573 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
575 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
576 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
577 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
580 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
581 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
582 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
583 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
584 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
585 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
586 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
587 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
589 // vextractps - extract 32 bits from XMM
590 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
591 (ins VR128X:$src1, u8imm:$src2),
592 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
593 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
596 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
597 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
598 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
599 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
600 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
602 //===---------------------------------------------------------------------===//
605 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
606 ValueType svt, X86VectorVTInfo _> {
607 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
608 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
609 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
613 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
614 (ins _.ScalarMemOp:$src),
615 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
616 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
621 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
622 AVX512VLVectorVTInfo _> {
623 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
626 let Predicates = [HasVLX] in {
627 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
632 let ExeDomain = SSEPackedSingle in {
633 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
634 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
635 let Predicates = [HasVLX] in {
636 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
637 v4f32, v4f32x_info>, EVEX_V128,
638 EVEX_CD8<32, CD8VT1>;
642 let ExeDomain = SSEPackedDouble in {
643 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
644 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
647 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
648 // Later, we can canonize broadcast instructions before ISel phase and
649 // eliminate additional patterns on ISel.
650 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
651 // representations of source
652 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
653 X86VectorVTInfo _, RegisterClass SrcRC_v,
654 RegisterClass SrcRC_s> {
655 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
656 (!cast<Instruction>(InstName##"r")
657 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
659 let AddedComplexity = 30 in {
660 def : Pat<(_.VT (vselect _.KRCWM:$mask,
661 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
662 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
663 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
665 def : Pat<(_.VT(vselect _.KRCWM:$mask,
666 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
667 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
668 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
672 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
674 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
677 let Predicates = [HasVLX] in {
678 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
679 v8f32x_info, VR128X, FR32X>;
680 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
681 v4f32x_info, VR128X, FR32X>;
682 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
683 v4f64x_info, VR128X, FR64X>;
686 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
687 (VBROADCASTSSZm addr:$src)>;
688 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
689 (VBROADCASTSDZm addr:$src)>;
691 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
692 (VBROADCASTSSZm addr:$src)>;
693 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
694 (VBROADCASTSDZm addr:$src)>;
696 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
697 RegisterClass SrcRC> {
698 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
699 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
700 "$src", "$src", []>, T8PD, EVEX;
703 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
704 RegisterClass SrcRC, Predicate prd> {
705 let Predicates = [prd] in
706 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
707 let Predicates = [prd, HasVLX] in {
708 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
709 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
713 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
715 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
717 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
719 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
722 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
723 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
725 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
726 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
728 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
729 (VPBROADCASTDrZr GR32:$src)>;
730 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
731 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
732 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
733 (VPBROADCASTQrZr GR64:$src)>;
734 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
735 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
737 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
738 (VPBROADCASTDrZr GR32:$src)>;
739 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
740 (VPBROADCASTQrZr GR64:$src)>;
742 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
743 (v16i32 immAllZerosV), (i16 GR16:$mask))),
744 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
745 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
746 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
747 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
749 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
750 X86MemOperand x86memop, PatFrag ld_frag,
751 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
753 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
754 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
756 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
757 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
759 !strconcat(OpcodeStr,
760 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
762 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
765 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
766 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
768 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
769 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
771 !strconcat(OpcodeStr,
772 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
773 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
774 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
778 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
779 loadi32, VR512, v16i32, v4i32, VK16WM>,
780 EVEX_V512, EVEX_CD8<32, CD8VT1>;
781 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
782 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
783 EVEX_CD8<64, CD8VT1>;
785 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
786 X86MemOperand x86memop, PatFrag ld_frag,
789 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
790 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
792 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
794 !strconcat(OpcodeStr,
795 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
800 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
801 i128mem, loadv2i64, VK16WM>,
802 EVEX_V512, EVEX_CD8<32, CD8VT4>;
803 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
804 i256mem, loadv4i64, VK16WM>, VEX_W,
805 EVEX_V512, EVEX_CD8<64, CD8VT4>;
807 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
808 (VPBROADCASTDZrr VR128X:$src)>;
809 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
810 (VPBROADCASTQZrr VR128X:$src)>;
812 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
813 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
814 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
815 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
817 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
818 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
819 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
820 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
822 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
823 (VBROADCASTSSZr VR128X:$src)>;
824 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
825 (VBROADCASTSDZr VR128X:$src)>;
827 // Provide fallback in case the load node that is used in the patterns above
828 // is used by additional users, which prevents the pattern selection.
829 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
830 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
831 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
832 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
835 let Predicates = [HasAVX512] in {
836 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
838 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
839 addr:$src)), sub_ymm)>;
841 //===----------------------------------------------------------------------===//
842 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
845 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
847 let Predicates = [HasCDI] in
848 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
849 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
850 []>, EVEX, EVEX_V512;
852 let Predicates = [HasCDI, HasVLX] in {
853 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
854 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
855 []>, EVEX, EVEX_V128;
856 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
858 []>, EVEX, EVEX_V256;
862 let Predicates = [HasCDI] in {
863 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
865 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
869 //===----------------------------------------------------------------------===//
872 // -- immediate form --
873 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
875 let ExeDomain = _.ExeDomain in {
876 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
877 (ins _.RC:$src1, u8imm:$src2),
878 !strconcat(OpcodeStr,
879 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
881 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
883 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
884 (ins _.MemOp:$src1, u8imm:$src2),
885 !strconcat(OpcodeStr,
886 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
888 (_.VT (OpNode (_.LdFrag addr:$src1),
890 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
894 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
895 X86VectorVTInfo Ctrl> :
896 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
897 let ExeDomain = _.ExeDomain in {
898 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
899 (ins _.RC:$src1, _.RC:$src2),
900 !strconcat("vpermil" # _.Suffix,
901 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
903 (_.VT (X86VPermilpv _.RC:$src1,
904 (Ctrl.VT Ctrl.RC:$src2))))]>,
906 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
907 (ins _.RC:$src1, Ctrl.MemOp:$src2),
908 !strconcat("vpermil" # _.Suffix,
909 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
911 (_.VT (X86VPermilpv _.RC:$src1,
912 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
917 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
919 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
922 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
924 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
927 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
928 (VPERMILPSZri VR512:$src1, imm:$imm)>;
929 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
930 (VPERMILPDZri VR512:$src1, imm:$imm)>;
932 // -- VPERM - register form --
933 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
934 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
936 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
937 (ins RC:$src1, RC:$src2),
938 !strconcat(OpcodeStr,
939 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
941 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
943 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
944 (ins RC:$src1, x86memop:$src2),
945 !strconcat(OpcodeStr,
946 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
948 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
952 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, loadv16i32, i512mem,
953 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
954 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, loadv8i64, i512mem,
955 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
956 let ExeDomain = SSEPackedSingle in
957 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, loadv16f32, f512mem,
958 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
959 let ExeDomain = SSEPackedDouble in
960 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, loadv8f64, f512mem,
961 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
963 // -- VPERM2I - 3 source operands form --
964 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
965 PatFrag mem_frag, X86MemOperand x86memop,
966 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
967 let Constraints = "$src1 = $dst" in {
968 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
969 (ins RC:$src1, RC:$src2, RC:$src3),
970 !strconcat(OpcodeStr,
971 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
973 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
976 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
977 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
978 !strconcat(OpcodeStr,
979 "\t{$src3, $src2, $dst {${mask}}|"
980 "$dst {${mask}}, $src2, $src3}"),
981 [(set RC:$dst, (OpVT (vselect KRC:$mask,
982 (OpNode RC:$src1, RC:$src2,
987 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
988 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
989 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
990 !strconcat(OpcodeStr,
991 "\t{$src3, $src2, $dst {${mask}} {z} |",
992 "$dst {${mask}} {z}, $src2, $src3}"),
993 [(set RC:$dst, (OpVT (vselect KRC:$mask,
994 (OpNode RC:$src1, RC:$src2,
997 (v16i32 immAllZerosV))))))]>,
1000 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1001 (ins RC:$src1, RC:$src2, x86memop:$src3),
1002 !strconcat(OpcodeStr,
1003 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1005 (OpVT (OpNode RC:$src1, RC:$src2,
1006 (mem_frag addr:$src3))))]>, EVEX_4V;
1008 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1009 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1010 !strconcat(OpcodeStr,
1011 "\t{$src3, $src2, $dst {${mask}}|"
1012 "$dst {${mask}}, $src2, $src3}"),
1014 (OpVT (vselect KRC:$mask,
1015 (OpNode RC:$src1, RC:$src2,
1016 (mem_frag addr:$src3)),
1020 let AddedComplexity = 10 in // Prefer over the rrkz variant
1021 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1022 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1023 !strconcat(OpcodeStr,
1024 "\t{$src3, $src2, $dst {${mask}} {z}|"
1025 "$dst {${mask}} {z}, $src2, $src3}"),
1027 (OpVT (vselect KRC:$mask,
1028 (OpNode RC:$src1, RC:$src2,
1029 (mem_frag addr:$src3)),
1031 (v16i32 immAllZerosV))))))]>,
1035 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
1036 i512mem, X86VPermiv3, v16i32, VK16WM>,
1037 EVEX_V512, EVEX_CD8<32, CD8VF>;
1038 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
1039 i512mem, X86VPermiv3, v8i64, VK8WM>,
1040 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1041 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
1042 i512mem, X86VPermiv3, v16f32, VK16WM>,
1043 EVEX_V512, EVEX_CD8<32, CD8VF>;
1044 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
1045 i512mem, X86VPermiv3, v8f64, VK8WM>,
1046 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1048 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1049 PatFrag mem_frag, X86MemOperand x86memop,
1050 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1051 ValueType MaskVT, RegisterClass MRC> :
1052 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1054 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1055 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1056 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1058 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1059 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1060 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1061 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1064 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
1065 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1066 EVEX_V512, EVEX_CD8<32, CD8VF>;
1067 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
1068 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1069 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1070 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
1071 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1072 EVEX_V512, EVEX_CD8<32, CD8VF>;
1073 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
1074 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1075 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1077 //===----------------------------------------------------------------------===//
1078 // AVX-512 - BLEND using mask
1080 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1081 let ExeDomain = _.ExeDomain in {
1082 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1083 (ins _.RC:$src1, _.RC:$src2),
1084 !strconcat(OpcodeStr,
1085 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1087 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1088 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1089 !strconcat(OpcodeStr,
1090 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1091 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1092 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1093 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1094 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1095 !strconcat(OpcodeStr,
1096 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1097 []>, EVEX_4V, EVEX_KZ;
1098 let mayLoad = 1 in {
1099 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1100 (ins _.RC:$src1, _.MemOp:$src2),
1101 !strconcat(OpcodeStr,
1102 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1103 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1104 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1105 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1106 !strconcat(OpcodeStr,
1107 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1108 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1109 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1110 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1111 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1112 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1113 !strconcat(OpcodeStr,
1114 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1115 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1119 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1121 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1122 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1123 !strconcat(OpcodeStr,
1124 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1125 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1126 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1127 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1128 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1130 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1131 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1132 !strconcat(OpcodeStr,
1133 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1134 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1135 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1139 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1140 AVX512VLVectorVTInfo VTInfo> {
1141 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1142 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1144 let Predicates = [HasVLX] in {
1145 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1146 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1147 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1148 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1152 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1153 AVX512VLVectorVTInfo VTInfo> {
1154 let Predicates = [HasBWI] in
1155 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1157 let Predicates = [HasBWI, HasVLX] in {
1158 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1159 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1164 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1165 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1166 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1167 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1168 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1169 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1172 let Predicates = [HasAVX512] in {
1173 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1174 (v8f32 VR256X:$src2))),
1176 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1177 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1178 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1180 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1181 (v8i32 VR256X:$src2))),
1183 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1184 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1185 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1187 //===----------------------------------------------------------------------===//
1188 // Compare Instructions
1189 //===----------------------------------------------------------------------===//
1191 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1192 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1193 SDNode OpNode, ValueType VT,
1194 PatFrag ld_frag, string Suffix> {
1195 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1196 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1197 !strconcat("vcmp${cc}", Suffix,
1198 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1199 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1200 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1201 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1202 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1203 !strconcat("vcmp${cc}", Suffix,
1204 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1205 [(set VK1:$dst, (OpNode (VT RC:$src1),
1206 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1207 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1208 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1209 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1210 !strconcat("vcmp", Suffix,
1211 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1212 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1214 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1215 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1216 !strconcat("vcmp", Suffix,
1217 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1218 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1222 let Predicates = [HasAVX512] in {
1223 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1225 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1229 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1230 X86VectorVTInfo _> {
1231 def rr : AVX512BI<opc, MRMSrcReg,
1232 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1233 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1234 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1235 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1237 def rm : AVX512BI<opc, MRMSrcMem,
1238 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1239 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1240 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1241 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1242 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1243 def rrk : AVX512BI<opc, MRMSrcReg,
1244 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1245 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1246 "$dst {${mask}}, $src1, $src2}"),
1247 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1248 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1249 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1251 def rmk : AVX512BI<opc, MRMSrcMem,
1252 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1253 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1254 "$dst {${mask}}, $src1, $src2}"),
1255 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1256 (OpNode (_.VT _.RC:$src1),
1258 (_.LdFrag addr:$src2))))))],
1259 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1262 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1263 X86VectorVTInfo _> :
1264 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1265 let mayLoad = 1 in {
1266 def rmb : AVX512BI<opc, MRMSrcMem,
1267 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1268 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1269 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1270 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1271 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1272 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1273 def rmbk : AVX512BI<opc, MRMSrcMem,
1274 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1275 _.ScalarMemOp:$src2),
1276 !strconcat(OpcodeStr,
1277 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1278 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1279 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1280 (OpNode (_.VT _.RC:$src1),
1282 (_.ScalarLdFrag addr:$src2)))))],
1283 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1287 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1288 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1289 let Predicates = [prd] in
1290 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1293 let Predicates = [prd, HasVLX] in {
1294 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1296 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1301 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1302 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1304 let Predicates = [prd] in
1305 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1308 let Predicates = [prd, HasVLX] in {
1309 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1311 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1316 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1317 avx512vl_i8_info, HasBWI>,
1320 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1321 avx512vl_i16_info, HasBWI>,
1322 EVEX_CD8<16, CD8VF>;
1324 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1325 avx512vl_i32_info, HasAVX512>,
1326 EVEX_CD8<32, CD8VF>;
1328 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1329 avx512vl_i64_info, HasAVX512>,
1330 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1332 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1333 avx512vl_i8_info, HasBWI>,
1336 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1337 avx512vl_i16_info, HasBWI>,
1338 EVEX_CD8<16, CD8VF>;
1340 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1341 avx512vl_i32_info, HasAVX512>,
1342 EVEX_CD8<32, CD8VF>;
1344 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1345 avx512vl_i64_info, HasAVX512>,
1346 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1348 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1349 (COPY_TO_REGCLASS (VPCMPGTDZrr
1350 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1351 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1353 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1354 (COPY_TO_REGCLASS (VPCMPEQDZrr
1355 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1356 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1358 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1359 X86VectorVTInfo _> {
1360 def rri : AVX512AIi8<opc, MRMSrcReg,
1361 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1362 !strconcat("vpcmp${cc}", Suffix,
1363 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1364 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1366 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1368 def rmi : AVX512AIi8<opc, MRMSrcMem,
1369 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1370 !strconcat("vpcmp${cc}", Suffix,
1371 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1372 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1373 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1375 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1376 def rrik : AVX512AIi8<opc, MRMSrcReg,
1377 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1379 !strconcat("vpcmp${cc}", Suffix,
1380 "\t{$src2, $src1, $dst {${mask}}|",
1381 "$dst {${mask}}, $src1, $src2}"),
1382 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1383 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1385 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1387 def rmik : AVX512AIi8<opc, MRMSrcMem,
1388 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1390 !strconcat("vpcmp${cc}", Suffix,
1391 "\t{$src2, $src1, $dst {${mask}}|",
1392 "$dst {${mask}}, $src1, $src2}"),
1393 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1394 (OpNode (_.VT _.RC:$src1),
1395 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1397 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1399 // Accept explicit immediate argument form instead of comparison code.
1400 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1401 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1402 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1403 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1404 "$dst, $src1, $src2, $cc}"),
1405 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1407 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1408 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1409 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1410 "$dst, $src1, $src2, $cc}"),
1411 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1412 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1413 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1415 !strconcat("vpcmp", Suffix,
1416 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1417 "$dst {${mask}}, $src1, $src2, $cc}"),
1418 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1420 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1421 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1423 !strconcat("vpcmp", Suffix,
1424 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1425 "$dst {${mask}}, $src1, $src2, $cc}"),
1426 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1430 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1431 X86VectorVTInfo _> :
1432 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1433 def rmib : AVX512AIi8<opc, MRMSrcMem,
1434 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1436 !strconcat("vpcmp${cc}", Suffix,
1437 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1438 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1439 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1440 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1442 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1443 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1444 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1445 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1446 !strconcat("vpcmp${cc}", Suffix,
1447 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1448 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1449 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1450 (OpNode (_.VT _.RC:$src1),
1451 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1453 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1455 // Accept explicit immediate argument form instead of comparison code.
1456 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1457 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1458 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1460 !strconcat("vpcmp", Suffix,
1461 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1462 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1463 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1464 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1465 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1466 _.ScalarMemOp:$src2, u8imm:$cc),
1467 !strconcat("vpcmp", Suffix,
1468 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1469 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1470 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1474 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1475 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1476 let Predicates = [prd] in
1477 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1479 let Predicates = [prd, HasVLX] in {
1480 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1481 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1485 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1486 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1487 let Predicates = [prd] in
1488 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1491 let Predicates = [prd, HasVLX] in {
1492 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1494 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1499 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1500 HasBWI>, EVEX_CD8<8, CD8VF>;
1501 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1502 HasBWI>, EVEX_CD8<8, CD8VF>;
1504 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1505 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1506 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1507 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1509 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1510 HasAVX512>, EVEX_CD8<32, CD8VF>;
1511 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1512 HasAVX512>, EVEX_CD8<32, CD8VF>;
1514 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1515 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1516 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1517 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1519 // avx512_cmp_packed - compare packed instructions
1520 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1521 X86MemOperand x86memop, ValueType vt,
1522 string suffix, Domain d> {
1523 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1524 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1525 !strconcat("vcmp${cc}", suffix,
1526 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1527 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1528 let hasSideEffects = 0 in
1529 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1530 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1531 !strconcat("vcmp${cc}", suffix,
1532 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1534 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1535 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1536 !strconcat("vcmp${cc}", suffix,
1537 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1539 (X86cmpm (vt RC:$src1), (load addr:$src2), imm:$cc))], d>;
1541 // Accept explicit immediate argument form instead of comparison code.
1542 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1543 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1544 (outs KRC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1545 !strconcat("vcmp", suffix,
1546 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1548 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1549 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1550 !strconcat("vcmp", suffix,
1551 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1555 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1556 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1557 EVEX_CD8<32, CD8VF>;
1558 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1559 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1560 EVEX_CD8<64, CD8VF>;
1562 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1563 (COPY_TO_REGCLASS (VCMPPSZrri
1564 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1565 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1567 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1568 (COPY_TO_REGCLASS (VPCMPDZrri
1569 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1570 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1572 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1573 (COPY_TO_REGCLASS (VPCMPUDZrri
1574 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1575 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1578 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1579 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1581 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1582 (I8Imm imm:$cc)), GR16)>;
1584 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1585 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1587 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1588 (I8Imm imm:$cc)), GR8)>;
1590 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1591 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1593 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1594 (I8Imm imm:$cc)), GR16)>;
1596 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1597 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1599 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1600 (I8Imm imm:$cc)), GR8)>;
1602 // Mask register copy, including
1603 // - copy between mask registers
1604 // - load/store mask registers
1605 // - copy from GPR to mask register and vice versa
1607 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1608 string OpcodeStr, RegisterClass KRC,
1609 ValueType vvt, X86MemOperand x86memop> {
1610 let hasSideEffects = 0 in {
1611 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1612 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1614 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1615 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1616 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1618 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1619 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1620 [(store KRC:$src, addr:$dst)]>;
1624 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1626 RegisterClass KRC, RegisterClass GRC> {
1627 let hasSideEffects = 0 in {
1628 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1629 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1630 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1631 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1635 let Predicates = [HasDQI] in
1636 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1637 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1640 let Predicates = [HasAVX512] in
1641 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1642 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1645 let Predicates = [HasBWI] in {
1646 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1648 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1652 let Predicates = [HasBWI] in {
1653 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1655 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1659 // GR from/to mask register
1660 let Predicates = [HasDQI] in {
1661 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1662 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1663 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1664 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1666 let Predicates = [HasAVX512] in {
1667 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1668 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1669 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1670 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1672 let Predicates = [HasBWI] in {
1673 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1674 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1676 let Predicates = [HasBWI] in {
1677 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1678 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1682 let Predicates = [HasDQI] in {
1683 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1684 (KMOVBmk addr:$dst, VK8:$src)>;
1685 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1686 (KMOVBkm addr:$src)>;
1688 let Predicates = [HasAVX512, NoDQI] in {
1689 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1690 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1691 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1692 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1694 let Predicates = [HasAVX512] in {
1695 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1696 (KMOVWmk addr:$dst, VK16:$src)>;
1697 def : Pat<(i1 (load addr:$src)),
1698 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1699 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1700 (KMOVWkm addr:$src)>;
1702 let Predicates = [HasBWI] in {
1703 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1704 (KMOVDmk addr:$dst, VK32:$src)>;
1705 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1706 (KMOVDkm addr:$src)>;
1708 let Predicates = [HasBWI] in {
1709 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1710 (KMOVQmk addr:$dst, VK64:$src)>;
1711 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1712 (KMOVQkm addr:$src)>;
1715 let Predicates = [HasAVX512] in {
1716 def : Pat<(i1 (trunc (i64 GR64:$src))),
1717 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1720 def : Pat<(i1 (trunc (i32 GR32:$src))),
1721 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1723 def : Pat<(i1 (trunc (i8 GR8:$src))),
1725 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1727 def : Pat<(i1 (trunc (i16 GR16:$src))),
1729 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1732 def : Pat<(i32 (zext VK1:$src)),
1733 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1734 def : Pat<(i8 (zext VK1:$src)),
1737 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1738 def : Pat<(i64 (zext VK1:$src)),
1739 (AND64ri8 (SUBREG_TO_REG (i64 0),
1740 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1741 def : Pat<(i16 (zext VK1:$src)),
1743 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1745 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1746 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1747 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1748 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1750 let Predicates = [HasBWI] in {
1751 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1752 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1753 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1754 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1758 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1759 let Predicates = [HasAVX512] in {
1760 // GR from/to 8-bit mask without native support
1761 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1763 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1765 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1767 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1770 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1771 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1772 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1773 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1775 let Predicates = [HasBWI] in {
1776 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1777 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1778 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1779 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1782 // Mask unary operation
1784 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1785 RegisterClass KRC, SDPatternOperator OpNode,
1787 let Predicates = [prd] in
1788 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1789 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1790 [(set KRC:$dst, (OpNode KRC:$src))]>;
1793 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1794 SDPatternOperator OpNode> {
1795 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1797 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1798 HasAVX512>, VEX, PS;
1799 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1800 HasBWI>, VEX, PD, VEX_W;
1801 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1802 HasBWI>, VEX, PS, VEX_W;
1805 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1807 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1808 let Predicates = [HasAVX512] in
1809 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1811 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1812 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1814 defm : avx512_mask_unop_int<"knot", "KNOT">;
1816 let Predicates = [HasDQI] in
1817 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1818 let Predicates = [HasAVX512] in
1819 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1820 let Predicates = [HasBWI] in
1821 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1822 let Predicates = [HasBWI] in
1823 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1825 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1826 let Predicates = [HasAVX512, NoDQI] in {
1827 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1828 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1830 def : Pat<(not VK8:$src),
1832 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1835 // Mask binary operation
1836 // - KAND, KANDN, KOR, KXNOR, KXOR
1837 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1838 RegisterClass KRC, SDPatternOperator OpNode,
1840 let Predicates = [prd] in
1841 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1842 !strconcat(OpcodeStr,
1843 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1844 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1847 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1848 SDPatternOperator OpNode> {
1849 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1850 HasDQI>, VEX_4V, VEX_L, PD;
1851 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1852 HasAVX512>, VEX_4V, VEX_L, PS;
1853 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1854 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1855 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1856 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1859 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1860 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1862 let isCommutable = 1 in {
1863 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1864 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1865 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1866 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1868 let isCommutable = 0 in
1869 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1871 def : Pat<(xor VK1:$src1, VK1:$src2),
1872 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1873 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1875 def : Pat<(or VK1:$src1, VK1:$src2),
1876 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1877 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1879 def : Pat<(and VK1:$src1, VK1:$src2),
1880 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1881 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1883 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1884 let Predicates = [HasAVX512] in
1885 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1886 (i16 GR16:$src1), (i16 GR16:$src2)),
1887 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1888 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1889 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1892 defm : avx512_mask_binop_int<"kand", "KAND">;
1893 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1894 defm : avx512_mask_binop_int<"kor", "KOR">;
1895 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1896 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1898 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1899 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1900 let Predicates = [HasAVX512] in
1901 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1903 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1904 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1907 defm : avx512_binop_pat<and, KANDWrr>;
1908 defm : avx512_binop_pat<andn, KANDNWrr>;
1909 defm : avx512_binop_pat<or, KORWrr>;
1910 defm : avx512_binop_pat<xnor, KXNORWrr>;
1911 defm : avx512_binop_pat<xor, KXORWrr>;
1914 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1915 RegisterClass KRC> {
1916 let Predicates = [HasAVX512] in
1917 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1918 !strconcat(OpcodeStr,
1919 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1922 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1923 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1927 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1928 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1929 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1930 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1933 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1934 let Predicates = [HasAVX512] in
1935 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1936 (i16 GR16:$src1), (i16 GR16:$src2)),
1937 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1938 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1939 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1941 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1944 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1946 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1947 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1948 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1949 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1952 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1953 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1955 let Predicates = [HasDQI] in
1956 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
1958 let Predicates = [HasBWI] in {
1959 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
1961 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
1966 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1969 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1971 let Predicates = [HasAVX512] in
1972 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
1973 !strconcat(OpcodeStr,
1974 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1975 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1978 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1980 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1982 let Predicates = [HasDQI] in
1983 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
1985 let Predicates = [HasBWI] in {
1986 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
1988 let Predicates = [HasDQI] in
1989 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
1994 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1995 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1997 // Mask setting all 0s or 1s
1998 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1999 let Predicates = [HasAVX512] in
2000 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2001 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2002 [(set KRC:$dst, (VT Val))]>;
2005 multiclass avx512_mask_setop_w<PatFrag Val> {
2006 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2007 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2010 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2011 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2013 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2014 let Predicates = [HasAVX512] in {
2015 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2016 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2017 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2018 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2019 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2021 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2022 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2024 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2025 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2027 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2028 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2030 let Predicates = [HasVLX] in {
2031 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2032 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2033 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2034 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2035 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2036 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2037 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2038 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2041 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2042 (v8i1 (COPY_TO_REGCLASS
2043 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2044 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2046 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2047 (v8i1 (COPY_TO_REGCLASS
2048 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2049 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2050 //===----------------------------------------------------------------------===//
2051 // AVX-512 - Aligned and unaligned load and store
2054 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
2055 RegisterClass KRC, RegisterClass RC,
2056 ValueType vt, ValueType zvt, X86MemOperand memop,
2057 Domain d, bit IsReMaterializable = 1> {
2058 let hasSideEffects = 0 in {
2059 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2060 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2062 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2063 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2064 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2066 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2067 SchedRW = [WriteLoad] in
2068 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2069 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2070 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2073 let AddedComplexity = 20 in {
2074 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2075 let hasSideEffects = 0 in
2076 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2077 (ins RC:$src0, KRC:$mask, RC:$src1),
2078 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2079 "${dst} {${mask}}, $src1}"),
2080 [(set RC:$dst, (vt (vselect KRC:$mask,
2084 let mayLoad = 1, SchedRW = [WriteLoad] in
2085 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2086 (ins RC:$src0, KRC:$mask, memop:$src1),
2087 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2088 "${dst} {${mask}}, $src1}"),
2091 (vt (bitconvert (ld_frag addr:$src1))),
2095 let mayLoad = 1, SchedRW = [WriteLoad] in
2096 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2097 (ins KRC:$mask, memop:$src),
2098 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2099 "${dst} {${mask}} {z}, $src}"),
2102 (vt (bitconvert (ld_frag addr:$src))),
2103 (vt (bitconvert (zvt immAllZerosV))))))],
2108 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2109 string elty, string elsz, string vsz512,
2110 string vsz256, string vsz128, Domain d,
2111 Predicate prd, bit IsReMaterializable = 1> {
2112 let Predicates = [prd] in
2113 defm Z : avx512_load<opc, OpcodeStr,
2114 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2115 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2116 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2117 !cast<X86MemOperand>(elty##"512mem"), d,
2118 IsReMaterializable>, EVEX_V512;
2120 let Predicates = [prd, HasVLX] in {
2121 defm Z256 : avx512_load<opc, OpcodeStr,
2122 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2123 "v"##vsz256##elty##elsz, "v4i64")),
2124 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2125 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2126 !cast<X86MemOperand>(elty##"256mem"), d,
2127 IsReMaterializable>, EVEX_V256;
2129 defm Z128 : avx512_load<opc, OpcodeStr,
2130 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2131 "v"##vsz128##elty##elsz, "v2i64")),
2132 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2133 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2134 !cast<X86MemOperand>(elty##"128mem"), d,
2135 IsReMaterializable>, EVEX_V128;
2140 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2141 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2142 X86MemOperand memop, Domain d> {
2143 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2144 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2145 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2147 let Constraints = "$src1 = $dst" in
2148 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2149 (ins RC:$src1, KRC:$mask, RC:$src2),
2150 !strconcat(OpcodeStr,
2151 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2153 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2154 (ins KRC:$mask, RC:$src),
2155 !strconcat(OpcodeStr,
2156 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2157 [], d>, EVEX, EVEX_KZ;
2159 let mayStore = 1 in {
2160 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2161 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2162 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2163 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2164 (ins memop:$dst, KRC:$mask, RC:$src),
2165 !strconcat(OpcodeStr,
2166 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2167 [], d>, EVEX, EVEX_K;
2172 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2173 string st_suff_512, string st_suff_256,
2174 string st_suff_128, string elty, string elsz,
2175 string vsz512, string vsz256, string vsz128,
2176 Domain d, Predicate prd> {
2177 let Predicates = [prd] in
2178 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2179 !cast<ValueType>("v"##vsz512##elty##elsz),
2180 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2181 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2183 let Predicates = [prd, HasVLX] in {
2184 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2185 !cast<ValueType>("v"##vsz256##elty##elsz),
2186 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2187 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2189 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2190 !cast<ValueType>("v"##vsz128##elty##elsz),
2191 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2192 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2196 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2197 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2198 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2199 "512", "256", "", "f", "32", "16", "8", "4",
2200 SSEPackedSingle, HasAVX512>,
2201 PS, EVEX_CD8<32, CD8VF>;
2203 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2204 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2205 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2206 "512", "256", "", "f", "64", "8", "4", "2",
2207 SSEPackedDouble, HasAVX512>,
2208 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2210 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2211 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2212 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2213 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2214 PS, EVEX_CD8<32, CD8VF>;
2216 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2217 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2218 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2219 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2220 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2222 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2223 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2224 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2226 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2227 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2228 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2230 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2231 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2232 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2234 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2235 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2236 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2238 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2239 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2240 (VMOVAPDZrm addr:$ptr)>;
2242 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2243 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2244 (VMOVAPSZrm addr:$ptr)>;
2246 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2248 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2250 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2252 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2255 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2257 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2259 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2261 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2264 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2265 (VMOVUPSZmrk addr:$ptr,
2266 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2267 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2269 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2270 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2271 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2273 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2274 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2276 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2277 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2279 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2280 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2282 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2283 (bc_v16f32 (v16i32 immAllZerosV)))),
2284 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2286 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2287 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2289 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2290 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2292 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2293 (bc_v8f64 (v16i32 immAllZerosV)))),
2294 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2296 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2297 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2299 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2300 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2301 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2302 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2304 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2305 "16", "8", "4", SSEPackedInt, HasAVX512>,
2306 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2307 "512", "256", "", "i", "32", "16", "8", "4",
2308 SSEPackedInt, HasAVX512>,
2309 PD, EVEX_CD8<32, CD8VF>;
2311 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2312 "8", "4", "2", SSEPackedInt, HasAVX512>,
2313 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2314 "512", "256", "", "i", "64", "8", "4", "2",
2315 SSEPackedInt, HasAVX512>,
2316 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2318 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2319 "64", "32", "16", SSEPackedInt, HasBWI>,
2320 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2321 "i", "8", "64", "32", "16", SSEPackedInt,
2322 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2324 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2325 "32", "16", "8", SSEPackedInt, HasBWI>,
2326 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2327 "i", "16", "32", "16", "8", SSEPackedInt,
2328 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2330 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2331 "16", "8", "4", SSEPackedInt, HasAVX512>,
2332 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2333 "i", "32", "16", "8", "4", SSEPackedInt,
2334 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2336 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2337 "8", "4", "2", SSEPackedInt, HasAVX512>,
2338 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2339 "i", "64", "8", "4", "2", SSEPackedInt,
2340 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2342 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2343 (v16i32 immAllZerosV), GR16:$mask)),
2344 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2346 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2347 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2348 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2350 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2352 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2354 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2356 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2359 let AddedComplexity = 20 in {
2360 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2361 (bc_v8i64 (v16i32 immAllZerosV)))),
2362 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2364 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2365 (v8i64 VR512:$src))),
2366 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2369 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2370 (v16i32 immAllZerosV))),
2371 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2373 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2374 (v16i32 VR512:$src))),
2375 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2378 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2379 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2381 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2382 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2384 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2385 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2387 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2388 (bc_v8i64 (v16i32 immAllZerosV)))),
2389 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2391 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2392 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2394 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2395 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2397 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2398 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2400 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2401 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2404 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2405 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2408 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2409 (VMOVDQU32Zmrk addr:$ptr,
2410 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2411 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2413 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2414 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2415 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2418 // Move Int Doubleword to Packed Double Int
2420 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2421 "vmovd\t{$src, $dst|$dst, $src}",
2423 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2425 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2426 "vmovd\t{$src, $dst|$dst, $src}",
2428 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2429 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2430 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2431 "vmovq\t{$src, $dst|$dst, $src}",
2433 (v2i64 (scalar_to_vector GR64:$src)))],
2434 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2435 let isCodeGenOnly = 1 in {
2436 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2437 "vmovq\t{$src, $dst|$dst, $src}",
2438 [(set FR64:$dst, (bitconvert GR64:$src))],
2439 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2440 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2441 "vmovq\t{$src, $dst|$dst, $src}",
2442 [(set GR64:$dst, (bitconvert FR64:$src))],
2443 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2445 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2446 "vmovq\t{$src, $dst|$dst, $src}",
2447 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2448 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2449 EVEX_CD8<64, CD8VT1>;
2451 // Move Int Doubleword to Single Scalar
2453 let isCodeGenOnly = 1 in {
2454 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2455 "vmovd\t{$src, $dst|$dst, $src}",
2456 [(set FR32X:$dst, (bitconvert GR32:$src))],
2457 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2459 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2460 "vmovd\t{$src, $dst|$dst, $src}",
2461 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2462 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2465 // Move doubleword from xmm register to r/m32
2467 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2468 "vmovd\t{$src, $dst|$dst, $src}",
2469 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2470 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2472 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2473 (ins i32mem:$dst, VR128X:$src),
2474 "vmovd\t{$src, $dst|$dst, $src}",
2475 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2476 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2477 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2479 // Move quadword from xmm1 register to r/m64
2481 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2482 "vmovq\t{$src, $dst|$dst, $src}",
2483 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2485 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2486 Requires<[HasAVX512, In64BitMode]>;
2488 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2489 (ins i64mem:$dst, VR128X:$src),
2490 "vmovq\t{$src, $dst|$dst, $src}",
2491 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2492 addr:$dst)], IIC_SSE_MOVDQ>,
2493 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2494 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2496 // Move Scalar Single to Double Int
2498 let isCodeGenOnly = 1 in {
2499 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2501 "vmovd\t{$src, $dst|$dst, $src}",
2502 [(set GR32:$dst, (bitconvert FR32X:$src))],
2503 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2504 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2505 (ins i32mem:$dst, FR32X:$src),
2506 "vmovd\t{$src, $dst|$dst, $src}",
2507 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2508 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2511 // Move Quadword Int to Packed Quadword Int
2513 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2515 "vmovq\t{$src, $dst|$dst, $src}",
2517 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2518 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2520 //===----------------------------------------------------------------------===//
2521 // AVX-512 MOVSS, MOVSD
2522 //===----------------------------------------------------------------------===//
2524 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2525 SDNode OpNode, ValueType vt,
2526 X86MemOperand x86memop, PatFrag mem_pat> {
2527 let hasSideEffects = 0 in {
2528 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2529 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2530 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2531 (scalar_to_vector RC:$src2))))],
2532 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2533 let Constraints = "$src1 = $dst" in
2534 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2535 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2537 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2538 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2539 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2540 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2541 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2543 let mayStore = 1 in {
2544 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2545 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2546 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2548 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2549 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2550 [], IIC_SSE_MOV_S_MR>,
2551 EVEX, VEX_LIG, EVEX_K;
2553 } //hasSideEffects = 0
2556 let ExeDomain = SSEPackedSingle in
2557 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2558 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2560 let ExeDomain = SSEPackedDouble in
2561 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2562 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2564 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2565 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2566 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2568 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2569 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2570 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2572 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2573 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2574 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2576 // For the disassembler
2577 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2578 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2579 (ins VR128X:$src1, FR32X:$src2),
2580 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2582 XS, EVEX_4V, VEX_LIG;
2583 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2584 (ins VR128X:$src1, FR64X:$src2),
2585 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2587 XD, EVEX_4V, VEX_LIG, VEX_W;
2590 let Predicates = [HasAVX512] in {
2591 let AddedComplexity = 15 in {
2592 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2593 // MOVS{S,D} to the lower bits.
2594 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2595 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2596 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2597 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2598 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2599 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2600 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2601 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2603 // Move low f32 and clear high bits.
2604 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2605 (SUBREG_TO_REG (i32 0),
2606 (VMOVSSZrr (v4f32 (V_SET0)),
2607 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2608 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2609 (SUBREG_TO_REG (i32 0),
2610 (VMOVSSZrr (v4i32 (V_SET0)),
2611 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2614 let AddedComplexity = 20 in {
2615 // MOVSSrm zeros the high parts of the register; represent this
2616 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2617 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2618 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2619 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2620 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2621 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2622 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2624 // MOVSDrm zeros the high parts of the register; represent this
2625 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2626 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2627 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2628 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2629 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2630 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2631 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2632 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2633 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2634 def : Pat<(v2f64 (X86vzload addr:$src)),
2635 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2637 // Represent the same patterns above but in the form they appear for
2639 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2640 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2641 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2642 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2643 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2644 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2645 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2646 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2647 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2649 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2650 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2651 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2652 FR32X:$src)), sub_xmm)>;
2653 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2654 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2655 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2656 FR64X:$src)), sub_xmm)>;
2657 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2658 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2659 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2661 // Move low f64 and clear high bits.
2662 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2663 (SUBREG_TO_REG (i32 0),
2664 (VMOVSDZrr (v2f64 (V_SET0)),
2665 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2667 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2668 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2669 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2671 // Extract and store.
2672 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2674 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2675 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2677 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2679 // Shuffle with VMOVSS
2680 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2681 (VMOVSSZrr (v4i32 VR128X:$src1),
2682 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2683 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2684 (VMOVSSZrr (v4f32 VR128X:$src1),
2685 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2688 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2689 (SUBREG_TO_REG (i32 0),
2690 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2691 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2693 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2694 (SUBREG_TO_REG (i32 0),
2695 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2696 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2699 // Shuffle with VMOVSD
2700 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2701 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2702 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2703 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2704 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2705 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2706 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2707 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2710 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2711 (SUBREG_TO_REG (i32 0),
2712 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2713 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2715 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2716 (SUBREG_TO_REG (i32 0),
2717 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2718 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2721 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2722 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2723 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2724 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2725 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2726 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2727 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2728 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2731 let AddedComplexity = 15 in
2732 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2734 "vmovq\t{$src, $dst|$dst, $src}",
2735 [(set VR128X:$dst, (v2i64 (X86vzmovl
2736 (v2i64 VR128X:$src))))],
2737 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2739 let AddedComplexity = 20 in
2740 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2742 "vmovq\t{$src, $dst|$dst, $src}",
2743 [(set VR128X:$dst, (v2i64 (X86vzmovl
2744 (loadv2i64 addr:$src))))],
2745 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2746 EVEX_CD8<8, CD8VT8>;
2748 let Predicates = [HasAVX512] in {
2749 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2750 let AddedComplexity = 20 in {
2751 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2752 (VMOVDI2PDIZrm addr:$src)>;
2753 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2754 (VMOV64toPQIZrr GR64:$src)>;
2755 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2756 (VMOVDI2PDIZrr GR32:$src)>;
2758 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2759 (VMOVDI2PDIZrm addr:$src)>;
2760 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2761 (VMOVDI2PDIZrm addr:$src)>;
2762 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2763 (VMOVZPQILo2PQIZrm addr:$src)>;
2764 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2765 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2766 def : Pat<(v2i64 (X86vzload addr:$src)),
2767 (VMOVZPQILo2PQIZrm addr:$src)>;
2770 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2771 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2772 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2773 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2774 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2775 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2776 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2779 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2780 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2782 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2783 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2785 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2786 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2788 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2789 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2791 //===----------------------------------------------------------------------===//
2792 // AVX-512 - Non-temporals
2793 //===----------------------------------------------------------------------===//
2794 let SchedRW = [WriteLoad] in {
2795 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2796 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2797 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2798 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2799 EVEX_CD8<64, CD8VF>;
2801 let Predicates = [HasAVX512, HasVLX] in {
2802 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2804 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2805 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2806 EVEX_CD8<64, CD8VF>;
2808 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2810 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2811 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2812 EVEX_CD8<64, CD8VF>;
2816 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2817 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2818 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2819 let SchedRW = [WriteStore], mayStore = 1,
2820 AddedComplexity = 400 in
2821 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2822 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2823 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2826 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2827 string elty, string elsz, string vsz512,
2828 string vsz256, string vsz128, Domain d,
2829 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2830 let Predicates = [prd] in
2831 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2832 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2833 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2836 let Predicates = [prd, HasVLX] in {
2837 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2838 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2839 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2842 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2843 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2844 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2849 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2850 "i", "64", "8", "4", "2", SSEPackedInt,
2851 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2853 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2854 "f", "64", "8", "4", "2", SSEPackedDouble,
2855 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2857 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2858 "f", "32", "16", "8", "4", SSEPackedSingle,
2859 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2861 //===----------------------------------------------------------------------===//
2862 // AVX-512 - Integer arithmetic
2864 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2865 X86VectorVTInfo _, OpndItins itins,
2866 bit IsCommutable = 0> {
2867 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2868 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2869 "$src2, $src1", "$src1, $src2",
2870 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2871 "", itins.rr, IsCommutable>,
2872 AVX512BIBase, EVEX_4V;
2875 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2876 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2877 "$src2, $src1", "$src1, $src2",
2878 (_.VT (OpNode _.RC:$src1,
2879 (bitconvert (_.LdFrag addr:$src2)))),
2881 AVX512BIBase, EVEX_4V;
2884 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2885 X86VectorVTInfo _, OpndItins itins,
2886 bit IsCommutable = 0> :
2887 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2889 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2890 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2891 "${src2}"##_.BroadcastStr##", $src1",
2892 "$src1, ${src2}"##_.BroadcastStr,
2893 (_.VT (OpNode _.RC:$src1,
2895 (_.ScalarLdFrag addr:$src2)))),
2897 AVX512BIBase, EVEX_4V, EVEX_B;
2900 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2901 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2902 Predicate prd, bit IsCommutable = 0> {
2903 let Predicates = [prd] in
2904 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2905 IsCommutable>, EVEX_V512;
2907 let Predicates = [prd, HasVLX] in {
2908 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2909 IsCommutable>, EVEX_V256;
2910 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2911 IsCommutable>, EVEX_V128;
2915 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2916 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2917 Predicate prd, bit IsCommutable = 0> {
2918 let Predicates = [prd] in
2919 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2920 IsCommutable>, EVEX_V512;
2922 let Predicates = [prd, HasVLX] in {
2923 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2924 IsCommutable>, EVEX_V256;
2925 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2926 IsCommutable>, EVEX_V128;
2930 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2931 OpndItins itins, Predicate prd,
2932 bit IsCommutable = 0> {
2933 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2934 itins, prd, IsCommutable>,
2935 VEX_W, EVEX_CD8<64, CD8VF>;
2938 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2939 OpndItins itins, Predicate prd,
2940 bit IsCommutable = 0> {
2941 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2942 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2945 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2946 OpndItins itins, Predicate prd,
2947 bit IsCommutable = 0> {
2948 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2949 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2952 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2953 OpndItins itins, Predicate prd,
2954 bit IsCommutable = 0> {
2955 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2956 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2959 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2960 SDNode OpNode, OpndItins itins, Predicate prd,
2961 bit IsCommutable = 0> {
2962 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2965 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2969 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2970 SDNode OpNode, OpndItins itins, Predicate prd,
2971 bit IsCommutable = 0> {
2972 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2975 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2979 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2980 bits<8> opc_d, bits<8> opc_q,
2981 string OpcodeStr, SDNode OpNode,
2982 OpndItins itins, bit IsCommutable = 0> {
2983 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2984 itins, HasAVX512, IsCommutable>,
2985 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2986 itins, HasBWI, IsCommutable>;
2989 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2990 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2991 PatFrag memop_frag, X86MemOperand x86memop,
2992 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2993 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2994 let isCommutable = IsCommutable in
2996 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2997 (ins RC:$src1, RC:$src2),
2998 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3000 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3001 (ins KRC:$mask, RC:$src1, RC:$src2),
3002 !strconcat(OpcodeStr,
3003 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3004 [], itins.rr>, EVEX_4V, EVEX_K;
3005 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3006 (ins KRC:$mask, RC:$src1, RC:$src2),
3007 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
3008 "|$dst {${mask}} {z}, $src1, $src2}"),
3009 [], itins.rr>, EVEX_4V, EVEX_KZ;
3011 let mayLoad = 1 in {
3012 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3013 (ins RC:$src1, x86memop:$src2),
3014 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3016 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3017 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3018 !strconcat(OpcodeStr,
3019 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3020 [], itins.rm>, EVEX_4V, EVEX_K;
3021 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3022 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3023 !strconcat(OpcodeStr,
3024 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
3025 [], itins.rm>, EVEX_4V, EVEX_KZ;
3026 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3027 (ins RC:$src1, x86scalar_mop:$src2),
3028 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3029 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
3030 [], itins.rm>, EVEX_4V, EVEX_B;
3031 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3032 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3033 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3034 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
3036 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
3037 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3038 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3039 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3040 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3042 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
3046 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3047 SSE_INTALU_ITINS_P, 1>;
3048 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3049 SSE_INTALU_ITINS_P, 0>;
3050 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3051 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3052 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3053 SSE_INTALU_ITINS_P, HasBWI, 1>;
3054 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3055 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3057 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
3058 loadv8i64, i512mem, loadi64, i64mem, "{1to8}",
3059 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
3060 EVEX_CD8<64, CD8VF>, VEX_W;
3062 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
3063 loadv8i64, i512mem, loadi64, i64mem, "{1to8}",
3064 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3066 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
3067 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3069 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
3070 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3071 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3072 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
3073 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3074 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
3076 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3077 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3078 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3079 SSE_INTALU_ITINS_P, HasBWI, 1>;
3080 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3081 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3083 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3084 SSE_INTALU_ITINS_P, HasBWI, 1>;
3085 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3086 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3087 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3088 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3090 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3091 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3092 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3093 SSE_INTALU_ITINS_P, HasBWI, 1>;
3094 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3095 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3097 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3098 SSE_INTALU_ITINS_P, HasBWI, 1>;
3099 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3100 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3101 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3102 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3104 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3105 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3106 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3107 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3108 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3109 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3110 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3111 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3112 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3113 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3114 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3115 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3116 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3117 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3118 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3119 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3120 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3121 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3122 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3123 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3124 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3125 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3126 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3127 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3128 //===----------------------------------------------------------------------===//
3129 // AVX-512 - Unpack Instructions
3130 //===----------------------------------------------------------------------===//
3132 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3133 PatFrag mem_frag, RegisterClass RC,
3134 X86MemOperand x86memop, string asm,
3136 def rr : AVX512PI<opc, MRMSrcReg,
3137 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3139 (vt (OpNode RC:$src1, RC:$src2)))],
3141 def rm : AVX512PI<opc, MRMSrcMem,
3142 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3144 (vt (OpNode RC:$src1,
3145 (bitconvert (mem_frag addr:$src2)))))],
3149 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3150 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3151 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3152 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3153 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3154 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3155 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3156 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3157 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3158 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3159 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3160 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3162 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3163 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3164 X86MemOperand x86memop> {
3165 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3166 (ins RC:$src1, RC:$src2),
3167 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3168 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3169 IIC_SSE_UNPCK>, EVEX_4V;
3170 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3171 (ins RC:$src1, x86memop:$src2),
3172 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3173 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3174 (bitconvert (memop_frag addr:$src2)))))],
3175 IIC_SSE_UNPCK>, EVEX_4V;
3177 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3178 VR512, loadv16i32, i512mem>, EVEX_V512,
3179 EVEX_CD8<32, CD8VF>;
3180 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3181 VR512, loadv8i64, i512mem>, EVEX_V512,
3182 VEX_W, EVEX_CD8<64, CD8VF>;
3183 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3184 VR512, loadv16i32, i512mem>, EVEX_V512,
3185 EVEX_CD8<32, CD8VF>;
3186 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3187 VR512, loadv8i64, i512mem>, EVEX_V512,
3188 VEX_W, EVEX_CD8<64, CD8VF>;
3189 //===----------------------------------------------------------------------===//
3193 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3194 SDNode OpNode, PatFrag mem_frag,
3195 X86MemOperand x86memop, ValueType OpVT> {
3196 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3197 (ins RC:$src1, u8imm:$src2),
3198 !strconcat(OpcodeStr,
3199 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3201 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3203 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3204 (ins x86memop:$src1, u8imm:$src2),
3205 !strconcat(OpcodeStr,
3206 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3208 (OpVT (OpNode (mem_frag addr:$src1),
3209 (i8 imm:$src2))))]>, EVEX;
3212 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, loadv16i32,
3213 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3215 //===----------------------------------------------------------------------===//
3216 // AVX-512 Logical Instructions
3217 //===----------------------------------------------------------------------===//
3219 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3220 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3221 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3222 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3223 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3224 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3225 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3226 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3228 //===----------------------------------------------------------------------===//
3229 // AVX-512 FP arithmetic
3230 //===----------------------------------------------------------------------===//
3232 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3234 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3235 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3236 EVEX_CD8<32, CD8VT1>;
3237 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3238 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3239 EVEX_CD8<64, CD8VT1>;
3242 let isCommutable = 1 in {
3243 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3244 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3245 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3246 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3248 let isCommutable = 0 in {
3249 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3250 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3253 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3254 X86VectorVTInfo _, bit IsCommutable> {
3255 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3256 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3257 "$src2, $src1", "$src1, $src2",
3258 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3259 let mayLoad = 1 in {
3260 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3261 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3262 "$src2, $src1", "$src1, $src2",
3263 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3264 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3265 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3266 "${src2}"##_.BroadcastStr##", $src1",
3267 "$src1, ${src2}"##_.BroadcastStr,
3268 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3269 (_.ScalarLdFrag addr:$src2))))>,
3274 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3275 X86VectorVTInfo _, bit IsCommutable> {
3276 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3277 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3278 "$rc, $src2, $src1", "$src1, $src2, $rc",
3279 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3280 EVEX_4V, EVEX_B, EVEX_RC;
3283 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3284 bit IsCommutable = 0> {
3285 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3286 IsCommutable>, EVEX_V512, PS,
3287 EVEX_CD8<32, CD8VF>;
3288 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3289 IsCommutable>, EVEX_V512, PD, VEX_W,
3290 EVEX_CD8<64, CD8VF>;
3292 // Define only if AVX512VL feature is present.
3293 let Predicates = [HasVLX] in {
3294 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3295 IsCommutable>, EVEX_V128, PS,
3296 EVEX_CD8<32, CD8VF>;
3297 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3298 IsCommutable>, EVEX_V256, PS,
3299 EVEX_CD8<32, CD8VF>;
3300 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3301 IsCommutable>, EVEX_V128, PD, VEX_W,
3302 EVEX_CD8<64, CD8VF>;
3303 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3304 IsCommutable>, EVEX_V256, PD, VEX_W,
3305 EVEX_CD8<64, CD8VF>;
3309 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3310 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3311 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3312 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3313 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3316 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3317 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3318 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3319 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3320 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3321 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3322 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3323 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3324 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3325 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3327 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3328 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3329 (i16 -1), FROUND_CURRENT)),
3330 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3332 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3333 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3334 (i8 -1), FROUND_CURRENT)),
3335 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3337 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3338 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3339 (i16 -1), FROUND_CURRENT)),
3340 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3342 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3343 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3344 (i8 -1), FROUND_CURRENT)),
3345 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3346 //===----------------------------------------------------------------------===//
3347 // AVX-512 VPTESTM instructions
3348 //===----------------------------------------------------------------------===//
3350 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3351 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3352 SDNode OpNode, ValueType vt> {
3353 def rr : AVX512PI<opc, MRMSrcReg,
3354 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3356 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3357 SSEPackedInt>, EVEX_4V;
3358 def rm : AVX512PI<opc, MRMSrcMem,
3359 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3361 [(set KRC:$dst, (OpNode (vt RC:$src1),
3362 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3365 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3366 loadv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3367 EVEX_CD8<32, CD8VF>;
3368 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3369 loadv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3370 EVEX_CD8<64, CD8VF>;
3372 let Predicates = [HasCDI] in {
3373 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3374 loadv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3375 EVEX_CD8<32, CD8VF>;
3376 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3377 loadv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3378 EVEX_CD8<64, CD8VF>;
3381 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3382 (v16i32 VR512:$src2), (i16 -1))),
3383 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3385 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3386 (v8i64 VR512:$src2), (i8 -1))),
3387 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3389 //===----------------------------------------------------------------------===//
3390 // AVX-512 Shift instructions
3391 //===----------------------------------------------------------------------===//
3392 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3393 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3394 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3395 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3396 "$src2, $src1", "$src1, $src2",
3397 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3398 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3399 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3400 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3401 "$src2, $src1", "$src1, $src2",
3402 (_.VT (OpNode (_.LdFrag addr:$src1), (i8 imm:$src2))),
3403 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3406 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3407 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3408 // src2 is always 128-bit
3409 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3410 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3411 "$src2, $src1", "$src1, $src2",
3412 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3413 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3414 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3415 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3416 "$src2, $src1", "$src1, $src2",
3417 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3418 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3421 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3422 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3423 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3426 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3428 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3429 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3430 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3431 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3434 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3436 EVEX_V512, EVEX_CD8<32, CD8VF>;
3437 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3438 v8i64_info>, EVEX_V512,
3439 EVEX_CD8<64, CD8VF>, VEX_W;
3441 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3442 v16i32_info>, EVEX_V512,
3443 EVEX_CD8<32, CD8VF>;
3444 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3445 v8i64_info>, EVEX_V512,
3446 EVEX_CD8<64, CD8VF>, VEX_W;
3448 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3450 EVEX_V512, EVEX_CD8<32, CD8VF>;
3451 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3452 v8i64_info>, EVEX_V512,
3453 EVEX_CD8<64, CD8VF>, VEX_W;
3455 defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3456 defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3457 defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3459 //===-------------------------------------------------------------------===//
3460 // Variable Bit Shifts
3461 //===-------------------------------------------------------------------===//
3462 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3463 X86VectorVTInfo _> {
3464 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3465 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3466 "$src2, $src1", "$src1, $src2",
3467 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3468 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3469 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3470 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3471 "$src2, $src1", "$src1, $src2",
3472 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2))),
3473 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
3476 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3477 AVX512VLVectorVTInfo _> {
3478 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3481 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3483 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3484 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
3485 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3486 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3489 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
3490 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
3491 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
3493 //===----------------------------------------------------------------------===//
3494 // AVX-512 - MOVDDUP
3495 //===----------------------------------------------------------------------===//
3497 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3498 X86MemOperand x86memop, PatFrag memop_frag> {
3499 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3500 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3501 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3502 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3503 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3505 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3508 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3509 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3510 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3511 (VMOVDDUPZrm addr:$src)>;
3513 //===---------------------------------------------------------------------===//
3514 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3515 //===---------------------------------------------------------------------===//
3516 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3517 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3518 X86MemOperand x86memop> {
3519 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3520 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3521 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3523 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3524 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3525 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3528 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3529 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3530 EVEX_CD8<32, CD8VF>;
3531 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3532 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3533 EVEX_CD8<32, CD8VF>;
3535 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3536 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3537 (VMOVSHDUPZrm addr:$src)>;
3538 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3539 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3540 (VMOVSLDUPZrm addr:$src)>;
3542 //===----------------------------------------------------------------------===//
3543 // Move Low to High and High to Low packed FP Instructions
3544 //===----------------------------------------------------------------------===//
3545 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3546 (ins VR128X:$src1, VR128X:$src2),
3547 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3548 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3549 IIC_SSE_MOV_LH>, EVEX_4V;
3550 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3551 (ins VR128X:$src1, VR128X:$src2),
3552 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3553 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3554 IIC_SSE_MOV_LH>, EVEX_4V;
3556 let Predicates = [HasAVX512] in {
3558 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3559 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3560 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3561 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3564 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3565 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3568 //===----------------------------------------------------------------------===//
3569 // FMA - Fused Multiply Operations
3572 let Constraints = "$src1 = $dst" in {
3573 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3574 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3575 SDPatternOperator OpNode = null_frag> {
3576 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3577 (ins _.RC:$src2, _.RC:$src3),
3578 OpcodeStr, "$src3, $src2", "$src2, $src3",
3579 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3583 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3584 (ins _.RC:$src2, _.MemOp:$src3),
3585 OpcodeStr, "$src3, $src2", "$src2, $src3",
3586 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3589 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3590 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3591 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ),
3592 (OpNode _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3593 AVX512FMA3Base, EVEX_B;
3595 } // Constraints = "$src1 = $dst"
3597 let Constraints = "$src1 = $dst" in {
3598 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3599 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3600 SDPatternOperator OpNode> {
3601 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3602 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
3603 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
3604 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
3605 AVX512FMA3Base, EVEX_B, EVEX_RC;
3607 } // Constraints = "$src1 = $dst"
3609 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
3610 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
3611 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3612 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3615 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3616 string OpcodeStr, X86VectorVTInfo VTI,
3617 SDPatternOperator OpNode> {
3618 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3619 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3621 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3622 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
3625 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
3627 SDPatternOperator OpNode,
3628 SDPatternOperator OpNodeRnd> {
3629 let ExeDomain = SSEPackedSingle in {
3630 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3631 v16f32_info, OpNode>,
3632 avx512_fma3_round_forms<opc213, OpcodeStr,
3633 v16f32_info, OpNodeRnd>, EVEX_V512;
3634 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3635 v8f32x_info, OpNode>, EVEX_V256;
3636 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3637 v4f32x_info, OpNode>, EVEX_V128;
3639 let ExeDomain = SSEPackedDouble in {
3640 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3641 v8f64_info, OpNode>,
3642 avx512_fma3_round_forms<opc213, OpcodeStr,
3643 v8f64_info, OpNodeRnd>, EVEX_V512, VEX_W;
3644 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3645 v4f64x_info, OpNode>, EVEX_V256, VEX_W;
3646 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3647 v2f64x_info, OpNode>, EVEX_V128, VEX_W;
3651 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
3652 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
3653 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
3654 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
3655 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
3656 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
3658 let Constraints = "$src1 = $dst" in {
3659 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3660 X86VectorVTInfo _> {
3662 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3663 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3664 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3665 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
3667 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3668 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3669 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3670 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3672 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3673 (_.ScalarLdFrag addr:$src2))),
3674 _.RC:$src3))]>, EVEX_B;
3676 } // Constraints = "$src1 = $dst"
3679 multiclass avx512_fma3p_m132_f<bits<8> opc,
3683 let ExeDomain = SSEPackedSingle in {
3684 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
3685 OpNode,v16f32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3686 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3687 OpNode, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>;
3688 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3689 OpNode, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>;
3691 let ExeDomain = SSEPackedDouble in {
3692 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
3693 OpNode, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VF>;
3694 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3695 OpNode, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<32, CD8VF>;
3696 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3697 OpNode, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<32, CD8VF>;
3701 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
3702 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
3703 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
3704 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
3705 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
3706 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
3710 let Constraints = "$src1 = $dst" in {
3711 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3712 RegisterClass RC, ValueType OpVT,
3713 X86MemOperand x86memop, Operand memop,
3715 let isCommutable = 1 in
3716 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3717 (ins RC:$src1, RC:$src2, RC:$src3),
3718 !strconcat(OpcodeStr,
3719 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3721 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3723 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3724 (ins RC:$src1, RC:$src2, f128mem:$src3),
3725 !strconcat(OpcodeStr,
3726 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3728 (OpVT (OpNode RC:$src2, RC:$src1,
3729 (mem_frag addr:$src3))))]>;
3732 } // Constraints = "$src1 = $dst"
3734 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3735 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3736 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3737 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3738 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3739 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3740 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3741 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3742 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3743 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3744 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3745 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3746 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3747 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3748 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3749 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3751 //===----------------------------------------------------------------------===//
3752 // AVX-512 Scalar convert from sign integer to float/double
3753 //===----------------------------------------------------------------------===//
3755 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3756 X86MemOperand x86memop, string asm> {
3757 let hasSideEffects = 0 in {
3758 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3759 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3762 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3763 (ins DstRC:$src1, x86memop:$src),
3764 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3766 } // hasSideEffects = 0
3768 let Predicates = [HasAVX512] in {
3769 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3770 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3771 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3772 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3773 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3774 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3775 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3776 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3778 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3779 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3780 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3781 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3782 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3783 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3784 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3785 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3787 def : Pat<(f32 (sint_to_fp GR32:$src)),
3788 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3789 def : Pat<(f32 (sint_to_fp GR64:$src)),
3790 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3791 def : Pat<(f64 (sint_to_fp GR32:$src)),
3792 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3793 def : Pat<(f64 (sint_to_fp GR64:$src)),
3794 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3796 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3797 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3798 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3799 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3800 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3801 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3802 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3803 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3805 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3806 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3807 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3808 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3809 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3810 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3811 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3812 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3814 def : Pat<(f32 (uint_to_fp GR32:$src)),
3815 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3816 def : Pat<(f32 (uint_to_fp GR64:$src)),
3817 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3818 def : Pat<(f64 (uint_to_fp GR32:$src)),
3819 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3820 def : Pat<(f64 (uint_to_fp GR64:$src)),
3821 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3824 //===----------------------------------------------------------------------===//
3825 // AVX-512 Scalar convert from float/double to integer
3826 //===----------------------------------------------------------------------===//
3827 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3828 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3830 let hasSideEffects = 0 in {
3831 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3832 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3833 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3834 Requires<[HasAVX512]>;
3836 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3837 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3838 Requires<[HasAVX512]>;
3839 } // hasSideEffects = 0
3841 let Predicates = [HasAVX512] in {
3842 // Convert float/double to signed/unsigned int 32/64
3843 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3844 ssmem, sse_load_f32, "cvtss2si">,
3845 XS, EVEX_CD8<32, CD8VT1>;
3846 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3847 ssmem, sse_load_f32, "cvtss2si">,
3848 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3849 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3850 ssmem, sse_load_f32, "cvtss2usi">,
3851 XS, EVEX_CD8<32, CD8VT1>;
3852 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3853 int_x86_avx512_cvtss2usi64, ssmem,
3854 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3855 EVEX_CD8<32, CD8VT1>;
3856 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3857 sdmem, sse_load_f64, "cvtsd2si">,
3858 XD, EVEX_CD8<64, CD8VT1>;
3859 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3860 sdmem, sse_load_f64, "cvtsd2si">,
3861 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3862 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3863 sdmem, sse_load_f64, "cvtsd2usi">,
3864 XD, EVEX_CD8<64, CD8VT1>;
3865 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3866 int_x86_avx512_cvtsd2usi64, sdmem,
3867 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3868 EVEX_CD8<64, CD8VT1>;
3870 let isCodeGenOnly = 1 in {
3871 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3872 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3873 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3874 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3875 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3876 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3877 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3878 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3879 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3880 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3881 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3882 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3884 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3885 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3886 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3887 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3888 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3889 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3890 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3891 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3892 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3893 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3894 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3895 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3896 } // isCodeGenOnly = 1
3898 // Convert float/double to signed/unsigned int 32/64 with truncation
3899 let isCodeGenOnly = 1 in {
3900 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3901 ssmem, sse_load_f32, "cvttss2si">,
3902 XS, EVEX_CD8<32, CD8VT1>;
3903 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3904 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3905 "cvttss2si">, XS, VEX_W,
3906 EVEX_CD8<32, CD8VT1>;
3907 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3908 sdmem, sse_load_f64, "cvttsd2si">, XD,
3909 EVEX_CD8<64, CD8VT1>;
3910 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3911 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3912 "cvttsd2si">, XD, VEX_W,
3913 EVEX_CD8<64, CD8VT1>;
3914 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3915 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3916 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3917 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3918 int_x86_avx512_cvttss2usi64, ssmem,
3919 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3920 EVEX_CD8<32, CD8VT1>;
3921 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3922 int_x86_avx512_cvttsd2usi,
3923 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3924 EVEX_CD8<64, CD8VT1>;
3925 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3926 int_x86_avx512_cvttsd2usi64, sdmem,
3927 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3928 EVEX_CD8<64, CD8VT1>;
3929 } // isCodeGenOnly = 1
3931 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3932 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3934 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3935 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3936 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3937 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3938 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3939 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3942 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3943 loadf32, "cvttss2si">, XS,
3944 EVEX_CD8<32, CD8VT1>;
3945 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3946 loadf32, "cvttss2usi">, XS,
3947 EVEX_CD8<32, CD8VT1>;
3948 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3949 loadf32, "cvttss2si">, XS, VEX_W,
3950 EVEX_CD8<32, CD8VT1>;
3951 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3952 loadf32, "cvttss2usi">, XS, VEX_W,
3953 EVEX_CD8<32, CD8VT1>;
3954 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3955 loadf64, "cvttsd2si">, XD,
3956 EVEX_CD8<64, CD8VT1>;
3957 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3958 loadf64, "cvttsd2usi">, XD,
3959 EVEX_CD8<64, CD8VT1>;
3960 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3961 loadf64, "cvttsd2si">, XD, VEX_W,
3962 EVEX_CD8<64, CD8VT1>;
3963 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3964 loadf64, "cvttsd2usi">, XD, VEX_W,
3965 EVEX_CD8<64, CD8VT1>;
3967 //===----------------------------------------------------------------------===//
3968 // AVX-512 Convert form float to double and back
3969 //===----------------------------------------------------------------------===//
3970 let hasSideEffects = 0 in {
3971 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3972 (ins FR32X:$src1, FR32X:$src2),
3973 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3974 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3976 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3977 (ins FR32X:$src1, f32mem:$src2),
3978 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3979 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3980 EVEX_CD8<32, CD8VT1>;
3982 // Convert scalar double to scalar single
3983 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3984 (ins FR64X:$src1, FR64X:$src2),
3985 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3986 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3988 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3989 (ins FR64X:$src1, f64mem:$src2),
3990 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3991 []>, EVEX_4V, VEX_LIG, VEX_W,
3992 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3995 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3996 Requires<[HasAVX512]>;
3997 def : Pat<(fextend (loadf32 addr:$src)),
3998 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4000 def : Pat<(extloadf32 addr:$src),
4001 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4002 Requires<[HasAVX512, OptForSize]>;
4004 def : Pat<(extloadf32 addr:$src),
4005 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4006 Requires<[HasAVX512, OptForSpeed]>;
4008 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4009 Requires<[HasAVX512]>;
4011 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4012 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4013 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4015 let hasSideEffects = 0 in {
4016 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4017 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4019 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4020 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4021 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4022 [], d>, EVEX, EVEX_B, EVEX_RC;
4024 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4025 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4027 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4028 } // hasSideEffects = 0
4031 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4032 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4033 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4035 let hasSideEffects = 0 in {
4036 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4037 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4039 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4041 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4042 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4044 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4045 } // hasSideEffects = 0
4048 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4049 loadv8f64, f512mem, v8f32, v8f64,
4050 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4051 EVEX_CD8<64, CD8VF>;
4053 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4054 loadv4f64, f256mem, v8f64, v8f32,
4055 SSEPackedDouble>, EVEX_V512, PS,
4056 EVEX_CD8<32, CD8VH>;
4057 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4058 (VCVTPS2PDZrm addr:$src)>;
4060 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4061 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4062 (VCVTPD2PSZrr VR512:$src)>;
4064 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4065 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4066 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4068 //===----------------------------------------------------------------------===//
4069 // AVX-512 Vector convert from sign integer to float/double
4070 //===----------------------------------------------------------------------===//
4072 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4073 loadv8i64, i512mem, v16f32, v16i32,
4074 SSEPackedSingle>, EVEX_V512, PS,
4075 EVEX_CD8<32, CD8VF>;
4077 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4078 loadv4i64, i256mem, v8f64, v8i32,
4079 SSEPackedDouble>, EVEX_V512, XS,
4080 EVEX_CD8<32, CD8VH>;
4082 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4083 loadv16f32, f512mem, v16i32, v16f32,
4084 SSEPackedSingle>, EVEX_V512, XS,
4085 EVEX_CD8<32, CD8VF>;
4087 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4088 loadv8f64, f512mem, v8i32, v8f64,
4089 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4090 EVEX_CD8<64, CD8VF>;
4092 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4093 loadv16f32, f512mem, v16i32, v16f32,
4094 SSEPackedSingle>, EVEX_V512, PS,
4095 EVEX_CD8<32, CD8VF>;
4097 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4098 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4099 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4100 (VCVTTPS2UDQZrr VR512:$src)>;
4102 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4103 loadv8f64, f512mem, v8i32, v8f64,
4104 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4105 EVEX_CD8<64, CD8VF>;
4107 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4108 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4109 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4110 (VCVTTPD2UDQZrr VR512:$src)>;
4112 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4113 loadv4i64, f256mem, v8f64, v8i32,
4114 SSEPackedDouble>, EVEX_V512, XS,
4115 EVEX_CD8<32, CD8VH>;
4117 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4118 loadv16i32, f512mem, v16f32, v16i32,
4119 SSEPackedSingle>, EVEX_V512, XD,
4120 EVEX_CD8<32, CD8VF>;
4122 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4123 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4124 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4126 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4127 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4128 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4130 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4131 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4132 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4134 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4135 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4136 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4138 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4139 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4140 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4142 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4143 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4144 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4145 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4146 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4147 (VCVTDQ2PDZrr VR256X:$src)>;
4148 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4149 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4150 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4151 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4152 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4153 (VCVTUDQ2PDZrr VR256X:$src)>;
4155 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4156 RegisterClass DstRC, PatFrag mem_frag,
4157 X86MemOperand x86memop, Domain d> {
4158 let hasSideEffects = 0 in {
4159 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4160 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4162 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4163 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4164 [], d>, EVEX, EVEX_B, EVEX_RC;
4166 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4167 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4169 } // hasSideEffects = 0
4172 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4173 loadv16f32, f512mem, SSEPackedSingle>, PD,
4174 EVEX_V512, EVEX_CD8<32, CD8VF>;
4175 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4176 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4177 EVEX_V512, EVEX_CD8<64, CD8VF>;
4179 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4180 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4181 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4183 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4184 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4185 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4187 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4188 loadv16f32, f512mem, SSEPackedSingle>,
4189 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4190 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4191 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4192 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4194 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4195 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4196 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4198 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4199 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4200 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4202 let Predicates = [HasAVX512] in {
4203 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4204 (VCVTPD2PSZrm addr:$src)>;
4205 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4206 (VCVTPS2PDZrm addr:$src)>;
4209 //===----------------------------------------------------------------------===//
4210 // Half precision conversion instructions
4211 //===----------------------------------------------------------------------===//
4212 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4213 X86MemOperand x86memop> {
4214 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4215 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4217 let hasSideEffects = 0, mayLoad = 1 in
4218 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4219 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4222 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4223 X86MemOperand x86memop> {
4224 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4225 (ins srcRC:$src1, i32u8imm:$src2),
4226 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4228 let hasSideEffects = 0, mayStore = 1 in
4229 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4230 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4231 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4234 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4235 EVEX_CD8<32, CD8VH>;
4236 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4237 EVEX_CD8<32, CD8VH>;
4239 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4240 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4241 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4243 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4244 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4245 (VCVTPH2PSZrr VR256X:$src)>;
4247 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4248 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4249 "ucomiss">, PS, EVEX, VEX_LIG,
4250 EVEX_CD8<32, CD8VT1>;
4251 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4252 "ucomisd">, PD, EVEX,
4253 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4254 let Pattern = []<dag> in {
4255 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4256 "comiss">, PS, EVEX, VEX_LIG,
4257 EVEX_CD8<32, CD8VT1>;
4258 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4259 "comisd">, PD, EVEX,
4260 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4262 let isCodeGenOnly = 1 in {
4263 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4264 load, "ucomiss">, PS, EVEX, VEX_LIG,
4265 EVEX_CD8<32, CD8VT1>;
4266 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4267 load, "ucomisd">, PD, EVEX,
4268 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4270 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4271 load, "comiss">, PS, EVEX, VEX_LIG,
4272 EVEX_CD8<32, CD8VT1>;
4273 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4274 load, "comisd">, PD, EVEX,
4275 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4279 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4280 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4281 X86MemOperand x86memop> {
4282 let hasSideEffects = 0 in {
4283 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4284 (ins RC:$src1, RC:$src2),
4285 !strconcat(OpcodeStr,
4286 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4287 let mayLoad = 1 in {
4288 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4289 (ins RC:$src1, x86memop:$src2),
4290 !strconcat(OpcodeStr,
4291 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4296 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4297 EVEX_CD8<32, CD8VT1>;
4298 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4299 VEX_W, EVEX_CD8<64, CD8VT1>;
4300 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4301 EVEX_CD8<32, CD8VT1>;
4302 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4303 VEX_W, EVEX_CD8<64, CD8VT1>;
4305 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4306 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4307 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4308 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4310 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4311 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4312 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4313 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4315 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4316 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4317 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4318 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4320 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4321 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4322 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4323 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4325 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4326 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4327 X86VectorVTInfo _> {
4328 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4329 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4330 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4331 let mayLoad = 1 in {
4332 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4333 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4335 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4336 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4337 (ins _.ScalarMemOp:$src), OpcodeStr,
4338 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4340 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4345 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4346 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4347 EVEX_V512, EVEX_CD8<32, CD8VF>;
4348 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4349 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4351 // Define only if AVX512VL feature is present.
4352 let Predicates = [HasVLX] in {
4353 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4354 OpNode, v4f32x_info>,
4355 EVEX_V128, EVEX_CD8<32, CD8VF>;
4356 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4357 OpNode, v8f32x_info>,
4358 EVEX_V256, EVEX_CD8<32, CD8VF>;
4359 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4360 OpNode, v2f64x_info>,
4361 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4362 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4363 OpNode, v4f64x_info>,
4364 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4368 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4369 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4371 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4372 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4373 (VRSQRT14PSZr VR512:$src)>;
4374 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4375 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4376 (VRSQRT14PDZr VR512:$src)>;
4378 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4379 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4380 (VRCP14PSZr VR512:$src)>;
4381 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4382 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4383 (VRCP14PDZr VR512:$src)>;
4385 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4386 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4389 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4390 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4391 "$src2, $src1", "$src1, $src2",
4392 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4393 (i32 FROUND_CURRENT))>;
4395 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4396 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4397 "$src2, $src1", "$src1, $src2",
4398 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4399 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4401 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4402 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4403 "$src2, $src1", "$src1, $src2",
4404 (OpNode (_.VT _.RC:$src1),
4405 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4406 (i32 FROUND_CURRENT))>;
4409 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4410 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4411 EVEX_CD8<32, CD8VT1>;
4412 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4413 EVEX_CD8<64, CD8VT1>, VEX_W;
4416 let hasSideEffects = 0, Predicates = [HasERI] in {
4417 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4418 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4420 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4422 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4425 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4426 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4427 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4429 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4430 (ins _.RC:$src), OpcodeStr,
4432 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4435 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4436 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4438 (bitconvert (_.LdFrag addr:$src))),
4439 (i32 FROUND_CURRENT))>;
4441 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4442 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4444 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4445 (i32 FROUND_CURRENT))>, EVEX_B;
4448 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4449 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4450 EVEX_CD8<32, CD8VF>;
4451 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4452 VEX_W, EVEX_CD8<32, CD8VF>;
4455 let Predicates = [HasERI], hasSideEffects = 0 in {
4457 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4458 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4459 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4462 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4463 SDNode OpNode, X86VectorVTInfo _>{
4464 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4465 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4466 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4467 let mayLoad = 1 in {
4468 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4469 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4471 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4473 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4474 (ins _.ScalarMemOp:$src), OpcodeStr,
4475 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4477 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4482 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4483 Intrinsic F32Int, Intrinsic F64Int,
4484 OpndItins itins_s, OpndItins itins_d> {
4485 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4486 (ins FR32X:$src1, FR32X:$src2),
4487 !strconcat(OpcodeStr,
4488 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4489 [], itins_s.rr>, XS, EVEX_4V;
4490 let isCodeGenOnly = 1 in
4491 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4492 (ins VR128X:$src1, VR128X:$src2),
4493 !strconcat(OpcodeStr,
4494 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4496 (F32Int VR128X:$src1, VR128X:$src2))],
4497 itins_s.rr>, XS, EVEX_4V;
4498 let mayLoad = 1 in {
4499 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4500 (ins FR32X:$src1, f32mem:$src2),
4501 !strconcat(OpcodeStr,
4502 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4503 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4504 let isCodeGenOnly = 1 in
4505 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4506 (ins VR128X:$src1, ssmem:$src2),
4507 !strconcat(OpcodeStr,
4508 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4510 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4511 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4513 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4514 (ins FR64X:$src1, FR64X:$src2),
4515 !strconcat(OpcodeStr,
4516 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4518 let isCodeGenOnly = 1 in
4519 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4520 (ins VR128X:$src1, VR128X:$src2),
4521 !strconcat(OpcodeStr,
4522 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4524 (F64Int VR128X:$src1, VR128X:$src2))],
4525 itins_s.rr>, XD, EVEX_4V, VEX_W;
4526 let mayLoad = 1 in {
4527 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4528 (ins FR64X:$src1, f64mem:$src2),
4529 !strconcat(OpcodeStr,
4530 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4531 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4532 let isCodeGenOnly = 1 in
4533 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4534 (ins VR128X:$src1, sdmem:$src2),
4535 !strconcat(OpcodeStr,
4536 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4538 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4539 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4543 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4545 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4547 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4548 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4550 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4551 // Define only if AVX512VL feature is present.
4552 let Predicates = [HasVLX] in {
4553 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4554 OpNode, v4f32x_info>,
4555 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4556 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4557 OpNode, v8f32x_info>,
4558 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4559 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4560 OpNode, v2f64x_info>,
4561 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4562 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4563 OpNode, v4f64x_info>,
4564 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4568 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4570 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4571 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4572 SSE_SQRTSS, SSE_SQRTSD>;
4574 let Predicates = [HasAVX512] in {
4575 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4576 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4577 (VSQRTPSZr VR512:$src1)>;
4578 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4579 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4580 (VSQRTPDZr VR512:$src1)>;
4582 def : Pat<(f32 (fsqrt FR32X:$src)),
4583 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4584 def : Pat<(f32 (fsqrt (load addr:$src))),
4585 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4586 Requires<[OptForSize]>;
4587 def : Pat<(f64 (fsqrt FR64X:$src)),
4588 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4589 def : Pat<(f64 (fsqrt (load addr:$src))),
4590 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4591 Requires<[OptForSize]>;
4593 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4594 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4595 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4596 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4597 Requires<[OptForSize]>;
4599 def : Pat<(f32 (X86frcp FR32X:$src)),
4600 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4601 def : Pat<(f32 (X86frcp (load addr:$src))),
4602 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4603 Requires<[OptForSize]>;
4605 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4606 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4607 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4609 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4610 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4612 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4613 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4614 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4616 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4617 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4621 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4622 X86MemOperand x86memop, RegisterClass RC,
4623 PatFrag mem_frag, Domain d> {
4624 let ExeDomain = d in {
4625 // Intrinsic operation, reg.
4626 // Vector intrinsic operation, reg
4627 def r : AVX512AIi8<opc, MRMSrcReg,
4628 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
4629 !strconcat(OpcodeStr,
4630 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4633 // Vector intrinsic operation, mem
4634 def m : AVX512AIi8<opc, MRMSrcMem,
4635 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
4636 !strconcat(OpcodeStr,
4637 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4642 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4643 loadv16f32, SSEPackedSingle>, EVEX_V512,
4644 EVEX_CD8<32, CD8VF>;
4646 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4647 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4649 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4652 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4653 loadv8f64, SSEPackedDouble>, EVEX_V512,
4654 VEX_W, EVEX_CD8<64, CD8VF>;
4656 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4657 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4659 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4662 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
4664 let ExeDomain = _.ExeDomain in {
4665 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4666 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
4667 "$src3, $src2, $src1", "$src1, $src2, $src3",
4668 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4669 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
4671 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4672 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
4673 "$src3, $src2, $src1", "$src1, $src2, $src3",
4674 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4675 (i32 imm:$src3), (i32 FROUND_NO_EXC))), "{sae}">, EVEX_B;
4678 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4679 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
4680 "$src3, $src2, $src1", "$src1, $src2, $src3",
4681 (_.VT (X86RndScale (_.VT _.RC:$src1),
4682 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4683 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
4685 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
4686 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4687 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
4688 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
4689 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4690 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
4691 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
4692 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4693 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
4694 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
4695 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4696 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
4697 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
4698 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4699 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
4701 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4702 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4703 addr:$src, (i32 0x1))), _.FRC)>;
4704 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4705 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4706 addr:$src, (i32 0x2))), _.FRC)>;
4707 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4708 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4709 addr:$src, (i32 0x3))), _.FRC)>;
4710 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4711 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4712 addr:$src, (i32 0x4))), _.FRC)>;
4713 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4714 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4715 addr:$src, (i32 0xc))), _.FRC)>;
4718 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
4719 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4721 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
4722 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
4724 def : Pat<(v16f32 (ffloor VR512:$src)),
4725 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4726 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4727 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4728 def : Pat<(v16f32 (fceil VR512:$src)),
4729 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4730 def : Pat<(v16f32 (frint VR512:$src)),
4731 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4732 def : Pat<(v16f32 (ftrunc VR512:$src)),
4733 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4735 def : Pat<(v8f64 (ffloor VR512:$src)),
4736 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4737 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4738 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4739 def : Pat<(v8f64 (fceil VR512:$src)),
4740 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4741 def : Pat<(v8f64 (frint VR512:$src)),
4742 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4743 def : Pat<(v8f64 (ftrunc VR512:$src)),
4744 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4746 //-------------------------------------------------
4747 // Integer truncate and extend operations
4748 //-------------------------------------------------
4750 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4751 RegisterClass dstRC, RegisterClass srcRC,
4752 RegisterClass KRC, X86MemOperand x86memop> {
4753 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4755 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4758 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4759 (ins KRC:$mask, srcRC:$src),
4760 !strconcat(OpcodeStr,
4761 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4764 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4765 (ins KRC:$mask, srcRC:$src),
4766 !strconcat(OpcodeStr,
4767 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4770 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4771 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4774 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4775 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4776 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4780 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4781 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4782 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4783 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4784 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4785 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4786 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4787 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4788 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4789 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4790 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4791 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4792 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4793 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4794 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4795 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4796 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4797 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4798 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4799 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4800 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4801 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4802 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4803 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4804 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4805 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4806 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4807 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4808 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4809 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4811 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4812 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4813 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4814 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4815 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4817 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4818 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4819 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4820 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4821 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4822 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4823 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4824 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4827 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4828 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4829 PatFrag mem_frag, X86MemOperand x86memop,
4830 ValueType OpVT, ValueType InVT> {
4832 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4834 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4835 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4837 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4838 (ins KRC:$mask, SrcRC:$src),
4839 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4842 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4843 (ins KRC:$mask, SrcRC:$src),
4844 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4847 let mayLoad = 1 in {
4848 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4849 (ins x86memop:$src),
4850 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4852 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4855 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4856 (ins KRC:$mask, x86memop:$src),
4857 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4861 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4862 (ins KRC:$mask, x86memop:$src),
4863 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4869 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4870 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4872 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4873 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4875 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4876 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4877 EVEX_CD8<16, CD8VH>;
4878 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4879 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4880 EVEX_CD8<16, CD8VQ>;
4881 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4882 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4883 EVEX_CD8<32, CD8VH>;
4885 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4886 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4888 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4889 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4891 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4892 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4893 EVEX_CD8<16, CD8VH>;
4894 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4895 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4896 EVEX_CD8<16, CD8VQ>;
4897 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4898 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4899 EVEX_CD8<32, CD8VH>;
4901 //===----------------------------------------------------------------------===//
4902 // GATHER - SCATTER Operations
4904 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4905 RegisterClass RC, X86MemOperand memop> {
4907 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4908 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4909 (ins RC:$src1, KRC:$mask, memop:$src2),
4910 !strconcat(OpcodeStr,
4911 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4915 let ExeDomain = SSEPackedDouble in {
4916 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4917 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4918 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4919 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4922 let ExeDomain = SSEPackedSingle in {
4923 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4924 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4925 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4926 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4929 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4930 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4931 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4932 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4934 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4935 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4936 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4937 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4939 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4940 RegisterClass RC, X86MemOperand memop> {
4941 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4942 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4943 (ins memop:$dst, KRC:$mask, RC:$src2),
4944 !strconcat(OpcodeStr,
4945 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4949 let ExeDomain = SSEPackedDouble in {
4950 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4951 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4952 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4953 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4956 let ExeDomain = SSEPackedSingle in {
4957 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4958 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4959 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4960 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4963 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4964 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4965 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4966 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4968 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4969 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4970 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4971 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4974 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4975 RegisterClass KRC, X86MemOperand memop> {
4976 let Predicates = [HasPFI], hasSideEffects = 1 in
4977 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4978 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4982 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4983 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4985 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4986 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4988 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4989 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4991 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4992 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4994 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4995 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4997 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4998 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5000 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5001 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5003 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5004 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5006 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5007 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5009 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5010 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5012 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5013 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5015 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5016 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5018 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5019 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5021 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5022 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5024 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5025 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5027 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5028 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5029 //===----------------------------------------------------------------------===//
5030 // VSHUFPS - VSHUFPD Operations
5032 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5033 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5035 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5036 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5037 !strconcat(OpcodeStr,
5038 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5039 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5040 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5041 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5042 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5043 (ins RC:$src1, RC:$src2, u8imm:$src3),
5044 !strconcat(OpcodeStr,
5045 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5046 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5047 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5048 EVEX_4V, Sched<[WriteShuffle]>;
5051 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5052 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5053 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5054 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5056 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5057 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5058 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5059 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5060 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5062 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5063 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5064 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5065 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5066 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5068 multiclass avx512_valign<X86VectorVTInfo _> {
5069 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5070 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5072 "$src3, $src2, $src1", "$src1, $src2, $src3",
5073 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5075 AVX512AIi8Base, EVEX_4V;
5077 // Also match valign of packed floats.
5078 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5079 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5082 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5083 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5084 !strconcat("valign"##_.Suffix,
5085 "\t{$src3, $src2, $src1, $dst|"
5086 "$dst, $src1, $src2, $src3}"),
5089 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5090 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5092 // Helper fragments to match sext vXi1 to vXiY.
5093 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5094 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5096 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5097 RegisterClass KRC, RegisterClass RC,
5098 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5100 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5101 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5103 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5104 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5106 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5107 !strconcat(OpcodeStr,
5108 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5110 let mayLoad = 1 in {
5111 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5112 (ins x86memop:$src),
5113 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5115 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5116 (ins KRC:$mask, x86memop:$src),
5117 !strconcat(OpcodeStr,
5118 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5120 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5121 (ins KRC:$mask, x86memop:$src),
5122 !strconcat(OpcodeStr,
5123 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5125 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5126 (ins x86scalar_mop:$src),
5127 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5128 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5130 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5131 (ins KRC:$mask, x86scalar_mop:$src),
5132 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5133 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5134 []>, EVEX, EVEX_B, EVEX_K;
5135 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5136 (ins KRC:$mask, x86scalar_mop:$src),
5137 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5138 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5140 []>, EVEX, EVEX_B, EVEX_KZ;
5144 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5145 i512mem, i32mem, "{1to16}">, EVEX_V512,
5146 EVEX_CD8<32, CD8VF>;
5147 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5148 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5149 EVEX_CD8<64, CD8VF>;
5152 (bc_v16i32 (v16i1sextv16i32)),
5153 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5154 (VPABSDZrr VR512:$src)>;
5156 (bc_v8i64 (v8i1sextv8i64)),
5157 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5158 (VPABSQZrr VR512:$src)>;
5160 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5161 (v16i32 immAllZerosV), (i16 -1))),
5162 (VPABSDZrr VR512:$src)>;
5163 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5164 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5165 (VPABSQZrr VR512:$src)>;
5167 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5168 RegisterClass RC, RegisterClass KRC,
5169 X86MemOperand x86memop,
5170 X86MemOperand x86scalar_mop, string BrdcstStr> {
5171 let hasSideEffects = 0 in {
5172 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5174 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5177 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5178 (ins x86memop:$src),
5179 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5182 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5183 (ins x86scalar_mop:$src),
5184 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5185 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5187 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5188 (ins KRC:$mask, RC:$src),
5189 !strconcat(OpcodeStr,
5190 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5193 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5194 (ins KRC:$mask, x86memop:$src),
5195 !strconcat(OpcodeStr,
5196 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5199 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5200 (ins KRC:$mask, x86scalar_mop:$src),
5201 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5202 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5204 []>, EVEX, EVEX_KZ, EVEX_B;
5206 let Constraints = "$src1 = $dst" in {
5207 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5208 (ins RC:$src1, KRC:$mask, RC:$src2),
5209 !strconcat(OpcodeStr,
5210 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5213 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5214 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5215 !strconcat(OpcodeStr,
5216 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5219 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5220 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5221 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5222 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5223 []>, EVEX, EVEX_K, EVEX_B;
5228 let Predicates = [HasCDI] in {
5229 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5230 i512mem, i32mem, "{1to16}">,
5231 EVEX_V512, EVEX_CD8<32, CD8VF>;
5234 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5235 i512mem, i64mem, "{1to8}">,
5236 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5240 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5242 (VPCONFLICTDrrk VR512:$src1,
5243 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5245 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5247 (VPCONFLICTQrrk VR512:$src1,
5248 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5250 let Predicates = [HasCDI] in {
5251 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5252 i512mem, i32mem, "{1to16}">,
5253 EVEX_V512, EVEX_CD8<32, CD8VF>;
5256 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5257 i512mem, i64mem, "{1to8}">,
5258 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5262 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5264 (VPLZCNTDrrk VR512:$src1,
5265 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5267 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5269 (VPLZCNTQrrk VR512:$src1,
5270 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5272 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5273 (VPLZCNTDrm addr:$src)>;
5274 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5275 (VPLZCNTDrr VR512:$src)>;
5276 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5277 (VPLZCNTQrm addr:$src)>;
5278 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5279 (VPLZCNTQrr VR512:$src)>;
5281 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5282 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5283 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5285 def : Pat<(store VK1:$src, addr:$dst),
5287 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5288 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5290 def : Pat<(store VK8:$src, addr:$dst),
5292 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5293 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5295 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5296 (truncstore node:$val, node:$ptr), [{
5297 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5300 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5301 (MOV8mr addr:$dst, GR8:$src)>;
5303 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5304 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5305 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5306 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5309 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5310 string OpcodeStr, Predicate prd> {
5311 let Predicates = [prd] in
5312 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5314 let Predicates = [prd, HasVLX] in {
5315 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5316 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5320 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5321 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5323 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5325 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5327 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5331 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5333 //===----------------------------------------------------------------------===//
5334 // AVX-512 - COMPRESS and EXPAND
5336 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5338 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5339 (ins _.KRCWM:$mask, _.RC:$src),
5340 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5341 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5342 _.ImmAllZerosV)))]>, EVEX_KZ;
5344 let Constraints = "$src0 = $dst" in
5345 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5346 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5347 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5348 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5349 _.RC:$src0)))]>, EVEX_K;
5351 let mayStore = 1 in {
5352 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5353 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5354 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5355 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5357 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5361 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5362 AVX512VLVectorVTInfo VTInfo> {
5363 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5365 let Predicates = [HasVLX] in {
5366 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5367 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5371 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5373 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5375 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5377 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5381 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5383 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5384 (ins _.KRCWM:$mask, _.RC:$src),
5385 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5386 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5387 _.ImmAllZerosV)))]>, EVEX_KZ;
5389 let Constraints = "$src0 = $dst" in
5390 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5391 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5392 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5393 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5394 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5396 let mayLoad = 1, Constraints = "$src0 = $dst" in
5397 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5398 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5399 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5400 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5402 (_.LdFrag addr:$src))),
5404 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5407 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5408 (ins _.KRCWM:$mask, _.MemOp:$src),
5409 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5410 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5411 (_.VT (bitconvert (_.LdFrag addr:$src))),
5412 _.ImmAllZerosV)))]>,
5413 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5417 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5418 AVX512VLVectorVTInfo VTInfo> {
5419 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5421 let Predicates = [HasVLX] in {
5422 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5423 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5427 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5429 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5431 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5433 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,