1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
9 ValueType EltVT = eltvt;
10 int NumElts = numelts;
12 // Corresponding mask register class.
13 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
15 // Corresponding write-mask register class.
16 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
18 // The GPR register class that can hold the write mask. Use GR8 for fewer
19 // than 8 elements. Use shift-right and equal to work around the lack of
22 !cast<RegisterClass>("GR" #
23 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
25 // Suffix used in the instruction mnemonic.
26 string Suffix = suffix;
28 // VTName is a string name for vector VT. For vector types it will be
29 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
30 // It is a little bit complex for scalar types, where NumElts = 1.
31 // In this case we build v4f32 or v2f64
32 string VTName = "v" # !if (!eq (NumElts, 1),
33 !if (!eq (EltVT.Size, 32), 4,
34 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
37 ValueType VT = !cast<ValueType>(VTName);
39 string EltTypeName = !cast<string>(EltVT);
40 // Size of the element type in bits, e.g. 32 for v16i32.
41 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
42 int EltSize = EltVT.Size;
44 // "i" for integer types and "f" for floating-point types
45 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
47 // Size of RC in bits, e.g. 512 for VR512.
50 // The corresponding memory operand, e.g. i512mem for VR512.
51 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
52 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
55 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
56 // due to load promotion during legalization
57 PatFrag LdFrag = !cast<PatFrag>("load" #
58 !if (!eq (TypeVariantName, "i"),
59 !if (!eq (Size, 128), "v2i64",
60 !if (!eq (Size, 256), "v4i64",
62 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
64 // Load patterns used for memory operands. We only have this defined in
65 // case of i64 element types for sub-512 integer vectors. For now, keep
66 // MemOpFrag undefined in these cases.
68 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
69 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
70 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
71 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
72 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
74 // The corresponding float type, e.g. v16f32 for v16i32
75 // Note: For EltSize < 32, FloatVT is illegal and TableGen
76 // fails to compile, so we choose FloatVT = VT
77 ValueType FloatVT = !cast<ValueType>(
78 !if (!eq (!srl(EltSize,5),0),
80 !if (!eq(TypeVariantName, "i"),
81 "v" # NumElts # "f" # EltSize,
84 // The string to specify embedded broadcast in assembly.
85 string BroadcastStr = "{1to" # NumElts # "}";
87 // 8-bit compressed displacement tuple/subvector format. This is only
88 // defined for NumElts <= 8.
89 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
90 !cast<CD8VForm>("CD8VT" # NumElts), ?);
92 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
93 !if (!eq (Size, 256), sub_ymm, ?));
95 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
96 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
99 // A vector type of the same width with element type i32. This is used to
100 // create the canonical constant zero node ImmAllZerosV.
101 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
102 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
105 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
106 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
107 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
108 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
109 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
110 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
112 // "x" in v32i8x_info means RC = VR256X
113 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
114 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
115 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
116 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
117 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
118 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
120 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
121 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
122 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
123 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
124 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
125 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
127 // We map scalar types to the smallest (128-bit) vector type
128 // with the appropriate element type. This allows to use the same masking logic.
129 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
130 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
132 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
133 X86VectorVTInfo i128> {
134 X86VectorVTInfo info512 = i512;
135 X86VectorVTInfo info256 = i256;
136 X86VectorVTInfo info128 = i128;
139 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
141 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
143 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
145 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
147 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
149 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
152 // This multiclass generates the masking variants from the non-masking
153 // variant. It only provides the assembly pieces for the masking variants.
154 // It assumes custom ISel patterns for masking which can be provided as
155 // template arguments.
156 multiclass AVX512_maskable_custom<bits<8> O, Format F,
158 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
160 string AttSrcAsm, string IntelSrcAsm,
162 list<dag> MaskingPattern,
163 list<dag> ZeroMaskingPattern,
165 string MaskingConstraint = "",
166 InstrItinClass itin = NoItinerary,
167 bit IsCommutable = 0> {
168 let isCommutable = IsCommutable in
169 def NAME: AVX512<O, F, Outs, Ins,
170 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
171 "$dst "#Round#", "#IntelSrcAsm#"}",
174 // Prefer over VMOV*rrk Pat<>
175 let AddedComplexity = 20 in
176 def NAME#k: AVX512<O, F, Outs, MaskingIns,
177 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
178 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
179 MaskingPattern, itin>,
181 // In case of the 3src subclass this is overridden with a let.
182 string Constraints = MaskingConstraint;
184 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
185 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
186 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
187 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
194 // Common base class of AVX512_maskable and AVX512_maskable_3src.
195 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
197 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
199 string AttSrcAsm, string IntelSrcAsm,
200 dag RHS, dag MaskingRHS,
201 SDNode Select = vselect, string Round = "",
202 string MaskingConstraint = "",
203 InstrItinClass itin = NoItinerary,
204 bit IsCommutable = 0> :
205 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
206 AttSrcAsm, IntelSrcAsm,
207 [(set _.RC:$dst, RHS)],
208 [(set _.RC:$dst, MaskingRHS)],
210 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
211 Round, MaskingConstraint, NoItinerary, IsCommutable>;
213 // This multiclass generates the unconditional/non-masking, the masking and
214 // the zero-masking variant of the vector instruction. In the masking case, the
215 // perserved vector elements come from a new dummy input operand tied to $dst.
216 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Outs, dag Ins, string OpcodeStr,
218 string AttSrcAsm, string IntelSrcAsm,
219 dag RHS, string Round = "",
220 InstrItinClass itin = NoItinerary,
221 bit IsCommutable = 0> :
222 AVX512_maskable_common<O, F, _, Outs, Ins,
223 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
224 !con((ins _.KRCWM:$mask), Ins),
225 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
226 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
227 Round, "$src0 = $dst", itin, IsCommutable>;
229 // This multiclass generates the unconditional/non-masking, the masking and
230 // the zero-masking variant of the scalar instruction.
231 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
232 dag Outs, dag Ins, string OpcodeStr,
233 string AttSrcAsm, string IntelSrcAsm,
234 dag RHS, string Round = "",
235 InstrItinClass itin = NoItinerary,
236 bit IsCommutable = 0> :
237 AVX512_maskable_common<O, F, _, Outs, Ins,
238 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
239 !con((ins _.KRCWM:$mask), Ins),
240 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
241 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
242 Round, "$src0 = $dst", itin, IsCommutable>;
244 // Similar to AVX512_maskable but in this case one of the source operands
245 // ($src1) is already tied to $dst so we just use that for the preserved
246 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
248 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
249 dag Outs, dag NonTiedIns, string OpcodeStr,
250 string AttSrcAsm, string IntelSrcAsm,
252 AVX512_maskable_common<O, F, _, Outs,
253 !con((ins _.RC:$src1), NonTiedIns),
254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
255 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
256 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
257 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
260 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
263 string AttSrcAsm, string IntelSrcAsm,
265 AVX512_maskable_custom<O, F, Outs, Ins,
266 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
267 !con((ins _.KRCWM:$mask), Ins),
268 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
271 // Bitcasts between 512-bit vector types. Return the original type since
272 // no instruction is needed for the conversion
273 let Predicates = [HasAVX512] in {
274 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
275 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
276 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
277 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
278 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
279 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
280 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
281 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
282 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
283 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
284 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
285 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
286 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
287 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
288 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
289 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
290 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
291 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
292 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
293 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
296 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
297 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
299 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
300 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
302 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
303 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
304 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
306 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
307 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
308 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
309 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
310 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
311 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
312 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
313 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
314 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
315 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
316 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
317 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
318 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
319 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
320 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
321 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
322 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
323 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
324 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
325 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
326 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
327 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
328 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
329 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
330 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
331 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
332 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
333 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
334 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
335 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
337 // Bitcasts between 256-bit vector types. Return the original type since
338 // no instruction is needed for the conversion
339 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
340 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
341 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
342 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
343 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
344 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
346 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
347 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
348 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
350 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
351 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
352 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
353 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
355 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
357 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
358 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
359 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
360 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
361 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
363 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
365 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
367 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
368 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
372 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
375 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
376 isPseudo = 1, Predicates = [HasAVX512] in {
377 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
378 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
381 let Predicates = [HasAVX512] in {
382 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
383 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
384 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
387 //===----------------------------------------------------------------------===//
388 // AVX-512 - VECTOR INSERT
391 multiclass vinsert_for_size_no_alt<int Opcode,
392 X86VectorVTInfo From, X86VectorVTInfo To,
393 PatFrag vinsert_insert,
394 SDNodeXForm INSERT_get_vinsert_imm> {
395 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
396 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
397 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
398 "vinsert" # From.EltTypeName # "x" # From.NumElts #
399 "\t{$src3, $src2, $src1, $dst|"
400 "$dst, $src1, $src2, $src3}",
401 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
402 (From.VT From.RC:$src2),
407 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
408 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
409 "vinsert" # From.EltTypeName # "x" # From.NumElts #
410 "\t{$src3, $src2, $src1, $dst|"
411 "$dst, $src1, $src2, $src3}",
413 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
417 multiclass vinsert_for_size<int Opcode,
418 X86VectorVTInfo From, X86VectorVTInfo To,
419 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
420 PatFrag vinsert_insert,
421 SDNodeXForm INSERT_get_vinsert_imm> :
422 vinsert_for_size_no_alt<Opcode, From, To,
423 vinsert_insert, INSERT_get_vinsert_imm> {
424 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
425 // vinserti32x4. Only add this if 64x2 and friends are not supported
426 // natively via AVX512DQ.
427 let Predicates = [NoDQI] in
428 def : Pat<(vinsert_insert:$ins
429 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
430 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
431 VR512:$src1, From.RC:$src2,
432 (INSERT_get_vinsert_imm VR512:$ins)))>;
435 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
436 ValueType EltVT64, int Opcode256> {
437 defm NAME # "32x4" : vinsert_for_size<Opcode128,
438 X86VectorVTInfo< 4, EltVT32, VR128X>,
439 X86VectorVTInfo<16, EltVT32, VR512>,
440 X86VectorVTInfo< 2, EltVT64, VR128X>,
441 X86VectorVTInfo< 8, EltVT64, VR512>,
443 INSERT_get_vinsert128_imm>;
444 let Predicates = [HasDQI] in
445 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
446 X86VectorVTInfo< 2, EltVT64, VR128X>,
447 X86VectorVTInfo< 8, EltVT64, VR512>,
449 INSERT_get_vinsert128_imm>, VEX_W;
450 defm NAME # "64x4" : vinsert_for_size<Opcode256,
451 X86VectorVTInfo< 4, EltVT64, VR256X>,
452 X86VectorVTInfo< 8, EltVT64, VR512>,
453 X86VectorVTInfo< 8, EltVT32, VR256>,
454 X86VectorVTInfo<16, EltVT32, VR512>,
456 INSERT_get_vinsert256_imm>, VEX_W;
457 let Predicates = [HasDQI] in
458 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
459 X86VectorVTInfo< 8, EltVT32, VR256X>,
460 X86VectorVTInfo<16, EltVT32, VR512>,
462 INSERT_get_vinsert256_imm>;
465 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
466 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
468 // vinsertps - insert f32 to XMM
469 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
470 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
471 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
472 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
474 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
475 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
476 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
477 [(set VR128X:$dst, (X86insertps VR128X:$src1,
478 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
479 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
481 //===----------------------------------------------------------------------===//
482 // AVX-512 VECTOR EXTRACT
485 multiclass vextract_for_size<int Opcode,
486 X86VectorVTInfo From, X86VectorVTInfo To,
487 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
488 PatFrag vextract_extract,
489 SDNodeXForm EXTRACT_get_vextract_imm> {
490 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
491 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
492 (ins VR512:$src1, i8imm:$idx),
493 "vextract" # To.EltTypeName # "x4",
494 "$idx, $src1", "$src1, $idx",
495 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
497 AVX512AIi8Base, EVEX, EVEX_V512;
499 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
500 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
501 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
502 "$dst, $src1, $src2}",
503 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
506 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
508 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
509 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
511 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
513 // A 128/256-bit subvector extract from the first 512-bit vector position is
514 // a subregister copy that needs no instruction.
515 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
517 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
519 // And for the alternative types.
520 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
522 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
524 // Intrinsic call with masking.
525 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
527 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
528 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
529 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
530 VR512:$src1, imm:$idx)>;
532 // Intrinsic call with zero-masking.
533 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
535 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
536 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
537 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
538 VR512:$src1, imm:$idx)>;
540 // Intrinsic call without masking.
541 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
543 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
544 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
545 VR512:$src1, imm:$idx)>;
548 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
549 ValueType EltVT64, int Opcode64> {
550 defm NAME # "32x4" : vextract_for_size<Opcode32,
551 X86VectorVTInfo<16, EltVT32, VR512>,
552 X86VectorVTInfo< 4, EltVT32, VR128X>,
553 X86VectorVTInfo< 8, EltVT64, VR512>,
554 X86VectorVTInfo< 2, EltVT64, VR128X>,
556 EXTRACT_get_vextract128_imm>;
557 defm NAME # "64x4" : vextract_for_size<Opcode64,
558 X86VectorVTInfo< 8, EltVT64, VR512>,
559 X86VectorVTInfo< 4, EltVT64, VR256X>,
560 X86VectorVTInfo<16, EltVT32, VR512>,
561 X86VectorVTInfo< 8, EltVT32, VR256>,
563 EXTRACT_get_vextract256_imm>, VEX_W;
566 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
567 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
569 // A 128-bit subvector insert to the first 512-bit vector position
570 // is a subregister copy that needs no instruction.
571 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
572 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
573 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
575 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
576 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
577 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
579 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
580 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
581 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
583 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
584 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
585 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
588 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
589 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
590 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
591 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
592 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
593 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
594 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
595 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
597 // vextractps - extract 32 bits from XMM
598 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
599 (ins VR128X:$src1, i32i8imm:$src2),
600 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
601 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
604 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
605 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
606 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
607 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
608 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
610 //===---------------------------------------------------------------------===//
613 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
614 ValueType svt, X86VectorVTInfo _> {
615 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
616 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
617 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
621 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
622 (ins _.ScalarMemOp:$src),
623 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
624 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
629 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
630 AVX512VLVectorVTInfo _> {
631 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
634 let Predicates = [HasVLX] in {
635 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
640 let ExeDomain = SSEPackedSingle in {
641 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
642 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
643 let Predicates = [HasVLX] in {
644 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
645 v4f32, v4f32x_info>, EVEX_V128,
646 EVEX_CD8<32, CD8VT1>;
650 let ExeDomain = SSEPackedDouble in {
651 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
652 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
655 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
656 // Later, we can canonize broadcast instructions before ISel phase and
657 // eliminate additional patterns on ISel.
658 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
659 // representations of source
660 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
661 X86VectorVTInfo _, RegisterClass SrcRC_v,
662 RegisterClass SrcRC_s> {
663 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
664 (!cast<Instruction>(InstName##"r")
665 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
667 let AddedComplexity = 30 in {
668 def : Pat<(_.VT (vselect _.KRCWM:$mask,
669 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
670 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
671 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
673 def : Pat<(_.VT(vselect _.KRCWM:$mask,
674 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
675 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
676 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
680 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
682 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
685 let Predicates = [HasVLX] in {
686 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
687 v8f32x_info, VR128X, FR32X>;
688 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
689 v4f32x_info, VR128X, FR32X>;
690 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
691 v4f64x_info, VR128X, FR64X>;
694 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
695 (VBROADCASTSSZm addr:$src)>;
696 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
697 (VBROADCASTSDZm addr:$src)>;
699 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
700 (VBROADCASTSSZm addr:$src)>;
701 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
702 (VBROADCASTSDZm addr:$src)>;
704 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
705 RegisterClass SrcRC> {
706 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
707 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
708 "$src", "$src", []>, T8PD, EVEX;
711 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
712 RegisterClass SrcRC, Predicate prd> {
713 let Predicates = [prd] in
714 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
715 let Predicates = [prd, HasVLX] in {
716 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
717 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
721 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
723 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
725 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
727 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
730 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
731 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
733 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
734 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
736 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
737 (VPBROADCASTDrZr GR32:$src)>;
738 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
739 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
740 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
741 (VPBROADCASTQrZr GR64:$src)>;
742 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
743 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
745 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
746 (VPBROADCASTDrZr GR32:$src)>;
747 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
748 (VPBROADCASTQrZr GR64:$src)>;
750 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
751 (v16i32 immAllZerosV), (i16 GR16:$mask))),
752 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
753 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
754 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
755 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
757 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
758 X86MemOperand x86memop, PatFrag ld_frag,
759 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
761 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
764 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
765 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
767 !strconcat(OpcodeStr,
768 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
770 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
773 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
774 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
776 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
777 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
779 !strconcat(OpcodeStr,
780 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
781 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
782 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
786 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
787 loadi32, VR512, v16i32, v4i32, VK16WM>,
788 EVEX_V512, EVEX_CD8<32, CD8VT1>;
789 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
790 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
791 EVEX_CD8<64, CD8VT1>;
793 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
794 X86MemOperand x86memop, PatFrag ld_frag,
797 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
800 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
802 !strconcat(OpcodeStr,
803 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
808 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
809 i128mem, loadv2i64, VK16WM>,
810 EVEX_V512, EVEX_CD8<32, CD8VT4>;
811 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
812 i256mem, loadv4i64, VK16WM>, VEX_W,
813 EVEX_V512, EVEX_CD8<64, CD8VT4>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
816 (VPBROADCASTDZrr VR128X:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
818 (VPBROADCASTQZrr VR128X:$src)>;
820 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
821 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
822 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
823 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
825 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
826 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
827 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
828 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
830 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
831 (VBROADCASTSSZr VR128X:$src)>;
832 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
833 (VBROADCASTSDZr VR128X:$src)>;
835 // Provide fallback in case the load node that is used in the patterns above
836 // is used by additional users, which prevents the pattern selection.
837 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
838 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
839 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
840 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
843 let Predicates = [HasAVX512] in {
844 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
846 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
847 addr:$src)), sub_ymm)>;
849 //===----------------------------------------------------------------------===//
850 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
853 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
855 let Predicates = [HasCDI] in
856 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
858 []>, EVEX, EVEX_V512;
860 let Predicates = [HasCDI, HasVLX] in {
861 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
862 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
863 []>, EVEX, EVEX_V128;
864 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
865 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
866 []>, EVEX, EVEX_V256;
870 let Predicates = [HasCDI] in {
871 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
873 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
877 //===----------------------------------------------------------------------===//
880 // -- immediate form --
881 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
883 let ExeDomain = _.ExeDomain in {
884 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
885 (ins _.RC:$src1, i8imm:$src2),
886 !strconcat(OpcodeStr,
887 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
889 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
891 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
892 (ins _.MemOp:$src1, i8imm:$src2),
893 !strconcat(OpcodeStr,
894 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
896 (_.VT (OpNode (_.MemOpFrag addr:$src1),
898 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
902 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
903 X86VectorVTInfo Ctrl> :
904 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
905 let ExeDomain = _.ExeDomain in {
906 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
907 (ins _.RC:$src1, _.RC:$src2),
908 !strconcat("vpermil" # _.Suffix,
909 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
911 (_.VT (X86VPermilpv _.RC:$src1,
912 (Ctrl.VT Ctrl.RC:$src2))))]>,
914 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
915 (ins _.RC:$src1, Ctrl.MemOp:$src2),
916 !strconcat("vpermil" # _.Suffix,
917 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
919 (_.VT (X86VPermilpv _.RC:$src1,
920 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
925 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
927 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
930 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
932 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
935 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
936 (VPERMILPSZri VR512:$src1, imm:$imm)>;
937 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
938 (VPERMILPDZri VR512:$src1, imm:$imm)>;
940 // -- VPERM - register form --
941 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
942 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
944 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
945 (ins RC:$src1, RC:$src2),
946 !strconcat(OpcodeStr,
947 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
949 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
951 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
952 (ins RC:$src1, x86memop:$src2),
953 !strconcat(OpcodeStr,
954 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
956 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
960 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
961 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
962 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
963 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
964 let ExeDomain = SSEPackedSingle in
965 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
966 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
967 let ExeDomain = SSEPackedDouble in
968 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
969 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
971 // -- VPERM2I - 3 source operands form --
972 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
973 PatFrag mem_frag, X86MemOperand x86memop,
974 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
975 let Constraints = "$src1 = $dst" in {
976 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
977 (ins RC:$src1, RC:$src2, RC:$src3),
978 !strconcat(OpcodeStr,
979 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
981 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
984 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
985 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
986 !strconcat(OpcodeStr,
987 "\t{$src3, $src2, $dst {${mask}}|"
988 "$dst {${mask}}, $src2, $src3}"),
989 [(set RC:$dst, (OpVT (vselect KRC:$mask,
990 (OpNode RC:$src1, RC:$src2,
995 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
996 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
997 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
998 !strconcat(OpcodeStr,
999 "\t{$src3, $src2, $dst {${mask}} {z} |",
1000 "$dst {${mask}} {z}, $src2, $src3}"),
1001 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1002 (OpNode RC:$src1, RC:$src2,
1005 (v16i32 immAllZerosV))))))]>,
1008 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1009 (ins RC:$src1, RC:$src2, x86memop:$src3),
1010 !strconcat(OpcodeStr,
1011 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1013 (OpVT (OpNode RC:$src1, RC:$src2,
1014 (mem_frag addr:$src3))))]>, EVEX_4V;
1016 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1017 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1018 !strconcat(OpcodeStr,
1019 "\t{$src3, $src2, $dst {${mask}}|"
1020 "$dst {${mask}}, $src2, $src3}"),
1022 (OpVT (vselect KRC:$mask,
1023 (OpNode RC:$src1, RC:$src2,
1024 (mem_frag addr:$src3)),
1028 let AddedComplexity = 10 in // Prefer over the rrkz variant
1029 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1030 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1031 !strconcat(OpcodeStr,
1032 "\t{$src3, $src2, $dst {${mask}} {z}|"
1033 "$dst {${mask}} {z}, $src2, $src3}"),
1035 (OpVT (vselect KRC:$mask,
1036 (OpNode RC:$src1, RC:$src2,
1037 (mem_frag addr:$src3)),
1039 (v16i32 immAllZerosV))))))]>,
1043 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
1044 i512mem, X86VPermiv3, v16i32, VK16WM>,
1045 EVEX_V512, EVEX_CD8<32, CD8VF>;
1046 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
1047 i512mem, X86VPermiv3, v8i64, VK8WM>,
1048 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1049 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
1050 i512mem, X86VPermiv3, v16f32, VK16WM>,
1051 EVEX_V512, EVEX_CD8<32, CD8VF>;
1052 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
1053 i512mem, X86VPermiv3, v8f64, VK8WM>,
1054 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1056 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1057 PatFrag mem_frag, X86MemOperand x86memop,
1058 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1059 ValueType MaskVT, RegisterClass MRC> :
1060 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1062 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1063 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1064 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1066 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1067 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1068 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1069 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1072 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1073 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1074 EVEX_V512, EVEX_CD8<32, CD8VF>;
1075 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1076 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1077 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1078 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1079 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1080 EVEX_V512, EVEX_CD8<32, CD8VF>;
1081 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1082 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1083 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1085 //===----------------------------------------------------------------------===//
1086 // AVX-512 - BLEND using mask
1088 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1089 let ExeDomain = _.ExeDomain in {
1090 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1091 (ins _.RC:$src1, _.RC:$src2),
1092 !strconcat(OpcodeStr,
1093 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1095 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1096 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1097 !strconcat(OpcodeStr,
1098 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1099 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1100 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1101 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1102 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1103 !strconcat(OpcodeStr,
1104 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1105 []>, EVEX_4V, EVEX_KZ;
1106 let mayLoad = 1 in {
1107 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1108 (ins _.RC:$src1, _.MemOp:$src2),
1109 !strconcat(OpcodeStr,
1110 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1111 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1112 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1113 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1114 !strconcat(OpcodeStr,
1115 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1116 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1117 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1118 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1119 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1120 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1121 !strconcat(OpcodeStr,
1122 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1123 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1127 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1129 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1130 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1131 !strconcat(OpcodeStr,
1132 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1133 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1134 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1135 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1136 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1138 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1139 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1140 !strconcat(OpcodeStr,
1141 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1142 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1143 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1147 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1148 AVX512VLVectorVTInfo VTInfo> {
1149 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1150 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1152 let Predicates = [HasVLX] in {
1153 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1154 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1155 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1156 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1160 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1161 AVX512VLVectorVTInfo VTInfo> {
1162 let Predicates = [HasBWI] in
1163 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1165 let Predicates = [HasBWI, HasVLX] in {
1166 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1167 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1172 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1173 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1174 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1175 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1176 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1177 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1180 let Predicates = [HasAVX512] in {
1181 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1182 (v8f32 VR256X:$src2))),
1184 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1185 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1186 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1188 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1189 (v8i32 VR256X:$src2))),
1191 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1192 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1193 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1195 //===----------------------------------------------------------------------===//
1196 // Compare Instructions
1197 //===----------------------------------------------------------------------===//
1199 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1200 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1201 Operand CC, SDNode OpNode, ValueType VT,
1202 PatFrag ld_frag, string asm, string asm_alt> {
1203 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1204 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1205 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1206 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1207 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1208 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1209 [(set VK1:$dst, (OpNode (VT RC:$src1),
1210 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1211 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1212 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1213 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1214 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1215 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1216 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1217 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1221 let Predicates = [HasAVX512] in {
1222 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1223 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1224 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1226 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1227 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1228 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1232 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1233 X86VectorVTInfo _> {
1234 def rr : AVX512BI<opc, MRMSrcReg,
1235 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1236 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1237 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1238 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1240 def rm : AVX512BI<opc, MRMSrcMem,
1241 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1242 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1243 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1244 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1245 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1246 def rrk : AVX512BI<opc, MRMSrcReg,
1247 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1249 "$dst {${mask}}, $src1, $src2}"),
1250 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1251 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1252 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1254 def rmk : AVX512BI<opc, MRMSrcMem,
1255 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1257 "$dst {${mask}}, $src1, $src2}"),
1258 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1259 (OpNode (_.VT _.RC:$src1),
1261 (_.LdFrag addr:$src2))))))],
1262 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1265 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1266 X86VectorVTInfo _> :
1267 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1268 let mayLoad = 1 in {
1269 def rmb : AVX512BI<opc, MRMSrcMem,
1270 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1271 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1272 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1273 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1274 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1275 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1276 def rmbk : AVX512BI<opc, MRMSrcMem,
1277 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1278 _.ScalarMemOp:$src2),
1279 !strconcat(OpcodeStr,
1280 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1281 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1282 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1283 (OpNode (_.VT _.RC:$src1),
1285 (_.ScalarLdFrag addr:$src2)))))],
1286 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1290 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1291 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1292 let Predicates = [prd] in
1293 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1296 let Predicates = [prd, HasVLX] in {
1297 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1299 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1304 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1305 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1307 let Predicates = [prd] in
1308 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1311 let Predicates = [prd, HasVLX] in {
1312 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1314 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1319 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1320 avx512vl_i8_info, HasBWI>,
1323 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1324 avx512vl_i16_info, HasBWI>,
1325 EVEX_CD8<16, CD8VF>;
1327 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1328 avx512vl_i32_info, HasAVX512>,
1329 EVEX_CD8<32, CD8VF>;
1331 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1332 avx512vl_i64_info, HasAVX512>,
1333 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1335 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1336 avx512vl_i8_info, HasBWI>,
1339 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1340 avx512vl_i16_info, HasBWI>,
1341 EVEX_CD8<16, CD8VF>;
1343 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1344 avx512vl_i32_info, HasAVX512>,
1345 EVEX_CD8<32, CD8VF>;
1347 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1348 avx512vl_i64_info, HasAVX512>,
1349 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1351 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1352 (COPY_TO_REGCLASS (VPCMPGTDZrr
1353 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1354 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1356 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1357 (COPY_TO_REGCLASS (VPCMPEQDZrr
1358 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1359 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1361 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1362 X86VectorVTInfo _> {
1363 def rri : AVX512AIi8<opc, MRMSrcReg,
1364 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1365 !strconcat("vpcmp${cc}", Suffix,
1366 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1367 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1369 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1371 def rmi : AVX512AIi8<opc, MRMSrcMem,
1372 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1373 !strconcat("vpcmp${cc}", Suffix,
1374 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1375 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1376 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1378 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1379 def rrik : AVX512AIi8<opc, MRMSrcReg,
1380 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1382 !strconcat("vpcmp${cc}", Suffix,
1383 "\t{$src2, $src1, $dst {${mask}}|",
1384 "$dst {${mask}}, $src1, $src2}"),
1385 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1386 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1388 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1390 def rmik : AVX512AIi8<opc, MRMSrcMem,
1391 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1393 !strconcat("vpcmp${cc}", Suffix,
1394 "\t{$src2, $src1, $dst {${mask}}|",
1395 "$dst {${mask}}, $src1, $src2}"),
1396 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1397 (OpNode (_.VT _.RC:$src1),
1398 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1400 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1402 // Accept explicit immediate argument form instead of comparison code.
1403 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1404 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1405 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1406 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1407 "$dst, $src1, $src2, $cc}"),
1408 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1409 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1410 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1411 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1412 "$dst, $src1, $src2, $cc}"),
1413 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1414 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1415 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1417 !strconcat("vpcmp", Suffix,
1418 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1419 "$dst {${mask}}, $src1, $src2, $cc}"),
1420 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1421 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1422 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1424 !strconcat("vpcmp", Suffix,
1425 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1426 "$dst {${mask}}, $src1, $src2, $cc}"),
1427 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1431 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1432 X86VectorVTInfo _> :
1433 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1434 let mayLoad = 1 in {
1435 def rmib : AVX512AIi8<opc, MRMSrcMem,
1436 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1438 !strconcat("vpcmp${cc}", Suffix,
1439 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1440 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1441 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1442 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1444 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1445 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1446 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1447 _.ScalarMemOp:$src2, AVXCC:$cc),
1448 !strconcat("vpcmp${cc}", Suffix,
1449 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1450 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1451 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1452 (OpNode (_.VT _.RC:$src1),
1453 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1455 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1458 // Accept explicit immediate argument form instead of comparison code.
1459 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1460 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1461 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1463 !strconcat("vpcmp", Suffix,
1464 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1465 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1466 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1467 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1468 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1469 _.ScalarMemOp:$src2, i8imm:$cc),
1470 !strconcat("vpcmp", Suffix,
1471 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1472 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1473 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1477 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1478 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1479 let Predicates = [prd] in
1480 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1482 let Predicates = [prd, HasVLX] in {
1483 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1484 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1488 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1489 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1490 let Predicates = [prd] in
1491 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1494 let Predicates = [prd, HasVLX] in {
1495 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1497 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1502 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1503 HasBWI>, EVEX_CD8<8, CD8VF>;
1504 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1505 HasBWI>, EVEX_CD8<8, CD8VF>;
1507 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1508 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1509 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1510 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1512 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1513 HasAVX512>, EVEX_CD8<32, CD8VF>;
1514 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1515 HasAVX512>, EVEX_CD8<32, CD8VF>;
1517 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1518 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1519 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1520 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1522 // avx512_cmp_packed - compare packed instructions
1523 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1524 X86MemOperand x86memop, ValueType vt,
1525 string suffix, Domain d> {
1526 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1527 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1528 !strconcat("vcmp${cc}", suffix,
1529 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1530 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1531 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1532 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1533 !strconcat("vcmp${cc}", suffix,
1534 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1536 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1537 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1538 !strconcat("vcmp${cc}", suffix,
1539 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1541 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1543 // Accept explicit immediate argument form instead of comparison code.
1544 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1545 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1546 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1547 !strconcat("vcmp", suffix,
1548 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1549 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1550 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1551 !strconcat("vcmp", suffix,
1552 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1556 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1557 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1558 EVEX_CD8<32, CD8VF>;
1559 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1560 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1561 EVEX_CD8<64, CD8VF>;
1563 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1564 (COPY_TO_REGCLASS (VCMPPSZrri
1565 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1566 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1568 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1569 (COPY_TO_REGCLASS (VPCMPDZrri
1570 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1571 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1573 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1574 (COPY_TO_REGCLASS (VPCMPUDZrri
1575 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1576 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1579 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1580 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1582 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1583 (I8Imm imm:$cc)), GR16)>;
1585 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1586 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1588 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1589 (I8Imm imm:$cc)), GR8)>;
1591 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1592 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1594 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1595 (I8Imm imm:$cc)), GR16)>;
1597 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1598 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1600 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1601 (I8Imm imm:$cc)), GR8)>;
1603 // Mask register copy, including
1604 // - copy between mask registers
1605 // - load/store mask registers
1606 // - copy from GPR to mask register and vice versa
1608 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1609 string OpcodeStr, RegisterClass KRC,
1610 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1611 let hasSideEffects = 0 in {
1612 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1613 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1615 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1617 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1619 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1620 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1624 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1626 RegisterClass KRC, RegisterClass GRC> {
1627 let hasSideEffects = 0 in {
1628 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1629 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1630 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1631 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1635 let Predicates = [HasDQI] in
1636 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1638 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1641 let Predicates = [HasAVX512] in
1642 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1644 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1647 let Predicates = [HasBWI] in {
1648 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1649 i32mem>, VEX, PD, VEX_W;
1650 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1654 let Predicates = [HasBWI] in {
1655 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1656 i64mem>, VEX, PS, VEX_W;
1657 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1661 // GR from/to mask register
1662 let Predicates = [HasDQI] in {
1663 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1664 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1665 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1666 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1668 let Predicates = [HasAVX512] in {
1669 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1670 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1671 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1672 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1674 let Predicates = [HasBWI] in {
1675 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1676 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1678 let Predicates = [HasBWI] in {
1679 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1680 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1684 let Predicates = [HasDQI] in {
1685 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1686 (KMOVBmk addr:$dst, VK8:$src)>;
1688 let Predicates = [HasAVX512] in {
1689 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1690 (KMOVWmk addr:$dst, VK16:$src)>;
1691 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1692 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1693 def : Pat<(i1 (load addr:$src)),
1694 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1695 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1696 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1698 let Predicates = [HasBWI] in {
1699 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1700 (KMOVDmk addr:$dst, VK32:$src)>;
1702 let Predicates = [HasBWI] in {
1703 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1704 (KMOVQmk addr:$dst, VK64:$src)>;
1707 let Predicates = [HasAVX512] in {
1708 def : Pat<(i1 (trunc (i64 GR64:$src))),
1709 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1712 def : Pat<(i1 (trunc (i32 GR32:$src))),
1713 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1715 def : Pat<(i1 (trunc (i8 GR8:$src))),
1717 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1719 def : Pat<(i1 (trunc (i16 GR16:$src))),
1721 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1724 def : Pat<(i32 (zext VK1:$src)),
1725 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1726 def : Pat<(i8 (zext VK1:$src)),
1729 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1730 def : Pat<(i64 (zext VK1:$src)),
1731 (AND64ri8 (SUBREG_TO_REG (i64 0),
1732 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1733 def : Pat<(i16 (zext VK1:$src)),
1735 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1737 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1738 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1739 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1740 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1742 let Predicates = [HasBWI] in {
1743 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1744 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1745 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1746 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1750 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1751 let Predicates = [HasAVX512] in {
1752 // GR from/to 8-bit mask without native support
1753 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1755 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1757 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1759 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1762 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1763 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1764 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1765 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1767 let Predicates = [HasBWI] in {
1768 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1769 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1770 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1771 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1774 // Mask unary operation
1776 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1777 RegisterClass KRC, SDPatternOperator OpNode,
1779 let Predicates = [prd] in
1780 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1782 [(set KRC:$dst, (OpNode KRC:$src))]>;
1785 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1786 SDPatternOperator OpNode> {
1787 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1789 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1790 HasAVX512>, VEX, PS;
1791 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1792 HasBWI>, VEX, PD, VEX_W;
1793 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1794 HasBWI>, VEX, PS, VEX_W;
1797 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1799 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1800 let Predicates = [HasAVX512] in
1801 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1803 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1804 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1806 defm : avx512_mask_unop_int<"knot", "KNOT">;
1808 let Predicates = [HasDQI] in
1809 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1810 let Predicates = [HasAVX512] in
1811 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1812 let Predicates = [HasBWI] in
1813 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1814 let Predicates = [HasBWI] in
1815 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1817 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1818 let Predicates = [HasAVX512] in {
1819 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1820 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1822 def : Pat<(not VK8:$src),
1824 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1827 // Mask binary operation
1828 // - KAND, KANDN, KOR, KXNOR, KXOR
1829 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1830 RegisterClass KRC, SDPatternOperator OpNode,
1832 let Predicates = [prd] in
1833 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1834 !strconcat(OpcodeStr,
1835 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1836 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1839 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1840 SDPatternOperator OpNode> {
1841 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1842 HasDQI>, VEX_4V, VEX_L, PD;
1843 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1844 HasAVX512>, VEX_4V, VEX_L, PS;
1845 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1846 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1847 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1848 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1851 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1852 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1854 let isCommutable = 1 in {
1855 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1856 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1857 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1858 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1860 let isCommutable = 0 in
1861 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1863 def : Pat<(xor VK1:$src1, VK1:$src2),
1864 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1865 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1867 def : Pat<(or VK1:$src1, VK1:$src2),
1868 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1869 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1871 def : Pat<(and VK1:$src1, VK1:$src2),
1872 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1873 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1875 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1876 let Predicates = [HasAVX512] in
1877 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1878 (i16 GR16:$src1), (i16 GR16:$src2)),
1879 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1880 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1881 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1884 defm : avx512_mask_binop_int<"kand", "KAND">;
1885 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1886 defm : avx512_mask_binop_int<"kor", "KOR">;
1887 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1888 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1890 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1891 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1892 let Predicates = [HasAVX512] in
1893 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1895 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1896 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1899 defm : avx512_binop_pat<and, KANDWrr>;
1900 defm : avx512_binop_pat<andn, KANDNWrr>;
1901 defm : avx512_binop_pat<or, KORWrr>;
1902 defm : avx512_binop_pat<xnor, KXNORWrr>;
1903 defm : avx512_binop_pat<xor, KXORWrr>;
1906 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1907 RegisterClass KRC> {
1908 let Predicates = [HasAVX512] in
1909 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1910 !strconcat(OpcodeStr,
1911 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1914 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1915 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1919 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1920 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1921 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1922 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1925 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1926 let Predicates = [HasAVX512] in
1927 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1928 (i16 GR16:$src1), (i16 GR16:$src2)),
1929 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1930 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1931 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1933 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1936 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1938 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1939 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1940 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1941 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1944 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1945 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1949 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1951 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1952 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1953 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1956 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1958 let Predicates = [HasAVX512] in
1959 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1960 !strconcat(OpcodeStr,
1961 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1962 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1965 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1967 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1971 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1972 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1974 // Mask setting all 0s or 1s
1975 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1976 let Predicates = [HasAVX512] in
1977 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1978 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1979 [(set KRC:$dst, (VT Val))]>;
1982 multiclass avx512_mask_setop_w<PatFrag Val> {
1983 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1984 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1987 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1988 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1990 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1991 let Predicates = [HasAVX512] in {
1992 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1993 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1994 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1995 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1996 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1998 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1999 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2001 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2002 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2004 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2005 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2007 let Predicates = [HasVLX] in {
2008 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2009 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2010 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2011 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2012 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2013 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2014 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2015 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2018 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2019 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
2021 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2022 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
2023 //===----------------------------------------------------------------------===//
2024 // AVX-512 - Aligned and unaligned load and store
2027 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
2028 RegisterClass KRC, RegisterClass RC,
2029 ValueType vt, ValueType zvt, X86MemOperand memop,
2030 Domain d, bit IsReMaterializable = 1> {
2031 let hasSideEffects = 0 in {
2032 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2033 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2035 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2036 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2037 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2039 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2040 SchedRW = [WriteLoad] in
2041 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2042 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2043 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2046 let AddedComplexity = 20 in {
2047 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2048 let hasSideEffects = 0 in
2049 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2050 (ins RC:$src0, KRC:$mask, RC:$src1),
2051 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2052 "${dst} {${mask}}, $src1}"),
2053 [(set RC:$dst, (vt (vselect KRC:$mask,
2057 let mayLoad = 1, SchedRW = [WriteLoad] in
2058 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2059 (ins RC:$src0, KRC:$mask, memop:$src1),
2060 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2061 "${dst} {${mask}}, $src1}"),
2064 (vt (bitconvert (ld_frag addr:$src1))),
2068 let mayLoad = 1, SchedRW = [WriteLoad] in
2069 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2070 (ins KRC:$mask, memop:$src),
2071 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2072 "${dst} {${mask}} {z}, $src}"),
2075 (vt (bitconvert (ld_frag addr:$src))),
2076 (vt (bitconvert (zvt immAllZerosV))))))],
2081 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2082 string elty, string elsz, string vsz512,
2083 string vsz256, string vsz128, Domain d,
2084 Predicate prd, bit IsReMaterializable = 1> {
2085 let Predicates = [prd] in
2086 defm Z : avx512_load<opc, OpcodeStr,
2087 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2088 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2089 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2090 !cast<X86MemOperand>(elty##"512mem"), d,
2091 IsReMaterializable>, EVEX_V512;
2093 let Predicates = [prd, HasVLX] in {
2094 defm Z256 : avx512_load<opc, OpcodeStr,
2095 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2096 "v"##vsz256##elty##elsz, "v4i64")),
2097 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2098 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2099 !cast<X86MemOperand>(elty##"256mem"), d,
2100 IsReMaterializable>, EVEX_V256;
2102 defm Z128 : avx512_load<opc, OpcodeStr,
2103 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2104 "v"##vsz128##elty##elsz, "v2i64")),
2105 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2106 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2107 !cast<X86MemOperand>(elty##"128mem"), d,
2108 IsReMaterializable>, EVEX_V128;
2113 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2114 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2115 X86MemOperand memop, Domain d> {
2116 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2117 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2118 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2120 let Constraints = "$src1 = $dst" in
2121 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2122 (ins RC:$src1, KRC:$mask, RC:$src2),
2123 !strconcat(OpcodeStr,
2124 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2126 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2127 (ins KRC:$mask, RC:$src),
2128 !strconcat(OpcodeStr,
2129 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2130 [], d>, EVEX, EVEX_KZ;
2132 let mayStore = 1 in {
2133 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2134 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2135 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2136 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2137 (ins memop:$dst, KRC:$mask, RC:$src),
2138 !strconcat(OpcodeStr,
2139 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2140 [], d>, EVEX, EVEX_K;
2145 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2146 string st_suff_512, string st_suff_256,
2147 string st_suff_128, string elty, string elsz,
2148 string vsz512, string vsz256, string vsz128,
2149 Domain d, Predicate prd> {
2150 let Predicates = [prd] in
2151 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2152 !cast<ValueType>("v"##vsz512##elty##elsz),
2153 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2154 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2156 let Predicates = [prd, HasVLX] in {
2157 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2158 !cast<ValueType>("v"##vsz256##elty##elsz),
2159 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2160 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2162 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2163 !cast<ValueType>("v"##vsz128##elty##elsz),
2164 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2165 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2169 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2170 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2171 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2172 "512", "256", "", "f", "32", "16", "8", "4",
2173 SSEPackedSingle, HasAVX512>,
2174 PS, EVEX_CD8<32, CD8VF>;
2176 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2177 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2178 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2179 "512", "256", "", "f", "64", "8", "4", "2",
2180 SSEPackedDouble, HasAVX512>,
2181 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2183 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2184 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2185 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2186 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2187 PS, EVEX_CD8<32, CD8VF>;
2189 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2190 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2191 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2192 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2193 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2195 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2196 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2197 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2199 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2200 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2201 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2203 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2204 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2205 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2207 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2208 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2209 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2211 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2212 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2213 (VMOVAPDZrm addr:$ptr)>;
2215 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2216 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2217 (VMOVAPSZrm addr:$ptr)>;
2219 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2221 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2223 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2225 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2228 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2230 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2232 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2234 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2237 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2238 (VMOVUPSZmrk addr:$ptr,
2239 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2240 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2242 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2243 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2244 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2246 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2247 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2249 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2250 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2252 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2253 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2255 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2256 (bc_v16f32 (v16i32 immAllZerosV)))),
2257 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2259 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2260 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2262 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2263 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2265 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2266 (bc_v8f64 (v16i32 immAllZerosV)))),
2267 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2269 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2270 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2272 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2273 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2274 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2275 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2277 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2278 "16", "8", "4", SSEPackedInt, HasAVX512>,
2279 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2280 "512", "256", "", "i", "32", "16", "8", "4",
2281 SSEPackedInt, HasAVX512>,
2282 PD, EVEX_CD8<32, CD8VF>;
2284 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2285 "8", "4", "2", SSEPackedInt, HasAVX512>,
2286 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2287 "512", "256", "", "i", "64", "8", "4", "2",
2288 SSEPackedInt, HasAVX512>,
2289 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2291 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2292 "64", "32", "16", SSEPackedInt, HasBWI>,
2293 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2294 "i", "8", "64", "32", "16", SSEPackedInt,
2295 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2297 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2298 "32", "16", "8", SSEPackedInt, HasBWI>,
2299 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2300 "i", "16", "32", "16", "8", SSEPackedInt,
2301 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2303 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2304 "16", "8", "4", SSEPackedInt, HasAVX512>,
2305 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2306 "i", "32", "16", "8", "4", SSEPackedInt,
2307 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2309 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2310 "8", "4", "2", SSEPackedInt, HasAVX512>,
2311 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2312 "i", "64", "8", "4", "2", SSEPackedInt,
2313 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2315 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2316 (v16i32 immAllZerosV), GR16:$mask)),
2317 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2319 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2320 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2321 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2323 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2325 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2327 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2329 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2332 let AddedComplexity = 20 in {
2333 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2334 (bc_v8i64 (v16i32 immAllZerosV)))),
2335 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2337 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2338 (v8i64 VR512:$src))),
2339 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2342 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2343 (v16i32 immAllZerosV))),
2344 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2346 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2347 (v16i32 VR512:$src))),
2348 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2351 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2352 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2354 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2355 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2357 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2358 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2360 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2361 (bc_v8i64 (v16i32 immAllZerosV)))),
2362 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2364 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2365 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2367 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2368 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2370 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2371 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2373 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2374 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2377 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2378 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2381 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2382 (VMOVDQU32Zmrk addr:$ptr,
2383 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2384 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2386 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2387 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2388 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2391 // Move Int Doubleword to Packed Double Int
2393 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2394 "vmovd\t{$src, $dst|$dst, $src}",
2396 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2398 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2399 "vmovd\t{$src, $dst|$dst, $src}",
2401 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2402 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2403 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2404 "vmovq\t{$src, $dst|$dst, $src}",
2406 (v2i64 (scalar_to_vector GR64:$src)))],
2407 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2408 let isCodeGenOnly = 1 in {
2409 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2410 "vmovq\t{$src, $dst|$dst, $src}",
2411 [(set FR64:$dst, (bitconvert GR64:$src))],
2412 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2413 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2414 "vmovq\t{$src, $dst|$dst, $src}",
2415 [(set GR64:$dst, (bitconvert FR64:$src))],
2416 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2418 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2419 "vmovq\t{$src, $dst|$dst, $src}",
2420 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2421 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2422 EVEX_CD8<64, CD8VT1>;
2424 // Move Int Doubleword to Single Scalar
2426 let isCodeGenOnly = 1 in {
2427 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2428 "vmovd\t{$src, $dst|$dst, $src}",
2429 [(set FR32X:$dst, (bitconvert GR32:$src))],
2430 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2432 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2433 "vmovd\t{$src, $dst|$dst, $src}",
2434 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2435 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2438 // Move doubleword from xmm register to r/m32
2440 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2441 "vmovd\t{$src, $dst|$dst, $src}",
2442 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2443 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2445 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2446 (ins i32mem:$dst, VR128X:$src),
2447 "vmovd\t{$src, $dst|$dst, $src}",
2448 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2449 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2450 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2452 // Move quadword from xmm1 register to r/m64
2454 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2455 "vmovq\t{$src, $dst|$dst, $src}",
2456 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2458 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2459 Requires<[HasAVX512, In64BitMode]>;
2461 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2462 (ins i64mem:$dst, VR128X:$src),
2463 "vmovq\t{$src, $dst|$dst, $src}",
2464 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2465 addr:$dst)], IIC_SSE_MOVDQ>,
2466 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2467 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2469 // Move Scalar Single to Double Int
2471 let isCodeGenOnly = 1 in {
2472 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2474 "vmovd\t{$src, $dst|$dst, $src}",
2475 [(set GR32:$dst, (bitconvert FR32X:$src))],
2476 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2477 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2478 (ins i32mem:$dst, FR32X:$src),
2479 "vmovd\t{$src, $dst|$dst, $src}",
2480 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2481 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2484 // Move Quadword Int to Packed Quadword Int
2486 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2488 "vmovq\t{$src, $dst|$dst, $src}",
2490 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2491 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2493 //===----------------------------------------------------------------------===//
2494 // AVX-512 MOVSS, MOVSD
2495 //===----------------------------------------------------------------------===//
2497 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2498 SDNode OpNode, ValueType vt,
2499 X86MemOperand x86memop, PatFrag mem_pat> {
2500 let hasSideEffects = 0 in {
2501 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2502 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2503 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2504 (scalar_to_vector RC:$src2))))],
2505 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2506 let Constraints = "$src1 = $dst" in
2507 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2508 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2510 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2511 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2512 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2513 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2514 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2516 let mayStore = 1 in {
2517 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2518 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2519 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2521 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2522 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2523 [], IIC_SSE_MOV_S_MR>,
2524 EVEX, VEX_LIG, EVEX_K;
2526 } //hasSideEffects = 0
2529 let ExeDomain = SSEPackedSingle in
2530 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2531 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2533 let ExeDomain = SSEPackedDouble in
2534 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2535 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2537 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2538 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2539 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2541 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2542 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2543 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2545 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2546 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2547 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2549 // For the disassembler
2550 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2551 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2552 (ins VR128X:$src1, FR32X:$src2),
2553 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2555 XS, EVEX_4V, VEX_LIG;
2556 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2557 (ins VR128X:$src1, FR64X:$src2),
2558 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2560 XD, EVEX_4V, VEX_LIG, VEX_W;
2563 let Predicates = [HasAVX512] in {
2564 let AddedComplexity = 15 in {
2565 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2566 // MOVS{S,D} to the lower bits.
2567 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2568 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2569 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2570 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2571 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2572 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2573 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2574 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2576 // Move low f32 and clear high bits.
2577 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2578 (SUBREG_TO_REG (i32 0),
2579 (VMOVSSZrr (v4f32 (V_SET0)),
2580 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2581 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2582 (SUBREG_TO_REG (i32 0),
2583 (VMOVSSZrr (v4i32 (V_SET0)),
2584 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2587 let AddedComplexity = 20 in {
2588 // MOVSSrm zeros the high parts of the register; represent this
2589 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2590 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2591 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2592 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2593 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2594 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2595 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2597 // MOVSDrm zeros the high parts of the register; represent this
2598 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2599 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2600 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2601 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2602 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2603 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2604 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2605 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2606 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2607 def : Pat<(v2f64 (X86vzload addr:$src)),
2608 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2610 // Represent the same patterns above but in the form they appear for
2612 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2613 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2614 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2615 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2616 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2617 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2618 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2619 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2620 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2622 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2623 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2624 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2625 FR32X:$src)), sub_xmm)>;
2626 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2627 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2628 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2629 FR64X:$src)), sub_xmm)>;
2630 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2631 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2632 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2634 // Move low f64 and clear high bits.
2635 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2636 (SUBREG_TO_REG (i32 0),
2637 (VMOVSDZrr (v2f64 (V_SET0)),
2638 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2640 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2641 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2642 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2644 // Extract and store.
2645 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2647 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2648 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2650 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2652 // Shuffle with VMOVSS
2653 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2654 (VMOVSSZrr (v4i32 VR128X:$src1),
2655 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2656 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2657 (VMOVSSZrr (v4f32 VR128X:$src1),
2658 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2661 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2662 (SUBREG_TO_REG (i32 0),
2663 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2664 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2666 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2667 (SUBREG_TO_REG (i32 0),
2668 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2669 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2672 // Shuffle with VMOVSD
2673 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2674 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2675 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2676 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2677 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2678 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2679 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2680 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2683 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2684 (SUBREG_TO_REG (i32 0),
2685 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2686 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2688 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2689 (SUBREG_TO_REG (i32 0),
2690 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2691 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2694 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2695 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2696 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2697 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2698 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2699 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2700 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2701 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2704 let AddedComplexity = 15 in
2705 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2707 "vmovq\t{$src, $dst|$dst, $src}",
2708 [(set VR128X:$dst, (v2i64 (X86vzmovl
2709 (v2i64 VR128X:$src))))],
2710 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2712 let AddedComplexity = 20 in
2713 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2715 "vmovq\t{$src, $dst|$dst, $src}",
2716 [(set VR128X:$dst, (v2i64 (X86vzmovl
2717 (loadv2i64 addr:$src))))],
2718 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2719 EVEX_CD8<8, CD8VT8>;
2721 let Predicates = [HasAVX512] in {
2722 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2723 let AddedComplexity = 20 in {
2724 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2725 (VMOVDI2PDIZrm addr:$src)>;
2726 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2727 (VMOV64toPQIZrr GR64:$src)>;
2728 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2729 (VMOVDI2PDIZrr GR32:$src)>;
2731 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2732 (VMOVDI2PDIZrm addr:$src)>;
2733 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2734 (VMOVDI2PDIZrm addr:$src)>;
2735 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2736 (VMOVZPQILo2PQIZrm addr:$src)>;
2737 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2738 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2739 def : Pat<(v2i64 (X86vzload addr:$src)),
2740 (VMOVZPQILo2PQIZrm addr:$src)>;
2743 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2744 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2745 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2746 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2747 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2748 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2749 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2752 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2753 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2755 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2756 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2758 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2759 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2761 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2762 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2764 //===----------------------------------------------------------------------===//
2765 // AVX-512 - Non-temporals
2766 //===----------------------------------------------------------------------===//
2767 let SchedRW = [WriteLoad] in {
2768 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2769 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2770 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2771 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2772 EVEX_CD8<64, CD8VF>;
2774 let Predicates = [HasAVX512, HasVLX] in {
2775 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2777 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2778 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2779 EVEX_CD8<64, CD8VF>;
2781 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2783 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2784 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2785 EVEX_CD8<64, CD8VF>;
2789 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2790 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2791 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2792 let SchedRW = [WriteStore], mayStore = 1,
2793 AddedComplexity = 400 in
2794 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2795 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2796 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2799 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2800 string elty, string elsz, string vsz512,
2801 string vsz256, string vsz128, Domain d,
2802 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2803 let Predicates = [prd] in
2804 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2805 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2806 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2809 let Predicates = [prd, HasVLX] in {
2810 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2811 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2812 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2815 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2816 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2817 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2822 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2823 "i", "64", "8", "4", "2", SSEPackedInt,
2824 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2826 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2827 "f", "64", "8", "4", "2", SSEPackedDouble,
2828 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2830 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2831 "f", "32", "16", "8", "4", SSEPackedSingle,
2832 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2834 //===----------------------------------------------------------------------===//
2835 // AVX-512 - Integer arithmetic
2837 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2838 X86VectorVTInfo _, OpndItins itins,
2839 bit IsCommutable = 0> {
2840 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2841 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2842 "$src2, $src1", "$src1, $src2",
2843 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2844 "", itins.rr, IsCommutable>,
2845 AVX512BIBase, EVEX_4V;
2848 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2849 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2850 "$src2, $src1", "$src1, $src2",
2851 (_.VT (OpNode _.RC:$src1,
2852 (bitconvert (_.LdFrag addr:$src2)))),
2854 AVX512BIBase, EVEX_4V;
2857 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2858 X86VectorVTInfo _, OpndItins itins,
2859 bit IsCommutable = 0> :
2860 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2862 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2863 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2864 "${src2}"##_.BroadcastStr##", $src1",
2865 "$src1, ${src2}"##_.BroadcastStr,
2866 (_.VT (OpNode _.RC:$src1,
2868 (_.ScalarLdFrag addr:$src2)))),
2870 AVX512BIBase, EVEX_4V, EVEX_B;
2873 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2874 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2875 Predicate prd, bit IsCommutable = 0> {
2876 let Predicates = [prd] in
2877 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2878 IsCommutable>, EVEX_V512;
2880 let Predicates = [prd, HasVLX] in {
2881 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2882 IsCommutable>, EVEX_V256;
2883 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2884 IsCommutable>, EVEX_V128;
2888 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2889 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2890 Predicate prd, bit IsCommutable = 0> {
2891 let Predicates = [prd] in
2892 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2893 IsCommutable>, EVEX_V512;
2895 let Predicates = [prd, HasVLX] in {
2896 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2897 IsCommutable>, EVEX_V256;
2898 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2899 IsCommutable>, EVEX_V128;
2903 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2904 OpndItins itins, Predicate prd,
2905 bit IsCommutable = 0> {
2906 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2907 itins, prd, IsCommutable>,
2908 VEX_W, EVEX_CD8<64, CD8VF>;
2911 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2912 OpndItins itins, Predicate prd,
2913 bit IsCommutable = 0> {
2914 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2915 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2918 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2919 OpndItins itins, Predicate prd,
2920 bit IsCommutable = 0> {
2921 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2922 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2925 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2926 OpndItins itins, Predicate prd,
2927 bit IsCommutable = 0> {
2928 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2929 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2932 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2933 SDNode OpNode, OpndItins itins, Predicate prd,
2934 bit IsCommutable = 0> {
2935 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2938 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2942 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2943 SDNode OpNode, OpndItins itins, Predicate prd,
2944 bit IsCommutable = 0> {
2945 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2948 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2952 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2953 bits<8> opc_d, bits<8> opc_q,
2954 string OpcodeStr, SDNode OpNode,
2955 OpndItins itins, bit IsCommutable = 0> {
2956 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2957 itins, HasAVX512, IsCommutable>,
2958 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2959 itins, HasBWI, IsCommutable>;
2962 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2963 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2964 PatFrag memop_frag, X86MemOperand x86memop,
2965 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2966 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2967 let isCommutable = IsCommutable in
2969 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2970 (ins RC:$src1, RC:$src2),
2971 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2973 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2974 (ins KRC:$mask, RC:$src1, RC:$src2),
2975 !strconcat(OpcodeStr,
2976 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2977 [], itins.rr>, EVEX_4V, EVEX_K;
2978 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2979 (ins KRC:$mask, RC:$src1, RC:$src2),
2980 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
2981 "|$dst {${mask}} {z}, $src1, $src2}"),
2982 [], itins.rr>, EVEX_4V, EVEX_KZ;
2984 let mayLoad = 1 in {
2985 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2986 (ins RC:$src1, x86memop:$src2),
2987 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2989 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2990 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2991 !strconcat(OpcodeStr,
2992 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2993 [], itins.rm>, EVEX_4V, EVEX_K;
2994 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2995 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2996 !strconcat(OpcodeStr,
2997 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2998 [], itins.rm>, EVEX_4V, EVEX_KZ;
2999 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3000 (ins RC:$src1, x86scalar_mop:$src2),
3001 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3002 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
3003 [], itins.rm>, EVEX_4V, EVEX_B;
3004 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3005 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3006 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3007 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
3009 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
3010 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3011 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3012 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3013 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3015 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
3019 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3020 SSE_INTALU_ITINS_P, 1>;
3021 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3022 SSE_INTALU_ITINS_P, 0>;
3023 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3024 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3025 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3026 SSE_INTALU_ITINS_P, HasBWI, 1>;
3027 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3028 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3030 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
3031 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3032 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
3033 EVEX_CD8<64, CD8VF>, VEX_W;
3035 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
3036 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3037 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3039 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
3040 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3042 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
3043 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3044 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3045 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
3046 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3047 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
3049 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3050 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3051 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3052 SSE_INTALU_ITINS_P, HasBWI, 1>;
3053 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3054 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3056 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3057 SSE_INTALU_ITINS_P, HasBWI, 1>;
3058 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3059 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3060 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3061 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3063 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3064 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3065 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3066 SSE_INTALU_ITINS_P, HasBWI, 1>;
3067 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3068 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3070 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3071 SSE_INTALU_ITINS_P, HasBWI, 1>;
3072 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3073 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3074 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3075 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3077 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3078 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3079 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3080 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3081 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3082 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3083 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3084 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3085 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3086 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3087 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3088 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3089 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3090 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3091 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3092 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3093 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3094 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3095 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3096 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3097 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3098 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3099 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3100 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3101 //===----------------------------------------------------------------------===//
3102 // AVX-512 - Unpack Instructions
3103 //===----------------------------------------------------------------------===//
3105 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3106 PatFrag mem_frag, RegisterClass RC,
3107 X86MemOperand x86memop, string asm,
3109 def rr : AVX512PI<opc, MRMSrcReg,
3110 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3112 (vt (OpNode RC:$src1, RC:$src2)))],
3114 def rm : AVX512PI<opc, MRMSrcMem,
3115 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3117 (vt (OpNode RC:$src1,
3118 (bitconvert (mem_frag addr:$src2)))))],
3122 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3123 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3124 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3125 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3126 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3127 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3128 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3129 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3130 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3131 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3132 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3133 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3135 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3136 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3137 X86MemOperand x86memop> {
3138 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3139 (ins RC:$src1, RC:$src2),
3140 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3141 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3142 IIC_SSE_UNPCK>, EVEX_4V;
3143 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3144 (ins RC:$src1, x86memop:$src2),
3145 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3146 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3147 (bitconvert (memop_frag addr:$src2)))))],
3148 IIC_SSE_UNPCK>, EVEX_4V;
3150 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3151 VR512, memopv16i32, i512mem>, EVEX_V512,
3152 EVEX_CD8<32, CD8VF>;
3153 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3154 VR512, memopv8i64, i512mem>, EVEX_V512,
3155 VEX_W, EVEX_CD8<64, CD8VF>;
3156 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3157 VR512, memopv16i32, i512mem>, EVEX_V512,
3158 EVEX_CD8<32, CD8VF>;
3159 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3160 VR512, memopv8i64, i512mem>, EVEX_V512,
3161 VEX_W, EVEX_CD8<64, CD8VF>;
3162 //===----------------------------------------------------------------------===//
3166 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3167 SDNode OpNode, PatFrag mem_frag,
3168 X86MemOperand x86memop, ValueType OpVT> {
3169 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3170 (ins RC:$src1, i8imm:$src2),
3171 !strconcat(OpcodeStr,
3172 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3174 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3176 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3177 (ins x86memop:$src1, i8imm:$src2),
3178 !strconcat(OpcodeStr,
3179 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3181 (OpVT (OpNode (mem_frag addr:$src1),
3182 (i8 imm:$src2))))]>, EVEX;
3185 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3186 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3188 //===----------------------------------------------------------------------===//
3189 // AVX-512 Logical Instructions
3190 //===----------------------------------------------------------------------===//
3192 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3193 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3194 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3195 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3196 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3197 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3198 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3199 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3201 //===----------------------------------------------------------------------===//
3202 // AVX-512 FP arithmetic
3203 //===----------------------------------------------------------------------===//
3205 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3207 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3208 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3209 EVEX_CD8<32, CD8VT1>;
3210 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3211 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3212 EVEX_CD8<64, CD8VT1>;
3215 let isCommutable = 1 in {
3216 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3217 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3218 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3219 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3221 let isCommutable = 0 in {
3222 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3223 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3226 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3227 X86VectorVTInfo _, bit IsCommutable> {
3228 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3229 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3230 "$src2, $src1", "$src1, $src2",
3231 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3232 let mayLoad = 1 in {
3233 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3234 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3235 "$src2, $src1", "$src1, $src2",
3236 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3237 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3238 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3239 "${src2}"##_.BroadcastStr##", $src1",
3240 "$src1, ${src2}"##_.BroadcastStr,
3241 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3242 (_.ScalarLdFrag addr:$src2))))>,
3247 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3248 bit IsCommutable = 0> {
3249 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3250 IsCommutable>, EVEX_V512, PS,
3251 EVEX_CD8<32, CD8VF>;
3252 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3253 IsCommutable>, EVEX_V512, PD, VEX_W,
3254 EVEX_CD8<64, CD8VF>;
3256 // Define only if AVX512VL feature is present.
3257 let Predicates = [HasVLX] in {
3258 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3259 IsCommutable>, EVEX_V128, PS,
3260 EVEX_CD8<32, CD8VF>;
3261 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3262 IsCommutable>, EVEX_V256, PS,
3263 EVEX_CD8<32, CD8VF>;
3264 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3265 IsCommutable>, EVEX_V128, PD, VEX_W,
3266 EVEX_CD8<64, CD8VF>;
3267 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3268 IsCommutable>, EVEX_V256, PD, VEX_W,
3269 EVEX_CD8<64, CD8VF>;
3273 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3274 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3275 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3276 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3277 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3278 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3280 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3281 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3282 (i16 -1), FROUND_CURRENT)),
3283 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3285 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3286 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3287 (i8 -1), FROUND_CURRENT)),
3288 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3290 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3291 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3292 (i16 -1), FROUND_CURRENT)),
3293 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3295 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3296 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3297 (i8 -1), FROUND_CURRENT)),
3298 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3299 //===----------------------------------------------------------------------===//
3300 // AVX-512 VPTESTM instructions
3301 //===----------------------------------------------------------------------===//
3303 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3304 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3305 SDNode OpNode, ValueType vt> {
3306 def rr : AVX512PI<opc, MRMSrcReg,
3307 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3308 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3309 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3310 SSEPackedInt>, EVEX_4V;
3311 def rm : AVX512PI<opc, MRMSrcMem,
3312 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3313 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3314 [(set KRC:$dst, (OpNode (vt RC:$src1),
3315 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3318 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3319 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3320 EVEX_CD8<32, CD8VF>;
3321 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3322 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3323 EVEX_CD8<64, CD8VF>;
3325 let Predicates = [HasCDI] in {
3326 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3327 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3328 EVEX_CD8<32, CD8VF>;
3329 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3330 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3331 EVEX_CD8<64, CD8VF>;
3334 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3335 (v16i32 VR512:$src2), (i16 -1))),
3336 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3338 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3339 (v8i64 VR512:$src2), (i8 -1))),
3340 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3342 //===----------------------------------------------------------------------===//
3343 // AVX-512 Shift instructions
3344 //===----------------------------------------------------------------------===//
3345 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3346 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3347 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3348 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3349 "$src2, $src1", "$src1, $src2",
3350 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3351 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3352 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3353 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3354 "$src2, $src1", "$src1, $src2",
3355 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3356 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3359 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3360 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3361 // src2 is always 128-bit
3362 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3363 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3364 "$src2, $src1", "$src1, $src2",
3365 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3366 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3367 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3368 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3369 "$src2, $src1", "$src1, $src2",
3370 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3371 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3374 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3375 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3376 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3379 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3381 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3382 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3383 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3384 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3387 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3389 EVEX_V512, EVEX_CD8<32, CD8VF>;
3390 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3391 v8i64_info>, EVEX_V512,
3392 EVEX_CD8<64, CD8VF>, VEX_W;
3394 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3395 v16i32_info>, EVEX_V512,
3396 EVEX_CD8<32, CD8VF>;
3397 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3398 v8i64_info>, EVEX_V512,
3399 EVEX_CD8<64, CD8VF>, VEX_W;
3401 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3403 EVEX_V512, EVEX_CD8<32, CD8VF>;
3404 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3405 v8i64_info>, EVEX_V512,
3406 EVEX_CD8<64, CD8VF>, VEX_W;
3408 defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3409 defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3410 defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3412 //===-------------------------------------------------------------------===//
3413 // Variable Bit Shifts
3414 //===-------------------------------------------------------------------===//
3415 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3416 X86VectorVTInfo _> {
3417 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3418 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3419 "$src2, $src1", "$src1, $src2",
3420 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3421 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3422 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3423 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3424 "$src2, $src1", "$src1, $src2",
3425 (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2))),
3426 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
3429 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3430 AVX512VLVectorVTInfo _> {
3431 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3434 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3436 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3437 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
3438 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3439 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3442 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
3443 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
3444 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
3446 //===----------------------------------------------------------------------===//
3447 // AVX-512 - MOVDDUP
3448 //===----------------------------------------------------------------------===//
3450 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3451 X86MemOperand x86memop, PatFrag memop_frag> {
3452 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3453 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3454 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3455 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3456 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3458 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3461 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3462 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3463 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3464 (VMOVDDUPZrm addr:$src)>;
3466 //===---------------------------------------------------------------------===//
3467 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3468 //===---------------------------------------------------------------------===//
3469 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3470 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3471 X86MemOperand x86memop> {
3472 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3473 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3474 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3476 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3477 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3478 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3481 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3482 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3483 EVEX_CD8<32, CD8VF>;
3484 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3485 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3486 EVEX_CD8<32, CD8VF>;
3488 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3489 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3490 (VMOVSHDUPZrm addr:$src)>;
3491 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3492 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3493 (VMOVSLDUPZrm addr:$src)>;
3495 //===----------------------------------------------------------------------===//
3496 // Move Low to High and High to Low packed FP Instructions
3497 //===----------------------------------------------------------------------===//
3498 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3499 (ins VR128X:$src1, VR128X:$src2),
3500 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3501 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3502 IIC_SSE_MOV_LH>, EVEX_4V;
3503 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3504 (ins VR128X:$src1, VR128X:$src2),
3505 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3506 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3507 IIC_SSE_MOV_LH>, EVEX_4V;
3509 let Predicates = [HasAVX512] in {
3511 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3512 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3513 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3514 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3517 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3518 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3521 //===----------------------------------------------------------------------===//
3522 // FMA - Fused Multiply Operations
3525 let Constraints = "$src1 = $dst" in {
3526 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3527 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3528 SDPatternOperator OpNode = null_frag> {
3529 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3530 (ins _.RC:$src2, _.RC:$src3),
3531 OpcodeStr, "$src3, $src2", "$src2, $src3",
3532 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3536 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3537 (ins _.RC:$src2, _.MemOp:$src3),
3538 OpcodeStr, "$src3, $src2", "$src2, $src3",
3539 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3542 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3543 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3544 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ),
3545 (OpNode _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3546 AVX512FMA3Base, EVEX_B;
3548 } // Constraints = "$src1 = $dst"
3550 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3551 string OpcodeStr, X86VectorVTInfo VTI,
3552 SDPatternOperator OpNode> {
3553 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3554 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3556 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3557 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
3560 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
3562 SDPatternOperator OpNode> {
3563 let ExeDomain = SSEPackedSingle in {
3564 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3565 v16f32_info, OpNode>, EVEX_V512;
3566 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3567 v8f32x_info, OpNode>, EVEX_V256;
3568 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3569 v4f32x_info, OpNode>, EVEX_V128;
3571 let ExeDomain = SSEPackedDouble in {
3572 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3573 v8f64_info, OpNode>, EVEX_V512, VEX_W;
3574 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3575 v4f64x_info, OpNode>, EVEX_V256, VEX_W;
3576 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3577 v2f64x_info, OpNode>, EVEX_V128, VEX_W;
3581 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd>;
3582 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub>;
3583 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub>;
3584 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd>;
3585 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd>;
3586 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub>;
3588 let Constraints = "$src1 = $dst" in {
3589 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3590 X86VectorVTInfo _> {
3592 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3593 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3594 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3595 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3597 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3598 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3599 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3600 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3602 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3603 (_.ScalarLdFrag addr:$src2))),
3604 _.RC:$src3))]>, EVEX_B;
3606 } // Constraints = "$src1 = $dst"
3609 multiclass avx512_fma3p_m132_f<bits<8> opc,
3613 let ExeDomain = SSEPackedSingle in {
3614 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
3615 OpNode,v16f32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3616 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3617 OpNode, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>;
3618 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3619 OpNode, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>;
3621 let ExeDomain = SSEPackedDouble in {
3622 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
3623 OpNode, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VF>;
3624 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3625 OpNode, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<32, CD8VF>;
3626 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3627 OpNode, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<32, CD8VF>;
3631 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
3632 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
3633 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
3634 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
3635 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
3636 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
3640 let Constraints = "$src1 = $dst" in {
3641 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3642 RegisterClass RC, ValueType OpVT,
3643 X86MemOperand x86memop, Operand memop,
3645 let isCommutable = 1 in
3646 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3647 (ins RC:$src1, RC:$src2, RC:$src3),
3648 !strconcat(OpcodeStr,
3649 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3651 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3653 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3654 (ins RC:$src1, RC:$src2, f128mem:$src3),
3655 !strconcat(OpcodeStr,
3656 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3658 (OpVT (OpNode RC:$src2, RC:$src1,
3659 (mem_frag addr:$src3))))]>;
3662 } // Constraints = "$src1 = $dst"
3664 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3665 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3666 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3667 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3668 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3669 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3670 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3671 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3672 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3673 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3674 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3675 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3676 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3677 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3678 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3679 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3681 //===----------------------------------------------------------------------===//
3682 // AVX-512 Scalar convert from sign integer to float/double
3683 //===----------------------------------------------------------------------===//
3685 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3686 X86MemOperand x86memop, string asm> {
3687 let hasSideEffects = 0 in {
3688 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3689 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3692 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3693 (ins DstRC:$src1, x86memop:$src),
3694 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3696 } // hasSideEffects = 0
3698 let Predicates = [HasAVX512] in {
3699 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3700 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3701 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3702 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3703 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3704 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3705 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3706 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3708 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3709 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3710 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3711 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3712 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3713 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3714 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3715 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3717 def : Pat<(f32 (sint_to_fp GR32:$src)),
3718 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3719 def : Pat<(f32 (sint_to_fp GR64:$src)),
3720 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3721 def : Pat<(f64 (sint_to_fp GR32:$src)),
3722 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3723 def : Pat<(f64 (sint_to_fp GR64:$src)),
3724 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3726 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3727 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3728 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3729 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3730 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3731 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3732 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3733 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3735 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3736 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3737 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3738 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3739 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3740 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3741 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3742 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3744 def : Pat<(f32 (uint_to_fp GR32:$src)),
3745 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3746 def : Pat<(f32 (uint_to_fp GR64:$src)),
3747 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3748 def : Pat<(f64 (uint_to_fp GR32:$src)),
3749 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3750 def : Pat<(f64 (uint_to_fp GR64:$src)),
3751 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3754 //===----------------------------------------------------------------------===//
3755 // AVX-512 Scalar convert from float/double to integer
3756 //===----------------------------------------------------------------------===//
3757 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3758 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3760 let hasSideEffects = 0 in {
3761 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3762 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3763 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3764 Requires<[HasAVX512]>;
3766 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3767 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3768 Requires<[HasAVX512]>;
3769 } // hasSideEffects = 0
3771 let Predicates = [HasAVX512] in {
3772 // Convert float/double to signed/unsigned int 32/64
3773 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3774 ssmem, sse_load_f32, "cvtss2si">,
3775 XS, EVEX_CD8<32, CD8VT1>;
3776 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3777 ssmem, sse_load_f32, "cvtss2si">,
3778 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3779 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3780 ssmem, sse_load_f32, "cvtss2usi">,
3781 XS, EVEX_CD8<32, CD8VT1>;
3782 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3783 int_x86_avx512_cvtss2usi64, ssmem,
3784 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3785 EVEX_CD8<32, CD8VT1>;
3786 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3787 sdmem, sse_load_f64, "cvtsd2si">,
3788 XD, EVEX_CD8<64, CD8VT1>;
3789 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3790 sdmem, sse_load_f64, "cvtsd2si">,
3791 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3792 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3793 sdmem, sse_load_f64, "cvtsd2usi">,
3794 XD, EVEX_CD8<64, CD8VT1>;
3795 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3796 int_x86_avx512_cvtsd2usi64, sdmem,
3797 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3798 EVEX_CD8<64, CD8VT1>;
3800 let isCodeGenOnly = 1 in {
3801 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3802 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3803 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3804 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3805 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3806 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3807 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3808 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3809 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3810 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3811 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3812 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3814 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3815 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3816 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3817 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3818 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3819 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3820 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3821 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3822 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3823 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3824 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3825 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3826 } // isCodeGenOnly = 1
3828 // Convert float/double to signed/unsigned int 32/64 with truncation
3829 let isCodeGenOnly = 1 in {
3830 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3831 ssmem, sse_load_f32, "cvttss2si">,
3832 XS, EVEX_CD8<32, CD8VT1>;
3833 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3834 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3835 "cvttss2si">, XS, VEX_W,
3836 EVEX_CD8<32, CD8VT1>;
3837 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3838 sdmem, sse_load_f64, "cvttsd2si">, XD,
3839 EVEX_CD8<64, CD8VT1>;
3840 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3841 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3842 "cvttsd2si">, XD, VEX_W,
3843 EVEX_CD8<64, CD8VT1>;
3844 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3845 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3846 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3847 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3848 int_x86_avx512_cvttss2usi64, ssmem,
3849 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3850 EVEX_CD8<32, CD8VT1>;
3851 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3852 int_x86_avx512_cvttsd2usi,
3853 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3854 EVEX_CD8<64, CD8VT1>;
3855 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3856 int_x86_avx512_cvttsd2usi64, sdmem,
3857 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3858 EVEX_CD8<64, CD8VT1>;
3859 } // isCodeGenOnly = 1
3861 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3862 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3864 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3865 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3866 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3867 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3868 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3869 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3872 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3873 loadf32, "cvttss2si">, XS,
3874 EVEX_CD8<32, CD8VT1>;
3875 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3876 loadf32, "cvttss2usi">, XS,
3877 EVEX_CD8<32, CD8VT1>;
3878 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3879 loadf32, "cvttss2si">, XS, VEX_W,
3880 EVEX_CD8<32, CD8VT1>;
3881 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3882 loadf32, "cvttss2usi">, XS, VEX_W,
3883 EVEX_CD8<32, CD8VT1>;
3884 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3885 loadf64, "cvttsd2si">, XD,
3886 EVEX_CD8<64, CD8VT1>;
3887 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3888 loadf64, "cvttsd2usi">, XD,
3889 EVEX_CD8<64, CD8VT1>;
3890 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3891 loadf64, "cvttsd2si">, XD, VEX_W,
3892 EVEX_CD8<64, CD8VT1>;
3893 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3894 loadf64, "cvttsd2usi">, XD, VEX_W,
3895 EVEX_CD8<64, CD8VT1>;
3897 //===----------------------------------------------------------------------===//
3898 // AVX-512 Convert form float to double and back
3899 //===----------------------------------------------------------------------===//
3900 let hasSideEffects = 0 in {
3901 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3902 (ins FR32X:$src1, FR32X:$src2),
3903 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3904 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3906 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3907 (ins FR32X:$src1, f32mem:$src2),
3908 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3909 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3910 EVEX_CD8<32, CD8VT1>;
3912 // Convert scalar double to scalar single
3913 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3914 (ins FR64X:$src1, FR64X:$src2),
3915 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3916 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3918 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3919 (ins FR64X:$src1, f64mem:$src2),
3920 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3921 []>, EVEX_4V, VEX_LIG, VEX_W,
3922 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3925 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3926 Requires<[HasAVX512]>;
3927 def : Pat<(fextend (loadf32 addr:$src)),
3928 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3930 def : Pat<(extloadf32 addr:$src),
3931 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3932 Requires<[HasAVX512, OptForSize]>;
3934 def : Pat<(extloadf32 addr:$src),
3935 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3936 Requires<[HasAVX512, OptForSpeed]>;
3938 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3939 Requires<[HasAVX512]>;
3941 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3942 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3943 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3945 let hasSideEffects = 0 in {
3946 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3947 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3949 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3950 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3951 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3952 [], d>, EVEX, EVEX_B, EVEX_RC;
3954 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3955 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3957 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3958 } // hasSideEffects = 0
3961 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3962 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3963 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3965 let hasSideEffects = 0 in {
3966 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3967 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3969 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3971 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3972 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3974 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3975 } // hasSideEffects = 0
3978 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3979 memopv8f64, f512mem, v8f32, v8f64,
3980 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3981 EVEX_CD8<64, CD8VF>;
3983 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3984 memopv4f64, f256mem, v8f64, v8f32,
3985 SSEPackedDouble>, EVEX_V512, PS,
3986 EVEX_CD8<32, CD8VH>;
3987 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3988 (VCVTPS2PDZrm addr:$src)>;
3990 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3991 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3992 (VCVTPD2PSZrr VR512:$src)>;
3994 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3995 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3996 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3998 //===----------------------------------------------------------------------===//
3999 // AVX-512 Vector convert from sign integer to float/double
4000 //===----------------------------------------------------------------------===//
4002 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4003 memopv8i64, i512mem, v16f32, v16i32,
4004 SSEPackedSingle>, EVEX_V512, PS,
4005 EVEX_CD8<32, CD8VF>;
4007 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4008 memopv4i64, i256mem, v8f64, v8i32,
4009 SSEPackedDouble>, EVEX_V512, XS,
4010 EVEX_CD8<32, CD8VH>;
4012 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4013 memopv16f32, f512mem, v16i32, v16f32,
4014 SSEPackedSingle>, EVEX_V512, XS,
4015 EVEX_CD8<32, CD8VF>;
4017 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4018 memopv8f64, f512mem, v8i32, v8f64,
4019 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4020 EVEX_CD8<64, CD8VF>;
4022 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4023 memopv16f32, f512mem, v16i32, v16f32,
4024 SSEPackedSingle>, EVEX_V512, PS,
4025 EVEX_CD8<32, CD8VF>;
4027 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4028 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4029 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4030 (VCVTTPS2UDQZrr VR512:$src)>;
4032 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4033 memopv8f64, f512mem, v8i32, v8f64,
4034 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4035 EVEX_CD8<64, CD8VF>;
4037 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4038 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4039 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4040 (VCVTTPD2UDQZrr VR512:$src)>;
4042 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4043 memopv4i64, f256mem, v8f64, v8i32,
4044 SSEPackedDouble>, EVEX_V512, XS,
4045 EVEX_CD8<32, CD8VH>;
4047 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4048 memopv16i32, f512mem, v16f32, v16i32,
4049 SSEPackedSingle>, EVEX_V512, XD,
4050 EVEX_CD8<32, CD8VF>;
4052 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4053 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4054 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4056 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4057 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4058 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4060 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4061 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4062 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4064 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4065 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4066 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4068 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4069 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4070 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4072 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4073 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4074 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4075 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4076 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4077 (VCVTDQ2PDZrr VR256X:$src)>;
4078 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4079 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4080 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4081 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4082 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4083 (VCVTUDQ2PDZrr VR256X:$src)>;
4085 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4086 RegisterClass DstRC, PatFrag mem_frag,
4087 X86MemOperand x86memop, Domain d> {
4088 let hasSideEffects = 0 in {
4089 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4090 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4092 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4093 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4094 [], d>, EVEX, EVEX_B, EVEX_RC;
4096 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4097 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4099 } // hasSideEffects = 0
4102 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4103 memopv16f32, f512mem, SSEPackedSingle>, PD,
4104 EVEX_V512, EVEX_CD8<32, CD8VF>;
4105 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4106 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4107 EVEX_V512, EVEX_CD8<64, CD8VF>;
4109 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4110 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4111 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4113 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4114 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4115 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4117 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4118 memopv16f32, f512mem, SSEPackedSingle>,
4119 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4120 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4121 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4122 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4124 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4125 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4126 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4128 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4129 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4130 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4132 let Predicates = [HasAVX512] in {
4133 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4134 (VCVTPD2PSZrm addr:$src)>;
4135 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4136 (VCVTPS2PDZrm addr:$src)>;
4139 //===----------------------------------------------------------------------===//
4140 // Half precision conversion instructions
4141 //===----------------------------------------------------------------------===//
4142 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4143 X86MemOperand x86memop> {
4144 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4145 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4147 let hasSideEffects = 0, mayLoad = 1 in
4148 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4149 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4152 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4153 X86MemOperand x86memop> {
4154 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4155 (ins srcRC:$src1, i32i8imm:$src2),
4156 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4158 let hasSideEffects = 0, mayStore = 1 in
4159 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4160 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
4161 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4164 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4165 EVEX_CD8<32, CD8VH>;
4166 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4167 EVEX_CD8<32, CD8VH>;
4169 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4170 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4171 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4173 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4174 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4175 (VCVTPH2PSZrr VR256X:$src)>;
4177 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4178 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4179 "ucomiss">, PS, EVEX, VEX_LIG,
4180 EVEX_CD8<32, CD8VT1>;
4181 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4182 "ucomisd">, PD, EVEX,
4183 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4184 let Pattern = []<dag> in {
4185 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4186 "comiss">, PS, EVEX, VEX_LIG,
4187 EVEX_CD8<32, CD8VT1>;
4188 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4189 "comisd">, PD, EVEX,
4190 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4192 let isCodeGenOnly = 1 in {
4193 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4194 load, "ucomiss">, PS, EVEX, VEX_LIG,
4195 EVEX_CD8<32, CD8VT1>;
4196 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4197 load, "ucomisd">, PD, EVEX,
4198 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4200 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4201 load, "comiss">, PS, EVEX, VEX_LIG,
4202 EVEX_CD8<32, CD8VT1>;
4203 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4204 load, "comisd">, PD, EVEX,
4205 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4209 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4210 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4211 X86MemOperand x86memop> {
4212 let hasSideEffects = 0 in {
4213 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4214 (ins RC:$src1, RC:$src2),
4215 !strconcat(OpcodeStr,
4216 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4217 let mayLoad = 1 in {
4218 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4219 (ins RC:$src1, x86memop:$src2),
4220 !strconcat(OpcodeStr,
4221 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4226 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4227 EVEX_CD8<32, CD8VT1>;
4228 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4229 VEX_W, EVEX_CD8<64, CD8VT1>;
4230 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4231 EVEX_CD8<32, CD8VT1>;
4232 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4233 VEX_W, EVEX_CD8<64, CD8VT1>;
4235 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4236 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4237 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4238 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4240 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4241 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4242 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4243 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4245 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4246 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4247 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4248 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4250 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4251 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4252 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4253 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4255 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4256 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4257 X86VectorVTInfo _> {
4258 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4259 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4260 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4261 let mayLoad = 1 in {
4262 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4263 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4265 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4266 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4267 (ins _.ScalarMemOp:$src), OpcodeStr,
4268 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4270 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4275 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4276 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4277 EVEX_V512, EVEX_CD8<32, CD8VF>;
4278 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4279 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4281 // Define only if AVX512VL feature is present.
4282 let Predicates = [HasVLX] in {
4283 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4284 OpNode, v4f32x_info>,
4285 EVEX_V128, EVEX_CD8<32, CD8VF>;
4286 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4287 OpNode, v8f32x_info>,
4288 EVEX_V256, EVEX_CD8<32, CD8VF>;
4289 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4290 OpNode, v2f64x_info>,
4291 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4292 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4293 OpNode, v4f64x_info>,
4294 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4298 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4299 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4301 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4302 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4303 (VRSQRT14PSZr VR512:$src)>;
4304 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4305 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4306 (VRSQRT14PDZr VR512:$src)>;
4308 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4309 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4310 (VRCP14PSZr VR512:$src)>;
4311 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4312 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4313 (VRCP14PDZr VR512:$src)>;
4315 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4316 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4319 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4320 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4321 "$src2, $src1", "$src1, $src2",
4322 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4323 (i32 FROUND_CURRENT))>;
4325 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4326 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4327 "$src2, $src1", "$src1, $src2",
4328 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4329 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4331 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4332 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4333 "$src2, $src1", "$src1, $src2",
4334 (OpNode (_.VT _.RC:$src1),
4335 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4336 (i32 FROUND_CURRENT))>;
4339 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4340 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4341 EVEX_CD8<32, CD8VT1>;
4342 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4343 EVEX_CD8<64, CD8VT1>, VEX_W;
4346 let hasSideEffects = 0, Predicates = [HasERI] in {
4347 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4348 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4350 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4352 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4355 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4356 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4357 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4359 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4360 (ins _.RC:$src), OpcodeStr,
4362 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4365 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4366 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4368 (bitconvert (_.LdFrag addr:$src))),
4369 (i32 FROUND_CURRENT))>;
4371 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4372 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4374 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4375 (i32 FROUND_CURRENT))>, EVEX_B;
4378 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4379 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4380 EVEX_CD8<32, CD8VF>;
4381 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4382 VEX_W, EVEX_CD8<32, CD8VF>;
4385 let Predicates = [HasERI], hasSideEffects = 0 in {
4387 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4388 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4389 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4392 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4393 SDNode OpNode, X86VectorVTInfo _>{
4394 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4395 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4396 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4397 let mayLoad = 1 in {
4398 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4399 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4401 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4403 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4404 (ins _.ScalarMemOp:$src), OpcodeStr,
4405 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4407 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4412 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4413 Intrinsic F32Int, Intrinsic F64Int,
4414 OpndItins itins_s, OpndItins itins_d> {
4415 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4416 (ins FR32X:$src1, FR32X:$src2),
4417 !strconcat(OpcodeStr,
4418 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4419 [], itins_s.rr>, XS, EVEX_4V;
4420 let isCodeGenOnly = 1 in
4421 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4422 (ins VR128X:$src1, VR128X:$src2),
4423 !strconcat(OpcodeStr,
4424 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4426 (F32Int VR128X:$src1, VR128X:$src2))],
4427 itins_s.rr>, XS, EVEX_4V;
4428 let mayLoad = 1 in {
4429 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4430 (ins FR32X:$src1, f32mem:$src2),
4431 !strconcat(OpcodeStr,
4432 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4433 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4434 let isCodeGenOnly = 1 in
4435 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4436 (ins VR128X:$src1, ssmem:$src2),
4437 !strconcat(OpcodeStr,
4438 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4440 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4441 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4443 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4444 (ins FR64X:$src1, FR64X:$src2),
4445 !strconcat(OpcodeStr,
4446 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4448 let isCodeGenOnly = 1 in
4449 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4450 (ins VR128X:$src1, VR128X:$src2),
4451 !strconcat(OpcodeStr,
4452 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4454 (F64Int VR128X:$src1, VR128X:$src2))],
4455 itins_s.rr>, XD, EVEX_4V, VEX_W;
4456 let mayLoad = 1 in {
4457 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4458 (ins FR64X:$src1, f64mem:$src2),
4459 !strconcat(OpcodeStr,
4460 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4461 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4462 let isCodeGenOnly = 1 in
4463 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4464 (ins VR128X:$src1, sdmem:$src2),
4465 !strconcat(OpcodeStr,
4466 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4468 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4469 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4473 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4475 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4477 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4478 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4480 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4481 // Define only if AVX512VL feature is present.
4482 let Predicates = [HasVLX] in {
4483 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4484 OpNode, v4f32x_info>,
4485 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4486 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4487 OpNode, v8f32x_info>,
4488 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4489 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4490 OpNode, v2f64x_info>,
4491 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4492 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4493 OpNode, v4f64x_info>,
4494 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4498 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4500 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4501 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4502 SSE_SQRTSS, SSE_SQRTSD>;
4504 let Predicates = [HasAVX512] in {
4505 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4506 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4507 (VSQRTPSZr VR512:$src1)>;
4508 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4509 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4510 (VSQRTPDZr VR512:$src1)>;
4512 def : Pat<(f32 (fsqrt FR32X:$src)),
4513 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4514 def : Pat<(f32 (fsqrt (load addr:$src))),
4515 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4516 Requires<[OptForSize]>;
4517 def : Pat<(f64 (fsqrt FR64X:$src)),
4518 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4519 def : Pat<(f64 (fsqrt (load addr:$src))),
4520 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4521 Requires<[OptForSize]>;
4523 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4524 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4525 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4526 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4527 Requires<[OptForSize]>;
4529 def : Pat<(f32 (X86frcp FR32X:$src)),
4530 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4531 def : Pat<(f32 (X86frcp (load addr:$src))),
4532 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4533 Requires<[OptForSize]>;
4535 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4536 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4537 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4539 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4540 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4542 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4543 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4544 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4546 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4547 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4551 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4552 X86MemOperand x86memop, RegisterClass RC,
4553 PatFrag mem_frag32, PatFrag mem_frag64,
4554 Intrinsic V4F32Int, Intrinsic V2F64Int,
4556 let ExeDomain = SSEPackedSingle in {
4557 // Intrinsic operation, reg.
4558 // Vector intrinsic operation, reg
4559 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4560 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4561 !strconcat(OpcodeStr,
4562 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4563 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4565 // Vector intrinsic operation, mem
4566 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4567 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4568 !strconcat(OpcodeStr,
4569 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4571 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4572 EVEX_CD8<32, VForm>;
4573 } // ExeDomain = SSEPackedSingle
4575 let ExeDomain = SSEPackedDouble in {
4576 // Vector intrinsic operation, reg
4577 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4578 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4579 !strconcat(OpcodeStr,
4580 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4581 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4583 // Vector intrinsic operation, mem
4584 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4585 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4586 !strconcat(OpcodeStr,
4587 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4589 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4590 EVEX_CD8<64, VForm>;
4591 } // ExeDomain = SSEPackedDouble
4594 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4598 let ExeDomain = GenericDomain in {
4600 let hasSideEffects = 0 in
4601 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4602 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4603 !strconcat(OpcodeStr,
4604 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4607 // Intrinsic operation, reg.
4608 let isCodeGenOnly = 1 in
4609 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4610 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4611 !strconcat(OpcodeStr,
4612 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4613 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4615 // Intrinsic operation, mem.
4616 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4617 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4618 !strconcat(OpcodeStr,
4619 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4620 [(set VR128X:$dst, (F32Int VR128X:$src1,
4621 sse_load_f32:$src2, imm:$src3))]>,
4622 EVEX_CD8<32, CD8VT1>;
4625 let hasSideEffects = 0 in
4626 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4627 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4628 !strconcat(OpcodeStr,
4629 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4632 // Intrinsic operation, reg.
4633 let isCodeGenOnly = 1 in
4634 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4635 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4636 !strconcat(OpcodeStr,
4637 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4638 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4641 // Intrinsic operation, mem.
4642 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4643 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4644 !strconcat(OpcodeStr,
4645 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4647 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4648 VEX_W, EVEX_CD8<64, CD8VT1>;
4649 } // ExeDomain = GenericDomain
4652 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4653 X86MemOperand x86memop, RegisterClass RC,
4654 PatFrag mem_frag, Domain d> {
4655 let ExeDomain = d in {
4656 // Intrinsic operation, reg.
4657 // Vector intrinsic operation, reg
4658 def r : AVX512AIi8<opc, MRMSrcReg,
4659 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4660 !strconcat(OpcodeStr,
4661 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4664 // Vector intrinsic operation, mem
4665 def m : AVX512AIi8<opc, MRMSrcMem,
4666 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4667 !strconcat(OpcodeStr,
4668 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4674 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4675 memopv16f32, SSEPackedSingle>, EVEX_V512,
4676 EVEX_CD8<32, CD8VF>;
4678 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4679 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4681 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4684 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4685 memopv8f64, SSEPackedDouble>, EVEX_V512,
4686 VEX_W, EVEX_CD8<64, CD8VF>;
4688 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4689 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4691 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4693 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4694 Operand x86memop, RegisterClass RC, Domain d> {
4695 let ExeDomain = d in {
4696 def r : AVX512AIi8<opc, MRMSrcReg,
4697 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4698 !strconcat(OpcodeStr,
4699 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4702 def m : AVX512AIi8<opc, MRMSrcMem,
4703 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4704 !strconcat(OpcodeStr,
4705 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4710 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4711 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4713 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4714 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4716 def : Pat<(ffloor FR32X:$src),
4717 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4718 def : Pat<(f64 (ffloor FR64X:$src)),
4719 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4720 def : Pat<(f32 (fnearbyint FR32X:$src)),
4721 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4722 def : Pat<(f64 (fnearbyint FR64X:$src)),
4723 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4724 def : Pat<(f32 (fceil FR32X:$src)),
4725 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4726 def : Pat<(f64 (fceil FR64X:$src)),
4727 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4728 def : Pat<(f32 (frint FR32X:$src)),
4729 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4730 def : Pat<(f64 (frint FR64X:$src)),
4731 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4732 def : Pat<(f32 (ftrunc FR32X:$src)),
4733 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4734 def : Pat<(f64 (ftrunc FR64X:$src)),
4735 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4737 def : Pat<(v16f32 (ffloor VR512:$src)),
4738 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4739 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4740 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4741 def : Pat<(v16f32 (fceil VR512:$src)),
4742 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4743 def : Pat<(v16f32 (frint VR512:$src)),
4744 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4745 def : Pat<(v16f32 (ftrunc VR512:$src)),
4746 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4748 def : Pat<(v8f64 (ffloor VR512:$src)),
4749 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4750 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4751 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4752 def : Pat<(v8f64 (fceil VR512:$src)),
4753 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4754 def : Pat<(v8f64 (frint VR512:$src)),
4755 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4756 def : Pat<(v8f64 (ftrunc VR512:$src)),
4757 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4759 //-------------------------------------------------
4760 // Integer truncate and extend operations
4761 //-------------------------------------------------
4763 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4764 RegisterClass dstRC, RegisterClass srcRC,
4765 RegisterClass KRC, X86MemOperand x86memop> {
4766 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4768 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4771 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4772 (ins KRC:$mask, srcRC:$src),
4773 !strconcat(OpcodeStr,
4774 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4777 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4778 (ins KRC:$mask, srcRC:$src),
4779 !strconcat(OpcodeStr,
4780 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4783 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4784 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4787 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4788 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4789 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4793 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4794 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4795 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4796 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4797 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4798 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4799 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4800 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4801 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4802 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4803 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4804 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4805 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4806 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4807 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4808 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4809 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4810 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4811 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4812 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4813 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4814 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4815 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4816 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4817 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4818 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4819 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4820 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4821 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4822 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4824 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4825 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4826 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4827 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4828 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4830 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4831 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4832 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4833 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4834 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4835 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4836 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4837 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4840 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4841 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4842 PatFrag mem_frag, X86MemOperand x86memop,
4843 ValueType OpVT, ValueType InVT> {
4845 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4848 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4850 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4851 (ins KRC:$mask, SrcRC:$src),
4852 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4855 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4856 (ins KRC:$mask, SrcRC:$src),
4857 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4860 let mayLoad = 1 in {
4861 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4862 (ins x86memop:$src),
4863 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4865 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4868 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4869 (ins KRC:$mask, x86memop:$src),
4870 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4874 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4875 (ins KRC:$mask, x86memop:$src),
4876 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4882 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4883 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4885 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4886 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4888 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4889 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4890 EVEX_CD8<16, CD8VH>;
4891 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4892 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4893 EVEX_CD8<16, CD8VQ>;
4894 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4895 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4896 EVEX_CD8<32, CD8VH>;
4898 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4899 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4901 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4902 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4904 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4905 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4906 EVEX_CD8<16, CD8VH>;
4907 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4908 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4909 EVEX_CD8<16, CD8VQ>;
4910 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4911 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4912 EVEX_CD8<32, CD8VH>;
4914 //===----------------------------------------------------------------------===//
4915 // GATHER - SCATTER Operations
4917 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4918 RegisterClass RC, X86MemOperand memop> {
4920 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4921 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4922 (ins RC:$src1, KRC:$mask, memop:$src2),
4923 !strconcat(OpcodeStr,
4924 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4928 let ExeDomain = SSEPackedDouble in {
4929 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4930 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4931 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4932 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4935 let ExeDomain = SSEPackedSingle in {
4936 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4937 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4938 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4939 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4942 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4943 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4944 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4945 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4947 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4948 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4949 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4950 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4952 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4953 RegisterClass RC, X86MemOperand memop> {
4954 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4955 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4956 (ins memop:$dst, KRC:$mask, RC:$src2),
4957 !strconcat(OpcodeStr,
4958 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4962 let ExeDomain = SSEPackedDouble in {
4963 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4964 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4965 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4966 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4969 let ExeDomain = SSEPackedSingle in {
4970 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4971 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4972 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4973 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4976 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4977 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4978 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4979 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4981 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4982 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4983 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4984 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4987 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4988 RegisterClass KRC, X86MemOperand memop> {
4989 let Predicates = [HasPFI], hasSideEffects = 1 in
4990 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4991 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4995 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4996 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4998 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4999 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5001 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5002 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5004 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
5005 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5007 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
5008 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5010 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
5011 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5013 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5014 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5016 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5017 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5019 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5020 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5022 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5023 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5025 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5026 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5028 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5029 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5031 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5032 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5034 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5035 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5037 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5038 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5040 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5041 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5042 //===----------------------------------------------------------------------===//
5043 // VSHUFPS - VSHUFPD Operations
5045 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5046 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5048 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5049 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
5050 !strconcat(OpcodeStr,
5051 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5052 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5053 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5054 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5055 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5056 (ins RC:$src1, RC:$src2, i8imm:$src3),
5057 !strconcat(OpcodeStr,
5058 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5059 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5060 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5061 EVEX_4V, Sched<[WriteShuffle]>;
5064 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
5065 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5066 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
5067 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5069 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5070 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5071 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5072 (memopv16i32 addr:$src2), (i8 imm:$imm))),
5073 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5075 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5076 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5077 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5078 (memopv8i64 addr:$src2), (i8 imm:$imm))),
5079 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5081 multiclass avx512_valign<X86VectorVTInfo _> {
5082 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5083 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
5085 "$src3, $src2, $src1", "$src1, $src2, $src3",
5086 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5088 AVX512AIi8Base, EVEX_4V;
5090 // Also match valign of packed floats.
5091 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5092 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5095 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5096 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
5097 !strconcat("valign"##_.Suffix,
5098 "\t{$src3, $src2, $src1, $dst|"
5099 "$dst, $src1, $src2, $src3}"),
5102 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5103 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5105 // Helper fragments to match sext vXi1 to vXiY.
5106 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5107 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5109 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5110 RegisterClass KRC, RegisterClass RC,
5111 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5113 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5116 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5117 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5119 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5120 !strconcat(OpcodeStr,
5121 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5123 let mayLoad = 1 in {
5124 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5125 (ins x86memop:$src),
5126 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5128 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5129 (ins KRC:$mask, x86memop:$src),
5130 !strconcat(OpcodeStr,
5131 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5133 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5134 (ins KRC:$mask, x86memop:$src),
5135 !strconcat(OpcodeStr,
5136 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5138 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5139 (ins x86scalar_mop:$src),
5140 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5141 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5143 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5144 (ins KRC:$mask, x86scalar_mop:$src),
5145 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5146 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5147 []>, EVEX, EVEX_B, EVEX_K;
5148 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5149 (ins KRC:$mask, x86scalar_mop:$src),
5150 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5151 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5153 []>, EVEX, EVEX_B, EVEX_KZ;
5157 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5158 i512mem, i32mem, "{1to16}">, EVEX_V512,
5159 EVEX_CD8<32, CD8VF>;
5160 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5161 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5162 EVEX_CD8<64, CD8VF>;
5165 (bc_v16i32 (v16i1sextv16i32)),
5166 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5167 (VPABSDZrr VR512:$src)>;
5169 (bc_v8i64 (v8i1sextv8i64)),
5170 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5171 (VPABSQZrr VR512:$src)>;
5173 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5174 (v16i32 immAllZerosV), (i16 -1))),
5175 (VPABSDZrr VR512:$src)>;
5176 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5177 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5178 (VPABSQZrr VR512:$src)>;
5180 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5181 RegisterClass RC, RegisterClass KRC,
5182 X86MemOperand x86memop,
5183 X86MemOperand x86scalar_mop, string BrdcstStr> {
5184 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5186 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5188 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5189 (ins x86memop:$src),
5190 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5192 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5193 (ins x86scalar_mop:$src),
5194 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5195 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5197 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5198 (ins KRC:$mask, RC:$src),
5199 !strconcat(OpcodeStr,
5200 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5202 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5203 (ins KRC:$mask, x86memop:$src),
5204 !strconcat(OpcodeStr,
5205 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5207 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5208 (ins KRC:$mask, x86scalar_mop:$src),
5209 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5210 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5212 []>, EVEX, EVEX_KZ, EVEX_B;
5214 let Constraints = "$src1 = $dst" in {
5215 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5216 (ins RC:$src1, KRC:$mask, RC:$src2),
5217 !strconcat(OpcodeStr,
5218 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5220 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5221 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5222 !strconcat(OpcodeStr,
5223 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5225 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5226 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5227 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5228 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5229 []>, EVEX, EVEX_K, EVEX_B;
5233 let Predicates = [HasCDI] in {
5234 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5235 i512mem, i32mem, "{1to16}">,
5236 EVEX_V512, EVEX_CD8<32, CD8VF>;
5239 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5240 i512mem, i64mem, "{1to8}">,
5241 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5245 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5247 (VPCONFLICTDrrk VR512:$src1,
5248 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5250 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5252 (VPCONFLICTQrrk VR512:$src1,
5253 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5255 let Predicates = [HasCDI] in {
5256 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5257 i512mem, i32mem, "{1to16}">,
5258 EVEX_V512, EVEX_CD8<32, CD8VF>;
5261 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5262 i512mem, i64mem, "{1to8}">,
5263 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5267 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5269 (VPLZCNTDrrk VR512:$src1,
5270 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5272 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5274 (VPLZCNTQrrk VR512:$src1,
5275 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5277 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5278 (VPLZCNTDrm addr:$src)>;
5279 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5280 (VPLZCNTDrr VR512:$src)>;
5281 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5282 (VPLZCNTQrm addr:$src)>;
5283 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5284 (VPLZCNTQrr VR512:$src)>;
5286 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5287 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5288 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5290 def : Pat<(store VK1:$src, addr:$dst),
5291 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5293 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5294 (truncstore node:$val, node:$ptr), [{
5295 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5298 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5299 (MOV8mr addr:$dst, GR8:$src)>;
5301 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5302 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5303 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5304 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5307 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5308 string OpcodeStr, Predicate prd> {
5309 let Predicates = [prd] in
5310 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5312 let Predicates = [prd, HasVLX] in {
5313 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5314 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5318 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5319 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5321 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5323 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5325 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5329 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5331 //===----------------------------------------------------------------------===//
5332 // AVX-512 - COMPRESS and EXPAND
5334 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5336 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5337 (ins _.KRCWM:$mask, _.RC:$src),
5338 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5339 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5340 _.ImmAllZerosV)))]>, EVEX_KZ;
5342 let Constraints = "$src0 = $dst" in
5343 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5344 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5345 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5346 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5347 _.RC:$src0)))]>, EVEX_K;
5349 let mayStore = 1 in {
5350 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5351 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5352 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5353 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5355 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5359 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5360 AVX512VLVectorVTInfo VTInfo> {
5361 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5363 let Predicates = [HasVLX] in {
5364 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5365 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5369 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5371 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5373 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5375 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5379 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5381 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5382 (ins _.KRCWM:$mask, _.RC:$src),
5383 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5384 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5385 _.ImmAllZerosV)))]>, EVEX_KZ;
5387 let Constraints = "$src0 = $dst" in
5388 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5389 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5390 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5391 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5392 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5394 let mayLoad = 1, Constraints = "$src0 = $dst" in
5395 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5396 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5397 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5398 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5400 (_.LdFrag addr:$src))),
5402 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5405 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5406 (ins _.KRCWM:$mask, _.MemOp:$src),
5407 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5408 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5409 (_.VT (bitconvert (_.LdFrag addr:$src))),
5410 _.ImmAllZerosV)))]>,
5411 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5415 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5416 AVX512VLVectorVTInfo VTInfo> {
5417 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5419 let Predicates = [HasVLX] in {
5420 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5421 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5425 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5427 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5429 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5431 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,