1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 // Similar to AVX512_maskable_3rc but in this case the input VT for the tied
280 // operand differs from the output VT. This requires a bitconvert on
281 // the preserved vector going into the vselect.
282 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
283 X86VectorVTInfo InVT,
284 dag Outs, dag NonTiedIns, string OpcodeStr,
285 string AttSrcAsm, string IntelSrcAsm,
287 AVX512_maskable_common<O, F, OutVT, Outs,
288 !con((ins InVT.RC:$src1), NonTiedIns),
289 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
290 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
291 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
292 (vselect InVT.KRCWM:$mask, RHS,
293 (bitconvert InVT.RC:$src1))>;
295 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
296 dag Outs, dag NonTiedIns, string OpcodeStr,
297 string AttSrcAsm, string IntelSrcAsm,
299 AVX512_maskable_common<O, F, _, Outs,
300 !con((ins _.RC:$src1), NonTiedIns),
301 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
302 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
303 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
304 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
306 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
309 string AttSrcAsm, string IntelSrcAsm,
311 AVX512_maskable_custom<O, F, Outs, Ins,
312 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
313 !con((ins _.KRCWM:$mask), Ins),
314 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
318 // Instruction with mask that puts result in mask register,
319 // like "compare" and "vptest"
320 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
322 dag Ins, dag MaskingIns,
324 string AttSrcAsm, string IntelSrcAsm,
326 list<dag> MaskingPattern,
328 InstrItinClass itin = NoItinerary> {
329 def NAME: AVX512<O, F, Outs, Ins,
330 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
331 "$dst "#Round#", "#IntelSrcAsm#"}",
334 def NAME#k: AVX512<O, F, Outs, MaskingIns,
335 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
336 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
337 MaskingPattern, itin>, EVEX_K;
340 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
342 dag Ins, dag MaskingIns,
344 string AttSrcAsm, string IntelSrcAsm,
345 dag RHS, dag MaskingRHS,
347 InstrItinClass itin = NoItinerary> :
348 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
349 AttSrcAsm, IntelSrcAsm,
350 [(set _.KRC:$dst, RHS)],
351 [(set _.KRC:$dst, MaskingRHS)],
354 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
355 dag Outs, dag Ins, string OpcodeStr,
356 string AttSrcAsm, string IntelSrcAsm,
357 dag RHS, string Round = "",
358 InstrItinClass itin = NoItinerary> :
359 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
360 !con((ins _.KRCWM:$mask), Ins),
361 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
362 (and _.KRCWM:$mask, RHS),
365 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
366 dag Outs, dag Ins, string OpcodeStr,
367 string AttSrcAsm, string IntelSrcAsm> :
368 AVX512_maskable_custom_cmp<O, F, Outs,
369 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
370 AttSrcAsm, IntelSrcAsm,
371 [],[],"", NoItinerary>;
373 // Bitcasts between 512-bit vector types. Return the original type since
374 // no instruction is needed for the conversion
375 let Predicates = [HasAVX512] in {
376 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
377 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
378 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
379 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
380 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
381 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
382 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
383 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
384 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
385 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
386 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
387 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
388 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
389 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
390 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
391 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
392 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
393 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
394 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
395 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
396 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
397 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
398 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
399 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
400 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
401 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
402 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
403 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
404 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
405 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
406 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
408 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
409 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
410 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
411 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
412 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
413 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
414 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
415 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
416 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
417 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
418 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
419 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
420 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
421 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
422 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
423 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
424 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
425 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
426 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
427 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
428 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
429 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
430 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
431 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
432 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
433 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
434 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
435 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
436 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
437 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
439 // Bitcasts between 256-bit vector types. Return the original type since
440 // no instruction is needed for the conversion
441 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
442 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
443 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
444 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
445 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
446 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
447 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
448 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
449 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
450 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
451 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
452 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
453 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
454 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
455 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
456 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
457 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
458 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
459 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
460 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
461 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
462 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
463 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
464 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
465 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
466 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
467 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
468 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
469 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
470 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
474 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
477 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
478 isPseudo = 1, Predicates = [HasAVX512] in {
479 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
480 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
483 let Predicates = [HasAVX512] in {
484 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
485 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
486 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
489 //===----------------------------------------------------------------------===//
490 // AVX-512 - VECTOR INSERT
492 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
493 PatFrag vinsert_insert> {
494 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
495 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
496 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
497 "vinsert" # From.EltTypeName # "x" # From.NumElts,
498 "$src3, $src2, $src1", "$src1, $src2, $src3",
499 (vinsert_insert:$src3 (To.VT To.RC:$src1),
500 (From.VT From.RC:$src2),
501 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
504 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
505 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
506 "vinsert" # From.EltTypeName # "x" # From.NumElts,
507 "$src3, $src2, $src1", "$src1, $src2, $src3",
508 (vinsert_insert:$src3 (To.VT To.RC:$src1),
509 (From.VT (bitconvert (From.LdFrag addr:$src2))),
510 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
511 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
515 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
516 X86VectorVTInfo To, PatFrag vinsert_insert,
517 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
518 let Predicates = p in {
519 def : Pat<(vinsert_insert:$ins
520 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
521 (To.VT (!cast<Instruction>(InstrStr#"rr")
522 To.RC:$src1, From.RC:$src2,
523 (INSERT_get_vinsert_imm To.RC:$ins)))>;
525 def : Pat<(vinsert_insert:$ins
527 (From.VT (bitconvert (From.LdFrag addr:$src2))),
529 (To.VT (!cast<Instruction>(InstrStr#"rm")
530 To.RC:$src1, addr:$src2,
531 (INSERT_get_vinsert_imm To.RC:$ins)))>;
535 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
536 ValueType EltVT64, int Opcode256> {
538 let Predicates = [HasVLX] in
539 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 4, EltVT32, VR128X>,
541 X86VectorVTInfo< 8, EltVT32, VR256X>,
542 vinsert128_insert>, EVEX_V256;
544 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
545 X86VectorVTInfo< 4, EltVT32, VR128X>,
546 X86VectorVTInfo<16, EltVT32, VR512>,
547 vinsert128_insert>, EVEX_V512;
549 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
550 X86VectorVTInfo< 4, EltVT64, VR256X>,
551 X86VectorVTInfo< 8, EltVT64, VR512>,
552 vinsert256_insert>, VEX_W, EVEX_V512;
554 let Predicates = [HasVLX, HasDQI] in
555 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
556 X86VectorVTInfo< 2, EltVT64, VR128X>,
557 X86VectorVTInfo< 4, EltVT64, VR256X>,
558 vinsert128_insert>, VEX_W, EVEX_V256;
560 let Predicates = [HasDQI] in {
561 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
562 X86VectorVTInfo< 2, EltVT64, VR128X>,
563 X86VectorVTInfo< 8, EltVT64, VR512>,
564 vinsert128_insert>, VEX_W, EVEX_V512;
566 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
567 X86VectorVTInfo< 8, EltVT32, VR256X>,
568 X86VectorVTInfo<16, EltVT32, VR512>,
569 vinsert256_insert>, EVEX_V512;
573 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
574 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
576 // Codegen pattern with the alternative types,
577 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
578 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
583 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
588 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
593 // Codegen pattern with the alternative types insert VEC128 into VEC256
594 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
595 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
596 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
597 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
598 // Codegen pattern with the alternative types insert VEC128 into VEC512
599 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
600 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
601 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
602 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
603 // Codegen pattern with the alternative types insert VEC256 into VEC512
604 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
605 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
606 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
607 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
609 // vinsertps - insert f32 to XMM
610 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
611 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
612 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
613 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
615 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
616 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
617 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
618 [(set VR128X:$dst, (X86insertps VR128X:$src1,
619 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
620 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
622 //===----------------------------------------------------------------------===//
623 // AVX-512 VECTOR EXTRACT
626 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
627 X86VectorVTInfo To> {
628 // A subvector extract from the first vector position is
629 // a subregister copy that needs no instruction.
630 def NAME # To.NumElts:
631 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
632 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
635 multiclass vextract_for_size<int Opcode,
636 X86VectorVTInfo From, X86VectorVTInfo To,
637 PatFrag vextract_extract> :
638 vextract_for_size_first_position_lowering<From, To> {
640 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
641 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
642 // vextract_extract), we interesting only in patterns without mask,
643 // intrinsics pattern match generated bellow.
644 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
645 (ins From.RC:$src1, i32u8imm:$idx),
646 "vextract" # To.EltTypeName # "x" # To.NumElts,
647 "$idx, $src1", "$src1, $idx",
648 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
650 AVX512AIi8Base, EVEX;
651 let mayStore = 1 in {
652 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
653 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
654 "vextract" # To.EltTypeName # "x" # To.NumElts #
655 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
658 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
659 (ins To.MemOp:$dst, To.KRCWM:$mask,
660 From.RC:$src1, i32u8imm:$src2),
661 "vextract" # To.EltTypeName # "x" # To.NumElts #
662 "\t{$src2, $src1, $dst {${mask}}|"
663 "$dst {${mask}}, $src1, $src2}",
668 // Intrinsic call with masking.
669 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
670 "x" # To.NumElts # "_" # From.Size)
671 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
672 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
673 From.ZSuffix # "rrk")
675 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
676 From.RC:$src1, imm:$idx)>;
678 // Intrinsic call with zero-masking.
679 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
680 "x" # To.NumElts # "_" # From.Size)
681 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
682 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
683 From.ZSuffix # "rrkz")
684 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
685 From.RC:$src1, imm:$idx)>;
687 // Intrinsic call without masking.
688 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
689 "x" # To.NumElts # "_" # From.Size)
690 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
691 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
693 From.RC:$src1, imm:$idx)>;
696 // Codegen pattern for the alternative types
697 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
698 X86VectorVTInfo To, PatFrag vextract_extract,
699 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
700 vextract_for_size_first_position_lowering<From, To> {
702 let Predicates = p in
703 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
704 (To.VT (!cast<Instruction>(InstrStr#"rr")
706 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
709 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
710 ValueType EltVT64, int Opcode256> {
711 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
712 X86VectorVTInfo<16, EltVT32, VR512>,
713 X86VectorVTInfo< 4, EltVT32, VR128X>,
714 vextract128_extract>,
715 EVEX_V512, EVEX_CD8<32, CD8VT4>;
716 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
717 X86VectorVTInfo< 8, EltVT64, VR512>,
718 X86VectorVTInfo< 4, EltVT64, VR256X>,
719 vextract256_extract>,
720 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
721 let Predicates = [HasVLX] in
722 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
723 X86VectorVTInfo< 8, EltVT32, VR256X>,
724 X86VectorVTInfo< 4, EltVT32, VR128X>,
725 vextract128_extract>,
726 EVEX_V256, EVEX_CD8<32, CD8VT4>;
727 let Predicates = [HasVLX, HasDQI] in
728 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
729 X86VectorVTInfo< 4, EltVT64, VR256X>,
730 X86VectorVTInfo< 2, EltVT64, VR128X>,
731 vextract128_extract>,
732 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
733 let Predicates = [HasDQI] in {
734 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
735 X86VectorVTInfo< 8, EltVT64, VR512>,
736 X86VectorVTInfo< 2, EltVT64, VR128X>,
737 vextract128_extract>,
738 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
739 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
740 X86VectorVTInfo<16, EltVT32, VR512>,
741 X86VectorVTInfo< 8, EltVT32, VR256X>,
742 vextract256_extract>,
743 EVEX_V512, EVEX_CD8<32, CD8VT8>;
747 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
748 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
750 // extract_subvector codegen patterns with the alternative types.
751 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
752 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
757 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
762 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
763 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
764 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
765 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
767 // Codegen pattern with the alternative types extract VEC128 from VEC512
768 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
769 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
770 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
771 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
772 // Codegen pattern with the alternative types extract VEC256 from VEC512
773 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
774 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
775 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
776 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
778 // A 128-bit subvector insert to the first 512-bit vector position
779 // is a subregister copy that needs no instruction.
780 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
781 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
782 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
784 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
785 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
786 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
788 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
789 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
790 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
792 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
793 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
794 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
797 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
798 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
799 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
800 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
801 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
802 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
803 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
804 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
805 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
806 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
807 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
808 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
810 // vextractps - extract 32 bits from XMM
811 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
812 (ins VR128X:$src1, u8imm:$src2),
813 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
817 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
818 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
819 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
820 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
821 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
823 //===---------------------------------------------------------------------===//
827 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
830 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
831 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
832 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
835 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
836 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
837 (DestInfo.VT (X86VBroadcast
838 (SrcInfo.ScalarLdFrag addr:$src)))>,
839 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
842 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
843 AVX512VLVectorVTInfo _> {
844 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
847 let Predicates = [HasVLX] in {
848 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
853 let ExeDomain = SSEPackedSingle in {
854 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
856 let Predicates = [HasVLX] in {
857 defm VBROADCASTSSZ128 : avx512_broadcast_rm<0x18, "vbroadcastss",
858 v4f32x_info, v4f32x_info>, EVEX_V128;
862 let ExeDomain = SSEPackedDouble in {
863 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, "vbroadcastsd",
864 avx512vl_f64_info>, VEX_W;
867 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
868 // Later, we can canonize broadcast instructions before ISel phase and
869 // eliminate additional patterns on ISel.
870 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
871 // representations of source
872 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
873 X86VectorVTInfo _, RegisterClass SrcRC_v,
874 RegisterClass SrcRC_s> {
875 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
876 (!cast<Instruction>(InstName##"r")
877 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
879 let AddedComplexity = 30 in {
880 def : Pat<(_.VT (vselect _.KRCWM:$mask,
881 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
882 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
883 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
885 def : Pat<(_.VT(vselect _.KRCWM:$mask,
886 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
887 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
888 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
892 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
894 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
897 let Predicates = [HasVLX] in {
898 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
899 v8f32x_info, VR128X, FR32X>;
900 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
901 v4f32x_info, VR128X, FR32X>;
902 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
903 v4f64x_info, VR128X, FR64X>;
906 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
907 (VBROADCASTSSZm addr:$src)>;
908 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
909 (VBROADCASTSDZm addr:$src)>;
911 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
912 (VBROADCASTSSZm addr:$src)>;
913 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
914 (VBROADCASTSDZm addr:$src)>;
916 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
917 RegisterClass SrcRC> {
918 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
919 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
920 "$src", "$src", []>, T8PD, EVEX;
923 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
924 RegisterClass SrcRC, Predicate prd> {
925 let Predicates = [prd] in
926 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
927 let Predicates = [prd, HasVLX] in {
928 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
929 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
933 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
935 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
937 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
939 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
942 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
943 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
945 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
946 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
948 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
949 (VPBROADCASTDrZr GR32:$src)>;
950 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
951 (VPBROADCASTQrZr GR64:$src)>;
953 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
954 (VPBROADCASTDrZr GR32:$src)>;
955 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
956 (VPBROADCASTQrZr GR64:$src)>;
958 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
959 (v16i32 immAllZerosV), (i16 GR16:$mask))),
960 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
961 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
962 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
963 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
965 // Provide aliases for broadcast from the same register class that
966 // automatically does the extract.
967 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
968 X86VectorVTInfo SrcInfo> {
969 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
970 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
971 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
974 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
975 AVX512VLVectorVTInfo _, Predicate prd> {
976 let Predicates = [prd] in {
977 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
978 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
980 // Defined separately to avoid redefinition.
981 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
983 let Predicates = [prd, HasVLX] in {
984 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
985 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
987 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
992 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
993 avx512vl_i8_info, HasBWI>;
994 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
995 avx512vl_i16_info, HasBWI>;
996 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
997 avx512vl_i32_info, HasAVX512>;
998 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
999 avx512vl_i64_info, HasAVX512>, VEX_W;
1001 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
1002 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
1004 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1005 (ins _Src.MemOp:$src), OpcodeStr, "$src", "$src",
1006 (_Dst.VT (X86SubVBroadcast
1007 (_Src.VT (bitconvert (_Src.LdFrag addr:$src)))))>,
1011 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1012 v16i32_info, v4i32x_info>,
1013 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1014 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1015 v16f32_info, v4f32x_info>,
1016 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1017 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1018 v8i64_info, v4i64x_info>, VEX_W,
1019 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1020 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1021 v8f64_info, v4f64x_info>, VEX_W,
1022 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1024 let Predicates = [HasVLX] in {
1025 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1026 v8i32x_info, v4i32x_info>,
1027 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1028 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1029 v8f32x_info, v4f32x_info>,
1030 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1032 let Predicates = [HasVLX, HasDQI] in {
1033 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1034 v4i64x_info, v2i64x_info>, VEX_W,
1035 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1036 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1037 v4f64x_info, v2f64x_info>, VEX_W,
1038 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1040 let Predicates = [HasDQI] in {
1041 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1042 v8i64_info, v2i64x_info>, VEX_W,
1043 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1044 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1045 v16i32_info, v8i32x_info>,
1046 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1047 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1048 v8f64_info, v2f64x_info>, VEX_W,
1049 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1050 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1051 v16f32_info, v8f32x_info>,
1052 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1055 multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
1056 X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
1057 SDNode OpNode = X86SubVBroadcast> {
1059 defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
1060 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
1061 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1064 defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1065 (ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
1067 (_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
1068 T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
1071 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1072 AVX512VLVectorVTInfo _> {
1073 let Predicates = [HasDQI] in
1074 defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
1076 let Predicates = [HasDQI, HasVLX] in
1077 defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
1081 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1082 AVX512VLVectorVTInfo _> :
1083 avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
1085 let Predicates = [HasDQI, HasVLX] in
1086 defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
1087 X86SubV32x2Broadcast>, EVEX_V128;
1090 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1092 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1095 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1096 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1097 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1098 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1100 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1101 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1102 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1103 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1105 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1106 (VBROADCASTSSZr VR128X:$src)>;
1107 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1108 (VBROADCASTSDZr VR128X:$src)>;
1110 // Provide fallback in case the load node that is used in the patterns above
1111 // is used by additional users, which prevents the pattern selection.
1112 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1113 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1114 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1115 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1118 //===----------------------------------------------------------------------===//
1119 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1121 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1122 X86VectorVTInfo _, RegisterClass KRC> {
1123 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1124 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1125 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1128 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1129 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1130 let Predicates = [HasCDI] in
1131 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1132 let Predicates = [HasCDI, HasVLX] in {
1133 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1134 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1138 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1139 avx512vl_i32_info, VK16>;
1140 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1141 avx512vl_i64_info, VK8>, VEX_W;
1143 //===----------------------------------------------------------------------===//
1144 // -- VPERMI2 - 3 source operands form --
1145 multiclass avx512_perm_i<bits<8> opc, string OpcodeStr,
1146 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1147 let Constraints = "$src1 = $dst" in {
1148 defm rr: AVX512_maskable_3src_cast<opc, MRMSrcReg, _, IdxVT, (outs _.RC:$dst),
1149 (ins _.RC:$src2, _.RC:$src3),
1150 OpcodeStr, "$src3, $src2", "$src2, $src3",
1151 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1155 defm rm: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1156 (ins _.RC:$src2, _.MemOp:$src3),
1157 OpcodeStr, "$src3, $src2", "$src2, $src3",
1158 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2,
1159 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1160 EVEX_4V, AVX5128IBase;
1163 multiclass avx512_perm_i_mb<bits<8> opc, string OpcodeStr,
1164 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1165 let mayLoad = 1, Constraints = "$src1 = $dst" in
1166 defm rmb: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1167 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1168 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1169 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1170 (_.VT (X86VPermi2X IdxVT.RC:$src1,
1171 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1172 AVX5128IBase, EVEX_4V, EVEX_B;
1175 multiclass avx512_perm_i_sizes<bits<8> opc, string OpcodeStr,
1176 AVX512VLVectorVTInfo VTInfo,
1177 AVX512VLVectorVTInfo ShuffleMask> {
1178 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1179 ShuffleMask.info512>,
1180 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info512,
1181 ShuffleMask.info512>, EVEX_V512;
1182 let Predicates = [HasVLX] in {
1183 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1184 ShuffleMask.info128>,
1185 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info128,
1186 ShuffleMask.info128>, EVEX_V128;
1187 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1188 ShuffleMask.info256>,
1189 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info256,
1190 ShuffleMask.info256>, EVEX_V256;
1194 multiclass avx512_perm_i_sizes_w<bits<8> opc, string OpcodeStr,
1195 AVX512VLVectorVTInfo VTInfo,
1196 AVX512VLVectorVTInfo Idx> {
1197 let Predicates = [HasBWI] in
1198 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1199 Idx.info512>, EVEX_V512;
1200 let Predicates = [HasBWI, HasVLX] in {
1201 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1202 Idx.info128>, EVEX_V128;
1203 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1204 Idx.info256>, EVEX_V256;
1208 defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d",
1209 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1210 defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q",
1211 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1212 defm VPERMI2W : avx512_perm_i_sizes_w<0x75, "vpermi2w",
1213 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1214 defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps",
1215 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1216 defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd",
1217 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1220 multiclass avx512_perm_t<bits<8> opc, string OpcodeStr,
1221 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1222 let Constraints = "$src1 = $dst" in {
1223 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1224 (ins IdxVT.RC:$src2, _.RC:$src3),
1225 OpcodeStr, "$src3, $src2", "$src2, $src3",
1226 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3))>, EVEX_4V,
1230 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1231 (ins IdxVT.RC:$src2, _.MemOp:$src3),
1232 OpcodeStr, "$src3, $src2", "$src2, $src3",
1233 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2,
1234 (bitconvert (_.LdFrag addr:$src3))))>,
1235 EVEX_4V, AVX5128IBase;
1238 multiclass avx512_perm_t_mb<bits<8> opc, string OpcodeStr,
1239 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1240 let mayLoad = 1, Constraints = "$src1 = $dst" in
1241 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1242 (ins IdxVT.RC:$src2, _.ScalarMemOp:$src3),
1243 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1244 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1245 (_.VT (X86VPermt2 _.RC:$src1,
1246 IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1247 AVX5128IBase, EVEX_4V, EVEX_B;
1250 multiclass avx512_perm_t_sizes<bits<8> opc, string OpcodeStr,
1251 AVX512VLVectorVTInfo VTInfo,
1252 AVX512VLVectorVTInfo ShuffleMask> {
1253 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1254 ShuffleMask.info512>,
1255 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info512,
1256 ShuffleMask.info512>, EVEX_V512;
1257 let Predicates = [HasVLX] in {
1258 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1259 ShuffleMask.info128>,
1260 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info128,
1261 ShuffleMask.info128>, EVEX_V128;
1262 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1263 ShuffleMask.info256>,
1264 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info256,
1265 ShuffleMask.info256>, EVEX_V256;
1269 multiclass avx512_perm_t_sizes_w<bits<8> opc, string OpcodeStr,
1270 AVX512VLVectorVTInfo VTInfo,
1271 AVX512VLVectorVTInfo Idx> {
1272 let Predicates = [HasBWI] in
1273 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1274 Idx.info512>, EVEX_V512;
1275 let Predicates = [HasBWI, HasVLX] in {
1276 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1277 Idx.info128>, EVEX_V128;
1278 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1279 Idx.info256>, EVEX_V256;
1283 defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d",
1284 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1285 defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q",
1286 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1287 defm VPERMT2W : avx512_perm_t_sizes_w<0x7D, "vpermt2w",
1288 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1289 defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps",
1290 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1291 defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd",
1292 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1294 //===----------------------------------------------------------------------===//
1295 // AVX-512 - BLEND using mask
1297 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1298 let ExeDomain = _.ExeDomain in {
1299 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1300 (ins _.RC:$src1, _.RC:$src2),
1301 !strconcat(OpcodeStr,
1302 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1304 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1305 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1306 !strconcat(OpcodeStr,
1307 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1308 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1309 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1310 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1311 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1312 !strconcat(OpcodeStr,
1313 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1314 []>, EVEX_4V, EVEX_KZ;
1315 let mayLoad = 1 in {
1316 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1317 (ins _.RC:$src1, _.MemOp:$src2),
1318 !strconcat(OpcodeStr,
1319 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1320 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1321 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1322 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1323 !strconcat(OpcodeStr,
1324 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1325 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1326 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1327 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1328 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1329 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1330 !strconcat(OpcodeStr,
1331 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1332 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1336 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1338 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1339 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1340 !strconcat(OpcodeStr,
1341 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1342 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1343 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1344 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1345 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1347 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1348 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1349 !strconcat(OpcodeStr,
1350 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1351 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1352 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1356 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1357 AVX512VLVectorVTInfo VTInfo> {
1358 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1359 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1361 let Predicates = [HasVLX] in {
1362 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1363 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1364 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1365 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1369 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1370 AVX512VLVectorVTInfo VTInfo> {
1371 let Predicates = [HasBWI] in
1372 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1374 let Predicates = [HasBWI, HasVLX] in {
1375 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1376 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1381 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1382 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1383 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1384 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1385 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1386 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1389 let Predicates = [HasAVX512] in {
1390 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1391 (v8f32 VR256X:$src2))),
1393 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1394 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1395 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1397 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1398 (v8i32 VR256X:$src2))),
1400 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1401 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1402 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1404 //===----------------------------------------------------------------------===//
1405 // Compare Instructions
1406 //===----------------------------------------------------------------------===//
1408 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1410 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1412 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1414 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1415 "vcmp${cc}"#_.Suffix,
1416 "$src2, $src1", "$src1, $src2",
1417 (OpNode (_.VT _.RC:$src1),
1421 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1423 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1424 "vcmp${cc}"#_.Suffix,
1425 "$src2, $src1", "$src1, $src2",
1426 (OpNode (_.VT _.RC:$src1),
1427 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1428 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1430 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1432 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1433 "vcmp${cc}"#_.Suffix,
1434 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1435 (OpNodeRnd (_.VT _.RC:$src1),
1438 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1439 // Accept explicit immediate argument form instead of comparison code.
1440 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1441 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1443 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1445 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1446 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1448 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1450 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1451 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1453 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1455 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1457 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1459 }// let isAsmParserOnly = 1, hasSideEffects = 0
1461 let isCodeGenOnly = 1 in {
1462 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1463 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1464 !strconcat("vcmp${cc}", _.Suffix,
1465 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1466 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1469 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1471 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1473 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1474 !strconcat("vcmp${cc}", _.Suffix,
1475 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1476 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1477 (_.ScalarLdFrag addr:$src2),
1479 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1483 let Predicates = [HasAVX512] in {
1484 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1486 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1487 AVX512XDIi8Base, VEX_W;
1490 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1491 X86VectorVTInfo _> {
1492 def rr : AVX512BI<opc, MRMSrcReg,
1493 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1494 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1495 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1496 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1498 def rm : AVX512BI<opc, MRMSrcMem,
1499 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1500 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1501 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1502 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1503 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1504 def rrk : AVX512BI<opc, MRMSrcReg,
1505 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1506 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1507 "$dst {${mask}}, $src1, $src2}"),
1508 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1509 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1510 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1512 def rmk : AVX512BI<opc, MRMSrcMem,
1513 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1514 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1515 "$dst {${mask}}, $src1, $src2}"),
1516 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1517 (OpNode (_.VT _.RC:$src1),
1519 (_.LdFrag addr:$src2))))))],
1520 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1523 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1524 X86VectorVTInfo _> :
1525 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1526 let mayLoad = 1 in {
1527 def rmb : AVX512BI<opc, MRMSrcMem,
1528 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1529 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1530 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1531 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1532 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1533 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1534 def rmbk : AVX512BI<opc, MRMSrcMem,
1535 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1536 _.ScalarMemOp:$src2),
1537 !strconcat(OpcodeStr,
1538 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1539 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1540 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1541 (OpNode (_.VT _.RC:$src1),
1543 (_.ScalarLdFrag addr:$src2)))))],
1544 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1548 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1549 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1550 let Predicates = [prd] in
1551 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1554 let Predicates = [prd, HasVLX] in {
1555 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1557 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1562 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1563 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1565 let Predicates = [prd] in
1566 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1569 let Predicates = [prd, HasVLX] in {
1570 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1572 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1577 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1578 avx512vl_i8_info, HasBWI>,
1581 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1582 avx512vl_i16_info, HasBWI>,
1583 EVEX_CD8<16, CD8VF>;
1585 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1586 avx512vl_i32_info, HasAVX512>,
1587 EVEX_CD8<32, CD8VF>;
1589 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1590 avx512vl_i64_info, HasAVX512>,
1591 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1593 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1594 avx512vl_i8_info, HasBWI>,
1597 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1598 avx512vl_i16_info, HasBWI>,
1599 EVEX_CD8<16, CD8VF>;
1601 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1602 avx512vl_i32_info, HasAVX512>,
1603 EVEX_CD8<32, CD8VF>;
1605 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1606 avx512vl_i64_info, HasAVX512>,
1607 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1609 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1610 (COPY_TO_REGCLASS (VPCMPGTDZrr
1611 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1612 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1614 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1615 (COPY_TO_REGCLASS (VPCMPEQDZrr
1616 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1617 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1619 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1620 X86VectorVTInfo _> {
1621 def rri : AVX512AIi8<opc, MRMSrcReg,
1622 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1623 !strconcat("vpcmp${cc}", Suffix,
1624 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1625 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1627 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1629 def rmi : AVX512AIi8<opc, MRMSrcMem,
1630 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1631 !strconcat("vpcmp${cc}", Suffix,
1632 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1633 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1634 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1636 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1637 def rrik : AVX512AIi8<opc, MRMSrcReg,
1638 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1640 !strconcat("vpcmp${cc}", Suffix,
1641 "\t{$src2, $src1, $dst {${mask}}|",
1642 "$dst {${mask}}, $src1, $src2}"),
1643 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1644 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1646 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1648 def rmik : AVX512AIi8<opc, MRMSrcMem,
1649 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1651 !strconcat("vpcmp${cc}", Suffix,
1652 "\t{$src2, $src1, $dst {${mask}}|",
1653 "$dst {${mask}}, $src1, $src2}"),
1654 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1655 (OpNode (_.VT _.RC:$src1),
1656 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1658 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1660 // Accept explicit immediate argument form instead of comparison code.
1661 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1662 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1663 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1664 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1665 "$dst, $src1, $src2, $cc}"),
1666 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1668 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1669 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1670 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1671 "$dst, $src1, $src2, $cc}"),
1672 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1673 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1674 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1676 !strconcat("vpcmp", Suffix,
1677 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1678 "$dst {${mask}}, $src1, $src2, $cc}"),
1679 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1681 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1682 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1684 !strconcat("vpcmp", Suffix,
1685 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1686 "$dst {${mask}}, $src1, $src2, $cc}"),
1687 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1691 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1692 X86VectorVTInfo _> :
1693 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1694 def rmib : AVX512AIi8<opc, MRMSrcMem,
1695 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1697 !strconcat("vpcmp${cc}", Suffix,
1698 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1699 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1700 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1701 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1703 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1704 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1705 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1706 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1707 !strconcat("vpcmp${cc}", Suffix,
1708 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1709 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1710 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1711 (OpNode (_.VT _.RC:$src1),
1712 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1714 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1716 // Accept explicit immediate argument form instead of comparison code.
1717 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1718 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1719 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1721 !strconcat("vpcmp", Suffix,
1722 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1723 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1724 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1725 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1726 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1727 _.ScalarMemOp:$src2, u8imm:$cc),
1728 !strconcat("vpcmp", Suffix,
1729 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1730 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1731 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1735 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1736 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1737 let Predicates = [prd] in
1738 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1740 let Predicates = [prd, HasVLX] in {
1741 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1742 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1746 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1747 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1748 let Predicates = [prd] in
1749 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1752 let Predicates = [prd, HasVLX] in {
1753 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1755 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1760 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1761 HasBWI>, EVEX_CD8<8, CD8VF>;
1762 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1763 HasBWI>, EVEX_CD8<8, CD8VF>;
1765 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1766 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1767 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1768 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1770 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1771 HasAVX512>, EVEX_CD8<32, CD8VF>;
1772 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1773 HasAVX512>, EVEX_CD8<32, CD8VF>;
1775 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1776 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1777 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1778 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1780 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1782 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1783 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1784 "vcmp${cc}"#_.Suffix,
1785 "$src2, $src1", "$src1, $src2",
1786 (X86cmpm (_.VT _.RC:$src1),
1790 let mayLoad = 1 in {
1791 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1792 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1793 "vcmp${cc}"#_.Suffix,
1794 "$src2, $src1", "$src1, $src2",
1795 (X86cmpm (_.VT _.RC:$src1),
1796 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1799 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1801 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1802 "vcmp${cc}"#_.Suffix,
1803 "${src2}"##_.BroadcastStr##", $src1",
1804 "$src1, ${src2}"##_.BroadcastStr,
1805 (X86cmpm (_.VT _.RC:$src1),
1806 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1809 // Accept explicit immediate argument form instead of comparison code.
1810 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1811 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1813 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1815 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1817 let mayLoad = 1 in {
1818 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1820 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1822 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1824 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1826 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1828 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1829 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1834 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1835 // comparison code form (VCMP[EQ/LT/LE/...]
1836 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1837 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1838 "vcmp${cc}"#_.Suffix,
1839 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1840 (X86cmpmRnd (_.VT _.RC:$src1),
1843 (i32 FROUND_NO_EXC))>, EVEX_B;
1845 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1846 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1848 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1850 "$cc,{sae}, $src2, $src1",
1851 "$src1, $src2,{sae}, $cc">, EVEX_B;
1855 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1856 let Predicates = [HasAVX512] in {
1857 defm Z : avx512_vcmp_common<_.info512>,
1858 avx512_vcmp_sae<_.info512>, EVEX_V512;
1861 let Predicates = [HasAVX512,HasVLX] in {
1862 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1863 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1867 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1868 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1869 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1870 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1872 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1873 (COPY_TO_REGCLASS (VCMPPSZrri
1874 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1875 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1877 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1878 (COPY_TO_REGCLASS (VPCMPDZrri
1879 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1880 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1882 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1883 (COPY_TO_REGCLASS (VPCMPUDZrri
1884 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1885 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1888 // ----------------------------------------------------------------
1890 //handle fpclass instruction mask = op(reg_scalar,imm)
1891 // op(mem_scalar,imm)
1892 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1893 X86VectorVTInfo _, Predicate prd> {
1894 let Predicates = [prd] in {
1895 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1896 (ins _.RC:$src1, i32u8imm:$src2),
1897 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1898 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1899 (i32 imm:$src2)))], NoItinerary>;
1900 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1901 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1902 OpcodeStr##_.Suffix#
1903 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1904 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1905 (OpNode (_.VT _.RC:$src1),
1906 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1907 let mayLoad = 1, AddedComplexity = 20 in {
1908 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1909 (ins _.MemOp:$src1, i32u8imm:$src2),
1910 OpcodeStr##_.Suffix##
1911 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1913 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1914 (i32 imm:$src2)))], NoItinerary>;
1915 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1916 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1917 OpcodeStr##_.Suffix##
1918 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1919 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1920 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1921 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1926 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1927 // fpclass(reg_vec, mem_vec, imm)
1928 // fpclass(reg_vec, broadcast(eltVt), imm)
1929 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1930 X86VectorVTInfo _, string mem, string broadcast>{
1931 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1932 (ins _.RC:$src1, i32u8imm:$src2),
1933 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1934 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1935 (i32 imm:$src2)))], NoItinerary>;
1936 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1937 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1938 OpcodeStr##_.Suffix#
1939 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1940 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1941 (OpNode (_.VT _.RC:$src1),
1942 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1943 let mayLoad = 1 in {
1944 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1945 (ins _.MemOp:$src1, i32u8imm:$src2),
1946 OpcodeStr##_.Suffix##mem#
1947 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1948 [(set _.KRC:$dst,(OpNode
1949 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1950 (i32 imm:$src2)))], NoItinerary>;
1951 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1952 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1953 OpcodeStr##_.Suffix##mem#
1954 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1955 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1956 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1957 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1958 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1959 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1960 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1961 _.BroadcastStr##", $dst | $dst, ${src1}"
1962 ##_.BroadcastStr##", $src2}",
1963 [(set _.KRC:$dst,(OpNode
1964 (_.VT (X86VBroadcast
1965 (_.ScalarLdFrag addr:$src1))),
1966 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1967 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1968 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1969 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1970 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1971 _.BroadcastStr##", $src2}",
1972 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1973 (_.VT (X86VBroadcast
1974 (_.ScalarLdFrag addr:$src1))),
1975 (i32 imm:$src2))))], NoItinerary>,
1980 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1981 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1983 let Predicates = [prd] in {
1984 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1985 broadcast>, EVEX_V512;
1987 let Predicates = [prd, HasVLX] in {
1988 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1989 broadcast>, EVEX_V128;
1990 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1991 broadcast>, EVEX_V256;
1995 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1996 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
1997 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1998 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1999 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
2000 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
2001 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
2002 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
2003 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
2004 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
2007 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
2008 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
2010 //-----------------------------------------------------------------
2011 // Mask register copy, including
2012 // - copy between mask registers
2013 // - load/store mask registers
2014 // - copy from GPR to mask register and vice versa
2016 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
2017 string OpcodeStr, RegisterClass KRC,
2018 ValueType vvt, X86MemOperand x86memop> {
2019 let hasSideEffects = 0 in {
2020 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2021 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2023 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
2024 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2025 [(set KRC:$dst, (vvt (load addr:$src)))]>;
2027 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
2028 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2029 [(store KRC:$src, addr:$dst)]>;
2033 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
2035 RegisterClass KRC, RegisterClass GRC> {
2036 let hasSideEffects = 0 in {
2037 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
2038 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2039 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
2040 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2044 let Predicates = [HasDQI] in
2045 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
2046 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
2049 let Predicates = [HasAVX512] in
2050 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
2051 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
2054 let Predicates = [HasBWI] in {
2055 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2057 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
2061 let Predicates = [HasBWI] in {
2062 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2064 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
2068 // GR from/to mask register
2069 let Predicates = [HasDQI] in {
2070 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2071 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2072 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2073 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2075 let Predicates = [HasAVX512] in {
2076 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2077 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2078 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2079 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2081 let Predicates = [HasBWI] in {
2082 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2083 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2085 let Predicates = [HasBWI] in {
2086 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2087 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2091 let Predicates = [HasDQI] in {
2092 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2093 (KMOVBmk addr:$dst, VK8:$src)>;
2094 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2095 (KMOVBkm addr:$src)>;
2097 def : Pat<(store VK4:$src, addr:$dst),
2098 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2099 def : Pat<(store VK2:$src, addr:$dst),
2100 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2102 let Predicates = [HasAVX512, NoDQI] in {
2103 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2104 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2105 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2106 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2108 let Predicates = [HasAVX512] in {
2109 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2110 (KMOVWmk addr:$dst, VK16:$src)>;
2111 def : Pat<(i1 (load addr:$src)),
2112 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2113 (MOV8rm addr:$src), sub_8bit)),
2115 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2116 (KMOVWkm addr:$src)>;
2118 let Predicates = [HasBWI] in {
2119 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2120 (KMOVDmk addr:$dst, VK32:$src)>;
2121 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2122 (KMOVDkm addr:$src)>;
2124 let Predicates = [HasBWI] in {
2125 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2126 (KMOVQmk addr:$dst, VK64:$src)>;
2127 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2128 (KMOVQkm addr:$src)>;
2131 let Predicates = [HasAVX512] in {
2132 def : Pat<(i1 (trunc (i64 GR64:$src))),
2133 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2136 def : Pat<(i1 (trunc (i32 GR32:$src))),
2137 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2139 def : Pat<(i1 (trunc (i8 GR8:$src))),
2141 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2143 def : Pat<(i1 (trunc (i16 GR16:$src))),
2145 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2148 def : Pat<(i32 (zext VK1:$src)),
2149 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2150 def : Pat<(i32 (anyext VK1:$src)),
2151 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2153 def : Pat<(i8 (zext VK1:$src)),
2156 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2157 def : Pat<(i8 (anyext VK1:$src)),
2159 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2161 def : Pat<(i64 (zext VK1:$src)),
2162 (AND64ri8 (SUBREG_TO_REG (i64 0),
2163 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2164 def : Pat<(i16 (zext VK1:$src)),
2166 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2169 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2170 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2171 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2172 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2173 def : Pat<(v4i1 (scalar_to_vector VK1:$src)),
2174 (COPY_TO_REGCLASS VK1:$src, VK4)>;
2175 def : Pat<(v2i1 (scalar_to_vector VK1:$src)),
2176 (COPY_TO_REGCLASS VK1:$src, VK2)>;
2177 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2178 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2179 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2180 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2183 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2184 let Predicates = [HasAVX512, NoDQI] in {
2185 // GR from/to 8-bit mask without native support
2186 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2188 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2189 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2191 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2195 let Predicates = [HasAVX512] in {
2196 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2197 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2198 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2199 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2201 let Predicates = [HasBWI] in {
2202 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2203 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2204 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2205 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2208 // Mask unary operation
2210 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2211 RegisterClass KRC, SDPatternOperator OpNode,
2213 let Predicates = [prd] in
2214 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2215 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2216 [(set KRC:$dst, (OpNode KRC:$src))]>;
2219 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2220 SDPatternOperator OpNode> {
2221 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2223 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2224 HasAVX512>, VEX, PS;
2225 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2226 HasBWI>, VEX, PD, VEX_W;
2227 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2228 HasBWI>, VEX, PS, VEX_W;
2231 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2233 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2234 let Predicates = [HasAVX512] in
2235 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2237 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2238 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2240 defm : avx512_mask_unop_int<"knot", "KNOT">;
2242 let Predicates = [HasDQI] in
2243 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2244 let Predicates = [HasAVX512] in
2245 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2246 let Predicates = [HasBWI] in
2247 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2248 let Predicates = [HasBWI] in
2249 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2251 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2252 let Predicates = [HasAVX512, NoDQI] in {
2253 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2254 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2255 def : Pat<(not VK8:$src),
2257 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2259 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2260 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2261 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2262 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2264 // Mask binary operation
2265 // - KAND, KANDN, KOR, KXNOR, KXOR
2266 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2267 RegisterClass KRC, SDPatternOperator OpNode,
2268 Predicate prd, bit IsCommutable> {
2269 let Predicates = [prd], isCommutable = IsCommutable in
2270 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2271 !strconcat(OpcodeStr,
2272 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2273 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2276 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2277 SDPatternOperator OpNode, bit IsCommutable,
2278 Predicate prdW = HasAVX512> {
2279 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2280 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2281 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2282 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2283 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2284 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2285 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2286 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2289 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2290 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2292 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2293 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2294 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2295 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2296 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2297 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2299 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2300 let Predicates = [HasAVX512] in
2301 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2302 (i16 GR16:$src1), (i16 GR16:$src2)),
2303 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2304 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2305 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2308 defm : avx512_mask_binop_int<"kand", "KAND">;
2309 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2310 defm : avx512_mask_binop_int<"kor", "KOR">;
2311 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2312 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2314 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2315 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2316 // for the DQI set, this type is legal and KxxxB instruction is used
2317 let Predicates = [NoDQI] in
2318 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2320 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2321 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2323 // All types smaller than 8 bits require conversion anyway
2324 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2325 (COPY_TO_REGCLASS (Inst
2326 (COPY_TO_REGCLASS VK1:$src1, VK16),
2327 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2328 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2329 (COPY_TO_REGCLASS (Inst
2330 (COPY_TO_REGCLASS VK2:$src1, VK16),
2331 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2332 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2333 (COPY_TO_REGCLASS (Inst
2334 (COPY_TO_REGCLASS VK4:$src1, VK16),
2335 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2338 defm : avx512_binop_pat<and, KANDWrr>;
2339 defm : avx512_binop_pat<andn, KANDNWrr>;
2340 defm : avx512_binop_pat<or, KORWrr>;
2341 defm : avx512_binop_pat<xnor, KXNORWrr>;
2342 defm : avx512_binop_pat<xor, KXORWrr>;
2344 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2345 (KXNORWrr VK16:$src1, VK16:$src2)>;
2346 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2347 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2348 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2349 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2350 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2351 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2353 let Predicates = [NoDQI] in
2354 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2355 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2356 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2358 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2359 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2360 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2362 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2363 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2364 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2366 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2367 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2368 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2371 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2372 RegisterClass KRCSrc, Predicate prd> {
2373 let Predicates = [prd] in {
2374 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2375 (ins KRC:$src1, KRC:$src2),
2376 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2379 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2380 (!cast<Instruction>(NAME##rr)
2381 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2382 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2386 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2387 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2388 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2391 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2392 SDNode OpNode, Predicate prd> {
2393 let Predicates = [prd], Defs = [EFLAGS] in
2394 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2395 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2396 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2399 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2400 Predicate prdW = HasAVX512> {
2401 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2403 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2405 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2407 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2411 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2412 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2415 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2417 let Predicates = [HasAVX512] in
2418 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2419 !strconcat(OpcodeStr,
2420 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2421 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2424 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2426 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2428 let Predicates = [HasDQI] in
2429 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2431 let Predicates = [HasBWI] in {
2432 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2434 let Predicates = [HasDQI] in
2435 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2440 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2441 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2443 // Mask setting all 0s or 1s
2444 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2445 let Predicates = [HasAVX512] in
2446 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2447 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2448 [(set KRC:$dst, (VT Val))]>;
2451 multiclass avx512_mask_setop_w<PatFrag Val> {
2452 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2453 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2454 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2455 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2458 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2459 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2461 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2462 let Predicates = [HasAVX512] in {
2463 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2464 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2465 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2466 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2467 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2468 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2469 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2471 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2472 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2474 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2475 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2477 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2478 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2480 def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 0))),
2481 (v16i1 (COPY_TO_REGCLASS VK32:$src, VK16))>;
2483 def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 16))),
2484 (v16i1 (COPY_TO_REGCLASS (KSHIFTRDri VK32:$src, (i8 16)), VK16))>;
2486 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2487 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2489 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2490 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2492 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2493 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2495 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2496 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2498 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2499 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2501 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2502 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2503 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2504 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2506 def : Pat<(v32i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2507 (v32i1 (COPY_TO_REGCLASS VK2:$src, VK32))>;
2508 def : Pat<(v32i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2509 (v32i1 (COPY_TO_REGCLASS VK4:$src, VK32))>;
2510 def : Pat<(v32i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2511 (v32i1 (COPY_TO_REGCLASS VK8:$src, VK32))>;
2512 def : Pat<(v32i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2513 (v32i1 (COPY_TO_REGCLASS VK16:$src, VK32))>;
2515 def : Pat<(v64i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2516 (v64i1 (COPY_TO_REGCLASS VK2:$src, VK64))>;
2517 def : Pat<(v64i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2518 (v64i1 (COPY_TO_REGCLASS VK4:$src, VK64))>;
2519 def : Pat<(v64i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2520 (v64i1 (COPY_TO_REGCLASS VK8:$src, VK64))>;
2521 def : Pat<(v64i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2522 (v64i1 (COPY_TO_REGCLASS VK16:$src, VK64))>;
2523 def : Pat<(v64i1 (insert_subvector undef, VK32:$src, (iPTR 0))),
2524 (v64i1 (COPY_TO_REGCLASS VK32:$src, VK64))>;
2527 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2528 (v8i1 (COPY_TO_REGCLASS
2529 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2530 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2532 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2533 (v8i1 (COPY_TO_REGCLASS
2534 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2535 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2537 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2538 (v4i1 (COPY_TO_REGCLASS
2539 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2540 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2542 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2543 (v4i1 (COPY_TO_REGCLASS
2544 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2545 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2547 //===----------------------------------------------------------------------===//
2548 // AVX-512 - Aligned and unaligned load and store
2552 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2553 PatFrag ld_frag, PatFrag mload,
2554 bit IsReMaterializable = 1> {
2555 let hasSideEffects = 0 in {
2556 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2557 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2559 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2560 (ins _.KRCWM:$mask, _.RC:$src),
2561 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2562 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2565 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2566 SchedRW = [WriteLoad] in
2567 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2568 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2569 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2572 let Constraints = "$src0 = $dst" in {
2573 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2574 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2575 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2576 "${dst} {${mask}}, $src1}"),
2577 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2579 (_.VT _.RC:$src0))))], _.ExeDomain>,
2581 let mayLoad = 1, SchedRW = [WriteLoad] in
2582 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2583 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2584 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2585 "${dst} {${mask}}, $src1}"),
2586 [(set _.RC:$dst, (_.VT
2587 (vselect _.KRCWM:$mask,
2588 (_.VT (bitconvert (ld_frag addr:$src1))),
2589 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2591 let mayLoad = 1, SchedRW = [WriteLoad] in
2592 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2593 (ins _.KRCWM:$mask, _.MemOp:$src),
2594 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2595 "${dst} {${mask}} {z}, $src}",
2596 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2597 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2598 _.ExeDomain>, EVEX, EVEX_KZ;
2600 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2601 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2603 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2604 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2606 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2607 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2608 _.KRCWM:$mask, addr:$ptr)>;
2611 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2612 AVX512VLVectorVTInfo _,
2614 bit IsReMaterializable = 1> {
2615 let Predicates = [prd] in
2616 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2617 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2619 let Predicates = [prd, HasVLX] in {
2620 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2621 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2622 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2623 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2627 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2628 AVX512VLVectorVTInfo _,
2630 bit IsReMaterializable = 1> {
2631 let Predicates = [prd] in
2632 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2633 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2635 let Predicates = [prd, HasVLX] in {
2636 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2637 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2638 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2639 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2643 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2644 PatFrag st_frag, PatFrag mstore> {
2646 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2647 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
2648 [], _.ExeDomain>, EVEX;
2649 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2650 (ins _.KRCWM:$mask, _.RC:$src),
2651 OpcodeStr # ".s\t{$src, ${dst} {${mask}}|"#
2652 "${dst} {${mask}}, $src}",
2653 [], _.ExeDomain>, EVEX, EVEX_K;
2654 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2655 (ins _.KRCWM:$mask, _.RC:$src),
2656 OpcodeStr # ".s\t{$src, ${dst} {${mask}} {z}|" #
2657 "${dst} {${mask}} {z}, $src}",
2658 [], _.ExeDomain>, EVEX, EVEX_KZ;
2660 let mayStore = 1 in {
2661 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2662 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2663 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2664 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2665 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2666 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2667 [], _.ExeDomain>, EVEX, EVEX_K;
2670 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2671 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2672 _.KRCWM:$mask, _.RC:$src)>;
2676 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2677 AVX512VLVectorVTInfo _, Predicate prd> {
2678 let Predicates = [prd] in
2679 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2680 masked_store_unaligned>, EVEX_V512;
2682 let Predicates = [prd, HasVLX] in {
2683 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2684 masked_store_unaligned>, EVEX_V256;
2685 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2686 masked_store_unaligned>, EVEX_V128;
2690 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2691 AVX512VLVectorVTInfo _, Predicate prd> {
2692 let Predicates = [prd] in
2693 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2694 masked_store_aligned512>, EVEX_V512;
2696 let Predicates = [prd, HasVLX] in {
2697 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2698 masked_store_aligned256>, EVEX_V256;
2699 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2700 masked_store_aligned128>, EVEX_V128;
2704 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2706 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2707 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2709 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2711 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2712 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2714 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2715 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2716 PS, EVEX_CD8<32, CD8VF>;
2718 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2719 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2720 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2722 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2723 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2724 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2726 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2727 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2728 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2730 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2731 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2732 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2734 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2735 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2736 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2738 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2739 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2740 (VMOVAPDZrm addr:$ptr)>;
2742 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2743 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2744 (VMOVAPSZrm addr:$ptr)>;
2746 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2748 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2750 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2752 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2755 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2757 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2759 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2761 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2764 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2766 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2767 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2769 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2771 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2772 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2774 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2775 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2776 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2778 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2779 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2780 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2782 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2783 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2784 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2786 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2787 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2788 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2790 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2791 (v16i32 immAllZerosV), GR16:$mask)),
2792 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2794 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2795 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2796 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2798 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2800 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2802 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2804 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2807 let AddedComplexity = 20 in {
2808 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2809 (bc_v8i64 (v16i32 immAllZerosV)))),
2810 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2812 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2813 (v8i64 VR512:$src))),
2814 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2817 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2818 (v16i32 immAllZerosV))),
2819 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2821 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2822 (v16i32 VR512:$src))),
2823 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2826 // Move Int Doubleword to Packed Double Int
2828 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2829 "vmovd\t{$src, $dst|$dst, $src}",
2831 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2833 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2834 "vmovd\t{$src, $dst|$dst, $src}",
2836 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2837 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2838 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2839 "vmovq\t{$src, $dst|$dst, $src}",
2841 (v2i64 (scalar_to_vector GR64:$src)))],
2842 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2843 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
2844 def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2846 "vmovq\t{$src, $dst|$dst, $src}", []>,
2847 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2848 let isCodeGenOnly = 1 in {
2849 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2850 "vmovq\t{$src, $dst|$dst, $src}",
2851 [(set FR64:$dst, (bitconvert GR64:$src))],
2852 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2853 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2854 "vmovq\t{$src, $dst|$dst, $src}",
2855 [(set GR64:$dst, (bitconvert FR64:$src))],
2856 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2857 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2858 "vmovq\t{$src, $dst|$dst, $src}",
2859 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2860 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2861 EVEX_CD8<64, CD8VT1>;
2864 // Move Int Doubleword to Single Scalar
2866 let isCodeGenOnly = 1 in {
2867 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2868 "vmovd\t{$src, $dst|$dst, $src}",
2869 [(set FR32X:$dst, (bitconvert GR32:$src))],
2870 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2872 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2873 "vmovd\t{$src, $dst|$dst, $src}",
2874 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2875 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2878 // Move doubleword from xmm register to r/m32
2880 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2881 "vmovd\t{$src, $dst|$dst, $src}",
2882 [(set GR32:$dst, (extractelt (v4i32 VR128X:$src),
2883 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2885 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2886 (ins i32mem:$dst, VR128X:$src),
2887 "vmovd\t{$src, $dst|$dst, $src}",
2888 [(store (i32 (extractelt (v4i32 VR128X:$src),
2889 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2890 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2892 // Move quadword from xmm1 register to r/m64
2894 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2895 "vmovq\t{$src, $dst|$dst, $src}",
2896 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2898 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2899 Requires<[HasAVX512, In64BitMode]>;
2901 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
2902 def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src),
2903 "vmovq\t{$src, $dst|$dst, $src}",
2904 [], IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2905 Requires<[HasAVX512, In64BitMode]>;
2907 def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs),
2908 (ins i64mem:$dst, VR128X:$src),
2909 "vmovq\t{$src, $dst|$dst, $src}",
2910 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2911 addr:$dst)], IIC_SSE_MOVDQ>,
2912 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2913 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2915 let hasSideEffects = 0 in
2916 def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
2918 "vmovq.s\t{$src, $dst|$dst, $src}",[]>,
2919 EVEX, VEX_W, VEX_LIG;
2921 // Move Scalar Single to Double Int
2923 let isCodeGenOnly = 1 in {
2924 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2926 "vmovd\t{$src, $dst|$dst, $src}",
2927 [(set GR32:$dst, (bitconvert FR32X:$src))],
2928 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2929 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2930 (ins i32mem:$dst, FR32X:$src),
2931 "vmovd\t{$src, $dst|$dst, $src}",
2932 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2933 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2936 // Move Quadword Int to Packed Quadword Int
2938 def VMOVQI2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2940 "vmovq\t{$src, $dst|$dst, $src}",
2942 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2943 EVEX, VEX_W, EVEX_CD8<8, CD8VT8>;
2945 //===----------------------------------------------------------------------===//
2946 // AVX-512 MOVSS, MOVSD
2947 //===----------------------------------------------------------------------===//
2949 multiclass avx512_move_scalar <string asm, SDNode OpNode,
2950 X86VectorVTInfo _> {
2951 defm rr_Int : AVX512_maskable_scalar<0x10, MRMSrcReg, _, (outs _.RC:$dst),
2952 (ins _.RC:$src1, _.RC:$src2),
2953 asm, "$src2, $src1","$src1, $src2",
2954 (_.VT (OpNode (_.VT _.RC:$src1),
2955 (_.VT _.RC:$src2))),
2956 IIC_SSE_MOV_S_RR>, EVEX_4V;
2957 let Constraints = "$src1 = $dst" , mayLoad = 1 in
2958 defm rm_Int : AVX512_maskable_3src_scalar<0x10, MRMSrcMem, _,
2960 (ins _.ScalarMemOp:$src),
2962 (_.VT (OpNode (_.VT _.RC:$src1),
2963 (_.VT (scalar_to_vector
2964 (_.ScalarLdFrag addr:$src)))))>, EVEX;
2965 let isCodeGenOnly = 1 in {
2966 def rr : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
2967 (ins _.RC:$src1, _.FRC:$src2),
2968 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2969 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1,
2970 (scalar_to_vector _.FRC:$src2))))],
2971 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V;
2973 def rm : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src),
2974 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2975 [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))],
2976 _.ExeDomain, IIC_SSE_MOV_S_RM>, EVEX;
2978 let mayStore = 1 in {
2979 def mr: AVX512PI<0x11, MRMDestMem, (outs), (ins _.ScalarMemOp:$dst, _.FRC:$src),
2980 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2981 [(store _.FRC:$src, addr:$dst)], _.ExeDomain, IIC_SSE_MOV_S_MR>,
2983 def mrk: AVX512PI<0x11, MRMDestMem, (outs),
2984 (ins _.ScalarMemOp:$dst, VK1WM:$mask, _.FRC:$src),
2985 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2986 [], _.ExeDomain, IIC_SSE_MOV_S_MR>, EVEX, EVEX_K;
2990 defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>,
2991 VEX_LIG, XS, EVEX_CD8<32, CD8VT1>;
2993 defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>,
2994 VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2996 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2997 (COPY_TO_REGCLASS (VMOVSSZrr_Intk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2998 VK1WM:$mask, (v4f32 (IMPLICIT_DEF)),(COPY_TO_REGCLASS FR32X:$src1, VR128X)), FR32X)>;
3000 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
3001 (COPY_TO_REGCLASS (VMOVSDZrr_Intk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
3002 VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR64X:$src1, VR128X)), FR64X)>;
3004 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
3005 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
3006 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3008 defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,
3009 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3010 "vmovss.s", "$src2, $src1", "$src1, $src2", []>,
3011 XS, EVEX_4V, VEX_LIG;
3013 defm VMOVSSDrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f64x_info,
3014 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3015 "vmovsd.s", "$src2, $src1", "$src1, $src2", []>,
3016 XD, EVEX_4V, VEX_LIG, VEX_W;
3018 let Predicates = [HasAVX512] in {
3019 let AddedComplexity = 15 in {
3020 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
3021 // MOVS{S,D} to the lower bits.
3022 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
3023 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
3024 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
3025 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3026 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
3027 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3028 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
3029 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
3031 // Move low f32 and clear high bits.
3032 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
3033 (SUBREG_TO_REG (i32 0),
3034 (VMOVSSZrr (v4f32 (V_SET0)),
3035 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
3036 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
3037 (SUBREG_TO_REG (i32 0),
3038 (VMOVSSZrr (v4i32 (V_SET0)),
3039 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
3042 let AddedComplexity = 20 in {
3043 // MOVSSrm zeros the high parts of the register; represent this
3044 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3045 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
3046 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3047 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
3048 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3049 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
3050 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3052 // MOVSDrm zeros the high parts of the register; represent this
3053 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3054 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
3055 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3056 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
3057 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3058 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
3059 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3060 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
3061 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3062 def : Pat<(v2f64 (X86vzload addr:$src)),
3063 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3065 // Represent the same patterns above but in the form they appear for
3067 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3068 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3069 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3070 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3071 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3072 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3073 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3074 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3075 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3077 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3078 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
3079 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
3080 FR32X:$src)), sub_xmm)>;
3081 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3082 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3083 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
3084 FR64X:$src)), sub_xmm)>;
3085 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3086 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3087 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3089 // Move low f64 and clear high bits.
3090 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3091 (SUBREG_TO_REG (i32 0),
3092 (VMOVSDZrr (v2f64 (V_SET0)),
3093 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3095 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3096 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3097 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3099 // Extract and store.
3100 def : Pat<(store (f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
3102 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3103 def : Pat<(store (f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
3105 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3107 // Shuffle with VMOVSS
3108 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3109 (VMOVSSZrr (v4i32 VR128X:$src1),
3110 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3111 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3112 (VMOVSSZrr (v4f32 VR128X:$src1),
3113 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3116 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3117 (SUBREG_TO_REG (i32 0),
3118 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3119 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3121 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3122 (SUBREG_TO_REG (i32 0),
3123 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3124 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3127 // Shuffle with VMOVSD
3128 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3129 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3130 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3131 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3132 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3133 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3134 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3135 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3138 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3139 (SUBREG_TO_REG (i32 0),
3140 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3141 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3143 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3144 (SUBREG_TO_REG (i32 0),
3145 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3146 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3149 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3150 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3151 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3152 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3153 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3154 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3155 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3156 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3159 let AddedComplexity = 15 in
3160 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3162 "vmovq\t{$src, $dst|$dst, $src}",
3163 [(set VR128X:$dst, (v2i64 (X86vzmovl
3164 (v2i64 VR128X:$src))))],
3165 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3167 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3168 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3170 "vmovq\t{$src, $dst|$dst, $src}",
3171 [(set VR128X:$dst, (v2i64 (X86vzmovl
3172 (loadv2i64 addr:$src))))],
3173 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3174 EVEX_CD8<8, CD8VT8>;
3176 let Predicates = [HasAVX512] in {
3177 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3178 let AddedComplexity = 20 in {
3179 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3180 (VMOVDI2PDIZrm addr:$src)>;
3181 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3182 (VMOV64toPQIZrr GR64:$src)>;
3183 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3184 (VMOVDI2PDIZrr GR32:$src)>;
3186 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3187 (VMOVDI2PDIZrm addr:$src)>;
3188 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3189 (VMOVDI2PDIZrm addr:$src)>;
3190 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3191 (VMOVZPQILo2PQIZrm addr:$src)>;
3192 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3193 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3194 def : Pat<(v2i64 (X86vzload addr:$src)),
3195 (VMOVZPQILo2PQIZrm addr:$src)>;
3198 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3199 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3200 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3201 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3202 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3203 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3204 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3207 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3208 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3210 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3211 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3213 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3214 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3216 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3217 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3219 //===----------------------------------------------------------------------===//
3220 // AVX-512 - Non-temporals
3221 //===----------------------------------------------------------------------===//
3222 let SchedRW = [WriteLoad] in {
3223 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3224 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3225 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3226 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3227 EVEX_CD8<64, CD8VF>;
3229 let Predicates = [HasAVX512, HasVLX] in {
3230 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3232 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3233 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3234 EVEX_CD8<64, CD8VF>;
3236 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3238 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3239 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3240 EVEX_CD8<64, CD8VF>;
3244 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3245 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3246 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3247 let SchedRW = [WriteStore], mayStore = 1,
3248 AddedComplexity = 400 in
3249 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3250 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3251 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3254 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3255 string elty, string elsz, string vsz512,
3256 string vsz256, string vsz128, Domain d,
3257 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3258 let Predicates = [prd] in
3259 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3260 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3261 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3264 let Predicates = [prd, HasVLX] in {
3265 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3266 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3267 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3270 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3271 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3272 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3277 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3278 "i", "64", "8", "4", "2", SSEPackedInt,
3279 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3281 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3282 "f", "64", "8", "4", "2", SSEPackedDouble,
3283 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3285 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3286 "f", "32", "16", "8", "4", SSEPackedSingle,
3287 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3289 //===----------------------------------------------------------------------===//
3290 // AVX-512 - Integer arithmetic
3292 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3293 X86VectorVTInfo _, OpndItins itins,
3294 bit IsCommutable = 0> {
3295 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3296 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3297 "$src2, $src1", "$src1, $src2",
3298 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3299 itins.rr, IsCommutable>,
3300 AVX512BIBase, EVEX_4V;
3303 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3304 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3305 "$src2, $src1", "$src1, $src2",
3306 (_.VT (OpNode _.RC:$src1,
3307 (bitconvert (_.LdFrag addr:$src2)))),
3309 AVX512BIBase, EVEX_4V;
3312 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3313 X86VectorVTInfo _, OpndItins itins,
3314 bit IsCommutable = 0> :
3315 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3317 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3318 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3319 "${src2}"##_.BroadcastStr##", $src1",
3320 "$src1, ${src2}"##_.BroadcastStr,
3321 (_.VT (OpNode _.RC:$src1,
3323 (_.ScalarLdFrag addr:$src2)))),
3325 AVX512BIBase, EVEX_4V, EVEX_B;
3328 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3329 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3330 Predicate prd, bit IsCommutable = 0> {
3331 let Predicates = [prd] in
3332 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3333 IsCommutable>, EVEX_V512;
3335 let Predicates = [prd, HasVLX] in {
3336 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3337 IsCommutable>, EVEX_V256;
3338 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3339 IsCommutable>, EVEX_V128;
3343 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3344 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3345 Predicate prd, bit IsCommutable = 0> {
3346 let Predicates = [prd] in
3347 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3348 IsCommutable>, EVEX_V512;
3350 let Predicates = [prd, HasVLX] in {
3351 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3352 IsCommutable>, EVEX_V256;
3353 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3354 IsCommutable>, EVEX_V128;
3358 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3359 OpndItins itins, Predicate prd,
3360 bit IsCommutable = 0> {
3361 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3362 itins, prd, IsCommutable>,
3363 VEX_W, EVEX_CD8<64, CD8VF>;
3366 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3367 OpndItins itins, Predicate prd,
3368 bit IsCommutable = 0> {
3369 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3370 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3373 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3374 OpndItins itins, Predicate prd,
3375 bit IsCommutable = 0> {
3376 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3377 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3380 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3381 OpndItins itins, Predicate prd,
3382 bit IsCommutable = 0> {
3383 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3384 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3387 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3388 SDNode OpNode, OpndItins itins, Predicate prd,
3389 bit IsCommutable = 0> {
3390 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3393 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3397 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3398 SDNode OpNode, OpndItins itins, Predicate prd,
3399 bit IsCommutable = 0> {
3400 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3403 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3407 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3408 bits<8> opc_d, bits<8> opc_q,
3409 string OpcodeStr, SDNode OpNode,
3410 OpndItins itins, bit IsCommutable = 0> {
3411 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3412 itins, HasAVX512, IsCommutable>,
3413 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3414 itins, HasBWI, IsCommutable>;
3417 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3418 SDNode OpNode,X86VectorVTInfo _Src,
3419 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3420 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3421 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3422 "$src2, $src1","$src1, $src2",
3424 (_Src.VT _Src.RC:$src1),
3425 (_Src.VT _Src.RC:$src2))),
3426 itins.rr, IsCommutable>,
3427 AVX512BIBase, EVEX_4V;
3428 let mayLoad = 1 in {
3429 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3430 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3431 "$src2, $src1", "$src1, $src2",
3432 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3433 (bitconvert (_Src.LdFrag addr:$src2)))),
3435 AVX512BIBase, EVEX_4V;
3437 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3438 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3440 "${src2}"##_Dst.BroadcastStr##", $src1",
3441 "$src1, ${src2}"##_Dst.BroadcastStr,
3442 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3443 (_Dst.VT (X86VBroadcast
3444 (_Dst.ScalarLdFrag addr:$src2)))))),
3446 AVX512BIBase, EVEX_4V, EVEX_B;
3450 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3451 SSE_INTALU_ITINS_P, 1>;
3452 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3453 SSE_INTALU_ITINS_P, 0>;
3454 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3455 SSE_INTALU_ITINS_P, HasBWI, 1>;
3456 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3457 SSE_INTALU_ITINS_P, HasBWI, 0>;
3458 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3459 SSE_INTALU_ITINS_P, HasBWI, 1>;
3460 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3461 SSE_INTALU_ITINS_P, HasBWI, 0>;
3462 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3463 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3464 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3465 SSE_INTALU_ITINS_P, HasBWI, 1>;
3466 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3467 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3468 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3470 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3472 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3474 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3475 SSE_INTALU_ITINS_P, HasBWI, 1>;
3477 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3478 SDNode OpNode, bit IsCommutable = 0> {
3480 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3481 v16i32_info, v8i64_info, IsCommutable>,
3482 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3483 let Predicates = [HasVLX] in {
3484 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3485 v8i32x_info, v4i64x_info, IsCommutable>,
3486 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3487 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3488 v4i32x_info, v2i64x_info, IsCommutable>,
3489 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3493 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3495 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3498 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3499 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3500 let mayLoad = 1 in {
3501 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3502 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3504 "${src2}"##_Src.BroadcastStr##", $src1",
3505 "$src1, ${src2}"##_Src.BroadcastStr,
3506 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3507 (_Src.VT (X86VBroadcast
3508 (_Src.ScalarLdFrag addr:$src2))))))>,
3509 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3513 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3514 SDNode OpNode,X86VectorVTInfo _Src,
3515 X86VectorVTInfo _Dst> {
3516 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3517 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3518 "$src2, $src1","$src1, $src2",
3520 (_Src.VT _Src.RC:$src1),
3521 (_Src.VT _Src.RC:$src2)))>,
3522 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3523 let mayLoad = 1 in {
3524 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3525 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3526 "$src2, $src1", "$src1, $src2",
3527 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3528 (bitconvert (_Src.LdFrag addr:$src2))))>,
3529 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3533 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3535 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3537 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3538 v32i16_info>, EVEX_V512;
3539 let Predicates = [HasVLX] in {
3540 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3542 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3543 v16i16x_info>, EVEX_V256;
3544 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3546 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3547 v8i16x_info>, EVEX_V128;
3550 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3552 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3553 v64i8_info>, EVEX_V512;
3554 let Predicates = [HasVLX] in {
3555 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3556 v32i8x_info>, EVEX_V256;
3557 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3558 v16i8x_info>, EVEX_V128;
3562 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3563 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3564 AVX512VLVectorVTInfo _Dst> {
3565 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3566 _Dst.info512>, EVEX_V512;
3567 let Predicates = [HasVLX] in {
3568 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3569 _Dst.info256>, EVEX_V256;
3570 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3571 _Dst.info128>, EVEX_V128;
3575 let Predicates = [HasBWI] in {
3576 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3577 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3578 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3579 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3581 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3582 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3583 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3584 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3587 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3588 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3589 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3590 SSE_INTALU_ITINS_P, HasBWI, 1>;
3591 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3592 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3594 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3595 SSE_INTALU_ITINS_P, HasBWI, 1>;
3596 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3597 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3598 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3599 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3601 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3602 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3603 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3604 SSE_INTALU_ITINS_P, HasBWI, 1>;
3605 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3606 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3608 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3609 SSE_INTALU_ITINS_P, HasBWI, 1>;
3610 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3611 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3612 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3613 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3614 //===----------------------------------------------------------------------===//
3615 // AVX-512 Logical Instructions
3616 //===----------------------------------------------------------------------===//
3618 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3619 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3620 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3621 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3622 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3623 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3624 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3625 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3627 //===----------------------------------------------------------------------===//
3628 // AVX-512 FP arithmetic
3629 //===----------------------------------------------------------------------===//
3630 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3631 SDNode OpNode, SDNode VecNode, OpndItins itins,
3634 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3635 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3636 "$src2, $src1", "$src1, $src2",
3637 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3638 (i32 FROUND_CURRENT)),
3639 itins.rr, IsCommutable>;
3641 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3642 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3643 "$src2, $src1", "$src1, $src2",
3644 (VecNode (_.VT _.RC:$src1),
3645 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3646 (i32 FROUND_CURRENT)),
3647 itins.rm, IsCommutable>;
3648 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3649 Predicates = [HasAVX512] in {
3650 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3651 (ins _.FRC:$src1, _.FRC:$src2),
3652 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3653 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3655 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3656 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3657 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3658 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3659 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3663 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3664 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3666 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3667 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3668 "$rc, $src2, $src1", "$src1, $src2, $rc",
3669 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3670 (i32 imm:$rc)), itins.rr, IsCommutable>,
3673 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3674 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3676 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3677 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3678 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3679 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3680 (i32 FROUND_NO_EXC))>, EVEX_B;
3683 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3685 SizeItins itins, bit IsCommutable> {
3686 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3687 itins.s, IsCommutable>,
3688 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3689 itins.s, IsCommutable>,
3690 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3691 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3692 itins.d, IsCommutable>,
3693 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3694 itins.d, IsCommutable>,
3695 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3698 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3700 SizeItins itins, bit IsCommutable> {
3701 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3702 itins.s, IsCommutable>,
3703 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3704 itins.s, IsCommutable>,
3705 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3706 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3707 itins.d, IsCommutable>,
3708 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3709 itins.d, IsCommutable>,
3710 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3712 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3713 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3714 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3715 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3716 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3717 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3719 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3720 X86VectorVTInfo _, bit IsCommutable> {
3721 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3722 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3723 "$src2, $src1", "$src1, $src2",
3724 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3725 let mayLoad = 1 in {
3726 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3727 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3728 "$src2, $src1", "$src1, $src2",
3729 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3730 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3731 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3732 "${src2}"##_.BroadcastStr##", $src1",
3733 "$src1, ${src2}"##_.BroadcastStr,
3734 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3735 (_.ScalarLdFrag addr:$src2))))>,
3740 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3741 X86VectorVTInfo _> {
3742 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3743 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3744 "$rc, $src2, $src1", "$src1, $src2, $rc",
3745 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3746 EVEX_4V, EVEX_B, EVEX_RC;
3750 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3751 X86VectorVTInfo _> {
3752 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3753 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3754 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3755 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3759 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3760 bit IsCommutable = 0> {
3761 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3762 IsCommutable>, EVEX_V512, PS,
3763 EVEX_CD8<32, CD8VF>;
3764 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3765 IsCommutable>, EVEX_V512, PD, VEX_W,
3766 EVEX_CD8<64, CD8VF>;
3768 // Define only if AVX512VL feature is present.
3769 let Predicates = [HasVLX] in {
3770 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3771 IsCommutable>, EVEX_V128, PS,
3772 EVEX_CD8<32, CD8VF>;
3773 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3774 IsCommutable>, EVEX_V256, PS,
3775 EVEX_CD8<32, CD8VF>;
3776 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3777 IsCommutable>, EVEX_V128, PD, VEX_W,
3778 EVEX_CD8<64, CD8VF>;
3779 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3780 IsCommutable>, EVEX_V256, PD, VEX_W,
3781 EVEX_CD8<64, CD8VF>;
3785 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3786 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3787 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3788 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3789 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3792 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3793 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3794 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3795 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3796 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3799 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3800 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3801 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3802 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3803 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3804 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3805 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3806 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3807 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3808 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3809 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3810 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3811 let Predicates = [HasDQI] in {
3812 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3813 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3814 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3815 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3818 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3819 X86VectorVTInfo _> {
3820 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3821 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3822 "$src2, $src1", "$src1, $src2",
3823 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3824 let mayLoad = 1 in {
3825 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3826 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3827 "$src2, $src1", "$src1, $src2",
3828 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3829 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3830 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3831 "${src2}"##_.BroadcastStr##", $src1",
3832 "$src1, ${src2}"##_.BroadcastStr,
3833 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3834 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3839 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3840 X86VectorVTInfo _> {
3841 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3842 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3843 "$src2, $src1", "$src1, $src2",
3844 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3845 let mayLoad = 1 in {
3846 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3847 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3848 "$src2, $src1", "$src1, $src2",
3849 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3853 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3854 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3855 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3856 EVEX_V512, EVEX_CD8<32, CD8VF>;
3857 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3858 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3859 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3860 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3861 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3862 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3863 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3864 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3865 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3867 // Define only if AVX512VL feature is present.
3868 let Predicates = [HasVLX] in {
3869 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3870 EVEX_V128, EVEX_CD8<32, CD8VF>;
3871 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3872 EVEX_V256, EVEX_CD8<32, CD8VF>;
3873 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3874 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3875 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3876 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3879 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3881 //===----------------------------------------------------------------------===//
3882 // AVX-512 VPTESTM instructions
3883 //===----------------------------------------------------------------------===//
3885 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3886 X86VectorVTInfo _> {
3887 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3888 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3889 "$src2, $src1", "$src1, $src2",
3890 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3893 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3894 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3895 "$src2, $src1", "$src1, $src2",
3896 (OpNode (_.VT _.RC:$src1),
3897 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3899 EVEX_CD8<_.EltSize, CD8VF>;
3902 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3903 X86VectorVTInfo _> {
3905 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3906 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3907 "${src2}"##_.BroadcastStr##", $src1",
3908 "$src1, ${src2}"##_.BroadcastStr,
3909 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3910 (_.ScalarLdFrag addr:$src2))))>,
3911 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3913 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3914 AVX512VLVectorVTInfo _> {
3915 let Predicates = [HasAVX512] in
3916 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3917 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3919 let Predicates = [HasAVX512, HasVLX] in {
3920 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3921 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3922 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3923 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3927 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3928 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3930 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3931 avx512vl_i64_info>, VEX_W;
3934 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3936 let Predicates = [HasBWI] in {
3937 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3939 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3942 let Predicates = [HasVLX, HasBWI] in {
3944 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3946 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3948 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3950 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3955 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3957 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3958 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3960 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3961 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3963 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3964 (v16i32 VR512:$src2), (i16 -1))),
3965 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3967 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3968 (v8i64 VR512:$src2), (i8 -1))),
3969 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3971 //===----------------------------------------------------------------------===//
3972 // AVX-512 Shift instructions
3973 //===----------------------------------------------------------------------===//
3974 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3975 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3976 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3977 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3978 "$src2, $src1", "$src1, $src2",
3979 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3980 SSE_INTSHIFT_ITINS_P.rr>;
3982 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3983 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3984 "$src2, $src1", "$src1, $src2",
3985 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3987 SSE_INTSHIFT_ITINS_P.rm>;
3990 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3991 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3993 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3994 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3995 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3996 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3997 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
4000 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4001 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
4002 // src2 is always 128-bit
4003 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4004 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
4005 "$src2, $src1", "$src1, $src2",
4006 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
4007 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
4008 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4009 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
4010 "$src2, $src1", "$src1, $src2",
4011 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
4012 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
4016 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4017 ValueType SrcVT, PatFrag bc_frag,
4018 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
4019 let Predicates = [prd] in
4020 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4021 VTInfo.info512>, EVEX_V512,
4022 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
4023 let Predicates = [prd, HasVLX] in {
4024 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4025 VTInfo.info256>, EVEX_V256,
4026 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
4027 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4028 VTInfo.info128>, EVEX_V128,
4029 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
4033 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
4034 string OpcodeStr, SDNode OpNode> {
4035 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
4036 avx512vl_i32_info, HasAVX512>;
4037 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
4038 avx512vl_i64_info, HasAVX512>, VEX_W;
4039 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
4040 avx512vl_i16_info, HasBWI>;
4043 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4044 string OpcodeStr, SDNode OpNode,
4045 AVX512VLVectorVTInfo VTInfo> {
4046 let Predicates = [HasAVX512] in
4047 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4049 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4050 VTInfo.info512>, EVEX_V512;
4051 let Predicates = [HasAVX512, HasVLX] in {
4052 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4054 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4055 VTInfo.info256>, EVEX_V256;
4056 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4058 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4059 VTInfo.info128>, EVEX_V128;
4063 multiclass avx512_shift_rmi_w<bits<8> opcw,
4064 Format ImmFormR, Format ImmFormM,
4065 string OpcodeStr, SDNode OpNode> {
4066 let Predicates = [HasBWI] in
4067 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4068 v32i16_info>, EVEX_V512;
4069 let Predicates = [HasVLX, HasBWI] in {
4070 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4071 v16i16x_info>, EVEX_V256;
4072 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4073 v8i16x_info>, EVEX_V128;
4077 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
4078 Format ImmFormR, Format ImmFormM,
4079 string OpcodeStr, SDNode OpNode> {
4080 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
4081 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
4082 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4083 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4086 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4087 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4089 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4090 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4092 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4093 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4095 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4096 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4098 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4099 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4100 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4102 //===-------------------------------------------------------------------===//
4103 // Variable Bit Shifts
4104 //===-------------------------------------------------------------------===//
4105 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4106 X86VectorVTInfo _> {
4107 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4108 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4109 "$src2, $src1", "$src1, $src2",
4110 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4111 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4113 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4114 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4115 "$src2, $src1", "$src1, $src2",
4116 (_.VT (OpNode _.RC:$src1,
4117 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4118 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4119 EVEX_CD8<_.EltSize, CD8VF>;
4122 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4123 X86VectorVTInfo _> {
4125 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4126 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4127 "${src2}"##_.BroadcastStr##", $src1",
4128 "$src1, ${src2}"##_.BroadcastStr,
4129 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4130 (_.ScalarLdFrag addr:$src2))))),
4131 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4132 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4134 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4135 AVX512VLVectorVTInfo _> {
4136 let Predicates = [HasAVX512] in
4137 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4138 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4140 let Predicates = [HasAVX512, HasVLX] in {
4141 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4142 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4143 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4144 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4148 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4150 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4152 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4153 avx512vl_i64_info>, VEX_W;
4156 // Use 512bit version to implement 128/256 bit in case NoVLX.
4157 multiclass avx512_var_shift_w_lowering<AVX512VLVectorVTInfo _, SDNode OpNode> {
4158 let Predicates = [HasBWI, NoVLX] in {
4159 def : Pat<(_.info256.VT (OpNode (_.info256.VT _.info256.RC:$src1),
4160 (_.info256.VT _.info256.RC:$src2))),
4162 (!cast<Instruction>(NAME#"WZrr")
4163 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
4164 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)),
4167 def : Pat<(_.info128.VT (OpNode (_.info128.VT _.info128.RC:$src1),
4168 (_.info128.VT _.info128.RC:$src2))),
4170 (!cast<Instruction>(NAME#"WZrr")
4171 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
4172 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)),
4177 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4179 let Predicates = [HasBWI] in
4180 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4182 let Predicates = [HasVLX, HasBWI] in {
4184 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4186 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4191 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4192 avx512_var_shift_w<0x12, "vpsllvw", shl>,
4193 avx512_var_shift_w_lowering<avx512vl_i16_info, shl>;
4194 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4195 avx512_var_shift_w<0x11, "vpsravw", sra>,
4196 avx512_var_shift_w_lowering<avx512vl_i16_info, sra>;
4197 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4198 avx512_var_shift_w<0x10, "vpsrlvw", srl>,
4199 avx512_var_shift_w_lowering<avx512vl_i16_info, srl>;
4200 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4201 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4203 //===-------------------------------------------------------------------===//
4204 // 1-src variable permutation VPERMW/D/Q
4205 //===-------------------------------------------------------------------===//
4206 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4207 AVX512VLVectorVTInfo _> {
4208 let Predicates = [HasAVX512] in
4209 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4210 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4212 let Predicates = [HasAVX512, HasVLX] in
4213 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4214 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4217 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4218 string OpcodeStr, SDNode OpNode,
4219 AVX512VLVectorVTInfo VTInfo> {
4220 let Predicates = [HasAVX512] in
4221 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4223 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4224 VTInfo.info512>, EVEX_V512;
4225 let Predicates = [HasAVX512, HasVLX] in
4226 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4228 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4229 VTInfo.info256>, EVEX_V256;
4233 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4235 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4237 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4238 avx512vl_i64_info>, VEX_W;
4239 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4241 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4242 avx512vl_f64_info>, VEX_W;
4244 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4245 X86VPermi, avx512vl_i64_info>,
4246 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4247 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4248 X86VPermi, avx512vl_f64_info>,
4249 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4250 //===----------------------------------------------------------------------===//
4251 // AVX-512 - VPERMIL
4252 //===----------------------------------------------------------------------===//
4254 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4255 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4256 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4257 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4258 "$src2, $src1", "$src1, $src2",
4259 (_.VT (OpNode _.RC:$src1,
4260 (Ctrl.VT Ctrl.RC:$src2)))>,
4262 let mayLoad = 1 in {
4263 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4264 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4265 "$src2, $src1", "$src1, $src2",
4268 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4269 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4270 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4271 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4272 "${src2}"##_.BroadcastStr##", $src1",
4273 "$src1, ${src2}"##_.BroadcastStr,
4276 (Ctrl.VT (X86VBroadcast
4277 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4278 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4282 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4283 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4284 let Predicates = [HasAVX512] in {
4285 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4286 Ctrl.info512>, EVEX_V512;
4288 let Predicates = [HasAVX512, HasVLX] in {
4289 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4290 Ctrl.info128>, EVEX_V128;
4291 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4292 Ctrl.info256>, EVEX_V256;
4296 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4297 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4299 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4300 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4302 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4305 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4307 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4308 avx512vl_i64_info>, VEX_W;
4309 //===----------------------------------------------------------------------===//
4310 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4311 //===----------------------------------------------------------------------===//
4313 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4314 X86PShufd, avx512vl_i32_info>,
4315 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4316 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4317 X86PShufhw>, EVEX, AVX512XSIi8Base;
4318 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4319 X86PShuflw>, EVEX, AVX512XDIi8Base;
4321 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4322 let Predicates = [HasBWI] in
4323 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4325 let Predicates = [HasVLX, HasBWI] in {
4326 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4327 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4331 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4333 //===----------------------------------------------------------------------===//
4334 // Move Low to High and High to Low packed FP Instructions
4335 //===----------------------------------------------------------------------===//
4336 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4337 (ins VR128X:$src1, VR128X:$src2),
4338 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4339 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4340 IIC_SSE_MOV_LH>, EVEX_4V;
4341 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4342 (ins VR128X:$src1, VR128X:$src2),
4343 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4344 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4345 IIC_SSE_MOV_LH>, EVEX_4V;
4347 let Predicates = [HasAVX512] in {
4349 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4350 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4351 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4352 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4355 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4356 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4359 //===----------------------------------------------------------------------===//
4360 // VMOVHPS/PD VMOVLPS Instructions
4361 // All patterns was taken from SSS implementation.
4362 //===----------------------------------------------------------------------===//
4363 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4364 X86VectorVTInfo _> {
4366 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
4367 (ins _.RC:$src1, f64mem:$src2),
4368 !strconcat(OpcodeStr,
4369 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4373 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
4374 IIC_SSE_MOV_LH>, EVEX_4V;
4377 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
4378 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4379 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
4380 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4381 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
4382 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4383 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
4384 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4386 let Predicates = [HasAVX512] in {
4388 def : Pat<(X86Movlhps VR128X:$src1,
4389 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
4390 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4391 def : Pat<(X86Movlhps VR128X:$src1,
4392 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
4393 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4395 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4396 (scalar_to_vector (loadf64 addr:$src2)))),
4397 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4398 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4399 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
4400 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4402 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4403 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4404 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4405 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4407 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4408 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4409 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4410 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4411 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
4412 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
4413 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4416 let mayStore = 1 in {
4417 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
4418 (ins f64mem:$dst, VR128X:$src),
4419 "vmovhps\t{$src, $dst|$dst, $src}",
4420 [(store (f64 (vector_extract
4421 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
4422 (bc_v2f64 (v4f32 VR128X:$src))),
4423 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4424 EVEX, EVEX_CD8<32, CD8VT2>;
4425 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
4426 (ins f64mem:$dst, VR128X:$src),
4427 "vmovhpd\t{$src, $dst|$dst, $src}",
4428 [(store (f64 (vector_extract
4429 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
4430 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4431 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4432 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
4433 (ins f64mem:$dst, VR128X:$src),
4434 "vmovlps\t{$src, $dst|$dst, $src}",
4435 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128X:$src)),
4436 (iPTR 0))), addr:$dst)],
4438 EVEX, EVEX_CD8<32, CD8VT2>;
4439 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
4440 (ins f64mem:$dst, VR128X:$src),
4441 "vmovlpd\t{$src, $dst|$dst, $src}",
4442 [(store (f64 (vector_extract (v2f64 VR128X:$src),
4443 (iPTR 0))), addr:$dst)],
4445 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4447 let Predicates = [HasAVX512] in {
4449 def : Pat<(store (f64 (vector_extract
4450 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
4451 (iPTR 0))), addr:$dst),
4452 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
4454 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
4456 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4457 def : Pat<(store (v4i32 (X86Movlps
4458 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
4459 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4461 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4463 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4464 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4466 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4468 //===----------------------------------------------------------------------===//
4469 // FMA - Fused Multiply Operations
4472 let Constraints = "$src1 = $dst" in {
4473 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4474 X86VectorVTInfo _> {
4475 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4476 (ins _.RC:$src2, _.RC:$src3),
4477 OpcodeStr, "$src3, $src2", "$src2, $src3",
4478 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4481 let mayLoad = 1 in {
4482 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4483 (ins _.RC:$src2, _.MemOp:$src3),
4484 OpcodeStr, "$src3, $src2", "$src2, $src3",
4485 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4488 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4489 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4490 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4491 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4493 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4494 AVX512FMA3Base, EVEX_B;
4498 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4499 X86VectorVTInfo _> {
4500 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4501 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4502 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4503 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4504 AVX512FMA3Base, EVEX_B, EVEX_RC;
4506 } // Constraints = "$src1 = $dst"
4508 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4509 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4510 let Predicates = [HasAVX512] in {
4511 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4512 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4513 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4515 let Predicates = [HasVLX, HasAVX512] in {
4516 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4517 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4518 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4519 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4523 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4524 SDNode OpNodeRnd > {
4525 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4527 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4528 avx512vl_f64_info>, VEX_W;
4531 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4532 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4533 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4534 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4535 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4536 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4539 let Constraints = "$src1 = $dst" in {
4540 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4541 X86VectorVTInfo _> {
4542 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4543 (ins _.RC:$src2, _.RC:$src3),
4544 OpcodeStr, "$src3, $src2", "$src2, $src3",
4545 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4548 let mayLoad = 1 in {
4549 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4550 (ins _.RC:$src2, _.MemOp:$src3),
4551 OpcodeStr, "$src3, $src2", "$src2, $src3",
4552 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4555 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4556 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4557 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4558 "$src2, ${src3}"##_.BroadcastStr,
4559 (_.VT (OpNode _.RC:$src2,
4560 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4561 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4565 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4566 X86VectorVTInfo _> {
4567 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4568 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4569 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4570 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4571 AVX512FMA3Base, EVEX_B, EVEX_RC;
4573 } // Constraints = "$src1 = $dst"
4575 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4576 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4577 let Predicates = [HasAVX512] in {
4578 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4579 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4580 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4582 let Predicates = [HasVLX, HasAVX512] in {
4583 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4584 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4585 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4586 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4590 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4591 SDNode OpNodeRnd > {
4592 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4594 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4595 avx512vl_f64_info>, VEX_W;
4598 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4599 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4600 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4601 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4602 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4603 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4605 let Constraints = "$src1 = $dst" in {
4606 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4607 X86VectorVTInfo _> {
4608 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4609 (ins _.RC:$src3, _.RC:$src2),
4610 OpcodeStr, "$src2, $src3", "$src3, $src2",
4611 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4614 let mayLoad = 1 in {
4615 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4616 (ins _.RC:$src3, _.MemOp:$src2),
4617 OpcodeStr, "$src2, $src3", "$src3, $src2",
4618 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4621 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4622 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4623 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4624 "$src3, ${src2}"##_.BroadcastStr,
4625 (_.VT (OpNode _.RC:$src1,
4626 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4627 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4631 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4632 X86VectorVTInfo _> {
4633 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4634 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4635 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4636 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4637 AVX512FMA3Base, EVEX_B, EVEX_RC;
4639 } // Constraints = "$src1 = $dst"
4641 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4642 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4643 let Predicates = [HasAVX512] in {
4644 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4645 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4646 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4648 let Predicates = [HasVLX, HasAVX512] in {
4649 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4650 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4651 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4652 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4656 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4657 SDNode OpNodeRnd > {
4658 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4660 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4661 avx512vl_f64_info>, VEX_W;
4664 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4665 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4666 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4667 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4668 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4669 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4672 let Constraints = "$src1 = $dst" in {
4673 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4674 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4675 dag RHS_r, dag RHS_m > {
4676 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4677 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4678 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4681 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4682 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4683 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4685 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4686 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4687 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4688 AVX512FMA3Base, EVEX_B, EVEX_RC;
4690 let isCodeGenOnly = 1 in {
4691 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4692 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4693 !strconcat(OpcodeStr,
4694 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4697 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4698 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4699 !strconcat(OpcodeStr,
4700 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4702 }// isCodeGenOnly = 1
4704 }// Constraints = "$src1 = $dst"
4706 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4707 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4710 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4711 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4712 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4713 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4714 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4716 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4718 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4719 (_.ScalarLdFrag addr:$src3))))>;
4721 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4722 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4723 (_.VT (OpNode _.RC:$src2,
4724 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4726 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4728 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4730 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4731 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4733 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4734 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4735 (_.VT (OpNode _.RC:$src1,
4736 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4738 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4740 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4742 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4743 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4746 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4747 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4748 let Predicates = [HasAVX512] in {
4749 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4750 OpNodeRnd, f32x_info, "SS">,
4751 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4752 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4753 OpNodeRnd, f64x_info, "SD">,
4754 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4758 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4759 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4760 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4761 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4763 //===----------------------------------------------------------------------===//
4764 // AVX-512 Scalar convert from sign integer to float/double
4765 //===----------------------------------------------------------------------===//
4767 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4768 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4769 PatFrag ld_frag, string asm> {
4770 let hasSideEffects = 0 in {
4771 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4772 (ins DstVT.FRC:$src1, SrcRC:$src),
4773 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4776 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4777 (ins DstVT.FRC:$src1, x86memop:$src),
4778 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4780 } // hasSideEffects = 0
4781 let isCodeGenOnly = 1 in {
4782 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4783 (ins DstVT.RC:$src1, SrcRC:$src2),
4784 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4785 [(set DstVT.RC:$dst,
4786 (OpNode (DstVT.VT DstVT.RC:$src1),
4788 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4790 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4791 (ins DstVT.RC:$src1, x86memop:$src2),
4792 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4793 [(set DstVT.RC:$dst,
4794 (OpNode (DstVT.VT DstVT.RC:$src1),
4795 (ld_frag addr:$src2),
4796 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4797 }//isCodeGenOnly = 1
4800 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4801 X86VectorVTInfo DstVT, string asm> {
4802 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4803 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4805 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4806 [(set DstVT.RC:$dst,
4807 (OpNode (DstVT.VT DstVT.RC:$src1),
4809 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4812 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4813 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4814 PatFrag ld_frag, string asm> {
4815 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4816 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4820 let Predicates = [HasAVX512] in {
4821 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4822 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4823 XS, EVEX_CD8<32, CD8VT1>;
4824 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4825 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4826 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4827 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4828 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4829 XD, EVEX_CD8<32, CD8VT1>;
4830 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4831 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4832 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4834 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4835 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4836 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4837 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4838 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4839 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4840 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4841 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4843 def : Pat<(f32 (sint_to_fp GR32:$src)),
4844 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4845 def : Pat<(f32 (sint_to_fp GR64:$src)),
4846 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4847 def : Pat<(f64 (sint_to_fp GR32:$src)),
4848 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4849 def : Pat<(f64 (sint_to_fp GR64:$src)),
4850 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4852 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4853 v4f32x_info, i32mem, loadi32,
4854 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4855 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4856 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4857 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4858 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4859 i32mem, loadi32, "cvtusi2sd{l}">,
4860 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4861 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4862 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4863 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4865 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4866 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4867 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4868 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4869 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4870 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4871 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4872 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4874 def : Pat<(f32 (uint_to_fp GR32:$src)),
4875 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4876 def : Pat<(f32 (uint_to_fp GR64:$src)),
4877 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4878 def : Pat<(f64 (uint_to_fp GR32:$src)),
4879 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4880 def : Pat<(f64 (uint_to_fp GR64:$src)),
4881 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4884 //===----------------------------------------------------------------------===//
4885 // AVX-512 Scalar convert from float/double to integer
4886 //===----------------------------------------------------------------------===//
4887 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4888 RegisterClass DstRC, Intrinsic Int,
4889 Operand memop, ComplexPattern mem_cpat, string asm> {
4890 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4891 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4892 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4893 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4894 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4895 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4896 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4898 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4899 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4900 } // hasSideEffects = 0, Predicates = [HasAVX512]
4903 // Convert float/double to signed/unsigned int 32/64
4904 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4905 ssmem, sse_load_f32, "cvtss2si">,
4906 XS, EVEX_CD8<32, CD8VT1>;
4907 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4908 int_x86_sse_cvtss2si64,
4909 ssmem, sse_load_f32, "cvtss2si">,
4910 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4911 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4912 int_x86_avx512_cvtss2usi,
4913 ssmem, sse_load_f32, "cvtss2usi">,
4914 XS, EVEX_CD8<32, CD8VT1>;
4915 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4916 int_x86_avx512_cvtss2usi64, ssmem,
4917 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4918 EVEX_CD8<32, CD8VT1>;
4919 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4920 sdmem, sse_load_f64, "cvtsd2si">,
4921 XD, EVEX_CD8<64, CD8VT1>;
4922 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4923 int_x86_sse2_cvtsd2si64,
4924 sdmem, sse_load_f64, "cvtsd2si">,
4925 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4926 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4927 int_x86_avx512_cvtsd2usi,
4928 sdmem, sse_load_f64, "cvtsd2usi">,
4929 XD, EVEX_CD8<64, CD8VT1>;
4930 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4931 int_x86_avx512_cvtsd2usi64, sdmem,
4932 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4933 EVEX_CD8<64, CD8VT1>;
4935 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4936 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4937 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4938 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4939 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4940 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4941 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4942 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4943 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4944 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4945 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4946 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4947 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4949 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4950 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4951 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4952 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4954 // Convert float/double to signed/unsigned int 32/64 with truncation
4955 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4956 X86VectorVTInfo _DstRC, SDNode OpNode,
4958 let Predicates = [HasAVX512] in {
4959 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4960 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4961 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4962 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4963 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4965 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4966 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4967 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4970 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4971 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4972 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4973 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4974 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4975 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4976 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4977 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4978 (i32 FROUND_NO_EXC)))]>,
4979 EVEX,VEX_LIG , EVEX_B;
4981 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4982 (ins _SrcRC.MemOp:$src),
4983 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4986 } // isCodeGenOnly = 1, hasSideEffects = 0
4991 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4992 fp_to_sint,X86cvttss2IntRnd>,
4993 XS, EVEX_CD8<32, CD8VT1>;
4994 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4995 fp_to_sint,X86cvttss2IntRnd>,
4996 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4997 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4998 fp_to_sint,X86cvttsd2IntRnd>,
4999 XD, EVEX_CD8<64, CD8VT1>;
5000 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
5001 fp_to_sint,X86cvttsd2IntRnd>,
5002 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
5004 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
5005 fp_to_uint,X86cvttss2UIntRnd>,
5006 XS, EVEX_CD8<32, CD8VT1>;
5007 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
5008 fp_to_uint,X86cvttss2UIntRnd>,
5009 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
5010 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
5011 fp_to_uint,X86cvttsd2UIntRnd>,
5012 XD, EVEX_CD8<64, CD8VT1>;
5013 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
5014 fp_to_uint,X86cvttsd2UIntRnd>,
5015 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5016 let Predicates = [HasAVX512] in {
5017 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
5018 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5019 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
5020 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5021 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
5022 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5023 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
5024 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5027 //===----------------------------------------------------------------------===//
5028 // AVX-512 Convert form float to double and back
5029 //===----------------------------------------------------------------------===//
5030 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5031 X86VectorVTInfo _Src, SDNode OpNode> {
5032 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5033 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5034 "$src2, $src1", "$src1, $src2",
5035 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5036 (_Src.VT _Src.RC:$src2)))>,
5037 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
5038 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5039 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
5040 "$src2, $src1", "$src1, $src2",
5041 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5042 (_Src.VT (scalar_to_vector
5043 (_Src.ScalarLdFrag addr:$src2)))))>,
5044 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
5047 // Scalar Coversion with SAE - suppress all exceptions
5048 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5049 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5050 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5051 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5052 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5053 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5054 (_Src.VT _Src.RC:$src2),
5055 (i32 FROUND_NO_EXC)))>,
5056 EVEX_4V, VEX_LIG, EVEX_B;
5059 // Scalar Conversion with rounding control (RC)
5060 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5061 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5062 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5063 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
5064 "$rc, $src2, $src1", "$src1, $src2, $rc",
5065 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5066 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
5067 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
5070 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
5071 SDNode OpNodeRnd, X86VectorVTInfo _src,
5072 X86VectorVTInfo _dst> {
5073 let Predicates = [HasAVX512] in {
5074 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5075 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
5076 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
5081 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5082 SDNode OpNodeRnd, X86VectorVTInfo _src,
5083 X86VectorVTInfo _dst> {
5084 let Predicates = [HasAVX512] in {
5085 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5086 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
5087 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
5090 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
5091 X86froundRnd, f64x_info, f32x_info>;
5092 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
5093 X86fpextRnd,f32x_info, f64x_info >;
5095 def : Pat<(f64 (fextend FR32X:$src)),
5096 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
5097 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
5098 Requires<[HasAVX512]>;
5099 def : Pat<(f64 (fextend (loadf32 addr:$src))),
5100 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5101 Requires<[HasAVX512]>;
5103 def : Pat<(f64 (extloadf32 addr:$src)),
5104 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5105 Requires<[HasAVX512, OptForSize]>;
5107 def : Pat<(f64 (extloadf32 addr:$src)),
5108 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
5109 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
5110 Requires<[HasAVX512, OptForSpeed]>;
5112 def : Pat<(f32 (fround FR64X:$src)),
5113 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
5114 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
5115 Requires<[HasAVX512]>;
5116 //===----------------------------------------------------------------------===//
5117 // AVX-512 Vector convert from signed/unsigned integer to float/double
5118 // and from float/double to signed/unsigned integer
5119 //===----------------------------------------------------------------------===//
5121 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5122 X86VectorVTInfo _Src, SDNode OpNode,
5123 string Broadcast = _.BroadcastStr,
5124 string Alias = ""> {
5126 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5127 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
5128 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
5130 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5131 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
5132 (_.VT (OpNode (_Src.VT
5133 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
5135 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5136 (ins _Src.MemOp:$src), OpcodeStr,
5137 "${src}"##Broadcast, "${src}"##Broadcast,
5138 (_.VT (OpNode (_Src.VT
5139 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
5142 // Coversion with SAE - suppress all exceptions
5143 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5144 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5145 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5146 (ins _Src.RC:$src), OpcodeStr,
5147 "{sae}, $src", "$src, {sae}",
5148 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
5149 (i32 FROUND_NO_EXC)))>,
5153 // Conversion with rounding control (RC)
5154 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5155 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5156 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5157 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5158 "$rc, $src", "$src, $rc",
5159 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5160 EVEX, EVEX_B, EVEX_RC;
5163 // Extend Float to Double
5164 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5165 let Predicates = [HasAVX512] in {
5166 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5167 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5168 X86vfpextRnd>, EVEX_V512;
5170 let Predicates = [HasVLX] in {
5171 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5172 X86vfpext, "{1to2}">, EVEX_V128;
5173 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5178 // Truncate Double to Float
5179 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5180 let Predicates = [HasAVX512] in {
5181 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5182 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5183 X86vfproundRnd>, EVEX_V512;
5185 let Predicates = [HasVLX] in {
5186 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5187 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5188 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5189 "{1to4}", "{y}">, EVEX_V256;
5193 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5194 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5195 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5196 PS, EVEX_CD8<32, CD8VH>;
5198 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5199 (VCVTPS2PDZrm addr:$src)>;
5201 let Predicates = [HasVLX] in {
5202 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5203 (VCVTPS2PDZ256rm addr:$src)>;
5206 // Convert Signed/Unsigned Doubleword to Double
5207 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5209 // No rounding in this op
5210 let Predicates = [HasAVX512] in
5211 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5214 let Predicates = [HasVLX] in {
5215 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5216 OpNode128, "{1to2}">, EVEX_V128;
5217 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5222 // Convert Signed/Unsigned Doubleword to Float
5223 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5225 let Predicates = [HasAVX512] in
5226 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5227 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5228 OpNodeRnd>, EVEX_V512;
5230 let Predicates = [HasVLX] in {
5231 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5233 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5238 // Convert Float to Signed/Unsigned Doubleword with truncation
5239 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5240 SDNode OpNode, SDNode OpNodeRnd> {
5241 let Predicates = [HasAVX512] in {
5242 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5243 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5244 OpNodeRnd>, EVEX_V512;
5246 let Predicates = [HasVLX] in {
5247 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5249 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5254 // Convert Float to Signed/Unsigned Doubleword
5255 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5256 SDNode OpNode, SDNode OpNodeRnd> {
5257 let Predicates = [HasAVX512] in {
5258 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5259 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5260 OpNodeRnd>, EVEX_V512;
5262 let Predicates = [HasVLX] in {
5263 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5265 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5270 // Convert Double to Signed/Unsigned Doubleword with truncation
5271 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5272 SDNode OpNode, SDNode OpNodeRnd> {
5273 let Predicates = [HasAVX512] in {
5274 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5275 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5276 OpNodeRnd>, EVEX_V512;
5278 let Predicates = [HasVLX] in {
5279 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5280 // memory forms of these instructions in Asm Parcer. They have the same
5281 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5282 // due to the same reason.
5283 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5284 "{1to2}", "{x}">, EVEX_V128;
5285 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5286 "{1to4}", "{y}">, EVEX_V256;
5290 // Convert Double to Signed/Unsigned Doubleword
5291 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5292 SDNode OpNode, SDNode OpNodeRnd> {
5293 let Predicates = [HasAVX512] in {
5294 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5295 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5296 OpNodeRnd>, EVEX_V512;
5298 let Predicates = [HasVLX] in {
5299 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5300 // memory forms of these instructions in Asm Parcer. They have the same
5301 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5302 // due to the same reason.
5303 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5304 "{1to2}", "{x}">, EVEX_V128;
5305 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5306 "{1to4}", "{y}">, EVEX_V256;
5310 // Convert Double to Signed/Unsigned Quardword
5311 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5312 SDNode OpNode, SDNode OpNodeRnd> {
5313 let Predicates = [HasDQI] in {
5314 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5315 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5316 OpNodeRnd>, EVEX_V512;
5318 let Predicates = [HasDQI, HasVLX] in {
5319 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5321 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5326 // Convert Double to Signed/Unsigned Quardword with truncation
5327 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5328 SDNode OpNode, SDNode OpNodeRnd> {
5329 let Predicates = [HasDQI] in {
5330 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5331 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5332 OpNodeRnd>, EVEX_V512;
5334 let Predicates = [HasDQI, HasVLX] in {
5335 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5337 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5342 // Convert Signed/Unsigned Quardword to Double
5343 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5344 SDNode OpNode, SDNode OpNodeRnd> {
5345 let Predicates = [HasDQI] in {
5346 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5347 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5348 OpNodeRnd>, EVEX_V512;
5350 let Predicates = [HasDQI, HasVLX] in {
5351 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5353 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5358 // Convert Float to Signed/Unsigned Quardword
5359 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5360 SDNode OpNode, SDNode OpNodeRnd> {
5361 let Predicates = [HasDQI] in {
5362 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5363 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5364 OpNodeRnd>, EVEX_V512;
5366 let Predicates = [HasDQI, HasVLX] in {
5367 // Explicitly specified broadcast string, since we take only 2 elements
5368 // from v4f32x_info source
5369 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5370 "{1to2}">, EVEX_V128;
5371 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5376 // Convert Float to Signed/Unsigned Quardword with truncation
5377 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5378 SDNode OpNode, SDNode OpNodeRnd> {
5379 let Predicates = [HasDQI] in {
5380 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5381 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5382 OpNodeRnd>, EVEX_V512;
5384 let Predicates = [HasDQI, HasVLX] in {
5385 // Explicitly specified broadcast string, since we take only 2 elements
5386 // from v4f32x_info source
5387 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5388 "{1to2}">, EVEX_V128;
5389 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5394 // Convert Signed/Unsigned Quardword to Float
5395 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5396 SDNode OpNode, SDNode OpNodeRnd> {
5397 let Predicates = [HasDQI] in {
5398 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5399 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5400 OpNodeRnd>, EVEX_V512;
5402 let Predicates = [HasDQI, HasVLX] in {
5403 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5404 // memory forms of these instructions in Asm Parcer. They have the same
5405 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5406 // due to the same reason.
5407 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5408 "{1to2}", "{x}">, EVEX_V128;
5409 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5410 "{1to4}", "{y}">, EVEX_V256;
5414 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5415 EVEX_CD8<32, CD8VH>;
5417 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5419 PS, EVEX_CD8<32, CD8VF>;
5421 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5423 XS, EVEX_CD8<32, CD8VF>;
5425 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5427 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5429 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5430 X86VFpToUintRnd>, PS,
5431 EVEX_CD8<32, CD8VF>;
5433 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5434 X86VFpToUintRnd>, PS, VEX_W,
5435 EVEX_CD8<64, CD8VF>;
5437 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5438 XS, EVEX_CD8<32, CD8VH>;
5440 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5441 X86VUintToFpRnd>, XD,
5442 EVEX_CD8<32, CD8VF>;
5444 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5445 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5447 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5448 X86cvtpd2IntRnd>, XD, VEX_W,
5449 EVEX_CD8<64, CD8VF>;
5451 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5453 PS, EVEX_CD8<32, CD8VF>;
5454 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5455 X86cvtpd2UIntRnd>, VEX_W,
5456 PS, EVEX_CD8<64, CD8VF>;
5458 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5459 X86cvtpd2IntRnd>, VEX_W,
5460 PD, EVEX_CD8<64, CD8VF>;
5462 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5463 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5465 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5466 X86cvtpd2UIntRnd>, VEX_W,
5467 PD, EVEX_CD8<64, CD8VF>;
5469 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5470 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5472 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5473 X86VFpToSlongRnd>, VEX_W,
5474 PD, EVEX_CD8<64, CD8VF>;
5476 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5477 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5479 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5480 X86VFpToUlongRnd>, VEX_W,
5481 PD, EVEX_CD8<64, CD8VF>;
5483 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5484 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5486 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5487 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5489 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5490 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5492 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5493 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5495 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5496 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5498 let Predicates = [HasAVX512, NoVLX] in {
5499 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5500 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5501 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5503 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5504 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5505 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5507 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5508 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5509 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5511 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5512 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5513 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5515 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5516 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5517 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5520 let Predicates = [HasAVX512] in {
5521 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5522 (VCVTPD2PSZrm addr:$src)>;
5523 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5524 (VCVTPS2PDZrm addr:$src)>;
5527 //===----------------------------------------------------------------------===//
5528 // Half precision conversion instructions
5529 //===----------------------------------------------------------------------===//
5530 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5531 X86MemOperand x86memop, PatFrag ld_frag> {
5532 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5533 "vcvtph2ps", "$src", "$src",
5534 (X86cvtph2ps (_src.VT _src.RC:$src),
5535 (i32 FROUND_CURRENT))>, T8PD;
5536 let hasSideEffects = 0, mayLoad = 1 in {
5537 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5538 "vcvtph2ps", "$src", "$src",
5539 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5540 (i32 FROUND_CURRENT))>, T8PD;
5544 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5545 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5546 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5547 (X86cvtph2ps (_src.VT _src.RC:$src),
5548 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5552 let Predicates = [HasAVX512] in {
5553 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5554 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5555 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5556 let Predicates = [HasVLX] in {
5557 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5558 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5559 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5560 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5564 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5565 X86MemOperand x86memop> {
5566 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5567 (ins _src.RC:$src1, i32u8imm:$src2),
5568 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5569 (X86cvtps2ph (_src.VT _src.RC:$src1),
5571 (i32 FROUND_CURRENT))>, AVX512AIi8Base;
5572 let hasSideEffects = 0, mayStore = 1 in {
5573 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5574 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5575 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5576 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5577 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5579 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5580 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5581 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5585 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5586 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5587 (ins _src.RC:$src1, i32u8imm:$src2),
5588 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, $src2, {sae}",
5589 (X86cvtps2ph (_src.VT _src.RC:$src1),
5591 (i32 FROUND_NO_EXC))>, EVEX_B, AVX512AIi8Base;
5593 let Predicates = [HasAVX512] in {
5594 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5595 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5596 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5597 let Predicates = [HasVLX] in {
5598 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5599 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5600 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5601 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5605 // Unordered/Ordered scalar fp compare with Sea and set EFLAGS
5606 multiclass avx512_ord_cmp_sae<bits<8> opc, X86VectorVTInfo _, SDNode OpNode,
5608 def rb: AVX512<opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),
5609 !strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"),
5610 [(set EFLAGS, (OpNode (_.VT _.RC:$src1), _.RC:$src2,
5611 (i32 FROUND_NO_EXC)))],
5612 IIC_SSE_COMIS_RR>, EVEX, EVEX_B, VEX_LIG, EVEX_V128,
5616 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5617 defm VUCOMISSZ : avx512_ord_cmp_sae<0x2E, v4f32x_info, X86ucomiSae, "vucomiss">,
5618 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
5619 defm VUCOMISDZ : avx512_ord_cmp_sae<0x2E, v2f64x_info, X86ucomiSae, "vucomisd">,
5620 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
5621 defm VCOMISSZ : avx512_ord_cmp_sae<0x2F, v4f32x_info, X86comiSae, "vcomiss">,
5622 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
5623 defm VCOMISDZ : avx512_ord_cmp_sae<0x2F, v2f64x_info, X86comiSae, "vcomisd">,
5624 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
5627 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5628 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5629 "ucomiss">, PS, EVEX, VEX_LIG,
5630 EVEX_CD8<32, CD8VT1>;
5631 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5632 "ucomisd">, PD, EVEX,
5633 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5634 let Pattern = []<dag> in {
5635 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5636 "comiss">, PS, EVEX, VEX_LIG,
5637 EVEX_CD8<32, CD8VT1>;
5638 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5639 "comisd">, PD, EVEX,
5640 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5642 let isCodeGenOnly = 1 in {
5643 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5644 load, "ucomiss">, PS, EVEX, VEX_LIG,
5645 EVEX_CD8<32, CD8VT1>;
5646 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5647 load, "ucomisd">, PD, EVEX,
5648 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5650 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5651 load, "comiss">, PS, EVEX, VEX_LIG,
5652 EVEX_CD8<32, CD8VT1>;
5653 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5654 load, "comisd">, PD, EVEX,
5655 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5659 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5660 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5661 X86VectorVTInfo _> {
5662 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5663 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5664 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5665 "$src2, $src1", "$src1, $src2",
5666 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5667 let mayLoad = 1 in {
5668 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5669 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5670 "$src2, $src1", "$src1, $src2",
5671 (OpNode (_.VT _.RC:$src1),
5672 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5677 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5678 EVEX_CD8<32, CD8VT1>, T8PD;
5679 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5680 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5681 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5682 EVEX_CD8<32, CD8VT1>, T8PD;
5683 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5684 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5686 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5687 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5688 X86VectorVTInfo _> {
5689 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5690 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5691 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5692 let mayLoad = 1 in {
5693 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5694 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5696 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5697 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5698 (ins _.ScalarMemOp:$src), OpcodeStr,
5699 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5701 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5706 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5707 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5708 EVEX_V512, EVEX_CD8<32, CD8VF>;
5709 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5710 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5712 // Define only if AVX512VL feature is present.
5713 let Predicates = [HasVLX] in {
5714 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5715 OpNode, v4f32x_info>,
5716 EVEX_V128, EVEX_CD8<32, CD8VF>;
5717 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5718 OpNode, v8f32x_info>,
5719 EVEX_V256, EVEX_CD8<32, CD8VF>;
5720 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5721 OpNode, v2f64x_info>,
5722 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5723 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5724 OpNode, v4f64x_info>,
5725 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5729 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5730 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5732 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5733 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5736 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5737 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5738 "$src2, $src1", "$src1, $src2",
5739 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5740 (i32 FROUND_CURRENT))>;
5742 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5743 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5744 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5745 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5746 (i32 FROUND_NO_EXC))>, EVEX_B;
5748 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5749 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5750 "$src2, $src1", "$src1, $src2",
5751 (OpNode (_.VT _.RC:$src1),
5752 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5753 (i32 FROUND_CURRENT))>;
5756 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5757 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5758 EVEX_CD8<32, CD8VT1>;
5759 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5760 EVEX_CD8<64, CD8VT1>, VEX_W;
5763 let hasSideEffects = 0, Predicates = [HasERI] in {
5764 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5765 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5768 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5769 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5771 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5774 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5775 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5776 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5778 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5779 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5781 (bitconvert (_.LdFrag addr:$src))),
5782 (i32 FROUND_CURRENT))>;
5784 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5785 (ins _.MemOp:$src), OpcodeStr,
5786 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5788 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5789 (i32 FROUND_CURRENT))>, EVEX_B;
5791 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5793 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5794 (ins _.RC:$src), OpcodeStr,
5795 "{sae}, $src", "$src, {sae}",
5796 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5799 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5800 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5801 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5802 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5803 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5804 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5805 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5808 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5810 // Define only if AVX512VL feature is present.
5811 let Predicates = [HasVLX] in {
5812 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5813 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5814 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5815 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5816 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5817 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5818 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5819 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5822 let Predicates = [HasERI], hasSideEffects = 0 in {
5824 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5825 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5826 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5828 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5829 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5831 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5832 SDNode OpNodeRnd, X86VectorVTInfo _>{
5833 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5834 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5835 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5836 EVEX, EVEX_B, EVEX_RC;
5839 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5840 SDNode OpNode, X86VectorVTInfo _>{
5841 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5842 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5843 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5844 let mayLoad = 1 in {
5845 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5846 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5848 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5850 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5851 (ins _.ScalarMemOp:$src), OpcodeStr,
5852 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5854 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5859 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5861 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5863 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5864 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5866 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5867 // Define only if AVX512VL feature is present.
5868 let Predicates = [HasVLX] in {
5869 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5870 OpNode, v4f32x_info>,
5871 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5872 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5873 OpNode, v8f32x_info>,
5874 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5875 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5876 OpNode, v2f64x_info>,
5877 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5878 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5879 OpNode, v4f64x_info>,
5880 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5884 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5886 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5887 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5888 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5889 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5892 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5893 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5895 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5896 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5897 "$src2, $src1", "$src1, $src2",
5898 (OpNodeRnd (_.VT _.RC:$src1),
5900 (i32 FROUND_CURRENT))>;
5902 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5903 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5904 "$src2, $src1", "$src1, $src2",
5905 (OpNodeRnd (_.VT _.RC:$src1),
5906 (_.VT (scalar_to_vector
5907 (_.ScalarLdFrag addr:$src2))),
5908 (i32 FROUND_CURRENT))>;
5910 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5911 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5912 "$rc, $src2, $src1", "$src1, $src2, $rc",
5913 (OpNodeRnd (_.VT _.RC:$src1),
5918 let isCodeGenOnly = 1 in {
5919 def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
5920 (ins _.FRC:$src1, _.FRC:$src2),
5921 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5924 def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
5925 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5926 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5929 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5930 (!cast<Instruction>(NAME#SUFF#Zr)
5931 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5933 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5934 (!cast<Instruction>(NAME#SUFF#Zm)
5935 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5938 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5939 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5940 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5941 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5942 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5945 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5946 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5948 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5950 let Predicates = [HasAVX512] in {
5951 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5952 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5953 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5954 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5955 Requires<[OptForSize]>;
5956 def : Pat<(f32 (X86frcp FR32X:$src)),
5957 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5958 def : Pat<(f32 (X86frcp (load addr:$src))),
5959 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5960 Requires<[OptForSize]>;
5964 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5966 let ExeDomain = _.ExeDomain in {
5967 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5968 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5969 "$src3, $src2, $src1", "$src1, $src2, $src3",
5970 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5971 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5973 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5974 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5975 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5976 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5977 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5980 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5981 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5982 "$src3, $src2, $src1", "$src1, $src2, $src3",
5983 (_.VT (X86RndScales (_.VT _.RC:$src1),
5984 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5985 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5987 let Predicates = [HasAVX512] in {
5988 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5989 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5990 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5991 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5992 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5993 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5994 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5995 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5996 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5997 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5998 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5999 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
6000 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
6001 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
6002 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
6004 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6005 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6006 addr:$src, (i32 0x1))), _.FRC)>;
6007 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6008 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6009 addr:$src, (i32 0x2))), _.FRC)>;
6010 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6011 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6012 addr:$src, (i32 0x3))), _.FRC)>;
6013 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6014 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6015 addr:$src, (i32 0x4))), _.FRC)>;
6016 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6017 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6018 addr:$src, (i32 0xc))), _.FRC)>;
6022 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
6023 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6025 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
6026 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
6028 //-------------------------------------------------
6029 // Integer truncate and extend operations
6030 //-------------------------------------------------
6032 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
6033 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
6034 X86MemOperand x86memop> {
6036 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
6037 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
6038 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
6041 // for intrinsic patter match
6042 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6043 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6045 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6048 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6049 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6050 DestInfo.ImmAllZerosV)),
6051 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6054 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6055 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6056 DestInfo.RC:$src0)),
6057 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
6058 DestInfo.KRCWM:$mask ,
6061 let mayStore = 1 in {
6062 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
6063 (ins x86memop:$dst, SrcInfo.RC:$src),
6064 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6067 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
6068 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
6069 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6074 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
6075 X86VectorVTInfo DestInfo,
6076 PatFrag truncFrag, PatFrag mtruncFrag > {
6078 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
6079 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
6080 addr:$dst, SrcInfo.RC:$src)>;
6082 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
6083 (SrcInfo.VT SrcInfo.RC:$src)),
6084 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
6085 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
6088 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
6089 X86VectorVTInfo DestInfo, string sat > {
6091 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6092 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6093 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
6094 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
6095 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
6096 (SrcInfo.VT SrcInfo.RC:$src))>;
6098 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6099 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6100 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
6101 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
6102 (SrcInfo.VT SrcInfo.RC:$src))>;
6105 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
6106 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6107 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6108 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6109 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
6110 Predicate prd = HasAVX512>{
6112 let Predicates = [HasVLX, prd] in {
6113 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6114 DestInfoZ128, x86memopZ128>,
6115 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6116 truncFrag, mtruncFrag>, EVEX_V128;
6118 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6119 DestInfoZ256, x86memopZ256>,
6120 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6121 truncFrag, mtruncFrag>, EVEX_V256;
6123 let Predicates = [prd] in
6124 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6125 DestInfoZ, x86memopZ>,
6126 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6127 truncFrag, mtruncFrag>, EVEX_V512;
6130 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
6131 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6132 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6133 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6134 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
6136 let Predicates = [HasVLX, prd] in {
6137 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6138 DestInfoZ128, x86memopZ128>,
6139 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6142 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6143 DestInfoZ256, x86memopZ256>,
6144 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6147 let Predicates = [prd] in
6148 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6149 DestInfoZ, x86memopZ>,
6150 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6154 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6155 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6156 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6157 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
6159 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
6160 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
6161 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6162 sat>, EVEX_CD8<8, CD8VO>;
6165 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6166 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6167 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6168 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6170 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6171 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6172 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6173 sat>, EVEX_CD8<16, CD8VQ>;
6176 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6177 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6178 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6179 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6181 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6182 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6183 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6184 sat>, EVEX_CD8<32, CD8VH>;
6187 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6188 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6189 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6190 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6192 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6193 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6194 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6195 sat>, EVEX_CD8<8, CD8VQ>;
6198 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6199 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6200 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6201 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6203 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6204 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6205 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6206 sat>, EVEX_CD8<16, CD8VH>;
6209 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6210 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6211 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6212 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6214 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6215 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6216 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6217 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6220 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6221 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6222 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6224 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6225 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6226 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6228 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6229 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6230 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6232 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6233 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6234 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6236 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6237 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6238 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6240 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6241 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6242 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6244 let Predicates = [HasAVX512, NoVLX] in {
6245 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6246 (v8i16 (EXTRACT_SUBREG
6247 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6248 VR256X:$src, sub_ymm)))), sub_xmm))>;
6249 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6250 (v4i32 (EXTRACT_SUBREG
6251 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6252 VR256X:$src, sub_ymm)))), sub_xmm))>;
6255 let Predicates = [HasBWI, NoVLX] in {
6256 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6257 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6258 VR256X:$src, sub_ymm))), sub_xmm))>;
6261 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6262 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6263 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6265 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6266 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6267 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6270 let mayLoad = 1 in {
6271 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6272 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6273 (DestInfo.VT (LdFrag addr:$src))>,
6278 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6279 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6280 let Predicates = [HasVLX, HasBWI] in {
6281 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6282 v16i8x_info, i64mem, LdFrag, OpNode>,
6283 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6285 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6286 v16i8x_info, i128mem, LdFrag, OpNode>,
6287 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6289 let Predicates = [HasBWI] in {
6290 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6291 v32i8x_info, i256mem, LdFrag, OpNode>,
6292 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6296 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6297 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6298 let Predicates = [HasVLX, HasAVX512] in {
6299 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6300 v16i8x_info, i32mem, LdFrag, OpNode>,
6301 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6303 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6304 v16i8x_info, i64mem, LdFrag, OpNode>,
6305 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6307 let Predicates = [HasAVX512] in {
6308 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6309 v16i8x_info, i128mem, LdFrag, OpNode>,
6310 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6314 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6315 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6316 let Predicates = [HasVLX, HasAVX512] in {
6317 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6318 v16i8x_info, i16mem, LdFrag, OpNode>,
6319 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6321 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6322 v16i8x_info, i32mem, LdFrag, OpNode>,
6323 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6325 let Predicates = [HasAVX512] in {
6326 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6327 v16i8x_info, i64mem, LdFrag, OpNode>,
6328 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6332 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6333 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6334 let Predicates = [HasVLX, HasAVX512] in {
6335 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6336 v8i16x_info, i64mem, LdFrag, OpNode>,
6337 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6339 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6340 v8i16x_info, i128mem, LdFrag, OpNode>,
6341 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6343 let Predicates = [HasAVX512] in {
6344 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6345 v16i16x_info, i256mem, LdFrag, OpNode>,
6346 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6350 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6351 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6352 let Predicates = [HasVLX, HasAVX512] in {
6353 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6354 v8i16x_info, i32mem, LdFrag, OpNode>,
6355 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6357 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6358 v8i16x_info, i64mem, LdFrag, OpNode>,
6359 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6361 let Predicates = [HasAVX512] in {
6362 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6363 v8i16x_info, i128mem, LdFrag, OpNode>,
6364 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6368 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6369 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6371 let Predicates = [HasVLX, HasAVX512] in {
6372 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6373 v4i32x_info, i64mem, LdFrag, OpNode>,
6374 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6376 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6377 v4i32x_info, i128mem, LdFrag, OpNode>,
6378 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6380 let Predicates = [HasAVX512] in {
6381 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6382 v8i32x_info, i256mem, LdFrag, OpNode>,
6383 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6387 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6388 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6389 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6390 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6391 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6392 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6395 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6396 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6397 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6398 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6399 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6400 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6402 //===----------------------------------------------------------------------===//
6403 // GATHER - SCATTER Operations
6405 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6406 X86MemOperand memop, PatFrag GatherNode> {
6407 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6408 ExeDomain = _.ExeDomain in
6409 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6410 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6411 !strconcat(OpcodeStr#_.Suffix,
6412 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6413 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6414 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6415 vectoraddr:$src2))]>, EVEX, EVEX_K,
6416 EVEX_CD8<_.EltSize, CD8VT1>;
6419 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6420 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6421 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6422 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6423 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6424 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6425 let Predicates = [HasVLX] in {
6426 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6427 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6428 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6429 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6430 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6431 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6432 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6433 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6437 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6438 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6439 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6440 mgatherv16i32>, EVEX_V512;
6441 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6442 mgatherv8i64>, EVEX_V512;
6443 let Predicates = [HasVLX] in {
6444 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6445 vy32xmem, mgatherv8i32>, EVEX_V256;
6446 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6447 vy64xmem, mgatherv4i64>, EVEX_V256;
6448 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6449 vx32xmem, mgatherv4i32>, EVEX_V128;
6450 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6451 vx64xmem, mgatherv2i64>, EVEX_V128;
6456 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6457 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6459 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6460 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6462 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6463 X86MemOperand memop, PatFrag ScatterNode> {
6465 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6467 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6468 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6469 !strconcat(OpcodeStr#_.Suffix,
6470 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6471 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6472 _.KRCWM:$mask, vectoraddr:$dst))]>,
6473 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6476 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6477 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6478 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6479 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6480 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6481 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6482 let Predicates = [HasVLX] in {
6483 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6484 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6485 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6486 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6487 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6488 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6489 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6490 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6494 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6495 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6496 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6497 mscatterv16i32>, EVEX_V512;
6498 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6499 mscatterv8i64>, EVEX_V512;
6500 let Predicates = [HasVLX] in {
6501 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6502 vy32xmem, mscatterv8i32>, EVEX_V256;
6503 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6504 vy64xmem, mscatterv4i64>, EVEX_V256;
6505 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6506 vx32xmem, mscatterv4i32>, EVEX_V128;
6507 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6508 vx64xmem, mscatterv2i64>, EVEX_V128;
6512 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6513 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6515 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6516 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6519 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6520 RegisterClass KRC, X86MemOperand memop> {
6521 let Predicates = [HasPFI], hasSideEffects = 1 in
6522 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6523 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6527 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6528 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6530 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6531 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6533 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6534 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6536 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6537 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6539 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6540 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6542 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6543 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6545 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6546 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6548 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6549 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6551 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6552 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6554 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6555 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6557 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6558 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6560 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6561 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6563 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6564 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6566 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6567 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6569 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6570 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6572 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6573 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6575 // Helper fragments to match sext vXi1 to vXiY.
6576 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6577 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6579 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6580 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6581 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6583 def : Pat<(store VK1:$src, addr:$dst),
6585 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6586 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6588 def : Pat<(store VK8:$src, addr:$dst),
6590 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6591 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6593 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6594 (truncstore node:$val, node:$ptr), [{
6595 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6598 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6599 (MOV8mr addr:$dst, GR8:$src)>;
6601 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6602 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6603 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6604 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6607 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6608 string OpcodeStr, Predicate prd> {
6609 let Predicates = [prd] in
6610 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6612 let Predicates = [prd, HasVLX] in {
6613 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6614 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6618 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6619 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6621 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6623 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6625 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6629 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6631 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6632 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6633 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6634 [(set _.KRC:$dst, (X86cvt2mask (_.VT _.RC:$src)))]>, EVEX;
6637 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6638 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6639 let Predicates = [prd] in
6640 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6643 let Predicates = [prd, HasVLX] in {
6644 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6646 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6651 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6652 avx512vl_i8_info, HasBWI>;
6653 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6654 avx512vl_i16_info, HasBWI>, VEX_W;
6655 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6656 avx512vl_i32_info, HasDQI>;
6657 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6658 avx512vl_i64_info, HasDQI>, VEX_W;
6660 //===----------------------------------------------------------------------===//
6661 // AVX-512 - COMPRESS and EXPAND
6664 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6666 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6667 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6668 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6670 let mayStore = 1 in {
6671 def mr : AVX5128I<opc, MRMDestMem, (outs),
6672 (ins _.MemOp:$dst, _.RC:$src),
6673 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6674 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6676 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6677 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6678 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6679 [(store (_.VT (vselect _.KRCWM:$mask,
6680 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6682 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6686 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6687 AVX512VLVectorVTInfo VTInfo> {
6688 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6690 let Predicates = [HasVLX] in {
6691 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6692 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6696 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6698 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6700 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6702 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6706 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6708 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6709 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6710 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6713 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6714 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6715 (_.VT (X86expand (_.VT (bitconvert
6716 (_.LdFrag addr:$src1)))))>,
6717 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6720 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6721 AVX512VLVectorVTInfo VTInfo> {
6722 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6724 let Predicates = [HasVLX] in {
6725 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6726 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6730 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6732 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6734 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6736 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6739 //handle instruction reg_vec1 = op(reg_vec,imm)
6741 // op(broadcast(eltVt),imm)
6742 //all instruction created with FROUND_CURRENT
6743 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6745 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6746 (ins _.RC:$src1, i32u8imm:$src2),
6747 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6748 (OpNode (_.VT _.RC:$src1),
6750 (i32 FROUND_CURRENT))>;
6751 let mayLoad = 1 in {
6752 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6753 (ins _.MemOp:$src1, i32u8imm:$src2),
6754 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6755 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6757 (i32 FROUND_CURRENT))>;
6758 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6759 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6760 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6761 "${src1}"##_.BroadcastStr##", $src2",
6762 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6764 (i32 FROUND_CURRENT))>, EVEX_B;
6768 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6769 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6770 SDNode OpNode, X86VectorVTInfo _>{
6771 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6772 (ins _.RC:$src1, i32u8imm:$src2),
6773 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6774 "$src1, {sae}, $src2",
6775 (OpNode (_.VT _.RC:$src1),
6777 (i32 FROUND_NO_EXC))>, EVEX_B;
6780 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6781 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6782 let Predicates = [prd] in {
6783 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6784 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6787 let Predicates = [prd, HasVLX] in {
6788 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6790 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6795 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6796 // op(reg_vec2,mem_vec,imm)
6797 // op(reg_vec2,broadcast(eltVt),imm)
6798 //all instruction created with FROUND_CURRENT
6799 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6801 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6802 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6803 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6804 (OpNode (_.VT _.RC:$src1),
6807 (i32 FROUND_CURRENT))>;
6808 let mayLoad = 1 in {
6809 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6810 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6811 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6812 (OpNode (_.VT _.RC:$src1),
6813 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6815 (i32 FROUND_CURRENT))>;
6816 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6817 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6818 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6819 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6820 (OpNode (_.VT _.RC:$src1),
6821 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6823 (i32 FROUND_CURRENT))>, EVEX_B;
6827 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6828 // op(reg_vec2,mem_vec,imm)
6829 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6830 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6832 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6833 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6834 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6835 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6836 (SrcInfo.VT SrcInfo.RC:$src2),
6839 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6840 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6841 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6842 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6843 (SrcInfo.VT (bitconvert
6844 (SrcInfo.LdFrag addr:$src2))),
6848 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6849 // op(reg_vec2,mem_vec,imm)
6850 // op(reg_vec2,broadcast(eltVt),imm)
6851 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6853 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6856 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6857 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6858 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6859 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6860 (OpNode (_.VT _.RC:$src1),
6861 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6862 (i8 imm:$src3))>, EVEX_B;
6865 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6866 // op(reg_vec2,mem_scalar,imm)
6867 //all instruction created with FROUND_CURRENT
6868 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6869 X86VectorVTInfo _> {
6871 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6872 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6873 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6874 (OpNode (_.VT _.RC:$src1),
6877 (i32 FROUND_CURRENT))>;
6878 let mayLoad = 1 in {
6879 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6880 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6881 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6882 (OpNode (_.VT _.RC:$src1),
6883 (_.VT (scalar_to_vector
6884 (_.ScalarLdFrag addr:$src2))),
6886 (i32 FROUND_CURRENT))>;
6888 let isAsmParserOnly = 1 in {
6889 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6890 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6891 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6897 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6898 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6899 SDNode OpNode, X86VectorVTInfo _>{
6900 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6901 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6902 OpcodeStr, "$src3,{sae}, $src2, $src1",
6903 "$src1, $src2,{sae}, $src3",
6904 (OpNode (_.VT _.RC:$src1),
6907 (i32 FROUND_NO_EXC))>, EVEX_B;
6909 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6910 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6911 SDNode OpNode, X86VectorVTInfo _> {
6912 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6913 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6914 OpcodeStr, "$src3,{sae}, $src2, $src1",
6915 "$src1, $src2,{sae}, $src3",
6916 (OpNode (_.VT _.RC:$src1),
6919 (i32 FROUND_NO_EXC))>, EVEX_B;
6922 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6923 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6924 let Predicates = [prd] in {
6925 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6926 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6930 let Predicates = [prd, HasVLX] in {
6931 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6933 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6938 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6939 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6940 let Predicates = [HasBWI] in {
6941 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6942 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6944 let Predicates = [HasBWI, HasVLX] in {
6945 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6946 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6947 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6948 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6952 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6953 bits<8> opc, SDNode OpNode>{
6954 let Predicates = [HasAVX512] in {
6955 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6957 let Predicates = [HasAVX512, HasVLX] in {
6958 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6959 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6963 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6964 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6965 let Predicates = [prd] in {
6966 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6967 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6971 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6972 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6973 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6974 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6975 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6976 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6979 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6980 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6981 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6982 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6983 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6984 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6986 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6987 0x55, X86VFixupimm, HasAVX512>,
6988 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6989 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6990 0x55, X86VFixupimm, HasAVX512>,
6991 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6993 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6994 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6995 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6996 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6997 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6998 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
7001 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
7002 0x50, X86VRange, HasDQI>,
7003 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7004 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
7005 0x50, X86VRange, HasDQI>,
7006 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7008 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
7009 0x51, X86VRange, HasDQI>,
7010 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7011 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
7012 0x51, X86VRange, HasDQI>,
7013 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7015 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
7016 0x57, X86Reduces, HasDQI>,
7017 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7018 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
7019 0x57, X86Reduces, HasDQI>,
7020 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7022 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
7023 0x27, X86GetMants, HasAVX512>,
7024 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7025 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
7026 0x27, X86GetMants, HasAVX512>,
7027 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7029 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
7030 bits<8> opc, SDNode OpNode = X86Shuf128>{
7031 let Predicates = [HasAVX512] in {
7032 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
7035 let Predicates = [HasAVX512, HasVLX] in {
7036 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
7039 let Predicates = [HasAVX512] in {
7040 def : Pat<(v16f32 (ffloor VR512:$src)),
7041 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
7042 def : Pat<(v16f32 (fnearbyint VR512:$src)),
7043 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
7044 def : Pat<(v16f32 (fceil VR512:$src)),
7045 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
7046 def : Pat<(v16f32 (frint VR512:$src)),
7047 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
7048 def : Pat<(v16f32 (ftrunc VR512:$src)),
7049 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
7051 def : Pat<(v8f64 (ffloor VR512:$src)),
7052 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
7053 def : Pat<(v8f64 (fnearbyint VR512:$src)),
7054 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
7055 def : Pat<(v8f64 (fceil VR512:$src)),
7056 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
7057 def : Pat<(v8f64 (frint VR512:$src)),
7058 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
7059 def : Pat<(v8f64 (ftrunc VR512:$src)),
7060 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
7063 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
7064 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7065 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
7066 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7067 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
7068 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7069 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
7070 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7072 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I> {
7073 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
7074 AVX512AIi8Base, EVEX_4V;
7077 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info>,
7078 EVEX_CD8<32, CD8VF>;
7079 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info>,
7080 EVEX_CD8<64, CD8VF>, VEX_W;
7082 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
7083 let Predicates = p in
7084 def NAME#_.VTName#rri:
7085 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
7086 (!cast<Instruction>(NAME#_.ZSuffix#rri)
7087 _.RC:$src1, _.RC:$src2, imm:$imm)>;
7090 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
7091 avx512_vpalign_lowering<_.info512, [HasBWI]>,
7092 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
7093 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
7095 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
7096 avx512vl_i8_info, avx512vl_i8_info>,
7097 avx512_vpalign_lowering_common<avx512vl_i16_info>,
7098 avx512_vpalign_lowering_common<avx512vl_i32_info>,
7099 avx512_vpalign_lowering_common<avx512vl_f32_info>,
7100 avx512_vpalign_lowering_common<avx512vl_i64_info>,
7101 avx512_vpalign_lowering_common<avx512vl_f64_info>,
7104 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
7105 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
7107 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7108 X86VectorVTInfo _> {
7109 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7110 (ins _.RC:$src1), OpcodeStr,
7112 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
7115 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7116 (ins _.MemOp:$src1), OpcodeStr,
7118 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
7119 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
7122 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7123 X86VectorVTInfo _> :
7124 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
7126 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7127 (ins _.ScalarMemOp:$src1), OpcodeStr,
7128 "${src1}"##_.BroadcastStr,
7129 "${src1}"##_.BroadcastStr,
7130 (_.VT (OpNode (X86VBroadcast
7131 (_.ScalarLdFrag addr:$src1))))>,
7132 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
7135 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7136 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7137 let Predicates = [prd] in
7138 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7140 let Predicates = [prd, HasVLX] in {
7141 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7143 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
7148 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7149 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7150 let Predicates = [prd] in
7151 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
7154 let Predicates = [prd, HasVLX] in {
7155 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
7157 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7162 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7163 SDNode OpNode, Predicate prd> {
7164 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
7166 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
7170 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7171 SDNode OpNode, Predicate prd> {
7172 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
7173 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
7176 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7177 bits<8> opc_d, bits<8> opc_q,
7178 string OpcodeStr, SDNode OpNode> {
7179 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7181 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7185 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7188 (bc_v16i32 (v16i1sextv16i32)),
7189 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7190 (VPABSDZrr VR512:$src)>;
7192 (bc_v8i64 (v8i1sextv8i64)),
7193 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7194 (VPABSQZrr VR512:$src)>;
7196 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7198 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7201 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7202 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7204 //===---------------------------------------------------------------------===//
7205 // Replicate Single FP - MOVSHDUP and MOVSLDUP
7206 //===---------------------------------------------------------------------===//
7207 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7208 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
7212 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
7213 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
7215 //===----------------------------------------------------------------------===//
7216 // AVX-512 - MOVDDUP
7217 //===----------------------------------------------------------------------===//
7219 multiclass avx512_movddup_128<bits<8> opc, string OpcodeStr, SDNode OpNode,
7220 X86VectorVTInfo _> {
7221 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7222 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7223 (_.VT (OpNode (_.VT _.RC:$src)))>, EVEX;
7225 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7226 (ins _.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
7227 (_.VT (OpNode (_.VT (scalar_to_vector
7228 (_.ScalarLdFrag addr:$src)))))>,
7229 EVEX, EVEX_CD8<_.EltSize, CD8VH>;
7232 multiclass avx512_movddup_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
7233 AVX512VLVectorVTInfo VTInfo> {
7235 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7237 let Predicates = [HasAVX512, HasVLX] in {
7238 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7240 defm Z128 : avx512_movddup_128<opc, OpcodeStr, OpNode, VTInfo.info128>,
7245 multiclass avx512_movddup<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7246 defm NAME: avx512_movddup_common<opc, OpcodeStr, OpNode,
7247 avx512vl_f64_info>, XD, VEX_W;
7250 defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup>;
7252 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
7253 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7254 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
7255 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7257 //===----------------------------------------------------------------------===//
7258 // AVX-512 - Unpack Instructions
7259 //===----------------------------------------------------------------------===//
7260 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
7261 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
7263 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7264 SSE_INTALU_ITINS_P, HasBWI>;
7265 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7266 SSE_INTALU_ITINS_P, HasBWI>;
7267 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7268 SSE_INTALU_ITINS_P, HasBWI>;
7269 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7270 SSE_INTALU_ITINS_P, HasBWI>;
7272 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7273 SSE_INTALU_ITINS_P, HasAVX512>;
7274 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7275 SSE_INTALU_ITINS_P, HasAVX512>;
7276 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7277 SSE_INTALU_ITINS_P, HasAVX512>;
7278 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7279 SSE_INTALU_ITINS_P, HasAVX512>;
7281 //===----------------------------------------------------------------------===//
7282 // AVX-512 - Extract & Insert Integer Instructions
7283 //===----------------------------------------------------------------------===//
7285 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7286 X86VectorVTInfo _> {
7288 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7289 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7290 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7291 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7294 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7297 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7298 let Predicates = [HasBWI] in {
7299 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7300 (ins _.RC:$src1, u8imm:$src2),
7301 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7302 [(set GR32orGR64:$dst,
7303 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7306 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7310 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7311 let Predicates = [HasBWI] in {
7312 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7313 (ins _.RC:$src1, u8imm:$src2),
7314 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7315 [(set GR32orGR64:$dst,
7316 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7319 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
7320 (ins _.RC:$src1, u8imm:$src2),
7321 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7324 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7328 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7329 RegisterClass GRC> {
7330 let Predicates = [HasDQI] in {
7331 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7332 (ins _.RC:$src1, u8imm:$src2),
7333 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7335 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7339 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7340 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7341 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7342 [(store (extractelt (_.VT _.RC:$src1),
7343 imm:$src2),addr:$dst)]>,
7344 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7348 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7349 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7350 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7351 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7353 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7354 X86VectorVTInfo _, PatFrag LdFrag> {
7355 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7356 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7357 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7359 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7360 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7363 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7364 X86VectorVTInfo _, PatFrag LdFrag> {
7365 let Predicates = [HasBWI] in {
7366 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7367 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7368 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7370 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7372 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7376 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7377 X86VectorVTInfo _, RegisterClass GRC> {
7378 let Predicates = [HasDQI] in {
7379 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7380 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7381 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7383 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7386 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7387 _.ScalarLdFrag>, TAPD;
7391 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7393 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7395 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7396 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7397 //===----------------------------------------------------------------------===//
7398 // VSHUFPS - VSHUFPD Operations
7399 //===----------------------------------------------------------------------===//
7400 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7401 AVX512VLVectorVTInfo VTInfo_FP>{
7402 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7403 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7404 AVX512AIi8Base, EVEX_4V;
7407 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7408 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7409 //===----------------------------------------------------------------------===//
7410 // AVX-512 - Byte shift Left/Right
7411 //===----------------------------------------------------------------------===//
7413 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7414 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7415 def rr : AVX512<opc, MRMr,
7416 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7417 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7418 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7420 def rm : AVX512<opc, MRMm,
7421 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7422 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7423 [(set _.RC:$dst,(_.VT (OpNode
7424 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7427 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7428 Format MRMm, string OpcodeStr, Predicate prd>{
7429 let Predicates = [prd] in
7430 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7431 OpcodeStr, v8i64_info>, EVEX_V512;
7432 let Predicates = [prd, HasVLX] in {
7433 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7434 OpcodeStr, v4i64x_info>, EVEX_V256;
7435 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7436 OpcodeStr, v2i64x_info>, EVEX_V128;
7439 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7440 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7441 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7442 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7445 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7446 string OpcodeStr, X86VectorVTInfo _dst,
7447 X86VectorVTInfo _src>{
7448 def rr : AVX512BI<opc, MRMSrcReg,
7449 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7450 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7451 [(set _dst.RC:$dst,(_dst.VT
7452 (OpNode (_src.VT _src.RC:$src1),
7453 (_src.VT _src.RC:$src2))))]>;
7455 def rm : AVX512BI<opc, MRMSrcMem,
7456 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7457 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7458 [(set _dst.RC:$dst,(_dst.VT
7459 (OpNode (_src.VT _src.RC:$src1),
7460 (_src.VT (bitconvert
7461 (_src.LdFrag addr:$src2))))))]>;
7464 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7465 string OpcodeStr, Predicate prd> {
7466 let Predicates = [prd] in
7467 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v8i64_info,
7468 v64i8_info>, EVEX_V512;
7469 let Predicates = [prd, HasVLX] in {
7470 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v4i64x_info,
7471 v32i8x_info>, EVEX_V256;
7472 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v2i64x_info,
7473 v16i8x_info>, EVEX_V128;
7477 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7480 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7482 let Constraints = "$src1 = $dst" in {
7483 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7484 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7485 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7486 (OpNode (_.VT _.RC:$src1),
7489 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7490 let mayLoad = 1 in {
7491 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7492 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7493 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7494 (OpNode (_.VT _.RC:$src1),
7496 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7498 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7499 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7500 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7501 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7502 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7503 (OpNode (_.VT _.RC:$src1),
7505 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7506 (i8 imm:$src4))>, EVEX_B,
7507 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7509 }// Constraints = "$src1 = $dst"
7512 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7513 let Predicates = [HasAVX512] in
7514 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7515 let Predicates = [HasAVX512, HasVLX] in {
7516 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7517 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7521 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7522 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;