1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
77 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
79 // The corresponding float type, e.g. v16f32 for v16i32
80 // Note: For EltSize < 32, FloatVT is illegal and TableGen
81 // fails to compile, so we choose FloatVT = VT
82 ValueType FloatVT = !cast<ValueType>(
83 !if (!eq (!srl(EltSize,5),0),
85 !if (!eq(TypeVariantName, "i"),
86 "v" # NumElts # "f" # EltSize,
89 // The string to specify embedded broadcast in assembly.
90 string BroadcastStr = "{1to" # NumElts # "}";
92 // 8-bit compressed displacement tuple/subvector format. This is only
93 // defined for NumElts <= 8.
94 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
95 !cast<CD8VForm>("CD8VT" # NumElts), ?);
97 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
98 !if (!eq (Size, 256), sub_ymm, ?));
100 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
101 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
104 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
106 // A vector type of the same width with element type i32. This is used to
107 // create the canonical constant zero node ImmAllZerosV.
108 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
109 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
112 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
113 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
114 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
115 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
116 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
117 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
119 // "x" in v32i8x_info means RC = VR256X
120 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
121 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
122 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
123 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
124 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
125 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
127 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
128 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
129 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
130 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
131 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
132 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
134 // We map scalar types to the smallest (128-bit) vector type
135 // with the appropriate element type. This allows to use the same masking logic.
136 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
137 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
139 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
140 X86VectorVTInfo i128> {
141 X86VectorVTInfo info512 = i512;
142 X86VectorVTInfo info256 = i256;
143 X86VectorVTInfo info128 = i128;
146 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
148 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
150 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
152 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
154 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
156 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
159 // This multiclass generates the masking variants from the non-masking
160 // variant. It only provides the assembly pieces for the masking variants.
161 // It assumes custom ISel patterns for masking which can be provided as
162 // template arguments.
163 multiclass AVX512_maskable_custom<bits<8> O, Format F,
165 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
167 string AttSrcAsm, string IntelSrcAsm,
169 list<dag> MaskingPattern,
170 list<dag> ZeroMaskingPattern,
172 string MaskingConstraint = "",
173 InstrItinClass itin = NoItinerary,
174 bit IsCommutable = 0> {
175 let isCommutable = IsCommutable in
176 def NAME: AVX512<O, F, Outs, Ins,
177 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
178 "$dst "#Round#", "#IntelSrcAsm#"}",
181 // Prefer over VMOV*rrk Pat<>
182 let AddedComplexity = 20 in
183 def NAME#k: AVX512<O, F, Outs, MaskingIns,
184 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
185 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
186 MaskingPattern, itin>,
188 // In case of the 3src subclass this is overridden with a let.
189 string Constraints = MaskingConstraint;
191 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
192 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
193 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
194 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
201 // Common base class of AVX512_maskable and AVX512_maskable_3src.
202 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
204 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
206 string AttSrcAsm, string IntelSrcAsm,
207 dag RHS, dag MaskingRHS,
208 SDNode Select = vselect, string Round = "",
209 string MaskingConstraint = "",
210 InstrItinClass itin = NoItinerary,
211 bit IsCommutable = 0> :
212 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
213 AttSrcAsm, IntelSrcAsm,
214 [(set _.RC:$dst, RHS)],
215 [(set _.RC:$dst, MaskingRHS)],
217 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
218 Round, MaskingConstraint, NoItinerary, IsCommutable>;
220 // This multiclass generates the unconditional/non-masking, the masking and
221 // the zero-masking variant of the vector instruction. In the masking case, the
222 // perserved vector elements come from a new dummy input operand tied to $dst.
223 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
224 dag Outs, dag Ins, string OpcodeStr,
225 string AttSrcAsm, string IntelSrcAsm,
226 dag RHS, string Round = "",
227 InstrItinClass itin = NoItinerary,
228 bit IsCommutable = 0> :
229 AVX512_maskable_common<O, F, _, Outs, Ins,
230 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
231 !con((ins _.KRCWM:$mask), Ins),
232 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
233 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
234 Round, "$src0 = $dst", itin, IsCommutable>;
236 // This multiclass generates the unconditional/non-masking, the masking and
237 // the zero-masking variant of the scalar instruction.
238 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
239 dag Outs, dag Ins, string OpcodeStr,
240 string AttSrcAsm, string IntelSrcAsm,
241 dag RHS, string Round = "",
242 InstrItinClass itin = NoItinerary,
243 bit IsCommutable = 0> :
244 AVX512_maskable_common<O, F, _, Outs, Ins,
245 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
246 !con((ins _.KRCWM:$mask), Ins),
247 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
248 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
249 Round, "$src0 = $dst", itin, IsCommutable>;
251 // Similar to AVX512_maskable but in this case one of the source operands
252 // ($src1) is already tied to $dst so we just use that for the preserved
253 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
255 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
256 dag Outs, dag NonTiedIns, string OpcodeStr,
257 string AttSrcAsm, string IntelSrcAsm,
259 AVX512_maskable_common<O, F, _, Outs,
260 !con((ins _.RC:$src1), NonTiedIns),
261 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
262 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
263 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
264 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
267 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_custom<O, F, Outs, Ins,
273 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
274 !con((ins _.KRCWM:$mask), Ins),
275 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
278 // Bitcasts between 512-bit vector types. Return the original type since
279 // no instruction is needed for the conversion
280 let Predicates = [HasAVX512] in {
281 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
282 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
283 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
284 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
285 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
286 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
287 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
288 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
289 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
290 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
291 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
292 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
293 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
294 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
295 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
296 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
297 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
298 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
299 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
300 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
301 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
302 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
303 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
304 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
305 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
306 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
307 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
308 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
309 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
310 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
311 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
313 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
314 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
315 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
316 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
317 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
318 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
319 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
320 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
321 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
322 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
323 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
324 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
325 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
326 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
327 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
328 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
329 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
330 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
331 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
332 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
333 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
334 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
335 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
336 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
337 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
338 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
339 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
340 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
341 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
342 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
344 // Bitcasts between 256-bit vector types. Return the original type since
345 // no instruction is needed for the conversion
346 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
347 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
348 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
349 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
350 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
351 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
352 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
353 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
354 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
355 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
356 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
357 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
358 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
359 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
360 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
361 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
362 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
363 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
364 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
365 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
366 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
367 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
368 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
369 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
370 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
371 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
372 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
373 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
374 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
375 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
379 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
382 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
383 isPseudo = 1, Predicates = [HasAVX512] in {
384 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
385 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
388 let Predicates = [HasAVX512] in {
389 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
390 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
391 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
394 //===----------------------------------------------------------------------===//
395 // AVX-512 - VECTOR INSERT
398 multiclass vinsert_for_size_no_alt<int Opcode,
399 X86VectorVTInfo From, X86VectorVTInfo To,
400 PatFrag vinsert_insert,
401 SDNodeXForm INSERT_get_vinsert_imm> {
402 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
403 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
404 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
405 "vinsert" # From.EltTypeName # "x" # From.NumElts #
406 "\t{$src3, $src2, $src1, $dst|"
407 "$dst, $src1, $src2, $src3}",
408 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
409 (From.VT From.RC:$src2),
414 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
415 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
416 "vinsert" # From.EltTypeName # "x" # From.NumElts #
417 "\t{$src3, $src2, $src1, $dst|"
418 "$dst, $src1, $src2, $src3}",
420 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
424 multiclass vinsert_for_size<int Opcode,
425 X86VectorVTInfo From, X86VectorVTInfo To,
426 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
427 PatFrag vinsert_insert,
428 SDNodeXForm INSERT_get_vinsert_imm> :
429 vinsert_for_size_no_alt<Opcode, From, To,
430 vinsert_insert, INSERT_get_vinsert_imm> {
431 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
432 // vinserti32x4. Only add this if 64x2 and friends are not supported
433 // natively via AVX512DQ.
434 let Predicates = [NoDQI] in
435 def : Pat<(vinsert_insert:$ins
436 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
437 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
438 VR512:$src1, From.RC:$src2,
439 (INSERT_get_vinsert_imm VR512:$ins)))>;
442 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
443 ValueType EltVT64, int Opcode256> {
444 defm NAME # "32x4" : vinsert_for_size<Opcode128,
445 X86VectorVTInfo< 4, EltVT32, VR128X>,
446 X86VectorVTInfo<16, EltVT32, VR512>,
447 X86VectorVTInfo< 2, EltVT64, VR128X>,
448 X86VectorVTInfo< 8, EltVT64, VR512>,
450 INSERT_get_vinsert128_imm>;
451 let Predicates = [HasDQI] in
452 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
453 X86VectorVTInfo< 2, EltVT64, VR128X>,
454 X86VectorVTInfo< 8, EltVT64, VR512>,
456 INSERT_get_vinsert128_imm>, VEX_W;
457 defm NAME # "64x4" : vinsert_for_size<Opcode256,
458 X86VectorVTInfo< 4, EltVT64, VR256X>,
459 X86VectorVTInfo< 8, EltVT64, VR512>,
460 X86VectorVTInfo< 8, EltVT32, VR256>,
461 X86VectorVTInfo<16, EltVT32, VR512>,
463 INSERT_get_vinsert256_imm>, VEX_W;
464 let Predicates = [HasDQI] in
465 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
466 X86VectorVTInfo< 8, EltVT32, VR256X>,
467 X86VectorVTInfo<16, EltVT32, VR512>,
469 INSERT_get_vinsert256_imm>;
472 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
473 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
475 // vinsertps - insert f32 to XMM
476 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
477 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
478 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
479 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
481 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
482 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
483 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
484 [(set VR128X:$dst, (X86insertps VR128X:$src1,
485 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
486 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
488 //===----------------------------------------------------------------------===//
489 // AVX-512 VECTOR EXTRACT
492 multiclass vextract_for_size<int Opcode,
493 X86VectorVTInfo From, X86VectorVTInfo To,
494 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
495 PatFrag vextract_extract,
496 SDNodeXForm EXTRACT_get_vextract_imm> {
497 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
498 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
499 (ins VR512:$src1, u8imm:$idx),
500 "vextract" # To.EltTypeName # "x4",
501 "$idx, $src1", "$src1, $idx",
502 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
504 AVX512AIi8Base, EVEX, EVEX_V512;
506 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
507 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
508 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
509 "$dst, $src1, $src2}",
510 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
513 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
515 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
516 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
518 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
520 // A 128/256-bit subvector extract from the first 512-bit vector position is
521 // a subregister copy that needs no instruction.
522 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
524 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
526 // And for the alternative types.
527 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
529 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
531 // Intrinsic call with masking.
532 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
534 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
535 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
536 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
537 VR512:$src1, imm:$idx)>;
539 // Intrinsic call with zero-masking.
540 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
542 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
543 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
544 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
545 VR512:$src1, imm:$idx)>;
547 // Intrinsic call without masking.
548 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
550 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
551 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
552 VR512:$src1, imm:$idx)>;
555 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
556 ValueType EltVT64, int Opcode64> {
557 defm NAME # "32x4" : vextract_for_size<Opcode32,
558 X86VectorVTInfo<16, EltVT32, VR512>,
559 X86VectorVTInfo< 4, EltVT32, VR128X>,
560 X86VectorVTInfo< 8, EltVT64, VR512>,
561 X86VectorVTInfo< 2, EltVT64, VR128X>,
563 EXTRACT_get_vextract128_imm>;
564 defm NAME # "64x4" : vextract_for_size<Opcode64,
565 X86VectorVTInfo< 8, EltVT64, VR512>,
566 X86VectorVTInfo< 4, EltVT64, VR256X>,
567 X86VectorVTInfo<16, EltVT32, VR512>,
568 X86VectorVTInfo< 8, EltVT32, VR256>,
570 EXTRACT_get_vextract256_imm>, VEX_W;
573 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
574 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
576 // A 128-bit subvector insert to the first 512-bit vector position
577 // is a subregister copy that needs no instruction.
578 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
579 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
580 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
582 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
583 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
584 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
586 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
587 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
588 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
590 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
591 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
592 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
595 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
596 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
597 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
598 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
599 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
600 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
601 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
602 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
604 // vextractps - extract 32 bits from XMM
605 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
606 (ins VR128X:$src1, u8imm:$src2),
607 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
608 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
611 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
612 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
613 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
614 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
615 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
617 //===---------------------------------------------------------------------===//
620 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
621 ValueType svt, X86VectorVTInfo _> {
622 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
623 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
624 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
628 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
629 (ins _.ScalarMemOp:$src),
630 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
631 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
636 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
637 AVX512VLVectorVTInfo _> {
638 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
641 let Predicates = [HasVLX] in {
642 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
647 let ExeDomain = SSEPackedSingle in {
648 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
649 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
650 let Predicates = [HasVLX] in {
651 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
652 v4f32, v4f32x_info>, EVEX_V128,
653 EVEX_CD8<32, CD8VT1>;
657 let ExeDomain = SSEPackedDouble in {
658 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
659 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
662 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
663 // Later, we can canonize broadcast instructions before ISel phase and
664 // eliminate additional patterns on ISel.
665 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
666 // representations of source
667 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
668 X86VectorVTInfo _, RegisterClass SrcRC_v,
669 RegisterClass SrcRC_s> {
670 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
671 (!cast<Instruction>(InstName##"r")
672 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
674 let AddedComplexity = 30 in {
675 def : Pat<(_.VT (vselect _.KRCWM:$mask,
676 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
677 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
678 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
680 def : Pat<(_.VT(vselect _.KRCWM:$mask,
681 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
682 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
683 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
687 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
689 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
692 let Predicates = [HasVLX] in {
693 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
694 v8f32x_info, VR128X, FR32X>;
695 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
696 v4f32x_info, VR128X, FR32X>;
697 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
698 v4f64x_info, VR128X, FR64X>;
701 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
702 (VBROADCASTSSZm addr:$src)>;
703 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
704 (VBROADCASTSDZm addr:$src)>;
706 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
707 (VBROADCASTSSZm addr:$src)>;
708 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
709 (VBROADCASTSDZm addr:$src)>;
711 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
712 RegisterClass SrcRC> {
713 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
714 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
715 "$src", "$src", []>, T8PD, EVEX;
718 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
719 RegisterClass SrcRC, Predicate prd> {
720 let Predicates = [prd] in
721 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
722 let Predicates = [prd, HasVLX] in {
723 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
724 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
728 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
730 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
732 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
734 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
737 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
738 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
740 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
741 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
743 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
744 (VPBROADCASTDrZr GR32:$src)>;
745 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
746 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
747 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
748 (VPBROADCASTQrZr GR64:$src)>;
749 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
750 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
752 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
753 (VPBROADCASTDrZr GR32:$src)>;
754 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
755 (VPBROADCASTQrZr GR64:$src)>;
757 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
758 (v16i32 immAllZerosV), (i16 GR16:$mask))),
759 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
760 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
761 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
762 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
764 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
765 X86MemOperand x86memop, PatFrag ld_frag,
766 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
768 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
769 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
771 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
772 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
774 !strconcat(OpcodeStr,
775 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
777 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
780 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
783 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
784 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
786 !strconcat(OpcodeStr,
787 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
788 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
789 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
793 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
794 loadi32, VR512, v16i32, v4i32, VK16WM>,
795 EVEX_V512, EVEX_CD8<32, CD8VT1>;
796 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
797 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
798 EVEX_CD8<64, CD8VT1>;
800 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
801 X86MemOperand x86memop, PatFrag ld_frag,
804 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
805 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
807 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
809 !strconcat(OpcodeStr,
810 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
815 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
816 i128mem, loadv2i64, VK16WM>,
817 EVEX_V512, EVEX_CD8<32, CD8VT4>;
818 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
819 i256mem, loadv4i64, VK16WM>, VEX_W,
820 EVEX_V512, EVEX_CD8<64, CD8VT4>;
822 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
823 (VPBROADCASTDZrr VR128X:$src)>;
824 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
825 (VPBROADCASTQZrr VR128X:$src)>;
827 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
828 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
829 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
830 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
832 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
833 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
834 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
835 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
837 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
838 (VBROADCASTSSZr VR128X:$src)>;
839 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
840 (VBROADCASTSDZr VR128X:$src)>;
842 // Provide fallback in case the load node that is used in the patterns above
843 // is used by additional users, which prevents the pattern selection.
844 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
845 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
846 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
847 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
850 let Predicates = [HasAVX512] in {
851 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
853 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
854 addr:$src)), sub_ymm)>;
856 //===----------------------------------------------------------------------===//
857 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
860 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
862 let Predicates = [HasCDI] in
863 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
864 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
865 []>, EVEX, EVEX_V512;
867 let Predicates = [HasCDI, HasVLX] in {
868 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
869 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
870 []>, EVEX, EVEX_V128;
871 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
872 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
873 []>, EVEX, EVEX_V256;
877 let Predicates = [HasCDI] in {
878 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
880 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
884 //===----------------------------------------------------------------------===//
887 // -- immediate form --
888 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
890 let ExeDomain = _.ExeDomain in {
891 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
892 (ins _.RC:$src1, u8imm:$src2),
893 !strconcat(OpcodeStr,
894 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
896 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
898 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
899 (ins _.MemOp:$src1, u8imm:$src2),
900 !strconcat(OpcodeStr,
901 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
903 (_.VT (OpNode (_.LdFrag addr:$src1),
905 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
909 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
910 X86VectorVTInfo Ctrl> :
911 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
912 let ExeDomain = _.ExeDomain in {
913 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
914 (ins _.RC:$src1, _.RC:$src2),
915 !strconcat("vpermil" # _.Suffix,
916 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
918 (_.VT (X86VPermilpv _.RC:$src1,
919 (Ctrl.VT Ctrl.RC:$src2))))]>,
921 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
922 (ins _.RC:$src1, Ctrl.MemOp:$src2),
923 !strconcat("vpermil" # _.Suffix,
924 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
926 (_.VT (X86VPermilpv _.RC:$src1,
927 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
932 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
934 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
937 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
939 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
942 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
943 (VPERMILPSZri VR512:$src1, imm:$imm)>;
944 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
945 (VPERMILPDZri VR512:$src1, imm:$imm)>;
947 // -- VPERM - register form --
948 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
949 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
951 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
952 (ins RC:$src1, RC:$src2),
953 !strconcat(OpcodeStr,
954 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
956 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
958 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
959 (ins RC:$src1, x86memop:$src2),
960 !strconcat(OpcodeStr,
961 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
963 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
967 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, loadv16i32, i512mem,
968 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
969 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, loadv8i64, i512mem,
970 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
971 let ExeDomain = SSEPackedSingle in
972 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, loadv16f32, f512mem,
973 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
974 let ExeDomain = SSEPackedDouble in
975 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, loadv8f64, f512mem,
976 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
978 // -- VPERM2I - 3 source operands form --
979 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
980 PatFrag mem_frag, X86MemOperand x86memop,
981 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
982 let Constraints = "$src1 = $dst" in {
983 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
984 (ins RC:$src1, RC:$src2, RC:$src3),
985 !strconcat(OpcodeStr,
986 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
988 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
991 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
992 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
993 !strconcat(OpcodeStr,
994 "\t{$src3, $src2, $dst {${mask}}|"
995 "$dst {${mask}}, $src2, $src3}"),
996 [(set RC:$dst, (OpVT (vselect KRC:$mask,
997 (OpNode RC:$src1, RC:$src2,
1002 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
1003 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1004 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1005 !strconcat(OpcodeStr,
1006 "\t{$src3, $src2, $dst {${mask}} {z} |",
1007 "$dst {${mask}} {z}, $src2, $src3}"),
1008 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1009 (OpNode RC:$src1, RC:$src2,
1012 (v16i32 immAllZerosV))))))]>,
1015 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1016 (ins RC:$src1, RC:$src2, x86memop:$src3),
1017 !strconcat(OpcodeStr,
1018 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1020 (OpVT (OpNode RC:$src1, RC:$src2,
1021 (mem_frag addr:$src3))))]>, EVEX_4V;
1023 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1024 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1025 !strconcat(OpcodeStr,
1026 "\t{$src3, $src2, $dst {${mask}}|"
1027 "$dst {${mask}}, $src2, $src3}"),
1029 (OpVT (vselect KRC:$mask,
1030 (OpNode RC:$src1, RC:$src2,
1031 (mem_frag addr:$src3)),
1035 let AddedComplexity = 10 in // Prefer over the rrkz variant
1036 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1037 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1038 !strconcat(OpcodeStr,
1039 "\t{$src3, $src2, $dst {${mask}} {z}|"
1040 "$dst {${mask}} {z}, $src2, $src3}"),
1042 (OpVT (vselect KRC:$mask,
1043 (OpNode RC:$src1, RC:$src2,
1044 (mem_frag addr:$src3)),
1046 (v16i32 immAllZerosV))))))]>,
1050 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
1051 i512mem, X86VPermiv3, v16i32, VK16WM>,
1052 EVEX_V512, EVEX_CD8<32, CD8VF>;
1053 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
1054 i512mem, X86VPermiv3, v8i64, VK8WM>,
1055 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1056 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
1057 i512mem, X86VPermiv3, v16f32, VK16WM>,
1058 EVEX_V512, EVEX_CD8<32, CD8VF>;
1059 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
1060 i512mem, X86VPermiv3, v8f64, VK8WM>,
1061 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1063 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1064 PatFrag mem_frag, X86MemOperand x86memop,
1065 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1066 ValueType MaskVT, RegisterClass MRC> :
1067 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1069 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1070 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1071 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1073 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1074 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1075 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1076 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1079 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
1080 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1081 EVEX_V512, EVEX_CD8<32, CD8VF>;
1082 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
1083 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1084 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1085 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
1086 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1087 EVEX_V512, EVEX_CD8<32, CD8VF>;
1088 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
1089 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1090 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1092 //===----------------------------------------------------------------------===//
1093 // AVX-512 - BLEND using mask
1095 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1096 let ExeDomain = _.ExeDomain in {
1097 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1098 (ins _.RC:$src1, _.RC:$src2),
1099 !strconcat(OpcodeStr,
1100 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1102 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1103 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1104 !strconcat(OpcodeStr,
1105 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1106 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1107 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1108 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1109 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1110 !strconcat(OpcodeStr,
1111 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1112 []>, EVEX_4V, EVEX_KZ;
1113 let mayLoad = 1 in {
1114 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1115 (ins _.RC:$src1, _.MemOp:$src2),
1116 !strconcat(OpcodeStr,
1117 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1118 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1119 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1120 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1121 !strconcat(OpcodeStr,
1122 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1123 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1124 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1125 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1126 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1127 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1128 !strconcat(OpcodeStr,
1129 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1130 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1134 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1136 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1137 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1138 !strconcat(OpcodeStr,
1139 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1140 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1141 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1142 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1143 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1145 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1146 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1147 !strconcat(OpcodeStr,
1148 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1149 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1150 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1154 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1155 AVX512VLVectorVTInfo VTInfo> {
1156 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1157 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1159 let Predicates = [HasVLX] in {
1160 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1161 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1162 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1163 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1167 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1168 AVX512VLVectorVTInfo VTInfo> {
1169 let Predicates = [HasBWI] in
1170 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1172 let Predicates = [HasBWI, HasVLX] in {
1173 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1174 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1179 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1180 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1181 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1182 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1183 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1184 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1187 let Predicates = [HasAVX512] in {
1188 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1189 (v8f32 VR256X:$src2))),
1191 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1192 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1193 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1195 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1196 (v8i32 VR256X:$src2))),
1198 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1199 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1200 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1202 //===----------------------------------------------------------------------===//
1203 // Compare Instructions
1204 //===----------------------------------------------------------------------===//
1206 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1207 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1208 SDNode OpNode, ValueType VT,
1209 PatFrag ld_frag, string Suffix> {
1210 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1211 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1212 !strconcat("vcmp${cc}", Suffix,
1213 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1214 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1215 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1216 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1217 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1218 !strconcat("vcmp${cc}", Suffix,
1219 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1220 [(set VK1:$dst, (OpNode (VT RC:$src1),
1221 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1222 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1223 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1224 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1225 !strconcat("vcmp", Suffix,
1226 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1227 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1229 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1230 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1231 !strconcat("vcmp", Suffix,
1232 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1233 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1237 let Predicates = [HasAVX512] in {
1238 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1240 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1244 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1245 X86VectorVTInfo _> {
1246 def rr : AVX512BI<opc, MRMSrcReg,
1247 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1249 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1250 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1252 def rm : AVX512BI<opc, MRMSrcMem,
1253 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1254 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1255 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1256 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1257 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1258 def rrk : AVX512BI<opc, MRMSrcReg,
1259 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1260 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1261 "$dst {${mask}}, $src1, $src2}"),
1262 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1263 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1264 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1266 def rmk : AVX512BI<opc, MRMSrcMem,
1267 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1269 "$dst {${mask}}, $src1, $src2}"),
1270 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1271 (OpNode (_.VT _.RC:$src1),
1273 (_.LdFrag addr:$src2))))))],
1274 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1277 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1278 X86VectorVTInfo _> :
1279 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1280 let mayLoad = 1 in {
1281 def rmb : AVX512BI<opc, MRMSrcMem,
1282 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1283 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1284 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1285 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1286 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1287 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1288 def rmbk : AVX512BI<opc, MRMSrcMem,
1289 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1290 _.ScalarMemOp:$src2),
1291 !strconcat(OpcodeStr,
1292 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1293 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1294 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1295 (OpNode (_.VT _.RC:$src1),
1297 (_.ScalarLdFrag addr:$src2)))))],
1298 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1302 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1303 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1304 let Predicates = [prd] in
1305 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1308 let Predicates = [prd, HasVLX] in {
1309 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1311 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1316 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1317 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1319 let Predicates = [prd] in
1320 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1323 let Predicates = [prd, HasVLX] in {
1324 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1326 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1331 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1332 avx512vl_i8_info, HasBWI>,
1335 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1336 avx512vl_i16_info, HasBWI>,
1337 EVEX_CD8<16, CD8VF>;
1339 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1340 avx512vl_i32_info, HasAVX512>,
1341 EVEX_CD8<32, CD8VF>;
1343 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1344 avx512vl_i64_info, HasAVX512>,
1345 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1347 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1348 avx512vl_i8_info, HasBWI>,
1351 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1352 avx512vl_i16_info, HasBWI>,
1353 EVEX_CD8<16, CD8VF>;
1355 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1356 avx512vl_i32_info, HasAVX512>,
1357 EVEX_CD8<32, CD8VF>;
1359 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1360 avx512vl_i64_info, HasAVX512>,
1361 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1363 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1364 (COPY_TO_REGCLASS (VPCMPGTDZrr
1365 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1366 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1368 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1369 (COPY_TO_REGCLASS (VPCMPEQDZrr
1370 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1371 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1373 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1374 X86VectorVTInfo _> {
1375 def rri : AVX512AIi8<opc, MRMSrcReg,
1376 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1377 !strconcat("vpcmp${cc}", Suffix,
1378 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1379 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1381 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1383 def rmi : AVX512AIi8<opc, MRMSrcMem,
1384 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1385 !strconcat("vpcmp${cc}", Suffix,
1386 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1387 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1388 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1390 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1391 def rrik : AVX512AIi8<opc, MRMSrcReg,
1392 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1394 !strconcat("vpcmp${cc}", Suffix,
1395 "\t{$src2, $src1, $dst {${mask}}|",
1396 "$dst {${mask}}, $src1, $src2}"),
1397 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1398 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1400 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1402 def rmik : AVX512AIi8<opc, MRMSrcMem,
1403 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1405 !strconcat("vpcmp${cc}", Suffix,
1406 "\t{$src2, $src1, $dst {${mask}}|",
1407 "$dst {${mask}}, $src1, $src2}"),
1408 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1409 (OpNode (_.VT _.RC:$src1),
1410 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1412 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1414 // Accept explicit immediate argument form instead of comparison code.
1415 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1416 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1417 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1418 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1419 "$dst, $src1, $src2, $cc}"),
1420 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1422 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1423 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1424 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1425 "$dst, $src1, $src2, $cc}"),
1426 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1427 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1428 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1430 !strconcat("vpcmp", Suffix,
1431 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1432 "$dst {${mask}}, $src1, $src2, $cc}"),
1433 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1435 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1436 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1438 !strconcat("vpcmp", Suffix,
1439 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1440 "$dst {${mask}}, $src1, $src2, $cc}"),
1441 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1445 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1446 X86VectorVTInfo _> :
1447 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1448 def rmib : AVX512AIi8<opc, MRMSrcMem,
1449 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1451 !strconcat("vpcmp${cc}", Suffix,
1452 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1453 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1454 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1455 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1457 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1458 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1459 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1460 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1461 !strconcat("vpcmp${cc}", Suffix,
1462 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1463 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1464 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1465 (OpNode (_.VT _.RC:$src1),
1466 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1468 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1470 // Accept explicit immediate argument form instead of comparison code.
1471 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1472 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1473 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1475 !strconcat("vpcmp", Suffix,
1476 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1477 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1478 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1479 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1480 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1481 _.ScalarMemOp:$src2, u8imm:$cc),
1482 !strconcat("vpcmp", Suffix,
1483 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1484 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1485 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1489 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1490 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1491 let Predicates = [prd] in
1492 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1494 let Predicates = [prd, HasVLX] in {
1495 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1496 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1500 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1501 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1502 let Predicates = [prd] in
1503 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1506 let Predicates = [prd, HasVLX] in {
1507 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1509 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1514 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1515 HasBWI>, EVEX_CD8<8, CD8VF>;
1516 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1517 HasBWI>, EVEX_CD8<8, CD8VF>;
1519 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1520 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1521 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1522 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1524 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1525 HasAVX512>, EVEX_CD8<32, CD8VF>;
1526 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1527 HasAVX512>, EVEX_CD8<32, CD8VF>;
1529 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1530 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1531 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1532 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1534 // avx512_cmp_packed - compare packed instructions
1535 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1536 X86MemOperand x86memop, ValueType vt,
1537 string suffix, Domain d> {
1538 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1539 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1540 !strconcat("vcmp${cc}", suffix,
1541 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1542 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1543 let hasSideEffects = 0 in
1544 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1545 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1546 !strconcat("vcmp${cc}", suffix,
1547 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1549 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1550 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1551 !strconcat("vcmp${cc}", suffix,
1552 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1554 (X86cmpm (vt RC:$src1), (load addr:$src2), imm:$cc))], d>;
1556 // Accept explicit immediate argument form instead of comparison code.
1557 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1558 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1559 (outs KRC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1560 !strconcat("vcmp", suffix,
1561 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1563 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1564 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1565 !strconcat("vcmp", suffix,
1566 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1570 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1571 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1572 EVEX_CD8<32, CD8VF>;
1573 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1574 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1575 EVEX_CD8<64, CD8VF>;
1577 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1578 (COPY_TO_REGCLASS (VCMPPSZrri
1579 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1580 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1582 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1583 (COPY_TO_REGCLASS (VPCMPDZrri
1584 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1585 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1587 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1588 (COPY_TO_REGCLASS (VPCMPUDZrri
1589 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1590 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1593 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1594 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1596 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1597 (I8Imm imm:$cc)), GR16)>;
1599 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1600 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1602 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1603 (I8Imm imm:$cc)), GR8)>;
1605 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1606 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1608 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1609 (I8Imm imm:$cc)), GR16)>;
1611 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1612 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1614 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1615 (I8Imm imm:$cc)), GR8)>;
1617 // Mask register copy, including
1618 // - copy between mask registers
1619 // - load/store mask registers
1620 // - copy from GPR to mask register and vice versa
1622 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1623 string OpcodeStr, RegisterClass KRC,
1624 ValueType vvt, X86MemOperand x86memop> {
1625 let hasSideEffects = 0 in {
1626 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1627 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1629 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1630 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1631 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1633 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1634 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1635 [(store KRC:$src, addr:$dst)]>;
1639 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1641 RegisterClass KRC, RegisterClass GRC> {
1642 let hasSideEffects = 0 in {
1643 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1644 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1645 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1646 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1650 let Predicates = [HasDQI] in
1651 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1652 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1655 let Predicates = [HasAVX512] in
1656 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1657 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1660 let Predicates = [HasBWI] in {
1661 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1663 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1667 let Predicates = [HasBWI] in {
1668 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1670 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1674 // GR from/to mask register
1675 let Predicates = [HasDQI] in {
1676 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1677 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1678 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1679 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1681 let Predicates = [HasAVX512] in {
1682 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1683 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1684 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1685 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1687 let Predicates = [HasBWI] in {
1688 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1689 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1691 let Predicates = [HasBWI] in {
1692 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1693 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1697 let Predicates = [HasDQI] in {
1698 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1699 (KMOVBmk addr:$dst, VK8:$src)>;
1700 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1701 (KMOVBkm addr:$src)>;
1703 let Predicates = [HasAVX512, NoDQI] in {
1704 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1705 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1706 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1707 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1709 let Predicates = [HasAVX512] in {
1710 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1711 (KMOVWmk addr:$dst, VK16:$src)>;
1712 def : Pat<(i1 (load addr:$src)),
1713 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1714 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1715 (KMOVWkm addr:$src)>;
1717 let Predicates = [HasBWI] in {
1718 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1719 (KMOVDmk addr:$dst, VK32:$src)>;
1720 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1721 (KMOVDkm addr:$src)>;
1723 let Predicates = [HasBWI] in {
1724 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1725 (KMOVQmk addr:$dst, VK64:$src)>;
1726 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1727 (KMOVQkm addr:$src)>;
1730 let Predicates = [HasAVX512] in {
1731 def : Pat<(i1 (trunc (i64 GR64:$src))),
1732 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1735 def : Pat<(i1 (trunc (i32 GR32:$src))),
1736 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1738 def : Pat<(i1 (trunc (i8 GR8:$src))),
1740 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1742 def : Pat<(i1 (trunc (i16 GR16:$src))),
1744 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1747 def : Pat<(i32 (zext VK1:$src)),
1748 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1749 def : Pat<(i8 (zext VK1:$src)),
1752 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1753 def : Pat<(i64 (zext VK1:$src)),
1754 (AND64ri8 (SUBREG_TO_REG (i64 0),
1755 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1756 def : Pat<(i16 (zext VK1:$src)),
1758 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1760 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1761 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1762 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1763 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1765 let Predicates = [HasBWI] in {
1766 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1767 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1768 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1769 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1773 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1774 let Predicates = [HasAVX512] in {
1775 // GR from/to 8-bit mask without native support
1776 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1778 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1780 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1782 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1785 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1786 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1787 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1788 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1790 let Predicates = [HasBWI] in {
1791 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1792 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1793 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1794 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1797 // Mask unary operation
1799 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1800 RegisterClass KRC, SDPatternOperator OpNode,
1802 let Predicates = [prd] in
1803 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1804 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1805 [(set KRC:$dst, (OpNode KRC:$src))]>;
1808 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1809 SDPatternOperator OpNode> {
1810 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1812 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1813 HasAVX512>, VEX, PS;
1814 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1815 HasBWI>, VEX, PD, VEX_W;
1816 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1817 HasBWI>, VEX, PS, VEX_W;
1820 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1822 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1823 let Predicates = [HasAVX512] in
1824 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1826 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1827 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1829 defm : avx512_mask_unop_int<"knot", "KNOT">;
1831 let Predicates = [HasDQI] in
1832 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1833 let Predicates = [HasAVX512] in
1834 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1835 let Predicates = [HasBWI] in
1836 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1837 let Predicates = [HasBWI] in
1838 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1840 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1841 let Predicates = [HasAVX512, NoDQI] in {
1842 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1843 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1845 def : Pat<(not VK8:$src),
1847 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1850 // Mask binary operation
1851 // - KAND, KANDN, KOR, KXNOR, KXOR
1852 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1853 RegisterClass KRC, SDPatternOperator OpNode,
1855 let Predicates = [prd] in
1856 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1857 !strconcat(OpcodeStr,
1858 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1859 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1862 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1863 SDPatternOperator OpNode> {
1864 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1865 HasDQI>, VEX_4V, VEX_L, PD;
1866 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1867 HasAVX512>, VEX_4V, VEX_L, PS;
1868 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1869 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1870 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1871 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1874 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1875 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1877 let isCommutable = 1 in {
1878 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1879 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1880 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1881 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1883 let isCommutable = 0 in
1884 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1886 def : Pat<(xor VK1:$src1, VK1:$src2),
1887 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1888 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1890 def : Pat<(or VK1:$src1, VK1:$src2),
1891 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1892 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1894 def : Pat<(and VK1:$src1, VK1:$src2),
1895 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1896 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1898 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1899 let Predicates = [HasAVX512] in
1900 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1901 (i16 GR16:$src1), (i16 GR16:$src2)),
1902 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1903 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1904 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1907 defm : avx512_mask_binop_int<"kand", "KAND">;
1908 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1909 defm : avx512_mask_binop_int<"kor", "KOR">;
1910 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1911 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1913 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1914 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1915 let Predicates = [HasAVX512] in
1916 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1918 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1919 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1922 defm : avx512_binop_pat<and, KANDWrr>;
1923 defm : avx512_binop_pat<andn, KANDNWrr>;
1924 defm : avx512_binop_pat<or, KORWrr>;
1925 defm : avx512_binop_pat<xnor, KXNORWrr>;
1926 defm : avx512_binop_pat<xor, KXORWrr>;
1929 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1930 RegisterClass KRC> {
1931 let Predicates = [HasAVX512] in
1932 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1933 !strconcat(OpcodeStr,
1934 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1937 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1938 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1942 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1943 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1944 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1945 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1948 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1949 let Predicates = [HasAVX512] in
1950 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1951 (i16 GR16:$src1), (i16 GR16:$src2)),
1952 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1953 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1954 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1956 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1959 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1961 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1962 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1963 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1964 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1967 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1968 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1970 let Predicates = [HasDQI] in
1971 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
1973 let Predicates = [HasBWI] in {
1974 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
1976 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
1981 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1984 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1986 let Predicates = [HasAVX512] in
1987 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
1988 !strconcat(OpcodeStr,
1989 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1990 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1993 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1995 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1997 let Predicates = [HasDQI] in
1998 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2000 let Predicates = [HasBWI] in {
2001 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2003 let Predicates = [HasDQI] in
2004 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2009 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2010 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2012 // Mask setting all 0s or 1s
2013 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2014 let Predicates = [HasAVX512] in
2015 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2016 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2017 [(set KRC:$dst, (VT Val))]>;
2020 multiclass avx512_mask_setop_w<PatFrag Val> {
2021 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2022 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2025 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2026 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2028 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2029 let Predicates = [HasAVX512] in {
2030 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2031 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2032 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2033 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2034 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2036 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2037 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2039 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2040 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2042 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2043 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2045 let Predicates = [HasVLX] in {
2046 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2047 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2048 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2049 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2050 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2051 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2052 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2053 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2056 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2057 (v8i1 (COPY_TO_REGCLASS
2058 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2059 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2061 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2062 (v8i1 (COPY_TO_REGCLASS
2063 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2064 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2065 //===----------------------------------------------------------------------===//
2066 // AVX-512 - Aligned and unaligned load and store
2069 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
2070 RegisterClass KRC, RegisterClass RC,
2071 ValueType vt, ValueType zvt, X86MemOperand memop,
2072 Domain d, bit IsReMaterializable = 1> {
2073 let hasSideEffects = 0 in {
2074 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2075 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2077 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2078 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2079 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2081 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2082 SchedRW = [WriteLoad] in
2083 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2084 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2085 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2088 let AddedComplexity = 20 in {
2089 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2090 let hasSideEffects = 0 in
2091 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2092 (ins RC:$src0, KRC:$mask, RC:$src1),
2093 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2094 "${dst} {${mask}}, $src1}"),
2095 [(set RC:$dst, (vt (vselect KRC:$mask,
2099 let mayLoad = 1, SchedRW = [WriteLoad] in
2100 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2101 (ins RC:$src0, KRC:$mask, memop:$src1),
2102 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2103 "${dst} {${mask}}, $src1}"),
2106 (vt (bitconvert (ld_frag addr:$src1))),
2110 let mayLoad = 1, SchedRW = [WriteLoad] in
2111 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2112 (ins KRC:$mask, memop:$src),
2113 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2114 "${dst} {${mask}} {z}, $src}"),
2117 (vt (bitconvert (ld_frag addr:$src))),
2118 (vt (bitconvert (zvt immAllZerosV))))))],
2123 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2124 string elty, string elsz, string vsz512,
2125 string vsz256, string vsz128, Domain d,
2126 Predicate prd, bit IsReMaterializable = 1> {
2127 let Predicates = [prd] in
2128 defm Z : avx512_load<opc, OpcodeStr,
2129 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2130 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2131 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2132 !cast<X86MemOperand>(elty##"512mem"), d,
2133 IsReMaterializable>, EVEX_V512;
2135 let Predicates = [prd, HasVLX] in {
2136 defm Z256 : avx512_load<opc, OpcodeStr,
2137 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2138 "v"##vsz256##elty##elsz, "v4i64")),
2139 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2140 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2141 !cast<X86MemOperand>(elty##"256mem"), d,
2142 IsReMaterializable>, EVEX_V256;
2144 defm Z128 : avx512_load<opc, OpcodeStr,
2145 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2146 "v"##vsz128##elty##elsz, "v2i64")),
2147 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2148 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2149 !cast<X86MemOperand>(elty##"128mem"), d,
2150 IsReMaterializable>, EVEX_V128;
2155 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2156 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2157 X86MemOperand memop, Domain d> {
2158 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2159 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2160 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2162 let Constraints = "$src1 = $dst" in
2163 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2164 (ins RC:$src1, KRC:$mask, RC:$src2),
2165 !strconcat(OpcodeStr,
2166 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2168 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2169 (ins KRC:$mask, RC:$src),
2170 !strconcat(OpcodeStr,
2171 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2172 [], d>, EVEX, EVEX_KZ;
2174 let mayStore = 1 in {
2175 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2176 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2177 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2178 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2179 (ins memop:$dst, KRC:$mask, RC:$src),
2180 !strconcat(OpcodeStr,
2181 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2182 [], d>, EVEX, EVEX_K;
2187 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2188 string st_suff_512, string st_suff_256,
2189 string st_suff_128, string elty, string elsz,
2190 string vsz512, string vsz256, string vsz128,
2191 Domain d, Predicate prd> {
2192 let Predicates = [prd] in
2193 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2194 !cast<ValueType>("v"##vsz512##elty##elsz),
2195 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2196 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2198 let Predicates = [prd, HasVLX] in {
2199 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2200 !cast<ValueType>("v"##vsz256##elty##elsz),
2201 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2202 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2204 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2205 !cast<ValueType>("v"##vsz128##elty##elsz),
2206 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2207 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2211 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2212 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2213 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2214 "512", "256", "", "f", "32", "16", "8", "4",
2215 SSEPackedSingle, HasAVX512>,
2216 PS, EVEX_CD8<32, CD8VF>;
2218 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2219 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2220 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2221 "512", "256", "", "f", "64", "8", "4", "2",
2222 SSEPackedDouble, HasAVX512>,
2223 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2225 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2226 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2227 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2228 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2229 PS, EVEX_CD8<32, CD8VF>;
2231 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2232 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2233 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2234 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2235 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2237 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2238 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2239 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2241 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2242 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2243 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2245 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2246 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2247 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2249 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2250 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2251 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2253 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2254 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2255 (VMOVAPDZrm addr:$ptr)>;
2257 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2258 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2259 (VMOVAPSZrm addr:$ptr)>;
2261 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2263 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2265 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2267 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2270 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2272 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2274 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2276 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2279 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2280 (VMOVUPSZmrk addr:$ptr,
2281 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2282 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2284 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2285 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2286 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2288 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2289 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2291 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2292 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2294 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2295 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2297 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2298 (bc_v16f32 (v16i32 immAllZerosV)))),
2299 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2301 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2302 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2304 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2305 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2307 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2308 (bc_v8f64 (v16i32 immAllZerosV)))),
2309 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2311 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2312 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2314 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2315 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2316 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2317 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2319 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2320 "16", "8", "4", SSEPackedInt, HasAVX512>,
2321 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2322 "512", "256", "", "i", "32", "16", "8", "4",
2323 SSEPackedInt, HasAVX512>,
2324 PD, EVEX_CD8<32, CD8VF>;
2326 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2327 "8", "4", "2", SSEPackedInt, HasAVX512>,
2328 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2329 "512", "256", "", "i", "64", "8", "4", "2",
2330 SSEPackedInt, HasAVX512>,
2331 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2333 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2334 "64", "32", "16", SSEPackedInt, HasBWI>,
2335 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2336 "i", "8", "64", "32", "16", SSEPackedInt,
2337 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2339 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2340 "32", "16", "8", SSEPackedInt, HasBWI>,
2341 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2342 "i", "16", "32", "16", "8", SSEPackedInt,
2343 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2345 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2346 "16", "8", "4", SSEPackedInt, HasAVX512>,
2347 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2348 "i", "32", "16", "8", "4", SSEPackedInt,
2349 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2351 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2352 "8", "4", "2", SSEPackedInt, HasAVX512>,
2353 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2354 "i", "64", "8", "4", "2", SSEPackedInt,
2355 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2357 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2358 (v16i32 immAllZerosV), GR16:$mask)),
2359 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2361 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2362 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2363 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2365 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2367 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2369 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2371 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2374 let AddedComplexity = 20 in {
2375 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2376 (bc_v8i64 (v16i32 immAllZerosV)))),
2377 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2379 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2380 (v8i64 VR512:$src))),
2381 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2384 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2385 (v16i32 immAllZerosV))),
2386 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2388 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2389 (v16i32 VR512:$src))),
2390 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2393 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2394 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2396 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2397 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2399 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2400 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2402 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2403 (bc_v8i64 (v16i32 immAllZerosV)))),
2404 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2406 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2407 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2409 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2410 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2412 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2413 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2415 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2416 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2419 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2420 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2423 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2424 (VMOVDQU32Zmrk addr:$ptr,
2425 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2426 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2428 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2429 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2430 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2433 // Move Int Doubleword to Packed Double Int
2435 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2436 "vmovd\t{$src, $dst|$dst, $src}",
2438 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2440 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2441 "vmovd\t{$src, $dst|$dst, $src}",
2443 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2444 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2445 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2446 "vmovq\t{$src, $dst|$dst, $src}",
2448 (v2i64 (scalar_to_vector GR64:$src)))],
2449 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2450 let isCodeGenOnly = 1 in {
2451 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2452 "vmovq\t{$src, $dst|$dst, $src}",
2453 [(set FR64:$dst, (bitconvert GR64:$src))],
2454 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2455 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2456 "vmovq\t{$src, $dst|$dst, $src}",
2457 [(set GR64:$dst, (bitconvert FR64:$src))],
2458 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2460 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2461 "vmovq\t{$src, $dst|$dst, $src}",
2462 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2463 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2464 EVEX_CD8<64, CD8VT1>;
2466 // Move Int Doubleword to Single Scalar
2468 let isCodeGenOnly = 1 in {
2469 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2470 "vmovd\t{$src, $dst|$dst, $src}",
2471 [(set FR32X:$dst, (bitconvert GR32:$src))],
2472 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2474 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2475 "vmovd\t{$src, $dst|$dst, $src}",
2476 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2477 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2480 // Move doubleword from xmm register to r/m32
2482 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2483 "vmovd\t{$src, $dst|$dst, $src}",
2484 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2485 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2487 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2488 (ins i32mem:$dst, VR128X:$src),
2489 "vmovd\t{$src, $dst|$dst, $src}",
2490 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2491 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2492 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2494 // Move quadword from xmm1 register to r/m64
2496 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2497 "vmovq\t{$src, $dst|$dst, $src}",
2498 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2500 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2501 Requires<[HasAVX512, In64BitMode]>;
2503 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2504 (ins i64mem:$dst, VR128X:$src),
2505 "vmovq\t{$src, $dst|$dst, $src}",
2506 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2507 addr:$dst)], IIC_SSE_MOVDQ>,
2508 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2509 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2511 // Move Scalar Single to Double Int
2513 let isCodeGenOnly = 1 in {
2514 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2516 "vmovd\t{$src, $dst|$dst, $src}",
2517 [(set GR32:$dst, (bitconvert FR32X:$src))],
2518 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2519 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2520 (ins i32mem:$dst, FR32X:$src),
2521 "vmovd\t{$src, $dst|$dst, $src}",
2522 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2523 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2526 // Move Quadword Int to Packed Quadword Int
2528 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2530 "vmovq\t{$src, $dst|$dst, $src}",
2532 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2533 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2535 //===----------------------------------------------------------------------===//
2536 // AVX-512 MOVSS, MOVSD
2537 //===----------------------------------------------------------------------===//
2539 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2540 SDNode OpNode, ValueType vt,
2541 X86MemOperand x86memop, PatFrag mem_pat> {
2542 let hasSideEffects = 0 in {
2543 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2544 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2545 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2546 (scalar_to_vector RC:$src2))))],
2547 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2548 let Constraints = "$src1 = $dst" in
2549 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2550 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2552 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2553 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2554 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2555 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2556 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2558 let mayStore = 1 in {
2559 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2560 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2561 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2563 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2564 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2565 [], IIC_SSE_MOV_S_MR>,
2566 EVEX, VEX_LIG, EVEX_K;
2568 } //hasSideEffects = 0
2571 let ExeDomain = SSEPackedSingle in
2572 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2573 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2575 let ExeDomain = SSEPackedDouble in
2576 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2577 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2579 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2580 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2581 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2583 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2584 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2585 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2587 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2588 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2589 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2591 // For the disassembler
2592 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2593 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2594 (ins VR128X:$src1, FR32X:$src2),
2595 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2597 XS, EVEX_4V, VEX_LIG;
2598 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2599 (ins VR128X:$src1, FR64X:$src2),
2600 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2602 XD, EVEX_4V, VEX_LIG, VEX_W;
2605 let Predicates = [HasAVX512] in {
2606 let AddedComplexity = 15 in {
2607 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2608 // MOVS{S,D} to the lower bits.
2609 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2610 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2611 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2612 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2613 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2614 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2615 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2616 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2618 // Move low f32 and clear high bits.
2619 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2620 (SUBREG_TO_REG (i32 0),
2621 (VMOVSSZrr (v4f32 (V_SET0)),
2622 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2623 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2624 (SUBREG_TO_REG (i32 0),
2625 (VMOVSSZrr (v4i32 (V_SET0)),
2626 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2629 let AddedComplexity = 20 in {
2630 // MOVSSrm zeros the high parts of the register; represent this
2631 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2632 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2633 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2634 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2635 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2636 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2637 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2639 // MOVSDrm zeros the high parts of the register; represent this
2640 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2641 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2642 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2643 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2644 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2645 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2646 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2647 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2648 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2649 def : Pat<(v2f64 (X86vzload addr:$src)),
2650 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2652 // Represent the same patterns above but in the form they appear for
2654 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2655 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2656 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2657 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2658 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2659 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2660 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2661 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2662 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2664 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2665 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2666 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2667 FR32X:$src)), sub_xmm)>;
2668 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2669 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2670 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2671 FR64X:$src)), sub_xmm)>;
2672 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2673 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2674 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2676 // Move low f64 and clear high bits.
2677 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2678 (SUBREG_TO_REG (i32 0),
2679 (VMOVSDZrr (v2f64 (V_SET0)),
2680 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2682 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2683 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2684 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2686 // Extract and store.
2687 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2689 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2690 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2692 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2694 // Shuffle with VMOVSS
2695 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2696 (VMOVSSZrr (v4i32 VR128X:$src1),
2697 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2698 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2699 (VMOVSSZrr (v4f32 VR128X:$src1),
2700 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2703 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2704 (SUBREG_TO_REG (i32 0),
2705 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2706 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2708 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2709 (SUBREG_TO_REG (i32 0),
2710 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2711 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2714 // Shuffle with VMOVSD
2715 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2716 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2717 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2718 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2719 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2720 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2721 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2722 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2725 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2726 (SUBREG_TO_REG (i32 0),
2727 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2728 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2730 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2731 (SUBREG_TO_REG (i32 0),
2732 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2733 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2736 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2737 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2738 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2739 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2740 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2741 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2742 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2743 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2746 let AddedComplexity = 15 in
2747 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2749 "vmovq\t{$src, $dst|$dst, $src}",
2750 [(set VR128X:$dst, (v2i64 (X86vzmovl
2751 (v2i64 VR128X:$src))))],
2752 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2754 let AddedComplexity = 20 in
2755 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2757 "vmovq\t{$src, $dst|$dst, $src}",
2758 [(set VR128X:$dst, (v2i64 (X86vzmovl
2759 (loadv2i64 addr:$src))))],
2760 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2761 EVEX_CD8<8, CD8VT8>;
2763 let Predicates = [HasAVX512] in {
2764 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2765 let AddedComplexity = 20 in {
2766 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2767 (VMOVDI2PDIZrm addr:$src)>;
2768 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2769 (VMOV64toPQIZrr GR64:$src)>;
2770 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2771 (VMOVDI2PDIZrr GR32:$src)>;
2773 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2774 (VMOVDI2PDIZrm addr:$src)>;
2775 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2776 (VMOVDI2PDIZrm addr:$src)>;
2777 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2778 (VMOVZPQILo2PQIZrm addr:$src)>;
2779 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2780 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2781 def : Pat<(v2i64 (X86vzload addr:$src)),
2782 (VMOVZPQILo2PQIZrm addr:$src)>;
2785 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2786 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2787 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2788 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2789 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2790 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2791 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2794 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2795 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2797 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2798 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2800 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2801 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2803 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2804 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2806 //===----------------------------------------------------------------------===//
2807 // AVX-512 - Non-temporals
2808 //===----------------------------------------------------------------------===//
2809 let SchedRW = [WriteLoad] in {
2810 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2811 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2812 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2813 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2814 EVEX_CD8<64, CD8VF>;
2816 let Predicates = [HasAVX512, HasVLX] in {
2817 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2819 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2820 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2821 EVEX_CD8<64, CD8VF>;
2823 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2825 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2826 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2827 EVEX_CD8<64, CD8VF>;
2831 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2832 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2833 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2834 let SchedRW = [WriteStore], mayStore = 1,
2835 AddedComplexity = 400 in
2836 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2837 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2838 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2841 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2842 string elty, string elsz, string vsz512,
2843 string vsz256, string vsz128, Domain d,
2844 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2845 let Predicates = [prd] in
2846 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2847 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2848 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2851 let Predicates = [prd, HasVLX] in {
2852 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2853 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2854 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2857 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2858 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2859 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2864 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2865 "i", "64", "8", "4", "2", SSEPackedInt,
2866 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2868 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2869 "f", "64", "8", "4", "2", SSEPackedDouble,
2870 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2872 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2873 "f", "32", "16", "8", "4", SSEPackedSingle,
2874 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2876 //===----------------------------------------------------------------------===//
2877 // AVX-512 - Integer arithmetic
2879 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2880 X86VectorVTInfo _, OpndItins itins,
2881 bit IsCommutable = 0> {
2882 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2883 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2884 "$src2, $src1", "$src1, $src2",
2885 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2886 "", itins.rr, IsCommutable>,
2887 AVX512BIBase, EVEX_4V;
2890 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2891 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2892 "$src2, $src1", "$src1, $src2",
2893 (_.VT (OpNode _.RC:$src1,
2894 (bitconvert (_.LdFrag addr:$src2)))),
2896 AVX512BIBase, EVEX_4V;
2899 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2900 X86VectorVTInfo _, OpndItins itins,
2901 bit IsCommutable = 0> :
2902 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2904 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2905 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2906 "${src2}"##_.BroadcastStr##", $src1",
2907 "$src1, ${src2}"##_.BroadcastStr,
2908 (_.VT (OpNode _.RC:$src1,
2910 (_.ScalarLdFrag addr:$src2)))),
2912 AVX512BIBase, EVEX_4V, EVEX_B;
2915 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2916 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2917 Predicate prd, bit IsCommutable = 0> {
2918 let Predicates = [prd] in
2919 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2920 IsCommutable>, EVEX_V512;
2922 let Predicates = [prd, HasVLX] in {
2923 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2924 IsCommutable>, EVEX_V256;
2925 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2926 IsCommutable>, EVEX_V128;
2930 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2931 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2932 Predicate prd, bit IsCommutable = 0> {
2933 let Predicates = [prd] in
2934 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2935 IsCommutable>, EVEX_V512;
2937 let Predicates = [prd, HasVLX] in {
2938 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2939 IsCommutable>, EVEX_V256;
2940 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2941 IsCommutable>, EVEX_V128;
2945 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2946 OpndItins itins, Predicate prd,
2947 bit IsCommutable = 0> {
2948 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2949 itins, prd, IsCommutable>,
2950 VEX_W, EVEX_CD8<64, CD8VF>;
2953 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2954 OpndItins itins, Predicate prd,
2955 bit IsCommutable = 0> {
2956 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2957 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2960 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2961 OpndItins itins, Predicate prd,
2962 bit IsCommutable = 0> {
2963 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2964 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2967 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2968 OpndItins itins, Predicate prd,
2969 bit IsCommutable = 0> {
2970 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2971 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2974 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2975 SDNode OpNode, OpndItins itins, Predicate prd,
2976 bit IsCommutable = 0> {
2977 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2980 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2984 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2985 SDNode OpNode, OpndItins itins, Predicate prd,
2986 bit IsCommutable = 0> {
2987 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2990 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2994 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2995 bits<8> opc_d, bits<8> opc_q,
2996 string OpcodeStr, SDNode OpNode,
2997 OpndItins itins, bit IsCommutable = 0> {
2998 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2999 itins, HasAVX512, IsCommutable>,
3000 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3001 itins, HasBWI, IsCommutable>;
3004 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
3005 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
3006 PatFrag memop_frag, X86MemOperand x86memop,
3007 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
3008 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
3009 let isCommutable = IsCommutable in
3011 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3012 (ins RC:$src1, RC:$src2),
3013 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3015 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3016 (ins KRC:$mask, RC:$src1, RC:$src2),
3017 !strconcat(OpcodeStr,
3018 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3019 [], itins.rr>, EVEX_4V, EVEX_K;
3020 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3021 (ins KRC:$mask, RC:$src1, RC:$src2),
3022 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
3023 "|$dst {${mask}} {z}, $src1, $src2}"),
3024 [], itins.rr>, EVEX_4V, EVEX_KZ;
3026 let mayLoad = 1 in {
3027 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3028 (ins RC:$src1, x86memop:$src2),
3029 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3031 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3032 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3033 !strconcat(OpcodeStr,
3034 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3035 [], itins.rm>, EVEX_4V, EVEX_K;
3036 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3037 (ins KRC:$mask, RC:$src1, x86memop:$src2),
3038 !strconcat(OpcodeStr,
3039 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
3040 [], itins.rm>, EVEX_4V, EVEX_KZ;
3041 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3042 (ins RC:$src1, x86scalar_mop:$src2),
3043 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3044 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
3045 [], itins.rm>, EVEX_4V, EVEX_B;
3046 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3047 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3048 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3049 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
3051 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
3052 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3053 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
3054 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3055 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3057 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
3061 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3062 SSE_INTALU_ITINS_P, 1>;
3063 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3064 SSE_INTALU_ITINS_P, 0>;
3065 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3066 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3067 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3068 SSE_INTALU_ITINS_P, HasBWI, 1>;
3069 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3070 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3072 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
3073 loadv8i64, i512mem, loadi64, i64mem, "{1to8}",
3074 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
3075 EVEX_CD8<64, CD8VF>, VEX_W;
3077 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
3078 loadv8i64, i512mem, loadi64, i64mem, "{1to8}",
3079 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3081 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
3082 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3084 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
3085 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3086 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3087 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
3088 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3089 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
3091 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3092 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3093 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3094 SSE_INTALU_ITINS_P, HasBWI, 1>;
3095 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3096 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3098 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3099 SSE_INTALU_ITINS_P, HasBWI, 1>;
3100 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3101 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3102 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3103 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3105 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3106 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3107 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3108 SSE_INTALU_ITINS_P, HasBWI, 1>;
3109 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3110 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3112 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3113 SSE_INTALU_ITINS_P, HasBWI, 1>;
3114 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3115 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3116 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3117 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3119 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3120 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3121 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3122 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3123 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3124 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3125 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3126 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3127 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3128 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3129 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3130 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3131 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3132 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3133 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3134 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3135 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3136 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3137 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3138 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3139 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3140 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3141 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3142 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3143 //===----------------------------------------------------------------------===//
3144 // AVX-512 - Unpack Instructions
3145 //===----------------------------------------------------------------------===//
3147 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3148 PatFrag mem_frag, RegisterClass RC,
3149 X86MemOperand x86memop, string asm,
3151 def rr : AVX512PI<opc, MRMSrcReg,
3152 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3154 (vt (OpNode RC:$src1, RC:$src2)))],
3156 def rm : AVX512PI<opc, MRMSrcMem,
3157 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3159 (vt (OpNode RC:$src1,
3160 (bitconvert (mem_frag addr:$src2)))))],
3164 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3165 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3166 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3167 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3168 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3169 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3170 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3171 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3172 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3173 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3174 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3175 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3177 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3178 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3179 X86MemOperand x86memop> {
3180 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3181 (ins RC:$src1, RC:$src2),
3182 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3183 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3184 IIC_SSE_UNPCK>, EVEX_4V;
3185 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3186 (ins RC:$src1, x86memop:$src2),
3187 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3188 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3189 (bitconvert (memop_frag addr:$src2)))))],
3190 IIC_SSE_UNPCK>, EVEX_4V;
3192 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3193 VR512, loadv16i32, i512mem>, EVEX_V512,
3194 EVEX_CD8<32, CD8VF>;
3195 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3196 VR512, loadv8i64, i512mem>, EVEX_V512,
3197 VEX_W, EVEX_CD8<64, CD8VF>;
3198 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3199 VR512, loadv16i32, i512mem>, EVEX_V512,
3200 EVEX_CD8<32, CD8VF>;
3201 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3202 VR512, loadv8i64, i512mem>, EVEX_V512,
3203 VEX_W, EVEX_CD8<64, CD8VF>;
3204 //===----------------------------------------------------------------------===//
3208 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3209 SDNode OpNode, PatFrag mem_frag,
3210 X86MemOperand x86memop, ValueType OpVT> {
3211 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3212 (ins RC:$src1, u8imm:$src2),
3213 !strconcat(OpcodeStr,
3214 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3216 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3218 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3219 (ins x86memop:$src1, u8imm:$src2),
3220 !strconcat(OpcodeStr,
3221 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3223 (OpVT (OpNode (mem_frag addr:$src1),
3224 (i8 imm:$src2))))]>, EVEX;
3227 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, loadv16i32,
3228 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3230 //===----------------------------------------------------------------------===//
3231 // AVX-512 Logical Instructions
3232 //===----------------------------------------------------------------------===//
3234 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3235 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3236 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3237 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3238 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3239 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3240 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3241 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3243 //===----------------------------------------------------------------------===//
3244 // AVX-512 FP arithmetic
3245 //===----------------------------------------------------------------------===//
3247 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3249 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3250 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3251 EVEX_CD8<32, CD8VT1>;
3252 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3253 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3254 EVEX_CD8<64, CD8VT1>;
3257 let isCommutable = 1 in {
3258 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3259 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3260 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3261 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3263 let isCommutable = 0 in {
3264 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3265 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3268 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3269 X86VectorVTInfo _, bit IsCommutable> {
3270 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3271 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3272 "$src2, $src1", "$src1, $src2",
3273 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3274 let mayLoad = 1 in {
3275 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3276 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3277 "$src2, $src1", "$src1, $src2",
3278 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3279 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3280 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3281 "${src2}"##_.BroadcastStr##", $src1",
3282 "$src1, ${src2}"##_.BroadcastStr,
3283 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3284 (_.ScalarLdFrag addr:$src2))))>,
3289 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3290 X86VectorVTInfo _, bit IsCommutable> {
3291 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3292 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3293 "$rc, $src2, $src1", "$src1, $src2, $rc",
3294 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3295 EVEX_4V, EVEX_B, EVEX_RC;
3298 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3299 bit IsCommutable = 0> {
3300 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3301 IsCommutable>, EVEX_V512, PS,
3302 EVEX_CD8<32, CD8VF>;
3303 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3304 IsCommutable>, EVEX_V512, PD, VEX_W,
3305 EVEX_CD8<64, CD8VF>;
3307 // Define only if AVX512VL feature is present.
3308 let Predicates = [HasVLX] in {
3309 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3310 IsCommutable>, EVEX_V128, PS,
3311 EVEX_CD8<32, CD8VF>;
3312 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3313 IsCommutable>, EVEX_V256, PS,
3314 EVEX_CD8<32, CD8VF>;
3315 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3316 IsCommutable>, EVEX_V128, PD, VEX_W,
3317 EVEX_CD8<64, CD8VF>;
3318 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3319 IsCommutable>, EVEX_V256, PD, VEX_W,
3320 EVEX_CD8<64, CD8VF>;
3324 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3325 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3326 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3327 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3328 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3331 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3332 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3333 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3334 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3335 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3336 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3337 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3338 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3339 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3340 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3342 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3343 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3344 (i16 -1), FROUND_CURRENT)),
3345 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3347 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3348 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3349 (i8 -1), FROUND_CURRENT)),
3350 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3352 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3353 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3354 (i16 -1), FROUND_CURRENT)),
3355 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3357 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3358 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3359 (i8 -1), FROUND_CURRENT)),
3360 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3361 //===----------------------------------------------------------------------===//
3362 // AVX-512 VPTESTM instructions
3363 //===----------------------------------------------------------------------===//
3365 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3366 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3367 SDNode OpNode, ValueType vt> {
3368 def rr : AVX512PI<opc, MRMSrcReg,
3369 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3370 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3371 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3372 SSEPackedInt>, EVEX_4V;
3373 def rm : AVX512PI<opc, MRMSrcMem,
3374 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3375 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3376 [(set KRC:$dst, (OpNode (vt RC:$src1),
3377 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3380 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3381 loadv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3382 EVEX_CD8<32, CD8VF>;
3383 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3384 loadv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3385 EVEX_CD8<64, CD8VF>;
3387 let Predicates = [HasCDI] in {
3388 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3389 loadv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3390 EVEX_CD8<32, CD8VF>;
3391 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3392 loadv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3393 EVEX_CD8<64, CD8VF>;
3396 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3397 (v16i32 VR512:$src2), (i16 -1))),
3398 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3400 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3401 (v8i64 VR512:$src2), (i8 -1))),
3402 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3404 //===----------------------------------------------------------------------===//
3405 // AVX-512 Shift instructions
3406 //===----------------------------------------------------------------------===//
3407 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3408 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3409 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3410 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3411 "$src2, $src1", "$src1, $src2",
3412 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3413 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3414 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3415 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3416 "$src2, $src1", "$src1, $src2",
3417 (_.VT (OpNode (_.LdFrag addr:$src1), (i8 imm:$src2))),
3418 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3421 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3422 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3423 // src2 is always 128-bit
3424 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3425 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3426 "$src2, $src1", "$src1, $src2",
3427 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3428 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3429 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3430 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3431 "$src2, $src1", "$src1, $src2",
3432 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3433 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3436 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3437 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3438 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3441 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3443 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3444 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3445 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3446 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3449 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3451 EVEX_V512, EVEX_CD8<32, CD8VF>;
3452 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3453 v8i64_info>, EVEX_V512,
3454 EVEX_CD8<64, CD8VF>, VEX_W;
3456 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3457 v16i32_info>, EVEX_V512,
3458 EVEX_CD8<32, CD8VF>;
3459 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3460 v8i64_info>, EVEX_V512,
3461 EVEX_CD8<64, CD8VF>, VEX_W;
3463 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3465 EVEX_V512, EVEX_CD8<32, CD8VF>;
3466 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3467 v8i64_info>, EVEX_V512,
3468 EVEX_CD8<64, CD8VF>, VEX_W;
3470 defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3471 defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3472 defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3474 //===-------------------------------------------------------------------===//
3475 // Variable Bit Shifts
3476 //===-------------------------------------------------------------------===//
3477 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3478 X86VectorVTInfo _> {
3479 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3480 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3481 "$src2, $src1", "$src1, $src2",
3482 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3483 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3484 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3485 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3486 "$src2, $src1", "$src1, $src2",
3487 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2))),
3488 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
3491 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3492 AVX512VLVectorVTInfo _> {
3493 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3496 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3498 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3499 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
3500 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3501 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3504 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
3505 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
3506 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
3508 //===----------------------------------------------------------------------===//
3509 // AVX-512 - MOVDDUP
3510 //===----------------------------------------------------------------------===//
3512 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3513 X86MemOperand x86memop, PatFrag memop_frag> {
3514 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3515 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3516 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3517 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3520 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3523 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3524 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3525 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3526 (VMOVDDUPZrm addr:$src)>;
3528 //===---------------------------------------------------------------------===//
3529 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3530 //===---------------------------------------------------------------------===//
3531 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3532 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3533 X86MemOperand x86memop> {
3534 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3535 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3536 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3538 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3539 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3540 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3543 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3544 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3545 EVEX_CD8<32, CD8VF>;
3546 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3547 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3548 EVEX_CD8<32, CD8VF>;
3550 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3551 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3552 (VMOVSHDUPZrm addr:$src)>;
3553 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3554 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3555 (VMOVSLDUPZrm addr:$src)>;
3557 //===----------------------------------------------------------------------===//
3558 // Move Low to High and High to Low packed FP Instructions
3559 //===----------------------------------------------------------------------===//
3560 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3561 (ins VR128X:$src1, VR128X:$src2),
3562 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3563 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3564 IIC_SSE_MOV_LH>, EVEX_4V;
3565 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3566 (ins VR128X:$src1, VR128X:$src2),
3567 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3568 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3569 IIC_SSE_MOV_LH>, EVEX_4V;
3571 let Predicates = [HasAVX512] in {
3573 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3574 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3575 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3576 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3579 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3580 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3583 //===----------------------------------------------------------------------===//
3584 // FMA - Fused Multiply Operations
3587 let Constraints = "$src1 = $dst" in {
3588 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3589 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3590 SDPatternOperator OpNode = null_frag> {
3591 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3592 (ins _.RC:$src2, _.RC:$src3),
3593 OpcodeStr, "$src3, $src2", "$src2, $src3",
3594 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3598 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3599 (ins _.RC:$src2, _.MemOp:$src3),
3600 OpcodeStr, "$src3, $src2", "$src2, $src3",
3601 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3604 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3605 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3606 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ),
3607 (OpNode _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3608 AVX512FMA3Base, EVEX_B;
3610 } // Constraints = "$src1 = $dst"
3612 let Constraints = "$src1 = $dst" in {
3613 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3614 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3615 SDPatternOperator OpNode> {
3616 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3617 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
3618 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
3619 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
3620 AVX512FMA3Base, EVEX_B, EVEX_RC;
3622 } // Constraints = "$src1 = $dst"
3624 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
3625 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
3626 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3627 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3630 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3631 string OpcodeStr, X86VectorVTInfo VTI,
3632 SDPatternOperator OpNode> {
3633 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3634 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3636 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3637 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
3640 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
3642 SDPatternOperator OpNode,
3643 SDPatternOperator OpNodeRnd> {
3644 let ExeDomain = SSEPackedSingle in {
3645 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3646 v16f32_info, OpNode>,
3647 avx512_fma3_round_forms<opc213, OpcodeStr,
3648 v16f32_info, OpNodeRnd>, EVEX_V512;
3649 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3650 v8f32x_info, OpNode>, EVEX_V256;
3651 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3652 v4f32x_info, OpNode>, EVEX_V128;
3654 let ExeDomain = SSEPackedDouble in {
3655 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3656 v8f64_info, OpNode>,
3657 avx512_fma3_round_forms<opc213, OpcodeStr,
3658 v8f64_info, OpNodeRnd>, EVEX_V512, VEX_W;
3659 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3660 v4f64x_info, OpNode>, EVEX_V256, VEX_W;
3661 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3662 v2f64x_info, OpNode>, EVEX_V128, VEX_W;
3666 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
3667 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
3668 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
3669 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
3670 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
3671 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
3673 let Constraints = "$src1 = $dst" in {
3674 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3675 X86VectorVTInfo _> {
3677 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3678 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3679 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3680 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
3682 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3683 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3684 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3685 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3687 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3688 (_.ScalarLdFrag addr:$src2))),
3689 _.RC:$src3))]>, EVEX_B;
3691 } // Constraints = "$src1 = $dst"
3694 multiclass avx512_fma3p_m132_f<bits<8> opc,
3698 let ExeDomain = SSEPackedSingle in {
3699 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
3700 OpNode,v16f32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3701 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3702 OpNode, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>;
3703 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3704 OpNode, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>;
3706 let ExeDomain = SSEPackedDouble in {
3707 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
3708 OpNode, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VF>;
3709 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3710 OpNode, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<32, CD8VF>;
3711 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3712 OpNode, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<32, CD8VF>;
3716 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
3717 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
3718 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
3719 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
3720 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
3721 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
3725 let Constraints = "$src1 = $dst" in {
3726 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3727 RegisterClass RC, ValueType OpVT,
3728 X86MemOperand x86memop, Operand memop,
3730 let isCommutable = 1 in
3731 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3732 (ins RC:$src1, RC:$src2, RC:$src3),
3733 !strconcat(OpcodeStr,
3734 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3736 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3738 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3739 (ins RC:$src1, RC:$src2, f128mem:$src3),
3740 !strconcat(OpcodeStr,
3741 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3743 (OpVT (OpNode RC:$src2, RC:$src1,
3744 (mem_frag addr:$src3))))]>;
3747 } // Constraints = "$src1 = $dst"
3749 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3750 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3751 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3752 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3753 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3754 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3755 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3756 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3757 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3758 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3759 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3760 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3761 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3762 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3763 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3764 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3766 //===----------------------------------------------------------------------===//
3767 // AVX-512 Scalar convert from sign integer to float/double
3768 //===----------------------------------------------------------------------===//
3770 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3771 X86MemOperand x86memop, string asm> {
3772 let hasSideEffects = 0 in {
3773 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3774 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3777 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3778 (ins DstRC:$src1, x86memop:$src),
3779 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3781 } // hasSideEffects = 0
3783 let Predicates = [HasAVX512] in {
3784 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3785 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3786 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3787 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3788 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3789 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3790 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3791 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3793 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3794 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3795 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3796 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3797 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3798 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3799 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3800 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3802 def : Pat<(f32 (sint_to_fp GR32:$src)),
3803 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3804 def : Pat<(f32 (sint_to_fp GR64:$src)),
3805 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3806 def : Pat<(f64 (sint_to_fp GR32:$src)),
3807 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3808 def : Pat<(f64 (sint_to_fp GR64:$src)),
3809 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3811 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3812 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3813 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3814 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3815 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3816 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3817 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3818 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3820 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3821 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3822 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3823 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3824 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3825 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3826 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3827 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3829 def : Pat<(f32 (uint_to_fp GR32:$src)),
3830 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3831 def : Pat<(f32 (uint_to_fp GR64:$src)),
3832 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3833 def : Pat<(f64 (uint_to_fp GR32:$src)),
3834 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3835 def : Pat<(f64 (uint_to_fp GR64:$src)),
3836 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3839 //===----------------------------------------------------------------------===//
3840 // AVX-512 Scalar convert from float/double to integer
3841 //===----------------------------------------------------------------------===//
3842 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3843 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3845 let hasSideEffects = 0 in {
3846 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3847 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3848 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3849 Requires<[HasAVX512]>;
3851 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3852 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3853 Requires<[HasAVX512]>;
3854 } // hasSideEffects = 0
3856 let Predicates = [HasAVX512] in {
3857 // Convert float/double to signed/unsigned int 32/64
3858 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3859 ssmem, sse_load_f32, "cvtss2si">,
3860 XS, EVEX_CD8<32, CD8VT1>;
3861 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3862 ssmem, sse_load_f32, "cvtss2si">,
3863 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3864 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3865 ssmem, sse_load_f32, "cvtss2usi">,
3866 XS, EVEX_CD8<32, CD8VT1>;
3867 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3868 int_x86_avx512_cvtss2usi64, ssmem,
3869 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3870 EVEX_CD8<32, CD8VT1>;
3871 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3872 sdmem, sse_load_f64, "cvtsd2si">,
3873 XD, EVEX_CD8<64, CD8VT1>;
3874 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3875 sdmem, sse_load_f64, "cvtsd2si">,
3876 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3877 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3878 sdmem, sse_load_f64, "cvtsd2usi">,
3879 XD, EVEX_CD8<64, CD8VT1>;
3880 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3881 int_x86_avx512_cvtsd2usi64, sdmem,
3882 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3883 EVEX_CD8<64, CD8VT1>;
3885 let isCodeGenOnly = 1 in {
3886 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3887 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3888 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3889 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3890 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3891 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3892 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3893 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3894 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3895 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3896 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3897 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3899 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3900 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3901 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3902 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3903 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3904 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3905 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3906 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3907 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3908 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3909 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3910 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3911 } // isCodeGenOnly = 1
3913 // Convert float/double to signed/unsigned int 32/64 with truncation
3914 let isCodeGenOnly = 1 in {
3915 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3916 ssmem, sse_load_f32, "cvttss2si">,
3917 XS, EVEX_CD8<32, CD8VT1>;
3918 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3919 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3920 "cvttss2si">, XS, VEX_W,
3921 EVEX_CD8<32, CD8VT1>;
3922 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3923 sdmem, sse_load_f64, "cvttsd2si">, XD,
3924 EVEX_CD8<64, CD8VT1>;
3925 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3926 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3927 "cvttsd2si">, XD, VEX_W,
3928 EVEX_CD8<64, CD8VT1>;
3929 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3930 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3931 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3932 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3933 int_x86_avx512_cvttss2usi64, ssmem,
3934 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3935 EVEX_CD8<32, CD8VT1>;
3936 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3937 int_x86_avx512_cvttsd2usi,
3938 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3939 EVEX_CD8<64, CD8VT1>;
3940 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3941 int_x86_avx512_cvttsd2usi64, sdmem,
3942 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3943 EVEX_CD8<64, CD8VT1>;
3944 } // isCodeGenOnly = 1
3946 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3947 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3949 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3950 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3951 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3952 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3953 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3954 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3957 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3958 loadf32, "cvttss2si">, XS,
3959 EVEX_CD8<32, CD8VT1>;
3960 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3961 loadf32, "cvttss2usi">, XS,
3962 EVEX_CD8<32, CD8VT1>;
3963 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3964 loadf32, "cvttss2si">, XS, VEX_W,
3965 EVEX_CD8<32, CD8VT1>;
3966 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3967 loadf32, "cvttss2usi">, XS, VEX_W,
3968 EVEX_CD8<32, CD8VT1>;
3969 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3970 loadf64, "cvttsd2si">, XD,
3971 EVEX_CD8<64, CD8VT1>;
3972 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3973 loadf64, "cvttsd2usi">, XD,
3974 EVEX_CD8<64, CD8VT1>;
3975 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3976 loadf64, "cvttsd2si">, XD, VEX_W,
3977 EVEX_CD8<64, CD8VT1>;
3978 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3979 loadf64, "cvttsd2usi">, XD, VEX_W,
3980 EVEX_CD8<64, CD8VT1>;
3982 //===----------------------------------------------------------------------===//
3983 // AVX-512 Convert form float to double and back
3984 //===----------------------------------------------------------------------===//
3985 let hasSideEffects = 0 in {
3986 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3987 (ins FR32X:$src1, FR32X:$src2),
3988 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3989 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3991 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3992 (ins FR32X:$src1, f32mem:$src2),
3993 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3994 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3995 EVEX_CD8<32, CD8VT1>;
3997 // Convert scalar double to scalar single
3998 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3999 (ins FR64X:$src1, FR64X:$src2),
4000 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4001 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4003 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4004 (ins FR64X:$src1, f64mem:$src2),
4005 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4006 []>, EVEX_4V, VEX_LIG, VEX_W,
4007 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4010 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4011 Requires<[HasAVX512]>;
4012 def : Pat<(fextend (loadf32 addr:$src)),
4013 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4015 def : Pat<(extloadf32 addr:$src),
4016 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4017 Requires<[HasAVX512, OptForSize]>;
4019 def : Pat<(extloadf32 addr:$src),
4020 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4021 Requires<[HasAVX512, OptForSpeed]>;
4023 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4024 Requires<[HasAVX512]>;
4026 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4027 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4028 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4030 let hasSideEffects = 0 in {
4031 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4032 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4034 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4035 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4036 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4037 [], d>, EVEX, EVEX_B, EVEX_RC;
4039 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4040 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4042 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4043 } // hasSideEffects = 0
4046 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4047 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4048 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4050 let hasSideEffects = 0 in {
4051 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4052 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4054 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4056 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4057 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4059 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4060 } // hasSideEffects = 0
4063 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4064 loadv8f64, f512mem, v8f32, v8f64,
4065 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4066 EVEX_CD8<64, CD8VF>;
4068 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4069 loadv4f64, f256mem, v8f64, v8f32,
4070 SSEPackedDouble>, EVEX_V512, PS,
4071 EVEX_CD8<32, CD8VH>;
4072 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4073 (VCVTPS2PDZrm addr:$src)>;
4075 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4076 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4077 (VCVTPD2PSZrr VR512:$src)>;
4079 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4080 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4081 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4083 //===----------------------------------------------------------------------===//
4084 // AVX-512 Vector convert from sign integer to float/double
4085 //===----------------------------------------------------------------------===//
4087 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4088 loadv8i64, i512mem, v16f32, v16i32,
4089 SSEPackedSingle>, EVEX_V512, PS,
4090 EVEX_CD8<32, CD8VF>;
4092 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4093 loadv4i64, i256mem, v8f64, v8i32,
4094 SSEPackedDouble>, EVEX_V512, XS,
4095 EVEX_CD8<32, CD8VH>;
4097 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4098 loadv16f32, f512mem, v16i32, v16f32,
4099 SSEPackedSingle>, EVEX_V512, XS,
4100 EVEX_CD8<32, CD8VF>;
4102 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4103 loadv8f64, f512mem, v8i32, v8f64,
4104 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4105 EVEX_CD8<64, CD8VF>;
4107 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4108 loadv16f32, f512mem, v16i32, v16f32,
4109 SSEPackedSingle>, EVEX_V512, PS,
4110 EVEX_CD8<32, CD8VF>;
4112 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4113 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4114 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4115 (VCVTTPS2UDQZrr VR512:$src)>;
4117 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4118 loadv8f64, f512mem, v8i32, v8f64,
4119 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4120 EVEX_CD8<64, CD8VF>;
4122 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4123 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4124 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4125 (VCVTTPD2UDQZrr VR512:$src)>;
4127 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4128 loadv4i64, f256mem, v8f64, v8i32,
4129 SSEPackedDouble>, EVEX_V512, XS,
4130 EVEX_CD8<32, CD8VH>;
4132 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4133 loadv16i32, f512mem, v16f32, v16i32,
4134 SSEPackedSingle>, EVEX_V512, XD,
4135 EVEX_CD8<32, CD8VF>;
4137 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4138 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4139 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4141 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4142 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4143 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4145 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4146 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4147 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4149 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4150 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4151 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4153 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4154 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4155 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4157 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4158 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4159 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4160 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4161 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4162 (VCVTDQ2PDZrr VR256X:$src)>;
4163 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4164 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4165 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4166 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4167 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4168 (VCVTUDQ2PDZrr VR256X:$src)>;
4170 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4171 RegisterClass DstRC, PatFrag mem_frag,
4172 X86MemOperand x86memop, Domain d> {
4173 let hasSideEffects = 0 in {
4174 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4175 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4177 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4178 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4179 [], d>, EVEX, EVEX_B, EVEX_RC;
4181 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4182 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4184 } // hasSideEffects = 0
4187 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4188 loadv16f32, f512mem, SSEPackedSingle>, PD,
4189 EVEX_V512, EVEX_CD8<32, CD8VF>;
4190 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4191 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4192 EVEX_V512, EVEX_CD8<64, CD8VF>;
4194 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4195 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4196 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4198 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4199 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4200 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4202 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4203 loadv16f32, f512mem, SSEPackedSingle>,
4204 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4205 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4206 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4207 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4209 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4210 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4211 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4213 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4214 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4215 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4217 let Predicates = [HasAVX512] in {
4218 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4219 (VCVTPD2PSZrm addr:$src)>;
4220 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4221 (VCVTPS2PDZrm addr:$src)>;
4224 //===----------------------------------------------------------------------===//
4225 // Half precision conversion instructions
4226 //===----------------------------------------------------------------------===//
4227 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4228 X86MemOperand x86memop> {
4229 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4230 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4232 let hasSideEffects = 0, mayLoad = 1 in
4233 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4234 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4237 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4238 X86MemOperand x86memop> {
4239 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4240 (ins srcRC:$src1, i32u8imm:$src2),
4241 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4243 let hasSideEffects = 0, mayStore = 1 in
4244 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4245 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4246 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4249 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4250 EVEX_CD8<32, CD8VH>;
4251 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4252 EVEX_CD8<32, CD8VH>;
4254 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4255 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4256 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4258 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4259 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4260 (VCVTPH2PSZrr VR256X:$src)>;
4262 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4263 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4264 "ucomiss">, PS, EVEX, VEX_LIG,
4265 EVEX_CD8<32, CD8VT1>;
4266 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4267 "ucomisd">, PD, EVEX,
4268 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4269 let Pattern = []<dag> in {
4270 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4271 "comiss">, PS, EVEX, VEX_LIG,
4272 EVEX_CD8<32, CD8VT1>;
4273 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4274 "comisd">, PD, EVEX,
4275 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4277 let isCodeGenOnly = 1 in {
4278 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4279 load, "ucomiss">, PS, EVEX, VEX_LIG,
4280 EVEX_CD8<32, CD8VT1>;
4281 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4282 load, "ucomisd">, PD, EVEX,
4283 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4285 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4286 load, "comiss">, PS, EVEX, VEX_LIG,
4287 EVEX_CD8<32, CD8VT1>;
4288 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4289 load, "comisd">, PD, EVEX,
4290 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4294 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4295 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4296 X86MemOperand x86memop> {
4297 let hasSideEffects = 0 in {
4298 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4299 (ins RC:$src1, RC:$src2),
4300 !strconcat(OpcodeStr,
4301 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4302 let mayLoad = 1 in {
4303 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4304 (ins RC:$src1, x86memop:$src2),
4305 !strconcat(OpcodeStr,
4306 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4311 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4312 EVEX_CD8<32, CD8VT1>;
4313 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4314 VEX_W, EVEX_CD8<64, CD8VT1>;
4315 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4316 EVEX_CD8<32, CD8VT1>;
4317 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4318 VEX_W, EVEX_CD8<64, CD8VT1>;
4320 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4321 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4322 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4323 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4325 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4326 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4327 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4328 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4330 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4331 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4332 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4333 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4335 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4336 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4337 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4338 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4340 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4341 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4342 X86VectorVTInfo _> {
4343 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4344 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4345 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4346 let mayLoad = 1 in {
4347 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4348 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4350 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4351 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4352 (ins _.ScalarMemOp:$src), OpcodeStr,
4353 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4355 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4360 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4361 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4362 EVEX_V512, EVEX_CD8<32, CD8VF>;
4363 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4364 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4366 // Define only if AVX512VL feature is present.
4367 let Predicates = [HasVLX] in {
4368 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4369 OpNode, v4f32x_info>,
4370 EVEX_V128, EVEX_CD8<32, CD8VF>;
4371 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4372 OpNode, v8f32x_info>,
4373 EVEX_V256, EVEX_CD8<32, CD8VF>;
4374 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4375 OpNode, v2f64x_info>,
4376 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4377 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4378 OpNode, v4f64x_info>,
4379 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4383 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4384 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4386 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4387 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4388 (VRSQRT14PSZr VR512:$src)>;
4389 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4390 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4391 (VRSQRT14PDZr VR512:$src)>;
4393 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4394 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4395 (VRCP14PSZr VR512:$src)>;
4396 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4397 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4398 (VRCP14PDZr VR512:$src)>;
4400 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4401 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4404 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4405 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4406 "$src2, $src1", "$src1, $src2",
4407 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4408 (i32 FROUND_CURRENT))>;
4410 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4411 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4412 "$src2, $src1", "$src1, $src2",
4413 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4414 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4416 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4417 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4418 "$src2, $src1", "$src1, $src2",
4419 (OpNode (_.VT _.RC:$src1),
4420 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4421 (i32 FROUND_CURRENT))>;
4424 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4425 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4426 EVEX_CD8<32, CD8VT1>;
4427 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4428 EVEX_CD8<64, CD8VT1>, VEX_W;
4431 let hasSideEffects = 0, Predicates = [HasERI] in {
4432 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4433 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4435 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4437 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4440 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4441 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4442 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4444 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4445 (ins _.RC:$src), OpcodeStr,
4447 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4450 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4451 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4453 (bitconvert (_.LdFrag addr:$src))),
4454 (i32 FROUND_CURRENT))>;
4456 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4457 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4459 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4460 (i32 FROUND_CURRENT))>, EVEX_B;
4463 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4464 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4465 EVEX_CD8<32, CD8VF>;
4466 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4467 VEX_W, EVEX_CD8<32, CD8VF>;
4470 let Predicates = [HasERI], hasSideEffects = 0 in {
4472 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4473 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4474 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4477 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4478 SDNode OpNode, X86VectorVTInfo _>{
4479 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4480 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4481 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4482 let mayLoad = 1 in {
4483 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4484 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4486 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4488 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4489 (ins _.ScalarMemOp:$src), OpcodeStr,
4490 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4492 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4497 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4498 Intrinsic F32Int, Intrinsic F64Int,
4499 OpndItins itins_s, OpndItins itins_d> {
4500 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4501 (ins FR32X:$src1, FR32X:$src2),
4502 !strconcat(OpcodeStr,
4503 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4504 [], itins_s.rr>, XS, EVEX_4V;
4505 let isCodeGenOnly = 1 in
4506 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4507 (ins VR128X:$src1, VR128X:$src2),
4508 !strconcat(OpcodeStr,
4509 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4511 (F32Int VR128X:$src1, VR128X:$src2))],
4512 itins_s.rr>, XS, EVEX_4V;
4513 let mayLoad = 1 in {
4514 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4515 (ins FR32X:$src1, f32mem:$src2),
4516 !strconcat(OpcodeStr,
4517 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4518 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4519 let isCodeGenOnly = 1 in
4520 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4521 (ins VR128X:$src1, ssmem:$src2),
4522 !strconcat(OpcodeStr,
4523 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4525 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4526 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4528 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4529 (ins FR64X:$src1, FR64X:$src2),
4530 !strconcat(OpcodeStr,
4531 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4533 let isCodeGenOnly = 1 in
4534 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4535 (ins VR128X:$src1, VR128X:$src2),
4536 !strconcat(OpcodeStr,
4537 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4539 (F64Int VR128X:$src1, VR128X:$src2))],
4540 itins_s.rr>, XD, EVEX_4V, VEX_W;
4541 let mayLoad = 1 in {
4542 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4543 (ins FR64X:$src1, f64mem:$src2),
4544 !strconcat(OpcodeStr,
4545 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4546 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4547 let isCodeGenOnly = 1 in
4548 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4549 (ins VR128X:$src1, sdmem:$src2),
4550 !strconcat(OpcodeStr,
4551 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4553 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4554 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4558 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4560 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4562 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4563 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4565 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4566 // Define only if AVX512VL feature is present.
4567 let Predicates = [HasVLX] in {
4568 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4569 OpNode, v4f32x_info>,
4570 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4571 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4572 OpNode, v8f32x_info>,
4573 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4574 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4575 OpNode, v2f64x_info>,
4576 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4577 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4578 OpNode, v4f64x_info>,
4579 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4583 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4585 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4586 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4587 SSE_SQRTSS, SSE_SQRTSD>;
4589 let Predicates = [HasAVX512] in {
4590 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4591 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4592 (VSQRTPSZr VR512:$src1)>;
4593 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4594 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4595 (VSQRTPDZr VR512:$src1)>;
4597 def : Pat<(f32 (fsqrt FR32X:$src)),
4598 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4599 def : Pat<(f32 (fsqrt (load addr:$src))),
4600 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4601 Requires<[OptForSize]>;
4602 def : Pat<(f64 (fsqrt FR64X:$src)),
4603 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4604 def : Pat<(f64 (fsqrt (load addr:$src))),
4605 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4606 Requires<[OptForSize]>;
4608 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4609 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4610 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4611 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4612 Requires<[OptForSize]>;
4614 def : Pat<(f32 (X86frcp FR32X:$src)),
4615 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4616 def : Pat<(f32 (X86frcp (load addr:$src))),
4617 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4618 Requires<[OptForSize]>;
4620 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4621 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4622 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4624 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4625 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4627 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4628 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4629 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4631 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4632 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4636 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4637 X86MemOperand x86memop, RegisterClass RC,
4638 PatFrag mem_frag, Domain d> {
4639 let ExeDomain = d in {
4640 // Intrinsic operation, reg.
4641 // Vector intrinsic operation, reg
4642 def r : AVX512AIi8<opc, MRMSrcReg,
4643 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
4644 !strconcat(OpcodeStr,
4645 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4648 // Vector intrinsic operation, mem
4649 def m : AVX512AIi8<opc, MRMSrcMem,
4650 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
4651 !strconcat(OpcodeStr,
4652 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4657 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4658 loadv16f32, SSEPackedSingle>, EVEX_V512,
4659 EVEX_CD8<32, CD8VF>;
4661 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4662 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4664 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4667 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4668 loadv8f64, SSEPackedDouble>, EVEX_V512,
4669 VEX_W, EVEX_CD8<64, CD8VF>;
4671 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4672 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4674 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4677 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
4679 let ExeDomain = _.ExeDomain in {
4680 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4681 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
4682 "$src3, $src2, $src1", "$src1, $src2, $src3",
4683 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4684 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
4686 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4687 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
4688 "$src3, $src2, $src1", "$src1, $src2, $src3",
4689 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4690 (i32 imm:$src3), (i32 FROUND_NO_EXC))), "{sae}">, EVEX_B;
4693 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4694 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
4695 "$src3, $src2, $src1", "$src1, $src2, $src3",
4696 (_.VT (X86RndScale (_.VT _.RC:$src1),
4697 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4698 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
4700 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
4701 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4702 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
4703 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
4704 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4705 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
4706 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
4707 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4708 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
4709 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
4710 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4711 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
4712 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
4713 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4714 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
4716 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4717 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4718 addr:$src, (i32 0x1))), _.FRC)>;
4719 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4720 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4721 addr:$src, (i32 0x2))), _.FRC)>;
4722 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4723 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4724 addr:$src, (i32 0x3))), _.FRC)>;
4725 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4726 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4727 addr:$src, (i32 0x4))), _.FRC)>;
4728 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4729 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4730 addr:$src, (i32 0xc))), _.FRC)>;
4733 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
4734 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4736 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
4737 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
4739 def : Pat<(v16f32 (ffloor VR512:$src)),
4740 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4741 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4742 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4743 def : Pat<(v16f32 (fceil VR512:$src)),
4744 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4745 def : Pat<(v16f32 (frint VR512:$src)),
4746 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4747 def : Pat<(v16f32 (ftrunc VR512:$src)),
4748 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4750 def : Pat<(v8f64 (ffloor VR512:$src)),
4751 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4752 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4753 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4754 def : Pat<(v8f64 (fceil VR512:$src)),
4755 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4756 def : Pat<(v8f64 (frint VR512:$src)),
4757 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4758 def : Pat<(v8f64 (ftrunc VR512:$src)),
4759 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4761 //-------------------------------------------------
4762 // Integer truncate and extend operations
4763 //-------------------------------------------------
4765 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4766 RegisterClass dstRC, RegisterClass srcRC,
4767 RegisterClass KRC, X86MemOperand x86memop> {
4768 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4770 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4773 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4774 (ins KRC:$mask, srcRC:$src),
4775 !strconcat(OpcodeStr,
4776 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4779 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4780 (ins KRC:$mask, srcRC:$src),
4781 !strconcat(OpcodeStr,
4782 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4785 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4786 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4789 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4790 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4791 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4795 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4796 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4797 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4798 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4799 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4800 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4801 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4802 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4803 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4804 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4805 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4806 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4807 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4808 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4809 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4810 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4811 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4812 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4813 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4814 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4815 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4816 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4817 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4818 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4819 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4820 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4821 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4822 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4823 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4824 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4826 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4827 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4828 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4829 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4830 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4832 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4833 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4834 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4835 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4836 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4837 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4838 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4839 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4842 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4843 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4844 PatFrag mem_frag, X86MemOperand x86memop,
4845 ValueType OpVT, ValueType InVT> {
4847 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4849 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4850 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4852 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4853 (ins KRC:$mask, SrcRC:$src),
4854 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4857 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4858 (ins KRC:$mask, SrcRC:$src),
4859 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4862 let mayLoad = 1 in {
4863 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4864 (ins x86memop:$src),
4865 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4867 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4870 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4871 (ins KRC:$mask, x86memop:$src),
4872 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4876 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4877 (ins KRC:$mask, x86memop:$src),
4878 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4884 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4885 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4887 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4888 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4890 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4891 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4892 EVEX_CD8<16, CD8VH>;
4893 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4894 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4895 EVEX_CD8<16, CD8VQ>;
4896 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4897 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4898 EVEX_CD8<32, CD8VH>;
4900 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4901 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4903 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4904 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4906 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4907 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4908 EVEX_CD8<16, CD8VH>;
4909 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4910 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4911 EVEX_CD8<16, CD8VQ>;
4912 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4913 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4914 EVEX_CD8<32, CD8VH>;
4916 //===----------------------------------------------------------------------===//
4917 // GATHER - SCATTER Operations
4919 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4920 RegisterClass RC, X86MemOperand memop> {
4922 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4923 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4924 (ins RC:$src1, KRC:$mask, memop:$src2),
4925 !strconcat(OpcodeStr,
4926 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4930 let ExeDomain = SSEPackedDouble in {
4931 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4932 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4933 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4934 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4937 let ExeDomain = SSEPackedSingle in {
4938 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4939 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4940 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4941 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4944 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4945 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4946 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4947 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4949 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4950 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4951 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4952 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4954 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4955 RegisterClass RC, X86MemOperand memop> {
4956 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4957 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4958 (ins memop:$dst, KRC:$mask, RC:$src2),
4959 !strconcat(OpcodeStr,
4960 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4964 let ExeDomain = SSEPackedDouble in {
4965 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4966 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4967 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4968 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4971 let ExeDomain = SSEPackedSingle in {
4972 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4973 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4974 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4975 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4978 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4979 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4980 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4981 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4983 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4984 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4985 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4986 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4989 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4990 RegisterClass KRC, X86MemOperand memop> {
4991 let Predicates = [HasPFI], hasSideEffects = 1 in
4992 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4993 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4997 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4998 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5000 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5001 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5003 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5004 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5006 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
5007 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5009 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
5010 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5012 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
5013 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5015 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5016 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5018 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5019 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5021 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5022 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5024 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5025 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5027 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5028 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5030 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5031 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5033 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5034 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5036 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5037 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5039 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5040 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5042 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5043 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5044 //===----------------------------------------------------------------------===//
5045 // VSHUFPS - VSHUFPD Operations
5047 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5048 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5050 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5051 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5052 !strconcat(OpcodeStr,
5053 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5054 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5055 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5056 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5057 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5058 (ins RC:$src1, RC:$src2, u8imm:$src3),
5059 !strconcat(OpcodeStr,
5060 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5061 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5062 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5063 EVEX_4V, Sched<[WriteShuffle]>;
5066 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5067 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5068 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5069 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5071 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5072 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5073 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5074 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5075 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5077 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5078 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5079 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5080 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5081 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5083 multiclass avx512_valign<X86VectorVTInfo _> {
5084 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5085 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5087 "$src3, $src2, $src1", "$src1, $src2, $src3",
5088 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5090 AVX512AIi8Base, EVEX_4V;
5092 // Also match valign of packed floats.
5093 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5094 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5097 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5098 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5099 !strconcat("valign"##_.Suffix,
5100 "\t{$src3, $src2, $src1, $dst|"
5101 "$dst, $src1, $src2, $src3}"),
5104 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5105 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5107 // Helper fragments to match sext vXi1 to vXiY.
5108 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5109 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5111 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5112 RegisterClass KRC, RegisterClass RC,
5113 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5115 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5116 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5118 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5119 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5121 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5122 !strconcat(OpcodeStr,
5123 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5125 let mayLoad = 1 in {
5126 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5127 (ins x86memop:$src),
5128 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5130 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5131 (ins KRC:$mask, x86memop:$src),
5132 !strconcat(OpcodeStr,
5133 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5135 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5136 (ins KRC:$mask, x86memop:$src),
5137 !strconcat(OpcodeStr,
5138 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5140 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5141 (ins x86scalar_mop:$src),
5142 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5143 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5145 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5146 (ins KRC:$mask, x86scalar_mop:$src),
5147 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5148 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5149 []>, EVEX, EVEX_B, EVEX_K;
5150 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5151 (ins KRC:$mask, x86scalar_mop:$src),
5152 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5153 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5155 []>, EVEX, EVEX_B, EVEX_KZ;
5159 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5160 i512mem, i32mem, "{1to16}">, EVEX_V512,
5161 EVEX_CD8<32, CD8VF>;
5162 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5163 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5164 EVEX_CD8<64, CD8VF>;
5167 (bc_v16i32 (v16i1sextv16i32)),
5168 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5169 (VPABSDZrr VR512:$src)>;
5171 (bc_v8i64 (v8i1sextv8i64)),
5172 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5173 (VPABSQZrr VR512:$src)>;
5175 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5176 (v16i32 immAllZerosV), (i16 -1))),
5177 (VPABSDZrr VR512:$src)>;
5178 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5179 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5180 (VPABSQZrr VR512:$src)>;
5182 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5183 RegisterClass RC, RegisterClass KRC,
5184 X86MemOperand x86memop,
5185 X86MemOperand x86scalar_mop, string BrdcstStr> {
5186 let hasSideEffects = 0 in {
5187 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5189 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5192 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5193 (ins x86memop:$src),
5194 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5197 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5198 (ins x86scalar_mop:$src),
5199 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5200 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5202 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5203 (ins KRC:$mask, RC:$src),
5204 !strconcat(OpcodeStr,
5205 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5208 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5209 (ins KRC:$mask, x86memop:$src),
5210 !strconcat(OpcodeStr,
5211 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5214 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5215 (ins KRC:$mask, x86scalar_mop:$src),
5216 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5217 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5219 []>, EVEX, EVEX_KZ, EVEX_B;
5221 let Constraints = "$src1 = $dst" in {
5222 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5223 (ins RC:$src1, KRC:$mask, RC:$src2),
5224 !strconcat(OpcodeStr,
5225 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5228 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5229 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5230 !strconcat(OpcodeStr,
5231 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5234 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5235 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5236 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5237 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5238 []>, EVEX, EVEX_K, EVEX_B;
5243 let Predicates = [HasCDI] in {
5244 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5245 i512mem, i32mem, "{1to16}">,
5246 EVEX_V512, EVEX_CD8<32, CD8VF>;
5249 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5250 i512mem, i64mem, "{1to8}">,
5251 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5255 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5257 (VPCONFLICTDrrk VR512:$src1,
5258 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5260 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5262 (VPCONFLICTQrrk VR512:$src1,
5263 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5265 let Predicates = [HasCDI] in {
5266 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5267 i512mem, i32mem, "{1to16}">,
5268 EVEX_V512, EVEX_CD8<32, CD8VF>;
5271 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5272 i512mem, i64mem, "{1to8}">,
5273 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5277 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5279 (VPLZCNTDrrk VR512:$src1,
5280 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5282 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5284 (VPLZCNTQrrk VR512:$src1,
5285 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5287 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5288 (VPLZCNTDrm addr:$src)>;
5289 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5290 (VPLZCNTDrr VR512:$src)>;
5291 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5292 (VPLZCNTQrm addr:$src)>;
5293 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5294 (VPLZCNTQrr VR512:$src)>;
5296 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5297 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5298 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5300 def : Pat<(store VK1:$src, addr:$dst),
5302 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5303 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5305 def : Pat<(store VK8:$src, addr:$dst),
5307 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5308 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5310 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5311 (truncstore node:$val, node:$ptr), [{
5312 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5315 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5316 (MOV8mr addr:$dst, GR8:$src)>;
5318 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5319 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5320 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5321 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5324 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5325 string OpcodeStr, Predicate prd> {
5326 let Predicates = [prd] in
5327 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5329 let Predicates = [prd, HasVLX] in {
5330 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5331 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5335 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5336 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5338 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5340 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5342 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5346 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5348 //===----------------------------------------------------------------------===//
5349 // AVX-512 - COMPRESS and EXPAND
5351 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5353 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5354 (ins _.KRCWM:$mask, _.RC:$src),
5355 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5356 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5357 _.ImmAllZerosV)))]>, EVEX_KZ;
5359 let Constraints = "$src0 = $dst" in
5360 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5361 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5362 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5363 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5364 _.RC:$src0)))]>, EVEX_K;
5366 let mayStore = 1 in {
5367 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5368 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5369 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5370 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5372 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5376 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5377 AVX512VLVectorVTInfo VTInfo> {
5378 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5380 let Predicates = [HasVLX] in {
5381 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5382 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5386 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5388 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5390 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5392 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5396 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5398 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5399 (ins _.KRCWM:$mask, _.RC:$src),
5400 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5401 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5402 _.ImmAllZerosV)))]>, EVEX_KZ;
5404 let Constraints = "$src0 = $dst" in
5405 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5406 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5407 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5408 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5409 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5411 let mayLoad = 1, Constraints = "$src0 = $dst" in
5412 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5413 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5414 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5415 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5417 (_.LdFrag addr:$src))),
5419 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5422 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5423 (ins _.KRCWM:$mask, _.MemOp:$src),
5424 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5425 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5426 (_.VT (bitconvert (_.LdFrag addr:$src))),
5427 _.ImmAllZerosV)))]>,
5428 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5432 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5433 AVX512VLVectorVTInfo VTInfo> {
5434 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5436 let Predicates = [HasVLX] in {
5437 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5438 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5442 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5444 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5446 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5448 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,