1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insertps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
625 def : Pat<(v16f32 (int_x86_avx512_mask_vpermt_ps_512 (v16i32 VR512:$idx),
626 (v16f32 VR512:$src1), (v16f32 VR512:$src2), (i16 -1))),
627 (VPERMT2PSrr VR512:$src1, VR512:$idx, VR512:$src2)>;
629 def : Pat<(v16i32 (int_x86_avx512_mask_vpermt_d_512 (v16i32 VR512:$idx),
630 (v16i32 VR512:$src1), (v16i32 VR512:$src2), (i16 -1))),
631 (VPERMT2Drr VR512:$src1, VR512:$idx, VR512:$src2)>;
633 def : Pat<(v8f64 (int_x86_avx512_mask_vpermt_pd_512 (v8i64 VR512:$idx),
634 (v8f64 VR512:$src1), (v8f64 VR512:$src2), (i8 -1))),
635 (VPERMT2PDrr VR512:$src1, VR512:$idx, VR512:$src2)>;
637 def : Pat<(v8i64 (int_x86_avx512_mask_vpermt_q_512 (v8i64 VR512:$idx),
638 (v8i64 VR512:$src1), (v8i64 VR512:$src2), (i8 -1))),
639 (VPERMT2Qrr VR512:$src1, VR512:$idx, VR512:$src2)>;
640 //===----------------------------------------------------------------------===//
641 // AVX-512 - BLEND using mask
643 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
644 RegisterClass KRC, RegisterClass RC,
645 X86MemOperand x86memop, PatFrag mem_frag,
646 SDNode OpNode, ValueType vt> {
647 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
648 (ins KRC:$mask, RC:$src1, RC:$src2),
649 !strconcat(OpcodeStr,
650 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
651 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
652 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
654 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
655 (ins KRC:$mask, RC:$src1, x86memop:$src2),
656 !strconcat(OpcodeStr,
657 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
658 []>, EVEX_4V, EVEX_K;
661 let ExeDomain = SSEPackedSingle in
662 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
663 VK16WM, VR512, f512mem,
664 memopv16f32, vselect, v16f32>,
665 EVEX_CD8<32, CD8VF>, EVEX_V512;
666 let ExeDomain = SSEPackedDouble in
667 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
668 VK8WM, VR512, f512mem,
669 memopv8f64, vselect, v8f64>,
670 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
672 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
673 (v16f32 VR512:$src2), (i16 GR16:$mask))),
674 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
675 VR512:$src1, VR512:$src2)>;
677 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
678 (v8f64 VR512:$src2), (i8 GR8:$mask))),
679 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
680 VR512:$src1, VR512:$src2)>;
682 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
683 VK16WM, VR512, f512mem,
684 memopv16i32, vselect, v16i32>,
685 EVEX_CD8<32, CD8VF>, EVEX_V512;
687 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
688 VK8WM, VR512, f512mem,
689 memopv8i64, vselect, v8i64>,
690 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
692 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
693 (v16i32 VR512:$src2), (i16 GR16:$mask))),
694 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
695 VR512:$src1, VR512:$src2)>;
697 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
698 (v8i64 VR512:$src2), (i8 GR8:$mask))),
699 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
700 VR512:$src1, VR512:$src2)>;
702 let Predicates = [HasAVX512] in {
703 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
704 (v8f32 VR256X:$src2))),
706 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
707 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
708 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
710 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
711 (v8i32 VR256X:$src2))),
713 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
714 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
715 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
717 //===----------------------------------------------------------------------===//
718 // Compare Instructions
719 //===----------------------------------------------------------------------===//
721 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
722 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
723 Operand CC, SDNode OpNode, ValueType VT,
724 PatFrag ld_frag, string asm, string asm_alt> {
725 def rr : AVX512Ii8<0xC2, MRMSrcReg,
726 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
727 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
728 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
729 def rm : AVX512Ii8<0xC2, MRMSrcMem,
730 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
731 [(set VK1:$dst, (OpNode (VT RC:$src1),
732 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
733 let isAsmParserOnly = 1, hasSideEffects = 0 in {
734 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
735 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
736 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
737 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
738 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
739 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
743 let Predicates = [HasAVX512] in {
744 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
745 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
746 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
748 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
749 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
750 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
754 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
755 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
756 SDNode OpNode, ValueType vt> {
757 def rr : AVX512BI<opc, MRMSrcReg,
758 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
759 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
760 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
761 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
762 def rm : AVX512BI<opc, MRMSrcMem,
763 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
764 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
765 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
766 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
769 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
770 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
772 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
773 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
774 VEX_W, EVEX_CD8<64, CD8VF>;
776 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
777 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
779 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
780 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
781 VEX_W, EVEX_CD8<64, CD8VF>;
783 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
784 (COPY_TO_REGCLASS (VPCMPGTDZrr
785 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
786 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
788 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
789 (COPY_TO_REGCLASS (VPCMPEQDZrr
790 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
791 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
793 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
794 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
795 SDNode OpNode, ValueType vt, Operand CC, string asm,
797 def rri : AVX512AIi8<opc, MRMSrcReg,
798 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
799 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
800 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
801 def rmi : AVX512AIi8<opc, MRMSrcMem,
802 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
803 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
804 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
805 // Accept explicit immediate argument form instead of comparison code.
806 let isAsmParserOnly = 1, hasSideEffects = 0 in {
807 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
808 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
809 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
810 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
811 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
812 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
816 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
817 X86cmpm, v16i32, AVXCC,
818 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
819 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
820 EVEX_V512, EVEX_CD8<32, CD8VF>;
821 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
822 X86cmpmu, v16i32, AVXCC,
823 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
824 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
825 EVEX_V512, EVEX_CD8<32, CD8VF>;
827 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
828 X86cmpm, v8i64, AVXCC,
829 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
830 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
831 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
832 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
833 X86cmpmu, v8i64, AVXCC,
834 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
835 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
836 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
838 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
839 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
840 X86MemOperand x86memop, ValueType vt,
841 string suffix, Domain d> {
842 def rri : AVX512PIi8<0xC2, MRMSrcReg,
843 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
844 !strconcat("vcmp${cc}", suffix,
845 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
846 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
847 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
848 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
849 !strconcat("vcmp${cc}", suffix,
850 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
852 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
853 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
854 !strconcat("vcmp${cc}", suffix,
855 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
857 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
859 // Accept explicit immediate argument form instead of comparison code.
860 let isAsmParserOnly = 1, hasSideEffects = 0 in {
861 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
862 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
863 !strconcat("vcmp", suffix,
864 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
865 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
866 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
867 !strconcat("vcmp", suffix,
868 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
872 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
873 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
875 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
876 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
879 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
880 (COPY_TO_REGCLASS (VCMPPSZrri
881 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
882 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
884 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
885 (COPY_TO_REGCLASS (VPCMPDZrri
886 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
887 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
889 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
890 (COPY_TO_REGCLASS (VPCMPUDZrri
891 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
892 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
895 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
896 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
898 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
899 (I8Imm imm:$cc)), GR16)>;
901 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
902 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
904 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
905 (I8Imm imm:$cc)), GR8)>;
907 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
908 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
910 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
911 (I8Imm imm:$cc)), GR16)>;
913 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
914 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
916 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
917 (I8Imm imm:$cc)), GR8)>;
919 // Mask register copy, including
920 // - copy between mask registers
921 // - load/store mask registers
922 // - copy from GPR to mask register and vice versa
924 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
925 string OpcodeStr, RegisterClass KRC,
926 ValueType vt, X86MemOperand x86memop> {
927 let hasSideEffects = 0 in {
928 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
929 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
931 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
932 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
933 [(set KRC:$dst, (vt (load addr:$src)))]>;
935 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
936 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
940 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
942 RegisterClass KRC, RegisterClass GRC> {
943 let hasSideEffects = 0 in {
944 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
945 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
946 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
947 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
951 let Predicates = [HasAVX512] in {
952 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
954 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
958 let Predicates = [HasAVX512] in {
959 // GR16 from/to 16-bit mask
960 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
961 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
962 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
963 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
965 // Store kreg in memory
966 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
967 (KMOVWmk addr:$dst, VK16:$src)>;
969 def : Pat<(store VK8:$src, addr:$dst),
970 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
972 def : Pat<(i1 (load addr:$src)),
973 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
975 def : Pat<(v8i1 (load addr:$src)),
976 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
978 def : Pat<(i1 (trunc (i32 GR32:$src))),
979 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
981 def : Pat<(i1 (trunc (i8 GR8:$src))),
983 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
985 def : Pat<(i1 (trunc (i16 GR16:$src))),
987 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
990 def : Pat<(i32 (zext VK1:$src)),
991 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
992 def : Pat<(i8 (zext VK1:$src)),
995 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
996 def : Pat<(i64 (zext VK1:$src)),
997 (AND64ri8 (SUBREG_TO_REG (i64 0),
998 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
999 def : Pat<(i16 (zext VK1:$src)),
1001 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1003 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1004 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1005 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1006 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1008 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1009 let Predicates = [HasAVX512] in {
1010 // GR from/to 8-bit mask without native support
1011 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1013 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1015 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1017 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1020 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1021 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1022 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1023 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1027 // Mask unary operation
1029 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1030 RegisterClass KRC, SDPatternOperator OpNode> {
1031 let Predicates = [HasAVX512] in
1032 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1033 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1034 [(set KRC:$dst, (OpNode KRC:$src))]>;
1037 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1038 SDPatternOperator OpNode> {
1039 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1043 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1045 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1046 let Predicates = [HasAVX512] in
1047 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1049 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1050 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1052 defm : avx512_mask_unop_int<"knot", "KNOT">;
1054 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1055 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1056 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1058 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1059 def : Pat<(not VK8:$src),
1061 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1063 // Mask binary operation
1064 // - KAND, KANDN, KOR, KXNOR, KXOR
1065 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1066 RegisterClass KRC, SDPatternOperator OpNode> {
1067 let Predicates = [HasAVX512] in
1068 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1069 !strconcat(OpcodeStr,
1070 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1071 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1074 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1075 SDPatternOperator OpNode> {
1076 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1080 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1081 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1083 let isCommutable = 1 in {
1084 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1085 let isCommutable = 0 in
1086 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1087 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1088 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1089 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1092 def : Pat<(xor VK1:$src1, VK1:$src2),
1093 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1094 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1096 def : Pat<(or VK1:$src1, VK1:$src2),
1097 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1098 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1100 def : Pat<(and VK1:$src1, VK1:$src2),
1101 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1102 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1104 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1105 let Predicates = [HasAVX512] in
1106 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1107 (i16 GR16:$src1), (i16 GR16:$src2)),
1108 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1109 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1110 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1113 defm : avx512_mask_binop_int<"kand", "KAND">;
1114 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1115 defm : avx512_mask_binop_int<"kor", "KOR">;
1116 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1117 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1119 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1120 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1121 let Predicates = [HasAVX512] in
1122 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1124 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1125 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1128 defm : avx512_binop_pat<and, KANDWrr>;
1129 defm : avx512_binop_pat<andn, KANDNWrr>;
1130 defm : avx512_binop_pat<or, KORWrr>;
1131 defm : avx512_binop_pat<xnor, KXNORWrr>;
1132 defm : avx512_binop_pat<xor, KXORWrr>;
1135 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1136 RegisterClass KRC> {
1137 let Predicates = [HasAVX512] in
1138 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1139 !strconcat(OpcodeStr,
1140 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1143 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1144 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1148 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1149 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1150 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1151 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1154 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1155 let Predicates = [HasAVX512] in
1156 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1157 (i16 GR16:$src1), (i16 GR16:$src2)),
1158 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1159 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1160 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1162 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1165 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1167 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1168 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1169 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1170 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1173 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1174 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1178 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1180 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1181 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1182 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1185 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1187 let Predicates = [HasAVX512] in
1188 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1189 !strconcat(OpcodeStr,
1190 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1191 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1194 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1196 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1200 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1201 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1203 // Mask setting all 0s or 1s
1204 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1205 let Predicates = [HasAVX512] in
1206 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1207 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1208 [(set KRC:$dst, (VT Val))]>;
1211 multiclass avx512_mask_setop_w<PatFrag Val> {
1212 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1213 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1216 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1217 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1219 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1220 let Predicates = [HasAVX512] in {
1221 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1222 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1223 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1224 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1225 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1227 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1228 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1230 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1231 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1233 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1234 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1236 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1237 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1239 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1240 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1241 //===----------------------------------------------------------------------===//
1242 // AVX-512 - Aligned and unaligned load and store
1245 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1246 X86MemOperand x86memop, PatFrag ld_frag,
1247 string asm, Domain d,
1248 ValueType vt, bit IsReMaterializable = 1> {
1249 let hasSideEffects = 0 in {
1250 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1251 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1253 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1255 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1256 [], d>, EVEX, EVEX_KZ;
1258 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1259 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1260 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1261 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1262 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1263 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1264 (ins RC:$src1, KRC:$mask, RC:$src2),
1266 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1269 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1270 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1272 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1273 [], d>, EVEX, EVEX_K;
1276 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1277 (ins KRC:$mask, x86memop:$src2),
1279 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1280 [], d>, EVEX, EVEX_KZ;
1283 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1284 X86MemOperand x86memop, PatFrag store_frag,
1285 string asm, Domain d, ValueType vt> {
1286 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1287 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1288 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1290 let Constraints = "$src1 = $dst" in
1291 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1292 (ins RC:$src1, KRC:$mask, RC:$src2),
1294 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1296 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1297 (ins KRC:$mask, RC:$src),
1299 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1300 [], d>, EVEX, EVEX_KZ;
1302 let mayStore = 1 in {
1303 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1304 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1305 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1306 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1307 (ins x86memop:$dst, KRC:$mask, RC:$src),
1309 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1310 [], d>, EVEX, EVEX_K;
1311 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1312 (ins x86memop:$dst, KRC:$mask, RC:$src),
1314 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1315 [], d>, EVEX, EVEX_KZ;
1319 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1320 "vmovaps", SSEPackedSingle, v16f32>,
1321 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1322 "vmovaps", SSEPackedSingle, v16f32>,
1323 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1324 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1325 "vmovapd", SSEPackedDouble, v8f64>,
1326 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1327 "vmovapd", SSEPackedDouble, v8f64>,
1328 PD, EVEX_V512, VEX_W,
1329 EVEX_CD8<64, CD8VF>;
1330 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1331 "vmovups", SSEPackedSingle, v16f32>,
1332 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1333 "vmovups", SSEPackedSingle, v16f32>,
1334 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1335 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1336 "vmovupd", SSEPackedDouble, v8f64, 0>,
1337 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1338 "vmovupd", SSEPackedDouble, v8f64>,
1339 PD, EVEX_V512, VEX_W,
1340 EVEX_CD8<64, CD8VF>;
1341 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1342 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1343 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1345 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1346 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1347 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1349 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1351 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1353 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1355 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1358 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1359 "vmovdqa32", SSEPackedInt, v16i32>,
1360 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1361 "vmovdqa32", SSEPackedInt, v16i32>,
1362 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1363 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1364 "vmovdqa64", SSEPackedInt, v8i64>,
1365 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1366 "vmovdqa64", SSEPackedInt, v8i64>,
1367 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1368 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1369 "vmovdqu32", SSEPackedInt, v16i32>,
1370 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1371 "vmovdqu32", SSEPackedInt, v16i32>,
1372 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1373 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1374 "vmovdqu64", SSEPackedInt, v8i64>,
1375 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1376 "vmovdqu64", SSEPackedInt, v8i64>,
1377 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1379 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1380 (v16i32 immAllZerosV), GR16:$mask)),
1381 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1383 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1384 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1385 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1387 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1389 (VMOVDQU32mrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1391 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1393 (VMOVDQU64mrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1396 let AddedComplexity = 20 in {
1397 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1398 (bc_v8i64 (v16i32 immAllZerosV)))),
1399 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1401 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1402 (v8i64 VR512:$src))),
1403 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1406 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1407 (v16i32 immAllZerosV))),
1408 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1410 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1411 (v16i32 VR512:$src))),
1412 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1414 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1415 (v16f32 VR512:$src2))),
1416 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1417 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1418 (v8f64 VR512:$src2))),
1419 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1420 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1421 (v16i32 VR512:$src2))),
1422 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1423 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1424 (v8i64 VR512:$src2))),
1425 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1427 // Move Int Doubleword to Packed Double Int
1429 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1430 "vmovd\t{$src, $dst|$dst, $src}",
1432 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1434 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1435 "vmovd\t{$src, $dst|$dst, $src}",
1437 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1438 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1439 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1440 "vmovq\t{$src, $dst|$dst, $src}",
1442 (v2i64 (scalar_to_vector GR64:$src)))],
1443 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1444 let isCodeGenOnly = 1 in {
1445 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1446 "vmovq\t{$src, $dst|$dst, $src}",
1447 [(set FR64:$dst, (bitconvert GR64:$src))],
1448 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1449 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1450 "vmovq\t{$src, $dst|$dst, $src}",
1451 [(set GR64:$dst, (bitconvert FR64:$src))],
1452 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1454 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1455 "vmovq\t{$src, $dst|$dst, $src}",
1456 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1457 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1458 EVEX_CD8<64, CD8VT1>;
1460 // Move Int Doubleword to Single Scalar
1462 let isCodeGenOnly = 1 in {
1463 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1464 "vmovd\t{$src, $dst|$dst, $src}",
1465 [(set FR32X:$dst, (bitconvert GR32:$src))],
1466 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1468 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1469 "vmovd\t{$src, $dst|$dst, $src}",
1470 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1471 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1474 // Move doubleword from xmm register to r/m32
1476 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1477 "vmovd\t{$src, $dst|$dst, $src}",
1478 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1479 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1481 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1482 (ins i32mem:$dst, VR128X:$src),
1483 "vmovd\t{$src, $dst|$dst, $src}",
1484 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1485 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1486 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1488 // Move quadword from xmm1 register to r/m64
1490 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1491 "vmovq\t{$src, $dst|$dst, $src}",
1492 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1494 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1495 Requires<[HasAVX512, In64BitMode]>;
1497 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1498 (ins i64mem:$dst, VR128X:$src),
1499 "vmovq\t{$src, $dst|$dst, $src}",
1500 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1501 addr:$dst)], IIC_SSE_MOVDQ>,
1502 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1503 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1505 // Move Scalar Single to Double Int
1507 let isCodeGenOnly = 1 in {
1508 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1510 "vmovd\t{$src, $dst|$dst, $src}",
1511 [(set GR32:$dst, (bitconvert FR32X:$src))],
1512 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1513 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1514 (ins i32mem:$dst, FR32X:$src),
1515 "vmovd\t{$src, $dst|$dst, $src}",
1516 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1517 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1520 // Move Quadword Int to Packed Quadword Int
1522 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1524 "vmovq\t{$src, $dst|$dst, $src}",
1526 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1527 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1529 //===----------------------------------------------------------------------===//
1530 // AVX-512 MOVSS, MOVSD
1531 //===----------------------------------------------------------------------===//
1533 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1534 SDNode OpNode, ValueType vt,
1535 X86MemOperand x86memop, PatFrag mem_pat> {
1536 let hasSideEffects = 0 in {
1537 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1538 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1539 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1540 (scalar_to_vector RC:$src2))))],
1541 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1542 let Constraints = "$src1 = $dst" in
1543 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1544 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1546 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1547 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1548 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1549 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1550 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1552 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1553 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1554 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1556 } //hasSideEffects = 0
1559 let ExeDomain = SSEPackedSingle in
1560 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1561 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1563 let ExeDomain = SSEPackedDouble in
1564 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1565 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1567 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1568 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1569 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1571 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1572 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1573 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1575 // For the disassembler
1576 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1577 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1578 (ins VR128X:$src1, FR32X:$src2),
1579 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1581 XS, EVEX_4V, VEX_LIG;
1582 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1583 (ins VR128X:$src1, FR64X:$src2),
1584 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1586 XD, EVEX_4V, VEX_LIG, VEX_W;
1589 let Predicates = [HasAVX512] in {
1590 let AddedComplexity = 15 in {
1591 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1592 // MOVS{S,D} to the lower bits.
1593 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1594 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1595 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1596 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1597 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1598 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1599 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1600 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1602 // Move low f32 and clear high bits.
1603 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1604 (SUBREG_TO_REG (i32 0),
1605 (VMOVSSZrr (v4f32 (V_SET0)),
1606 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1607 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1608 (SUBREG_TO_REG (i32 0),
1609 (VMOVSSZrr (v4i32 (V_SET0)),
1610 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1613 let AddedComplexity = 20 in {
1614 // MOVSSrm zeros the high parts of the register; represent this
1615 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1616 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1617 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1618 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1619 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1620 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1621 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1623 // MOVSDrm zeros the high parts of the register; represent this
1624 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1625 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1626 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1627 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1628 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1629 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1630 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1631 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1632 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1633 def : Pat<(v2f64 (X86vzload addr:$src)),
1634 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1636 // Represent the same patterns above but in the form they appear for
1638 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1639 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1640 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1641 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1642 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1643 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1644 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1645 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1646 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1648 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1649 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1650 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1651 FR32X:$src)), sub_xmm)>;
1652 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1653 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1654 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1655 FR64X:$src)), sub_xmm)>;
1656 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1657 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1658 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1660 // Move low f64 and clear high bits.
1661 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1662 (SUBREG_TO_REG (i32 0),
1663 (VMOVSDZrr (v2f64 (V_SET0)),
1664 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1666 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1667 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1668 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1670 // Extract and store.
1671 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1673 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1674 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1676 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1678 // Shuffle with VMOVSS
1679 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1680 (VMOVSSZrr (v4i32 VR128X:$src1),
1681 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1682 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1683 (VMOVSSZrr (v4f32 VR128X:$src1),
1684 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1687 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1688 (SUBREG_TO_REG (i32 0),
1689 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1690 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1692 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1693 (SUBREG_TO_REG (i32 0),
1694 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1695 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1698 // Shuffle with VMOVSD
1699 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1700 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1701 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1702 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1703 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1704 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1705 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1706 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1709 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1710 (SUBREG_TO_REG (i32 0),
1711 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1712 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1714 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1715 (SUBREG_TO_REG (i32 0),
1716 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1717 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1720 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1721 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1722 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1723 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1724 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1725 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1726 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1727 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1730 let AddedComplexity = 15 in
1731 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1733 "vmovq\t{$src, $dst|$dst, $src}",
1734 [(set VR128X:$dst, (v2i64 (X86vzmovl
1735 (v2i64 VR128X:$src))))],
1736 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1738 let AddedComplexity = 20 in
1739 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1741 "vmovq\t{$src, $dst|$dst, $src}",
1742 [(set VR128X:$dst, (v2i64 (X86vzmovl
1743 (loadv2i64 addr:$src))))],
1744 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1745 EVEX_CD8<8, CD8VT8>;
1747 let Predicates = [HasAVX512] in {
1748 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1749 let AddedComplexity = 20 in {
1750 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1751 (VMOVDI2PDIZrm addr:$src)>;
1752 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1753 (VMOV64toPQIZrr GR64:$src)>;
1754 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1755 (VMOVDI2PDIZrr GR32:$src)>;
1757 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1758 (VMOVDI2PDIZrm addr:$src)>;
1759 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1760 (VMOVDI2PDIZrm addr:$src)>;
1761 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1762 (VMOVZPQILo2PQIZrm addr:$src)>;
1763 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1764 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1765 def : Pat<(v2i64 (X86vzload addr:$src)),
1766 (VMOVZPQILo2PQIZrm addr:$src)>;
1769 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1770 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1771 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1772 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1773 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1774 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1775 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1778 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1779 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1781 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1782 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1784 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1785 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1787 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1788 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1790 //===----------------------------------------------------------------------===//
1791 // AVX-512 - Non-temporals
1792 //===----------------------------------------------------------------------===//
1794 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
1796 "vmovntdqa\t{$src, $dst|$dst, $src}",
1798 (int_x86_avx512_movntdqa addr:$src))]>,
1801 //===----------------------------------------------------------------------===//
1802 // AVX-512 - Integer arithmetic
1804 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1805 ValueType OpVT, RegisterClass KRC,
1806 RegisterClass RC, PatFrag memop_frag,
1807 X86MemOperand x86memop, PatFrag scalar_mfrag,
1808 X86MemOperand x86scalar_mop, string BrdcstStr,
1809 OpndItins itins, bit IsCommutable = 0> {
1810 let isCommutable = IsCommutable in
1811 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1812 (ins RC:$src1, RC:$src2),
1813 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1814 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1816 let AddedComplexity = 30 in {
1817 let Constraints = "$src0 = $dst" in
1818 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1819 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
1820 !strconcat(OpcodeStr,
1821 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1822 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1823 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1825 itins.rr>, EVEX_4V, EVEX_K;
1826 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1827 (ins KRC:$mask, RC:$src1, RC:$src2),
1828 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1829 "|$dst {${mask}} {z}, $src1, $src2}"),
1830 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1831 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1832 (OpVT immAllZerosV))))],
1833 itins.rr>, EVEX_4V, EVEX_KZ;
1836 let mayLoad = 1 in {
1837 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1838 (ins RC:$src1, x86memop:$src2),
1839 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1840 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1842 let AddedComplexity = 30 in {
1843 let Constraints = "$src0 = $dst" in
1844 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1845 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
1846 !strconcat(OpcodeStr,
1847 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1848 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1849 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1851 itins.rm>, EVEX_4V, EVEX_K;
1852 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1853 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1854 !strconcat(OpcodeStr,
1855 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1856 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1857 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1858 (OpVT immAllZerosV))))],
1859 itins.rm>, EVEX_4V, EVEX_KZ;
1861 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1862 (ins RC:$src1, x86scalar_mop:$src2),
1863 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1864 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1865 [(set RC:$dst, (OpNode RC:$src1,
1866 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1867 itins.rm>, EVEX_4V, EVEX_B;
1868 let AddedComplexity = 30 in {
1869 let Constraints = "$src0 = $dst" in
1870 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1871 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1872 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1873 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1875 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1876 (OpNode (OpVT RC:$src1),
1877 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1879 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1880 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1881 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1882 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1883 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1885 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1886 (OpNode (OpVT RC:$src1),
1887 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1888 (OpVT immAllZerosV))))],
1889 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1894 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
1895 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
1896 PatFrag memop_frag, X86MemOperand x86memop,
1897 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
1898 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
1899 let isCommutable = IsCommutable in
1901 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1902 (ins RC:$src1, RC:$src2),
1903 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1905 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1906 (ins KRC:$mask, RC:$src1, RC:$src2),
1907 !strconcat(OpcodeStr,
1908 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1909 [], itins.rr>, EVEX_4V, EVEX_K;
1910 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1911 (ins KRC:$mask, RC:$src1, RC:$src2),
1912 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1913 "|$dst {${mask}} {z}, $src1, $src2}"),
1914 [], itins.rr>, EVEX_4V, EVEX_KZ;
1916 let mayLoad = 1 in {
1917 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1918 (ins RC:$src1, x86memop:$src2),
1919 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1921 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1922 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1923 !strconcat(OpcodeStr,
1924 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1925 [], itins.rm>, EVEX_4V, EVEX_K;
1926 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1927 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1928 !strconcat(OpcodeStr,
1929 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1930 [], itins.rm>, EVEX_4V, EVEX_KZ;
1931 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1932 (ins RC:$src1, x86scalar_mop:$src2),
1933 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1934 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1935 [], itins.rm>, EVEX_4V, EVEX_B;
1936 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1937 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1938 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1939 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1941 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1942 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1943 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1944 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1945 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1947 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1951 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
1952 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1953 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1955 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
1956 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1957 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1959 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
1960 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1961 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1963 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
1964 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1965 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1967 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
1968 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1969 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1971 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
1972 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1973 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
1974 EVEX_CD8<64, CD8VF>, VEX_W;
1976 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
1977 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1978 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
1980 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1981 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1983 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1984 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1985 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1986 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1987 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1988 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1990 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
1991 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1992 SSE_INTALU_ITINS_P, 1>,
1993 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1994 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
1995 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1996 SSE_INTALU_ITINS_P, 0>,
1997 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1999 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2000 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2001 SSE_INTALU_ITINS_P, 1>,
2002 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2003 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2004 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2005 SSE_INTALU_ITINS_P, 0>,
2006 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2008 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2009 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2010 SSE_INTALU_ITINS_P, 1>,
2011 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2012 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2013 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2014 SSE_INTALU_ITINS_P, 0>,
2015 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2017 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2018 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2019 SSE_INTALU_ITINS_P, 1>,
2020 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2021 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2022 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2023 SSE_INTALU_ITINS_P, 0>,
2024 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2026 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2027 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2028 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2029 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2030 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2031 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2032 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2033 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2034 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2035 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2036 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2037 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2038 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2039 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2040 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2041 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2042 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2043 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2044 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2045 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2046 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2047 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2048 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2049 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2050 //===----------------------------------------------------------------------===//
2051 // AVX-512 - Unpack Instructions
2052 //===----------------------------------------------------------------------===//
2054 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2055 PatFrag mem_frag, RegisterClass RC,
2056 X86MemOperand x86memop, string asm,
2058 def rr : AVX512PI<opc, MRMSrcReg,
2059 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2061 (vt (OpNode RC:$src1, RC:$src2)))],
2063 def rm : AVX512PI<opc, MRMSrcMem,
2064 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2066 (vt (OpNode RC:$src1,
2067 (bitconvert (mem_frag addr:$src2)))))],
2071 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2072 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2073 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2074 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2075 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2076 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2077 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2078 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2079 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2080 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2081 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2082 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2084 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2085 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2086 X86MemOperand x86memop> {
2087 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2088 (ins RC:$src1, RC:$src2),
2089 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2090 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2091 IIC_SSE_UNPCK>, EVEX_4V;
2092 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2093 (ins RC:$src1, x86memop:$src2),
2094 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2095 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2096 (bitconvert (memop_frag addr:$src2)))))],
2097 IIC_SSE_UNPCK>, EVEX_4V;
2099 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2100 VR512, memopv16i32, i512mem>, EVEX_V512,
2101 EVEX_CD8<32, CD8VF>;
2102 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2103 VR512, memopv8i64, i512mem>, EVEX_V512,
2104 VEX_W, EVEX_CD8<64, CD8VF>;
2105 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2106 VR512, memopv16i32, i512mem>, EVEX_V512,
2107 EVEX_CD8<32, CD8VF>;
2108 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2109 VR512, memopv8i64, i512mem>, EVEX_V512,
2110 VEX_W, EVEX_CD8<64, CD8VF>;
2111 //===----------------------------------------------------------------------===//
2115 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2116 SDNode OpNode, PatFrag mem_frag,
2117 X86MemOperand x86memop, ValueType OpVT> {
2118 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2119 (ins RC:$src1, i8imm:$src2),
2120 !strconcat(OpcodeStr,
2121 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2123 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2125 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2126 (ins x86memop:$src1, i8imm:$src2),
2127 !strconcat(OpcodeStr,
2128 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2130 (OpVT (OpNode (mem_frag addr:$src1),
2131 (i8 imm:$src2))))]>, EVEX;
2134 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2135 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2137 let ExeDomain = SSEPackedSingle in
2138 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2139 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2140 EVEX_CD8<32, CD8VF>;
2141 let ExeDomain = SSEPackedDouble in
2142 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2143 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2144 VEX_W, EVEX_CD8<32, CD8VF>;
2146 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2147 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2148 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2149 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2151 //===----------------------------------------------------------------------===//
2152 // AVX-512 Logical Instructions
2153 //===----------------------------------------------------------------------===//
2155 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2156 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2157 EVEX_V512, EVEX_CD8<32, CD8VF>;
2158 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2159 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2160 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2161 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2162 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2163 EVEX_V512, EVEX_CD8<32, CD8VF>;
2164 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2165 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2166 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2167 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2168 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2169 EVEX_V512, EVEX_CD8<32, CD8VF>;
2170 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2171 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2172 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2173 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2174 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2175 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2176 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2177 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2178 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2180 //===----------------------------------------------------------------------===//
2181 // AVX-512 FP arithmetic
2182 //===----------------------------------------------------------------------===//
2184 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2186 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2187 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2188 EVEX_CD8<32, CD8VT1>;
2189 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2190 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2191 EVEX_CD8<64, CD8VT1>;
2194 let isCommutable = 1 in {
2195 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2196 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2197 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2198 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2200 let isCommutable = 0 in {
2201 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2202 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2205 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2207 RegisterClass RC, ValueType vt,
2208 X86MemOperand x86memop, PatFrag mem_frag,
2209 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2211 Domain d, OpndItins itins, bit commutable> {
2212 let isCommutable = commutable in {
2213 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2214 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2215 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2218 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2219 !strconcat(OpcodeStr,
2220 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2221 [], itins.rr, d>, EVEX_4V, EVEX_K;
2223 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2224 !strconcat(OpcodeStr,
2225 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2226 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2229 let mayLoad = 1 in {
2230 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2231 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2232 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2233 itins.rm, d>, EVEX_4V;
2235 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2236 (ins RC:$src1, x86scalar_mop:$src2),
2237 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2238 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2239 [(set RC:$dst, (OpNode RC:$src1,
2240 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2241 itins.rm, d>, EVEX_4V, EVEX_B;
2243 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2244 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2245 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2246 [], itins.rm, d>, EVEX_4V, EVEX_K;
2248 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2249 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2250 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2251 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2253 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2254 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2255 " \t{${src2}", BrdcstStr,
2256 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2257 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2259 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2260 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2261 " \t{${src2}", BrdcstStr,
2262 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2264 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2268 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2269 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2270 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2272 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2273 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2274 SSE_ALU_ITINS_P.d, 1>,
2275 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2277 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2278 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2279 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2280 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2281 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2282 SSE_ALU_ITINS_P.d, 1>,
2283 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2285 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2286 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2287 SSE_ALU_ITINS_P.s, 1>,
2288 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2289 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2290 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2291 SSE_ALU_ITINS_P.s, 1>,
2292 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2294 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2295 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2296 SSE_ALU_ITINS_P.d, 1>,
2297 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2298 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2299 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2300 SSE_ALU_ITINS_P.d, 1>,
2301 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2303 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2304 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2305 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2306 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2307 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2308 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2310 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2311 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2312 SSE_ALU_ITINS_P.d, 0>,
2313 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2314 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2315 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2316 SSE_ALU_ITINS_P.d, 0>,
2317 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2319 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2320 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2321 (i16 -1), FROUND_CURRENT)),
2322 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2324 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2325 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2326 (i8 -1), FROUND_CURRENT)),
2327 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2329 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2330 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2331 (i16 -1), FROUND_CURRENT)),
2332 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2334 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2335 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2336 (i8 -1), FROUND_CURRENT)),
2337 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2338 //===----------------------------------------------------------------------===//
2339 // AVX-512 VPTESTM instructions
2340 //===----------------------------------------------------------------------===//
2342 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2343 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2344 SDNode OpNode, ValueType vt> {
2345 def rr : AVX512PI<opc, MRMSrcReg,
2346 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2347 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2348 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2349 SSEPackedInt>, EVEX_4V;
2350 def rm : AVX512PI<opc, MRMSrcMem,
2351 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2352 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2353 [(set KRC:$dst, (OpNode (vt RC:$src1),
2354 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2357 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2358 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2359 EVEX_CD8<32, CD8VF>;
2360 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2361 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2362 EVEX_CD8<64, CD8VF>;
2364 let Predicates = [HasCDI] in {
2365 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2366 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2367 EVEX_CD8<32, CD8VF>;
2368 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2369 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2370 EVEX_CD8<64, CD8VF>;
2373 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2374 (v16i32 VR512:$src2), (i16 -1))),
2375 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2377 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2378 (v8i64 VR512:$src2), (i8 -1))),
2379 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2380 //===----------------------------------------------------------------------===//
2381 // AVX-512 Shift instructions
2382 //===----------------------------------------------------------------------===//
2383 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2384 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2385 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2386 RegisterClass KRC> {
2387 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2388 (ins RC:$src1, i8imm:$src2),
2389 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2390 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2391 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2392 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2393 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2394 !strconcat(OpcodeStr,
2395 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2396 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2397 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2398 (ins x86memop:$src1, i8imm:$src2),
2399 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2400 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2401 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2402 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2403 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2404 !strconcat(OpcodeStr,
2405 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2406 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2409 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2410 RegisterClass RC, ValueType vt, ValueType SrcVT,
2411 PatFrag bc_frag, RegisterClass KRC> {
2412 // src2 is always 128-bit
2413 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2414 (ins RC:$src1, VR128X:$src2),
2415 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2416 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2417 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2418 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2419 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2420 !strconcat(OpcodeStr,
2421 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2422 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2423 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2424 (ins RC:$src1, i128mem:$src2),
2425 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2426 [(set RC:$dst, (vt (OpNode RC:$src1,
2427 (bc_frag (memopv2i64 addr:$src2)))))],
2428 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2429 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2430 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2431 !strconcat(OpcodeStr,
2432 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2433 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2436 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2437 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2438 EVEX_V512, EVEX_CD8<32, CD8VF>;
2439 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2440 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2441 EVEX_CD8<32, CD8VQ>;
2443 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2444 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2445 EVEX_CD8<64, CD8VF>, VEX_W;
2446 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2447 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2448 EVEX_CD8<64, CD8VQ>, VEX_W;
2450 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2451 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2452 EVEX_CD8<32, CD8VF>;
2453 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2454 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2455 EVEX_CD8<32, CD8VQ>;
2457 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2458 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2459 EVEX_CD8<64, CD8VF>, VEX_W;
2460 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2461 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2462 EVEX_CD8<64, CD8VQ>, VEX_W;
2464 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2465 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2466 EVEX_V512, EVEX_CD8<32, CD8VF>;
2467 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2468 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2469 EVEX_CD8<32, CD8VQ>;
2471 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2472 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2473 EVEX_CD8<64, CD8VF>, VEX_W;
2474 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2475 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2476 EVEX_CD8<64, CD8VQ>, VEX_W;
2478 //===-------------------------------------------------------------------===//
2479 // Variable Bit Shifts
2480 //===-------------------------------------------------------------------===//
2481 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2482 RegisterClass RC, ValueType vt,
2483 X86MemOperand x86memop, PatFrag mem_frag> {
2484 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2485 (ins RC:$src1, RC:$src2),
2486 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2488 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2490 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2491 (ins RC:$src1, x86memop:$src2),
2492 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2494 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2498 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2499 i512mem, memopv16i32>, EVEX_V512,
2500 EVEX_CD8<32, CD8VF>;
2501 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2502 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2503 EVEX_CD8<64, CD8VF>;
2504 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2505 i512mem, memopv16i32>, EVEX_V512,
2506 EVEX_CD8<32, CD8VF>;
2507 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2508 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2509 EVEX_CD8<64, CD8VF>;
2510 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2511 i512mem, memopv16i32>, EVEX_V512,
2512 EVEX_CD8<32, CD8VF>;
2513 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2514 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2515 EVEX_CD8<64, CD8VF>;
2517 //===----------------------------------------------------------------------===//
2518 // AVX-512 - MOVDDUP
2519 //===----------------------------------------------------------------------===//
2521 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2522 X86MemOperand x86memop, PatFrag memop_frag> {
2523 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2524 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2525 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2526 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2527 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2529 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2532 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2533 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2534 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2535 (VMOVDDUPZrm addr:$src)>;
2537 //===---------------------------------------------------------------------===//
2538 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2539 //===---------------------------------------------------------------------===//
2540 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2541 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2542 X86MemOperand x86memop> {
2543 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2544 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2545 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2547 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2548 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2549 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2552 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2553 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2554 EVEX_CD8<32, CD8VF>;
2555 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2556 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2557 EVEX_CD8<32, CD8VF>;
2559 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2560 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2561 (VMOVSHDUPZrm addr:$src)>;
2562 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2563 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2564 (VMOVSLDUPZrm addr:$src)>;
2566 //===----------------------------------------------------------------------===//
2567 // Move Low to High and High to Low packed FP Instructions
2568 //===----------------------------------------------------------------------===//
2569 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2570 (ins VR128X:$src1, VR128X:$src2),
2571 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2572 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2573 IIC_SSE_MOV_LH>, EVEX_4V;
2574 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2575 (ins VR128X:$src1, VR128X:$src2),
2576 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2577 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2578 IIC_SSE_MOV_LH>, EVEX_4V;
2580 let Predicates = [HasAVX512] in {
2582 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2583 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2584 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2585 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2588 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2589 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2592 //===----------------------------------------------------------------------===//
2593 // FMA - Fused Multiply Operations
2595 let Constraints = "$src1 = $dst" in {
2596 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2597 RegisterClass RC, X86MemOperand x86memop,
2598 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2599 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2600 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2601 (ins RC:$src1, RC:$src2, RC:$src3),
2602 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2603 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2606 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2607 (ins RC:$src1, RC:$src2, x86memop:$src3),
2608 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2609 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2610 (mem_frag addr:$src3))))]>;
2611 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2612 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2613 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2614 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2615 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2616 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2618 } // Constraints = "$src1 = $dst"
2620 let ExeDomain = SSEPackedSingle in {
2621 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2622 memopv16f32, f32mem, loadf32, "{1to16}",
2623 X86Fmadd, v16f32>, EVEX_V512,
2624 EVEX_CD8<32, CD8VF>;
2625 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2626 memopv16f32, f32mem, loadf32, "{1to16}",
2627 X86Fmsub, v16f32>, EVEX_V512,
2628 EVEX_CD8<32, CD8VF>;
2629 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2630 memopv16f32, f32mem, loadf32, "{1to16}",
2631 X86Fmaddsub, v16f32>,
2632 EVEX_V512, EVEX_CD8<32, CD8VF>;
2633 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2634 memopv16f32, f32mem, loadf32, "{1to16}",
2635 X86Fmsubadd, v16f32>,
2636 EVEX_V512, EVEX_CD8<32, CD8VF>;
2637 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2638 memopv16f32, f32mem, loadf32, "{1to16}",
2639 X86Fnmadd, v16f32>, EVEX_V512,
2640 EVEX_CD8<32, CD8VF>;
2641 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2642 memopv16f32, f32mem, loadf32, "{1to16}",
2643 X86Fnmsub, v16f32>, EVEX_V512,
2644 EVEX_CD8<32, CD8VF>;
2646 let ExeDomain = SSEPackedDouble in {
2647 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2648 memopv8f64, f64mem, loadf64, "{1to8}",
2649 X86Fmadd, v8f64>, EVEX_V512,
2650 VEX_W, EVEX_CD8<64, CD8VF>;
2651 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2652 memopv8f64, f64mem, loadf64, "{1to8}",
2653 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2654 EVEX_CD8<64, CD8VF>;
2655 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2656 memopv8f64, f64mem, loadf64, "{1to8}",
2657 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2658 EVEX_CD8<64, CD8VF>;
2659 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2660 memopv8f64, f64mem, loadf64, "{1to8}",
2661 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2662 EVEX_CD8<64, CD8VF>;
2663 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2664 memopv8f64, f64mem, loadf64, "{1to8}",
2665 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2666 EVEX_CD8<64, CD8VF>;
2667 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2668 memopv8f64, f64mem, loadf64, "{1to8}",
2669 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2670 EVEX_CD8<64, CD8VF>;
2673 let Constraints = "$src1 = $dst" in {
2674 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2675 RegisterClass RC, X86MemOperand x86memop,
2676 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2677 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2679 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2680 (ins RC:$src1, RC:$src3, x86memop:$src2),
2681 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2682 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2683 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2684 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2685 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2686 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2687 [(set RC:$dst, (OpNode RC:$src1,
2688 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2690 } // Constraints = "$src1 = $dst"
2693 let ExeDomain = SSEPackedSingle in {
2694 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2695 memopv16f32, f32mem, loadf32, "{1to16}",
2696 X86Fmadd, v16f32>, EVEX_V512,
2697 EVEX_CD8<32, CD8VF>;
2698 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2699 memopv16f32, f32mem, loadf32, "{1to16}",
2700 X86Fmsub, v16f32>, EVEX_V512,
2701 EVEX_CD8<32, CD8VF>;
2702 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2703 memopv16f32, f32mem, loadf32, "{1to16}",
2704 X86Fmaddsub, v16f32>,
2705 EVEX_V512, EVEX_CD8<32, CD8VF>;
2706 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2707 memopv16f32, f32mem, loadf32, "{1to16}",
2708 X86Fmsubadd, v16f32>,
2709 EVEX_V512, EVEX_CD8<32, CD8VF>;
2710 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2711 memopv16f32, f32mem, loadf32, "{1to16}",
2712 X86Fnmadd, v16f32>, EVEX_V512,
2713 EVEX_CD8<32, CD8VF>;
2714 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2715 memopv16f32, f32mem, loadf32, "{1to16}",
2716 X86Fnmsub, v16f32>, EVEX_V512,
2717 EVEX_CD8<32, CD8VF>;
2719 let ExeDomain = SSEPackedDouble in {
2720 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2721 memopv8f64, f64mem, loadf64, "{1to8}",
2722 X86Fmadd, v8f64>, EVEX_V512,
2723 VEX_W, EVEX_CD8<64, CD8VF>;
2724 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2725 memopv8f64, f64mem, loadf64, "{1to8}",
2726 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2727 EVEX_CD8<64, CD8VF>;
2728 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2729 memopv8f64, f64mem, loadf64, "{1to8}",
2730 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2731 EVEX_CD8<64, CD8VF>;
2732 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2733 memopv8f64, f64mem, loadf64, "{1to8}",
2734 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2735 EVEX_CD8<64, CD8VF>;
2736 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2737 memopv8f64, f64mem, loadf64, "{1to8}",
2738 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2739 EVEX_CD8<64, CD8VF>;
2740 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2741 memopv8f64, f64mem, loadf64, "{1to8}",
2742 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2743 EVEX_CD8<64, CD8VF>;
2747 let Constraints = "$src1 = $dst" in {
2748 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2749 RegisterClass RC, ValueType OpVT,
2750 X86MemOperand x86memop, Operand memop,
2752 let isCommutable = 1 in
2753 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2754 (ins RC:$src1, RC:$src2, RC:$src3),
2755 !strconcat(OpcodeStr,
2756 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2758 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2760 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2761 (ins RC:$src1, RC:$src2, f128mem:$src3),
2762 !strconcat(OpcodeStr,
2763 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2765 (OpVT (OpNode RC:$src2, RC:$src1,
2766 (mem_frag addr:$src3))))]>;
2769 } // Constraints = "$src1 = $dst"
2771 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2772 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2773 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2774 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2775 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2776 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2777 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2778 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2779 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2780 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2781 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2782 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2783 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2784 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2785 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2786 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2788 //===----------------------------------------------------------------------===//
2789 // AVX-512 Scalar convert from sign integer to float/double
2790 //===----------------------------------------------------------------------===//
2792 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2793 X86MemOperand x86memop, string asm> {
2794 let hasSideEffects = 0 in {
2795 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2796 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2799 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2800 (ins DstRC:$src1, x86memop:$src),
2801 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2803 } // hasSideEffects = 0
2805 let Predicates = [HasAVX512] in {
2806 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2807 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2808 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2809 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2810 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2811 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2812 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2813 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2815 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2816 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2817 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2818 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2819 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2820 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2821 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2822 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2824 def : Pat<(f32 (sint_to_fp GR32:$src)),
2825 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2826 def : Pat<(f32 (sint_to_fp GR64:$src)),
2827 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2828 def : Pat<(f64 (sint_to_fp GR32:$src)),
2829 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2830 def : Pat<(f64 (sint_to_fp GR64:$src)),
2831 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2833 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2834 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2835 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2836 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2837 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2838 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2839 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2840 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2842 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2843 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2844 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2845 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2846 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2847 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2848 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2849 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2851 def : Pat<(f32 (uint_to_fp GR32:$src)),
2852 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2853 def : Pat<(f32 (uint_to_fp GR64:$src)),
2854 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2855 def : Pat<(f64 (uint_to_fp GR32:$src)),
2856 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2857 def : Pat<(f64 (uint_to_fp GR64:$src)),
2858 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2861 //===----------------------------------------------------------------------===//
2862 // AVX-512 Scalar convert from float/double to integer
2863 //===----------------------------------------------------------------------===//
2864 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2865 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2867 let hasSideEffects = 0 in {
2868 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2869 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2870 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2871 Requires<[HasAVX512]>;
2873 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2874 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2875 Requires<[HasAVX512]>;
2876 } // hasSideEffects = 0
2878 let Predicates = [HasAVX512] in {
2879 // Convert float/double to signed/unsigned int 32/64
2880 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2881 ssmem, sse_load_f32, "cvtss2si">,
2882 XS, EVEX_CD8<32, CD8VT1>;
2883 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2884 ssmem, sse_load_f32, "cvtss2si">,
2885 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2886 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2887 ssmem, sse_load_f32, "cvtss2usi">,
2888 XS, EVEX_CD8<32, CD8VT1>;
2889 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2890 int_x86_avx512_cvtss2usi64, ssmem,
2891 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2892 EVEX_CD8<32, CD8VT1>;
2893 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2894 sdmem, sse_load_f64, "cvtsd2si">,
2895 XD, EVEX_CD8<64, CD8VT1>;
2896 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2897 sdmem, sse_load_f64, "cvtsd2si">,
2898 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2899 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2900 sdmem, sse_load_f64, "cvtsd2usi">,
2901 XD, EVEX_CD8<64, CD8VT1>;
2902 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2903 int_x86_avx512_cvtsd2usi64, sdmem,
2904 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2905 EVEX_CD8<64, CD8VT1>;
2907 let isCodeGenOnly = 1 in {
2908 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2909 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2910 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2911 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2912 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2913 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2914 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2915 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2916 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2917 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2918 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2919 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2921 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2922 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2923 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2924 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2925 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2926 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2927 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2928 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2929 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2930 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2931 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2932 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2933 } // isCodeGenOnly = 1
2935 // Convert float/double to signed/unsigned int 32/64 with truncation
2936 let isCodeGenOnly = 1 in {
2937 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2938 ssmem, sse_load_f32, "cvttss2si">,
2939 XS, EVEX_CD8<32, CD8VT1>;
2940 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2941 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2942 "cvttss2si">, XS, VEX_W,
2943 EVEX_CD8<32, CD8VT1>;
2944 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2945 sdmem, sse_load_f64, "cvttsd2si">, XD,
2946 EVEX_CD8<64, CD8VT1>;
2947 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2948 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2949 "cvttsd2si">, XD, VEX_W,
2950 EVEX_CD8<64, CD8VT1>;
2951 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2952 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2953 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2954 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2955 int_x86_avx512_cvttss2usi64, ssmem,
2956 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2957 EVEX_CD8<32, CD8VT1>;
2958 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2959 int_x86_avx512_cvttsd2usi,
2960 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2961 EVEX_CD8<64, CD8VT1>;
2962 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2963 int_x86_avx512_cvttsd2usi64, sdmem,
2964 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2965 EVEX_CD8<64, CD8VT1>;
2966 } // isCodeGenOnly = 1
2968 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2969 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2971 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2972 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2973 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2974 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2975 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2976 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2979 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2980 loadf32, "cvttss2si">, XS,
2981 EVEX_CD8<32, CD8VT1>;
2982 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2983 loadf32, "cvttss2usi">, XS,
2984 EVEX_CD8<32, CD8VT1>;
2985 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2986 loadf32, "cvttss2si">, XS, VEX_W,
2987 EVEX_CD8<32, CD8VT1>;
2988 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2989 loadf32, "cvttss2usi">, XS, VEX_W,
2990 EVEX_CD8<32, CD8VT1>;
2991 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2992 loadf64, "cvttsd2si">, XD,
2993 EVEX_CD8<64, CD8VT1>;
2994 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2995 loadf64, "cvttsd2usi">, XD,
2996 EVEX_CD8<64, CD8VT1>;
2997 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2998 loadf64, "cvttsd2si">, XD, VEX_W,
2999 EVEX_CD8<64, CD8VT1>;
3000 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3001 loadf64, "cvttsd2usi">, XD, VEX_W,
3002 EVEX_CD8<64, CD8VT1>;
3004 //===----------------------------------------------------------------------===//
3005 // AVX-512 Convert form float to double and back
3006 //===----------------------------------------------------------------------===//
3007 let hasSideEffects = 0 in {
3008 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3009 (ins FR32X:$src1, FR32X:$src2),
3010 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3011 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3013 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3014 (ins FR32X:$src1, f32mem:$src2),
3015 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3016 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3017 EVEX_CD8<32, CD8VT1>;
3019 // Convert scalar double to scalar single
3020 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3021 (ins FR64X:$src1, FR64X:$src2),
3022 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3023 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3025 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3026 (ins FR64X:$src1, f64mem:$src2),
3027 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3028 []>, EVEX_4V, VEX_LIG, VEX_W,
3029 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3032 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3033 Requires<[HasAVX512]>;
3034 def : Pat<(fextend (loadf32 addr:$src)),
3035 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3037 def : Pat<(extloadf32 addr:$src),
3038 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3039 Requires<[HasAVX512, OptForSize]>;
3041 def : Pat<(extloadf32 addr:$src),
3042 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3043 Requires<[HasAVX512, OptForSpeed]>;
3045 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3046 Requires<[HasAVX512]>;
3048 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3049 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3050 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3052 let hasSideEffects = 0 in {
3053 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3054 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3056 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3057 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3058 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3059 [], d>, EVEX, EVEX_B, EVEX_RC;
3061 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3062 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3064 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3065 } // hasSideEffects = 0
3068 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3069 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3070 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3072 let hasSideEffects = 0 in {
3073 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3074 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3076 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3078 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3079 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3081 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3082 } // hasSideEffects = 0
3085 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3086 memopv8f64, f512mem, v8f32, v8f64,
3087 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3088 EVEX_CD8<64, CD8VF>;
3090 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3091 memopv4f64, f256mem, v8f64, v8f32,
3092 SSEPackedDouble>, EVEX_V512, PS,
3093 EVEX_CD8<32, CD8VH>;
3094 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3095 (VCVTPS2PDZrm addr:$src)>;
3097 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3098 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3099 (VCVTPD2PSZrr VR512:$src)>;
3101 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3102 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3103 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3105 //===----------------------------------------------------------------------===//
3106 // AVX-512 Vector convert from sign integer to float/double
3107 //===----------------------------------------------------------------------===//
3109 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3110 memopv8i64, i512mem, v16f32, v16i32,
3111 SSEPackedSingle>, EVEX_V512, PS,
3112 EVEX_CD8<32, CD8VF>;
3114 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3115 memopv4i64, i256mem, v8f64, v8i32,
3116 SSEPackedDouble>, EVEX_V512, XS,
3117 EVEX_CD8<32, CD8VH>;
3119 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3120 memopv16f32, f512mem, v16i32, v16f32,
3121 SSEPackedSingle>, EVEX_V512, XS,
3122 EVEX_CD8<32, CD8VF>;
3124 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3125 memopv8f64, f512mem, v8i32, v8f64,
3126 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3127 EVEX_CD8<64, CD8VF>;
3129 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3130 memopv16f32, f512mem, v16i32, v16f32,
3131 SSEPackedSingle>, EVEX_V512, PS,
3132 EVEX_CD8<32, CD8VF>;
3134 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3135 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3136 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3137 (VCVTTPS2UDQZrr VR512:$src)>;
3139 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3140 memopv8f64, f512mem, v8i32, v8f64,
3141 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3142 EVEX_CD8<64, CD8VF>;
3144 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3145 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3146 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3147 (VCVTTPD2UDQZrr VR512:$src)>;
3149 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3150 memopv4i64, f256mem, v8f64, v8i32,
3151 SSEPackedDouble>, EVEX_V512, XS,
3152 EVEX_CD8<32, CD8VH>;
3154 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3155 memopv16i32, f512mem, v16f32, v16i32,
3156 SSEPackedSingle>, EVEX_V512, XD,
3157 EVEX_CD8<32, CD8VF>;
3159 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3160 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3161 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3163 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3164 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3165 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3167 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3168 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3169 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3171 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3172 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3173 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3175 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3176 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3177 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3178 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3179 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3180 (VCVTDQ2PDZrr VR256X:$src)>;
3181 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3182 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3183 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3184 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3185 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3186 (VCVTUDQ2PDZrr VR256X:$src)>;
3188 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3189 RegisterClass DstRC, PatFrag mem_frag,
3190 X86MemOperand x86memop, Domain d> {
3191 let hasSideEffects = 0 in {
3192 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3193 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3195 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3196 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3197 [], d>, EVEX, EVEX_B, EVEX_RC;
3199 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3200 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3202 } // hasSideEffects = 0
3205 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3206 memopv16f32, f512mem, SSEPackedSingle>, PD,
3207 EVEX_V512, EVEX_CD8<32, CD8VF>;
3208 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3209 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3210 EVEX_V512, EVEX_CD8<64, CD8VF>;
3212 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3213 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3214 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3216 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3217 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3218 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3220 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3221 memopv16f32, f512mem, SSEPackedSingle>,
3222 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3223 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3224 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3225 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3227 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3228 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3229 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3231 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3232 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3233 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3235 let Predicates = [HasAVX512] in {
3236 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3237 (VCVTPD2PSZrm addr:$src)>;
3238 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3239 (VCVTPS2PDZrm addr:$src)>;
3242 //===----------------------------------------------------------------------===//
3243 // Half precision conversion instructions
3244 //===----------------------------------------------------------------------===//
3245 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3246 X86MemOperand x86memop> {
3247 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3248 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3250 let hasSideEffects = 0, mayLoad = 1 in
3251 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3252 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3255 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3256 X86MemOperand x86memop> {
3257 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3258 (ins srcRC:$src1, i32i8imm:$src2),
3259 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3261 let hasSideEffects = 0, mayStore = 1 in
3262 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3263 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3264 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3267 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3268 EVEX_CD8<32, CD8VH>;
3269 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3270 EVEX_CD8<32, CD8VH>;
3272 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3273 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3274 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3276 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3277 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3278 (VCVTPH2PSZrr VR256X:$src)>;
3280 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3281 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3282 "ucomiss">, PS, EVEX, VEX_LIG,
3283 EVEX_CD8<32, CD8VT1>;
3284 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3285 "ucomisd">, PD, EVEX,
3286 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3287 let Pattern = []<dag> in {
3288 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3289 "comiss">, PS, EVEX, VEX_LIG,
3290 EVEX_CD8<32, CD8VT1>;
3291 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3292 "comisd">, PD, EVEX,
3293 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3295 let isCodeGenOnly = 1 in {
3296 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3297 load, "ucomiss">, PS, EVEX, VEX_LIG,
3298 EVEX_CD8<32, CD8VT1>;
3299 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3300 load, "ucomisd">, PD, EVEX,
3301 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3303 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3304 load, "comiss">, PS, EVEX, VEX_LIG,
3305 EVEX_CD8<32, CD8VT1>;
3306 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3307 load, "comisd">, PD, EVEX,
3308 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3312 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3313 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3314 X86MemOperand x86memop> {
3315 let hasSideEffects = 0 in {
3316 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3317 (ins RC:$src1, RC:$src2),
3318 !strconcat(OpcodeStr,
3319 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3320 let mayLoad = 1 in {
3321 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3322 (ins RC:$src1, x86memop:$src2),
3323 !strconcat(OpcodeStr,
3324 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3329 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3330 EVEX_CD8<32, CD8VT1>;
3331 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3332 VEX_W, EVEX_CD8<64, CD8VT1>;
3333 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3334 EVEX_CD8<32, CD8VT1>;
3335 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3336 VEX_W, EVEX_CD8<64, CD8VT1>;
3338 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3339 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3340 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3341 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3343 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3344 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3345 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3346 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3348 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3349 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3350 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3351 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3353 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3354 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3355 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3356 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3358 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3359 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3360 RegisterClass RC, X86MemOperand x86memop,
3361 PatFrag mem_frag, ValueType OpVt> {
3362 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3363 !strconcat(OpcodeStr,
3364 " \t{$src, $dst|$dst, $src}"),
3365 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3367 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3368 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3369 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3372 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3373 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3374 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3375 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3376 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3377 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3378 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3379 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3381 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3382 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3383 (VRSQRT14PSZr VR512:$src)>;
3384 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3385 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3386 (VRSQRT14PDZr VR512:$src)>;
3388 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3389 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3390 (VRCP14PSZr VR512:$src)>;
3391 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3392 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3393 (VRCP14PDZr VR512:$src)>;
3395 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3396 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3397 X86MemOperand x86memop> {
3398 let hasSideEffects = 0, Predicates = [HasERI] in {
3399 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3400 (ins RC:$src1, RC:$src2),
3401 !strconcat(OpcodeStr,
3402 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3403 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3404 (ins RC:$src1, RC:$src2),
3405 !strconcat(OpcodeStr,
3406 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3407 []>, EVEX_4V, EVEX_B;
3408 let mayLoad = 1 in {
3409 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3410 (ins RC:$src1, x86memop:$src2),
3411 !strconcat(OpcodeStr,
3412 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3417 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3418 EVEX_CD8<32, CD8VT1>;
3419 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3420 VEX_W, EVEX_CD8<64, CD8VT1>;
3421 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3422 EVEX_CD8<32, CD8VT1>;
3423 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3424 VEX_W, EVEX_CD8<64, CD8VT1>;
3426 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3427 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3429 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3430 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3432 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3433 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3435 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3436 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3438 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3439 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3441 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3442 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3444 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3445 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3447 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3448 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3450 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3451 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3452 RegisterClass RC, X86MemOperand x86memop> {
3453 let hasSideEffects = 0, Predicates = [HasERI] in {
3454 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3455 !strconcat(OpcodeStr,
3456 " \t{$src, $dst|$dst, $src}"),
3458 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3459 !strconcat(OpcodeStr,
3460 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3462 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3463 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3467 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3468 EVEX_V512, EVEX_CD8<32, CD8VF>;
3469 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3470 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3471 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3472 EVEX_V512, EVEX_CD8<32, CD8VF>;
3473 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3474 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3476 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3477 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3478 (VRSQRT28PSZrb VR512:$src)>;
3479 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3480 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3481 (VRSQRT28PDZrb VR512:$src)>;
3483 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3484 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3485 (VRCP28PSZrb VR512:$src)>;
3486 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3487 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3488 (VRCP28PDZrb VR512:$src)>;
3490 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3491 Intrinsic V16F32Int, Intrinsic V8F64Int,
3492 OpndItins itins_s, OpndItins itins_d> {
3493 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3494 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3495 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3499 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3500 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3502 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3503 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3505 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3506 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3507 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3511 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3512 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3513 [(set VR512:$dst, (OpNode
3514 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3515 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3517 let isCodeGenOnly = 1 in {
3518 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3519 !strconcat(OpcodeStr,
3520 "ps\t{$src, $dst|$dst, $src}"),
3521 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3523 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3524 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3526 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3527 EVEX_V512, EVEX_CD8<32, CD8VF>;
3528 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3529 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3530 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3531 EVEX, EVEX_V512, VEX_W;
3532 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3533 !strconcat(OpcodeStr,
3534 "pd\t{$src, $dst|$dst, $src}"),
3535 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3536 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3537 } // isCodeGenOnly = 1
3540 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3541 Intrinsic F32Int, Intrinsic F64Int,
3542 OpndItins itins_s, OpndItins itins_d> {
3543 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3544 (ins FR32X:$src1, FR32X:$src2),
3545 !strconcat(OpcodeStr,
3546 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3547 [], itins_s.rr>, XS, EVEX_4V;
3548 let isCodeGenOnly = 1 in
3549 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3550 (ins VR128X:$src1, VR128X:$src2),
3551 !strconcat(OpcodeStr,
3552 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3554 (F32Int VR128X:$src1, VR128X:$src2))],
3555 itins_s.rr>, XS, EVEX_4V;
3556 let mayLoad = 1 in {
3557 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3558 (ins FR32X:$src1, f32mem:$src2),
3559 !strconcat(OpcodeStr,
3560 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3561 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3562 let isCodeGenOnly = 1 in
3563 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3564 (ins VR128X:$src1, ssmem:$src2),
3565 !strconcat(OpcodeStr,
3566 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3568 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3569 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3571 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3572 (ins FR64X:$src1, FR64X:$src2),
3573 !strconcat(OpcodeStr,
3574 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3576 let isCodeGenOnly = 1 in
3577 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3578 (ins VR128X:$src1, VR128X:$src2),
3579 !strconcat(OpcodeStr,
3580 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3582 (F64Int VR128X:$src1, VR128X:$src2))],
3583 itins_s.rr>, XD, EVEX_4V, VEX_W;
3584 let mayLoad = 1 in {
3585 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3586 (ins FR64X:$src1, f64mem:$src2),
3587 !strconcat(OpcodeStr,
3588 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3589 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3590 let isCodeGenOnly = 1 in
3591 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3592 (ins VR128X:$src1, sdmem:$src2),
3593 !strconcat(OpcodeStr,
3594 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3596 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3597 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3602 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3603 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3604 SSE_SQRTSS, SSE_SQRTSD>,
3605 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3606 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3607 SSE_SQRTPS, SSE_SQRTPD>;
3609 let Predicates = [HasAVX512] in {
3610 def : Pat<(f32 (fsqrt FR32X:$src)),
3611 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3612 def : Pat<(f32 (fsqrt (load addr:$src))),
3613 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3614 Requires<[OptForSize]>;
3615 def : Pat<(f64 (fsqrt FR64X:$src)),
3616 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3617 def : Pat<(f64 (fsqrt (load addr:$src))),
3618 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3619 Requires<[OptForSize]>;
3621 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3622 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3623 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3624 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3625 Requires<[OptForSize]>;
3627 def : Pat<(f32 (X86frcp FR32X:$src)),
3628 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3629 def : Pat<(f32 (X86frcp (load addr:$src))),
3630 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3631 Requires<[OptForSize]>;
3633 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3634 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3635 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3637 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3638 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3640 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3641 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3642 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3644 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3645 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3649 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3650 X86MemOperand x86memop, RegisterClass RC,
3651 PatFrag mem_frag32, PatFrag mem_frag64,
3652 Intrinsic V4F32Int, Intrinsic V2F64Int,
3654 let ExeDomain = SSEPackedSingle in {
3655 // Intrinsic operation, reg.
3656 // Vector intrinsic operation, reg
3657 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3658 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3659 !strconcat(OpcodeStr,
3660 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3661 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3663 // Vector intrinsic operation, mem
3664 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3665 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3666 !strconcat(OpcodeStr,
3667 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3669 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3670 EVEX_CD8<32, VForm>;
3671 } // ExeDomain = SSEPackedSingle
3673 let ExeDomain = SSEPackedDouble in {
3674 // Vector intrinsic operation, reg
3675 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3676 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3677 !strconcat(OpcodeStr,
3678 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3679 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3681 // Vector intrinsic operation, mem
3682 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3683 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3684 !strconcat(OpcodeStr,
3685 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3687 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3688 EVEX_CD8<64, VForm>;
3689 } // ExeDomain = SSEPackedDouble
3692 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3696 let ExeDomain = GenericDomain in {
3698 let hasSideEffects = 0 in
3699 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3700 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3701 !strconcat(OpcodeStr,
3702 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3705 // Intrinsic operation, reg.
3706 let isCodeGenOnly = 1 in
3707 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3708 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3709 !strconcat(OpcodeStr,
3710 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3711 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3713 // Intrinsic operation, mem.
3714 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3715 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3716 !strconcat(OpcodeStr,
3717 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3718 [(set VR128X:$dst, (F32Int VR128X:$src1,
3719 sse_load_f32:$src2, imm:$src3))]>,
3720 EVEX_CD8<32, CD8VT1>;
3723 let hasSideEffects = 0 in
3724 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3725 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3726 !strconcat(OpcodeStr,
3727 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3730 // Intrinsic operation, reg.
3731 let isCodeGenOnly = 1 in
3732 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3733 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3734 !strconcat(OpcodeStr,
3735 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3736 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3739 // Intrinsic operation, mem.
3740 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3741 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3742 !strconcat(OpcodeStr,
3743 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3745 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3746 VEX_W, EVEX_CD8<64, CD8VT1>;
3747 } // ExeDomain = GenericDomain
3750 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3751 X86MemOperand x86memop, RegisterClass RC,
3752 PatFrag mem_frag, Domain d> {
3753 let ExeDomain = d in {
3754 // Intrinsic operation, reg.
3755 // Vector intrinsic operation, reg
3756 def r : AVX512AIi8<opc, MRMSrcReg,
3757 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3758 !strconcat(OpcodeStr,
3759 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3762 // Vector intrinsic operation, mem
3763 def m : AVX512AIi8<opc, MRMSrcMem,
3764 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3765 !strconcat(OpcodeStr,
3766 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3772 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3773 memopv16f32, SSEPackedSingle>, EVEX_V512,
3774 EVEX_CD8<32, CD8VF>;
3776 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3777 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
3779 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3782 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3783 memopv8f64, SSEPackedDouble>, EVEX_V512,
3784 VEX_W, EVEX_CD8<64, CD8VF>;
3786 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3787 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
3789 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3791 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3792 Operand x86memop, RegisterClass RC, Domain d> {
3793 let ExeDomain = d in {
3794 def r : AVX512AIi8<opc, MRMSrcReg,
3795 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3796 !strconcat(OpcodeStr,
3797 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3800 def m : AVX512AIi8<opc, MRMSrcMem,
3801 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3802 !strconcat(OpcodeStr,
3803 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3808 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3809 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3811 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3812 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3814 def : Pat<(ffloor FR32X:$src),
3815 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3816 def : Pat<(f64 (ffloor FR64X:$src)),
3817 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3818 def : Pat<(f32 (fnearbyint FR32X:$src)),
3819 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3820 def : Pat<(f64 (fnearbyint FR64X:$src)),
3821 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3822 def : Pat<(f32 (fceil FR32X:$src)),
3823 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3824 def : Pat<(f64 (fceil FR64X:$src)),
3825 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3826 def : Pat<(f32 (frint FR32X:$src)),
3827 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3828 def : Pat<(f64 (frint FR64X:$src)),
3829 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3830 def : Pat<(f32 (ftrunc FR32X:$src)),
3831 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3832 def : Pat<(f64 (ftrunc FR64X:$src)),
3833 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3835 def : Pat<(v16f32 (ffloor VR512:$src)),
3836 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3837 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3838 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3839 def : Pat<(v16f32 (fceil VR512:$src)),
3840 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3841 def : Pat<(v16f32 (frint VR512:$src)),
3842 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3843 def : Pat<(v16f32 (ftrunc VR512:$src)),
3844 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3846 def : Pat<(v8f64 (ffloor VR512:$src)),
3847 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3848 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3849 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3850 def : Pat<(v8f64 (fceil VR512:$src)),
3851 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3852 def : Pat<(v8f64 (frint VR512:$src)),
3853 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3854 def : Pat<(v8f64 (ftrunc VR512:$src)),
3855 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3857 //-------------------------------------------------
3858 // Integer truncate and extend operations
3859 //-------------------------------------------------
3861 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3862 RegisterClass dstRC, RegisterClass srcRC,
3863 RegisterClass KRC, X86MemOperand x86memop> {
3864 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3866 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3869 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3870 (ins KRC:$mask, srcRC:$src),
3871 !strconcat(OpcodeStr,
3872 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
3875 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3876 (ins KRC:$mask, srcRC:$src),
3877 !strconcat(OpcodeStr,
3878 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3881 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3882 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3885 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
3886 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
3887 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
3891 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3892 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3893 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3894 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3895 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3896 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3897 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3898 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3899 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3900 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3901 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3902 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3903 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3904 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3905 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3906 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3907 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3908 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3909 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3910 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3911 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3912 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3913 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3914 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3915 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3916 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3917 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3918 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3919 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3920 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3922 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3923 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3924 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3925 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3926 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3928 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3929 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
3930 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3931 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
3932 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3933 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
3934 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3935 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
3938 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3939 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
3940 PatFrag mem_frag, X86MemOperand x86memop,
3941 ValueType OpVT, ValueType InVT> {
3943 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3945 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3946 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3948 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3949 (ins KRC:$mask, SrcRC:$src),
3950 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
3953 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3954 (ins KRC:$mask, SrcRC:$src),
3955 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
3958 let mayLoad = 1 in {
3959 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3960 (ins x86memop:$src),
3961 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3963 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3966 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3967 (ins KRC:$mask, x86memop:$src),
3968 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
3972 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3973 (ins KRC:$mask, x86memop:$src),
3974 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
3980 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
3981 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3983 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
3984 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3986 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
3987 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3988 EVEX_CD8<16, CD8VH>;
3989 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
3990 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3991 EVEX_CD8<16, CD8VQ>;
3992 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
3993 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3994 EVEX_CD8<32, CD8VH>;
3996 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
3997 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3999 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4000 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4002 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4003 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4004 EVEX_CD8<16, CD8VH>;
4005 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4006 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4007 EVEX_CD8<16, CD8VQ>;
4008 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4009 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4010 EVEX_CD8<32, CD8VH>;
4012 //===----------------------------------------------------------------------===//
4013 // GATHER - SCATTER Operations
4015 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4016 RegisterClass RC, X86MemOperand memop> {
4018 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4019 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4020 (ins RC:$src1, KRC:$mask, memop:$src2),
4021 !strconcat(OpcodeStr,
4022 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4026 let ExeDomain = SSEPackedDouble in {
4027 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4028 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4029 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4030 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4033 let ExeDomain = SSEPackedSingle in {
4034 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4035 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4036 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4037 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4040 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4041 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4042 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4043 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4045 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4046 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4047 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4048 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4050 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4051 RegisterClass RC, X86MemOperand memop> {
4052 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4053 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4054 (ins memop:$dst, KRC:$mask, RC:$src2),
4055 !strconcat(OpcodeStr,
4056 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4060 let ExeDomain = SSEPackedDouble in {
4061 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4062 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4063 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4064 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4067 let ExeDomain = SSEPackedSingle in {
4068 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4069 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4070 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4071 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4074 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4075 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4076 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4077 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4079 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4080 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4081 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4082 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4085 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4086 RegisterClass KRC, X86MemOperand memop> {
4087 let Predicates = [HasPFI], hasSideEffects = 1 in
4088 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4089 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4093 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4094 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4096 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4097 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4099 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4100 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4102 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4103 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4105 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4106 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4108 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4109 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4111 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4112 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4114 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4115 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4117 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4118 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4120 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4121 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4123 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4124 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4126 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4127 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4129 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4130 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4132 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4133 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4135 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4136 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4138 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4139 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4140 //===----------------------------------------------------------------------===//
4141 // VSHUFPS - VSHUFPD Operations
4143 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4144 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4146 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4147 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4148 !strconcat(OpcodeStr,
4149 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4150 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4151 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4152 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4153 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4154 (ins RC:$src1, RC:$src2, i8imm:$src3),
4155 !strconcat(OpcodeStr,
4156 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4157 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4158 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4159 EVEX_4V, Sched<[WriteShuffle]>;
4162 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4163 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4164 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4165 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4167 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4168 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4169 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4170 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4171 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4173 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4174 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4175 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4176 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4177 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4179 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4180 X86MemOperand x86memop> {
4181 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4182 (ins RC:$src1, RC:$src2, i8imm:$src3),
4183 !strconcat(OpcodeStr,
4184 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4187 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4188 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4189 !strconcat(OpcodeStr,
4190 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4193 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4194 EVEX_V512, EVEX_CD8<32, CD8VF>;
4195 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4196 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4198 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4199 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4200 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4201 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4202 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4203 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4204 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4205 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4207 // Helper fragments to match sext vXi1 to vXiY.
4208 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4209 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4211 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4212 RegisterClass KRC, RegisterClass RC,
4213 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4215 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4216 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4218 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4219 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4221 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4222 !strconcat(OpcodeStr,
4223 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4225 let mayLoad = 1 in {
4226 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4227 (ins x86memop:$src),
4228 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4230 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4231 (ins KRC:$mask, x86memop:$src),
4232 !strconcat(OpcodeStr,
4233 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4235 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4236 (ins KRC:$mask, x86memop:$src),
4237 !strconcat(OpcodeStr,
4238 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4240 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4241 (ins x86scalar_mop:$src),
4242 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4243 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4245 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4246 (ins KRC:$mask, x86scalar_mop:$src),
4247 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4248 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4249 []>, EVEX, EVEX_B, EVEX_K;
4250 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4251 (ins KRC:$mask, x86scalar_mop:$src),
4252 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4253 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4255 []>, EVEX, EVEX_B, EVEX_KZ;
4259 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4260 i512mem, i32mem, "{1to16}">, EVEX_V512,
4261 EVEX_CD8<32, CD8VF>;
4262 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4263 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4264 EVEX_CD8<64, CD8VF>;
4267 (bc_v16i32 (v16i1sextv16i32)),
4268 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4269 (VPABSDZrr VR512:$src)>;
4271 (bc_v8i64 (v8i1sextv8i64)),
4272 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4273 (VPABSQZrr VR512:$src)>;
4275 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4276 (v16i32 immAllZerosV), (i16 -1))),
4277 (VPABSDZrr VR512:$src)>;
4278 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4279 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4280 (VPABSQZrr VR512:$src)>;
4282 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4283 RegisterClass RC, RegisterClass KRC,
4284 X86MemOperand x86memop,
4285 X86MemOperand x86scalar_mop, string BrdcstStr> {
4286 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4288 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4290 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4291 (ins x86memop:$src),
4292 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4294 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4295 (ins x86scalar_mop:$src),
4296 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4297 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4299 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4300 (ins KRC:$mask, RC:$src),
4301 !strconcat(OpcodeStr,
4302 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4304 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4305 (ins KRC:$mask, x86memop:$src),
4306 !strconcat(OpcodeStr,
4307 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4309 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4310 (ins KRC:$mask, x86scalar_mop:$src),
4311 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4312 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4314 []>, EVEX, EVEX_KZ, EVEX_B;
4316 let Constraints = "$src1 = $dst" in {
4317 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4318 (ins RC:$src1, KRC:$mask, RC:$src2),
4319 !strconcat(OpcodeStr,
4320 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4322 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4323 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4324 !strconcat(OpcodeStr,
4325 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4327 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4328 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4329 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4330 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4331 []>, EVEX, EVEX_K, EVEX_B;
4335 let Predicates = [HasCDI] in {
4336 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4337 i512mem, i32mem, "{1to16}">,
4338 EVEX_V512, EVEX_CD8<32, CD8VF>;
4341 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4342 i512mem, i64mem, "{1to8}">,
4343 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4347 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4349 (VPCONFLICTDrrk VR512:$src1,
4350 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4352 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4354 (VPCONFLICTQrrk VR512:$src1,
4355 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4357 let Predicates = [HasCDI] in {
4358 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4359 i512mem, i32mem, "{1to16}">,
4360 EVEX_V512, EVEX_CD8<32, CD8VF>;
4363 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4364 i512mem, i64mem, "{1to8}">,
4365 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4369 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4371 (VPLZCNTDrrk VR512:$src1,
4372 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4374 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4376 (VPLZCNTQrrk VR512:$src1,
4377 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4379 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4380 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4381 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4383 def : Pat<(store VK1:$src, addr:$dst),
4384 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4386 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4387 (truncstore node:$val, node:$ptr), [{
4388 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4391 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4392 (MOV8mr addr:$dst, GR8:$src)>;