1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
184 string MaskingConstraint = "",
185 InstrItinClass itin = NoItinerary,
186 bit IsCommutable = 0> {
187 let isCommutable = IsCommutable in
188 def NAME: AVX512<O, F, Outs, Ins,
189 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
190 "$dst "#Round#", "#IntelSrcAsm#"}",
193 // Prefer over VMOV*rrk Pat<>
194 let AddedComplexity = 20 in
195 def NAME#k: AVX512<O, F, Outs, MaskingIns,
196 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
197 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
198 MaskingPattern, itin>,
200 // In case of the 3src subclass this is overridden with a let.
201 string Constraints = MaskingConstraint;
203 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
204 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
205 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
206 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
213 // Common base class of AVX512_maskable and AVX512_maskable_3src.
214 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
216 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
218 string AttSrcAsm, string IntelSrcAsm,
219 dag RHS, dag MaskingRHS,
220 SDNode Select = vselect, string Round = "",
221 string MaskingConstraint = "",
222 InstrItinClass itin = NoItinerary,
223 bit IsCommutable = 0> :
224 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
225 AttSrcAsm, IntelSrcAsm,
226 [(set _.RC:$dst, RHS)],
227 [(set _.RC:$dst, MaskingRHS)],
229 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
230 Round, MaskingConstraint, NoItinerary, IsCommutable>;
232 // This multiclass generates the unconditional/non-masking, the masking and
233 // the zero-masking variant of the vector instruction. In the masking case, the
234 // perserved vector elements come from a new dummy input operand tied to $dst.
235 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
236 dag Outs, dag Ins, string OpcodeStr,
237 string AttSrcAsm, string IntelSrcAsm,
238 dag RHS, string Round = "",
239 InstrItinClass itin = NoItinerary,
240 bit IsCommutable = 0> :
241 AVX512_maskable_common<O, F, _, Outs, Ins,
242 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
243 !con((ins _.KRCWM:$mask), Ins),
244 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
245 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
246 Round, "$src0 = $dst", itin, IsCommutable>;
248 // This multiclass generates the unconditional/non-masking, the masking and
249 // the zero-masking variant of the scalar instruction.
250 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
251 dag Outs, dag Ins, string OpcodeStr,
252 string AttSrcAsm, string IntelSrcAsm,
253 dag RHS, string Round = "",
254 InstrItinClass itin = NoItinerary,
255 bit IsCommutable = 0> :
256 AVX512_maskable_common<O, F, _, Outs, Ins,
257 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
258 !con((ins _.KRCWM:$mask), Ins),
259 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
260 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
261 Round, "$src0 = $dst", itin, IsCommutable>;
263 // Similar to AVX512_maskable but in this case one of the source operands
264 // ($src1) is already tied to $dst so we just use that for the preserved
265 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
267 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
268 dag Outs, dag NonTiedIns, string OpcodeStr,
269 string AttSrcAsm, string IntelSrcAsm,
271 AVX512_maskable_common<O, F, _, Outs,
272 !con((ins _.RC:$src1), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
276 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
282 string AttSrcAsm, string IntelSrcAsm,
284 AVX512_maskable_custom<O, F, Outs, Ins,
285 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
286 !con((ins _.KRCWM:$mask), Ins),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
290 // Bitcasts between 512-bit vector types. Return the original type since
291 // no instruction is needed for the conversion
292 let Predicates = [HasAVX512] in {
293 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
294 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
295 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
296 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
297 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
298 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
299 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
300 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
301 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
302 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
303 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
304 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
305 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
306 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
307 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
308 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
309 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
310 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
311 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
312 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
313 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
314 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
315 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
316 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
317 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
318 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
319 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
320 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
321 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
322 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
323 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
325 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
326 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
327 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
328 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
329 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
330 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
331 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
332 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
333 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
334 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
335 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
336 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
337 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
338 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
339 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
340 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
341 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
342 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
343 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
344 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
345 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
346 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
347 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
348 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
349 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
350 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
351 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
352 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
353 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
354 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
356 // Bitcasts between 256-bit vector types. Return the original type since
357 // no instruction is needed for the conversion
358 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
359 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
360 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
361 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
362 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
363 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
364 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
365 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
366 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
367 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
368 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
369 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
370 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
371 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
372 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
373 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
374 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
375 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
376 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
377 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
378 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
379 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
380 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
381 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
382 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
383 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
384 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
385 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
386 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
387 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
391 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
394 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
395 isPseudo = 1, Predicates = [HasAVX512] in {
396 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
397 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
400 let Predicates = [HasAVX512] in {
401 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
402 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
403 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
406 //===----------------------------------------------------------------------===//
407 // AVX-512 - VECTOR INSERT
410 multiclass vinsert_for_size_no_alt<int Opcode,
411 X86VectorVTInfo From, X86VectorVTInfo To,
412 PatFrag vinsert_insert,
413 SDNodeXForm INSERT_get_vinsert_imm> {
414 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
415 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
416 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
417 "vinsert" # From.EltTypeName # "x" # From.NumElts #
418 "\t{$src3, $src2, $src1, $dst|"
419 "$dst, $src1, $src2, $src3}",
420 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
421 (From.VT From.RC:$src2),
426 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
427 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
428 "vinsert" # From.EltTypeName # "x" # From.NumElts #
429 "\t{$src3, $src2, $src1, $dst|"
430 "$dst, $src1, $src2, $src3}",
432 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
436 multiclass vinsert_for_size<int Opcode,
437 X86VectorVTInfo From, X86VectorVTInfo To,
438 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
439 PatFrag vinsert_insert,
440 SDNodeXForm INSERT_get_vinsert_imm> :
441 vinsert_for_size_no_alt<Opcode, From, To,
442 vinsert_insert, INSERT_get_vinsert_imm> {
443 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
444 // vinserti32x4. Only add this if 64x2 and friends are not supported
445 // natively via AVX512DQ.
446 let Predicates = [NoDQI] in
447 def : Pat<(vinsert_insert:$ins
448 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
449 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
450 VR512:$src1, From.RC:$src2,
451 (INSERT_get_vinsert_imm VR512:$ins)))>;
454 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
455 ValueType EltVT64, int Opcode256> {
456 defm NAME # "32x4" : vinsert_for_size<Opcode128,
457 X86VectorVTInfo< 4, EltVT32, VR128X>,
458 X86VectorVTInfo<16, EltVT32, VR512>,
459 X86VectorVTInfo< 2, EltVT64, VR128X>,
460 X86VectorVTInfo< 8, EltVT64, VR512>,
462 INSERT_get_vinsert128_imm>;
463 let Predicates = [HasDQI] in
464 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
465 X86VectorVTInfo< 2, EltVT64, VR128X>,
466 X86VectorVTInfo< 8, EltVT64, VR512>,
468 INSERT_get_vinsert128_imm>, VEX_W;
469 defm NAME # "64x4" : vinsert_for_size<Opcode256,
470 X86VectorVTInfo< 4, EltVT64, VR256X>,
471 X86VectorVTInfo< 8, EltVT64, VR512>,
472 X86VectorVTInfo< 8, EltVT32, VR256>,
473 X86VectorVTInfo<16, EltVT32, VR512>,
475 INSERT_get_vinsert256_imm>, VEX_W;
476 let Predicates = [HasDQI] in
477 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
478 X86VectorVTInfo< 8, EltVT32, VR256X>,
479 X86VectorVTInfo<16, EltVT32, VR512>,
481 INSERT_get_vinsert256_imm>;
484 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
485 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
487 // vinsertps - insert f32 to XMM
488 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
489 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
490 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
491 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
493 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
494 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
495 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
496 [(set VR128X:$dst, (X86insertps VR128X:$src1,
497 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
498 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 VECTOR EXTRACT
504 multiclass vextract_for_size<int Opcode,
505 X86VectorVTInfo From, X86VectorVTInfo To,
506 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
507 PatFrag vextract_extract,
508 SDNodeXForm EXTRACT_get_vextract_imm> {
509 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
510 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
511 (ins VR512:$src1, u8imm:$idx),
512 "vextract" # To.EltTypeName # "x4",
513 "$idx, $src1", "$src1, $idx",
514 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
516 AVX512AIi8Base, EVEX, EVEX_V512;
518 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
519 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
520 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
521 "$dst, $src1, $src2}",
522 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
525 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
527 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
528 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
530 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
532 // A 128/256-bit subvector extract from the first 512-bit vector position is
533 // a subregister copy that needs no instruction.
534 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
536 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
538 // And for the alternative types.
539 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
541 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
543 // Intrinsic call with masking.
544 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
546 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
547 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
548 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
549 VR512:$src1, imm:$idx)>;
551 // Intrinsic call with zero-masking.
552 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
554 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
555 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
556 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
557 VR512:$src1, imm:$idx)>;
559 // Intrinsic call without masking.
560 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
562 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
563 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
564 VR512:$src1, imm:$idx)>;
567 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
568 ValueType EltVT64, int Opcode64> {
569 defm NAME # "32x4" : vextract_for_size<Opcode32,
570 X86VectorVTInfo<16, EltVT32, VR512>,
571 X86VectorVTInfo< 4, EltVT32, VR128X>,
572 X86VectorVTInfo< 8, EltVT64, VR512>,
573 X86VectorVTInfo< 2, EltVT64, VR128X>,
575 EXTRACT_get_vextract128_imm>;
576 defm NAME # "64x4" : vextract_for_size<Opcode64,
577 X86VectorVTInfo< 8, EltVT64, VR512>,
578 X86VectorVTInfo< 4, EltVT64, VR256X>,
579 X86VectorVTInfo<16, EltVT32, VR512>,
580 X86VectorVTInfo< 8, EltVT32, VR256>,
582 EXTRACT_get_vextract256_imm>, VEX_W;
585 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
586 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
588 // A 128-bit subvector insert to the first 512-bit vector position
589 // is a subregister copy that needs no instruction.
590 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
591 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
592 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
594 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
595 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
596 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
598 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
599 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
600 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
602 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
603 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
604 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
607 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
608 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
609 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
610 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
611 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
612 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
613 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
614 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
616 // vextractps - extract 32 bits from XMM
617 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
618 (ins VR128X:$src1, u8imm:$src2),
619 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
620 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
623 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
624 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
625 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
626 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
627 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
629 //===---------------------------------------------------------------------===//
632 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
633 ValueType svt, X86VectorVTInfo _> {
634 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
635 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
636 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
640 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
641 (ins _.ScalarMemOp:$src),
642 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
643 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
648 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
649 AVX512VLVectorVTInfo _> {
650 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
653 let Predicates = [HasVLX] in {
654 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
659 let ExeDomain = SSEPackedSingle in {
660 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
661 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
662 let Predicates = [HasVLX] in {
663 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
664 v4f32, v4f32x_info>, EVEX_V128,
665 EVEX_CD8<32, CD8VT1>;
669 let ExeDomain = SSEPackedDouble in {
670 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
671 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
674 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
675 // Later, we can canonize broadcast instructions before ISel phase and
676 // eliminate additional patterns on ISel.
677 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
678 // representations of source
679 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
680 X86VectorVTInfo _, RegisterClass SrcRC_v,
681 RegisterClass SrcRC_s> {
682 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
683 (!cast<Instruction>(InstName##"r")
684 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
686 let AddedComplexity = 30 in {
687 def : Pat<(_.VT (vselect _.KRCWM:$mask,
688 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
689 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
690 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
692 def : Pat<(_.VT(vselect _.KRCWM:$mask,
693 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
694 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
695 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
699 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
701 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
704 let Predicates = [HasVLX] in {
705 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
706 v8f32x_info, VR128X, FR32X>;
707 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
708 v4f32x_info, VR128X, FR32X>;
709 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
710 v4f64x_info, VR128X, FR64X>;
713 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
714 (VBROADCASTSSZm addr:$src)>;
715 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
716 (VBROADCASTSDZm addr:$src)>;
718 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
719 (VBROADCASTSSZm addr:$src)>;
720 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
721 (VBROADCASTSDZm addr:$src)>;
723 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
724 RegisterClass SrcRC> {
725 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
726 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
727 "$src", "$src", []>, T8PD, EVEX;
730 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
731 RegisterClass SrcRC, Predicate prd> {
732 let Predicates = [prd] in
733 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
734 let Predicates = [prd, HasVLX] in {
735 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
736 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
740 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
742 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
744 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
746 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
749 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
750 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
752 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
753 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
755 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
756 (VPBROADCASTDrZr GR32:$src)>;
757 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
758 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
759 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
760 (VPBROADCASTQrZr GR64:$src)>;
761 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
762 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
764 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
765 (VPBROADCASTDrZr GR32:$src)>;
766 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
767 (VPBROADCASTQrZr GR64:$src)>;
769 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
770 (v16i32 immAllZerosV), (i16 GR16:$mask))),
771 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
772 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
773 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
774 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
776 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
777 X86MemOperand x86memop, PatFrag ld_frag,
778 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
780 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
781 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
783 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
784 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
786 !strconcat(OpcodeStr,
787 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
789 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
792 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
793 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
795 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
796 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
798 !strconcat(OpcodeStr,
799 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
800 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
801 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
805 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
806 loadi32, VR512, v16i32, v4i32, VK16WM>,
807 EVEX_V512, EVEX_CD8<32, CD8VT1>;
808 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
809 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
810 EVEX_CD8<64, CD8VT1>;
812 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
813 X86MemOperand x86memop, PatFrag ld_frag,
816 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
817 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
819 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
821 !strconcat(OpcodeStr,
822 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
827 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
828 i128mem, loadv2i64, VK16WM>,
829 EVEX_V512, EVEX_CD8<32, CD8VT4>;
830 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
831 i256mem, loadv4i64, VK16WM>, VEX_W,
832 EVEX_V512, EVEX_CD8<64, CD8VT4>;
834 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
835 (VPBROADCASTDZrr VR128X:$src)>;
836 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
837 (VPBROADCASTQZrr VR128X:$src)>;
839 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
840 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
841 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
842 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
844 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
845 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
846 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
847 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
849 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
850 (VBROADCASTSSZr VR128X:$src)>;
851 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
852 (VBROADCASTSDZr VR128X:$src)>;
854 // Provide fallback in case the load node that is used in the patterns above
855 // is used by additional users, which prevents the pattern selection.
856 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
857 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
858 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
859 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
862 let Predicates = [HasAVX512] in {
863 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
865 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
866 addr:$src)), sub_ymm)>;
868 //===----------------------------------------------------------------------===//
869 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
872 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
874 let Predicates = [HasCDI] in
875 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
876 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
877 []>, EVEX, EVEX_V512;
879 let Predicates = [HasCDI, HasVLX] in {
880 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
881 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
882 []>, EVEX, EVEX_V128;
883 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
884 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
885 []>, EVEX, EVEX_V256;
889 let Predicates = [HasCDI] in {
890 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
892 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
896 //===----------------------------------------------------------------------===//
899 // -- immediate form --
900 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
902 let ExeDomain = _.ExeDomain in {
903 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
904 (ins _.RC:$src1, u8imm:$src2),
905 !strconcat(OpcodeStr,
906 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
908 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
910 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
911 (ins _.MemOp:$src1, u8imm:$src2),
912 !strconcat(OpcodeStr,
913 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
915 (_.VT (OpNode (_.LdFrag addr:$src1),
917 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
921 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
922 X86VectorVTInfo Ctrl> :
923 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
924 let ExeDomain = _.ExeDomain in {
925 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
926 (ins _.RC:$src1, _.RC:$src2),
927 !strconcat("vpermil" # _.Suffix,
928 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
930 (_.VT (X86VPermilpv _.RC:$src1,
931 (Ctrl.VT Ctrl.RC:$src2))))]>,
933 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
934 (ins _.RC:$src1, Ctrl.MemOp:$src2),
935 !strconcat("vpermil" # _.Suffix,
936 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
938 (_.VT (X86VPermilpv _.RC:$src1,
939 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
944 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
946 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
949 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
951 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
954 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
955 (VPERMILPSZri VR512:$src1, imm:$imm)>;
956 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
957 (VPERMILPDZri VR512:$src1, imm:$imm)>;
959 // -- VPERM - register form --
960 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
961 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
963 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
964 (ins RC:$src1, RC:$src2),
965 !strconcat(OpcodeStr,
966 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
968 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
970 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
971 (ins RC:$src1, x86memop:$src2),
972 !strconcat(OpcodeStr,
973 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
975 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
979 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, loadv16i32, i512mem,
980 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
981 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, loadv8i64, i512mem,
982 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
983 let ExeDomain = SSEPackedSingle in
984 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, loadv16f32, f512mem,
985 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
986 let ExeDomain = SSEPackedDouble in
987 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, loadv8f64, f512mem,
988 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
990 // -- VPERM2I - 3 source operands form --
991 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
992 PatFrag mem_frag, X86MemOperand x86memop,
993 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
994 let Constraints = "$src1 = $dst" in {
995 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
996 (ins RC:$src1, RC:$src2, RC:$src3),
997 !strconcat(OpcodeStr,
998 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1000 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
1003 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1004 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1005 !strconcat(OpcodeStr,
1006 "\t{$src3, $src2, $dst {${mask}}|"
1007 "$dst {${mask}}, $src2, $src3}"),
1008 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1009 (OpNode RC:$src1, RC:$src2,
1014 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
1015 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1016 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1017 !strconcat(OpcodeStr,
1018 "\t{$src3, $src2, $dst {${mask}} {z} |",
1019 "$dst {${mask}} {z}, $src2, $src3}"),
1020 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1021 (OpNode RC:$src1, RC:$src2,
1024 (v16i32 immAllZerosV))))))]>,
1027 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1028 (ins RC:$src1, RC:$src2, x86memop:$src3),
1029 !strconcat(OpcodeStr,
1030 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1032 (OpVT (OpNode RC:$src1, RC:$src2,
1033 (mem_frag addr:$src3))))]>, EVEX_4V;
1035 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1036 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1037 !strconcat(OpcodeStr,
1038 "\t{$src3, $src2, $dst {${mask}}|"
1039 "$dst {${mask}}, $src2, $src3}"),
1041 (OpVT (vselect KRC:$mask,
1042 (OpNode RC:$src1, RC:$src2,
1043 (mem_frag addr:$src3)),
1047 let AddedComplexity = 10 in // Prefer over the rrkz variant
1048 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1049 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1050 !strconcat(OpcodeStr,
1051 "\t{$src3, $src2, $dst {${mask}} {z}|"
1052 "$dst {${mask}} {z}, $src2, $src3}"),
1054 (OpVT (vselect KRC:$mask,
1055 (OpNode RC:$src1, RC:$src2,
1056 (mem_frag addr:$src3)),
1058 (v16i32 immAllZerosV))))))]>,
1062 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
1063 i512mem, X86VPermiv3, v16i32, VK16WM>,
1064 EVEX_V512, EVEX_CD8<32, CD8VF>;
1065 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
1066 i512mem, X86VPermiv3, v8i64, VK8WM>,
1067 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1068 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
1069 i512mem, X86VPermiv3, v16f32, VK16WM>,
1070 EVEX_V512, EVEX_CD8<32, CD8VF>;
1071 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
1072 i512mem, X86VPermiv3, v8f64, VK8WM>,
1073 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1075 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1076 PatFrag mem_frag, X86MemOperand x86memop,
1077 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1078 ValueType MaskVT, RegisterClass MRC> :
1079 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1081 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1082 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1083 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1085 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1086 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1087 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1088 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1091 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
1092 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1093 EVEX_V512, EVEX_CD8<32, CD8VF>;
1094 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
1095 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1096 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1097 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
1098 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1099 EVEX_V512, EVEX_CD8<32, CD8VF>;
1100 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
1101 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1102 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1104 //===----------------------------------------------------------------------===//
1105 // AVX-512 - BLEND using mask
1107 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1108 let ExeDomain = _.ExeDomain in {
1109 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1110 (ins _.RC:$src1, _.RC:$src2),
1111 !strconcat(OpcodeStr,
1112 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1114 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1115 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1116 !strconcat(OpcodeStr,
1117 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1118 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1119 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1120 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1121 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1122 !strconcat(OpcodeStr,
1123 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1124 []>, EVEX_4V, EVEX_KZ;
1125 let mayLoad = 1 in {
1126 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1127 (ins _.RC:$src1, _.MemOp:$src2),
1128 !strconcat(OpcodeStr,
1129 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1130 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1131 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1132 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1133 !strconcat(OpcodeStr,
1134 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1135 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1136 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1137 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1138 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1139 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1140 !strconcat(OpcodeStr,
1141 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1142 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1146 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1148 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1149 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1150 !strconcat(OpcodeStr,
1151 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1152 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1153 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1154 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1155 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1157 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1158 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1159 !strconcat(OpcodeStr,
1160 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1161 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1162 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1166 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1167 AVX512VLVectorVTInfo VTInfo> {
1168 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1169 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1171 let Predicates = [HasVLX] in {
1172 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1173 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1174 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1175 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1179 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1180 AVX512VLVectorVTInfo VTInfo> {
1181 let Predicates = [HasBWI] in
1182 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1184 let Predicates = [HasBWI, HasVLX] in {
1185 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1186 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1191 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1192 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1193 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1194 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1195 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1196 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1199 let Predicates = [HasAVX512] in {
1200 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1201 (v8f32 VR256X:$src2))),
1203 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1204 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1205 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1207 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1208 (v8i32 VR256X:$src2))),
1210 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1211 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1212 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1214 //===----------------------------------------------------------------------===//
1215 // Compare Instructions
1216 //===----------------------------------------------------------------------===//
1218 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1219 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1220 SDNode OpNode, ValueType VT,
1221 PatFrag ld_frag, string Suffix> {
1222 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1223 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1224 !strconcat("vcmp${cc}", Suffix,
1225 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1226 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1227 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1228 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1229 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1230 !strconcat("vcmp${cc}", Suffix,
1231 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1232 [(set VK1:$dst, (OpNode (VT RC:$src1),
1233 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1234 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1235 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1236 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1237 !strconcat("vcmp", Suffix,
1238 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1239 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1241 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1242 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1243 !strconcat("vcmp", Suffix,
1244 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1245 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1249 let Predicates = [HasAVX512] in {
1250 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1252 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1256 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1257 X86VectorVTInfo _> {
1258 def rr : AVX512BI<opc, MRMSrcReg,
1259 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1260 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1261 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1262 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1264 def rm : AVX512BI<opc, MRMSrcMem,
1265 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1266 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1267 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1268 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1269 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1270 def rrk : AVX512BI<opc, MRMSrcReg,
1271 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1272 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1273 "$dst {${mask}}, $src1, $src2}"),
1274 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1275 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1276 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1278 def rmk : AVX512BI<opc, MRMSrcMem,
1279 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1280 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1281 "$dst {${mask}}, $src1, $src2}"),
1282 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1283 (OpNode (_.VT _.RC:$src1),
1285 (_.LdFrag addr:$src2))))))],
1286 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1289 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1290 X86VectorVTInfo _> :
1291 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1292 let mayLoad = 1 in {
1293 def rmb : AVX512BI<opc, MRMSrcMem,
1294 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1295 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1296 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1297 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1298 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1299 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1300 def rmbk : AVX512BI<opc, MRMSrcMem,
1301 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1302 _.ScalarMemOp:$src2),
1303 !strconcat(OpcodeStr,
1304 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1305 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1306 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1307 (OpNode (_.VT _.RC:$src1),
1309 (_.ScalarLdFrag addr:$src2)))))],
1310 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1314 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1315 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1316 let Predicates = [prd] in
1317 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1320 let Predicates = [prd, HasVLX] in {
1321 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1323 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1328 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1329 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1331 let Predicates = [prd] in
1332 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1335 let Predicates = [prd, HasVLX] in {
1336 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1338 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1343 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1344 avx512vl_i8_info, HasBWI>,
1347 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1348 avx512vl_i16_info, HasBWI>,
1349 EVEX_CD8<16, CD8VF>;
1351 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1352 avx512vl_i32_info, HasAVX512>,
1353 EVEX_CD8<32, CD8VF>;
1355 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1356 avx512vl_i64_info, HasAVX512>,
1357 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1359 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1360 avx512vl_i8_info, HasBWI>,
1363 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1364 avx512vl_i16_info, HasBWI>,
1365 EVEX_CD8<16, CD8VF>;
1367 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1368 avx512vl_i32_info, HasAVX512>,
1369 EVEX_CD8<32, CD8VF>;
1371 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1372 avx512vl_i64_info, HasAVX512>,
1373 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1375 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1376 (COPY_TO_REGCLASS (VPCMPGTDZrr
1377 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1378 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1380 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1381 (COPY_TO_REGCLASS (VPCMPEQDZrr
1382 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1383 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1385 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1386 X86VectorVTInfo _> {
1387 def rri : AVX512AIi8<opc, MRMSrcReg,
1388 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1389 !strconcat("vpcmp${cc}", Suffix,
1390 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1391 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1393 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1395 def rmi : AVX512AIi8<opc, MRMSrcMem,
1396 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1397 !strconcat("vpcmp${cc}", Suffix,
1398 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1399 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1400 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1402 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1403 def rrik : AVX512AIi8<opc, MRMSrcReg,
1404 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1406 !strconcat("vpcmp${cc}", Suffix,
1407 "\t{$src2, $src1, $dst {${mask}}|",
1408 "$dst {${mask}}, $src1, $src2}"),
1409 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1410 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1412 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1414 def rmik : AVX512AIi8<opc, MRMSrcMem,
1415 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1417 !strconcat("vpcmp${cc}", Suffix,
1418 "\t{$src2, $src1, $dst {${mask}}|",
1419 "$dst {${mask}}, $src1, $src2}"),
1420 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1421 (OpNode (_.VT _.RC:$src1),
1422 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1424 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1426 // Accept explicit immediate argument form instead of comparison code.
1427 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1428 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1429 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1430 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1431 "$dst, $src1, $src2, $cc}"),
1432 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1434 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1435 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1436 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1437 "$dst, $src1, $src2, $cc}"),
1438 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1439 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1440 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1442 !strconcat("vpcmp", Suffix,
1443 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1444 "$dst {${mask}}, $src1, $src2, $cc}"),
1445 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1447 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1448 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1450 !strconcat("vpcmp", Suffix,
1451 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1452 "$dst {${mask}}, $src1, $src2, $cc}"),
1453 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1457 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1458 X86VectorVTInfo _> :
1459 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1460 def rmib : AVX512AIi8<opc, MRMSrcMem,
1461 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1463 !strconcat("vpcmp${cc}", Suffix,
1464 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1465 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1466 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1467 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1469 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1470 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1471 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1472 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1473 !strconcat("vpcmp${cc}", Suffix,
1474 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1475 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1476 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1477 (OpNode (_.VT _.RC:$src1),
1478 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1480 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1482 // Accept explicit immediate argument form instead of comparison code.
1483 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1484 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1485 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1487 !strconcat("vpcmp", Suffix,
1488 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1489 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1490 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1491 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1492 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1493 _.ScalarMemOp:$src2, u8imm:$cc),
1494 !strconcat("vpcmp", Suffix,
1495 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1496 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1497 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1501 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1502 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1503 let Predicates = [prd] in
1504 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1506 let Predicates = [prd, HasVLX] in {
1507 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1508 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1512 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1513 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1514 let Predicates = [prd] in
1515 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1518 let Predicates = [prd, HasVLX] in {
1519 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1521 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1526 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1527 HasBWI>, EVEX_CD8<8, CD8VF>;
1528 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1529 HasBWI>, EVEX_CD8<8, CD8VF>;
1531 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1532 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1533 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1534 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1536 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1537 HasAVX512>, EVEX_CD8<32, CD8VF>;
1538 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1539 HasAVX512>, EVEX_CD8<32, CD8VF>;
1541 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1542 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1543 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1544 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1546 // avx512_cmp_packed - compare packed instructions
1547 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1548 X86MemOperand x86memop, ValueType vt,
1549 string suffix, Domain d> {
1550 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1551 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1552 !strconcat("vcmp${cc}", suffix,
1553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1554 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1555 let hasSideEffects = 0 in
1556 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1557 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1558 !strconcat("vcmp${cc}", suffix,
1559 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1561 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1562 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1563 !strconcat("vcmp${cc}", suffix,
1564 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1566 (X86cmpm (vt RC:$src1), (load addr:$src2), imm:$cc))], d>;
1568 // Accept explicit immediate argument form instead of comparison code.
1569 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1570 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1571 (outs KRC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1572 !strconcat("vcmp", suffix,
1573 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1574 def rrib_alt: AVX512PIi8<0xC2, MRMSrcReg,
1575 (outs KRC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1576 !strconcat("vcmp", suffix,
1577 "\t{{sae}, $cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc, {sae}}"),
1580 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1581 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1582 !strconcat("vcmp", suffix,
1583 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1587 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1588 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1589 EVEX_CD8<32, CD8VF>;
1590 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1591 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1592 EVEX_CD8<64, CD8VF>;
1594 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1595 (COPY_TO_REGCLASS (VCMPPSZrri
1596 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1597 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1599 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1600 (COPY_TO_REGCLASS (VPCMPDZrri
1601 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1602 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1604 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1605 (COPY_TO_REGCLASS (VPCMPUDZrri
1606 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1607 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1610 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1611 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1613 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1614 (I8Imm imm:$cc)), GR16)>;
1616 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1617 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1619 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1620 (I8Imm imm:$cc)), GR8)>;
1622 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1623 (v16f32 VR512:$src2), i8immZExt5:$cc, (i16 -1),
1625 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1626 (I8Imm imm:$cc)), GR16)>;
1628 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1629 (v8f64 VR512:$src2), i8immZExt5:$cc, (i8 -1),
1631 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1632 (I8Imm imm:$cc)), GR8)>;
1634 // Mask register copy, including
1635 // - copy between mask registers
1636 // - load/store mask registers
1637 // - copy from GPR to mask register and vice versa
1639 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1640 string OpcodeStr, RegisterClass KRC,
1641 ValueType vvt, X86MemOperand x86memop> {
1642 let hasSideEffects = 0 in {
1643 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1644 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1646 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1647 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1648 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1650 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1651 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1652 [(store KRC:$src, addr:$dst)]>;
1656 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1658 RegisterClass KRC, RegisterClass GRC> {
1659 let hasSideEffects = 0 in {
1660 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1661 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1662 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1663 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1667 let Predicates = [HasDQI] in
1668 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1669 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1672 let Predicates = [HasAVX512] in
1673 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1674 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1677 let Predicates = [HasBWI] in {
1678 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1680 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1684 let Predicates = [HasBWI] in {
1685 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1687 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1691 // GR from/to mask register
1692 let Predicates = [HasDQI] in {
1693 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1694 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1695 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1696 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1698 let Predicates = [HasAVX512] in {
1699 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1700 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1701 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1702 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1704 let Predicates = [HasBWI] in {
1705 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1706 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1708 let Predicates = [HasBWI] in {
1709 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1710 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1714 let Predicates = [HasDQI] in {
1715 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1716 (KMOVBmk addr:$dst, VK8:$src)>;
1717 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1718 (KMOVBkm addr:$src)>;
1720 let Predicates = [HasAVX512, NoDQI] in {
1721 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1722 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1723 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1724 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1726 let Predicates = [HasAVX512] in {
1727 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1728 (KMOVWmk addr:$dst, VK16:$src)>;
1729 def : Pat<(i1 (load addr:$src)),
1730 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1731 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1732 (KMOVWkm addr:$src)>;
1734 let Predicates = [HasBWI] in {
1735 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1736 (KMOVDmk addr:$dst, VK32:$src)>;
1737 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1738 (KMOVDkm addr:$src)>;
1740 let Predicates = [HasBWI] in {
1741 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1742 (KMOVQmk addr:$dst, VK64:$src)>;
1743 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1744 (KMOVQkm addr:$src)>;
1747 let Predicates = [HasAVX512] in {
1748 def : Pat<(i1 (trunc (i64 GR64:$src))),
1749 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1752 def : Pat<(i1 (trunc (i32 GR32:$src))),
1753 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1755 def : Pat<(i1 (trunc (i8 GR8:$src))),
1757 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1759 def : Pat<(i1 (trunc (i16 GR16:$src))),
1761 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1764 def : Pat<(i32 (zext VK1:$src)),
1765 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1766 def : Pat<(i8 (zext VK1:$src)),
1769 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1770 def : Pat<(i64 (zext VK1:$src)),
1771 (AND64ri8 (SUBREG_TO_REG (i64 0),
1772 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1773 def : Pat<(i16 (zext VK1:$src)),
1775 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1777 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1778 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1779 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1780 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1782 let Predicates = [HasBWI] in {
1783 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1784 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1785 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1786 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1790 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1791 let Predicates = [HasAVX512] in {
1792 // GR from/to 8-bit mask without native support
1793 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1795 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1797 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1799 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1802 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1803 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1804 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1805 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1807 let Predicates = [HasBWI] in {
1808 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1809 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1810 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1811 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1814 // Mask unary operation
1816 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1817 RegisterClass KRC, SDPatternOperator OpNode,
1819 let Predicates = [prd] in
1820 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1821 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1822 [(set KRC:$dst, (OpNode KRC:$src))]>;
1825 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1826 SDPatternOperator OpNode> {
1827 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1829 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1830 HasAVX512>, VEX, PS;
1831 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1832 HasBWI>, VEX, PD, VEX_W;
1833 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1834 HasBWI>, VEX, PS, VEX_W;
1837 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1839 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1840 let Predicates = [HasAVX512] in
1841 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1843 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1844 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1846 defm : avx512_mask_unop_int<"knot", "KNOT">;
1848 let Predicates = [HasDQI] in
1849 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1850 let Predicates = [HasAVX512] in
1851 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1852 let Predicates = [HasBWI] in
1853 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1854 let Predicates = [HasBWI] in
1855 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1857 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1858 let Predicates = [HasAVX512, NoDQI] in {
1859 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1860 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1862 def : Pat<(not VK8:$src),
1864 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1867 // Mask binary operation
1868 // - KAND, KANDN, KOR, KXNOR, KXOR
1869 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1870 RegisterClass KRC, SDPatternOperator OpNode,
1872 let Predicates = [prd] in
1873 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1874 !strconcat(OpcodeStr,
1875 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1876 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1879 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1880 SDPatternOperator OpNode> {
1881 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1882 HasDQI>, VEX_4V, VEX_L, PD;
1883 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1884 HasAVX512>, VEX_4V, VEX_L, PS;
1885 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1886 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1887 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1888 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1891 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1892 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1894 let isCommutable = 1 in {
1895 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1896 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1897 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1898 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1900 let isCommutable = 0 in
1901 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1903 def : Pat<(xor VK1:$src1, VK1:$src2),
1904 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1905 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1907 def : Pat<(or VK1:$src1, VK1:$src2),
1908 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1909 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1911 def : Pat<(and VK1:$src1, VK1:$src2),
1912 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1913 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1915 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1916 let Predicates = [HasAVX512] in
1917 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1918 (i16 GR16:$src1), (i16 GR16:$src2)),
1919 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1920 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1921 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1924 defm : avx512_mask_binop_int<"kand", "KAND">;
1925 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1926 defm : avx512_mask_binop_int<"kor", "KOR">;
1927 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1928 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1930 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1931 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1932 let Predicates = [HasAVX512] in
1933 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1935 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1936 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1939 defm : avx512_binop_pat<and, KANDWrr>;
1940 defm : avx512_binop_pat<andn, KANDNWrr>;
1941 defm : avx512_binop_pat<or, KORWrr>;
1942 defm : avx512_binop_pat<xnor, KXNORWrr>;
1943 defm : avx512_binop_pat<xor, KXORWrr>;
1946 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1947 RegisterClass KRC> {
1948 let Predicates = [HasAVX512] in
1949 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1950 !strconcat(OpcodeStr,
1951 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1954 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1955 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1959 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1960 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1961 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1962 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1965 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1966 let Predicates = [HasAVX512] in
1967 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1968 (i16 GR16:$src1), (i16 GR16:$src2)),
1969 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1970 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1971 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1973 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1976 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1978 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1979 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1980 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1981 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1984 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1985 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1987 let Predicates = [HasDQI] in
1988 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
1990 let Predicates = [HasBWI] in {
1991 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
1993 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
1998 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2001 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2003 let Predicates = [HasAVX512] in
2004 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2005 !strconcat(OpcodeStr,
2006 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2007 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2010 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2012 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2014 let Predicates = [HasDQI] in
2015 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2017 let Predicates = [HasBWI] in {
2018 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2020 let Predicates = [HasDQI] in
2021 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2026 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2027 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2029 // Mask setting all 0s or 1s
2030 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2031 let Predicates = [HasAVX512] in
2032 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2033 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2034 [(set KRC:$dst, (VT Val))]>;
2037 multiclass avx512_mask_setop_w<PatFrag Val> {
2038 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2039 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2042 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2043 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2045 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2046 let Predicates = [HasAVX512] in {
2047 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2048 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2049 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2050 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2051 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2053 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2054 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2056 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2057 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2059 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2060 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2062 let Predicates = [HasVLX] in {
2063 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2064 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2065 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2066 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2067 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2068 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2069 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2070 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2071 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2072 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2075 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2076 (v8i1 (COPY_TO_REGCLASS
2077 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2078 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2080 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2081 (v8i1 (COPY_TO_REGCLASS
2082 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2083 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2085 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2086 (v4i1 (COPY_TO_REGCLASS
2087 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2088 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2090 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2091 (v4i1 (COPY_TO_REGCLASS
2092 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2093 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2095 //===----------------------------------------------------------------------===//
2096 // AVX-512 - Aligned and unaligned load and store
2100 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2101 PatFrag ld_frag, PatFrag mload,
2102 bit IsReMaterializable = 1> {
2103 let hasSideEffects = 0 in {
2104 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2105 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2107 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2108 (ins _.KRCWM:$mask, _.RC:$src),
2109 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2110 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2113 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2114 SchedRW = [WriteLoad] in
2115 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2116 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2117 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2120 let Constraints = "$src0 = $dst" in {
2121 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2122 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2123 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2124 "${dst} {${mask}}, $src1}"),
2125 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2127 (_.VT _.RC:$src0))))], _.ExeDomain>,
2129 let mayLoad = 1, SchedRW = [WriteLoad] in
2130 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2131 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2132 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2133 "${dst} {${mask}}, $src1}"),
2134 [(set _.RC:$dst, (_.VT
2135 (vselect _.KRCWM:$mask,
2136 (_.VT (bitconvert (ld_frag addr:$src1))),
2137 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2139 let mayLoad = 1, SchedRW = [WriteLoad] in
2140 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2141 (ins _.KRCWM:$mask, _.MemOp:$src),
2142 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2143 "${dst} {${mask}} {z}, $src}",
2144 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2145 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2146 _.ExeDomain>, EVEX, EVEX_KZ;
2148 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2149 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2151 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2152 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2154 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2155 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2156 _.KRCWM:$mask, addr:$ptr)>;
2159 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2160 AVX512VLVectorVTInfo _,
2162 bit IsReMaterializable = 1> {
2163 let Predicates = [prd] in
2164 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2165 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2167 let Predicates = [prd, HasVLX] in {
2168 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2169 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2170 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2171 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2175 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2176 AVX512VLVectorVTInfo _,
2178 bit IsReMaterializable = 1> {
2179 let Predicates = [prd] in
2180 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2181 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2183 let Predicates = [prd, HasVLX] in {
2184 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2185 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2186 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2187 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2191 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2192 PatFrag st_frag, PatFrag mstore> {
2193 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2194 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2195 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2197 let Constraints = "$src1 = $dst" in
2198 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2199 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2201 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2202 [], _.ExeDomain>, EVEX, EVEX_K;
2203 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2204 (ins _.KRCWM:$mask, _.RC:$src),
2206 "\t{$src, ${dst} {${mask}} {z}|" #
2207 "${dst} {${mask}} {z}, $src}",
2208 [], _.ExeDomain>, EVEX, EVEX_KZ;
2210 let mayStore = 1 in {
2211 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2212 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2213 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2214 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2215 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2216 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2217 [], _.ExeDomain>, EVEX, EVEX_K;
2220 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2221 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2222 _.KRCWM:$mask, _.RC:$src)>;
2226 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2227 AVX512VLVectorVTInfo _, Predicate prd> {
2228 let Predicates = [prd] in
2229 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2230 masked_store_unaligned>, EVEX_V512;
2232 let Predicates = [prd, HasVLX] in {
2233 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2234 masked_store_unaligned>, EVEX_V256;
2235 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2236 masked_store_unaligned>, EVEX_V128;
2240 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2241 AVX512VLVectorVTInfo _, Predicate prd> {
2242 let Predicates = [prd] in
2243 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2244 masked_store_aligned512>, EVEX_V512;
2246 let Predicates = [prd, HasVLX] in {
2247 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2248 masked_store_aligned256>, EVEX_V256;
2249 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2250 masked_store_aligned128>, EVEX_V128;
2254 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2256 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2257 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2259 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2261 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2262 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2264 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2265 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2266 PS, EVEX_CD8<32, CD8VF>;
2268 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2269 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2270 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2272 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2273 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2274 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2276 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2277 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2278 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2280 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2281 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2282 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2284 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2285 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2286 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2288 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2289 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2290 (VMOVAPDZrm addr:$ptr)>;
2292 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2293 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2294 (VMOVAPSZrm addr:$ptr)>;
2296 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2298 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2300 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2302 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2305 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2307 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2309 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2311 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2314 let Predicates = [HasAVX512, NoVLX] in {
2315 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2316 (VMOVUPSZmrk addr:$ptr,
2317 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2318 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2320 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2321 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2322 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2324 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2325 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2326 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2327 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2330 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2332 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2333 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2335 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2337 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2338 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2340 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2341 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2342 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2344 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2345 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2346 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2348 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2349 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2350 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2352 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2353 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2354 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2356 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2357 (v16i32 immAllZerosV), GR16:$mask)),
2358 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2360 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2361 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2362 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2364 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2366 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2368 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2370 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2373 let AddedComplexity = 20 in {
2374 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2375 (bc_v8i64 (v16i32 immAllZerosV)))),
2376 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2378 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2379 (v8i64 VR512:$src))),
2380 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2383 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2384 (v16i32 immAllZerosV))),
2385 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2387 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2388 (v16i32 VR512:$src))),
2389 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2392 let Predicates = [HasAVX512, NoVLX] in {
2393 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2394 (VMOVDQU32Zmrk addr:$ptr,
2395 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2396 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2398 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2399 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2400 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2403 // Move Int Doubleword to Packed Double Int
2405 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2406 "vmovd\t{$src, $dst|$dst, $src}",
2408 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2410 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2411 "vmovd\t{$src, $dst|$dst, $src}",
2413 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2414 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2415 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2416 "vmovq\t{$src, $dst|$dst, $src}",
2418 (v2i64 (scalar_to_vector GR64:$src)))],
2419 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2420 let isCodeGenOnly = 1 in {
2421 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2422 "vmovq\t{$src, $dst|$dst, $src}",
2423 [(set FR64:$dst, (bitconvert GR64:$src))],
2424 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2425 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2426 "vmovq\t{$src, $dst|$dst, $src}",
2427 [(set GR64:$dst, (bitconvert FR64:$src))],
2428 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2430 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2431 "vmovq\t{$src, $dst|$dst, $src}",
2432 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2433 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2434 EVEX_CD8<64, CD8VT1>;
2436 // Move Int Doubleword to Single Scalar
2438 let isCodeGenOnly = 1 in {
2439 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2440 "vmovd\t{$src, $dst|$dst, $src}",
2441 [(set FR32X:$dst, (bitconvert GR32:$src))],
2442 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2444 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2445 "vmovd\t{$src, $dst|$dst, $src}",
2446 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2447 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2450 // Move doubleword from xmm register to r/m32
2452 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2453 "vmovd\t{$src, $dst|$dst, $src}",
2454 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2455 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2457 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2458 (ins i32mem:$dst, VR128X:$src),
2459 "vmovd\t{$src, $dst|$dst, $src}",
2460 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2461 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2462 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2464 // Move quadword from xmm1 register to r/m64
2466 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2467 "vmovq\t{$src, $dst|$dst, $src}",
2468 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2470 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2471 Requires<[HasAVX512, In64BitMode]>;
2473 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2474 (ins i64mem:$dst, VR128X:$src),
2475 "vmovq\t{$src, $dst|$dst, $src}",
2476 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2477 addr:$dst)], IIC_SSE_MOVDQ>,
2478 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2479 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2481 // Move Scalar Single to Double Int
2483 let isCodeGenOnly = 1 in {
2484 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2486 "vmovd\t{$src, $dst|$dst, $src}",
2487 [(set GR32:$dst, (bitconvert FR32X:$src))],
2488 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2489 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2490 (ins i32mem:$dst, FR32X:$src),
2491 "vmovd\t{$src, $dst|$dst, $src}",
2492 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2493 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2496 // Move Quadword Int to Packed Quadword Int
2498 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2500 "vmovq\t{$src, $dst|$dst, $src}",
2502 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2503 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2505 //===----------------------------------------------------------------------===//
2506 // AVX-512 MOVSS, MOVSD
2507 //===----------------------------------------------------------------------===//
2509 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2510 SDNode OpNode, ValueType vt,
2511 X86MemOperand x86memop, PatFrag mem_pat> {
2512 let hasSideEffects = 0 in {
2513 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2514 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2515 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2516 (scalar_to_vector RC:$src2))))],
2517 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2518 let Constraints = "$src1 = $dst" in
2519 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2520 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2522 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2523 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2524 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2526 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2528 let mayStore = 1 in {
2529 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2530 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2531 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2533 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2534 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2535 [], IIC_SSE_MOV_S_MR>,
2536 EVEX, VEX_LIG, EVEX_K;
2538 } //hasSideEffects = 0
2541 let ExeDomain = SSEPackedSingle in
2542 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2543 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2545 let ExeDomain = SSEPackedDouble in
2546 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2547 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2549 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2550 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2551 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2553 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2554 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2555 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2557 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2558 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2559 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2561 // For the disassembler
2562 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2563 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2564 (ins VR128X:$src1, FR32X:$src2),
2565 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2567 XS, EVEX_4V, VEX_LIG;
2568 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2569 (ins VR128X:$src1, FR64X:$src2),
2570 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2572 XD, EVEX_4V, VEX_LIG, VEX_W;
2575 let Predicates = [HasAVX512] in {
2576 let AddedComplexity = 15 in {
2577 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2578 // MOVS{S,D} to the lower bits.
2579 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2580 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2581 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2582 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2583 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2584 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2585 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2586 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2588 // Move low f32 and clear high bits.
2589 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2590 (SUBREG_TO_REG (i32 0),
2591 (VMOVSSZrr (v4f32 (V_SET0)),
2592 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2593 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2594 (SUBREG_TO_REG (i32 0),
2595 (VMOVSSZrr (v4i32 (V_SET0)),
2596 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2599 let AddedComplexity = 20 in {
2600 // MOVSSrm zeros the high parts of the register; represent this
2601 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2602 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2603 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2604 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2605 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2606 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2607 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2609 // MOVSDrm zeros the high parts of the register; represent this
2610 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2611 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2612 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2613 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2614 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2615 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2616 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2617 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2618 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2619 def : Pat<(v2f64 (X86vzload addr:$src)),
2620 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2622 // Represent the same patterns above but in the form they appear for
2624 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2625 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2626 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2627 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2628 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2629 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2630 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2631 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2632 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2634 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2635 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2636 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2637 FR32X:$src)), sub_xmm)>;
2638 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2639 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2640 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2641 FR64X:$src)), sub_xmm)>;
2642 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2643 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2644 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2646 // Move low f64 and clear high bits.
2647 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2648 (SUBREG_TO_REG (i32 0),
2649 (VMOVSDZrr (v2f64 (V_SET0)),
2650 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2652 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2653 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2654 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2656 // Extract and store.
2657 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2659 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2660 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2662 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2664 // Shuffle with VMOVSS
2665 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2666 (VMOVSSZrr (v4i32 VR128X:$src1),
2667 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2668 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2669 (VMOVSSZrr (v4f32 VR128X:$src1),
2670 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2673 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2674 (SUBREG_TO_REG (i32 0),
2675 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2676 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2678 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2679 (SUBREG_TO_REG (i32 0),
2680 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2681 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2684 // Shuffle with VMOVSD
2685 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2686 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2687 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2688 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2689 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2690 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2691 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2692 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2695 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2696 (SUBREG_TO_REG (i32 0),
2697 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2698 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2700 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2701 (SUBREG_TO_REG (i32 0),
2702 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2703 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2706 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2707 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2708 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2709 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2710 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2711 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2712 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2713 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2716 let AddedComplexity = 15 in
2717 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2719 "vmovq\t{$src, $dst|$dst, $src}",
2720 [(set VR128X:$dst, (v2i64 (X86vzmovl
2721 (v2i64 VR128X:$src))))],
2722 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2724 let AddedComplexity = 20 in
2725 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2727 "vmovq\t{$src, $dst|$dst, $src}",
2728 [(set VR128X:$dst, (v2i64 (X86vzmovl
2729 (loadv2i64 addr:$src))))],
2730 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2731 EVEX_CD8<8, CD8VT8>;
2733 let Predicates = [HasAVX512] in {
2734 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2735 let AddedComplexity = 20 in {
2736 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2737 (VMOVDI2PDIZrm addr:$src)>;
2738 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2739 (VMOV64toPQIZrr GR64:$src)>;
2740 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2741 (VMOVDI2PDIZrr GR32:$src)>;
2743 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2744 (VMOVDI2PDIZrm addr:$src)>;
2745 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2746 (VMOVDI2PDIZrm addr:$src)>;
2747 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2748 (VMOVZPQILo2PQIZrm addr:$src)>;
2749 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2750 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2751 def : Pat<(v2i64 (X86vzload addr:$src)),
2752 (VMOVZPQILo2PQIZrm addr:$src)>;
2755 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2756 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2757 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2758 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2759 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2760 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2761 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2764 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2765 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2767 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2768 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2770 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2771 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2773 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2774 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2776 //===----------------------------------------------------------------------===//
2777 // AVX-512 - Non-temporals
2778 //===----------------------------------------------------------------------===//
2779 let SchedRW = [WriteLoad] in {
2780 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2781 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2782 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2783 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2784 EVEX_CD8<64, CD8VF>;
2786 let Predicates = [HasAVX512, HasVLX] in {
2787 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2789 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2790 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2791 EVEX_CD8<64, CD8VF>;
2793 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2795 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2796 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2797 EVEX_CD8<64, CD8VF>;
2801 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2802 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2803 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2804 let SchedRW = [WriteStore], mayStore = 1,
2805 AddedComplexity = 400 in
2806 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2807 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2808 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2811 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2812 string elty, string elsz, string vsz512,
2813 string vsz256, string vsz128, Domain d,
2814 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2815 let Predicates = [prd] in
2816 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2817 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2818 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2821 let Predicates = [prd, HasVLX] in {
2822 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2823 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2824 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2827 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2828 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2829 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2834 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2835 "i", "64", "8", "4", "2", SSEPackedInt,
2836 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2838 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2839 "f", "64", "8", "4", "2", SSEPackedDouble,
2840 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2842 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2843 "f", "32", "16", "8", "4", SSEPackedSingle,
2844 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2846 //===----------------------------------------------------------------------===//
2847 // AVX-512 - Integer arithmetic
2849 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2850 X86VectorVTInfo _, OpndItins itins,
2851 bit IsCommutable = 0> {
2852 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2853 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2854 "$src2, $src1", "$src1, $src2",
2855 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2856 "", itins.rr, IsCommutable>,
2857 AVX512BIBase, EVEX_4V;
2860 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2861 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2862 "$src2, $src1", "$src1, $src2",
2863 (_.VT (OpNode _.RC:$src1,
2864 (bitconvert (_.LdFrag addr:$src2)))),
2866 AVX512BIBase, EVEX_4V;
2869 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2870 X86VectorVTInfo _, OpndItins itins,
2871 bit IsCommutable = 0> :
2872 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2874 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2875 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2876 "${src2}"##_.BroadcastStr##", $src1",
2877 "$src1, ${src2}"##_.BroadcastStr,
2878 (_.VT (OpNode _.RC:$src1,
2880 (_.ScalarLdFrag addr:$src2)))),
2882 AVX512BIBase, EVEX_4V, EVEX_B;
2885 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2886 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2887 Predicate prd, bit IsCommutable = 0> {
2888 let Predicates = [prd] in
2889 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2890 IsCommutable>, EVEX_V512;
2892 let Predicates = [prd, HasVLX] in {
2893 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2894 IsCommutable>, EVEX_V256;
2895 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2896 IsCommutable>, EVEX_V128;
2900 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2901 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2902 Predicate prd, bit IsCommutable = 0> {
2903 let Predicates = [prd] in
2904 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2905 IsCommutable>, EVEX_V512;
2907 let Predicates = [prd, HasVLX] in {
2908 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2909 IsCommutable>, EVEX_V256;
2910 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2911 IsCommutable>, EVEX_V128;
2915 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2916 OpndItins itins, Predicate prd,
2917 bit IsCommutable = 0> {
2918 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2919 itins, prd, IsCommutable>,
2920 VEX_W, EVEX_CD8<64, CD8VF>;
2923 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2924 OpndItins itins, Predicate prd,
2925 bit IsCommutable = 0> {
2926 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2927 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2930 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2931 OpndItins itins, Predicate prd,
2932 bit IsCommutable = 0> {
2933 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2934 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2937 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2938 OpndItins itins, Predicate prd,
2939 bit IsCommutable = 0> {
2940 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2941 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2944 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2945 SDNode OpNode, OpndItins itins, Predicate prd,
2946 bit IsCommutable = 0> {
2947 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2950 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2954 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2955 SDNode OpNode, OpndItins itins, Predicate prd,
2956 bit IsCommutable = 0> {
2957 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2960 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2964 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2965 bits<8> opc_d, bits<8> opc_q,
2966 string OpcodeStr, SDNode OpNode,
2967 OpndItins itins, bit IsCommutable = 0> {
2968 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2969 itins, HasAVX512, IsCommutable>,
2970 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2971 itins, HasBWI, IsCommutable>;
2974 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
2975 SDNode OpNode,X86VectorVTInfo _Src,
2976 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
2977 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
2978 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
2979 "$src2, $src1","$src1, $src2",
2981 (_Src.VT _Src.RC:$src1),
2982 (_Src.VT _Src.RC:$src2))),
2983 "",itins.rr, IsCommutable>,
2984 AVX512BIBase, EVEX_4V;
2985 let mayLoad = 1 in {
2986 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
2987 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
2988 "$src2, $src1", "$src1, $src2",
2989 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
2990 (bitconvert (_Src.LdFrag addr:$src2)))),
2992 AVX512BIBase, EVEX_4V;
2994 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
2995 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
2997 "${src2}"##_Dst.BroadcastStr##", $src1",
2998 "$src1, ${src2}"##_Dst.BroadcastStr,
2999 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3000 (_Dst.VT (X86VBroadcast
3001 (_Dst.ScalarLdFrag addr:$src2)))))),
3003 AVX512BIBase, EVEX_4V, EVEX_B;
3007 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3008 SSE_INTALU_ITINS_P, 1>;
3009 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3010 SSE_INTALU_ITINS_P, 0>;
3011 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3012 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3013 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3014 SSE_INTALU_ITINS_P, HasBWI, 1>;
3015 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3016 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3019 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3020 SDNode OpNode, bit IsCommutable = 0> {
3022 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3023 v16i32_info, v8i64_info, IsCommutable>,
3024 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3025 let Predicates = [HasVLX] in {
3026 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3027 v8i32x_info, v4i64x_info, IsCommutable>,
3028 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3029 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3030 v4i32x_info, v2i64x_info, IsCommutable>,
3031 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3035 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3037 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3040 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3041 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3042 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3043 SSE_INTALU_ITINS_P, HasBWI, 1>;
3044 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3045 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3047 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3048 SSE_INTALU_ITINS_P, HasBWI, 1>;
3049 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3050 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3051 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3052 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3054 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3055 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3056 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3057 SSE_INTALU_ITINS_P, HasBWI, 1>;
3058 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3059 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3061 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3062 SSE_INTALU_ITINS_P, HasBWI, 1>;
3063 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3064 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3065 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3066 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3068 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3069 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3070 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3071 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3072 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3073 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3074 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3075 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3076 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3077 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3078 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3079 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3080 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3081 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3082 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3083 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3084 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3085 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3086 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3087 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3088 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3089 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3090 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3091 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3092 //===----------------------------------------------------------------------===//
3093 // AVX-512 - Unpack Instructions
3094 //===----------------------------------------------------------------------===//
3096 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3097 PatFrag mem_frag, RegisterClass RC,
3098 X86MemOperand x86memop, string asm,
3100 def rr : AVX512PI<opc, MRMSrcReg,
3101 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3103 (vt (OpNode RC:$src1, RC:$src2)))],
3105 def rm : AVX512PI<opc, MRMSrcMem,
3106 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3108 (vt (OpNode RC:$src1,
3109 (bitconvert (mem_frag addr:$src2)))))],
3113 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3114 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3115 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3116 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3117 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3118 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3119 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3120 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3121 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3122 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3123 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3124 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3126 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3127 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3128 X86MemOperand x86memop> {
3129 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3130 (ins RC:$src1, RC:$src2),
3131 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3132 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3133 IIC_SSE_UNPCK>, EVEX_4V;
3134 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3135 (ins RC:$src1, x86memop:$src2),
3136 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3137 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3138 (bitconvert (memop_frag addr:$src2)))))],
3139 IIC_SSE_UNPCK>, EVEX_4V;
3141 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3142 VR512, loadv16i32, i512mem>, EVEX_V512,
3143 EVEX_CD8<32, CD8VF>;
3144 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3145 VR512, loadv8i64, i512mem>, EVEX_V512,
3146 VEX_W, EVEX_CD8<64, CD8VF>;
3147 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3148 VR512, loadv16i32, i512mem>, EVEX_V512,
3149 EVEX_CD8<32, CD8VF>;
3150 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3151 VR512, loadv8i64, i512mem>, EVEX_V512,
3152 VEX_W, EVEX_CD8<64, CD8VF>;
3153 //===----------------------------------------------------------------------===//
3157 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3158 SDNode OpNode, PatFrag mem_frag,
3159 X86MemOperand x86memop, ValueType OpVT> {
3160 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3161 (ins RC:$src1, u8imm:$src2),
3162 !strconcat(OpcodeStr,
3163 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3165 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3167 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3168 (ins x86memop:$src1, u8imm:$src2),
3169 !strconcat(OpcodeStr,
3170 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3172 (OpVT (OpNode (mem_frag addr:$src1),
3173 (i8 imm:$src2))))]>, EVEX;
3176 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, loadv16i32,
3177 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3179 //===----------------------------------------------------------------------===//
3180 // AVX-512 Logical Instructions
3181 //===----------------------------------------------------------------------===//
3183 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3184 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3185 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3186 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3187 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3188 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3189 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3190 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3192 //===----------------------------------------------------------------------===//
3193 // AVX-512 FP arithmetic
3194 //===----------------------------------------------------------------------===//
3195 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3196 SDNode OpNode, SDNode VecNode, OpndItins itins,
3199 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3200 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3201 "$src2, $src1", "$src1, $src2",
3202 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3203 (i32 FROUND_CURRENT)),
3204 "", itins.rr, IsCommutable>;
3206 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3207 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3208 "$src2, $src1", "$src1, $src2",
3209 (VecNode (_.VT _.RC:$src1),
3210 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3211 (i32 FROUND_CURRENT)),
3212 "", itins.rm, IsCommutable>;
3213 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3214 Predicates = [HasAVX512] in {
3215 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3216 (ins _.FRC:$src1, _.FRC:$src2),
3217 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3218 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3220 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3221 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3222 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3223 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3224 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3228 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3229 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3231 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3232 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3233 "$rc, $src2, $src1", "$src1, $src2, $rc",
3234 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3235 (i32 imm:$rc)), "", itins.rr, IsCommutable>,
3238 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3239 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3241 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3242 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3243 "$src2, $src1", "$src1, $src2",
3244 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3245 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
3248 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3250 SizeItins itins, bit IsCommutable> {
3251 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3252 itins.s, IsCommutable>,
3253 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3254 itins.s, IsCommutable>,
3255 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3256 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3257 itins.d, IsCommutable>,
3258 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3259 itins.d, IsCommutable>,
3260 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3263 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3265 SizeItins itins, bit IsCommutable> {
3266 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3267 itins.s, IsCommutable>,
3268 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3269 itins.s, IsCommutable>,
3270 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3271 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3272 itins.d, IsCommutable>,
3273 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3274 itins.d, IsCommutable>,
3275 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3277 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3278 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3279 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3280 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3281 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3282 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3284 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3285 X86VectorVTInfo _, bit IsCommutable> {
3286 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3287 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3288 "$src2, $src1", "$src1, $src2",
3289 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3290 let mayLoad = 1 in {
3291 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3292 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3293 "$src2, $src1", "$src1, $src2",
3294 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3295 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3296 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3297 "${src2}"##_.BroadcastStr##", $src1",
3298 "$src1, ${src2}"##_.BroadcastStr,
3299 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3300 (_.ScalarLdFrag addr:$src2))))>,
3305 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3306 X86VectorVTInfo _, bit IsCommutable> {
3307 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3308 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3309 "$rc, $src2, $src1", "$src1, $src2, $rc",
3310 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3311 EVEX_4V, EVEX_B, EVEX_RC;
3314 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3315 bit IsCommutable = 0> {
3316 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3317 IsCommutable>, EVEX_V512, PS,
3318 EVEX_CD8<32, CD8VF>;
3319 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3320 IsCommutable>, EVEX_V512, PD, VEX_W,
3321 EVEX_CD8<64, CD8VF>;
3323 // Define only if AVX512VL feature is present.
3324 let Predicates = [HasVLX] in {
3325 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3326 IsCommutable>, EVEX_V128, PS,
3327 EVEX_CD8<32, CD8VF>;
3328 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3329 IsCommutable>, EVEX_V256, PS,
3330 EVEX_CD8<32, CD8VF>;
3331 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3332 IsCommutable>, EVEX_V128, PD, VEX_W,
3333 EVEX_CD8<64, CD8VF>;
3334 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3335 IsCommutable>, EVEX_V256, PD, VEX_W,
3336 EVEX_CD8<64, CD8VF>;
3340 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3341 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3342 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3343 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3344 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3347 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3348 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3349 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3350 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3351 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3352 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3353 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3354 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3355 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3356 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3357 let Predicates = [HasDQI] in {
3358 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3359 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3360 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3361 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3363 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3364 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3365 (i16 -1), FROUND_CURRENT)),
3366 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3368 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3369 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3370 (i8 -1), FROUND_CURRENT)),
3371 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3373 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3374 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3375 (i16 -1), FROUND_CURRENT)),
3376 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3378 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3379 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3380 (i8 -1), FROUND_CURRENT)),
3381 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3382 //===----------------------------------------------------------------------===//
3383 // AVX-512 VPTESTM instructions
3384 //===----------------------------------------------------------------------===//
3386 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3387 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3388 SDNode OpNode, ValueType vt> {
3389 def rr : AVX512PI<opc, MRMSrcReg,
3390 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3391 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3392 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3393 SSEPackedInt>, EVEX_4V;
3394 def rm : AVX512PI<opc, MRMSrcMem,
3395 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3396 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3397 [(set KRC:$dst, (OpNode (vt RC:$src1),
3398 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3401 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3402 loadv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3403 EVEX_CD8<32, CD8VF>;
3404 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3405 loadv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3406 EVEX_CD8<64, CD8VF>;
3408 let Predicates = [HasCDI] in {
3409 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3410 loadv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3411 EVEX_CD8<32, CD8VF>;
3412 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3413 loadv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3414 EVEX_CD8<64, CD8VF>;
3417 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3418 (v16i32 VR512:$src2), (i16 -1))),
3419 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3421 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3422 (v8i64 VR512:$src2), (i8 -1))),
3423 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3425 //===----------------------------------------------------------------------===//
3426 // AVX-512 Shift instructions
3427 //===----------------------------------------------------------------------===//
3428 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3429 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3430 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3431 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3432 "$src2, $src1", "$src1, $src2",
3433 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3434 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3436 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3437 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3438 "$src2, $src1", "$src1, $src2",
3439 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3441 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3444 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3445 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3447 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3448 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3449 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3450 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3451 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V, EVEX_B;
3454 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3455 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3456 // src2 is always 128-bit
3457 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3458 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3459 "$src2, $src1", "$src1, $src2",
3460 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3461 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3462 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3463 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3464 "$src2, $src1", "$src1, $src2",
3465 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3466 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3470 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3471 ValueType SrcVT, PatFrag bc_frag,
3472 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3473 let Predicates = [prd] in
3474 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3475 VTInfo.info512>, EVEX_V512,
3476 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3477 let Predicates = [prd, HasVLX] in {
3478 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3479 VTInfo.info256>, EVEX_V256,
3480 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3481 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3482 VTInfo.info128>, EVEX_V128,
3483 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3487 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3488 string OpcodeStr, SDNode OpNode> {
3489 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3490 avx512vl_i32_info, HasAVX512>;
3491 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3492 avx512vl_i64_info, HasAVX512>, VEX_W;
3493 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3494 avx512vl_i16_info, HasBWI>;
3497 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3498 string OpcodeStr, SDNode OpNode,
3499 AVX512VLVectorVTInfo VTInfo> {
3500 let Predicates = [HasAVX512] in
3501 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3503 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3504 VTInfo.info512>, EVEX_V512;
3505 let Predicates = [HasAVX512, HasVLX] in {
3506 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3508 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3509 VTInfo.info256>, EVEX_V256;
3510 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3512 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3513 VTInfo.info128>, EVEX_V128;
3517 multiclass avx512_shift_rmi_w<bits<8> opcw,
3518 Format ImmFormR, Format ImmFormM,
3519 string OpcodeStr, SDNode OpNode> {
3520 let Predicates = [HasBWI] in
3521 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3522 v32i16_info>, EVEX_V512;
3523 let Predicates = [HasVLX, HasBWI] in {
3524 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3525 v16i16x_info>, EVEX_V256;
3526 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3527 v8i16x_info>, EVEX_V128;
3531 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3532 Format ImmFormR, Format ImmFormM,
3533 string OpcodeStr, SDNode OpNode> {
3534 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3535 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3536 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3537 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3540 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3541 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>;
3543 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3544 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>;
3546 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x73, MRM4r, MRM4m, "vpsra", X86vsrai>,
3547 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>;
3549 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>;
3550 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>;
3552 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3553 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3554 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3556 //===-------------------------------------------------------------------===//
3557 // Variable Bit Shifts
3558 //===-------------------------------------------------------------------===//
3559 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3560 X86VectorVTInfo _> {
3561 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3562 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3563 "$src2, $src1", "$src1, $src2",
3564 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3565 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3567 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3568 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3569 "$src2, $src1", "$src1, $src2",
3570 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2))),
3571 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3572 EVEX_CD8<_.EltSize, CD8VF>;
3575 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3576 X86VectorVTInfo _> {
3578 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3579 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3580 "${src2}"##_.BroadcastStr##", $src1",
3581 "$src1, ${src2}"##_.BroadcastStr,
3582 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3583 (_.ScalarLdFrag addr:$src2))))),
3584 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3585 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3587 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3588 AVX512VLVectorVTInfo _> {
3589 let Predicates = [HasAVX512] in
3590 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3591 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3593 let Predicates = [HasAVX512, HasVLX] in {
3594 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3595 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3596 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3597 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3601 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3603 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3605 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3606 avx512vl_i64_info>, VEX_W;
3609 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3611 let Predicates = [HasBWI] in
3612 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3614 let Predicates = [HasVLX, HasBWI] in {
3616 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3618 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3623 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3624 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3625 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3626 avx512_var_shift_w<0x11, "vpsravw", sra>;
3627 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3628 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3629 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3630 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3632 //===----------------------------------------------------------------------===//
3633 // AVX-512 - MOVDDUP
3634 //===----------------------------------------------------------------------===//
3636 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3637 X86MemOperand x86memop, PatFrag memop_frag> {
3638 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3639 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3640 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3641 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3642 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3644 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3647 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3648 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3649 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3650 (VMOVDDUPZrm addr:$src)>;
3652 //===---------------------------------------------------------------------===//
3653 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3654 //===---------------------------------------------------------------------===//
3655 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3656 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3657 X86MemOperand x86memop> {
3658 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3659 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3660 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3662 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3663 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3664 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3667 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3668 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3669 EVEX_CD8<32, CD8VF>;
3670 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3671 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3672 EVEX_CD8<32, CD8VF>;
3674 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3675 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3676 (VMOVSHDUPZrm addr:$src)>;
3677 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3678 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3679 (VMOVSLDUPZrm addr:$src)>;
3681 //===----------------------------------------------------------------------===//
3682 // Move Low to High and High to Low packed FP Instructions
3683 //===----------------------------------------------------------------------===//
3684 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3685 (ins VR128X:$src1, VR128X:$src2),
3686 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3687 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3688 IIC_SSE_MOV_LH>, EVEX_4V;
3689 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3690 (ins VR128X:$src1, VR128X:$src2),
3691 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3692 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3693 IIC_SSE_MOV_LH>, EVEX_4V;
3695 let Predicates = [HasAVX512] in {
3697 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3698 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3699 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3700 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3703 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3704 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3707 //===----------------------------------------------------------------------===//
3708 // FMA - Fused Multiply Operations
3711 let Constraints = "$src1 = $dst" in {
3712 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3713 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3714 SDPatternOperator OpNode = null_frag> {
3715 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3716 (ins _.RC:$src2, _.RC:$src3),
3717 OpcodeStr, "$src3, $src2", "$src2, $src3",
3718 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3722 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3723 (ins _.RC:$src2, _.MemOp:$src3),
3724 OpcodeStr, "$src3, $src2", "$src2, $src3",
3725 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3728 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3729 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3730 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
3731 !strconcat("$src2, ${src3}", _.BroadcastStr ),
3733 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3734 AVX512FMA3Base, EVEX_B;
3736 } // Constraints = "$src1 = $dst"
3738 let Constraints = "$src1 = $dst" in {
3739 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3740 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr,
3742 SDPatternOperator OpNode> {
3743 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3744 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
3745 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
3746 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
3747 AVX512FMA3Base, EVEX_B, EVEX_RC;
3749 } // Constraints = "$src1 = $dst"
3751 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
3752 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
3753 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3754 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3757 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3758 string OpcodeStr, X86VectorVTInfo VTI,
3759 SDPatternOperator OpNode> {
3760 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3761 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3762 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3763 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
3766 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
3768 SDPatternOperator OpNode,
3769 SDPatternOperator OpNodeRnd> {
3770 let ExeDomain = SSEPackedSingle in {
3771 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3772 v16f32_info, OpNode>,
3773 avx512_fma3_round_forms<opc213, OpcodeStr,
3774 v16f32_info, OpNodeRnd>, EVEX_V512;
3775 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3776 v8f32x_info, OpNode>, EVEX_V256;
3777 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3778 v4f32x_info, OpNode>, EVEX_V128;
3780 let ExeDomain = SSEPackedDouble in {
3781 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3782 v8f64_info, OpNode>,
3783 avx512_fma3_round_forms<opc213, OpcodeStr, v8f64_info,
3784 OpNodeRnd>, EVEX_V512, VEX_W;
3785 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3786 v4f64x_info, OpNode>,
3788 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3789 v2f64x_info, OpNode>,
3794 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
3795 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
3796 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
3797 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
3798 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
3799 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
3801 let Constraints = "$src1 = $dst" in {
3802 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3803 X86VectorVTInfo _> {
3805 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3806 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3807 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3808 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
3810 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3811 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3812 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3813 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3815 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3816 (_.ScalarLdFrag addr:$src2))),
3817 _.RC:$src3))]>, EVEX_B;
3819 } // Constraints = "$src1 = $dst"
3821 multiclass avx512_fma3p_m132_f<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3823 let ExeDomain = SSEPackedSingle in {
3824 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
3825 OpNode,v16f32_info>, EVEX_V512,
3826 EVEX_CD8<32, CD8VF>;
3827 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3828 OpNode, v8f32x_info>, EVEX_V256,
3829 EVEX_CD8<32, CD8VF>;
3830 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3831 OpNode, v4f32x_info>, EVEX_V128,
3832 EVEX_CD8<32, CD8VF>;
3834 let ExeDomain = SSEPackedDouble in {
3835 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
3836 OpNode, v8f64_info>, EVEX_V512,
3837 VEX_W, EVEX_CD8<32, CD8VF>;
3838 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3839 OpNode, v4f64x_info>, EVEX_V256,
3840 VEX_W, EVEX_CD8<32, CD8VF>;
3841 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3842 OpNode, v2f64x_info>, EVEX_V128,
3843 VEX_W, EVEX_CD8<32, CD8VF>;
3847 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
3848 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
3849 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
3850 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
3851 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
3852 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
3855 let Constraints = "$src1 = $dst" in {
3856 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3857 RegisterClass RC, ValueType OpVT,
3858 X86MemOperand x86memop, Operand memop,
3860 let isCommutable = 1 in
3861 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3862 (ins RC:$src1, RC:$src2, RC:$src3),
3863 !strconcat(OpcodeStr,
3864 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3866 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3868 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3869 (ins RC:$src1, RC:$src2, f128mem:$src3),
3870 !strconcat(OpcodeStr,
3871 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3873 (OpVT (OpNode RC:$src2, RC:$src1,
3874 (mem_frag addr:$src3))))]>;
3876 } // Constraints = "$src1 = $dst"
3878 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3879 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3880 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3881 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3882 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3883 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3884 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3885 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3886 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3887 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3888 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3889 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3890 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3891 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3892 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3893 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3895 //===----------------------------------------------------------------------===//
3896 // AVX-512 Scalar convert from sign integer to float/double
3897 //===----------------------------------------------------------------------===//
3899 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3900 X86MemOperand x86memop, string asm> {
3901 let hasSideEffects = 0 in {
3902 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3903 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3906 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3907 (ins DstRC:$src1, x86memop:$src),
3908 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3910 } // hasSideEffects = 0
3913 let Predicates = [HasAVX512] in {
3914 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3915 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3916 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3917 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3918 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3919 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3920 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3921 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3923 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3924 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3925 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3926 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3927 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3928 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3929 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3930 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3932 def : Pat<(f32 (sint_to_fp GR32:$src)),
3933 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3934 def : Pat<(f32 (sint_to_fp GR64:$src)),
3935 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3936 def : Pat<(f64 (sint_to_fp GR32:$src)),
3937 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3938 def : Pat<(f64 (sint_to_fp GR64:$src)),
3939 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3941 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3942 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3943 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3944 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3945 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3946 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3947 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3948 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3950 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3951 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3952 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3953 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3954 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3955 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3956 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3957 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3959 def : Pat<(f32 (uint_to_fp GR32:$src)),
3960 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3961 def : Pat<(f32 (uint_to_fp GR64:$src)),
3962 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3963 def : Pat<(f64 (uint_to_fp GR32:$src)),
3964 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3965 def : Pat<(f64 (uint_to_fp GR64:$src)),
3966 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3969 //===----------------------------------------------------------------------===//
3970 // AVX-512 Scalar convert from float/double to integer
3971 //===----------------------------------------------------------------------===//
3972 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3973 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3975 let hasSideEffects = 0 in {
3976 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3977 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3978 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3979 Requires<[HasAVX512]>;
3981 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3982 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3983 Requires<[HasAVX512]>;
3984 } // hasSideEffects = 0
3986 let Predicates = [HasAVX512] in {
3987 // Convert float/double to signed/unsigned int 32/64
3988 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3989 ssmem, sse_load_f32, "cvtss2si">,
3990 XS, EVEX_CD8<32, CD8VT1>;
3991 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3992 ssmem, sse_load_f32, "cvtss2si">,
3993 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3994 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3995 ssmem, sse_load_f32, "cvtss2usi">,
3996 XS, EVEX_CD8<32, CD8VT1>;
3997 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3998 int_x86_avx512_cvtss2usi64, ssmem,
3999 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4000 EVEX_CD8<32, CD8VT1>;
4001 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4002 sdmem, sse_load_f64, "cvtsd2si">,
4003 XD, EVEX_CD8<64, CD8VT1>;
4004 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4005 sdmem, sse_load_f64, "cvtsd2si">,
4006 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4007 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4008 sdmem, sse_load_f64, "cvtsd2usi">,
4009 XD, EVEX_CD8<64, CD8VT1>;
4010 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4011 int_x86_avx512_cvtsd2usi64, sdmem,
4012 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4013 EVEX_CD8<64, CD8VT1>;
4015 let isCodeGenOnly = 1 in {
4016 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4017 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4018 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4019 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4020 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4021 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4022 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4023 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4024 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4025 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4026 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4027 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4029 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4030 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
4031 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4032 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4033 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
4034 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4035 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4036 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4037 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4038 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4039 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
4040 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4041 } // isCodeGenOnly = 1
4043 // Convert float/double to signed/unsigned int 32/64 with truncation
4044 let isCodeGenOnly = 1 in {
4045 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4046 ssmem, sse_load_f32, "cvttss2si">,
4047 XS, EVEX_CD8<32, CD8VT1>;
4048 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4049 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4050 "cvttss2si">, XS, VEX_W,
4051 EVEX_CD8<32, CD8VT1>;
4052 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4053 sdmem, sse_load_f64, "cvttsd2si">, XD,
4054 EVEX_CD8<64, CD8VT1>;
4055 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4056 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4057 "cvttsd2si">, XD, VEX_W,
4058 EVEX_CD8<64, CD8VT1>;
4059 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4060 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4061 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4062 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4063 int_x86_avx512_cvttss2usi64, ssmem,
4064 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4065 EVEX_CD8<32, CD8VT1>;
4066 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4067 int_x86_avx512_cvttsd2usi,
4068 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4069 EVEX_CD8<64, CD8VT1>;
4070 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4071 int_x86_avx512_cvttsd2usi64, sdmem,
4072 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4073 EVEX_CD8<64, CD8VT1>;
4074 } // isCodeGenOnly = 1
4076 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4077 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4079 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4080 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4081 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4082 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4083 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4084 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4087 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4088 loadf32, "cvttss2si">, XS,
4089 EVEX_CD8<32, CD8VT1>;
4090 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4091 loadf32, "cvttss2usi">, XS,
4092 EVEX_CD8<32, CD8VT1>;
4093 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4094 loadf32, "cvttss2si">, XS, VEX_W,
4095 EVEX_CD8<32, CD8VT1>;
4096 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4097 loadf32, "cvttss2usi">, XS, VEX_W,
4098 EVEX_CD8<32, CD8VT1>;
4099 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4100 loadf64, "cvttsd2si">, XD,
4101 EVEX_CD8<64, CD8VT1>;
4102 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4103 loadf64, "cvttsd2usi">, XD,
4104 EVEX_CD8<64, CD8VT1>;
4105 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4106 loadf64, "cvttsd2si">, XD, VEX_W,
4107 EVEX_CD8<64, CD8VT1>;
4108 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4109 loadf64, "cvttsd2usi">, XD, VEX_W,
4110 EVEX_CD8<64, CD8VT1>;
4112 //===----------------------------------------------------------------------===//
4113 // AVX-512 Convert form float to double and back
4114 //===----------------------------------------------------------------------===//
4115 let hasSideEffects = 0 in {
4116 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4117 (ins FR32X:$src1, FR32X:$src2),
4118 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4119 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4121 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4122 (ins FR32X:$src1, f32mem:$src2),
4123 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4124 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4125 EVEX_CD8<32, CD8VT1>;
4127 // Convert scalar double to scalar single
4128 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4129 (ins FR64X:$src1, FR64X:$src2),
4130 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4131 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4133 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4134 (ins FR64X:$src1, f64mem:$src2),
4135 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4136 []>, EVEX_4V, VEX_LIG, VEX_W,
4137 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4140 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4141 Requires<[HasAVX512]>;
4142 def : Pat<(fextend (loadf32 addr:$src)),
4143 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4145 def : Pat<(extloadf32 addr:$src),
4146 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4147 Requires<[HasAVX512, OptForSize]>;
4149 def : Pat<(extloadf32 addr:$src),
4150 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4151 Requires<[HasAVX512, OptForSpeed]>;
4153 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4154 Requires<[HasAVX512]>;
4156 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4157 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4158 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4160 let hasSideEffects = 0 in {
4161 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4162 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4164 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4165 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4166 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4167 [], d>, EVEX, EVEX_B, EVEX_RC;
4169 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4170 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4172 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4173 } // hasSideEffects = 0
4176 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4177 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4178 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4180 let hasSideEffects = 0 in {
4181 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4182 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4184 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4186 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4187 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4189 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4190 } // hasSideEffects = 0
4193 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4194 loadv8f64, f512mem, v8f32, v8f64,
4195 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4196 EVEX_CD8<64, CD8VF>;
4198 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4199 loadv4f64, f256mem, v8f64, v8f32,
4200 SSEPackedDouble>, EVEX_V512, PS,
4201 EVEX_CD8<32, CD8VH>;
4202 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4203 (VCVTPS2PDZrm addr:$src)>;
4205 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4206 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4207 (VCVTPD2PSZrr VR512:$src)>;
4209 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4210 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4211 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4213 //===----------------------------------------------------------------------===//
4214 // AVX-512 Vector convert from sign integer to float/double
4215 //===----------------------------------------------------------------------===//
4217 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4218 loadv8i64, i512mem, v16f32, v16i32,
4219 SSEPackedSingle>, EVEX_V512, PS,
4220 EVEX_CD8<32, CD8VF>;
4222 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4223 loadv4i64, i256mem, v8f64, v8i32,
4224 SSEPackedDouble>, EVEX_V512, XS,
4225 EVEX_CD8<32, CD8VH>;
4227 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4228 loadv16f32, f512mem, v16i32, v16f32,
4229 SSEPackedSingle>, EVEX_V512, XS,
4230 EVEX_CD8<32, CD8VF>;
4232 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4233 loadv8f64, f512mem, v8i32, v8f64,
4234 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4235 EVEX_CD8<64, CD8VF>;
4237 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4238 loadv16f32, f512mem, v16i32, v16f32,
4239 SSEPackedSingle>, EVEX_V512, PS,
4240 EVEX_CD8<32, CD8VF>;
4242 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4243 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4244 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4245 (VCVTTPS2UDQZrr VR512:$src)>;
4247 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4248 loadv8f64, f512mem, v8i32, v8f64,
4249 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4250 EVEX_CD8<64, CD8VF>;
4252 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4253 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4254 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4255 (VCVTTPD2UDQZrr VR512:$src)>;
4257 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4258 loadv4i64, f256mem, v8f64, v8i32,
4259 SSEPackedDouble>, EVEX_V512, XS,
4260 EVEX_CD8<32, CD8VH>;
4262 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4263 loadv16i32, f512mem, v16f32, v16i32,
4264 SSEPackedSingle>, EVEX_V512, XD,
4265 EVEX_CD8<32, CD8VF>;
4267 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4268 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4269 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4271 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4272 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4273 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4275 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4276 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4277 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4279 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4280 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4281 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4283 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4284 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4285 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4287 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4288 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4289 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4290 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4291 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4292 (VCVTDQ2PDZrr VR256X:$src)>;
4293 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4294 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4295 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4296 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4297 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4298 (VCVTUDQ2PDZrr VR256X:$src)>;
4300 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4301 RegisterClass DstRC, PatFrag mem_frag,
4302 X86MemOperand x86memop, Domain d> {
4303 let hasSideEffects = 0 in {
4304 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4305 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4307 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4308 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4309 [], d>, EVEX, EVEX_B, EVEX_RC;
4311 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4312 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4314 } // hasSideEffects = 0
4317 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4318 loadv16f32, f512mem, SSEPackedSingle>, PD,
4319 EVEX_V512, EVEX_CD8<32, CD8VF>;
4320 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4321 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4322 EVEX_V512, EVEX_CD8<64, CD8VF>;
4324 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4325 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4326 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4328 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4329 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4330 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4332 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4333 loadv16f32, f512mem, SSEPackedSingle>,
4334 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4335 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4336 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4337 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4339 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4340 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4341 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4343 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4344 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4345 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4347 let Predicates = [HasAVX512] in {
4348 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4349 (VCVTPD2PSZrm addr:$src)>;
4350 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4351 (VCVTPS2PDZrm addr:$src)>;
4354 //===----------------------------------------------------------------------===//
4355 // Half precision conversion instructions
4356 //===----------------------------------------------------------------------===//
4357 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4358 X86MemOperand x86memop> {
4359 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4360 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4362 let hasSideEffects = 0, mayLoad = 1 in
4363 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4364 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4367 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4368 X86MemOperand x86memop> {
4369 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4370 (ins srcRC:$src1, i32u8imm:$src2),
4371 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4373 let hasSideEffects = 0, mayStore = 1 in
4374 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4375 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4376 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4379 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4380 EVEX_CD8<32, CD8VH>;
4381 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4382 EVEX_CD8<32, CD8VH>;
4384 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4385 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4386 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4388 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4389 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4390 (VCVTPH2PSZrr VR256X:$src)>;
4392 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4393 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4394 "ucomiss">, PS, EVEX, VEX_LIG,
4395 EVEX_CD8<32, CD8VT1>;
4396 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4397 "ucomisd">, PD, EVEX,
4398 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4399 let Pattern = []<dag> in {
4400 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4401 "comiss">, PS, EVEX, VEX_LIG,
4402 EVEX_CD8<32, CD8VT1>;
4403 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4404 "comisd">, PD, EVEX,
4405 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4407 let isCodeGenOnly = 1 in {
4408 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4409 load, "ucomiss">, PS, EVEX, VEX_LIG,
4410 EVEX_CD8<32, CD8VT1>;
4411 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4412 load, "ucomisd">, PD, EVEX,
4413 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4415 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4416 load, "comiss">, PS, EVEX, VEX_LIG,
4417 EVEX_CD8<32, CD8VT1>;
4418 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4419 load, "comisd">, PD, EVEX,
4420 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4424 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4425 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4426 X86MemOperand x86memop> {
4427 let hasSideEffects = 0 in {
4428 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4429 (ins RC:$src1, RC:$src2),
4430 !strconcat(OpcodeStr,
4431 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4432 let mayLoad = 1 in {
4433 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4434 (ins RC:$src1, x86memop:$src2),
4435 !strconcat(OpcodeStr,
4436 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4441 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4442 EVEX_CD8<32, CD8VT1>;
4443 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4444 VEX_W, EVEX_CD8<64, CD8VT1>;
4445 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4446 EVEX_CD8<32, CD8VT1>;
4447 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4448 VEX_W, EVEX_CD8<64, CD8VT1>;
4450 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4451 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4452 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4453 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4455 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4456 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4457 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4458 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4460 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4461 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4462 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4463 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4465 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4466 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4467 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4468 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4470 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4471 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4472 X86VectorVTInfo _> {
4473 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4474 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4475 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4476 let mayLoad = 1 in {
4477 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4478 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4480 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4481 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4482 (ins _.ScalarMemOp:$src), OpcodeStr,
4483 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4485 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4490 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4491 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4492 EVEX_V512, EVEX_CD8<32, CD8VF>;
4493 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4494 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4496 // Define only if AVX512VL feature is present.
4497 let Predicates = [HasVLX] in {
4498 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4499 OpNode, v4f32x_info>,
4500 EVEX_V128, EVEX_CD8<32, CD8VF>;
4501 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4502 OpNode, v8f32x_info>,
4503 EVEX_V256, EVEX_CD8<32, CD8VF>;
4504 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4505 OpNode, v2f64x_info>,
4506 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4507 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4508 OpNode, v4f64x_info>,
4509 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4513 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4514 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4516 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4517 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4518 (VRSQRT14PSZr VR512:$src)>;
4519 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4520 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4521 (VRSQRT14PDZr VR512:$src)>;
4523 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4524 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4525 (VRCP14PSZr VR512:$src)>;
4526 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4527 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4528 (VRCP14PDZr VR512:$src)>;
4530 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4531 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4534 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4535 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4536 "$src2, $src1", "$src1, $src2",
4537 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4538 (i32 FROUND_CURRENT))>;
4540 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4541 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4542 "$src2, $src1", "$src1, $src2",
4543 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4544 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4546 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4547 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4548 "$src2, $src1", "$src1, $src2",
4549 (OpNode (_.VT _.RC:$src1),
4550 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4551 (i32 FROUND_CURRENT))>;
4554 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4555 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4556 EVEX_CD8<32, CD8VT1>;
4557 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4558 EVEX_CD8<64, CD8VT1>, VEX_W;
4561 let hasSideEffects = 0, Predicates = [HasERI] in {
4562 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4563 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4565 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4567 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4570 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4571 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4572 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4574 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4575 (ins _.RC:$src), OpcodeStr,
4577 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4580 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4581 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4583 (bitconvert (_.LdFrag addr:$src))),
4584 (i32 FROUND_CURRENT))>;
4586 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4587 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4589 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4590 (i32 FROUND_CURRENT))>, EVEX_B;
4593 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4594 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4595 EVEX_CD8<32, CD8VF>;
4596 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4597 VEX_W, EVEX_CD8<32, CD8VF>;
4600 let Predicates = [HasERI], hasSideEffects = 0 in {
4602 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4603 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4604 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4607 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4608 SDNode OpNode, X86VectorVTInfo _>{
4609 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4610 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4611 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4612 let mayLoad = 1 in {
4613 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4614 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4616 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4618 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4619 (ins _.ScalarMemOp:$src), OpcodeStr,
4620 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4622 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4627 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4628 Intrinsic F32Int, Intrinsic F64Int,
4629 OpndItins itins_s, OpndItins itins_d> {
4630 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4631 (ins FR32X:$src1, FR32X:$src2),
4632 !strconcat(OpcodeStr,
4633 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4634 [], itins_s.rr>, XS, EVEX_4V;
4635 let isCodeGenOnly = 1 in
4636 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4637 (ins VR128X:$src1, VR128X:$src2),
4638 !strconcat(OpcodeStr,
4639 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4641 (F32Int VR128X:$src1, VR128X:$src2))],
4642 itins_s.rr>, XS, EVEX_4V;
4643 let mayLoad = 1 in {
4644 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4645 (ins FR32X:$src1, f32mem:$src2),
4646 !strconcat(OpcodeStr,
4647 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4648 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4649 let isCodeGenOnly = 1 in
4650 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4651 (ins VR128X:$src1, ssmem:$src2),
4652 !strconcat(OpcodeStr,
4653 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4655 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4656 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4658 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4659 (ins FR64X:$src1, FR64X:$src2),
4660 !strconcat(OpcodeStr,
4661 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4663 let isCodeGenOnly = 1 in
4664 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4665 (ins VR128X:$src1, VR128X:$src2),
4666 !strconcat(OpcodeStr,
4667 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4669 (F64Int VR128X:$src1, VR128X:$src2))],
4670 itins_s.rr>, XD, EVEX_4V, VEX_W;
4671 let mayLoad = 1 in {
4672 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4673 (ins FR64X:$src1, f64mem:$src2),
4674 !strconcat(OpcodeStr,
4675 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4676 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4677 let isCodeGenOnly = 1 in
4678 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4679 (ins VR128X:$src1, sdmem:$src2),
4680 !strconcat(OpcodeStr,
4681 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4683 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4684 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4688 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4690 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4692 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4693 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4695 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4696 // Define only if AVX512VL feature is present.
4697 let Predicates = [HasVLX] in {
4698 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4699 OpNode, v4f32x_info>,
4700 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4701 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4702 OpNode, v8f32x_info>,
4703 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4704 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4705 OpNode, v2f64x_info>,
4706 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4707 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4708 OpNode, v4f64x_info>,
4709 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4713 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4715 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4716 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4717 SSE_SQRTSS, SSE_SQRTSD>;
4719 let Predicates = [HasAVX512] in {
4720 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4721 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4722 (VSQRTPSZr VR512:$src1)>;
4723 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4724 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4725 (VSQRTPDZr VR512:$src1)>;
4727 def : Pat<(f32 (fsqrt FR32X:$src)),
4728 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4729 def : Pat<(f32 (fsqrt (load addr:$src))),
4730 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4731 Requires<[OptForSize]>;
4732 def : Pat<(f64 (fsqrt FR64X:$src)),
4733 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4734 def : Pat<(f64 (fsqrt (load addr:$src))),
4735 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4736 Requires<[OptForSize]>;
4738 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4739 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4740 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4741 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4742 Requires<[OptForSize]>;
4744 def : Pat<(f32 (X86frcp FR32X:$src)),
4745 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4746 def : Pat<(f32 (X86frcp (load addr:$src))),
4747 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4748 Requires<[OptForSize]>;
4750 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4751 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4752 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4754 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4755 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4757 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4758 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4759 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4761 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4762 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4766 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4767 X86MemOperand x86memop, RegisterClass RC,
4768 PatFrag mem_frag, Domain d> {
4769 let ExeDomain = d in {
4770 // Intrinsic operation, reg.
4771 // Vector intrinsic operation, reg
4772 def r : AVX512AIi8<opc, MRMSrcReg,
4773 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
4774 !strconcat(OpcodeStr,
4775 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4778 // Vector intrinsic operation, mem
4779 def m : AVX512AIi8<opc, MRMSrcMem,
4780 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
4781 !strconcat(OpcodeStr,
4782 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4787 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4788 loadv16f32, SSEPackedSingle>, EVEX_V512,
4789 EVEX_CD8<32, CD8VF>;
4791 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4792 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4794 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4797 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4798 loadv8f64, SSEPackedDouble>, EVEX_V512,
4799 VEX_W, EVEX_CD8<64, CD8VF>;
4801 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4802 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4804 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4807 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
4809 let ExeDomain = _.ExeDomain in {
4810 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4811 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
4812 "$src3, $src2, $src1", "$src1, $src2, $src3",
4813 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4814 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
4816 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4817 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
4818 "$src3, $src2, $src1", "$src1, $src2, $src3",
4819 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4820 (i32 imm:$src3), (i32 FROUND_NO_EXC))), "{sae}">, EVEX_B;
4823 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4824 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
4825 "$src3, $src2, $src1", "$src1, $src2, $src3",
4826 (_.VT (X86RndScale (_.VT _.RC:$src1),
4827 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4828 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
4830 let Predicates = [HasAVX512] in {
4831 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
4832 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4833 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
4834 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
4835 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4836 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
4837 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
4838 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4839 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
4840 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
4841 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4842 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
4843 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
4844 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
4845 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
4847 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4848 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4849 addr:$src, (i32 0x1))), _.FRC)>;
4850 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4851 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4852 addr:$src, (i32 0x2))), _.FRC)>;
4853 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4854 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4855 addr:$src, (i32 0x3))), _.FRC)>;
4856 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4857 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4858 addr:$src, (i32 0x4))), _.FRC)>;
4859 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
4860 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
4861 addr:$src, (i32 0xc))), _.FRC)>;
4865 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
4866 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4868 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
4869 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
4871 let Predicates = [HasAVX512] in {
4872 def : Pat<(v16f32 (ffloor VR512:$src)),
4873 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4874 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4875 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4876 def : Pat<(v16f32 (fceil VR512:$src)),
4877 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4878 def : Pat<(v16f32 (frint VR512:$src)),
4879 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4880 def : Pat<(v16f32 (ftrunc VR512:$src)),
4881 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4883 def : Pat<(v8f64 (ffloor VR512:$src)),
4884 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4885 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4886 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4887 def : Pat<(v8f64 (fceil VR512:$src)),
4888 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4889 def : Pat<(v8f64 (frint VR512:$src)),
4890 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4891 def : Pat<(v8f64 (ftrunc VR512:$src)),
4892 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4894 //-------------------------------------------------
4895 // Integer truncate and extend operations
4896 //-------------------------------------------------
4898 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4899 RegisterClass dstRC, RegisterClass srcRC,
4900 RegisterClass KRC, X86MemOperand x86memop> {
4901 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4903 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4906 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4907 (ins KRC:$mask, srcRC:$src),
4908 !strconcat(OpcodeStr,
4909 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4912 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4913 (ins KRC:$mask, srcRC:$src),
4914 !strconcat(OpcodeStr,
4915 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4918 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4919 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4922 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4923 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4924 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4928 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4929 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4930 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4931 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4932 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4933 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4934 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4935 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4936 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4937 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4938 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4939 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4940 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4941 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4942 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4943 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4944 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4945 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4946 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4947 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4948 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4949 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4950 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4951 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4952 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4953 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4954 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4955 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4956 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4957 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4959 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4960 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4961 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4962 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4963 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4965 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4966 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4967 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4968 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4969 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4970 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4971 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4972 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4975 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4976 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4977 PatFrag mem_frag, X86MemOperand x86memop,
4978 ValueType OpVT, ValueType InVT> {
4980 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4982 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4983 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4985 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4986 (ins KRC:$mask, SrcRC:$src),
4987 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4990 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4991 (ins KRC:$mask, SrcRC:$src),
4992 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4995 let mayLoad = 1 in {
4996 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4997 (ins x86memop:$src),
4998 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5000 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
5003 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5004 (ins KRC:$mask, x86memop:$src),
5005 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
5009 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5010 (ins KRC:$mask, x86memop:$src),
5011 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5017 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
5018 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
5020 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
5021 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
5023 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
5024 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
5025 EVEX_CD8<16, CD8VH>;
5026 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
5027 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
5028 EVEX_CD8<16, CD8VQ>;
5029 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
5030 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
5031 EVEX_CD8<32, CD8VH>;
5033 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
5034 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
5036 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
5037 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
5039 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
5040 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
5041 EVEX_CD8<16, CD8VH>;
5042 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
5043 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
5044 EVEX_CD8<16, CD8VQ>;
5045 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
5046 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
5047 EVEX_CD8<32, CD8VH>;
5049 //===----------------------------------------------------------------------===//
5050 // GATHER - SCATTER Operations
5052 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
5053 RegisterClass RC, X86MemOperand memop> {
5055 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
5056 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
5057 (ins RC:$src1, KRC:$mask, memop:$src2),
5058 !strconcat(OpcodeStr,
5059 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5063 let ExeDomain = SSEPackedDouble in {
5064 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
5065 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5066 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
5067 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5070 let ExeDomain = SSEPackedSingle in {
5071 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
5072 EVEX_V512, EVEX_CD8<32, CD8VT1>;
5073 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
5074 EVEX_V512, EVEX_CD8<32, CD8VT1>;
5077 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
5078 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5079 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
5080 EVEX_V512, EVEX_CD8<32, CD8VT1>;
5082 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
5083 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5084 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
5085 EVEX_V512, EVEX_CD8<32, CD8VT1>;
5087 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
5088 RegisterClass RC, X86MemOperand memop> {
5089 let mayStore = 1, Constraints = "$mask = $mask_wb" in
5090 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
5091 (ins memop:$dst, KRC:$mask, RC:$src2),
5092 !strconcat(OpcodeStr,
5093 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5097 let ExeDomain = SSEPackedDouble in {
5098 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
5099 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5100 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
5101 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5104 let ExeDomain = SSEPackedSingle in {
5105 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
5106 EVEX_V512, EVEX_CD8<32, CD8VT1>;
5107 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
5108 EVEX_V512, EVEX_CD8<32, CD8VT1>;
5111 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
5112 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5113 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
5114 EVEX_V512, EVEX_CD8<32, CD8VT1>;
5116 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
5117 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5118 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
5119 EVEX_V512, EVEX_CD8<32, CD8VT1>;
5122 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
5123 RegisterClass KRC, X86MemOperand memop> {
5124 let Predicates = [HasPFI], hasSideEffects = 1 in
5125 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
5126 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
5130 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
5131 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5133 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5134 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5136 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5137 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5139 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
5140 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5142 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
5143 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5145 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
5146 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5148 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5149 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5151 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5152 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5154 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5155 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5157 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5158 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5160 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5161 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5163 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5164 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5166 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5167 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5169 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5170 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5172 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5173 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5175 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5176 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5177 //===----------------------------------------------------------------------===//
5178 // VSHUFPS - VSHUFPD Operations
5180 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5181 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5183 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5184 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5185 !strconcat(OpcodeStr,
5186 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5187 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5188 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5189 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5190 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5191 (ins RC:$src1, RC:$src2, u8imm:$src3),
5192 !strconcat(OpcodeStr,
5193 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5194 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5195 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5196 EVEX_4V, Sched<[WriteShuffle]>;
5199 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5200 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5201 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5202 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5204 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5205 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5206 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5207 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5208 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5210 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5211 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5212 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5213 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5214 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5216 multiclass avx512_valign<X86VectorVTInfo _> {
5217 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5218 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5220 "$src3, $src2, $src1", "$src1, $src2, $src3",
5221 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5223 AVX512AIi8Base, EVEX_4V;
5225 // Also match valign of packed floats.
5226 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5227 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5230 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5231 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5232 !strconcat("valign"##_.Suffix,
5233 "\t{$src3, $src2, $src1, $dst|"
5234 "$dst, $src1, $src2, $src3}"),
5237 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5238 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5240 // Helper fragments to match sext vXi1 to vXiY.
5241 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5242 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5244 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5245 RegisterClass KRC, RegisterClass RC,
5246 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5248 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5249 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5251 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5252 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5254 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5255 !strconcat(OpcodeStr,
5256 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5258 let mayLoad = 1 in {
5259 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5260 (ins x86memop:$src),
5261 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5263 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5264 (ins KRC:$mask, x86memop:$src),
5265 !strconcat(OpcodeStr,
5266 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5268 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5269 (ins KRC:$mask, x86memop:$src),
5270 !strconcat(OpcodeStr,
5271 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5273 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5274 (ins x86scalar_mop:$src),
5275 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5276 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5278 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5279 (ins KRC:$mask, x86scalar_mop:$src),
5280 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5281 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5282 []>, EVEX, EVEX_B, EVEX_K;
5283 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5284 (ins KRC:$mask, x86scalar_mop:$src),
5285 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5286 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5288 []>, EVEX, EVEX_B, EVEX_KZ;
5292 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5293 i512mem, i32mem, "{1to16}">, EVEX_V512,
5294 EVEX_CD8<32, CD8VF>;
5295 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5296 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5297 EVEX_CD8<64, CD8VF>;
5300 (bc_v16i32 (v16i1sextv16i32)),
5301 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5302 (VPABSDZrr VR512:$src)>;
5304 (bc_v8i64 (v8i1sextv8i64)),
5305 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5306 (VPABSQZrr VR512:$src)>;
5308 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5309 (v16i32 immAllZerosV), (i16 -1))),
5310 (VPABSDZrr VR512:$src)>;
5311 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5312 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5313 (VPABSQZrr VR512:$src)>;
5315 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5316 RegisterClass RC, RegisterClass KRC,
5317 X86MemOperand x86memop,
5318 X86MemOperand x86scalar_mop, string BrdcstStr> {
5319 let hasSideEffects = 0 in {
5320 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5322 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5325 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5326 (ins x86memop:$src),
5327 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5330 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5331 (ins x86scalar_mop:$src),
5332 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5333 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5335 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5336 (ins KRC:$mask, RC:$src),
5337 !strconcat(OpcodeStr,
5338 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5341 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5342 (ins KRC:$mask, x86memop:$src),
5343 !strconcat(OpcodeStr,
5344 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5347 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5348 (ins KRC:$mask, x86scalar_mop:$src),
5349 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5350 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5352 []>, EVEX, EVEX_KZ, EVEX_B;
5354 let Constraints = "$src1 = $dst" in {
5355 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5356 (ins RC:$src1, KRC:$mask, RC:$src2),
5357 !strconcat(OpcodeStr,
5358 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5361 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5362 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5363 !strconcat(OpcodeStr,
5364 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5367 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5368 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5369 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5370 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5371 []>, EVEX, EVEX_K, EVEX_B;
5376 let Predicates = [HasCDI] in {
5377 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5378 i512mem, i32mem, "{1to16}">,
5379 EVEX_V512, EVEX_CD8<32, CD8VF>;
5382 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5383 i512mem, i64mem, "{1to8}">,
5384 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5388 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5390 (VPCONFLICTDrrk VR512:$src1,
5391 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5393 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5395 (VPCONFLICTQrrk VR512:$src1,
5396 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5398 let Predicates = [HasCDI] in {
5399 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5400 i512mem, i32mem, "{1to16}">,
5401 EVEX_V512, EVEX_CD8<32, CD8VF>;
5404 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5405 i512mem, i64mem, "{1to8}">,
5406 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5410 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5412 (VPLZCNTDrrk VR512:$src1,
5413 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5415 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5417 (VPLZCNTQrrk VR512:$src1,
5418 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5420 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5421 (VPLZCNTDrm addr:$src)>;
5422 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5423 (VPLZCNTDrr VR512:$src)>;
5424 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5425 (VPLZCNTQrm addr:$src)>;
5426 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5427 (VPLZCNTQrr VR512:$src)>;
5429 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5430 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5431 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5433 def : Pat<(store VK1:$src, addr:$dst),
5435 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5436 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5438 def : Pat<(store VK8:$src, addr:$dst),
5440 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5441 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5443 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5444 (truncstore node:$val, node:$ptr), [{
5445 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5448 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5449 (MOV8mr addr:$dst, GR8:$src)>;
5451 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5452 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5453 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5454 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5457 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5458 string OpcodeStr, Predicate prd> {
5459 let Predicates = [prd] in
5460 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5462 let Predicates = [prd, HasVLX] in {
5463 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5464 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5468 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5469 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5471 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5473 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5475 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5479 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5481 //===----------------------------------------------------------------------===//
5482 // AVX-512 - COMPRESS and EXPAND
5484 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5486 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5487 (ins _.KRCWM:$mask, _.RC:$src),
5488 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5489 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5490 _.ImmAllZerosV)))]>, EVEX_KZ;
5492 let Constraints = "$src0 = $dst" in
5493 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5494 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5495 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5496 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5497 _.RC:$src0)))]>, EVEX_K;
5499 let mayStore = 1 in {
5500 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5501 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5502 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5503 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5505 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5509 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5510 AVX512VLVectorVTInfo VTInfo> {
5511 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5513 let Predicates = [HasVLX] in {
5514 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5515 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5519 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5521 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5523 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5525 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5529 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5531 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5532 (ins _.KRCWM:$mask, _.RC:$src),
5533 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5534 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5535 _.ImmAllZerosV)))]>, EVEX_KZ;
5537 let Constraints = "$src0 = $dst" in
5538 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5539 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5540 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5541 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5542 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5544 let mayLoad = 1, Constraints = "$src0 = $dst" in
5545 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5546 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5547 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5548 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5550 (_.LdFrag addr:$src))),
5552 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5555 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5556 (ins _.KRCWM:$mask, _.MemOp:$src),
5557 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5558 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5559 (_.VT (bitconvert (_.LdFrag addr:$src))),
5560 _.ImmAllZerosV)))]>,
5561 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5565 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5566 AVX512VLVectorVTInfo VTInfo> {
5567 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5569 let Predicates = [HasVLX] in {
5570 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5571 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5575 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5577 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5579 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5581 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,