1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 // Similar to AVX512_maskable_3rc but in this case the input VT for the tied
280 // operand differs from the output VT. This requires a bitconvert on
281 // the preserved vector going into the vselect.
282 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
283 X86VectorVTInfo InVT,
284 dag Outs, dag NonTiedIns, string OpcodeStr,
285 string AttSrcAsm, string IntelSrcAsm,
287 AVX512_maskable_common<O, F, OutVT, Outs,
288 !con((ins InVT.RC:$src1), NonTiedIns),
289 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
290 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
291 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
292 (vselect InVT.KRCWM:$mask, RHS,
293 (bitconvert InVT.RC:$src1))>;
295 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
296 dag Outs, dag NonTiedIns, string OpcodeStr,
297 string AttSrcAsm, string IntelSrcAsm,
299 AVX512_maskable_common<O, F, _, Outs,
300 !con((ins _.RC:$src1), NonTiedIns),
301 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
302 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
303 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
304 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
306 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
309 string AttSrcAsm, string IntelSrcAsm,
311 AVX512_maskable_custom<O, F, Outs, Ins,
312 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
313 !con((ins _.KRCWM:$mask), Ins),
314 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
318 // Instruction with mask that puts result in mask register,
319 // like "compare" and "vptest"
320 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
322 dag Ins, dag MaskingIns,
324 string AttSrcAsm, string IntelSrcAsm,
326 list<dag> MaskingPattern,
328 InstrItinClass itin = NoItinerary> {
329 def NAME: AVX512<O, F, Outs, Ins,
330 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
331 "$dst "#Round#", "#IntelSrcAsm#"}",
334 def NAME#k: AVX512<O, F, Outs, MaskingIns,
335 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
336 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
337 MaskingPattern, itin>, EVEX_K;
340 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
342 dag Ins, dag MaskingIns,
344 string AttSrcAsm, string IntelSrcAsm,
345 dag RHS, dag MaskingRHS,
347 InstrItinClass itin = NoItinerary> :
348 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
349 AttSrcAsm, IntelSrcAsm,
350 [(set _.KRC:$dst, RHS)],
351 [(set _.KRC:$dst, MaskingRHS)],
354 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
355 dag Outs, dag Ins, string OpcodeStr,
356 string AttSrcAsm, string IntelSrcAsm,
357 dag RHS, string Round = "",
358 InstrItinClass itin = NoItinerary> :
359 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
360 !con((ins _.KRCWM:$mask), Ins),
361 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
362 (and _.KRCWM:$mask, RHS),
365 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
366 dag Outs, dag Ins, string OpcodeStr,
367 string AttSrcAsm, string IntelSrcAsm> :
368 AVX512_maskable_custom_cmp<O, F, Outs,
369 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
370 AttSrcAsm, IntelSrcAsm,
371 [],[],"", NoItinerary>;
373 // Bitcasts between 512-bit vector types. Return the original type since
374 // no instruction is needed for the conversion
375 let Predicates = [HasAVX512] in {
376 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
377 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
378 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
379 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
380 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
381 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
382 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
383 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
384 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
385 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
386 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
387 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
388 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
389 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
390 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
391 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
392 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
393 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
394 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
395 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
396 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
397 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
398 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
399 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
400 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
401 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
402 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
403 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
404 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
405 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
406 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
408 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
409 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
410 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
411 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
412 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
413 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
414 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
415 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
416 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
417 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
418 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
419 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
420 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
421 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
422 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
423 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
424 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
425 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
426 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
427 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
428 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
429 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
430 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
431 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
432 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
433 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
434 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
435 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
436 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
437 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
439 // Bitcasts between 256-bit vector types. Return the original type since
440 // no instruction is needed for the conversion
441 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
442 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
443 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
444 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
445 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
446 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
447 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
448 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
449 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
450 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
451 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
452 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
453 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
454 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
455 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
456 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
457 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
458 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
459 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
460 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
461 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
462 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
463 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
464 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
465 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
466 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
467 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
468 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
469 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
470 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
474 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
477 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
478 isPseudo = 1, Predicates = [HasAVX512] in {
479 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
480 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
483 let Predicates = [HasAVX512] in {
484 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
485 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
486 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
489 //===----------------------------------------------------------------------===//
490 // AVX-512 - VECTOR INSERT
492 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
493 PatFrag vinsert_insert> {
494 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
495 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
496 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
497 "vinsert" # From.EltTypeName # "x" # From.NumElts,
498 "$src3, $src2, $src1", "$src1, $src2, $src3",
499 (vinsert_insert:$src3 (To.VT To.RC:$src1),
500 (From.VT From.RC:$src2),
501 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
504 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
505 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
506 "vinsert" # From.EltTypeName # "x" # From.NumElts,
507 "$src3, $src2, $src1", "$src1, $src2, $src3",
508 (vinsert_insert:$src3 (To.VT To.RC:$src1),
509 (From.VT (bitconvert (From.LdFrag addr:$src2))),
510 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
511 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
515 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
516 X86VectorVTInfo To, PatFrag vinsert_insert,
517 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
518 let Predicates = p in {
519 def : Pat<(vinsert_insert:$ins
520 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
521 (To.VT (!cast<Instruction>(InstrStr#"rr")
522 To.RC:$src1, From.RC:$src2,
523 (INSERT_get_vinsert_imm To.RC:$ins)))>;
525 def : Pat<(vinsert_insert:$ins
527 (From.VT (bitconvert (From.LdFrag addr:$src2))),
529 (To.VT (!cast<Instruction>(InstrStr#"rm")
530 To.RC:$src1, addr:$src2,
531 (INSERT_get_vinsert_imm To.RC:$ins)))>;
535 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
536 ValueType EltVT64, int Opcode256> {
538 let Predicates = [HasVLX] in
539 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 4, EltVT32, VR128X>,
541 X86VectorVTInfo< 8, EltVT32, VR256X>,
542 vinsert128_insert>, EVEX_V256;
544 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
545 X86VectorVTInfo< 4, EltVT32, VR128X>,
546 X86VectorVTInfo<16, EltVT32, VR512>,
547 vinsert128_insert>, EVEX_V512;
549 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
550 X86VectorVTInfo< 4, EltVT64, VR256X>,
551 X86VectorVTInfo< 8, EltVT64, VR512>,
552 vinsert256_insert>, VEX_W, EVEX_V512;
554 let Predicates = [HasVLX, HasDQI] in
555 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
556 X86VectorVTInfo< 2, EltVT64, VR128X>,
557 X86VectorVTInfo< 4, EltVT64, VR256X>,
558 vinsert128_insert>, VEX_W, EVEX_V256;
560 let Predicates = [HasDQI] in {
561 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
562 X86VectorVTInfo< 2, EltVT64, VR128X>,
563 X86VectorVTInfo< 8, EltVT64, VR512>,
564 vinsert128_insert>, VEX_W, EVEX_V512;
566 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
567 X86VectorVTInfo< 8, EltVT32, VR256X>,
568 X86VectorVTInfo<16, EltVT32, VR512>,
569 vinsert256_insert>, EVEX_V512;
573 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
574 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
576 // Codegen pattern with the alternative types,
577 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
578 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
583 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
588 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
593 // Codegen pattern with the alternative types insert VEC128 into VEC256
594 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
595 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
596 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
597 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
598 // Codegen pattern with the alternative types insert VEC128 into VEC512
599 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
600 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
601 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
602 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
603 // Codegen pattern with the alternative types insert VEC256 into VEC512
604 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
605 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
606 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
607 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
609 // vinsertps - insert f32 to XMM
610 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
611 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
612 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
613 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
615 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
616 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
617 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
618 [(set VR128X:$dst, (X86insertps VR128X:$src1,
619 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
620 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
622 //===----------------------------------------------------------------------===//
623 // AVX-512 VECTOR EXTRACT
626 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
627 X86VectorVTInfo To> {
628 // A subvector extract from the first vector position is
629 // a subregister copy that needs no instruction.
630 def NAME # To.NumElts:
631 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
632 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
635 multiclass vextract_for_size<int Opcode,
636 X86VectorVTInfo From, X86VectorVTInfo To,
637 PatFrag vextract_extract> :
638 vextract_for_size_first_position_lowering<From, To> {
640 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
641 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
642 // vextract_extract), we interesting only in patterns without mask,
643 // intrinsics pattern match generated bellow.
644 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
645 (ins From.RC:$src1, i32u8imm:$idx),
646 "vextract" # To.EltTypeName # "x" # To.NumElts,
647 "$idx, $src1", "$src1, $idx",
648 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
650 AVX512AIi8Base, EVEX;
651 let mayStore = 1 in {
652 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
653 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
654 "vextract" # To.EltTypeName # "x" # To.NumElts #
655 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
658 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
659 (ins To.MemOp:$dst, To.KRCWM:$mask,
660 From.RC:$src1, i32u8imm:$src2),
661 "vextract" # To.EltTypeName # "x" # To.NumElts #
662 "\t{$src2, $src1, $dst {${mask}}|"
663 "$dst {${mask}}, $src1, $src2}",
668 // Intrinsic call with masking.
669 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
670 "x" # To.NumElts # "_" # From.Size)
671 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
672 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
673 From.ZSuffix # "rrk")
675 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
676 From.RC:$src1, imm:$idx)>;
678 // Intrinsic call with zero-masking.
679 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
680 "x" # To.NumElts # "_" # From.Size)
681 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
682 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
683 From.ZSuffix # "rrkz")
684 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
685 From.RC:$src1, imm:$idx)>;
687 // Intrinsic call without masking.
688 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
689 "x" # To.NumElts # "_" # From.Size)
690 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
691 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
693 From.RC:$src1, imm:$idx)>;
696 // Codegen pattern for the alternative types
697 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
698 X86VectorVTInfo To, PatFrag vextract_extract,
699 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
700 vextract_for_size_first_position_lowering<From, To> {
702 let Predicates = p in
703 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
704 (To.VT (!cast<Instruction>(InstrStr#"rr")
706 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
709 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
710 ValueType EltVT64, int Opcode256> {
711 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
712 X86VectorVTInfo<16, EltVT32, VR512>,
713 X86VectorVTInfo< 4, EltVT32, VR128X>,
714 vextract128_extract>,
715 EVEX_V512, EVEX_CD8<32, CD8VT4>;
716 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
717 X86VectorVTInfo< 8, EltVT64, VR512>,
718 X86VectorVTInfo< 4, EltVT64, VR256X>,
719 vextract256_extract>,
720 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
721 let Predicates = [HasVLX] in
722 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
723 X86VectorVTInfo< 8, EltVT32, VR256X>,
724 X86VectorVTInfo< 4, EltVT32, VR128X>,
725 vextract128_extract>,
726 EVEX_V256, EVEX_CD8<32, CD8VT4>;
727 let Predicates = [HasVLX, HasDQI] in
728 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
729 X86VectorVTInfo< 4, EltVT64, VR256X>,
730 X86VectorVTInfo< 2, EltVT64, VR128X>,
731 vextract128_extract>,
732 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
733 let Predicates = [HasDQI] in {
734 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
735 X86VectorVTInfo< 8, EltVT64, VR512>,
736 X86VectorVTInfo< 2, EltVT64, VR128X>,
737 vextract128_extract>,
738 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
739 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
740 X86VectorVTInfo<16, EltVT32, VR512>,
741 X86VectorVTInfo< 8, EltVT32, VR256X>,
742 vextract256_extract>,
743 EVEX_V512, EVEX_CD8<32, CD8VT8>;
747 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
748 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
750 // extract_subvector codegen patterns with the alternative types.
751 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
752 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
757 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
762 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
763 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
764 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
765 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
767 // Codegen pattern with the alternative types extract VEC128 from VEC512
768 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
769 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
770 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
771 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
772 // Codegen pattern with the alternative types extract VEC256 from VEC512
773 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
774 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
775 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
776 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
778 // A 128-bit subvector insert to the first 512-bit vector position
779 // is a subregister copy that needs no instruction.
780 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
781 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
782 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
784 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
785 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
786 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
788 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
789 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
790 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
792 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
793 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
794 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
797 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
798 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
799 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
800 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
801 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
802 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
803 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
804 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
805 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
806 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
807 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
808 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
810 // vextractps - extract 32 bits from XMM
811 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
812 (ins VR128X:$src1, u8imm:$src2),
813 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
817 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
818 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
819 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
820 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
821 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
823 //===---------------------------------------------------------------------===//
827 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
830 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
831 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
832 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
835 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
836 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
837 (DestInfo.VT (X86VBroadcast
838 (SrcInfo.ScalarLdFrag addr:$src)))>,
839 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
842 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
843 AVX512VLVectorVTInfo _> {
844 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
847 let Predicates = [HasVLX] in {
848 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
853 let ExeDomain = SSEPackedSingle in {
854 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
856 let Predicates = [HasVLX] in {
857 defm VBROADCASTSSZ128 : avx512_broadcast_rm<0x18, "vbroadcastss",
858 v4f32x_info, v4f32x_info>, EVEX_V128;
862 let ExeDomain = SSEPackedDouble in {
863 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, "vbroadcastsd",
864 avx512vl_f64_info>, VEX_W;
867 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
868 // Later, we can canonize broadcast instructions before ISel phase and
869 // eliminate additional patterns on ISel.
870 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
871 // representations of source
872 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
873 X86VectorVTInfo _, RegisterClass SrcRC_v,
874 RegisterClass SrcRC_s> {
875 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
876 (!cast<Instruction>(InstName##"r")
877 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
879 let AddedComplexity = 30 in {
880 def : Pat<(_.VT (vselect _.KRCWM:$mask,
881 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
882 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
883 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
885 def : Pat<(_.VT(vselect _.KRCWM:$mask,
886 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
887 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
888 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
892 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
894 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
897 let Predicates = [HasVLX] in {
898 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
899 v8f32x_info, VR128X, FR32X>;
900 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
901 v4f32x_info, VR128X, FR32X>;
902 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
903 v4f64x_info, VR128X, FR64X>;
906 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
907 (VBROADCASTSSZm addr:$src)>;
908 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
909 (VBROADCASTSDZm addr:$src)>;
911 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
912 (VBROADCASTSSZm addr:$src)>;
913 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
914 (VBROADCASTSDZm addr:$src)>;
916 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
917 RegisterClass SrcRC> {
918 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
919 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
920 "$src", "$src", []>, T8PD, EVEX;
923 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
924 RegisterClass SrcRC, Predicate prd> {
925 let Predicates = [prd] in
926 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
927 let Predicates = [prd, HasVLX] in {
928 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
929 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
933 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
935 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
937 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
939 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
942 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
943 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
945 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
946 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
948 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
949 (VPBROADCASTDrZr GR32:$src)>;
950 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
951 (VPBROADCASTQrZr GR64:$src)>;
953 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
954 (VPBROADCASTDrZr GR32:$src)>;
955 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
956 (VPBROADCASTQrZr GR64:$src)>;
958 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
959 (v16i32 immAllZerosV), (i16 GR16:$mask))),
960 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
961 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
962 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
963 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
965 // Provide aliases for broadcast from the same register class that
966 // automatically does the extract.
967 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
968 X86VectorVTInfo SrcInfo> {
969 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
970 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
971 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
974 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
975 AVX512VLVectorVTInfo _, Predicate prd> {
976 let Predicates = [prd] in {
977 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
978 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
980 // Defined separately to avoid redefinition.
981 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
983 let Predicates = [prd, HasVLX] in {
984 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
985 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
987 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
992 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
993 avx512vl_i8_info, HasBWI>;
994 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
995 avx512vl_i16_info, HasBWI>;
996 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
997 avx512vl_i32_info, HasAVX512>;
998 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
999 avx512vl_i64_info, HasAVX512>, VEX_W;
1001 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
1002 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
1004 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1005 (ins _Src.MemOp:$src), OpcodeStr, "$src", "$src",
1006 (_Dst.VT (X86SubVBroadcast
1007 (_Src.VT (bitconvert (_Src.LdFrag addr:$src)))))>,
1011 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1012 v16i32_info, v4i32x_info>,
1013 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1014 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1015 v16f32_info, v4f32x_info>,
1016 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1017 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1018 v8i64_info, v4i64x_info>, VEX_W,
1019 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1020 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1021 v8f64_info, v4f64x_info>, VEX_W,
1022 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1024 let Predicates = [HasVLX] in {
1025 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1026 v8i32x_info, v4i32x_info>,
1027 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1028 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1029 v8f32x_info, v4f32x_info>,
1030 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1032 let Predicates = [HasVLX, HasDQI] in {
1033 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1034 v4i64x_info, v2i64x_info>, VEX_W,
1035 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1036 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1037 v4f64x_info, v2f64x_info>, VEX_W,
1038 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1040 let Predicates = [HasDQI] in {
1041 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1042 v8i64_info, v2i64x_info>, VEX_W,
1043 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1044 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1045 v16i32_info, v8i32x_info>,
1046 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1047 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1048 v8f64_info, v2f64x_info>, VEX_W,
1049 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1050 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1051 v16f32_info, v8f32x_info>,
1052 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1055 multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
1056 X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
1057 SDNode OpNode = X86SubVBroadcast> {
1059 defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
1060 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
1061 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1064 defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1065 (ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
1067 (_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
1068 T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
1071 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1072 AVX512VLVectorVTInfo _> {
1073 let Predicates = [HasDQI] in
1074 defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
1076 let Predicates = [HasDQI, HasVLX] in
1077 defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
1081 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1082 AVX512VLVectorVTInfo _> :
1083 avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
1085 let Predicates = [HasDQI, HasVLX] in
1086 defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
1087 X86SubV32x2Broadcast>, EVEX_V128;
1090 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1092 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1095 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1096 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1097 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1098 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1100 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1101 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1102 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1103 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1105 // Provide fallback in case the load node that is used in the patterns above
1106 // is used by additional users, which prevents the pattern selection.
1107 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1108 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1109 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1110 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1113 //===----------------------------------------------------------------------===//
1114 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1116 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1117 X86VectorVTInfo _, RegisterClass KRC> {
1118 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1120 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1123 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1124 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1125 let Predicates = [HasCDI] in
1126 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1127 let Predicates = [HasCDI, HasVLX] in {
1128 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1129 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1133 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1134 avx512vl_i32_info, VK16>;
1135 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1136 avx512vl_i64_info, VK8>, VEX_W;
1138 //===----------------------------------------------------------------------===//
1139 // -- VPERMI2 - 3 source operands form --
1140 multiclass avx512_perm_i<bits<8> opc, string OpcodeStr,
1141 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1142 let Constraints = "$src1 = $dst" in {
1143 defm rr: AVX512_maskable_3src_cast<opc, MRMSrcReg, _, IdxVT, (outs _.RC:$dst),
1144 (ins _.RC:$src2, _.RC:$src3),
1145 OpcodeStr, "$src3, $src2", "$src2, $src3",
1146 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1150 defm rm: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1151 (ins _.RC:$src2, _.MemOp:$src3),
1152 OpcodeStr, "$src3, $src2", "$src2, $src3",
1153 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2,
1154 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1155 EVEX_4V, AVX5128IBase;
1158 multiclass avx512_perm_i_mb<bits<8> opc, string OpcodeStr,
1159 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1160 let mayLoad = 1, Constraints = "$src1 = $dst" in
1161 defm rmb: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1162 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1163 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1164 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1165 (_.VT (X86VPermi2X IdxVT.RC:$src1,
1166 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1167 AVX5128IBase, EVEX_4V, EVEX_B;
1170 multiclass avx512_perm_i_sizes<bits<8> opc, string OpcodeStr,
1171 AVX512VLVectorVTInfo VTInfo,
1172 AVX512VLVectorVTInfo ShuffleMask> {
1173 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1174 ShuffleMask.info512>,
1175 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info512,
1176 ShuffleMask.info512>, EVEX_V512;
1177 let Predicates = [HasVLX] in {
1178 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1179 ShuffleMask.info128>,
1180 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info128,
1181 ShuffleMask.info128>, EVEX_V128;
1182 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1183 ShuffleMask.info256>,
1184 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info256,
1185 ShuffleMask.info256>, EVEX_V256;
1189 multiclass avx512_perm_i_sizes_w<bits<8> opc, string OpcodeStr,
1190 AVX512VLVectorVTInfo VTInfo,
1191 AVX512VLVectorVTInfo Idx> {
1192 let Predicates = [HasBWI] in
1193 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1194 Idx.info512>, EVEX_V512;
1195 let Predicates = [HasBWI, HasVLX] in {
1196 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1197 Idx.info128>, EVEX_V128;
1198 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1199 Idx.info256>, EVEX_V256;
1203 defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d",
1204 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1205 defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q",
1206 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1207 defm VPERMI2W : avx512_perm_i_sizes_w<0x75, "vpermi2w",
1208 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1209 defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps",
1210 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1211 defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd",
1212 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1215 multiclass avx512_perm_t<bits<8> opc, string OpcodeStr,
1216 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1217 let Constraints = "$src1 = $dst" in {
1218 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1219 (ins IdxVT.RC:$src2, _.RC:$src3),
1220 OpcodeStr, "$src3, $src2", "$src2, $src3",
1221 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3))>, EVEX_4V,
1225 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1226 (ins IdxVT.RC:$src2, _.MemOp:$src3),
1227 OpcodeStr, "$src3, $src2", "$src2, $src3",
1228 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2,
1229 (bitconvert (_.LdFrag addr:$src3))))>,
1230 EVEX_4V, AVX5128IBase;
1233 multiclass avx512_perm_t_mb<bits<8> opc, string OpcodeStr,
1234 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1235 let mayLoad = 1, Constraints = "$src1 = $dst" in
1236 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1237 (ins IdxVT.RC:$src2, _.ScalarMemOp:$src3),
1238 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1239 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1240 (_.VT (X86VPermt2 _.RC:$src1,
1241 IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1242 AVX5128IBase, EVEX_4V, EVEX_B;
1245 multiclass avx512_perm_t_sizes<bits<8> opc, string OpcodeStr,
1246 AVX512VLVectorVTInfo VTInfo,
1247 AVX512VLVectorVTInfo ShuffleMask> {
1248 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1249 ShuffleMask.info512>,
1250 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info512,
1251 ShuffleMask.info512>, EVEX_V512;
1252 let Predicates = [HasVLX] in {
1253 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1254 ShuffleMask.info128>,
1255 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info128,
1256 ShuffleMask.info128>, EVEX_V128;
1257 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1258 ShuffleMask.info256>,
1259 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info256,
1260 ShuffleMask.info256>, EVEX_V256;
1264 multiclass avx512_perm_t_sizes_w<bits<8> opc, string OpcodeStr,
1265 AVX512VLVectorVTInfo VTInfo,
1266 AVX512VLVectorVTInfo Idx> {
1267 let Predicates = [HasBWI] in
1268 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1269 Idx.info512>, EVEX_V512;
1270 let Predicates = [HasBWI, HasVLX] in {
1271 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1272 Idx.info128>, EVEX_V128;
1273 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1274 Idx.info256>, EVEX_V256;
1278 defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d",
1279 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1280 defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q",
1281 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1282 defm VPERMT2W : avx512_perm_t_sizes_w<0x7D, "vpermt2w",
1283 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1284 defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps",
1285 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1286 defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd",
1287 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1289 //===----------------------------------------------------------------------===//
1290 // AVX-512 - BLEND using mask
1292 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1293 let ExeDomain = _.ExeDomain in {
1294 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1295 (ins _.RC:$src1, _.RC:$src2),
1296 !strconcat(OpcodeStr,
1297 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1299 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1300 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1301 !strconcat(OpcodeStr,
1302 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1303 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1304 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1305 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1306 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1307 !strconcat(OpcodeStr,
1308 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1309 []>, EVEX_4V, EVEX_KZ;
1310 let mayLoad = 1 in {
1311 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1312 (ins _.RC:$src1, _.MemOp:$src2),
1313 !strconcat(OpcodeStr,
1314 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1315 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1316 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1317 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1318 !strconcat(OpcodeStr,
1319 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1320 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1321 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1322 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1323 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1324 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1325 !strconcat(OpcodeStr,
1326 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1327 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1331 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1333 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1334 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1335 !strconcat(OpcodeStr,
1336 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1337 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1338 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1339 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1340 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1342 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1343 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1344 !strconcat(OpcodeStr,
1345 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1346 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1347 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1351 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1352 AVX512VLVectorVTInfo VTInfo> {
1353 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1354 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1356 let Predicates = [HasVLX] in {
1357 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1358 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1359 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1360 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1364 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1365 AVX512VLVectorVTInfo VTInfo> {
1366 let Predicates = [HasBWI] in
1367 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1369 let Predicates = [HasBWI, HasVLX] in {
1370 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1371 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1376 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1377 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1378 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1379 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1380 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1381 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1384 let Predicates = [HasAVX512] in {
1385 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1386 (v8f32 VR256X:$src2))),
1388 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1389 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1390 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1392 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1393 (v8i32 VR256X:$src2))),
1395 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1396 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1397 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1399 //===----------------------------------------------------------------------===//
1400 // Compare Instructions
1401 //===----------------------------------------------------------------------===//
1403 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1405 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1407 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1409 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1410 "vcmp${cc}"#_.Suffix,
1411 "$src2, $src1", "$src1, $src2",
1412 (OpNode (_.VT _.RC:$src1),
1416 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1418 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1419 "vcmp${cc}"#_.Suffix,
1420 "$src2, $src1", "$src1, $src2",
1421 (OpNode (_.VT _.RC:$src1),
1422 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1423 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1425 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1427 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1428 "vcmp${cc}"#_.Suffix,
1429 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1430 (OpNodeRnd (_.VT _.RC:$src1),
1433 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1434 // Accept explicit immediate argument form instead of comparison code.
1435 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1436 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1438 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1440 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1441 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1443 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1445 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1446 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1448 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1450 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1452 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1454 }// let isAsmParserOnly = 1, hasSideEffects = 0
1456 let isCodeGenOnly = 1 in {
1457 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1458 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1459 !strconcat("vcmp${cc}", _.Suffix,
1460 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1461 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1464 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1466 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1468 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1469 !strconcat("vcmp${cc}", _.Suffix,
1470 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1471 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1472 (_.ScalarLdFrag addr:$src2),
1474 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1478 let Predicates = [HasAVX512] in {
1479 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1481 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1482 AVX512XDIi8Base, VEX_W;
1485 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1486 X86VectorVTInfo _> {
1487 def rr : AVX512BI<opc, MRMSrcReg,
1488 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1489 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1490 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1491 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1493 def rm : AVX512BI<opc, MRMSrcMem,
1494 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1495 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1496 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1497 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1498 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1499 def rrk : AVX512BI<opc, MRMSrcReg,
1500 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1501 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1502 "$dst {${mask}}, $src1, $src2}"),
1503 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1504 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1505 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1507 def rmk : AVX512BI<opc, MRMSrcMem,
1508 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1509 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1510 "$dst {${mask}}, $src1, $src2}"),
1511 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1512 (OpNode (_.VT _.RC:$src1),
1514 (_.LdFrag addr:$src2))))))],
1515 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1518 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1519 X86VectorVTInfo _> :
1520 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1521 let mayLoad = 1 in {
1522 def rmb : AVX512BI<opc, MRMSrcMem,
1523 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1524 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1525 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1526 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1527 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1528 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1529 def rmbk : AVX512BI<opc, MRMSrcMem,
1530 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1531 _.ScalarMemOp:$src2),
1532 !strconcat(OpcodeStr,
1533 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1534 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1535 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1536 (OpNode (_.VT _.RC:$src1),
1538 (_.ScalarLdFrag addr:$src2)))))],
1539 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1543 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1544 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1545 let Predicates = [prd] in
1546 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1549 let Predicates = [prd, HasVLX] in {
1550 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1552 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1557 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1558 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1560 let Predicates = [prd] in
1561 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1564 let Predicates = [prd, HasVLX] in {
1565 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1567 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1572 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1573 avx512vl_i8_info, HasBWI>,
1576 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1577 avx512vl_i16_info, HasBWI>,
1578 EVEX_CD8<16, CD8VF>;
1580 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1581 avx512vl_i32_info, HasAVX512>,
1582 EVEX_CD8<32, CD8VF>;
1584 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1585 avx512vl_i64_info, HasAVX512>,
1586 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1588 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1589 avx512vl_i8_info, HasBWI>,
1592 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1593 avx512vl_i16_info, HasBWI>,
1594 EVEX_CD8<16, CD8VF>;
1596 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1597 avx512vl_i32_info, HasAVX512>,
1598 EVEX_CD8<32, CD8VF>;
1600 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1601 avx512vl_i64_info, HasAVX512>,
1602 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1604 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1605 (COPY_TO_REGCLASS (VPCMPGTDZrr
1606 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1607 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1609 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1610 (COPY_TO_REGCLASS (VPCMPEQDZrr
1611 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1612 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1614 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1615 X86VectorVTInfo _> {
1616 def rri : AVX512AIi8<opc, MRMSrcReg,
1617 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1618 !strconcat("vpcmp${cc}", Suffix,
1619 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1620 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1622 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1624 def rmi : AVX512AIi8<opc, MRMSrcMem,
1625 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1626 !strconcat("vpcmp${cc}", Suffix,
1627 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1628 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1629 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1631 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1632 def rrik : AVX512AIi8<opc, MRMSrcReg,
1633 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1635 !strconcat("vpcmp${cc}", Suffix,
1636 "\t{$src2, $src1, $dst {${mask}}|",
1637 "$dst {${mask}}, $src1, $src2}"),
1638 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1639 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1641 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1643 def rmik : AVX512AIi8<opc, MRMSrcMem,
1644 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1646 !strconcat("vpcmp${cc}", Suffix,
1647 "\t{$src2, $src1, $dst {${mask}}|",
1648 "$dst {${mask}}, $src1, $src2}"),
1649 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1650 (OpNode (_.VT _.RC:$src1),
1651 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1653 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1655 // Accept explicit immediate argument form instead of comparison code.
1656 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1657 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1658 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1659 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1660 "$dst, $src1, $src2, $cc}"),
1661 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1663 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1664 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1665 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1666 "$dst, $src1, $src2, $cc}"),
1667 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1668 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1669 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1671 !strconcat("vpcmp", Suffix,
1672 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1673 "$dst {${mask}}, $src1, $src2, $cc}"),
1674 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1676 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1677 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1679 !strconcat("vpcmp", Suffix,
1680 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1681 "$dst {${mask}}, $src1, $src2, $cc}"),
1682 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1686 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1687 X86VectorVTInfo _> :
1688 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1689 def rmib : AVX512AIi8<opc, MRMSrcMem,
1690 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1692 !strconcat("vpcmp${cc}", Suffix,
1693 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1694 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1695 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1696 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1698 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1699 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1700 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1701 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1702 !strconcat("vpcmp${cc}", Suffix,
1703 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1704 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1705 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1706 (OpNode (_.VT _.RC:$src1),
1707 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1709 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1711 // Accept explicit immediate argument form instead of comparison code.
1712 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1713 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1714 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1716 !strconcat("vpcmp", Suffix,
1717 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1718 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1719 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1720 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1721 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1722 _.ScalarMemOp:$src2, u8imm:$cc),
1723 !strconcat("vpcmp", Suffix,
1724 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1725 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1726 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1730 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1731 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1732 let Predicates = [prd] in
1733 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1735 let Predicates = [prd, HasVLX] in {
1736 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1737 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1741 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1742 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1743 let Predicates = [prd] in
1744 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1747 let Predicates = [prd, HasVLX] in {
1748 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1750 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1755 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1756 HasBWI>, EVEX_CD8<8, CD8VF>;
1757 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1758 HasBWI>, EVEX_CD8<8, CD8VF>;
1760 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1761 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1762 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1763 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1765 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1766 HasAVX512>, EVEX_CD8<32, CD8VF>;
1767 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1768 HasAVX512>, EVEX_CD8<32, CD8VF>;
1770 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1771 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1772 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1773 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1775 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1777 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1778 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1779 "vcmp${cc}"#_.Suffix,
1780 "$src2, $src1", "$src1, $src2",
1781 (X86cmpm (_.VT _.RC:$src1),
1785 let mayLoad = 1 in {
1786 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1787 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1788 "vcmp${cc}"#_.Suffix,
1789 "$src2, $src1", "$src1, $src2",
1790 (X86cmpm (_.VT _.RC:$src1),
1791 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1794 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1796 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1797 "vcmp${cc}"#_.Suffix,
1798 "${src2}"##_.BroadcastStr##", $src1",
1799 "$src1, ${src2}"##_.BroadcastStr,
1800 (X86cmpm (_.VT _.RC:$src1),
1801 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1804 // Accept explicit immediate argument form instead of comparison code.
1805 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1806 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1808 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1810 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1812 let mayLoad = 1 in {
1813 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1815 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1817 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1819 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1821 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1823 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1824 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1829 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1830 // comparison code form (VCMP[EQ/LT/LE/...]
1831 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1832 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1833 "vcmp${cc}"#_.Suffix,
1834 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1835 (X86cmpmRnd (_.VT _.RC:$src1),
1838 (i32 FROUND_NO_EXC))>, EVEX_B;
1840 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1841 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1843 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1845 "$cc,{sae}, $src2, $src1",
1846 "$src1, $src2,{sae}, $cc">, EVEX_B;
1850 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1851 let Predicates = [HasAVX512] in {
1852 defm Z : avx512_vcmp_common<_.info512>,
1853 avx512_vcmp_sae<_.info512>, EVEX_V512;
1856 let Predicates = [HasAVX512,HasVLX] in {
1857 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1858 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1862 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1863 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1864 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1865 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1867 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1868 (COPY_TO_REGCLASS (VCMPPSZrri
1869 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1870 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1872 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1873 (COPY_TO_REGCLASS (VPCMPDZrri
1874 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1875 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1877 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1878 (COPY_TO_REGCLASS (VPCMPUDZrri
1879 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1880 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1883 // ----------------------------------------------------------------
1885 //handle fpclass instruction mask = op(reg_scalar,imm)
1886 // op(mem_scalar,imm)
1887 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1888 X86VectorVTInfo _, Predicate prd> {
1889 let Predicates = [prd] in {
1890 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1891 (ins _.RC:$src1, i32u8imm:$src2),
1892 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1893 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1894 (i32 imm:$src2)))], NoItinerary>;
1895 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1896 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1897 OpcodeStr##_.Suffix#
1898 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1899 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1900 (OpNode (_.VT _.RC:$src1),
1901 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1902 let mayLoad = 1, AddedComplexity = 20 in {
1903 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1904 (ins _.MemOp:$src1, i32u8imm:$src2),
1905 OpcodeStr##_.Suffix##
1906 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1908 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1909 (i32 imm:$src2)))], NoItinerary>;
1910 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1911 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1912 OpcodeStr##_.Suffix##
1913 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1914 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1915 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1916 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1921 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1922 // fpclass(reg_vec, mem_vec, imm)
1923 // fpclass(reg_vec, broadcast(eltVt), imm)
1924 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1925 X86VectorVTInfo _, string mem, string broadcast>{
1926 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1927 (ins _.RC:$src1, i32u8imm:$src2),
1928 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1929 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1930 (i32 imm:$src2)))], NoItinerary>;
1931 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1932 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1933 OpcodeStr##_.Suffix#
1934 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1935 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1936 (OpNode (_.VT _.RC:$src1),
1937 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1938 let mayLoad = 1 in {
1939 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1940 (ins _.MemOp:$src1, i32u8imm:$src2),
1941 OpcodeStr##_.Suffix##mem#
1942 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1943 [(set _.KRC:$dst,(OpNode
1944 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1945 (i32 imm:$src2)))], NoItinerary>;
1946 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1947 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1948 OpcodeStr##_.Suffix##mem#
1949 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1950 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1951 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1952 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1953 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1954 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1955 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1956 _.BroadcastStr##", $dst | $dst, ${src1}"
1957 ##_.BroadcastStr##", $src2}",
1958 [(set _.KRC:$dst,(OpNode
1959 (_.VT (X86VBroadcast
1960 (_.ScalarLdFrag addr:$src1))),
1961 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1962 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1963 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1964 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1965 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1966 _.BroadcastStr##", $src2}",
1967 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1968 (_.VT (X86VBroadcast
1969 (_.ScalarLdFrag addr:$src1))),
1970 (i32 imm:$src2))))], NoItinerary>,
1975 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1976 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1978 let Predicates = [prd] in {
1979 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1980 broadcast>, EVEX_V512;
1982 let Predicates = [prd, HasVLX] in {
1983 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1984 broadcast>, EVEX_V128;
1985 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1986 broadcast>, EVEX_V256;
1990 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1991 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
1992 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1993 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1994 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1995 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1996 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1997 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
1998 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1999 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
2002 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
2003 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
2005 //-----------------------------------------------------------------
2006 // Mask register copy, including
2007 // - copy between mask registers
2008 // - load/store mask registers
2009 // - copy from GPR to mask register and vice versa
2011 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
2012 string OpcodeStr, RegisterClass KRC,
2013 ValueType vvt, X86MemOperand x86memop> {
2014 let hasSideEffects = 0 in {
2015 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2016 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2018 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
2019 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2020 [(set KRC:$dst, (vvt (load addr:$src)))]>;
2022 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
2023 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2024 [(store KRC:$src, addr:$dst)]>;
2028 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
2030 RegisterClass KRC, RegisterClass GRC> {
2031 let hasSideEffects = 0 in {
2032 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
2033 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2034 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
2035 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2039 let Predicates = [HasDQI] in
2040 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
2041 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
2044 let Predicates = [HasAVX512] in
2045 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
2046 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
2049 let Predicates = [HasBWI] in {
2050 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2052 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
2056 let Predicates = [HasBWI] in {
2057 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2059 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
2063 // GR from/to mask register
2064 let Predicates = [HasDQI] in {
2065 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2066 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2067 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2068 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2070 let Predicates = [HasAVX512] in {
2071 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2072 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2073 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2074 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2076 let Predicates = [HasBWI] in {
2077 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2078 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2080 let Predicates = [HasBWI] in {
2081 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2082 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2086 let Predicates = [HasDQI] in {
2087 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2088 (KMOVBmk addr:$dst, VK8:$src)>;
2089 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2090 (KMOVBkm addr:$src)>;
2092 def : Pat<(store VK4:$src, addr:$dst),
2093 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2094 def : Pat<(store VK2:$src, addr:$dst),
2095 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2097 let Predicates = [HasAVX512, NoDQI] in {
2098 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2099 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2100 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2101 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2103 let Predicates = [HasAVX512] in {
2104 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2105 (KMOVWmk addr:$dst, VK16:$src)>;
2106 def : Pat<(i1 (load addr:$src)),
2107 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2108 (MOV8rm addr:$src), sub_8bit)),
2110 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2111 (KMOVWkm addr:$src)>;
2113 let Predicates = [HasBWI] in {
2114 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2115 (KMOVDmk addr:$dst, VK32:$src)>;
2116 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2117 (KMOVDkm addr:$src)>;
2119 let Predicates = [HasBWI] in {
2120 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2121 (KMOVQmk addr:$dst, VK64:$src)>;
2122 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2123 (KMOVQkm addr:$src)>;
2126 let Predicates = [HasAVX512] in {
2127 def : Pat<(i1 (trunc (i64 GR64:$src))),
2128 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2131 def : Pat<(i1 (trunc (i32 GR32:$src))),
2132 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2134 def : Pat<(i1 (trunc (i8 GR8:$src))),
2136 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2138 def : Pat<(i1 (trunc (i16 GR16:$src))),
2140 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2143 def : Pat<(i32 (zext VK1:$src)),
2144 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2145 def : Pat<(i32 (anyext VK1:$src)),
2146 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2148 def : Pat<(i8 (zext VK1:$src)),
2151 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2152 def : Pat<(i8 (anyext VK1:$src)),
2154 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2156 def : Pat<(i64 (zext VK1:$src)),
2157 (AND64ri8 (SUBREG_TO_REG (i64 0),
2158 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2159 def : Pat<(i16 (zext VK1:$src)),
2161 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2164 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2165 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2166 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2167 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2168 def : Pat<(v4i1 (scalar_to_vector VK1:$src)),
2169 (COPY_TO_REGCLASS VK1:$src, VK4)>;
2170 def : Pat<(v2i1 (scalar_to_vector VK1:$src)),
2171 (COPY_TO_REGCLASS VK1:$src, VK2)>;
2172 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2173 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2174 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2175 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2178 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2179 let Predicates = [HasAVX512, NoDQI] in {
2180 // GR from/to 8-bit mask without native support
2181 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2183 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2184 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2186 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2190 let Predicates = [HasAVX512] in {
2191 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2192 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2193 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2194 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2196 let Predicates = [HasBWI] in {
2197 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2198 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2199 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2200 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2203 // Mask unary operation
2205 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2206 RegisterClass KRC, SDPatternOperator OpNode,
2208 let Predicates = [prd] in
2209 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2210 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2211 [(set KRC:$dst, (OpNode KRC:$src))]>;
2214 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2215 SDPatternOperator OpNode> {
2216 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2218 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2219 HasAVX512>, VEX, PS;
2220 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2221 HasBWI>, VEX, PD, VEX_W;
2222 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2223 HasBWI>, VEX, PS, VEX_W;
2226 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2228 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2229 let Predicates = [HasAVX512] in
2230 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2232 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2233 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2235 defm : avx512_mask_unop_int<"knot", "KNOT">;
2237 let Predicates = [HasDQI] in
2238 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2239 let Predicates = [HasAVX512] in
2240 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2241 let Predicates = [HasBWI] in
2242 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2243 let Predicates = [HasBWI] in
2244 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2246 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2247 let Predicates = [HasAVX512, NoDQI] in {
2248 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2249 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2250 def : Pat<(not VK8:$src),
2252 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2254 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2255 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2256 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2257 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2259 // Mask binary operation
2260 // - KAND, KANDN, KOR, KXNOR, KXOR
2261 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2262 RegisterClass KRC, SDPatternOperator OpNode,
2263 Predicate prd, bit IsCommutable> {
2264 let Predicates = [prd], isCommutable = IsCommutable in
2265 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2266 !strconcat(OpcodeStr,
2267 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2268 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2271 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2272 SDPatternOperator OpNode, bit IsCommutable,
2273 Predicate prdW = HasAVX512> {
2274 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2275 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2276 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2277 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2278 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2279 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2280 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2281 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2284 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2285 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2287 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2288 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2289 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2290 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2291 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2292 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2294 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2295 let Predicates = [HasAVX512] in
2296 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2297 (i16 GR16:$src1), (i16 GR16:$src2)),
2298 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2299 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2300 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2303 defm : avx512_mask_binop_int<"kand", "KAND">;
2304 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2305 defm : avx512_mask_binop_int<"kor", "KOR">;
2306 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2307 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2309 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2310 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2311 // for the DQI set, this type is legal and KxxxB instruction is used
2312 let Predicates = [NoDQI] in
2313 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2315 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2316 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2318 // All types smaller than 8 bits require conversion anyway
2319 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2320 (COPY_TO_REGCLASS (Inst
2321 (COPY_TO_REGCLASS VK1:$src1, VK16),
2322 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2323 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2324 (COPY_TO_REGCLASS (Inst
2325 (COPY_TO_REGCLASS VK2:$src1, VK16),
2326 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2327 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2328 (COPY_TO_REGCLASS (Inst
2329 (COPY_TO_REGCLASS VK4:$src1, VK16),
2330 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2333 defm : avx512_binop_pat<and, KANDWrr>;
2334 defm : avx512_binop_pat<andn, KANDNWrr>;
2335 defm : avx512_binop_pat<or, KORWrr>;
2336 defm : avx512_binop_pat<xnor, KXNORWrr>;
2337 defm : avx512_binop_pat<xor, KXORWrr>;
2339 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2340 (KXNORWrr VK16:$src1, VK16:$src2)>;
2341 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2342 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2343 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2344 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2345 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2346 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2348 let Predicates = [NoDQI] in
2349 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2350 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2351 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2353 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2354 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2355 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2357 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2358 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2359 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2361 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2362 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2363 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2366 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2367 RegisterClass KRCSrc, Predicate prd> {
2368 let Predicates = [prd] in {
2369 let hasSideEffects = 0 in
2370 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2371 (ins KRC:$src1, KRC:$src2),
2372 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2375 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2376 (!cast<Instruction>(NAME##rr)
2377 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2378 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2382 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2383 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2384 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2387 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2388 SDNode OpNode, Predicate prd> {
2389 let Predicates = [prd], Defs = [EFLAGS] in
2390 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2391 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2392 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2395 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2396 Predicate prdW = HasAVX512> {
2397 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2399 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2401 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2403 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2407 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2408 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2411 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2413 let Predicates = [HasAVX512] in
2414 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2415 !strconcat(OpcodeStr,
2416 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2417 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2420 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2422 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2424 let Predicates = [HasDQI] in
2425 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2427 let Predicates = [HasBWI] in {
2428 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2430 let Predicates = [HasDQI] in
2431 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2436 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2437 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2439 // Mask setting all 0s or 1s
2440 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2441 let Predicates = [HasAVX512] in
2442 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2443 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2444 [(set KRC:$dst, (VT Val))]>;
2447 multiclass avx512_mask_setop_w<PatFrag Val> {
2448 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2449 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2450 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2451 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2454 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2455 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2457 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2458 let Predicates = [HasAVX512] in {
2459 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2460 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2461 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2462 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2463 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2464 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2465 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2467 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2468 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2470 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2471 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2473 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2474 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2476 def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 0))),
2477 (v16i1 (COPY_TO_REGCLASS VK32:$src, VK16))>;
2479 def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 16))),
2480 (v16i1 (COPY_TO_REGCLASS (KSHIFTRDri VK32:$src, (i8 16)), VK16))>;
2482 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2483 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2485 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2486 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2488 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2489 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2491 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2492 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2494 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2495 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2497 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2498 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2499 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2500 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2502 def : Pat<(v32i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2503 (v32i1 (COPY_TO_REGCLASS VK2:$src, VK32))>;
2504 def : Pat<(v32i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2505 (v32i1 (COPY_TO_REGCLASS VK4:$src, VK32))>;
2506 def : Pat<(v32i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2507 (v32i1 (COPY_TO_REGCLASS VK8:$src, VK32))>;
2508 def : Pat<(v32i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2509 (v32i1 (COPY_TO_REGCLASS VK16:$src, VK32))>;
2511 def : Pat<(v64i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2512 (v64i1 (COPY_TO_REGCLASS VK2:$src, VK64))>;
2513 def : Pat<(v64i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2514 (v64i1 (COPY_TO_REGCLASS VK4:$src, VK64))>;
2515 def : Pat<(v64i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2516 (v64i1 (COPY_TO_REGCLASS VK8:$src, VK64))>;
2517 def : Pat<(v64i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2518 (v64i1 (COPY_TO_REGCLASS VK16:$src, VK64))>;
2519 def : Pat<(v64i1 (insert_subvector undef, VK32:$src, (iPTR 0))),
2520 (v64i1 (COPY_TO_REGCLASS VK32:$src, VK64))>;
2523 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2524 (v8i1 (COPY_TO_REGCLASS
2525 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2526 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2528 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2529 (v8i1 (COPY_TO_REGCLASS
2530 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2531 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2533 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2534 (v4i1 (COPY_TO_REGCLASS
2535 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2536 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2538 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2539 (v4i1 (COPY_TO_REGCLASS
2540 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2541 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2543 //===----------------------------------------------------------------------===//
2544 // AVX-512 - Aligned and unaligned load and store
2548 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2549 PatFrag ld_frag, PatFrag mload,
2550 bit IsReMaterializable = 1> {
2551 let hasSideEffects = 0 in {
2552 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2553 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2555 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2556 (ins _.KRCWM:$mask, _.RC:$src),
2557 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2558 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2561 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2562 SchedRW = [WriteLoad] in
2563 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2564 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2565 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2568 let Constraints = "$src0 = $dst" in {
2569 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2570 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2571 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2572 "${dst} {${mask}}, $src1}"),
2573 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2575 (_.VT _.RC:$src0))))], _.ExeDomain>,
2577 let mayLoad = 1, SchedRW = [WriteLoad] in
2578 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2579 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2580 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2581 "${dst} {${mask}}, $src1}"),
2582 [(set _.RC:$dst, (_.VT
2583 (vselect _.KRCWM:$mask,
2584 (_.VT (bitconvert (ld_frag addr:$src1))),
2585 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2587 let mayLoad = 1, SchedRW = [WriteLoad] in
2588 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2589 (ins _.KRCWM:$mask, _.MemOp:$src),
2590 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2591 "${dst} {${mask}} {z}, $src}",
2592 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2593 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2594 _.ExeDomain>, EVEX, EVEX_KZ;
2596 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2597 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2599 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2600 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2602 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2603 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2604 _.KRCWM:$mask, addr:$ptr)>;
2607 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2608 AVX512VLVectorVTInfo _,
2610 bit IsReMaterializable = 1> {
2611 let Predicates = [prd] in
2612 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2613 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2615 let Predicates = [prd, HasVLX] in {
2616 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2617 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2618 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2619 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2623 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2624 AVX512VLVectorVTInfo _,
2626 bit IsReMaterializable = 1> {
2627 let Predicates = [prd] in
2628 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2629 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2631 let Predicates = [prd, HasVLX] in {
2632 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2633 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2634 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2635 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2639 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2640 PatFrag st_frag, PatFrag mstore> {
2642 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2643 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
2644 [], _.ExeDomain>, EVEX;
2645 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2646 (ins _.KRCWM:$mask, _.RC:$src),
2647 OpcodeStr # ".s\t{$src, ${dst} {${mask}}|"#
2648 "${dst} {${mask}}, $src}",
2649 [], _.ExeDomain>, EVEX, EVEX_K;
2650 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2651 (ins _.KRCWM:$mask, _.RC:$src),
2652 OpcodeStr # ".s\t{$src, ${dst} {${mask}} {z}|" #
2653 "${dst} {${mask}} {z}, $src}",
2654 [], _.ExeDomain>, EVEX, EVEX_KZ;
2656 let mayStore = 1 in {
2657 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2658 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2659 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2660 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2661 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2662 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2663 [], _.ExeDomain>, EVEX, EVEX_K;
2666 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2667 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2668 _.KRCWM:$mask, _.RC:$src)>;
2672 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2673 AVX512VLVectorVTInfo _, Predicate prd> {
2674 let Predicates = [prd] in
2675 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2676 masked_store_unaligned>, EVEX_V512;
2678 let Predicates = [prd, HasVLX] in {
2679 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2680 masked_store_unaligned>, EVEX_V256;
2681 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2682 masked_store_unaligned>, EVEX_V128;
2686 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2687 AVX512VLVectorVTInfo _, Predicate prd> {
2688 let Predicates = [prd] in
2689 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2690 masked_store_aligned512>, EVEX_V512;
2692 let Predicates = [prd, HasVLX] in {
2693 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2694 masked_store_aligned256>, EVEX_V256;
2695 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2696 masked_store_aligned128>, EVEX_V128;
2700 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2702 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2703 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2705 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2707 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2708 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2710 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2711 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2712 PS, EVEX_CD8<32, CD8VF>;
2714 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2715 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2716 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2718 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2719 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2720 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2722 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2723 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2724 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2726 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2727 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2728 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2730 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2731 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2732 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2734 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2735 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2736 (VMOVAPDZrm addr:$ptr)>;
2738 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2739 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2740 (VMOVAPSZrm addr:$ptr)>;
2742 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2744 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2746 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2748 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2751 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2753 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2755 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2757 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2760 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2762 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2763 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2765 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2767 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2768 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2770 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2771 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2772 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2774 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2775 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2776 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2778 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2779 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2780 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2782 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2783 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2784 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2786 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2787 (v16i32 immAllZerosV), GR16:$mask)),
2788 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2790 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2791 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2792 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2794 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2796 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2798 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2800 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2803 let AddedComplexity = 20 in {
2804 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2805 (bc_v8i64 (v16i32 immAllZerosV)))),
2806 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2808 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2809 (v8i64 VR512:$src))),
2810 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2813 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2814 (v16i32 immAllZerosV))),
2815 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2817 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2818 (v16i32 VR512:$src))),
2819 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2822 // Move Int Doubleword to Packed Double Int
2824 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2825 "vmovd\t{$src, $dst|$dst, $src}",
2827 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2829 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2830 "vmovd\t{$src, $dst|$dst, $src}",
2832 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2833 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
2834 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2835 "vmovq\t{$src, $dst|$dst, $src}",
2837 (v2i64 (scalar_to_vector GR64:$src)))],
2838 IIC_SSE_MOVDQ>, EVEX, VEX_W;
2839 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
2840 def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2842 "vmovq\t{$src, $dst|$dst, $src}", []>,
2843 EVEX, VEX_W, EVEX_CD8<64, CD8VT1>;
2844 let isCodeGenOnly = 1 in {
2845 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src),
2846 "vmovq\t{$src, $dst|$dst, $src}",
2847 [(set FR64X:$dst, (bitconvert GR64:$src))],
2848 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2849 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src),
2850 "vmovq\t{$src, $dst|$dst, $src}",
2851 [(set GR64:$dst, (bitconvert FR64X:$src))],
2852 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2853 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64X:$src),
2854 "vmovq\t{$src, $dst|$dst, $src}",
2855 [(store (i64 (bitconvert FR64X:$src)), addr:$dst)],
2856 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2857 EVEX_CD8<64, CD8VT1>;
2860 // Move Int Doubleword to Single Scalar
2862 let isCodeGenOnly = 1 in {
2863 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2864 "vmovd\t{$src, $dst|$dst, $src}",
2865 [(set FR32X:$dst, (bitconvert GR32:$src))],
2866 IIC_SSE_MOVDQ>, EVEX;
2868 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2869 "vmovd\t{$src, $dst|$dst, $src}",
2870 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2871 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
2874 // Move doubleword from xmm register to r/m32
2876 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2877 "vmovd\t{$src, $dst|$dst, $src}",
2878 [(set GR32:$dst, (extractelt (v4i32 VR128X:$src),
2879 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2881 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2882 (ins i32mem:$dst, VR128X:$src),
2883 "vmovd\t{$src, $dst|$dst, $src}",
2884 [(store (i32 (extractelt (v4i32 VR128X:$src),
2885 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2886 EVEX, EVEX_CD8<32, CD8VT1>;
2888 // Move quadword from xmm1 register to r/m64
2890 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2891 "vmovq\t{$src, $dst|$dst, $src}",
2892 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2894 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_W,
2895 Requires<[HasAVX512, In64BitMode]>;
2897 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
2898 def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src),
2899 "vmovq\t{$src, $dst|$dst, $src}",
2900 [], IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_W,
2901 Requires<[HasAVX512, In64BitMode]>;
2903 def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs),
2904 (ins i64mem:$dst, VR128X:$src),
2905 "vmovq\t{$src, $dst|$dst, $src}",
2906 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2907 addr:$dst)], IIC_SSE_MOVDQ>,
2908 EVEX, PD, VEX_W, EVEX_CD8<64, CD8VT1>,
2909 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2911 let hasSideEffects = 0 in
2912 def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
2914 "vmovq.s\t{$src, $dst|$dst, $src}",[]>,
2917 // Move Scalar Single to Double Int
2919 let isCodeGenOnly = 1 in {
2920 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2922 "vmovd\t{$src, $dst|$dst, $src}",
2923 [(set GR32:$dst, (bitconvert FR32X:$src))],
2924 IIC_SSE_MOVD_ToGP>, EVEX;
2925 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2926 (ins i32mem:$dst, FR32X:$src),
2927 "vmovd\t{$src, $dst|$dst, $src}",
2928 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2929 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
2932 // Move Quadword Int to Packed Quadword Int
2934 def VMOVQI2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2936 "vmovq\t{$src, $dst|$dst, $src}",
2938 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2939 EVEX, VEX_W, EVEX_CD8<8, CD8VT8>;
2941 //===----------------------------------------------------------------------===//
2942 // AVX-512 MOVSS, MOVSD
2943 //===----------------------------------------------------------------------===//
2945 multiclass avx512_move_scalar <string asm, SDNode OpNode,
2946 X86VectorVTInfo _> {
2947 defm rr_Int : AVX512_maskable_scalar<0x10, MRMSrcReg, _, (outs _.RC:$dst),
2948 (ins _.RC:$src1, _.RC:$src2),
2949 asm, "$src2, $src1","$src1, $src2",
2950 (_.VT (OpNode (_.VT _.RC:$src1),
2951 (_.VT _.RC:$src2))),
2952 IIC_SSE_MOV_S_RR>, EVEX_4V;
2953 let Constraints = "$src1 = $dst" , mayLoad = 1 in
2954 defm rm_Int : AVX512_maskable_3src_scalar<0x10, MRMSrcMem, _,
2956 (ins _.ScalarMemOp:$src),
2958 (_.VT (OpNode (_.VT _.RC:$src1),
2959 (_.VT (scalar_to_vector
2960 (_.ScalarLdFrag addr:$src)))))>, EVEX;
2961 let isCodeGenOnly = 1 in {
2962 def rr : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
2963 (ins _.RC:$src1, _.FRC:$src2),
2964 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2965 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1,
2966 (scalar_to_vector _.FRC:$src2))))],
2967 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V;
2969 def rm : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src),
2970 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2971 [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))],
2972 _.ExeDomain, IIC_SSE_MOV_S_RM>, EVEX;
2974 let mayStore = 1 in {
2975 def mr: AVX512PI<0x11, MRMDestMem, (outs), (ins _.ScalarMemOp:$dst, _.FRC:$src),
2976 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2977 [(store _.FRC:$src, addr:$dst)], _.ExeDomain, IIC_SSE_MOV_S_MR>,
2979 def mrk: AVX512PI<0x11, MRMDestMem, (outs),
2980 (ins _.ScalarMemOp:$dst, VK1WM:$mask, _.FRC:$src),
2981 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2982 [], _.ExeDomain, IIC_SSE_MOV_S_MR>, EVEX, EVEX_K;
2986 defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>,
2987 VEX_LIG, XS, EVEX_CD8<32, CD8VT1>;
2989 defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>,
2990 VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2992 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2993 (COPY_TO_REGCLASS (VMOVSSZrr_Intk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2994 VK1WM:$mask, (v4f32 (IMPLICIT_DEF)),(COPY_TO_REGCLASS FR32X:$src1, VR128X)), FR32X)>;
2996 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2997 (COPY_TO_REGCLASS (VMOVSDZrr_Intk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2998 VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR64X:$src1, VR128X)), FR64X)>;
3000 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
3001 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
3002 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3004 defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,
3005 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3006 "vmovss.s", "$src2, $src1", "$src1, $src2", []>,
3007 XS, EVEX_4V, VEX_LIG;
3009 defm VMOVSSDrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f64x_info,
3010 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3011 "vmovsd.s", "$src2, $src1", "$src1, $src2", []>,
3012 XD, EVEX_4V, VEX_LIG, VEX_W;
3014 let Predicates = [HasAVX512] in {
3015 let AddedComplexity = 15 in {
3016 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
3017 // MOVS{S,D} to the lower bits.
3018 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
3019 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
3020 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
3021 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3022 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
3023 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3024 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
3025 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
3027 // Move low f32 and clear high bits.
3028 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
3029 (SUBREG_TO_REG (i32 0),
3030 (VMOVSSZrr (v4f32 (V_SET0)),
3031 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
3032 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
3033 (SUBREG_TO_REG (i32 0),
3034 (VMOVSSZrr (v4i32 (V_SET0)),
3035 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
3038 let AddedComplexity = 20 in {
3039 // MOVSSrm zeros the high parts of the register; represent this
3040 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3041 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
3042 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3043 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
3044 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3045 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
3046 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3048 // MOVSDrm zeros the high parts of the register; represent this
3049 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3050 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
3051 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3052 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
3053 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3054 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
3055 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3056 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
3057 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3058 def : Pat<(v2f64 (X86vzload addr:$src)),
3059 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3061 // Represent the same patterns above but in the form they appear for
3063 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3064 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3065 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3066 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3067 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3068 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3069 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3070 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3071 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3073 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3074 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
3075 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
3076 FR32X:$src)), sub_xmm)>;
3077 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3078 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3079 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
3080 FR64X:$src)), sub_xmm)>;
3081 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3082 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3083 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3085 // Move low f64 and clear high bits.
3086 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3087 (SUBREG_TO_REG (i32 0),
3088 (VMOVSDZrr (v2f64 (V_SET0)),
3089 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3091 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3092 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3093 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3095 // Extract and store.
3096 def : Pat<(store (f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
3098 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3099 def : Pat<(store (f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
3101 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3103 // Shuffle with VMOVSS
3104 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3105 (VMOVSSZrr (v4i32 VR128X:$src1),
3106 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3107 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3108 (VMOVSSZrr (v4f32 VR128X:$src1),
3109 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3112 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3113 (SUBREG_TO_REG (i32 0),
3114 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3115 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3117 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3118 (SUBREG_TO_REG (i32 0),
3119 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3120 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3123 // Shuffle with VMOVSD
3124 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3125 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3126 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3127 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3128 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3129 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3130 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3131 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3134 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3135 (SUBREG_TO_REG (i32 0),
3136 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3137 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3139 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3140 (SUBREG_TO_REG (i32 0),
3141 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3142 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3145 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3146 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3147 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3148 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3149 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3150 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3151 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3152 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3155 let AddedComplexity = 15 in
3156 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3158 "vmovq\t{$src, $dst|$dst, $src}",
3159 [(set VR128X:$dst, (v2i64 (X86vzmovl
3160 (v2i64 VR128X:$src))))],
3161 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3163 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3164 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3166 "vmovq\t{$src, $dst|$dst, $src}",
3167 [(set VR128X:$dst, (v2i64 (X86vzmovl
3168 (loadv2i64 addr:$src))))],
3169 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3170 EVEX_CD8<8, CD8VT8>;
3172 let Predicates = [HasAVX512] in {
3173 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3174 let AddedComplexity = 20 in {
3175 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3176 (VMOVDI2PDIZrm addr:$src)>;
3177 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3178 (VMOV64toPQIZrr GR64:$src)>;
3179 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3180 (VMOVDI2PDIZrr GR32:$src)>;
3182 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3183 (VMOVDI2PDIZrm addr:$src)>;
3184 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3185 (VMOVDI2PDIZrm addr:$src)>;
3186 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3187 (VMOVZPQILo2PQIZrm addr:$src)>;
3188 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3189 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3190 def : Pat<(v2i64 (X86vzload addr:$src)),
3191 (VMOVZPQILo2PQIZrm addr:$src)>;
3194 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3195 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3196 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3197 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3198 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3199 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3200 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3203 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3204 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3206 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3207 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3209 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3210 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3212 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3213 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3215 //===----------------------------------------------------------------------===//
3216 // AVX-512 - Non-temporals
3217 //===----------------------------------------------------------------------===//
3218 let SchedRW = [WriteLoad] in {
3219 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3220 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3221 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3222 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3223 EVEX_CD8<64, CD8VF>;
3225 let Predicates = [HasAVX512, HasVLX] in {
3226 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3228 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3229 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3230 EVEX_CD8<64, CD8VF>;
3232 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3234 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3235 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3236 EVEX_CD8<64, CD8VF>;
3240 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3241 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3242 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3243 let SchedRW = [WriteStore], mayStore = 1,
3244 AddedComplexity = 400 in
3245 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3246 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3247 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3250 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3251 string elty, string elsz, string vsz512,
3252 string vsz256, string vsz128, Domain d,
3253 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3254 let Predicates = [prd] in
3255 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3256 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3257 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3260 let Predicates = [prd, HasVLX] in {
3261 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3262 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3263 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3266 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3267 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3268 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3273 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3274 "i", "64", "8", "4", "2", SSEPackedInt,
3275 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3277 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3278 "f", "64", "8", "4", "2", SSEPackedDouble,
3279 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3281 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3282 "f", "32", "16", "8", "4", SSEPackedSingle,
3283 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3285 //===----------------------------------------------------------------------===//
3286 // AVX-512 - Integer arithmetic
3288 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3289 X86VectorVTInfo _, OpndItins itins,
3290 bit IsCommutable = 0> {
3291 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3292 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3293 "$src2, $src1", "$src1, $src2",
3294 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3295 itins.rr, IsCommutable>,
3296 AVX512BIBase, EVEX_4V;
3299 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3300 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3301 "$src2, $src1", "$src1, $src2",
3302 (_.VT (OpNode _.RC:$src1,
3303 (bitconvert (_.LdFrag addr:$src2)))),
3305 AVX512BIBase, EVEX_4V;
3308 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3309 X86VectorVTInfo _, OpndItins itins,
3310 bit IsCommutable = 0> :
3311 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3313 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3314 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3315 "${src2}"##_.BroadcastStr##", $src1",
3316 "$src1, ${src2}"##_.BroadcastStr,
3317 (_.VT (OpNode _.RC:$src1,
3319 (_.ScalarLdFrag addr:$src2)))),
3321 AVX512BIBase, EVEX_4V, EVEX_B;
3324 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3325 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3326 Predicate prd, bit IsCommutable = 0> {
3327 let Predicates = [prd] in
3328 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3329 IsCommutable>, EVEX_V512;
3331 let Predicates = [prd, HasVLX] in {
3332 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3333 IsCommutable>, EVEX_V256;
3334 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3335 IsCommutable>, EVEX_V128;
3339 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3340 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3341 Predicate prd, bit IsCommutable = 0> {
3342 let Predicates = [prd] in
3343 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3344 IsCommutable>, EVEX_V512;
3346 let Predicates = [prd, HasVLX] in {
3347 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3348 IsCommutable>, EVEX_V256;
3349 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3350 IsCommutable>, EVEX_V128;
3354 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3355 OpndItins itins, Predicate prd,
3356 bit IsCommutable = 0> {
3357 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3358 itins, prd, IsCommutable>,
3359 VEX_W, EVEX_CD8<64, CD8VF>;
3362 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3363 OpndItins itins, Predicate prd,
3364 bit IsCommutable = 0> {
3365 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3366 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3369 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3370 OpndItins itins, Predicate prd,
3371 bit IsCommutable = 0> {
3372 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3373 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3376 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3377 OpndItins itins, Predicate prd,
3378 bit IsCommutable = 0> {
3379 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3380 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3383 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3384 SDNode OpNode, OpndItins itins, Predicate prd,
3385 bit IsCommutable = 0> {
3386 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3389 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3393 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3394 SDNode OpNode, OpndItins itins, Predicate prd,
3395 bit IsCommutable = 0> {
3396 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3399 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3403 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3404 bits<8> opc_d, bits<8> opc_q,
3405 string OpcodeStr, SDNode OpNode,
3406 OpndItins itins, bit IsCommutable = 0> {
3407 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3408 itins, HasAVX512, IsCommutable>,
3409 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3410 itins, HasBWI, IsCommutable>;
3413 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3414 SDNode OpNode,X86VectorVTInfo _Src,
3415 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3416 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3417 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3418 "$src2, $src1","$src1, $src2",
3420 (_Src.VT _Src.RC:$src1),
3421 (_Src.VT _Src.RC:$src2))),
3422 itins.rr, IsCommutable>,
3423 AVX512BIBase, EVEX_4V;
3424 let mayLoad = 1 in {
3425 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3426 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3427 "$src2, $src1", "$src1, $src2",
3428 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3429 (bitconvert (_Src.LdFrag addr:$src2)))),
3431 AVX512BIBase, EVEX_4V;
3433 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3434 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3436 "${src2}"##_Dst.BroadcastStr##", $src1",
3437 "$src1, ${src2}"##_Dst.BroadcastStr,
3438 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3439 (_Dst.VT (X86VBroadcast
3440 (_Dst.ScalarLdFrag addr:$src2)))))),
3442 AVX512BIBase, EVEX_4V, EVEX_B;
3446 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3447 SSE_INTALU_ITINS_P, 1>;
3448 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3449 SSE_INTALU_ITINS_P, 0>;
3450 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3451 SSE_INTALU_ITINS_P, HasBWI, 1>;
3452 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3453 SSE_INTALU_ITINS_P, HasBWI, 0>;
3454 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3455 SSE_INTALU_ITINS_P, HasBWI, 1>;
3456 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3457 SSE_INTALU_ITINS_P, HasBWI, 0>;
3458 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3459 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3460 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3461 SSE_INTALU_ITINS_P, HasBWI, 1>;
3462 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3463 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3464 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3466 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3468 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3470 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3471 SSE_INTALU_ITINS_P, HasBWI, 1>;
3473 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3474 SDNode OpNode, bit IsCommutable = 0> {
3476 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3477 v16i32_info, v8i64_info, IsCommutable>,
3478 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3479 let Predicates = [HasVLX] in {
3480 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3481 v8i32x_info, v4i64x_info, IsCommutable>,
3482 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3483 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3484 v4i32x_info, v2i64x_info, IsCommutable>,
3485 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3489 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3491 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3494 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3495 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3496 let mayLoad = 1 in {
3497 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3498 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3500 "${src2}"##_Src.BroadcastStr##", $src1",
3501 "$src1, ${src2}"##_Src.BroadcastStr,
3502 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3503 (_Src.VT (X86VBroadcast
3504 (_Src.ScalarLdFrag addr:$src2))))))>,
3505 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3509 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3510 SDNode OpNode,X86VectorVTInfo _Src,
3511 X86VectorVTInfo _Dst> {
3512 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3513 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3514 "$src2, $src1","$src1, $src2",
3516 (_Src.VT _Src.RC:$src1),
3517 (_Src.VT _Src.RC:$src2)))>,
3518 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3519 let mayLoad = 1 in {
3520 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3521 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3522 "$src2, $src1", "$src1, $src2",
3523 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3524 (bitconvert (_Src.LdFrag addr:$src2))))>,
3525 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3529 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3531 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3533 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3534 v32i16_info>, EVEX_V512;
3535 let Predicates = [HasVLX] in {
3536 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3538 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3539 v16i16x_info>, EVEX_V256;
3540 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3542 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3543 v8i16x_info>, EVEX_V128;
3546 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3548 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3549 v64i8_info>, EVEX_V512;
3550 let Predicates = [HasVLX] in {
3551 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3552 v32i8x_info>, EVEX_V256;
3553 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3554 v16i8x_info>, EVEX_V128;
3558 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3559 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3560 AVX512VLVectorVTInfo _Dst> {
3561 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3562 _Dst.info512>, EVEX_V512;
3563 let Predicates = [HasVLX] in {
3564 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3565 _Dst.info256>, EVEX_V256;
3566 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3567 _Dst.info128>, EVEX_V128;
3571 let Predicates = [HasBWI] in {
3572 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3573 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3574 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3575 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3577 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3578 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3579 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3580 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3583 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3584 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3585 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3586 SSE_INTALU_ITINS_P, HasBWI, 1>;
3587 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3588 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3590 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3591 SSE_INTALU_ITINS_P, HasBWI, 1>;
3592 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3593 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3594 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3595 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3597 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3598 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3599 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3600 SSE_INTALU_ITINS_P, HasBWI, 1>;
3601 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3602 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3604 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3605 SSE_INTALU_ITINS_P, HasBWI, 1>;
3606 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3607 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3608 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3609 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3610 //===----------------------------------------------------------------------===//
3611 // AVX-512 Logical Instructions
3612 //===----------------------------------------------------------------------===//
3614 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3615 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3616 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3617 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3618 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3619 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3620 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3621 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3623 //===----------------------------------------------------------------------===//
3624 // AVX-512 FP arithmetic
3625 //===----------------------------------------------------------------------===//
3626 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3627 SDNode OpNode, SDNode VecNode, OpndItins itins,
3630 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3631 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3632 "$src2, $src1", "$src1, $src2",
3633 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3634 (i32 FROUND_CURRENT)),
3635 itins.rr, IsCommutable>;
3637 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3638 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3639 "$src2, $src1", "$src1, $src2",
3640 (VecNode (_.VT _.RC:$src1),
3641 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3642 (i32 FROUND_CURRENT)),
3643 itins.rm, IsCommutable>;
3644 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3645 Predicates = [HasAVX512] in {
3646 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3647 (ins _.FRC:$src1, _.FRC:$src2),
3648 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3649 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3651 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3652 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3653 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3654 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3655 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3659 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3660 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3662 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3663 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3664 "$rc, $src2, $src1", "$src1, $src2, $rc",
3665 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3666 (i32 imm:$rc)), itins.rr, IsCommutable>,
3669 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3670 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3672 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3673 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3674 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3675 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3676 (i32 FROUND_NO_EXC))>, EVEX_B;
3679 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3681 SizeItins itins, bit IsCommutable> {
3682 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3683 itins.s, IsCommutable>,
3684 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3685 itins.s, IsCommutable>,
3686 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3687 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3688 itins.d, IsCommutable>,
3689 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3690 itins.d, IsCommutable>,
3691 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3694 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3696 SizeItins itins, bit IsCommutable> {
3697 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3698 itins.s, IsCommutable>,
3699 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3700 itins.s, IsCommutable>,
3701 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3702 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3703 itins.d, IsCommutable>,
3704 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3705 itins.d, IsCommutable>,
3706 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3708 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3709 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3710 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3711 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3712 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3713 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3715 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3716 X86VectorVTInfo _, bit IsCommutable> {
3717 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3718 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3719 "$src2, $src1", "$src1, $src2",
3720 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3721 let mayLoad = 1 in {
3722 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3723 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3724 "$src2, $src1", "$src1, $src2",
3725 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3726 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3727 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3728 "${src2}"##_.BroadcastStr##", $src1",
3729 "$src1, ${src2}"##_.BroadcastStr,
3730 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3731 (_.ScalarLdFrag addr:$src2))))>,
3736 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3737 X86VectorVTInfo _> {
3738 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3739 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3740 "$rc, $src2, $src1", "$src1, $src2, $rc",
3741 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3742 EVEX_4V, EVEX_B, EVEX_RC;
3746 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3747 X86VectorVTInfo _> {
3748 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3749 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3750 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3751 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3755 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3756 bit IsCommutable = 0> {
3757 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3758 IsCommutable>, EVEX_V512, PS,
3759 EVEX_CD8<32, CD8VF>;
3760 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3761 IsCommutable>, EVEX_V512, PD, VEX_W,
3762 EVEX_CD8<64, CD8VF>;
3764 // Define only if AVX512VL feature is present.
3765 let Predicates = [HasVLX] in {
3766 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3767 IsCommutable>, EVEX_V128, PS,
3768 EVEX_CD8<32, CD8VF>;
3769 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3770 IsCommutable>, EVEX_V256, PS,
3771 EVEX_CD8<32, CD8VF>;
3772 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3773 IsCommutable>, EVEX_V128, PD, VEX_W,
3774 EVEX_CD8<64, CD8VF>;
3775 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3776 IsCommutable>, EVEX_V256, PD, VEX_W,
3777 EVEX_CD8<64, CD8VF>;
3781 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3782 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3783 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3784 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3785 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3788 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3789 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3790 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3791 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3792 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3795 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3796 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3797 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3798 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3799 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3800 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3801 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3802 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3803 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3804 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3805 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3806 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3807 let Predicates = [HasDQI] in {
3808 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3809 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3810 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3811 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3814 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3815 X86VectorVTInfo _> {
3816 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3817 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3818 "$src2, $src1", "$src1, $src2",
3819 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3820 let mayLoad = 1 in {
3821 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3822 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3823 "$src2, $src1", "$src1, $src2",
3824 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3825 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3826 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3827 "${src2}"##_.BroadcastStr##", $src1",
3828 "$src1, ${src2}"##_.BroadcastStr,
3829 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3830 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3835 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3836 X86VectorVTInfo _> {
3837 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3838 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3839 "$src2, $src1", "$src1, $src2",
3840 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3841 let mayLoad = 1 in {
3842 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3843 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3844 "$src2, $src1", "$src1, $src2",
3845 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3849 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3850 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3851 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3852 EVEX_V512, EVEX_CD8<32, CD8VF>;
3853 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3854 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3855 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3856 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3857 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3858 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3859 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3860 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3861 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3863 // Define only if AVX512VL feature is present.
3864 let Predicates = [HasVLX] in {
3865 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3866 EVEX_V128, EVEX_CD8<32, CD8VF>;
3867 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3868 EVEX_V256, EVEX_CD8<32, CD8VF>;
3869 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3870 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3871 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3872 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3875 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3877 //===----------------------------------------------------------------------===//
3878 // AVX-512 VPTESTM instructions
3879 //===----------------------------------------------------------------------===//
3881 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3882 X86VectorVTInfo _> {
3883 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3884 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3885 "$src2, $src1", "$src1, $src2",
3886 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3889 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3890 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3891 "$src2, $src1", "$src1, $src2",
3892 (OpNode (_.VT _.RC:$src1),
3893 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3895 EVEX_CD8<_.EltSize, CD8VF>;
3898 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3899 X86VectorVTInfo _> {
3901 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3902 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3903 "${src2}"##_.BroadcastStr##", $src1",
3904 "$src1, ${src2}"##_.BroadcastStr,
3905 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3906 (_.ScalarLdFrag addr:$src2))))>,
3907 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3909 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3910 AVX512VLVectorVTInfo _> {
3911 let Predicates = [HasAVX512] in
3912 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3913 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3915 let Predicates = [HasAVX512, HasVLX] in {
3916 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3917 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3918 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3919 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3923 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3924 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3926 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3927 avx512vl_i64_info>, VEX_W;
3930 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3932 let Predicates = [HasBWI] in {
3933 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3935 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3938 let Predicates = [HasVLX, HasBWI] in {
3940 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3942 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3944 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3946 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3951 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3953 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3954 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3956 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3957 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3959 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3960 (v16i32 VR512:$src2), (i16 -1))),
3961 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3963 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3964 (v8i64 VR512:$src2), (i8 -1))),
3965 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3967 //===----------------------------------------------------------------------===//
3968 // AVX-512 Shift instructions
3969 //===----------------------------------------------------------------------===//
3970 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3971 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3972 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3973 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3974 "$src2, $src1", "$src1, $src2",
3975 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3976 SSE_INTSHIFT_ITINS_P.rr>;
3978 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3979 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3980 "$src2, $src1", "$src1, $src2",
3981 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3983 SSE_INTSHIFT_ITINS_P.rm>;
3986 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3987 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3989 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3990 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3991 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3992 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3993 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3996 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3997 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3998 // src2 is always 128-bit
3999 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4000 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
4001 "$src2, $src1", "$src1, $src2",
4002 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
4003 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
4004 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4005 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
4006 "$src2, $src1", "$src1, $src2",
4007 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
4008 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
4012 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4013 ValueType SrcVT, PatFrag bc_frag,
4014 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
4015 let Predicates = [prd] in
4016 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4017 VTInfo.info512>, EVEX_V512,
4018 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
4019 let Predicates = [prd, HasVLX] in {
4020 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4021 VTInfo.info256>, EVEX_V256,
4022 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
4023 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4024 VTInfo.info128>, EVEX_V128,
4025 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
4029 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
4030 string OpcodeStr, SDNode OpNode> {
4031 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
4032 avx512vl_i32_info, HasAVX512>;
4033 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
4034 avx512vl_i64_info, HasAVX512>, VEX_W;
4035 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
4036 avx512vl_i16_info, HasBWI>;
4039 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4040 string OpcodeStr, SDNode OpNode,
4041 AVX512VLVectorVTInfo VTInfo> {
4042 let Predicates = [HasAVX512] in
4043 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4045 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4046 VTInfo.info512>, EVEX_V512;
4047 let Predicates = [HasAVX512, HasVLX] in {
4048 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4050 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4051 VTInfo.info256>, EVEX_V256;
4052 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4054 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4055 VTInfo.info128>, EVEX_V128;
4059 multiclass avx512_shift_rmi_w<bits<8> opcw,
4060 Format ImmFormR, Format ImmFormM,
4061 string OpcodeStr, SDNode OpNode> {
4062 let Predicates = [HasBWI] in
4063 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4064 v32i16_info>, EVEX_V512;
4065 let Predicates = [HasVLX, HasBWI] in {
4066 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4067 v16i16x_info>, EVEX_V256;
4068 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4069 v8i16x_info>, EVEX_V128;
4073 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
4074 Format ImmFormR, Format ImmFormM,
4075 string OpcodeStr, SDNode OpNode> {
4076 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
4077 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
4078 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4079 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4082 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4083 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4085 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4086 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4088 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4089 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4091 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4092 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4094 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4095 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4096 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4098 //===-------------------------------------------------------------------===//
4099 // Variable Bit Shifts
4100 //===-------------------------------------------------------------------===//
4101 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4102 X86VectorVTInfo _> {
4103 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4104 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4105 "$src2, $src1", "$src1, $src2",
4106 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4107 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4109 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4110 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4111 "$src2, $src1", "$src1, $src2",
4112 (_.VT (OpNode _.RC:$src1,
4113 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4114 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4115 EVEX_CD8<_.EltSize, CD8VF>;
4118 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4119 X86VectorVTInfo _> {
4121 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4122 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4123 "${src2}"##_.BroadcastStr##", $src1",
4124 "$src1, ${src2}"##_.BroadcastStr,
4125 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4126 (_.ScalarLdFrag addr:$src2))))),
4127 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4128 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4130 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4131 AVX512VLVectorVTInfo _> {
4132 let Predicates = [HasAVX512] in
4133 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4134 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4136 let Predicates = [HasAVX512, HasVLX] in {
4137 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4138 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4139 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4140 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4144 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4146 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4148 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4149 avx512vl_i64_info>, VEX_W;
4152 // Use 512bit version to implement 128/256 bit in case NoVLX.
4153 multiclass avx512_var_shift_w_lowering<AVX512VLVectorVTInfo _, SDNode OpNode> {
4154 let Predicates = [HasBWI, NoVLX] in {
4155 def : Pat<(_.info256.VT (OpNode (_.info256.VT _.info256.RC:$src1),
4156 (_.info256.VT _.info256.RC:$src2))),
4158 (!cast<Instruction>(NAME#"WZrr")
4159 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
4160 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)),
4163 def : Pat<(_.info128.VT (OpNode (_.info128.VT _.info128.RC:$src1),
4164 (_.info128.VT _.info128.RC:$src2))),
4166 (!cast<Instruction>(NAME#"WZrr")
4167 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
4168 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)),
4173 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4175 let Predicates = [HasBWI] in
4176 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4178 let Predicates = [HasVLX, HasBWI] in {
4180 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4182 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4187 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4188 avx512_var_shift_w<0x12, "vpsllvw", shl>,
4189 avx512_var_shift_w_lowering<avx512vl_i16_info, shl>;
4190 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4191 avx512_var_shift_w<0x11, "vpsravw", sra>,
4192 avx512_var_shift_w_lowering<avx512vl_i16_info, sra>;
4193 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4194 avx512_var_shift_w<0x10, "vpsrlvw", srl>,
4195 avx512_var_shift_w_lowering<avx512vl_i16_info, srl>;
4196 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4197 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4199 //===-------------------------------------------------------------------===//
4200 // 1-src variable permutation VPERMW/D/Q
4201 //===-------------------------------------------------------------------===//
4202 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4203 AVX512VLVectorVTInfo _> {
4204 let Predicates = [HasAVX512] in
4205 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4206 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4208 let Predicates = [HasAVX512, HasVLX] in
4209 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4210 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4213 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4214 string OpcodeStr, SDNode OpNode,
4215 AVX512VLVectorVTInfo VTInfo> {
4216 let Predicates = [HasAVX512] in
4217 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4219 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4220 VTInfo.info512>, EVEX_V512;
4221 let Predicates = [HasAVX512, HasVLX] in
4222 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4224 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4225 VTInfo.info256>, EVEX_V256;
4229 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4231 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4233 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4234 avx512vl_i64_info>, VEX_W;
4235 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4237 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4238 avx512vl_f64_info>, VEX_W;
4240 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4241 X86VPermi, avx512vl_i64_info>,
4242 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4243 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4244 X86VPermi, avx512vl_f64_info>,
4245 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4246 //===----------------------------------------------------------------------===//
4247 // AVX-512 - VPERMIL
4248 //===----------------------------------------------------------------------===//
4250 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4251 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4252 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4253 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4254 "$src2, $src1", "$src1, $src2",
4255 (_.VT (OpNode _.RC:$src1,
4256 (Ctrl.VT Ctrl.RC:$src2)))>,
4258 let mayLoad = 1 in {
4259 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4260 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4261 "$src2, $src1", "$src1, $src2",
4264 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4265 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4266 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4267 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4268 "${src2}"##_.BroadcastStr##", $src1",
4269 "$src1, ${src2}"##_.BroadcastStr,
4272 (Ctrl.VT (X86VBroadcast
4273 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4274 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4278 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4279 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4280 let Predicates = [HasAVX512] in {
4281 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4282 Ctrl.info512>, EVEX_V512;
4284 let Predicates = [HasAVX512, HasVLX] in {
4285 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4286 Ctrl.info128>, EVEX_V128;
4287 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4288 Ctrl.info256>, EVEX_V256;
4292 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4293 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4295 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4296 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4298 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4301 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4303 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4304 avx512vl_i64_info>, VEX_W;
4305 //===----------------------------------------------------------------------===//
4306 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4307 //===----------------------------------------------------------------------===//
4309 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4310 X86PShufd, avx512vl_i32_info>,
4311 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4312 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4313 X86PShufhw>, EVEX, AVX512XSIi8Base;
4314 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4315 X86PShuflw>, EVEX, AVX512XDIi8Base;
4317 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4318 let Predicates = [HasBWI] in
4319 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4321 let Predicates = [HasVLX, HasBWI] in {
4322 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4323 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4327 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4329 //===----------------------------------------------------------------------===//
4330 // Move Low to High and High to Low packed FP Instructions
4331 //===----------------------------------------------------------------------===//
4332 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4333 (ins VR128X:$src1, VR128X:$src2),
4334 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4335 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4336 IIC_SSE_MOV_LH>, EVEX_4V;
4337 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4338 (ins VR128X:$src1, VR128X:$src2),
4339 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4340 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4341 IIC_SSE_MOV_LH>, EVEX_4V;
4343 let Predicates = [HasAVX512] in {
4345 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4346 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4347 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4348 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4351 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4352 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4355 //===----------------------------------------------------------------------===//
4356 // VMOVHPS/PD VMOVLPS Instructions
4357 // All patterns was taken from SSS implementation.
4358 //===----------------------------------------------------------------------===//
4359 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4360 X86VectorVTInfo _> {
4362 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
4363 (ins _.RC:$src1, f64mem:$src2),
4364 !strconcat(OpcodeStr,
4365 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4369 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
4370 IIC_SSE_MOV_LH>, EVEX_4V;
4373 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
4374 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4375 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
4376 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4377 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
4378 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4379 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
4380 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4382 let Predicates = [HasAVX512] in {
4384 def : Pat<(X86Movlhps VR128X:$src1,
4385 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
4386 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4387 def : Pat<(X86Movlhps VR128X:$src1,
4388 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
4389 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4391 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4392 (scalar_to_vector (loadf64 addr:$src2)))),
4393 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4394 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4395 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
4396 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4398 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4399 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4400 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4401 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4403 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4404 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4405 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4406 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4407 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
4408 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
4409 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4412 let mayStore = 1 in {
4413 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
4414 (ins f64mem:$dst, VR128X:$src),
4415 "vmovhps\t{$src, $dst|$dst, $src}",
4416 [(store (f64 (vector_extract
4417 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
4418 (bc_v2f64 (v4f32 VR128X:$src))),
4419 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4420 EVEX, EVEX_CD8<32, CD8VT2>;
4421 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
4422 (ins f64mem:$dst, VR128X:$src),
4423 "vmovhpd\t{$src, $dst|$dst, $src}",
4424 [(store (f64 (vector_extract
4425 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
4426 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4427 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4428 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
4429 (ins f64mem:$dst, VR128X:$src),
4430 "vmovlps\t{$src, $dst|$dst, $src}",
4431 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128X:$src)),
4432 (iPTR 0))), addr:$dst)],
4434 EVEX, EVEX_CD8<32, CD8VT2>;
4435 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
4436 (ins f64mem:$dst, VR128X:$src),
4437 "vmovlpd\t{$src, $dst|$dst, $src}",
4438 [(store (f64 (vector_extract (v2f64 VR128X:$src),
4439 (iPTR 0))), addr:$dst)],
4441 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4443 let Predicates = [HasAVX512] in {
4445 def : Pat<(store (f64 (vector_extract
4446 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
4447 (iPTR 0))), addr:$dst),
4448 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
4450 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
4452 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4453 def : Pat<(store (v4i32 (X86Movlps
4454 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
4455 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4457 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4459 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4460 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4462 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4464 //===----------------------------------------------------------------------===//
4465 // FMA - Fused Multiply Operations
4468 let Constraints = "$src1 = $dst" in {
4469 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4470 X86VectorVTInfo _> {
4471 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4472 (ins _.RC:$src2, _.RC:$src3),
4473 OpcodeStr, "$src3, $src2", "$src2, $src3",
4474 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4477 let mayLoad = 1 in {
4478 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4479 (ins _.RC:$src2, _.MemOp:$src3),
4480 OpcodeStr, "$src3, $src2", "$src2, $src3",
4481 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4484 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4485 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4486 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4487 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4489 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4490 AVX512FMA3Base, EVEX_B;
4494 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4495 X86VectorVTInfo _> {
4496 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4497 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4498 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4499 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4500 AVX512FMA3Base, EVEX_B, EVEX_RC;
4502 } // Constraints = "$src1 = $dst"
4504 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4505 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4506 let Predicates = [HasAVX512] in {
4507 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4508 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4509 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4511 let Predicates = [HasVLX, HasAVX512] in {
4512 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4513 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4514 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4515 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4519 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4520 SDNode OpNodeRnd > {
4521 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4523 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4524 avx512vl_f64_info>, VEX_W;
4527 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4528 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4529 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4530 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4531 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4532 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4535 let Constraints = "$src1 = $dst" in {
4536 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4537 X86VectorVTInfo _> {
4538 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4539 (ins _.RC:$src2, _.RC:$src3),
4540 OpcodeStr, "$src3, $src2", "$src2, $src3",
4541 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4544 let mayLoad = 1 in {
4545 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4546 (ins _.RC:$src2, _.MemOp:$src3),
4547 OpcodeStr, "$src3, $src2", "$src2, $src3",
4548 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4551 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4552 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4553 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4554 "$src2, ${src3}"##_.BroadcastStr,
4555 (_.VT (OpNode _.RC:$src2,
4556 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4557 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4561 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4562 X86VectorVTInfo _> {
4563 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4564 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4565 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4566 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4567 AVX512FMA3Base, EVEX_B, EVEX_RC;
4569 } // Constraints = "$src1 = $dst"
4571 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4572 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4573 let Predicates = [HasAVX512] in {
4574 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4575 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4576 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4578 let Predicates = [HasVLX, HasAVX512] in {
4579 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4580 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4581 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4582 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4586 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4587 SDNode OpNodeRnd > {
4588 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4590 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4591 avx512vl_f64_info>, VEX_W;
4594 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4595 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4596 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4597 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4598 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4599 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4601 let Constraints = "$src1 = $dst" in {
4602 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4603 X86VectorVTInfo _> {
4604 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4605 (ins _.RC:$src3, _.RC:$src2),
4606 OpcodeStr, "$src2, $src3", "$src3, $src2",
4607 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4610 let mayLoad = 1 in {
4611 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4612 (ins _.RC:$src3, _.MemOp:$src2),
4613 OpcodeStr, "$src2, $src3", "$src3, $src2",
4614 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4617 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4618 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4619 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4620 "$src3, ${src2}"##_.BroadcastStr,
4621 (_.VT (OpNode _.RC:$src1,
4622 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4623 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4627 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4628 X86VectorVTInfo _> {
4629 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4630 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4631 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4632 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4633 AVX512FMA3Base, EVEX_B, EVEX_RC;
4635 } // Constraints = "$src1 = $dst"
4637 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4638 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4639 let Predicates = [HasAVX512] in {
4640 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4641 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4642 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4644 let Predicates = [HasVLX, HasAVX512] in {
4645 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4646 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4647 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4648 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4652 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4653 SDNode OpNodeRnd > {
4654 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4656 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4657 avx512vl_f64_info>, VEX_W;
4660 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4661 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4662 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4663 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4664 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4665 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4668 let Constraints = "$src1 = $dst" in {
4669 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4670 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4671 dag RHS_r, dag RHS_m > {
4672 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4673 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4674 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4677 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4678 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4679 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4681 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4682 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4683 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4684 AVX512FMA3Base, EVEX_B, EVEX_RC;
4686 let isCodeGenOnly = 1 in {
4687 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4688 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4689 !strconcat(OpcodeStr,
4690 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4693 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4694 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4695 !strconcat(OpcodeStr,
4696 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4698 }// isCodeGenOnly = 1
4700 }// Constraints = "$src1 = $dst"
4702 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4703 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4706 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4707 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4708 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4709 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4710 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4712 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4714 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4715 (_.ScalarLdFrag addr:$src3))))>;
4717 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4718 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4719 (_.VT (OpNode _.RC:$src2,
4720 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4722 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4724 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4726 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4727 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4729 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4730 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4731 (_.VT (OpNode _.RC:$src1,
4732 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4734 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4736 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4738 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4739 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4742 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4743 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4744 let Predicates = [HasAVX512] in {
4745 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4746 OpNodeRnd, f32x_info, "SS">,
4747 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4748 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4749 OpNodeRnd, f64x_info, "SD">,
4750 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4754 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4755 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4756 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4757 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4759 //===----------------------------------------------------------------------===//
4760 // AVX-512 Scalar convert from sign integer to float/double
4761 //===----------------------------------------------------------------------===//
4763 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4764 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4765 PatFrag ld_frag, string asm> {
4766 let hasSideEffects = 0 in {
4767 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4768 (ins DstVT.FRC:$src1, SrcRC:$src),
4769 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4772 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4773 (ins DstVT.FRC:$src1, x86memop:$src),
4774 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4776 } // hasSideEffects = 0
4777 let isCodeGenOnly = 1 in {
4778 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4779 (ins DstVT.RC:$src1, SrcRC:$src2),
4780 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4781 [(set DstVT.RC:$dst,
4782 (OpNode (DstVT.VT DstVT.RC:$src1),
4784 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4786 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4787 (ins DstVT.RC:$src1, x86memop:$src2),
4788 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4789 [(set DstVT.RC:$dst,
4790 (OpNode (DstVT.VT DstVT.RC:$src1),
4791 (ld_frag addr:$src2),
4792 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4793 }//isCodeGenOnly = 1
4796 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4797 X86VectorVTInfo DstVT, string asm> {
4798 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4799 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4801 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4802 [(set DstVT.RC:$dst,
4803 (OpNode (DstVT.VT DstVT.RC:$src1),
4805 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4808 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4809 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4810 PatFrag ld_frag, string asm> {
4811 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4812 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4816 let Predicates = [HasAVX512] in {
4817 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4818 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4819 XS, EVEX_CD8<32, CD8VT1>;
4820 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4821 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4822 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4823 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4824 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4825 XD, EVEX_CD8<32, CD8VT1>;
4826 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4827 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4828 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4830 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4831 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4832 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4833 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4834 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4835 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4836 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4837 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4839 def : Pat<(f32 (sint_to_fp GR32:$src)),
4840 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4841 def : Pat<(f32 (sint_to_fp GR64:$src)),
4842 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4843 def : Pat<(f64 (sint_to_fp GR32:$src)),
4844 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4845 def : Pat<(f64 (sint_to_fp GR64:$src)),
4846 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4848 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4849 v4f32x_info, i32mem, loadi32,
4850 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4851 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4852 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4853 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4854 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4855 i32mem, loadi32, "cvtusi2sd{l}">,
4856 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4857 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4858 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4859 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4861 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4862 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4863 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4864 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4865 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4866 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4867 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4868 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4870 def : Pat<(f32 (uint_to_fp GR32:$src)),
4871 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4872 def : Pat<(f32 (uint_to_fp GR64:$src)),
4873 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4874 def : Pat<(f64 (uint_to_fp GR32:$src)),
4875 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4876 def : Pat<(f64 (uint_to_fp GR64:$src)),
4877 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4880 //===----------------------------------------------------------------------===//
4881 // AVX-512 Scalar convert from float/double to integer
4882 //===----------------------------------------------------------------------===//
4883 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4884 RegisterClass DstRC, Intrinsic Int,
4885 Operand memop, ComplexPattern mem_cpat, string asm> {
4886 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4887 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4888 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4889 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4890 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4891 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4892 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4894 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4895 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4896 } // hasSideEffects = 0, Predicates = [HasAVX512]
4899 // Convert float/double to signed/unsigned int 32/64
4900 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4901 ssmem, sse_load_f32, "cvtss2si">,
4902 XS, EVEX_CD8<32, CD8VT1>;
4903 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4904 int_x86_sse_cvtss2si64,
4905 ssmem, sse_load_f32, "cvtss2si">,
4906 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4907 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4908 int_x86_avx512_cvtss2usi,
4909 ssmem, sse_load_f32, "cvtss2usi">,
4910 XS, EVEX_CD8<32, CD8VT1>;
4911 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4912 int_x86_avx512_cvtss2usi64, ssmem,
4913 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4914 EVEX_CD8<32, CD8VT1>;
4915 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4916 sdmem, sse_load_f64, "cvtsd2si">,
4917 XD, EVEX_CD8<64, CD8VT1>;
4918 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4919 int_x86_sse2_cvtsd2si64,
4920 sdmem, sse_load_f64, "cvtsd2si">,
4921 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4922 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4923 int_x86_avx512_cvtsd2usi,
4924 sdmem, sse_load_f64, "cvtsd2usi">,
4925 XD, EVEX_CD8<64, CD8VT1>;
4926 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4927 int_x86_avx512_cvtsd2usi64, sdmem,
4928 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4929 EVEX_CD8<64, CD8VT1>;
4931 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4932 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4933 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4934 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4935 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4936 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4937 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4938 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4939 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4940 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4941 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4942 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4943 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4945 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4946 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4947 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4948 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4950 // Convert float/double to signed/unsigned int 32/64 with truncation
4951 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4952 X86VectorVTInfo _DstRC, SDNode OpNode,
4954 let Predicates = [HasAVX512] in {
4955 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4956 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4957 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4958 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4959 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4961 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4962 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4963 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4966 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4967 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4968 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4969 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4970 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4971 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4972 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4973 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4974 (i32 FROUND_NO_EXC)))]>,
4975 EVEX,VEX_LIG , EVEX_B;
4977 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4978 (ins _SrcRC.MemOp:$src),
4979 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4982 } // isCodeGenOnly = 1, hasSideEffects = 0
4987 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4988 fp_to_sint,X86cvttss2IntRnd>,
4989 XS, EVEX_CD8<32, CD8VT1>;
4990 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4991 fp_to_sint,X86cvttss2IntRnd>,
4992 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4993 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4994 fp_to_sint,X86cvttsd2IntRnd>,
4995 XD, EVEX_CD8<64, CD8VT1>;
4996 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4997 fp_to_sint,X86cvttsd2IntRnd>,
4998 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
5000 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
5001 fp_to_uint,X86cvttss2UIntRnd>,
5002 XS, EVEX_CD8<32, CD8VT1>;
5003 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
5004 fp_to_uint,X86cvttss2UIntRnd>,
5005 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
5006 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
5007 fp_to_uint,X86cvttsd2UIntRnd>,
5008 XD, EVEX_CD8<64, CD8VT1>;
5009 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
5010 fp_to_uint,X86cvttsd2UIntRnd>,
5011 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5012 let Predicates = [HasAVX512] in {
5013 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
5014 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5015 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
5016 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5017 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
5018 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5019 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
5020 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5023 //===----------------------------------------------------------------------===//
5024 // AVX-512 Convert form float to double and back
5025 //===----------------------------------------------------------------------===//
5026 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5027 X86VectorVTInfo _Src, SDNode OpNode> {
5028 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5029 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5030 "$src2, $src1", "$src1, $src2",
5031 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5032 (_Src.VT _Src.RC:$src2)))>,
5033 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
5034 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5035 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
5036 "$src2, $src1", "$src1, $src2",
5037 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5038 (_Src.VT (scalar_to_vector
5039 (_Src.ScalarLdFrag addr:$src2)))))>,
5040 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
5043 // Scalar Coversion with SAE - suppress all exceptions
5044 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5045 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5046 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5047 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5048 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5049 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5050 (_Src.VT _Src.RC:$src2),
5051 (i32 FROUND_NO_EXC)))>,
5052 EVEX_4V, VEX_LIG, EVEX_B;
5055 // Scalar Conversion with rounding control (RC)
5056 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5057 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5058 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5059 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
5060 "$rc, $src2, $src1", "$src1, $src2, $rc",
5061 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5062 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
5063 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
5066 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
5067 SDNode OpNodeRnd, X86VectorVTInfo _src,
5068 X86VectorVTInfo _dst> {
5069 let Predicates = [HasAVX512] in {
5070 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5071 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
5072 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
5077 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5078 SDNode OpNodeRnd, X86VectorVTInfo _src,
5079 X86VectorVTInfo _dst> {
5080 let Predicates = [HasAVX512] in {
5081 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5082 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
5083 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
5086 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
5087 X86froundRnd, f64x_info, f32x_info>;
5088 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
5089 X86fpextRnd,f32x_info, f64x_info >;
5091 def : Pat<(f64 (fextend FR32X:$src)),
5092 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
5093 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
5094 Requires<[HasAVX512]>;
5095 def : Pat<(f64 (fextend (loadf32 addr:$src))),
5096 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5097 Requires<[HasAVX512]>;
5099 def : Pat<(f64 (extloadf32 addr:$src)),
5100 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5101 Requires<[HasAVX512, OptForSize]>;
5103 def : Pat<(f64 (extloadf32 addr:$src)),
5104 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
5105 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
5106 Requires<[HasAVX512, OptForSpeed]>;
5108 def : Pat<(f32 (fround FR64X:$src)),
5109 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
5110 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
5111 Requires<[HasAVX512]>;
5112 //===----------------------------------------------------------------------===//
5113 // AVX-512 Vector convert from signed/unsigned integer to float/double
5114 // and from float/double to signed/unsigned integer
5115 //===----------------------------------------------------------------------===//
5117 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5118 X86VectorVTInfo _Src, SDNode OpNode,
5119 string Broadcast = _.BroadcastStr,
5120 string Alias = ""> {
5122 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5123 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
5124 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
5126 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5127 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
5128 (_.VT (OpNode (_Src.VT
5129 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
5131 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5132 (ins _Src.MemOp:$src), OpcodeStr,
5133 "${src}"##Broadcast, "${src}"##Broadcast,
5134 (_.VT (OpNode (_Src.VT
5135 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
5138 // Coversion with SAE - suppress all exceptions
5139 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5140 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5141 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5142 (ins _Src.RC:$src), OpcodeStr,
5143 "{sae}, $src", "$src, {sae}",
5144 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
5145 (i32 FROUND_NO_EXC)))>,
5149 // Conversion with rounding control (RC)
5150 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5151 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5152 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5153 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5154 "$rc, $src", "$src, $rc",
5155 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5156 EVEX, EVEX_B, EVEX_RC;
5159 // Extend Float to Double
5160 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5161 let Predicates = [HasAVX512] in {
5162 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5163 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5164 X86vfpextRnd>, EVEX_V512;
5166 let Predicates = [HasVLX] in {
5167 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5168 X86vfpext, "{1to2}">, EVEX_V128;
5169 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5174 // Truncate Double to Float
5175 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5176 let Predicates = [HasAVX512] in {
5177 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5178 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5179 X86vfproundRnd>, EVEX_V512;
5181 let Predicates = [HasVLX] in {
5182 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5183 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5184 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5185 "{1to4}", "{y}">, EVEX_V256;
5189 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5190 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5191 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5192 PS, EVEX_CD8<32, CD8VH>;
5194 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5195 (VCVTPS2PDZrm addr:$src)>;
5197 let Predicates = [HasVLX] in {
5198 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5199 (VCVTPS2PDZ256rm addr:$src)>;
5202 // Convert Signed/Unsigned Doubleword to Double
5203 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5205 // No rounding in this op
5206 let Predicates = [HasAVX512] in
5207 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5210 let Predicates = [HasVLX] in {
5211 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5212 OpNode128, "{1to2}">, EVEX_V128;
5213 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5218 // Convert Signed/Unsigned Doubleword to Float
5219 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5221 let Predicates = [HasAVX512] in
5222 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5223 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5224 OpNodeRnd>, EVEX_V512;
5226 let Predicates = [HasVLX] in {
5227 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5229 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5234 // Convert Float to Signed/Unsigned Doubleword with truncation
5235 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5236 SDNode OpNode, SDNode OpNodeRnd> {
5237 let Predicates = [HasAVX512] in {
5238 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5239 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5240 OpNodeRnd>, EVEX_V512;
5242 let Predicates = [HasVLX] in {
5243 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5245 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5250 // Convert Float to Signed/Unsigned Doubleword
5251 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5252 SDNode OpNode, SDNode OpNodeRnd> {
5253 let Predicates = [HasAVX512] in {
5254 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5255 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5256 OpNodeRnd>, EVEX_V512;
5258 let Predicates = [HasVLX] in {
5259 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5261 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5266 // Convert Double to Signed/Unsigned Doubleword with truncation
5267 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5268 SDNode OpNode, SDNode OpNodeRnd> {
5269 let Predicates = [HasAVX512] in {
5270 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5271 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5272 OpNodeRnd>, EVEX_V512;
5274 let Predicates = [HasVLX] in {
5275 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5276 // memory forms of these instructions in Asm Parcer. They have the same
5277 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5278 // due to the same reason.
5279 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5280 "{1to2}", "{x}">, EVEX_V128;
5281 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5282 "{1to4}", "{y}">, EVEX_V256;
5286 // Convert Double to Signed/Unsigned Doubleword
5287 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5288 SDNode OpNode, SDNode OpNodeRnd> {
5289 let Predicates = [HasAVX512] in {
5290 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5291 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5292 OpNodeRnd>, EVEX_V512;
5294 let Predicates = [HasVLX] in {
5295 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5296 // memory forms of these instructions in Asm Parcer. They have the same
5297 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5298 // due to the same reason.
5299 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5300 "{1to2}", "{x}">, EVEX_V128;
5301 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5302 "{1to4}", "{y}">, EVEX_V256;
5306 // Convert Double to Signed/Unsigned Quardword
5307 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5308 SDNode OpNode, SDNode OpNodeRnd> {
5309 let Predicates = [HasDQI] in {
5310 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5311 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5312 OpNodeRnd>, EVEX_V512;
5314 let Predicates = [HasDQI, HasVLX] in {
5315 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5317 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5322 // Convert Double to Signed/Unsigned Quardword with truncation
5323 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5324 SDNode OpNode, SDNode OpNodeRnd> {
5325 let Predicates = [HasDQI] in {
5326 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5327 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5328 OpNodeRnd>, EVEX_V512;
5330 let Predicates = [HasDQI, HasVLX] in {
5331 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5333 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5338 // Convert Signed/Unsigned Quardword to Double
5339 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5340 SDNode OpNode, SDNode OpNodeRnd> {
5341 let Predicates = [HasDQI] in {
5342 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5343 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5344 OpNodeRnd>, EVEX_V512;
5346 let Predicates = [HasDQI, HasVLX] in {
5347 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5349 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5354 // Convert Float to Signed/Unsigned Quardword
5355 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5356 SDNode OpNode, SDNode OpNodeRnd> {
5357 let Predicates = [HasDQI] in {
5358 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5359 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5360 OpNodeRnd>, EVEX_V512;
5362 let Predicates = [HasDQI, HasVLX] in {
5363 // Explicitly specified broadcast string, since we take only 2 elements
5364 // from v4f32x_info source
5365 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5366 "{1to2}">, EVEX_V128;
5367 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5372 // Convert Float to Signed/Unsigned Quardword with truncation
5373 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5374 SDNode OpNode, SDNode OpNodeRnd> {
5375 let Predicates = [HasDQI] in {
5376 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5377 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5378 OpNodeRnd>, EVEX_V512;
5380 let Predicates = [HasDQI, HasVLX] in {
5381 // Explicitly specified broadcast string, since we take only 2 elements
5382 // from v4f32x_info source
5383 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5384 "{1to2}">, EVEX_V128;
5385 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5390 // Convert Signed/Unsigned Quardword to Float
5391 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5392 SDNode OpNode, SDNode OpNodeRnd> {
5393 let Predicates = [HasDQI] in {
5394 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5395 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5396 OpNodeRnd>, EVEX_V512;
5398 let Predicates = [HasDQI, HasVLX] in {
5399 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5400 // memory forms of these instructions in Asm Parcer. They have the same
5401 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5402 // due to the same reason.
5403 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5404 "{1to2}", "{x}">, EVEX_V128;
5405 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5406 "{1to4}", "{y}">, EVEX_V256;
5410 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5411 EVEX_CD8<32, CD8VH>;
5413 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5415 PS, EVEX_CD8<32, CD8VF>;
5417 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5419 XS, EVEX_CD8<32, CD8VF>;
5421 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5423 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5425 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5426 X86VFpToUintRnd>, PS,
5427 EVEX_CD8<32, CD8VF>;
5429 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5430 X86VFpToUintRnd>, PS, VEX_W,
5431 EVEX_CD8<64, CD8VF>;
5433 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5434 XS, EVEX_CD8<32, CD8VH>;
5436 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5437 X86VUintToFpRnd>, XD,
5438 EVEX_CD8<32, CD8VF>;
5440 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5441 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5443 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5444 X86cvtpd2IntRnd>, XD, VEX_W,
5445 EVEX_CD8<64, CD8VF>;
5447 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5449 PS, EVEX_CD8<32, CD8VF>;
5450 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5451 X86cvtpd2UIntRnd>, VEX_W,
5452 PS, EVEX_CD8<64, CD8VF>;
5454 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5455 X86cvtpd2IntRnd>, VEX_W,
5456 PD, EVEX_CD8<64, CD8VF>;
5458 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5459 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5461 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5462 X86cvtpd2UIntRnd>, VEX_W,
5463 PD, EVEX_CD8<64, CD8VF>;
5465 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5466 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5468 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5469 X86VFpToSlongRnd>, VEX_W,
5470 PD, EVEX_CD8<64, CD8VF>;
5472 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5473 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5475 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5476 X86VFpToUlongRnd>, VEX_W,
5477 PD, EVEX_CD8<64, CD8VF>;
5479 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5480 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5482 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5483 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5485 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5486 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5488 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5489 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5491 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5492 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5494 let Predicates = [HasAVX512, NoVLX] in {
5495 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5496 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5497 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5499 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5500 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5501 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5503 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5504 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5505 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5507 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5508 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5509 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5511 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5512 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5513 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5516 let Predicates = [HasAVX512] in {
5517 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5518 (VCVTPD2PSZrm addr:$src)>;
5519 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5520 (VCVTPS2PDZrm addr:$src)>;
5523 //===----------------------------------------------------------------------===//
5524 // Half precision conversion instructions
5525 //===----------------------------------------------------------------------===//
5526 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5527 X86MemOperand x86memop, PatFrag ld_frag> {
5528 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5529 "vcvtph2ps", "$src", "$src",
5530 (X86cvtph2ps (_src.VT _src.RC:$src),
5531 (i32 FROUND_CURRENT))>, T8PD;
5532 let hasSideEffects = 0, mayLoad = 1 in {
5533 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5534 "vcvtph2ps", "$src", "$src",
5535 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5536 (i32 FROUND_CURRENT))>, T8PD;
5540 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5541 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5542 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5543 (X86cvtph2ps (_src.VT _src.RC:$src),
5544 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5548 let Predicates = [HasAVX512] in {
5549 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5550 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5551 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5552 let Predicates = [HasVLX] in {
5553 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5554 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5555 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5556 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5560 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5561 X86MemOperand x86memop> {
5562 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5563 (ins _src.RC:$src1, i32u8imm:$src2),
5564 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5565 (X86cvtps2ph (_src.VT _src.RC:$src1),
5567 (i32 FROUND_CURRENT))>, AVX512AIi8Base;
5568 let hasSideEffects = 0, mayStore = 1 in {
5569 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5570 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5571 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5572 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5573 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5575 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5576 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5577 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5581 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5582 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5583 (ins _src.RC:$src1, i32u8imm:$src2),
5584 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, $src2, {sae}",
5585 (X86cvtps2ph (_src.VT _src.RC:$src1),
5587 (i32 FROUND_NO_EXC))>, EVEX_B, AVX512AIi8Base;
5589 let Predicates = [HasAVX512] in {
5590 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5591 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5592 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5593 let Predicates = [HasVLX] in {
5594 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5595 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5596 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5597 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5601 // Unordered/Ordered scalar fp compare with Sea and set EFLAGS
5602 multiclass avx512_ord_cmp_sae<bits<8> opc, X86VectorVTInfo _, SDNode OpNode,
5604 def rb: AVX512<opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),
5605 !strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"),
5606 [(set EFLAGS, (OpNode (_.VT _.RC:$src1), _.RC:$src2,
5607 (i32 FROUND_NO_EXC)))],
5608 IIC_SSE_COMIS_RR>, EVEX, EVEX_B, VEX_LIG, EVEX_V128,
5612 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5613 defm VUCOMISSZ : avx512_ord_cmp_sae<0x2E, v4f32x_info, X86ucomiSae, "vucomiss">,
5614 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
5615 defm VUCOMISDZ : avx512_ord_cmp_sae<0x2E, v2f64x_info, X86ucomiSae, "vucomisd">,
5616 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
5617 defm VCOMISSZ : avx512_ord_cmp_sae<0x2F, v4f32x_info, X86comiSae, "vcomiss">,
5618 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
5619 defm VCOMISDZ : avx512_ord_cmp_sae<0x2F, v2f64x_info, X86comiSae, "vcomisd">,
5620 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
5623 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5624 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5625 "ucomiss">, PS, EVEX, VEX_LIG,
5626 EVEX_CD8<32, CD8VT1>;
5627 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5628 "ucomisd">, PD, EVEX,
5629 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5630 let Pattern = []<dag> in {
5631 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5632 "comiss">, PS, EVEX, VEX_LIG,
5633 EVEX_CD8<32, CD8VT1>;
5634 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5635 "comisd">, PD, EVEX,
5636 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5638 let isCodeGenOnly = 1 in {
5639 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5640 load, "ucomiss">, PS, EVEX, VEX_LIG,
5641 EVEX_CD8<32, CD8VT1>;
5642 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5643 load, "ucomisd">, PD, EVEX,
5644 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5646 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5647 load, "comiss">, PS, EVEX, VEX_LIG,
5648 EVEX_CD8<32, CD8VT1>;
5649 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5650 load, "comisd">, PD, EVEX,
5651 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5655 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5656 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5657 X86VectorVTInfo _> {
5658 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5659 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5660 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5661 "$src2, $src1", "$src1, $src2",
5662 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5663 let mayLoad = 1 in {
5664 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5665 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5666 "$src2, $src1", "$src1, $src2",
5667 (OpNode (_.VT _.RC:$src1),
5668 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5673 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5674 EVEX_CD8<32, CD8VT1>, T8PD;
5675 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5676 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5677 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5678 EVEX_CD8<32, CD8VT1>, T8PD;
5679 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5680 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5682 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5683 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5684 X86VectorVTInfo _> {
5685 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5686 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5687 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5688 let mayLoad = 1 in {
5689 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5690 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5692 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5693 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5694 (ins _.ScalarMemOp:$src), OpcodeStr,
5695 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5697 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5702 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5703 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5704 EVEX_V512, EVEX_CD8<32, CD8VF>;
5705 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5706 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5708 // Define only if AVX512VL feature is present.
5709 let Predicates = [HasVLX] in {
5710 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5711 OpNode, v4f32x_info>,
5712 EVEX_V128, EVEX_CD8<32, CD8VF>;
5713 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5714 OpNode, v8f32x_info>,
5715 EVEX_V256, EVEX_CD8<32, CD8VF>;
5716 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5717 OpNode, v2f64x_info>,
5718 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5719 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5720 OpNode, v4f64x_info>,
5721 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5725 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5726 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5728 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5729 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5732 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5733 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5734 "$src2, $src1", "$src1, $src2",
5735 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5736 (i32 FROUND_CURRENT))>;
5738 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5739 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5740 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5741 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5742 (i32 FROUND_NO_EXC))>, EVEX_B;
5744 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5745 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5746 "$src2, $src1", "$src1, $src2",
5747 (OpNode (_.VT _.RC:$src1),
5748 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5749 (i32 FROUND_CURRENT))>;
5752 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5753 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5754 EVEX_CD8<32, CD8VT1>;
5755 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5756 EVEX_CD8<64, CD8VT1>, VEX_W;
5759 let hasSideEffects = 0, Predicates = [HasERI] in {
5760 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5761 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5764 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5765 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5767 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5770 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5771 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5772 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5774 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5775 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5777 (bitconvert (_.LdFrag addr:$src))),
5778 (i32 FROUND_CURRENT))>;
5780 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5781 (ins _.MemOp:$src), OpcodeStr,
5782 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5784 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5785 (i32 FROUND_CURRENT))>, EVEX_B;
5787 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5789 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5790 (ins _.RC:$src), OpcodeStr,
5791 "{sae}, $src", "$src, {sae}",
5792 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5795 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5796 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5797 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5798 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5799 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5800 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5801 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5804 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5806 // Define only if AVX512VL feature is present.
5807 let Predicates = [HasVLX] in {
5808 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5809 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5810 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5811 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5812 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5813 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5814 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5815 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5818 let Predicates = [HasERI], hasSideEffects = 0 in {
5820 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5821 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5822 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5824 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5825 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5827 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5828 SDNode OpNodeRnd, X86VectorVTInfo _>{
5829 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5830 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5831 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5832 EVEX, EVEX_B, EVEX_RC;
5835 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5836 SDNode OpNode, X86VectorVTInfo _>{
5837 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5838 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5839 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5840 let mayLoad = 1 in {
5841 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5842 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5844 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5846 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5847 (ins _.ScalarMemOp:$src), OpcodeStr,
5848 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5850 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5855 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5857 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5859 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5860 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5862 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5863 // Define only if AVX512VL feature is present.
5864 let Predicates = [HasVLX] in {
5865 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5866 OpNode, v4f32x_info>,
5867 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5868 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5869 OpNode, v8f32x_info>,
5870 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5871 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5872 OpNode, v2f64x_info>,
5873 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5874 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5875 OpNode, v4f64x_info>,
5876 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5880 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5882 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5883 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5884 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5885 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5888 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5889 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5891 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5892 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5893 "$src2, $src1", "$src1, $src2",
5894 (OpNodeRnd (_.VT _.RC:$src1),
5896 (i32 FROUND_CURRENT))>;
5898 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5899 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5900 "$src2, $src1", "$src1, $src2",
5901 (OpNodeRnd (_.VT _.RC:$src1),
5902 (_.VT (scalar_to_vector
5903 (_.ScalarLdFrag addr:$src2))),
5904 (i32 FROUND_CURRENT))>;
5906 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5907 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5908 "$rc, $src2, $src1", "$src1, $src2, $rc",
5909 (OpNodeRnd (_.VT _.RC:$src1),
5914 let isCodeGenOnly = 1 in {
5915 def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
5916 (ins _.FRC:$src1, _.FRC:$src2),
5917 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5920 def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
5921 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5922 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5925 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5926 (!cast<Instruction>(NAME#SUFF#Zr)
5927 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5929 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5930 (!cast<Instruction>(NAME#SUFF#Zm)
5931 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5934 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5935 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5936 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5937 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5938 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5941 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5942 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5944 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5946 let Predicates = [HasAVX512] in {
5947 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5948 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5949 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5950 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5951 Requires<[OptForSize]>;
5952 def : Pat<(f32 (X86frcp FR32X:$src)),
5953 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5954 def : Pat<(f32 (X86frcp (load addr:$src))),
5955 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5956 Requires<[OptForSize]>;
5960 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5962 let ExeDomain = _.ExeDomain in {
5963 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5964 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5965 "$src3, $src2, $src1", "$src1, $src2, $src3",
5966 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5967 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5969 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5970 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5971 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5972 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5973 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5976 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5977 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5978 "$src3, $src2, $src1", "$src1, $src2, $src3",
5979 (_.VT (X86RndScales (_.VT _.RC:$src1),
5980 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5981 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5983 let Predicates = [HasAVX512] in {
5984 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5985 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5986 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5987 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5988 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5989 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5990 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5991 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5992 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5993 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5994 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5995 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5996 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5997 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5998 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
6000 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6001 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6002 addr:$src, (i32 0x1))), _.FRC)>;
6003 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6004 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6005 addr:$src, (i32 0x2))), _.FRC)>;
6006 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6007 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6008 addr:$src, (i32 0x3))), _.FRC)>;
6009 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6010 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6011 addr:$src, (i32 0x4))), _.FRC)>;
6012 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6013 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6014 addr:$src, (i32 0xc))), _.FRC)>;
6018 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
6019 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6021 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
6022 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
6024 //-------------------------------------------------
6025 // Integer truncate and extend operations
6026 //-------------------------------------------------
6028 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
6029 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
6030 X86MemOperand x86memop> {
6032 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
6033 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
6034 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
6037 // for intrinsic patter match
6038 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6039 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6041 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6044 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6045 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6046 DestInfo.ImmAllZerosV)),
6047 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6050 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6051 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6052 DestInfo.RC:$src0)),
6053 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
6054 DestInfo.KRCWM:$mask ,
6057 let mayStore = 1 in {
6058 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
6059 (ins x86memop:$dst, SrcInfo.RC:$src),
6060 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6063 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
6064 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
6065 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6070 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
6071 X86VectorVTInfo DestInfo,
6072 PatFrag truncFrag, PatFrag mtruncFrag > {
6074 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
6075 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
6076 addr:$dst, SrcInfo.RC:$src)>;
6078 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
6079 (SrcInfo.VT SrcInfo.RC:$src)),
6080 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
6081 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
6084 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
6085 X86VectorVTInfo DestInfo, string sat > {
6087 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6088 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6089 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
6090 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
6091 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
6092 (SrcInfo.VT SrcInfo.RC:$src))>;
6094 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6095 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6096 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
6097 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
6098 (SrcInfo.VT SrcInfo.RC:$src))>;
6101 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
6102 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6103 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6104 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6105 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
6106 Predicate prd = HasAVX512>{
6108 let Predicates = [HasVLX, prd] in {
6109 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6110 DestInfoZ128, x86memopZ128>,
6111 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6112 truncFrag, mtruncFrag>, EVEX_V128;
6114 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6115 DestInfoZ256, x86memopZ256>,
6116 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6117 truncFrag, mtruncFrag>, EVEX_V256;
6119 let Predicates = [prd] in
6120 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6121 DestInfoZ, x86memopZ>,
6122 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6123 truncFrag, mtruncFrag>, EVEX_V512;
6126 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
6127 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6128 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6129 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6130 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
6132 let Predicates = [HasVLX, prd] in {
6133 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6134 DestInfoZ128, x86memopZ128>,
6135 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6138 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6139 DestInfoZ256, x86memopZ256>,
6140 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6143 let Predicates = [prd] in
6144 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6145 DestInfoZ, x86memopZ>,
6146 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6150 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6151 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6152 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6153 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
6155 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
6156 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
6157 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6158 sat>, EVEX_CD8<8, CD8VO>;
6161 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6162 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6163 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6164 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6166 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6167 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6168 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6169 sat>, EVEX_CD8<16, CD8VQ>;
6172 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6173 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6174 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6175 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6177 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6178 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6179 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6180 sat>, EVEX_CD8<32, CD8VH>;
6183 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6184 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6185 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6186 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6188 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6189 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6190 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6191 sat>, EVEX_CD8<8, CD8VQ>;
6194 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6195 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6196 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6197 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6199 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6200 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6201 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6202 sat>, EVEX_CD8<16, CD8VH>;
6205 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6206 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6207 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6208 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6210 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6211 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6212 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6213 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6216 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6217 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6218 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6220 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6221 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6222 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6224 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6225 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6226 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6228 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6229 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6230 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6232 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6233 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6234 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6236 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6237 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6238 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6240 let Predicates = [HasAVX512, NoVLX] in {
6241 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6242 (v8i16 (EXTRACT_SUBREG
6243 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6244 VR256X:$src, sub_ymm)))), sub_xmm))>;
6245 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6246 (v4i32 (EXTRACT_SUBREG
6247 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6248 VR256X:$src, sub_ymm)))), sub_xmm))>;
6251 let Predicates = [HasBWI, NoVLX] in {
6252 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6253 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6254 VR256X:$src, sub_ymm))), sub_xmm))>;
6257 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6258 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6259 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6261 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6262 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6263 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6266 let mayLoad = 1 in {
6267 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6268 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6269 (DestInfo.VT (LdFrag addr:$src))>,
6274 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6275 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6276 let Predicates = [HasVLX, HasBWI] in {
6277 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6278 v16i8x_info, i64mem, LdFrag, OpNode>,
6279 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6281 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6282 v16i8x_info, i128mem, LdFrag, OpNode>,
6283 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6285 let Predicates = [HasBWI] in {
6286 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6287 v32i8x_info, i256mem, LdFrag, OpNode>,
6288 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6292 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6293 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6294 let Predicates = [HasVLX, HasAVX512] in {
6295 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6296 v16i8x_info, i32mem, LdFrag, OpNode>,
6297 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6299 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6300 v16i8x_info, i64mem, LdFrag, OpNode>,
6301 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6303 let Predicates = [HasAVX512] in {
6304 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6305 v16i8x_info, i128mem, LdFrag, OpNode>,
6306 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6310 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6311 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6312 let Predicates = [HasVLX, HasAVX512] in {
6313 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6314 v16i8x_info, i16mem, LdFrag, OpNode>,
6315 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6317 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6318 v16i8x_info, i32mem, LdFrag, OpNode>,
6319 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6321 let Predicates = [HasAVX512] in {
6322 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6323 v16i8x_info, i64mem, LdFrag, OpNode>,
6324 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6328 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6329 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6330 let Predicates = [HasVLX, HasAVX512] in {
6331 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6332 v8i16x_info, i64mem, LdFrag, OpNode>,
6333 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6335 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6336 v8i16x_info, i128mem, LdFrag, OpNode>,
6337 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6339 let Predicates = [HasAVX512] in {
6340 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6341 v16i16x_info, i256mem, LdFrag, OpNode>,
6342 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6346 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6347 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6348 let Predicates = [HasVLX, HasAVX512] in {
6349 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6350 v8i16x_info, i32mem, LdFrag, OpNode>,
6351 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6353 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6354 v8i16x_info, i64mem, LdFrag, OpNode>,
6355 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6357 let Predicates = [HasAVX512] in {
6358 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6359 v8i16x_info, i128mem, LdFrag, OpNode>,
6360 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6364 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6365 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6367 let Predicates = [HasVLX, HasAVX512] in {
6368 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6369 v4i32x_info, i64mem, LdFrag, OpNode>,
6370 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6372 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6373 v4i32x_info, i128mem, LdFrag, OpNode>,
6374 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6376 let Predicates = [HasAVX512] in {
6377 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6378 v8i32x_info, i256mem, LdFrag, OpNode>,
6379 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6383 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6384 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6385 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6386 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6387 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6388 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6391 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6392 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6393 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6394 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6395 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6396 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6398 //===----------------------------------------------------------------------===//
6399 // GATHER - SCATTER Operations
6401 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6402 X86MemOperand memop, PatFrag GatherNode> {
6403 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6404 ExeDomain = _.ExeDomain in
6405 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6406 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6407 !strconcat(OpcodeStr#_.Suffix,
6408 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6409 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6410 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6411 vectoraddr:$src2))]>, EVEX, EVEX_K,
6412 EVEX_CD8<_.EltSize, CD8VT1>;
6415 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6416 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6417 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6418 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6419 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6420 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6421 let Predicates = [HasVLX] in {
6422 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6423 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6424 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6425 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6426 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6427 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6428 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6429 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6433 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6434 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6435 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6436 mgatherv16i32>, EVEX_V512;
6437 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6438 mgatherv8i64>, EVEX_V512;
6439 let Predicates = [HasVLX] in {
6440 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6441 vy32xmem, mgatherv8i32>, EVEX_V256;
6442 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6443 vy64xmem, mgatherv4i64>, EVEX_V256;
6444 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6445 vx32xmem, mgatherv4i32>, EVEX_V128;
6446 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6447 vx64xmem, mgatherv2i64>, EVEX_V128;
6452 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6453 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6455 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6456 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6458 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6459 X86MemOperand memop, PatFrag ScatterNode> {
6461 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6463 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6464 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6465 !strconcat(OpcodeStr#_.Suffix,
6466 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6467 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6468 _.KRCWM:$mask, vectoraddr:$dst))]>,
6469 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6472 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6473 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6474 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6475 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6476 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6477 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6478 let Predicates = [HasVLX] in {
6479 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6480 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6481 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6482 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6483 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6484 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6485 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6486 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6490 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6491 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6492 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6493 mscatterv16i32>, EVEX_V512;
6494 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6495 mscatterv8i64>, EVEX_V512;
6496 let Predicates = [HasVLX] in {
6497 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6498 vy32xmem, mscatterv8i32>, EVEX_V256;
6499 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6500 vy64xmem, mscatterv4i64>, EVEX_V256;
6501 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6502 vx32xmem, mscatterv4i32>, EVEX_V128;
6503 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6504 vx64xmem, mscatterv2i64>, EVEX_V128;
6508 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6509 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6511 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6512 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6515 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6516 RegisterClass KRC, X86MemOperand memop> {
6517 let Predicates = [HasPFI], hasSideEffects = 1 in
6518 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6519 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6523 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6524 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6526 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6527 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6529 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6530 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6532 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6533 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6535 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6536 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6538 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6539 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6541 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6542 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6544 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6545 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6547 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6548 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6550 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6551 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6553 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6554 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6556 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6557 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6559 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6560 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6562 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6563 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6565 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6566 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6568 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6569 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6571 // Helper fragments to match sext vXi1 to vXiY.
6572 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6573 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6575 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6576 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6577 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6579 def : Pat<(store VK1:$src, addr:$dst),
6581 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6582 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6584 def : Pat<(store VK8:$src, addr:$dst),
6586 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6587 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6589 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6590 (truncstore node:$val, node:$ptr), [{
6591 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6594 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6595 (MOV8mr addr:$dst, GR8:$src)>;
6597 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6598 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6599 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6600 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6603 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6604 string OpcodeStr, Predicate prd> {
6605 let Predicates = [prd] in
6606 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6608 let Predicates = [prd, HasVLX] in {
6609 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6610 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6614 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6615 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6617 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6619 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6621 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6625 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6627 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6628 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6629 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6630 [(set _.KRC:$dst, (X86cvt2mask (_.VT _.RC:$src)))]>, EVEX;
6633 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6634 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6635 let Predicates = [prd] in
6636 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6639 let Predicates = [prd, HasVLX] in {
6640 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6642 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6647 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6648 avx512vl_i8_info, HasBWI>;
6649 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6650 avx512vl_i16_info, HasBWI>, VEX_W;
6651 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6652 avx512vl_i32_info, HasDQI>;
6653 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6654 avx512vl_i64_info, HasDQI>, VEX_W;
6656 //===----------------------------------------------------------------------===//
6657 // AVX-512 - COMPRESS and EXPAND
6660 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6662 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6663 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6664 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6666 let mayStore = 1 in {
6667 def mr : AVX5128I<opc, MRMDestMem, (outs),
6668 (ins _.MemOp:$dst, _.RC:$src),
6669 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6670 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6672 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6673 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6674 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6675 [(store (_.VT (vselect _.KRCWM:$mask,
6676 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6678 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6682 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6683 AVX512VLVectorVTInfo VTInfo> {
6684 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6686 let Predicates = [HasVLX] in {
6687 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6688 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6692 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6694 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6696 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6698 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6702 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6704 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6705 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6706 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6709 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6710 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6711 (_.VT (X86expand (_.VT (bitconvert
6712 (_.LdFrag addr:$src1)))))>,
6713 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6716 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6717 AVX512VLVectorVTInfo VTInfo> {
6718 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6720 let Predicates = [HasVLX] in {
6721 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6722 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6726 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6728 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6730 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6732 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6735 //handle instruction reg_vec1 = op(reg_vec,imm)
6737 // op(broadcast(eltVt),imm)
6738 //all instruction created with FROUND_CURRENT
6739 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6741 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6742 (ins _.RC:$src1, i32u8imm:$src2),
6743 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6744 (OpNode (_.VT _.RC:$src1),
6746 (i32 FROUND_CURRENT))>;
6747 let mayLoad = 1 in {
6748 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6749 (ins _.MemOp:$src1, i32u8imm:$src2),
6750 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6751 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6753 (i32 FROUND_CURRENT))>;
6754 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6755 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6756 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6757 "${src1}"##_.BroadcastStr##", $src2",
6758 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6760 (i32 FROUND_CURRENT))>, EVEX_B;
6764 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6765 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6766 SDNode OpNode, X86VectorVTInfo _>{
6767 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6768 (ins _.RC:$src1, i32u8imm:$src2),
6769 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6770 "$src1, {sae}, $src2",
6771 (OpNode (_.VT _.RC:$src1),
6773 (i32 FROUND_NO_EXC))>, EVEX_B;
6776 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6777 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6778 let Predicates = [prd] in {
6779 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6780 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6783 let Predicates = [prd, HasVLX] in {
6784 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6786 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6791 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6792 // op(reg_vec2,mem_vec,imm)
6793 // op(reg_vec2,broadcast(eltVt),imm)
6794 //all instruction created with FROUND_CURRENT
6795 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6797 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6798 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6799 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6800 (OpNode (_.VT _.RC:$src1),
6803 (i32 FROUND_CURRENT))>;
6804 let mayLoad = 1 in {
6805 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6806 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6807 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6808 (OpNode (_.VT _.RC:$src1),
6809 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6811 (i32 FROUND_CURRENT))>;
6812 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6813 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6814 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6815 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6816 (OpNode (_.VT _.RC:$src1),
6817 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6819 (i32 FROUND_CURRENT))>, EVEX_B;
6823 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6824 // op(reg_vec2,mem_vec,imm)
6825 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6826 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6828 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6829 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6830 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6831 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6832 (SrcInfo.VT SrcInfo.RC:$src2),
6835 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6836 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6837 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6838 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6839 (SrcInfo.VT (bitconvert
6840 (SrcInfo.LdFrag addr:$src2))),
6844 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6845 // op(reg_vec2,mem_vec,imm)
6846 // op(reg_vec2,broadcast(eltVt),imm)
6847 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6849 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6852 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6853 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6854 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6855 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6856 (OpNode (_.VT _.RC:$src1),
6857 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6858 (i8 imm:$src3))>, EVEX_B;
6861 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6862 // op(reg_vec2,mem_scalar,imm)
6863 //all instruction created with FROUND_CURRENT
6864 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6865 X86VectorVTInfo _> {
6867 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6868 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6869 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6870 (OpNode (_.VT _.RC:$src1),
6873 (i32 FROUND_CURRENT))>;
6874 let mayLoad = 1 in {
6875 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6876 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6877 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6878 (OpNode (_.VT _.RC:$src1),
6879 (_.VT (scalar_to_vector
6880 (_.ScalarLdFrag addr:$src2))),
6882 (i32 FROUND_CURRENT))>;
6884 let isAsmParserOnly = 1 in {
6885 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6886 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6887 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6893 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6894 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6895 SDNode OpNode, X86VectorVTInfo _>{
6896 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6897 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6898 OpcodeStr, "$src3,{sae}, $src2, $src1",
6899 "$src1, $src2,{sae}, $src3",
6900 (OpNode (_.VT _.RC:$src1),
6903 (i32 FROUND_NO_EXC))>, EVEX_B;
6905 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6906 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6907 SDNode OpNode, X86VectorVTInfo _> {
6908 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6909 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6910 OpcodeStr, "$src3,{sae}, $src2, $src1",
6911 "$src1, $src2,{sae}, $src3",
6912 (OpNode (_.VT _.RC:$src1),
6915 (i32 FROUND_NO_EXC))>, EVEX_B;
6918 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6919 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6920 let Predicates = [prd] in {
6921 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6922 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6926 let Predicates = [prd, HasVLX] in {
6927 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6929 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6934 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6935 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6936 let Predicates = [HasBWI] in {
6937 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6938 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6940 let Predicates = [HasBWI, HasVLX] in {
6941 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6942 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6943 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6944 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6948 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6949 bits<8> opc, SDNode OpNode>{
6950 let Predicates = [HasAVX512] in {
6951 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6953 let Predicates = [HasAVX512, HasVLX] in {
6954 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6955 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6959 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6960 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6961 let Predicates = [prd] in {
6962 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6963 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6967 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6968 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6969 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6970 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6971 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6972 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6975 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6976 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6977 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6978 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6979 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6980 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6982 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6983 0x55, X86VFixupimm, HasAVX512>,
6984 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6985 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6986 0x55, X86VFixupimm, HasAVX512>,
6987 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6989 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6990 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6991 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6992 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6993 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6994 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6997 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6998 0x50, X86VRange, HasDQI>,
6999 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7000 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
7001 0x50, X86VRange, HasDQI>,
7002 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7004 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
7005 0x51, X86VRange, HasDQI>,
7006 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7007 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
7008 0x51, X86VRange, HasDQI>,
7009 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7011 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
7012 0x57, X86Reduces, HasDQI>,
7013 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7014 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
7015 0x57, X86Reduces, HasDQI>,
7016 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7018 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
7019 0x27, X86GetMants, HasAVX512>,
7020 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7021 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
7022 0x27, X86GetMants, HasAVX512>,
7023 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7025 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
7026 bits<8> opc, SDNode OpNode = X86Shuf128>{
7027 let Predicates = [HasAVX512] in {
7028 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
7031 let Predicates = [HasAVX512, HasVLX] in {
7032 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
7035 let Predicates = [HasAVX512] in {
7036 def : Pat<(v16f32 (ffloor VR512:$src)),
7037 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
7038 def : Pat<(v16f32 (fnearbyint VR512:$src)),
7039 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
7040 def : Pat<(v16f32 (fceil VR512:$src)),
7041 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
7042 def : Pat<(v16f32 (frint VR512:$src)),
7043 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
7044 def : Pat<(v16f32 (ftrunc VR512:$src)),
7045 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
7047 def : Pat<(v8f64 (ffloor VR512:$src)),
7048 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
7049 def : Pat<(v8f64 (fnearbyint VR512:$src)),
7050 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
7051 def : Pat<(v8f64 (fceil VR512:$src)),
7052 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
7053 def : Pat<(v8f64 (frint VR512:$src)),
7054 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
7055 def : Pat<(v8f64 (ftrunc VR512:$src)),
7056 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
7059 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
7060 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7061 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
7062 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7063 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
7064 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7065 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
7066 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7068 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I> {
7069 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
7070 AVX512AIi8Base, EVEX_4V;
7073 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info>,
7074 EVEX_CD8<32, CD8VF>;
7075 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info>,
7076 EVEX_CD8<64, CD8VF>, VEX_W;
7078 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
7079 let Predicates = p in
7080 def NAME#_.VTName#rri:
7081 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
7082 (!cast<Instruction>(NAME#_.ZSuffix#rri)
7083 _.RC:$src1, _.RC:$src2, imm:$imm)>;
7086 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
7087 avx512_vpalign_lowering<_.info512, [HasBWI]>,
7088 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
7089 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
7091 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
7092 avx512vl_i8_info, avx512vl_i8_info>,
7093 avx512_vpalign_lowering_common<avx512vl_i16_info>,
7094 avx512_vpalign_lowering_common<avx512vl_i32_info>,
7095 avx512_vpalign_lowering_common<avx512vl_f32_info>,
7096 avx512_vpalign_lowering_common<avx512vl_i64_info>,
7097 avx512_vpalign_lowering_common<avx512vl_f64_info>,
7100 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
7101 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
7103 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7104 X86VectorVTInfo _> {
7105 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7106 (ins _.RC:$src1), OpcodeStr,
7108 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
7111 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7112 (ins _.MemOp:$src1), OpcodeStr,
7114 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
7115 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
7118 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7119 X86VectorVTInfo _> :
7120 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
7122 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7123 (ins _.ScalarMemOp:$src1), OpcodeStr,
7124 "${src1}"##_.BroadcastStr,
7125 "${src1}"##_.BroadcastStr,
7126 (_.VT (OpNode (X86VBroadcast
7127 (_.ScalarLdFrag addr:$src1))))>,
7128 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
7131 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7132 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7133 let Predicates = [prd] in
7134 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7136 let Predicates = [prd, HasVLX] in {
7137 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7139 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
7144 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7145 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7146 let Predicates = [prd] in
7147 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
7150 let Predicates = [prd, HasVLX] in {
7151 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
7153 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7158 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7159 SDNode OpNode, Predicate prd> {
7160 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
7162 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
7166 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7167 SDNode OpNode, Predicate prd> {
7168 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
7169 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
7172 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7173 bits<8> opc_d, bits<8> opc_q,
7174 string OpcodeStr, SDNode OpNode> {
7175 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7177 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7181 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7184 (bc_v16i32 (v16i1sextv16i32)),
7185 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7186 (VPABSDZrr VR512:$src)>;
7188 (bc_v8i64 (v8i1sextv8i64)),
7189 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7190 (VPABSQZrr VR512:$src)>;
7192 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7194 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7197 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7198 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7200 //===---------------------------------------------------------------------===//
7201 // Replicate Single FP - MOVSHDUP and MOVSLDUP
7202 //===---------------------------------------------------------------------===//
7203 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7204 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
7208 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
7209 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
7211 //===----------------------------------------------------------------------===//
7212 // AVX-512 - MOVDDUP
7213 //===----------------------------------------------------------------------===//
7215 multiclass avx512_movddup_128<bits<8> opc, string OpcodeStr, SDNode OpNode,
7216 X86VectorVTInfo _> {
7217 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7218 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7219 (_.VT (OpNode (_.VT _.RC:$src)))>, EVEX;
7221 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7222 (ins _.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
7223 (_.VT (OpNode (_.VT (scalar_to_vector
7224 (_.ScalarLdFrag addr:$src)))))>,
7225 EVEX, EVEX_CD8<_.EltSize, CD8VH>;
7228 multiclass avx512_movddup_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
7229 AVX512VLVectorVTInfo VTInfo> {
7231 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7233 let Predicates = [HasAVX512, HasVLX] in {
7234 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7236 defm Z128 : avx512_movddup_128<opc, OpcodeStr, OpNode, VTInfo.info128>,
7241 multiclass avx512_movddup<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7242 defm NAME: avx512_movddup_common<opc, OpcodeStr, OpNode,
7243 avx512vl_f64_info>, XD, VEX_W;
7246 defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup>;
7248 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
7249 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7250 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
7251 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7253 //===----------------------------------------------------------------------===//
7254 // AVX-512 - Unpack Instructions
7255 //===----------------------------------------------------------------------===//
7256 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
7257 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
7259 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7260 SSE_INTALU_ITINS_P, HasBWI>;
7261 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7262 SSE_INTALU_ITINS_P, HasBWI>;
7263 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7264 SSE_INTALU_ITINS_P, HasBWI>;
7265 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7266 SSE_INTALU_ITINS_P, HasBWI>;
7268 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7269 SSE_INTALU_ITINS_P, HasAVX512>;
7270 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7271 SSE_INTALU_ITINS_P, HasAVX512>;
7272 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7273 SSE_INTALU_ITINS_P, HasAVX512>;
7274 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7275 SSE_INTALU_ITINS_P, HasAVX512>;
7277 //===----------------------------------------------------------------------===//
7278 // AVX-512 - Extract & Insert Integer Instructions
7279 //===----------------------------------------------------------------------===//
7281 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7282 X86VectorVTInfo _> {
7284 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7285 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7286 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7287 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7290 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7293 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7294 let Predicates = [HasBWI] in {
7295 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7296 (ins _.RC:$src1, u8imm:$src2),
7297 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7298 [(set GR32orGR64:$dst,
7299 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7302 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7306 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7307 let Predicates = [HasBWI] in {
7308 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7309 (ins _.RC:$src1, u8imm:$src2),
7310 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7311 [(set GR32orGR64:$dst,
7312 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7315 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
7316 (ins _.RC:$src1, u8imm:$src2),
7317 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7320 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7324 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7325 RegisterClass GRC> {
7326 let Predicates = [HasDQI] in {
7327 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7328 (ins _.RC:$src1, u8imm:$src2),
7329 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7331 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7335 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7336 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7337 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7338 [(store (extractelt (_.VT _.RC:$src1),
7339 imm:$src2),addr:$dst)]>,
7340 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7344 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7345 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7346 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7347 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7349 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7350 X86VectorVTInfo _, PatFrag LdFrag> {
7351 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7352 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7353 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7355 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7356 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7359 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7360 X86VectorVTInfo _, PatFrag LdFrag> {
7361 let Predicates = [HasBWI] in {
7362 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7363 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7364 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7366 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7368 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7372 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7373 X86VectorVTInfo _, RegisterClass GRC> {
7374 let Predicates = [HasDQI] in {
7375 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7376 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7377 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7379 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7382 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7383 _.ScalarLdFrag>, TAPD;
7387 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7389 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7391 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7392 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7393 //===----------------------------------------------------------------------===//
7394 // VSHUFPS - VSHUFPD Operations
7395 //===----------------------------------------------------------------------===//
7396 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7397 AVX512VLVectorVTInfo VTInfo_FP>{
7398 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7399 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7400 AVX512AIi8Base, EVEX_4V;
7403 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7404 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7405 //===----------------------------------------------------------------------===//
7406 // AVX-512 - Byte shift Left/Right
7407 //===----------------------------------------------------------------------===//
7409 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7410 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7411 def rr : AVX512<opc, MRMr,
7412 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7414 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7416 def rm : AVX512<opc, MRMm,
7417 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7418 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7419 [(set _.RC:$dst,(_.VT (OpNode
7420 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7423 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7424 Format MRMm, string OpcodeStr, Predicate prd>{
7425 let Predicates = [prd] in
7426 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7427 OpcodeStr, v8i64_info>, EVEX_V512;
7428 let Predicates = [prd, HasVLX] in {
7429 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7430 OpcodeStr, v4i64x_info>, EVEX_V256;
7431 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7432 OpcodeStr, v2i64x_info>, EVEX_V128;
7435 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7436 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7437 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7438 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7441 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7442 string OpcodeStr, X86VectorVTInfo _dst,
7443 X86VectorVTInfo _src>{
7444 def rr : AVX512BI<opc, MRMSrcReg,
7445 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7446 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7447 [(set _dst.RC:$dst,(_dst.VT
7448 (OpNode (_src.VT _src.RC:$src1),
7449 (_src.VT _src.RC:$src2))))]>;
7451 def rm : AVX512BI<opc, MRMSrcMem,
7452 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7453 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7454 [(set _dst.RC:$dst,(_dst.VT
7455 (OpNode (_src.VT _src.RC:$src1),
7456 (_src.VT (bitconvert
7457 (_src.LdFrag addr:$src2))))))]>;
7460 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7461 string OpcodeStr, Predicate prd> {
7462 let Predicates = [prd] in
7463 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v8i64_info,
7464 v64i8_info>, EVEX_V512;
7465 let Predicates = [prd, HasVLX] in {
7466 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v4i64x_info,
7467 v32i8x_info>, EVEX_V256;
7468 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v2i64x_info,
7469 v16i8x_info>, EVEX_V128;
7473 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7476 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7478 let Constraints = "$src1 = $dst" in {
7479 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7480 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7481 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7482 (OpNode (_.VT _.RC:$src1),
7485 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7486 let mayLoad = 1 in {
7487 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7488 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7489 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7490 (OpNode (_.VT _.RC:$src1),
7492 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7494 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7495 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7496 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7497 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7498 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7499 (OpNode (_.VT _.RC:$src1),
7501 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7502 (i8 imm:$src4))>, EVEX_B,
7503 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7505 }// Constraints = "$src1 = $dst"
7508 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7509 let Predicates = [HasAVX512] in
7510 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7511 let Predicates = [HasAVX512, HasVLX] in {
7512 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7513 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7517 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7518 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;