1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
26 string VTName = "v" # NumElts # EltVT;
29 ValueType VT = !cast<ValueType>(VTName);
31 string EltTypeName = !cast<string>(EltVT);
32 // Size of the element type in bits, e.g. 32 for v16i32.
33 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
34 int EltSize = EltVT.Size;
36 // "i" for integer types and "f" for floating-point types
37 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
39 // Size of RC in bits, e.g. 512 for VR512.
42 // The corresponding memory operand, e.g. i512mem for VR512.
43 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
44 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
47 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
48 // due to load promotion during legalization
49 PatFrag LdFrag = !cast<PatFrag>("load" #
50 !if (!eq (TypeVariantName, "i"),
51 !if (!eq (Size, 128), "v2i64",
52 !if (!eq (Size, 256), "v4i64",
54 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
56 // Load patterns used for memory operands. We only have this defined in
57 // case of i64 element types for sub-512 integer vectors. For now, keep
58 // MemOpFrag undefined in these cases.
60 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
62 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
64 // The corresponding float type, e.g. v16f32 for v16i32
65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
89 // A vector type of the same width with element type i32. This is used to
90 // create the canonical constant zero node ImmAllZerosV.
91 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
92 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
95 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
96 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
97 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
98 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
99 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
100 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
102 // "x" in v32i8x_info means RC = VR256X
103 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
104 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
105 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
106 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
107 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
108 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
110 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
111 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
112 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
113 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
114 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
115 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
117 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
118 X86VectorVTInfo i128> {
119 X86VectorVTInfo info512 = i512;
120 X86VectorVTInfo info256 = i256;
121 X86VectorVTInfo info128 = i128;
124 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
126 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
128 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
130 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
132 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
134 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
137 // This multiclass generates the masking variants from the non-masking
138 // variant. It only provides the assembly pieces for the masking variants.
139 // It assumes custom ISel patterns for masking which can be provided as
140 // template arguments.
141 multiclass AVX512_maskable_custom<bits<8> O, Format F,
143 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
145 string AttSrcAsm, string IntelSrcAsm,
147 list<dag> MaskingPattern,
148 list<dag> ZeroMaskingPattern,
150 string MaskingConstraint = "",
151 InstrItinClass itin = NoItinerary,
152 bit IsCommutable = 0> {
153 let isCommutable = IsCommutable in
154 def NAME: AVX512<O, F, Outs, Ins,
155 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
156 "$dst "#Round#", "#IntelSrcAsm#"}",
159 // Prefer over VMOV*rrk Pat<>
160 let AddedComplexity = 20 in
161 def NAME#k: AVX512<O, F, Outs, MaskingIns,
162 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
163 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
164 MaskingPattern, itin>,
166 // In case of the 3src subclass this is overridden with a let.
167 string Constraints = MaskingConstraint;
169 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
170 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
171 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
172 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
179 // Common base class of AVX512_maskable and AVX512_maskable_3src.
180 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
182 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
184 string AttSrcAsm, string IntelSrcAsm,
185 dag RHS, dag MaskingRHS,
187 string MaskingConstraint = "",
188 InstrItinClass itin = NoItinerary,
189 bit IsCommutable = 0> :
190 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
191 AttSrcAsm, IntelSrcAsm,
192 [(set _.RC:$dst, RHS)],
193 [(set _.RC:$dst, MaskingRHS)],
195 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
196 Round, MaskingConstraint, NoItinerary, IsCommutable>;
198 // This multiclass generates the unconditional/non-masking, the masking and
199 // the zero-masking variant of the instruction. In the masking case, the
200 // perserved vector elements come from a new dummy input operand tied to $dst.
201 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
202 dag Outs, dag Ins, string OpcodeStr,
203 string AttSrcAsm, string IntelSrcAsm,
204 dag RHS, string Round = "",
205 InstrItinClass itin = NoItinerary,
206 bit IsCommutable = 0> :
207 AVX512_maskable_common<O, F, _, Outs, Ins,
208 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
209 !con((ins _.KRCWM:$mask), Ins),
210 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
211 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), Round,
212 "$src0 = $dst", itin, IsCommutable>;
214 // Similar to AVX512_maskable but in this case one of the source operands
215 // ($src1) is already tied to $dst so we just use that for the preserved
216 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
218 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
219 dag Outs, dag NonTiedIns, string OpcodeStr,
220 string AttSrcAsm, string IntelSrcAsm,
222 AVX512_maskable_common<O, F, _, Outs,
223 !con((ins _.RC:$src1), NonTiedIns),
224 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
225 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
226 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
227 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
230 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
233 string AttSrcAsm, string IntelSrcAsm,
235 AVX512_maskable_custom<O, F, Outs, Ins,
236 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
237 !con((ins _.KRCWM:$mask), Ins),
238 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
241 // Bitcasts between 512-bit vector types. Return the original type since
242 // no instruction is needed for the conversion
243 let Predicates = [HasAVX512] in {
244 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
245 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
246 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
247 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
248 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
249 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
250 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
251 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
252 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
253 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
254 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
255 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
256 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
257 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
258 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
259 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
260 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
261 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
262 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
263 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
264 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
265 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
266 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
267 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
268 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
269 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
270 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
271 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
272 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
273 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
274 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
276 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
277 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
278 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
279 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
280 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
281 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
282 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
283 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
284 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
285 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
286 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
287 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
288 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
289 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
290 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
291 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
292 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
293 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
294 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
295 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
296 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
297 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
298 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
299 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
300 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
301 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
302 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
303 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
304 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
305 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
307 // Bitcasts between 256-bit vector types. Return the original type since
308 // no instruction is needed for the conversion
309 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
310 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
311 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
312 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
313 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
314 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
315 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
316 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
317 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
318 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
319 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
320 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
321 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
322 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
323 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
324 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
325 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
326 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
327 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
328 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
329 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
330 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
331 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
332 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
333 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
334 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
335 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
336 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
337 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
338 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
342 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
345 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
346 isPseudo = 1, Predicates = [HasAVX512] in {
347 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
348 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
351 let Predicates = [HasAVX512] in {
352 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
353 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
354 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
357 //===----------------------------------------------------------------------===//
358 // AVX-512 - VECTOR INSERT
361 multiclass vinsert_for_size_no_alt<int Opcode,
362 X86VectorVTInfo From, X86VectorVTInfo To,
363 PatFrag vinsert_insert,
364 SDNodeXForm INSERT_get_vinsert_imm> {
365 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
366 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
367 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
368 "vinsert" # From.EltTypeName # "x" # From.NumElts #
369 "\t{$src3, $src2, $src1, $dst|"
370 "$dst, $src1, $src2, $src3}",
371 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
372 (From.VT From.RC:$src2),
377 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
378 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
379 "vinsert" # From.EltTypeName # "x" # From.NumElts #
380 "\t{$src3, $src2, $src1, $dst|"
381 "$dst, $src1, $src2, $src3}",
383 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
387 multiclass vinsert_for_size<int Opcode,
388 X86VectorVTInfo From, X86VectorVTInfo To,
389 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
390 PatFrag vinsert_insert,
391 SDNodeXForm INSERT_get_vinsert_imm> :
392 vinsert_for_size_no_alt<Opcode, From, To,
393 vinsert_insert, INSERT_get_vinsert_imm> {
394 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
395 // vinserti32x4. Only add this if 64x2 and friends are not supported
396 // natively via AVX512DQ.
397 let Predicates = [NoDQI] in
398 def : Pat<(vinsert_insert:$ins
399 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
400 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
401 VR512:$src1, From.RC:$src2,
402 (INSERT_get_vinsert_imm VR512:$ins)))>;
405 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
406 ValueType EltVT64, int Opcode256> {
407 defm NAME # "32x4" : vinsert_for_size<Opcode128,
408 X86VectorVTInfo< 4, EltVT32, VR128X>,
409 X86VectorVTInfo<16, EltVT32, VR512>,
410 X86VectorVTInfo< 2, EltVT64, VR128X>,
411 X86VectorVTInfo< 8, EltVT64, VR512>,
413 INSERT_get_vinsert128_imm>;
414 let Predicates = [HasDQI] in
415 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
416 X86VectorVTInfo< 2, EltVT64, VR128X>,
417 X86VectorVTInfo< 8, EltVT64, VR512>,
419 INSERT_get_vinsert128_imm>, VEX_W;
420 defm NAME # "64x4" : vinsert_for_size<Opcode256,
421 X86VectorVTInfo< 4, EltVT64, VR256X>,
422 X86VectorVTInfo< 8, EltVT64, VR512>,
423 X86VectorVTInfo< 8, EltVT32, VR256>,
424 X86VectorVTInfo<16, EltVT32, VR512>,
426 INSERT_get_vinsert256_imm>, VEX_W;
427 let Predicates = [HasDQI] in
428 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
429 X86VectorVTInfo< 8, EltVT32, VR256X>,
430 X86VectorVTInfo<16, EltVT32, VR512>,
432 INSERT_get_vinsert256_imm>;
435 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
436 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
438 // vinsertps - insert f32 to XMM
439 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
440 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
441 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
442 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
444 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
445 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
446 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
447 [(set VR128X:$dst, (X86insertps VR128X:$src1,
448 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
449 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
451 //===----------------------------------------------------------------------===//
452 // AVX-512 VECTOR EXTRACT
455 multiclass vextract_for_size<int Opcode,
456 X86VectorVTInfo From, X86VectorVTInfo To,
457 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
458 PatFrag vextract_extract,
459 SDNodeXForm EXTRACT_get_vextract_imm> {
460 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
461 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
462 (ins VR512:$src1, i8imm:$idx),
463 "vextract" # To.EltTypeName # "x4",
464 "$idx, $src1", "$src1, $idx",
465 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
467 AVX512AIi8Base, EVEX, EVEX_V512;
469 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
470 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
471 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
472 "$dst, $src1, $src2}",
473 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
476 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
478 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
479 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
481 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
483 // A 128/256-bit subvector extract from the first 512-bit vector position is
484 // a subregister copy that needs no instruction.
485 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
487 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
489 // And for the alternative types.
490 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
492 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
494 // Intrinsic call with masking.
495 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
497 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
498 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
499 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
500 VR512:$src1, imm:$idx)>;
502 // Intrinsic call with zero-masking.
503 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
505 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
506 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
507 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
508 VR512:$src1, imm:$idx)>;
510 // Intrinsic call without masking.
511 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
513 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
514 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
515 VR512:$src1, imm:$idx)>;
518 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
519 ValueType EltVT64, int Opcode64> {
520 defm NAME # "32x4" : vextract_for_size<Opcode32,
521 X86VectorVTInfo<16, EltVT32, VR512>,
522 X86VectorVTInfo< 4, EltVT32, VR128X>,
523 X86VectorVTInfo< 8, EltVT64, VR512>,
524 X86VectorVTInfo< 2, EltVT64, VR128X>,
526 EXTRACT_get_vextract128_imm>;
527 defm NAME # "64x4" : vextract_for_size<Opcode64,
528 X86VectorVTInfo< 8, EltVT64, VR512>,
529 X86VectorVTInfo< 4, EltVT64, VR256X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 X86VectorVTInfo< 8, EltVT32, VR256>,
533 EXTRACT_get_vextract256_imm>, VEX_W;
536 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
537 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
539 // A 128-bit subvector insert to the first 512-bit vector position
540 // is a subregister copy that needs no instruction.
541 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
542 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
543 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
545 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
546 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
547 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
549 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
550 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
551 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
553 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
554 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
555 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
558 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
559 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
560 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
561 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
562 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
563 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
564 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
565 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
567 // vextractps - extract 32 bits from XMM
568 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
569 (ins VR128X:$src1, i32i8imm:$src2),
570 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
571 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
574 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
575 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
576 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
577 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
578 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
580 //===---------------------------------------------------------------------===//
583 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
584 ValueType svt, X86VectorVTInfo _> {
585 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
586 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
587 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
591 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
592 (ins _.ScalarMemOp:$src),
593 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
594 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
599 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
600 AVX512VLVectorVTInfo _> {
601 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
604 let Predicates = [HasVLX] in {
605 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
610 let ExeDomain = SSEPackedSingle in {
611 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
612 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
613 let Predicates = [HasVLX] in {
614 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
615 v4f32, v4f32x_info>, EVEX_V128,
616 EVEX_CD8<32, CD8VT1>;
620 let ExeDomain = SSEPackedDouble in {
621 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
622 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
625 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
626 (VBROADCASTSSZm addr:$src)>;
627 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
628 (VBROADCASTSDZm addr:$src)>;
630 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
631 (VBROADCASTSSZm addr:$src)>;
632 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
633 (VBROADCASTSDZm addr:$src)>;
635 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
636 RegisterClass SrcRC, RegisterClass KRC> {
637 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
638 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
639 []>, EVEX, EVEX_V512;
640 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
641 (ins KRC:$mask, SrcRC:$src),
642 !strconcat(OpcodeStr,
643 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
644 []>, EVEX, EVEX_V512, EVEX_KZ;
647 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
648 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
651 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
652 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
654 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
655 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
657 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
658 (VPBROADCASTDrZrr GR32:$src)>;
659 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
660 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
661 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
662 (VPBROADCASTQrZrr GR64:$src)>;
663 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
664 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
666 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
667 (VPBROADCASTDrZrr GR32:$src)>;
668 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
669 (VPBROADCASTQrZrr GR64:$src)>;
671 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
672 (v16i32 immAllZerosV), (i16 GR16:$mask))),
673 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
674 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
675 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
676 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
678 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
679 X86MemOperand x86memop, PatFrag ld_frag,
680 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
682 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
683 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
685 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
686 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
688 !strconcat(OpcodeStr,
689 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
691 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
694 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
695 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
697 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
698 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
700 !strconcat(OpcodeStr,
701 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
702 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
703 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
707 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
708 loadi32, VR512, v16i32, v4i32, VK16WM>,
709 EVEX_V512, EVEX_CD8<32, CD8VT1>;
710 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
711 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
712 EVEX_CD8<64, CD8VT1>;
714 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
715 X86MemOperand x86memop, PatFrag ld_frag,
718 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
719 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
721 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
723 !strconcat(OpcodeStr,
724 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
729 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
730 i128mem, loadv2i64, VK16WM>,
731 EVEX_V512, EVEX_CD8<32, CD8VT4>;
732 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
733 i256mem, loadv4i64, VK16WM>, VEX_W,
734 EVEX_V512, EVEX_CD8<64, CD8VT4>;
736 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
737 (VPBROADCASTDZrr VR128X:$src)>;
738 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
739 (VPBROADCASTQZrr VR128X:$src)>;
741 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
742 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
743 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
744 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
746 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
747 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
748 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
749 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
751 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
752 (VBROADCASTSSZr VR128X:$src)>;
753 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
754 (VBROADCASTSDZr VR128X:$src)>;
756 // Provide fallback in case the load node that is used in the patterns above
757 // is used by additional users, which prevents the pattern selection.
758 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
759 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
760 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
761 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
764 let Predicates = [HasAVX512] in {
765 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
767 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
768 addr:$src)), sub_ymm)>;
770 //===----------------------------------------------------------------------===//
771 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
774 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
776 let Predicates = [HasCDI] in
777 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
778 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
779 []>, EVEX, EVEX_V512;
781 let Predicates = [HasCDI, HasVLX] in {
782 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
783 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
784 []>, EVEX, EVEX_V128;
785 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
786 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
787 []>, EVEX, EVEX_V256;
791 let Predicates = [HasCDI] in {
792 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
794 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
798 //===----------------------------------------------------------------------===//
801 // -- immediate form --
802 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
804 let ExeDomain = _.ExeDomain in {
805 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
806 (ins _.RC:$src1, i8imm:$src2),
807 !strconcat(OpcodeStr,
808 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
810 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
812 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
813 (ins _.MemOp:$src1, i8imm:$src2),
814 !strconcat(OpcodeStr,
815 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
817 (_.VT (OpNode (_.MemOpFrag addr:$src1),
819 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
823 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
824 X86VectorVTInfo Ctrl> :
825 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
826 let ExeDomain = _.ExeDomain in {
827 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
828 (ins _.RC:$src1, _.RC:$src2),
829 !strconcat("vpermil" # _.Suffix,
830 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
832 (_.VT (X86VPermilpv _.RC:$src1,
833 (Ctrl.VT Ctrl.RC:$src2))))]>,
835 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
836 (ins _.RC:$src1, Ctrl.MemOp:$src2),
837 !strconcat("vpermil" # _.Suffix,
838 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
840 (_.VT (X86VPermilpv _.RC:$src1,
841 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
846 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
848 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
851 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
853 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
856 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
857 (VPERMILPSZri VR512:$src1, imm:$imm)>;
858 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
859 (VPERMILPDZri VR512:$src1, imm:$imm)>;
861 // -- VPERM - register form --
862 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
863 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
865 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
866 (ins RC:$src1, RC:$src2),
867 !strconcat(OpcodeStr,
868 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
870 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
872 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
873 (ins RC:$src1, x86memop:$src2),
874 !strconcat(OpcodeStr,
875 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
877 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
881 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
882 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
883 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
884 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
885 let ExeDomain = SSEPackedSingle in
886 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
887 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
888 let ExeDomain = SSEPackedDouble in
889 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
890 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
892 // -- VPERM2I - 3 source operands form --
893 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
894 PatFrag mem_frag, X86MemOperand x86memop,
895 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
896 let Constraints = "$src1 = $dst" in {
897 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
898 (ins RC:$src1, RC:$src2, RC:$src3),
899 !strconcat(OpcodeStr,
900 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
902 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
905 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
906 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
907 !strconcat(OpcodeStr,
908 " \t{$src3, $src2, $dst {${mask}}|"
909 "$dst {${mask}}, $src2, $src3}"),
910 [(set RC:$dst, (OpVT (vselect KRC:$mask,
911 (OpNode RC:$src1, RC:$src2,
916 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
917 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
918 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
919 !strconcat(OpcodeStr,
920 " \t{$src3, $src2, $dst {${mask}} {z} |",
921 "$dst {${mask}} {z}, $src2, $src3}"),
922 [(set RC:$dst, (OpVT (vselect KRC:$mask,
923 (OpNode RC:$src1, RC:$src2,
926 (v16i32 immAllZerosV))))))]>,
929 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
930 (ins RC:$src1, RC:$src2, x86memop:$src3),
931 !strconcat(OpcodeStr,
932 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
934 (OpVT (OpNode RC:$src1, RC:$src2,
935 (mem_frag addr:$src3))))]>, EVEX_4V;
937 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
938 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
939 !strconcat(OpcodeStr,
940 " \t{$src3, $src2, $dst {${mask}}|"
941 "$dst {${mask}}, $src2, $src3}"),
943 (OpVT (vselect KRC:$mask,
944 (OpNode RC:$src1, RC:$src2,
945 (mem_frag addr:$src3)),
949 let AddedComplexity = 10 in // Prefer over the rrkz variant
950 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
951 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
952 !strconcat(OpcodeStr,
953 " \t{$src3, $src2, $dst {${mask}} {z}|"
954 "$dst {${mask}} {z}, $src2, $src3}"),
956 (OpVT (vselect KRC:$mask,
957 (OpNode RC:$src1, RC:$src2,
958 (mem_frag addr:$src3)),
960 (v16i32 immAllZerosV))))))]>,
964 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
965 i512mem, X86VPermiv3, v16i32, VK16WM>,
966 EVEX_V512, EVEX_CD8<32, CD8VF>;
967 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
968 i512mem, X86VPermiv3, v8i64, VK8WM>,
969 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
970 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
971 i512mem, X86VPermiv3, v16f32, VK16WM>,
972 EVEX_V512, EVEX_CD8<32, CD8VF>;
973 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
974 i512mem, X86VPermiv3, v8f64, VK8WM>,
975 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
977 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
978 PatFrag mem_frag, X86MemOperand x86memop,
979 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
980 ValueType MaskVT, RegisterClass MRC> :
981 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
983 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
984 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
985 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
987 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
988 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
989 (!cast<Instruction>(NAME#rrk) VR512:$src1,
990 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
993 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
994 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
995 EVEX_V512, EVEX_CD8<32, CD8VF>;
996 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
997 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
998 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
999 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1000 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1001 EVEX_V512, EVEX_CD8<32, CD8VF>;
1002 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1003 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1004 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1006 //===----------------------------------------------------------------------===//
1007 // AVX-512 - BLEND using mask
1009 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
1010 RegisterClass KRC, RegisterClass RC,
1011 X86MemOperand x86memop, PatFrag mem_frag,
1012 SDNode OpNode, ValueType vt> {
1013 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1014 (ins KRC:$mask, RC:$src1, RC:$src2),
1015 !strconcat(OpcodeStr,
1016 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1017 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
1018 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
1020 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1021 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1022 !strconcat(OpcodeStr,
1023 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1024 []>, EVEX_4V, EVEX_K;
1027 let ExeDomain = SSEPackedSingle in
1028 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1029 VK16WM, VR512, f512mem,
1030 memopv16f32, vselect, v16f32>,
1031 EVEX_CD8<32, CD8VF>, EVEX_V512;
1032 let ExeDomain = SSEPackedDouble in
1033 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1034 VK8WM, VR512, f512mem,
1035 memopv8f64, vselect, v8f64>,
1036 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1038 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1039 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1040 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1041 VR512:$src1, VR512:$src2)>;
1043 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1044 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1045 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1046 VR512:$src1, VR512:$src2)>;
1048 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1049 VK16WM, VR512, f512mem,
1050 memopv16i32, vselect, v16i32>,
1051 EVEX_CD8<32, CD8VF>, EVEX_V512;
1053 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1054 VK8WM, VR512, f512mem,
1055 memopv8i64, vselect, v8i64>,
1056 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1058 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1059 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1060 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1061 VR512:$src1, VR512:$src2)>;
1063 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1064 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1065 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1066 VR512:$src1, VR512:$src2)>;
1068 let Predicates = [HasAVX512] in {
1069 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1070 (v8f32 VR256X:$src2))),
1072 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1073 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1074 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1076 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1077 (v8i32 VR256X:$src2))),
1079 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1080 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1081 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1083 //===----------------------------------------------------------------------===//
1084 // Compare Instructions
1085 //===----------------------------------------------------------------------===//
1087 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1088 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1089 Operand CC, SDNode OpNode, ValueType VT,
1090 PatFrag ld_frag, string asm, string asm_alt> {
1091 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1092 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1093 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1094 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1095 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1096 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1097 [(set VK1:$dst, (OpNode (VT RC:$src1),
1098 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1099 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1100 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1101 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1102 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1103 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1104 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1105 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1109 let Predicates = [HasAVX512] in {
1110 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1111 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1112 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1114 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1115 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1116 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1120 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1121 X86VectorVTInfo _> {
1122 def rr : AVX512BI<opc, MRMSrcReg,
1123 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1124 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1125 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1126 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1128 def rm : AVX512BI<opc, MRMSrcMem,
1129 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1130 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1131 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1132 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1133 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1134 def rrk : AVX512BI<opc, MRMSrcReg,
1135 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1136 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1137 "$dst {${mask}}, $src1, $src2}"),
1138 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1139 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1140 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1142 def rmk : AVX512BI<opc, MRMSrcMem,
1143 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1144 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1145 "$dst {${mask}}, $src1, $src2}"),
1146 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1147 (OpNode (_.VT _.RC:$src1),
1149 (_.LdFrag addr:$src2))))))],
1150 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1153 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1154 X86VectorVTInfo _> :
1155 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1156 let mayLoad = 1 in {
1157 def rmb : AVX512BI<opc, MRMSrcMem,
1158 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1159 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1160 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1161 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1162 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1163 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1164 def rmbk : AVX512BI<opc, MRMSrcMem,
1165 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1166 _.ScalarMemOp:$src2),
1167 !strconcat(OpcodeStr,
1168 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1169 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1170 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1171 (OpNode (_.VT _.RC:$src1),
1173 (_.ScalarLdFrag addr:$src2)))))],
1174 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1178 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1179 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1180 let Predicates = [prd] in
1181 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1184 let Predicates = [prd, HasVLX] in {
1185 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1187 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1192 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1193 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1195 let Predicates = [prd] in
1196 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1199 let Predicates = [prd, HasVLX] in {
1200 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1202 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1207 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1208 avx512vl_i8_info, HasBWI>,
1211 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1212 avx512vl_i16_info, HasBWI>,
1213 EVEX_CD8<16, CD8VF>;
1215 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1216 avx512vl_i32_info, HasAVX512>,
1217 EVEX_CD8<32, CD8VF>;
1219 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1220 avx512vl_i64_info, HasAVX512>,
1221 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1223 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1224 avx512vl_i8_info, HasBWI>,
1227 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1228 avx512vl_i16_info, HasBWI>,
1229 EVEX_CD8<16, CD8VF>;
1231 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1232 avx512vl_i32_info, HasAVX512>,
1233 EVEX_CD8<32, CD8VF>;
1235 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1236 avx512vl_i64_info, HasAVX512>,
1237 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1239 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1240 (COPY_TO_REGCLASS (VPCMPGTDZrr
1241 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1242 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1244 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1245 (COPY_TO_REGCLASS (VPCMPEQDZrr
1246 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1247 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1249 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1250 X86VectorVTInfo _> {
1251 def rri : AVX512AIi8<opc, MRMSrcReg,
1252 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1253 !strconcat("vpcmp${cc}", Suffix,
1254 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1255 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1257 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1259 def rmi : AVX512AIi8<opc, MRMSrcMem,
1260 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1261 !strconcat("vpcmp${cc}", Suffix,
1262 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1263 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1264 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1266 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1267 def rrik : AVX512AIi8<opc, MRMSrcReg,
1268 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1270 !strconcat("vpcmp${cc}", Suffix,
1271 "\t{$src2, $src1, $dst {${mask}}|",
1272 "$dst {${mask}}, $src1, $src2}"),
1273 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1274 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1276 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1278 def rmik : AVX512AIi8<opc, MRMSrcMem,
1279 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1281 !strconcat("vpcmp${cc}", Suffix,
1282 "\t{$src2, $src1, $dst {${mask}}|",
1283 "$dst {${mask}}, $src1, $src2}"),
1284 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1285 (OpNode (_.VT _.RC:$src1),
1286 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1288 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1290 // Accept explicit immediate argument form instead of comparison code.
1291 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1292 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1293 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1294 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1295 "$dst, $src1, $src2, $cc}"),
1296 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1297 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1298 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1299 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1300 "$dst, $src1, $src2, $cc}"),
1301 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1302 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1303 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1305 !strconcat("vpcmp", Suffix,
1306 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1307 "$dst {${mask}}, $src1, $src2, $cc}"),
1308 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1309 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1310 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1312 !strconcat("vpcmp", Suffix,
1313 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1314 "$dst {${mask}}, $src1, $src2, $cc}"),
1315 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1319 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1320 X86VectorVTInfo _> :
1321 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1322 let mayLoad = 1 in {
1323 def rmib : AVX512AIi8<opc, MRMSrcMem,
1324 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1326 !strconcat("vpcmp${cc}", Suffix,
1327 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1328 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1329 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1330 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1332 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1333 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1334 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1335 _.ScalarMemOp:$src2, AVXCC:$cc),
1336 !strconcat("vpcmp${cc}", Suffix,
1337 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1338 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1339 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1340 (OpNode (_.VT _.RC:$src1),
1341 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1343 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1346 // Accept explicit immediate argument form instead of comparison code.
1347 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1348 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1349 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1351 !strconcat("vpcmp", Suffix,
1352 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1353 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1354 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1355 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1356 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1357 _.ScalarMemOp:$src2, i8imm:$cc),
1358 !strconcat("vpcmp", Suffix,
1359 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1360 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1361 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1365 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1366 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1367 let Predicates = [prd] in
1368 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1370 let Predicates = [prd, HasVLX] in {
1371 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1372 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1376 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1377 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1378 let Predicates = [prd] in
1379 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1382 let Predicates = [prd, HasVLX] in {
1383 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1385 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1390 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1391 HasBWI>, EVEX_CD8<8, CD8VF>;
1392 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1393 HasBWI>, EVEX_CD8<8, CD8VF>;
1395 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1396 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1397 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1398 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1400 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1401 HasAVX512>, EVEX_CD8<32, CD8VF>;
1402 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1403 HasAVX512>, EVEX_CD8<32, CD8VF>;
1405 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1406 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1407 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1408 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1410 // avx512_cmp_packed - compare packed instructions
1411 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1412 X86MemOperand x86memop, ValueType vt,
1413 string suffix, Domain d> {
1414 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1415 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1416 !strconcat("vcmp${cc}", suffix,
1417 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1418 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1419 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1420 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1421 !strconcat("vcmp${cc}", suffix,
1422 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1424 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1425 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1426 !strconcat("vcmp${cc}", suffix,
1427 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1429 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1431 // Accept explicit immediate argument form instead of comparison code.
1432 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1433 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1434 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1435 !strconcat("vcmp", suffix,
1436 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1437 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1438 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1439 !strconcat("vcmp", suffix,
1440 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1444 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1445 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1446 EVEX_CD8<32, CD8VF>;
1447 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1448 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1449 EVEX_CD8<64, CD8VF>;
1451 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1452 (COPY_TO_REGCLASS (VCMPPSZrri
1453 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1454 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1456 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1457 (COPY_TO_REGCLASS (VPCMPDZrri
1458 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1459 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1461 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1462 (COPY_TO_REGCLASS (VPCMPUDZrri
1463 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1464 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1467 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1468 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1470 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1471 (I8Imm imm:$cc)), GR16)>;
1473 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1474 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1476 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1477 (I8Imm imm:$cc)), GR8)>;
1479 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1480 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1482 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1483 (I8Imm imm:$cc)), GR16)>;
1485 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1486 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1488 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1489 (I8Imm imm:$cc)), GR8)>;
1491 // Mask register copy, including
1492 // - copy between mask registers
1493 // - load/store mask registers
1494 // - copy from GPR to mask register and vice versa
1496 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1497 string OpcodeStr, RegisterClass KRC,
1498 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1499 let hasSideEffects = 0 in {
1500 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1501 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1503 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1504 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1505 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1507 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1508 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1512 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1514 RegisterClass KRC, RegisterClass GRC> {
1515 let hasSideEffects = 0 in {
1516 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1517 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1518 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1519 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1523 let Predicates = [HasDQI] in
1524 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1526 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1529 let Predicates = [HasAVX512] in
1530 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1532 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1535 let Predicates = [HasBWI] in {
1536 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1537 i32mem>, VEX, PD, VEX_W;
1538 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1542 let Predicates = [HasBWI] in {
1543 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1544 i64mem>, VEX, PS, VEX_W;
1545 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1549 // GR from/to mask register
1550 let Predicates = [HasDQI] in {
1551 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1552 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1553 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1554 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1556 let Predicates = [HasAVX512] in {
1557 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1558 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1559 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1560 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1562 let Predicates = [HasBWI] in {
1563 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1564 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1566 let Predicates = [HasBWI] in {
1567 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1568 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1572 let Predicates = [HasDQI] in {
1573 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1574 (KMOVBmk addr:$dst, VK8:$src)>;
1576 let Predicates = [HasAVX512] in {
1577 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1578 (KMOVWmk addr:$dst, VK16:$src)>;
1579 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1580 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1581 def : Pat<(i1 (load addr:$src)),
1582 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1583 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1584 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1586 let Predicates = [HasBWI] in {
1587 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1588 (KMOVDmk addr:$dst, VK32:$src)>;
1590 let Predicates = [HasBWI] in {
1591 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1592 (KMOVQmk addr:$dst, VK64:$src)>;
1595 let Predicates = [HasAVX512] in {
1596 def : Pat<(i1 (trunc (i64 GR64:$src))),
1597 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1600 def : Pat<(i1 (trunc (i32 GR32:$src))),
1601 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1603 def : Pat<(i1 (trunc (i8 GR8:$src))),
1605 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1607 def : Pat<(i1 (trunc (i16 GR16:$src))),
1609 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1612 def : Pat<(i32 (zext VK1:$src)),
1613 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1614 def : Pat<(i8 (zext VK1:$src)),
1617 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1618 def : Pat<(i64 (zext VK1:$src)),
1619 (AND64ri8 (SUBREG_TO_REG (i64 0),
1620 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1621 def : Pat<(i16 (zext VK1:$src)),
1623 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1625 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1626 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1627 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1628 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1630 let Predicates = [HasBWI] in {
1631 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1632 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1633 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1634 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1638 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1639 let Predicates = [HasAVX512] in {
1640 // GR from/to 8-bit mask without native support
1641 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1643 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1645 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1647 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1650 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1651 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1652 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1653 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1655 let Predicates = [HasBWI] in {
1656 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1657 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1658 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1659 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1662 // Mask unary operation
1664 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1665 RegisterClass KRC, SDPatternOperator OpNode,
1667 let Predicates = [prd] in
1668 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1669 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1670 [(set KRC:$dst, (OpNode KRC:$src))]>;
1673 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1674 SDPatternOperator OpNode> {
1675 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1677 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1678 HasAVX512>, VEX, PS;
1679 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1680 HasBWI>, VEX, PD, VEX_W;
1681 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1682 HasBWI>, VEX, PS, VEX_W;
1685 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1687 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1688 let Predicates = [HasAVX512] in
1689 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1691 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1692 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1694 defm : avx512_mask_unop_int<"knot", "KNOT">;
1696 let Predicates = [HasDQI] in
1697 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1698 let Predicates = [HasAVX512] in
1699 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1700 let Predicates = [HasBWI] in
1701 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1702 let Predicates = [HasBWI] in
1703 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1705 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1706 let Predicates = [HasAVX512] in {
1707 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1708 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1710 def : Pat<(not VK8:$src),
1712 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1715 // Mask binary operation
1716 // - KAND, KANDN, KOR, KXNOR, KXOR
1717 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1718 RegisterClass KRC, SDPatternOperator OpNode,
1720 let Predicates = [prd] in
1721 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1722 !strconcat(OpcodeStr,
1723 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1724 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1727 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1728 SDPatternOperator OpNode> {
1729 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1730 HasDQI>, VEX_4V, VEX_L, PD;
1731 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1732 HasAVX512>, VEX_4V, VEX_L, PS;
1733 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1734 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1735 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1736 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1739 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1740 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1742 let isCommutable = 1 in {
1743 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1744 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1745 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1746 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1748 let isCommutable = 0 in
1749 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1751 def : Pat<(xor VK1:$src1, VK1:$src2),
1752 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1753 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1755 def : Pat<(or VK1:$src1, VK1:$src2),
1756 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1757 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1759 def : Pat<(and VK1:$src1, VK1:$src2),
1760 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1761 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1763 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1764 let Predicates = [HasAVX512] in
1765 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1766 (i16 GR16:$src1), (i16 GR16:$src2)),
1767 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1768 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1769 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1772 defm : avx512_mask_binop_int<"kand", "KAND">;
1773 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1774 defm : avx512_mask_binop_int<"kor", "KOR">;
1775 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1776 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1778 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1779 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1780 let Predicates = [HasAVX512] in
1781 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1783 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1784 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1787 defm : avx512_binop_pat<and, KANDWrr>;
1788 defm : avx512_binop_pat<andn, KANDNWrr>;
1789 defm : avx512_binop_pat<or, KORWrr>;
1790 defm : avx512_binop_pat<xnor, KXNORWrr>;
1791 defm : avx512_binop_pat<xor, KXORWrr>;
1794 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1795 RegisterClass KRC> {
1796 let Predicates = [HasAVX512] in
1797 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1798 !strconcat(OpcodeStr,
1799 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1802 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1803 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1807 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1808 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1809 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1810 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1813 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1814 let Predicates = [HasAVX512] in
1815 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1816 (i16 GR16:$src1), (i16 GR16:$src2)),
1817 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1818 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1819 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1821 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1824 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1826 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1827 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1828 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1829 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1832 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1833 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1837 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1839 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1840 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1841 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1844 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1846 let Predicates = [HasAVX512] in
1847 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1848 !strconcat(OpcodeStr,
1849 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1850 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1853 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1855 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1859 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1860 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1862 // Mask setting all 0s or 1s
1863 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1864 let Predicates = [HasAVX512] in
1865 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1866 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1867 [(set KRC:$dst, (VT Val))]>;
1870 multiclass avx512_mask_setop_w<PatFrag Val> {
1871 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1872 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1875 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1876 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1878 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1879 let Predicates = [HasAVX512] in {
1880 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1881 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1882 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1883 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1884 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1886 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1887 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1889 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1890 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1892 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1893 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1895 let Predicates = [HasVLX] in {
1896 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1897 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1898 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1899 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1900 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1901 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1902 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1903 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1906 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1907 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1909 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1910 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1911 //===----------------------------------------------------------------------===//
1912 // AVX-512 - Aligned and unaligned load and store
1915 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1916 RegisterClass KRC, RegisterClass RC,
1917 ValueType vt, ValueType zvt, X86MemOperand memop,
1918 Domain d, bit IsReMaterializable = 1> {
1919 let hasSideEffects = 0 in {
1920 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1921 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1923 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1924 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1925 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1927 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1928 SchedRW = [WriteLoad] in
1929 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1930 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1931 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1934 let AddedComplexity = 20 in {
1935 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1936 let hasSideEffects = 0 in
1937 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1938 (ins RC:$src0, KRC:$mask, RC:$src1),
1939 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1940 "${dst} {${mask}}, $src1}"),
1941 [(set RC:$dst, (vt (vselect KRC:$mask,
1945 let mayLoad = 1, SchedRW = [WriteLoad] in
1946 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1947 (ins RC:$src0, KRC:$mask, memop:$src1),
1948 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1949 "${dst} {${mask}}, $src1}"),
1952 (vt (bitconvert (ld_frag addr:$src1))),
1956 let mayLoad = 1, SchedRW = [WriteLoad] in
1957 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1958 (ins KRC:$mask, memop:$src),
1959 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1960 "${dst} {${mask}} {z}, $src}"),
1963 (vt (bitconvert (ld_frag addr:$src))),
1964 (vt (bitconvert (zvt immAllZerosV))))))],
1969 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1970 string elty, string elsz, string vsz512,
1971 string vsz256, string vsz128, Domain d,
1972 Predicate prd, bit IsReMaterializable = 1> {
1973 let Predicates = [prd] in
1974 defm Z : avx512_load<opc, OpcodeStr,
1975 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1976 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1977 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1978 !cast<X86MemOperand>(elty##"512mem"), d,
1979 IsReMaterializable>, EVEX_V512;
1981 let Predicates = [prd, HasVLX] in {
1982 defm Z256 : avx512_load<opc, OpcodeStr,
1983 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1984 "v"##vsz256##elty##elsz, "v4i64")),
1985 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1986 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1987 !cast<X86MemOperand>(elty##"256mem"), d,
1988 IsReMaterializable>, EVEX_V256;
1990 defm Z128 : avx512_load<opc, OpcodeStr,
1991 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1992 "v"##vsz128##elty##elsz, "v2i64")),
1993 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1994 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1995 !cast<X86MemOperand>(elty##"128mem"), d,
1996 IsReMaterializable>, EVEX_V128;
2001 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2002 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2003 X86MemOperand memop, Domain d> {
2004 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2005 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2006 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2008 let Constraints = "$src1 = $dst" in
2009 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2010 (ins RC:$src1, KRC:$mask, RC:$src2),
2011 !strconcat(OpcodeStr,
2012 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2014 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2015 (ins KRC:$mask, RC:$src),
2016 !strconcat(OpcodeStr,
2017 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2018 [], d>, EVEX, EVEX_KZ;
2020 let mayStore = 1 in {
2021 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2022 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2023 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2024 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2025 (ins memop:$dst, KRC:$mask, RC:$src),
2026 !strconcat(OpcodeStr,
2027 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2028 [], d>, EVEX, EVEX_K;
2033 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2034 string st_suff_512, string st_suff_256,
2035 string st_suff_128, string elty, string elsz,
2036 string vsz512, string vsz256, string vsz128,
2037 Domain d, Predicate prd> {
2038 let Predicates = [prd] in
2039 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2040 !cast<ValueType>("v"##vsz512##elty##elsz),
2041 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2042 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2044 let Predicates = [prd, HasVLX] in {
2045 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2046 !cast<ValueType>("v"##vsz256##elty##elsz),
2047 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2048 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2050 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2051 !cast<ValueType>("v"##vsz128##elty##elsz),
2052 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2053 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2057 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2058 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2059 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2060 "512", "256", "", "f", "32", "16", "8", "4",
2061 SSEPackedSingle, HasAVX512>,
2062 PS, EVEX_CD8<32, CD8VF>;
2064 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2065 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2066 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2067 "512", "256", "", "f", "64", "8", "4", "2",
2068 SSEPackedDouble, HasAVX512>,
2069 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2071 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2072 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2073 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2074 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2075 PS, EVEX_CD8<32, CD8VF>;
2077 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2078 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2079 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2080 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2081 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2083 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2084 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2085 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2087 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2088 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2089 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2091 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2093 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2095 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2097 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2100 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2101 "16", "8", "4", SSEPackedInt, HasAVX512>,
2102 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2103 "512", "256", "", "i", "32", "16", "8", "4",
2104 SSEPackedInt, HasAVX512>,
2105 PD, EVEX_CD8<32, CD8VF>;
2107 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2108 "8", "4", "2", SSEPackedInt, HasAVX512>,
2109 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2110 "512", "256", "", "i", "64", "8", "4", "2",
2111 SSEPackedInt, HasAVX512>,
2112 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2114 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2115 "64", "32", "16", SSEPackedInt, HasBWI>,
2116 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2117 "i", "8", "64", "32", "16", SSEPackedInt,
2118 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2120 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2121 "32", "16", "8", SSEPackedInt, HasBWI>,
2122 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2123 "i", "16", "32", "16", "8", SSEPackedInt,
2124 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2126 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2127 "16", "8", "4", SSEPackedInt, HasAVX512>,
2128 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2129 "i", "32", "16", "8", "4", SSEPackedInt,
2130 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2132 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2133 "8", "4", "2", SSEPackedInt, HasAVX512>,
2134 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2135 "i", "64", "8", "4", "2", SSEPackedInt,
2136 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2138 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2139 (v16i32 immAllZerosV), GR16:$mask)),
2140 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2142 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2143 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2144 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2146 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2148 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2150 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2152 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2155 let AddedComplexity = 20 in {
2156 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2157 (bc_v8i64 (v16i32 immAllZerosV)))),
2158 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2160 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2161 (v8i64 VR512:$src))),
2162 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2165 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2166 (v16i32 immAllZerosV))),
2167 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2169 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2170 (v16i32 VR512:$src))),
2171 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2174 // Move Int Doubleword to Packed Double Int
2176 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2177 "vmovd\t{$src, $dst|$dst, $src}",
2179 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2181 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2182 "vmovd\t{$src, $dst|$dst, $src}",
2184 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2185 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2186 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2187 "vmovq\t{$src, $dst|$dst, $src}",
2189 (v2i64 (scalar_to_vector GR64:$src)))],
2190 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2191 let isCodeGenOnly = 1 in {
2192 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2193 "vmovq\t{$src, $dst|$dst, $src}",
2194 [(set FR64:$dst, (bitconvert GR64:$src))],
2195 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2196 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2197 "vmovq\t{$src, $dst|$dst, $src}",
2198 [(set GR64:$dst, (bitconvert FR64:$src))],
2199 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2201 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2202 "vmovq\t{$src, $dst|$dst, $src}",
2203 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2204 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2205 EVEX_CD8<64, CD8VT1>;
2207 // Move Int Doubleword to Single Scalar
2209 let isCodeGenOnly = 1 in {
2210 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2211 "vmovd\t{$src, $dst|$dst, $src}",
2212 [(set FR32X:$dst, (bitconvert GR32:$src))],
2213 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2215 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2216 "vmovd\t{$src, $dst|$dst, $src}",
2217 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2218 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2221 // Move doubleword from xmm register to r/m32
2223 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2224 "vmovd\t{$src, $dst|$dst, $src}",
2225 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2226 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2228 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2229 (ins i32mem:$dst, VR128X:$src),
2230 "vmovd\t{$src, $dst|$dst, $src}",
2231 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2232 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2233 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2235 // Move quadword from xmm1 register to r/m64
2237 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2238 "vmovq\t{$src, $dst|$dst, $src}",
2239 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2241 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2242 Requires<[HasAVX512, In64BitMode]>;
2244 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2245 (ins i64mem:$dst, VR128X:$src),
2246 "vmovq\t{$src, $dst|$dst, $src}",
2247 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2248 addr:$dst)], IIC_SSE_MOVDQ>,
2249 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2250 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2252 // Move Scalar Single to Double Int
2254 let isCodeGenOnly = 1 in {
2255 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2257 "vmovd\t{$src, $dst|$dst, $src}",
2258 [(set GR32:$dst, (bitconvert FR32X:$src))],
2259 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2260 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2261 (ins i32mem:$dst, FR32X:$src),
2262 "vmovd\t{$src, $dst|$dst, $src}",
2263 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2264 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2267 // Move Quadword Int to Packed Quadword Int
2269 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2271 "vmovq\t{$src, $dst|$dst, $src}",
2273 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2274 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2276 //===----------------------------------------------------------------------===//
2277 // AVX-512 MOVSS, MOVSD
2278 //===----------------------------------------------------------------------===//
2280 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2281 SDNode OpNode, ValueType vt,
2282 X86MemOperand x86memop, PatFrag mem_pat> {
2283 let hasSideEffects = 0 in {
2284 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2285 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2286 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2287 (scalar_to_vector RC:$src2))))],
2288 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2289 let Constraints = "$src1 = $dst" in
2290 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2291 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2293 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2294 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2295 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2296 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2297 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2299 let mayStore = 1 in {
2300 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2301 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2302 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2304 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2305 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2306 [], IIC_SSE_MOV_S_MR>,
2307 EVEX, VEX_LIG, EVEX_K;
2309 } //hasSideEffects = 0
2312 let ExeDomain = SSEPackedSingle in
2313 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2314 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2316 let ExeDomain = SSEPackedDouble in
2317 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2318 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2320 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2321 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2322 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2324 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2325 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2326 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2328 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2329 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2330 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2332 // For the disassembler
2333 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2334 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2335 (ins VR128X:$src1, FR32X:$src2),
2336 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2338 XS, EVEX_4V, VEX_LIG;
2339 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2340 (ins VR128X:$src1, FR64X:$src2),
2341 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2343 XD, EVEX_4V, VEX_LIG, VEX_W;
2346 let Predicates = [HasAVX512] in {
2347 let AddedComplexity = 15 in {
2348 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2349 // MOVS{S,D} to the lower bits.
2350 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2351 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2352 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2353 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2354 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2355 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2356 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2357 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2359 // Move low f32 and clear high bits.
2360 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2361 (SUBREG_TO_REG (i32 0),
2362 (VMOVSSZrr (v4f32 (V_SET0)),
2363 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2364 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2365 (SUBREG_TO_REG (i32 0),
2366 (VMOVSSZrr (v4i32 (V_SET0)),
2367 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2370 let AddedComplexity = 20 in {
2371 // MOVSSrm zeros the high parts of the register; represent this
2372 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2373 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2374 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2375 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2376 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2377 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2378 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2380 // MOVSDrm zeros the high parts of the register; represent this
2381 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2382 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2383 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2384 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2385 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2386 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2387 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2388 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2389 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2390 def : Pat<(v2f64 (X86vzload addr:$src)),
2391 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2393 // Represent the same patterns above but in the form they appear for
2395 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2396 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2397 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2398 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2399 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2400 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2401 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2402 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2403 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2405 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2406 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2407 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2408 FR32X:$src)), sub_xmm)>;
2409 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2410 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2411 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2412 FR64X:$src)), sub_xmm)>;
2413 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2414 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2415 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2417 // Move low f64 and clear high bits.
2418 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2419 (SUBREG_TO_REG (i32 0),
2420 (VMOVSDZrr (v2f64 (V_SET0)),
2421 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2423 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2424 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2425 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2427 // Extract and store.
2428 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2430 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2431 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2433 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2435 // Shuffle with VMOVSS
2436 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2437 (VMOVSSZrr (v4i32 VR128X:$src1),
2438 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2439 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2440 (VMOVSSZrr (v4f32 VR128X:$src1),
2441 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2444 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2445 (SUBREG_TO_REG (i32 0),
2446 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2447 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2449 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2450 (SUBREG_TO_REG (i32 0),
2451 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2452 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2455 // Shuffle with VMOVSD
2456 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2457 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2458 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2459 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2460 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2461 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2462 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2463 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2466 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2467 (SUBREG_TO_REG (i32 0),
2468 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2469 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2471 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2472 (SUBREG_TO_REG (i32 0),
2473 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2474 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2477 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2478 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2479 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2480 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2481 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2482 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2483 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2484 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2487 let AddedComplexity = 15 in
2488 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2490 "vmovq\t{$src, $dst|$dst, $src}",
2491 [(set VR128X:$dst, (v2i64 (X86vzmovl
2492 (v2i64 VR128X:$src))))],
2493 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2495 let AddedComplexity = 20 in
2496 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2498 "vmovq\t{$src, $dst|$dst, $src}",
2499 [(set VR128X:$dst, (v2i64 (X86vzmovl
2500 (loadv2i64 addr:$src))))],
2501 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2502 EVEX_CD8<8, CD8VT8>;
2504 let Predicates = [HasAVX512] in {
2505 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2506 let AddedComplexity = 20 in {
2507 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2508 (VMOVDI2PDIZrm addr:$src)>;
2509 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2510 (VMOV64toPQIZrr GR64:$src)>;
2511 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2512 (VMOVDI2PDIZrr GR32:$src)>;
2514 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2515 (VMOVDI2PDIZrm addr:$src)>;
2516 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2517 (VMOVDI2PDIZrm addr:$src)>;
2518 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2519 (VMOVZPQILo2PQIZrm addr:$src)>;
2520 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2521 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2522 def : Pat<(v2i64 (X86vzload addr:$src)),
2523 (VMOVZPQILo2PQIZrm addr:$src)>;
2526 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2527 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2528 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2529 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2530 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2531 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2532 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2535 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2536 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2538 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2539 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2541 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2542 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2544 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2545 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2547 //===----------------------------------------------------------------------===//
2548 // AVX-512 - Non-temporals
2549 //===----------------------------------------------------------------------===//
2550 let SchedRW = [WriteLoad] in {
2551 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2552 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2553 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2554 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2555 EVEX_CD8<64, CD8VF>;
2557 let Predicates = [HasAVX512, HasVLX] in {
2558 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2560 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2561 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2562 EVEX_CD8<64, CD8VF>;
2564 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2566 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2567 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2568 EVEX_CD8<64, CD8VF>;
2572 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2573 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2574 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2575 let SchedRW = [WriteStore], mayStore = 1,
2576 AddedComplexity = 400 in
2577 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2578 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2579 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2582 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2583 string elty, string elsz, string vsz512,
2584 string vsz256, string vsz128, Domain d,
2585 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2586 let Predicates = [prd] in
2587 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2588 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2589 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2592 let Predicates = [prd, HasVLX] in {
2593 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2594 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2595 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2598 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2599 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2600 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2605 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2606 "i", "64", "8", "4", "2", SSEPackedInt,
2607 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2609 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2610 "f", "64", "8", "4", "2", SSEPackedDouble,
2611 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2613 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2614 "f", "32", "16", "8", "4", SSEPackedSingle,
2615 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2617 //===----------------------------------------------------------------------===//
2618 // AVX-512 - Integer arithmetic
2620 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2621 X86VectorVTInfo _, OpndItins itins,
2622 bit IsCommutable = 0> {
2623 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2624 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2625 "$src2, $src1", "$src1, $src2",
2626 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2627 "", itins.rr, IsCommutable>,
2628 AVX512BIBase, EVEX_4V;
2631 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2632 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2633 "$src2, $src1", "$src1, $src2",
2634 (_.VT (OpNode _.RC:$src1,
2635 (bitconvert (_.LdFrag addr:$src2)))),
2637 AVX512BIBase, EVEX_4V;
2640 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2641 X86VectorVTInfo _, OpndItins itins,
2642 bit IsCommutable = 0> :
2643 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2645 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2646 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2647 "${src2}"##_.BroadcastStr##", $src1",
2648 "$src1, ${src2}"##_.BroadcastStr,
2649 (_.VT (OpNode _.RC:$src1,
2651 (_.ScalarLdFrag addr:$src2)))),
2653 AVX512BIBase, EVEX_4V, EVEX_B;
2656 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2657 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2658 Predicate prd, bit IsCommutable = 0> {
2659 let Predicates = [prd] in
2660 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2661 IsCommutable>, EVEX_V512;
2663 let Predicates = [prd, HasVLX] in {
2664 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2665 IsCommutable>, EVEX_V256;
2666 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2667 IsCommutable>, EVEX_V128;
2671 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2672 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2673 Predicate prd, bit IsCommutable = 0> {
2674 let Predicates = [prd] in
2675 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2676 IsCommutable>, EVEX_V512;
2678 let Predicates = [prd, HasVLX] in {
2679 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2680 IsCommutable>, EVEX_V256;
2681 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2682 IsCommutable>, EVEX_V128;
2686 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2687 OpndItins itins, Predicate prd,
2688 bit IsCommutable = 0> {
2689 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2690 itins, prd, IsCommutable>,
2691 VEX_W, EVEX_CD8<64, CD8VF>;
2694 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2695 OpndItins itins, Predicate prd,
2696 bit IsCommutable = 0> {
2697 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2698 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2701 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2702 OpndItins itins, Predicate prd,
2703 bit IsCommutable = 0> {
2704 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2705 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2708 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2709 OpndItins itins, Predicate prd,
2710 bit IsCommutable = 0> {
2711 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2712 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2715 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2716 SDNode OpNode, OpndItins itins, Predicate prd,
2717 bit IsCommutable = 0> {
2718 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2721 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2725 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2726 SDNode OpNode, OpndItins itins, Predicate prd,
2727 bit IsCommutable = 0> {
2728 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2731 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2735 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2736 bits<8> opc_d, bits<8> opc_q,
2737 string OpcodeStr, SDNode OpNode,
2738 OpndItins itins, bit IsCommutable = 0> {
2739 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2740 itins, HasAVX512, IsCommutable>,
2741 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2742 itins, HasBWI, IsCommutable>;
2745 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2746 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2747 PatFrag memop_frag, X86MemOperand x86memop,
2748 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2749 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2750 let isCommutable = IsCommutable in
2752 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2753 (ins RC:$src1, RC:$src2),
2754 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2756 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2757 (ins KRC:$mask, RC:$src1, RC:$src2),
2758 !strconcat(OpcodeStr,
2759 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2760 [], itins.rr>, EVEX_4V, EVEX_K;
2761 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2762 (ins KRC:$mask, RC:$src1, RC:$src2),
2763 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2764 "|$dst {${mask}} {z}, $src1, $src2}"),
2765 [], itins.rr>, EVEX_4V, EVEX_KZ;
2767 let mayLoad = 1 in {
2768 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2769 (ins RC:$src1, x86memop:$src2),
2770 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2772 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2773 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2774 !strconcat(OpcodeStr,
2775 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2776 [], itins.rm>, EVEX_4V, EVEX_K;
2777 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2778 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2779 !strconcat(OpcodeStr,
2780 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2781 [], itins.rm>, EVEX_4V, EVEX_KZ;
2782 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2783 (ins RC:$src1, x86scalar_mop:$src2),
2784 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2785 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2786 [], itins.rm>, EVEX_4V, EVEX_B;
2787 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2788 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2789 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2790 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2792 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2793 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2794 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2795 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2796 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2798 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2802 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2803 SSE_INTALU_ITINS_P, 1>;
2804 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2805 SSE_INTALU_ITINS_P, 0>;
2806 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2807 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2808 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2809 SSE_INTALU_ITINS_P, HasBWI, 1>;
2810 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2811 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2813 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2814 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2815 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2816 EVEX_CD8<64, CD8VF>, VEX_W;
2818 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2819 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2820 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2822 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2823 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2825 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2826 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2827 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2828 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2829 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2830 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2832 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2833 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2834 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2835 SSE_INTALU_ITINS_P, HasBWI, 1>;
2836 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2837 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2839 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2840 SSE_INTALU_ITINS_P, HasBWI, 1>;
2841 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2842 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2843 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2844 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2846 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2847 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2848 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2849 SSE_INTALU_ITINS_P, HasBWI, 1>;
2850 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2851 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2853 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2854 SSE_INTALU_ITINS_P, HasBWI, 1>;
2855 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2856 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2857 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2858 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2860 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2861 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2862 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2863 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2864 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2865 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2866 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2867 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2868 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2869 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2870 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2871 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2872 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2873 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2874 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2875 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2876 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2877 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2878 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2879 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2880 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2881 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2882 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2883 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2884 //===----------------------------------------------------------------------===//
2885 // AVX-512 - Unpack Instructions
2886 //===----------------------------------------------------------------------===//
2888 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2889 PatFrag mem_frag, RegisterClass RC,
2890 X86MemOperand x86memop, string asm,
2892 def rr : AVX512PI<opc, MRMSrcReg,
2893 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2895 (vt (OpNode RC:$src1, RC:$src2)))],
2897 def rm : AVX512PI<opc, MRMSrcMem,
2898 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2900 (vt (OpNode RC:$src1,
2901 (bitconvert (mem_frag addr:$src2)))))],
2905 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2906 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2907 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2908 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2909 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2910 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2911 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2912 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2913 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2914 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2915 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2916 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2918 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2919 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2920 X86MemOperand x86memop> {
2921 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2922 (ins RC:$src1, RC:$src2),
2923 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2924 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2925 IIC_SSE_UNPCK>, EVEX_4V;
2926 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2927 (ins RC:$src1, x86memop:$src2),
2928 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2929 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2930 (bitconvert (memop_frag addr:$src2)))))],
2931 IIC_SSE_UNPCK>, EVEX_4V;
2933 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2934 VR512, memopv16i32, i512mem>, EVEX_V512,
2935 EVEX_CD8<32, CD8VF>;
2936 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2937 VR512, memopv8i64, i512mem>, EVEX_V512,
2938 VEX_W, EVEX_CD8<64, CD8VF>;
2939 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2940 VR512, memopv16i32, i512mem>, EVEX_V512,
2941 EVEX_CD8<32, CD8VF>;
2942 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2943 VR512, memopv8i64, i512mem>, EVEX_V512,
2944 VEX_W, EVEX_CD8<64, CD8VF>;
2945 //===----------------------------------------------------------------------===//
2949 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2950 SDNode OpNode, PatFrag mem_frag,
2951 X86MemOperand x86memop, ValueType OpVT> {
2952 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2953 (ins RC:$src1, i8imm:$src2),
2954 !strconcat(OpcodeStr,
2955 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2957 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2959 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2960 (ins x86memop:$src1, i8imm:$src2),
2961 !strconcat(OpcodeStr,
2962 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2964 (OpVT (OpNode (mem_frag addr:$src1),
2965 (i8 imm:$src2))))]>, EVEX;
2968 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2969 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2971 //===----------------------------------------------------------------------===//
2972 // AVX-512 Logical Instructions
2973 //===----------------------------------------------------------------------===//
2975 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
2976 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2977 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
2978 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2979 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
2980 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2981 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
2982 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2984 //===----------------------------------------------------------------------===//
2985 // AVX-512 FP arithmetic
2986 //===----------------------------------------------------------------------===//
2988 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2990 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2991 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2992 EVEX_CD8<32, CD8VT1>;
2993 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2994 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2995 EVEX_CD8<64, CD8VT1>;
2998 let isCommutable = 1 in {
2999 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3000 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3001 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3002 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3004 let isCommutable = 0 in {
3005 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3006 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3009 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3010 X86VectorVTInfo _, bit IsCommutable> {
3011 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3012 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3013 "$src2, $src1", "$src1, $src2",
3014 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3015 let mayLoad = 1 in {
3016 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3017 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3018 "$src2, $src1", "$src1, $src2",
3019 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3020 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3021 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3022 "${src2}"##_.BroadcastStr##", $src1",
3023 "$src1, ${src2}"##_.BroadcastStr,
3024 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3025 (_.ScalarLdFrag addr:$src2))))>,
3030 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3031 bit IsCommutable = 0> {
3032 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3033 IsCommutable>, EVEX_V512, PS,
3034 EVEX_CD8<32, CD8VF>;
3035 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3036 IsCommutable>, EVEX_V512, PD, VEX_W,
3037 EVEX_CD8<64, CD8VF>;
3039 // Define only if AVX512VL feature is present.
3040 let Predicates = [HasVLX] in {
3041 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3042 IsCommutable>, EVEX_V128, PS,
3043 EVEX_CD8<32, CD8VF>;
3044 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3045 IsCommutable>, EVEX_V256, PS,
3046 EVEX_CD8<32, CD8VF>;
3047 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3048 IsCommutable>, EVEX_V128, PD, VEX_W,
3049 EVEX_CD8<64, CD8VF>;
3050 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3051 IsCommutable>, EVEX_V256, PD, VEX_W,
3052 EVEX_CD8<64, CD8VF>;
3056 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3057 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3058 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3059 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3060 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3061 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3063 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3064 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3065 (i16 -1), FROUND_CURRENT)),
3066 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3068 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3069 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3070 (i8 -1), FROUND_CURRENT)),
3071 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3073 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3074 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3075 (i16 -1), FROUND_CURRENT)),
3076 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3078 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3079 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3080 (i8 -1), FROUND_CURRENT)),
3081 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3082 //===----------------------------------------------------------------------===//
3083 // AVX-512 VPTESTM instructions
3084 //===----------------------------------------------------------------------===//
3086 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3087 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3088 SDNode OpNode, ValueType vt> {
3089 def rr : AVX512PI<opc, MRMSrcReg,
3090 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3091 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3092 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3093 SSEPackedInt>, EVEX_4V;
3094 def rm : AVX512PI<opc, MRMSrcMem,
3095 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3096 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3097 [(set KRC:$dst, (OpNode (vt RC:$src1),
3098 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3101 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3102 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3103 EVEX_CD8<32, CD8VF>;
3104 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3105 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3106 EVEX_CD8<64, CD8VF>;
3108 let Predicates = [HasCDI] in {
3109 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3110 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3111 EVEX_CD8<32, CD8VF>;
3112 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3113 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3114 EVEX_CD8<64, CD8VF>;
3117 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3118 (v16i32 VR512:$src2), (i16 -1))),
3119 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3121 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3122 (v8i64 VR512:$src2), (i8 -1))),
3123 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3124 //===----------------------------------------------------------------------===//
3125 // AVX-512 Shift instructions
3126 //===----------------------------------------------------------------------===//
3127 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3128 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3129 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3130 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3131 "$src2, $src1", "$src1, $src2",
3132 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3133 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3134 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3135 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3136 "$src2, $src1", "$src1, $src2",
3137 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3138 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3141 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3142 RegisterClass RC, ValueType vt, ValueType SrcVT,
3143 PatFrag bc_frag, RegisterClass KRC> {
3144 // src2 is always 128-bit
3145 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3146 (ins RC:$src1, VR128X:$src2),
3147 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3148 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3149 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3150 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3151 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3152 !strconcat(OpcodeStr,
3153 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3154 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3155 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3156 (ins RC:$src1, i128mem:$src2),
3157 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3158 [(set RC:$dst, (vt (OpNode RC:$src1,
3159 (bc_frag (memopv2i64 addr:$src2)))))],
3160 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3161 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3162 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3163 !strconcat(OpcodeStr,
3164 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3165 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3168 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3170 EVEX_V512, EVEX_CD8<32, CD8VF>;
3171 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3172 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3173 EVEX_CD8<32, CD8VQ>;
3175 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3176 v8i64_info>, EVEX_V512,
3177 EVEX_CD8<64, CD8VF>, VEX_W;
3178 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3179 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3180 EVEX_CD8<64, CD8VQ>, VEX_W;
3182 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3183 v16i32_info>, EVEX_V512,
3184 EVEX_CD8<32, CD8VF>;
3185 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3186 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3187 EVEX_CD8<32, CD8VQ>;
3189 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3190 v8i64_info>, EVEX_V512,
3191 EVEX_CD8<64, CD8VF>, VEX_W;
3192 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3193 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3194 EVEX_CD8<64, CD8VQ>, VEX_W;
3196 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3198 EVEX_V512, EVEX_CD8<32, CD8VF>;
3199 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3200 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3201 EVEX_CD8<32, CD8VQ>;
3203 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3204 v8i64_info>, EVEX_V512,
3205 EVEX_CD8<64, CD8VF>, VEX_W;
3206 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3207 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3208 EVEX_CD8<64, CD8VQ>, VEX_W;
3210 //===-------------------------------------------------------------------===//
3211 // Variable Bit Shifts
3212 //===-------------------------------------------------------------------===//
3213 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3214 RegisterClass RC, ValueType vt,
3215 X86MemOperand x86memop, PatFrag mem_frag> {
3216 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3217 (ins RC:$src1, RC:$src2),
3218 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3220 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3222 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3223 (ins RC:$src1, x86memop:$src2),
3224 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3226 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3230 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3231 i512mem, memopv16i32>, EVEX_V512,
3232 EVEX_CD8<32, CD8VF>;
3233 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3234 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3235 EVEX_CD8<64, CD8VF>;
3236 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3237 i512mem, memopv16i32>, EVEX_V512,
3238 EVEX_CD8<32, CD8VF>;
3239 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3240 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3241 EVEX_CD8<64, CD8VF>;
3242 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3243 i512mem, memopv16i32>, EVEX_V512,
3244 EVEX_CD8<32, CD8VF>;
3245 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3246 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3247 EVEX_CD8<64, CD8VF>;
3249 //===----------------------------------------------------------------------===//
3250 // AVX-512 - MOVDDUP
3251 //===----------------------------------------------------------------------===//
3253 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3254 X86MemOperand x86memop, PatFrag memop_frag> {
3255 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3256 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3257 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3258 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3259 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3261 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3264 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3265 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3266 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3267 (VMOVDDUPZrm addr:$src)>;
3269 //===---------------------------------------------------------------------===//
3270 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3271 //===---------------------------------------------------------------------===//
3272 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3273 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3274 X86MemOperand x86memop> {
3275 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3276 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3277 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3279 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3280 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3281 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3284 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3285 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3286 EVEX_CD8<32, CD8VF>;
3287 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3288 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3289 EVEX_CD8<32, CD8VF>;
3291 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3292 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3293 (VMOVSHDUPZrm addr:$src)>;
3294 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3295 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3296 (VMOVSLDUPZrm addr:$src)>;
3298 //===----------------------------------------------------------------------===//
3299 // Move Low to High and High to Low packed FP Instructions
3300 //===----------------------------------------------------------------------===//
3301 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3302 (ins VR128X:$src1, VR128X:$src2),
3303 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3304 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3305 IIC_SSE_MOV_LH>, EVEX_4V;
3306 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3307 (ins VR128X:$src1, VR128X:$src2),
3308 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3309 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3310 IIC_SSE_MOV_LH>, EVEX_4V;
3312 let Predicates = [HasAVX512] in {
3314 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3315 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3316 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3317 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3320 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3321 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3324 //===----------------------------------------------------------------------===//
3325 // FMA - Fused Multiply Operations
3328 let Constraints = "$src1 = $dst" in {
3329 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3330 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3331 SDPatternOperator OpNode = null_frag> {
3332 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3333 (ins _.RC:$src2, _.RC:$src3),
3334 OpcodeStr, "$src3, $src2", "$src2, $src3",
3335 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3339 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3340 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3341 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3342 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3343 (_.MemOpFrag addr:$src3))))]>;
3344 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3345 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3346 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3347 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3348 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3349 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3351 } // Constraints = "$src1 = $dst"
3353 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3354 string OpcodeStr, X86VectorVTInfo VTI,
3355 SDPatternOperator OpNode> {
3356 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3358 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3360 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3362 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3365 let ExeDomain = SSEPackedSingle in {
3366 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3367 v16f32_info, X86Fmadd>;
3368 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3369 v16f32_info, X86Fmsub>;
3370 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3371 v16f32_info, X86Fmaddsub>;
3372 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3373 v16f32_info, X86Fmsubadd>;
3374 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3375 v16f32_info, X86Fnmadd>;
3376 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3377 v16f32_info, X86Fnmsub>;
3379 let ExeDomain = SSEPackedDouble in {
3380 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3381 v8f64_info, X86Fmadd>, VEX_W;
3382 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3383 v8f64_info, X86Fmsub>, VEX_W;
3384 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3385 v8f64_info, X86Fmaddsub>, VEX_W;
3386 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3387 v8f64_info, X86Fmsubadd>, VEX_W;
3388 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3389 v8f64_info, X86Fnmadd>, VEX_W;
3390 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3391 v8f64_info, X86Fnmsub>, VEX_W;
3394 let Constraints = "$src1 = $dst" in {
3395 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3396 X86VectorVTInfo _> {
3398 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3399 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3400 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3401 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3403 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3404 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3405 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3406 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3408 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3409 (_.ScalarLdFrag addr:$src2))),
3410 _.RC:$src3))]>, EVEX_B;
3412 } // Constraints = "$src1 = $dst"
3415 let ExeDomain = SSEPackedSingle in {
3416 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3418 EVEX_V512, EVEX_CD8<32, CD8VF>;
3419 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3421 EVEX_V512, EVEX_CD8<32, CD8VF>;
3422 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3424 EVEX_V512, EVEX_CD8<32, CD8VF>;
3425 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3427 EVEX_V512, EVEX_CD8<32, CD8VF>;
3428 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3430 EVEX_V512, EVEX_CD8<32, CD8VF>;
3431 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3433 EVEX_V512, EVEX_CD8<32, CD8VF>;
3435 let ExeDomain = SSEPackedDouble in {
3436 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3438 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3439 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3441 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3442 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3444 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3445 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3447 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3448 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3450 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3451 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3453 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3457 let Constraints = "$src1 = $dst" in {
3458 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3459 RegisterClass RC, ValueType OpVT,
3460 X86MemOperand x86memop, Operand memop,
3462 let isCommutable = 1 in
3463 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3464 (ins RC:$src1, RC:$src2, RC:$src3),
3465 !strconcat(OpcodeStr,
3466 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3468 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3470 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3471 (ins RC:$src1, RC:$src2, f128mem:$src3),
3472 !strconcat(OpcodeStr,
3473 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3475 (OpVT (OpNode RC:$src2, RC:$src1,
3476 (mem_frag addr:$src3))))]>;
3479 } // Constraints = "$src1 = $dst"
3481 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3482 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3483 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3484 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3485 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3486 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3487 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3488 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3489 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3490 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3491 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3492 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3493 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3494 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3495 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3496 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3498 //===----------------------------------------------------------------------===//
3499 // AVX-512 Scalar convert from sign integer to float/double
3500 //===----------------------------------------------------------------------===//
3502 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3503 X86MemOperand x86memop, string asm> {
3504 let hasSideEffects = 0 in {
3505 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3506 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3509 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3510 (ins DstRC:$src1, x86memop:$src),
3511 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3513 } // hasSideEffects = 0
3515 let Predicates = [HasAVX512] in {
3516 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3517 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3518 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3519 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3520 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3521 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3522 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3523 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3525 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3526 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3527 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3528 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3529 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3530 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3531 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3532 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3534 def : Pat<(f32 (sint_to_fp GR32:$src)),
3535 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3536 def : Pat<(f32 (sint_to_fp GR64:$src)),
3537 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3538 def : Pat<(f64 (sint_to_fp GR32:$src)),
3539 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3540 def : Pat<(f64 (sint_to_fp GR64:$src)),
3541 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3543 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3544 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3545 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3546 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3547 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3548 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3549 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3550 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3552 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3553 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3554 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3555 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3556 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3557 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3558 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3559 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3561 def : Pat<(f32 (uint_to_fp GR32:$src)),
3562 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3563 def : Pat<(f32 (uint_to_fp GR64:$src)),
3564 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3565 def : Pat<(f64 (uint_to_fp GR32:$src)),
3566 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3567 def : Pat<(f64 (uint_to_fp GR64:$src)),
3568 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3571 //===----------------------------------------------------------------------===//
3572 // AVX-512 Scalar convert from float/double to integer
3573 //===----------------------------------------------------------------------===//
3574 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3575 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3577 let hasSideEffects = 0 in {
3578 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3579 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3580 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3581 Requires<[HasAVX512]>;
3583 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3584 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3585 Requires<[HasAVX512]>;
3586 } // hasSideEffects = 0
3588 let Predicates = [HasAVX512] in {
3589 // Convert float/double to signed/unsigned int 32/64
3590 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3591 ssmem, sse_load_f32, "cvtss2si">,
3592 XS, EVEX_CD8<32, CD8VT1>;
3593 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3594 ssmem, sse_load_f32, "cvtss2si">,
3595 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3596 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3597 ssmem, sse_load_f32, "cvtss2usi">,
3598 XS, EVEX_CD8<32, CD8VT1>;
3599 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3600 int_x86_avx512_cvtss2usi64, ssmem,
3601 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3602 EVEX_CD8<32, CD8VT1>;
3603 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3604 sdmem, sse_load_f64, "cvtsd2si">,
3605 XD, EVEX_CD8<64, CD8VT1>;
3606 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3607 sdmem, sse_load_f64, "cvtsd2si">,
3608 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3609 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3610 sdmem, sse_load_f64, "cvtsd2usi">,
3611 XD, EVEX_CD8<64, CD8VT1>;
3612 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3613 int_x86_avx512_cvtsd2usi64, sdmem,
3614 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3615 EVEX_CD8<64, CD8VT1>;
3617 let isCodeGenOnly = 1 in {
3618 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3619 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3620 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3621 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3622 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3623 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3624 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3625 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3626 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3627 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3628 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3629 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3631 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3632 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3633 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3634 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3635 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3636 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3637 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3638 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3639 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3640 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3641 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3642 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3643 } // isCodeGenOnly = 1
3645 // Convert float/double to signed/unsigned int 32/64 with truncation
3646 let isCodeGenOnly = 1 in {
3647 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3648 ssmem, sse_load_f32, "cvttss2si">,
3649 XS, EVEX_CD8<32, CD8VT1>;
3650 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3651 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3652 "cvttss2si">, XS, VEX_W,
3653 EVEX_CD8<32, CD8VT1>;
3654 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3655 sdmem, sse_load_f64, "cvttsd2si">, XD,
3656 EVEX_CD8<64, CD8VT1>;
3657 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3658 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3659 "cvttsd2si">, XD, VEX_W,
3660 EVEX_CD8<64, CD8VT1>;
3661 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3662 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3663 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3664 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3665 int_x86_avx512_cvttss2usi64, ssmem,
3666 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3667 EVEX_CD8<32, CD8VT1>;
3668 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3669 int_x86_avx512_cvttsd2usi,
3670 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3671 EVEX_CD8<64, CD8VT1>;
3672 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3673 int_x86_avx512_cvttsd2usi64, sdmem,
3674 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3675 EVEX_CD8<64, CD8VT1>;
3676 } // isCodeGenOnly = 1
3678 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3679 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3681 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3682 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3683 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3684 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3685 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3686 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3689 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3690 loadf32, "cvttss2si">, XS,
3691 EVEX_CD8<32, CD8VT1>;
3692 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3693 loadf32, "cvttss2usi">, XS,
3694 EVEX_CD8<32, CD8VT1>;
3695 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3696 loadf32, "cvttss2si">, XS, VEX_W,
3697 EVEX_CD8<32, CD8VT1>;
3698 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3699 loadf32, "cvttss2usi">, XS, VEX_W,
3700 EVEX_CD8<32, CD8VT1>;
3701 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3702 loadf64, "cvttsd2si">, XD,
3703 EVEX_CD8<64, CD8VT1>;
3704 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3705 loadf64, "cvttsd2usi">, XD,
3706 EVEX_CD8<64, CD8VT1>;
3707 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3708 loadf64, "cvttsd2si">, XD, VEX_W,
3709 EVEX_CD8<64, CD8VT1>;
3710 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3711 loadf64, "cvttsd2usi">, XD, VEX_W,
3712 EVEX_CD8<64, CD8VT1>;
3714 //===----------------------------------------------------------------------===//
3715 // AVX-512 Convert form float to double and back
3716 //===----------------------------------------------------------------------===//
3717 let hasSideEffects = 0 in {
3718 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3719 (ins FR32X:$src1, FR32X:$src2),
3720 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3721 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3723 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3724 (ins FR32X:$src1, f32mem:$src2),
3725 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3726 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3727 EVEX_CD8<32, CD8VT1>;
3729 // Convert scalar double to scalar single
3730 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3731 (ins FR64X:$src1, FR64X:$src2),
3732 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3733 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3735 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3736 (ins FR64X:$src1, f64mem:$src2),
3737 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3738 []>, EVEX_4V, VEX_LIG, VEX_W,
3739 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3742 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3743 Requires<[HasAVX512]>;
3744 def : Pat<(fextend (loadf32 addr:$src)),
3745 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3747 def : Pat<(extloadf32 addr:$src),
3748 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3749 Requires<[HasAVX512, OptForSize]>;
3751 def : Pat<(extloadf32 addr:$src),
3752 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3753 Requires<[HasAVX512, OptForSpeed]>;
3755 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3756 Requires<[HasAVX512]>;
3758 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3759 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3760 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3762 let hasSideEffects = 0 in {
3763 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3764 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3766 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3767 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3768 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3769 [], d>, EVEX, EVEX_B, EVEX_RC;
3771 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3772 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3774 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3775 } // hasSideEffects = 0
3778 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3779 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3780 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3782 let hasSideEffects = 0 in {
3783 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3784 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3786 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3788 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3789 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3791 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3792 } // hasSideEffects = 0
3795 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3796 memopv8f64, f512mem, v8f32, v8f64,
3797 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3798 EVEX_CD8<64, CD8VF>;
3800 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3801 memopv4f64, f256mem, v8f64, v8f32,
3802 SSEPackedDouble>, EVEX_V512, PS,
3803 EVEX_CD8<32, CD8VH>;
3804 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3805 (VCVTPS2PDZrm addr:$src)>;
3807 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3808 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3809 (VCVTPD2PSZrr VR512:$src)>;
3811 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3812 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3813 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3815 //===----------------------------------------------------------------------===//
3816 // AVX-512 Vector convert from sign integer to float/double
3817 //===----------------------------------------------------------------------===//
3819 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3820 memopv8i64, i512mem, v16f32, v16i32,
3821 SSEPackedSingle>, EVEX_V512, PS,
3822 EVEX_CD8<32, CD8VF>;
3824 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3825 memopv4i64, i256mem, v8f64, v8i32,
3826 SSEPackedDouble>, EVEX_V512, XS,
3827 EVEX_CD8<32, CD8VH>;
3829 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3830 memopv16f32, f512mem, v16i32, v16f32,
3831 SSEPackedSingle>, EVEX_V512, XS,
3832 EVEX_CD8<32, CD8VF>;
3834 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3835 memopv8f64, f512mem, v8i32, v8f64,
3836 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3837 EVEX_CD8<64, CD8VF>;
3839 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3840 memopv16f32, f512mem, v16i32, v16f32,
3841 SSEPackedSingle>, EVEX_V512, PS,
3842 EVEX_CD8<32, CD8VF>;
3844 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3845 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3846 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3847 (VCVTTPS2UDQZrr VR512:$src)>;
3849 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3850 memopv8f64, f512mem, v8i32, v8f64,
3851 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3852 EVEX_CD8<64, CD8VF>;
3854 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3855 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3856 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3857 (VCVTTPD2UDQZrr VR512:$src)>;
3859 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3860 memopv4i64, f256mem, v8f64, v8i32,
3861 SSEPackedDouble>, EVEX_V512, XS,
3862 EVEX_CD8<32, CD8VH>;
3864 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3865 memopv16i32, f512mem, v16f32, v16i32,
3866 SSEPackedSingle>, EVEX_V512, XD,
3867 EVEX_CD8<32, CD8VF>;
3869 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3870 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3871 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3873 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3874 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3875 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3877 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3878 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3879 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3881 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3882 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3883 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3885 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3886 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3887 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3889 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3890 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3891 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3892 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3893 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3894 (VCVTDQ2PDZrr VR256X:$src)>;
3895 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3896 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3897 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3898 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3899 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3900 (VCVTUDQ2PDZrr VR256X:$src)>;
3902 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3903 RegisterClass DstRC, PatFrag mem_frag,
3904 X86MemOperand x86memop, Domain d> {
3905 let hasSideEffects = 0 in {
3906 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3907 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3909 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3910 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3911 [], d>, EVEX, EVEX_B, EVEX_RC;
3913 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3914 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3916 } // hasSideEffects = 0
3919 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3920 memopv16f32, f512mem, SSEPackedSingle>, PD,
3921 EVEX_V512, EVEX_CD8<32, CD8VF>;
3922 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3923 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3924 EVEX_V512, EVEX_CD8<64, CD8VF>;
3926 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3927 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3928 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3930 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3931 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3932 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3934 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3935 memopv16f32, f512mem, SSEPackedSingle>,
3936 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3937 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3938 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3939 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3941 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3942 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3943 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3945 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3946 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3947 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3949 let Predicates = [HasAVX512] in {
3950 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3951 (VCVTPD2PSZrm addr:$src)>;
3952 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3953 (VCVTPS2PDZrm addr:$src)>;
3956 //===----------------------------------------------------------------------===//
3957 // Half precision conversion instructions
3958 //===----------------------------------------------------------------------===//
3959 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3960 X86MemOperand x86memop> {
3961 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3962 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3964 let hasSideEffects = 0, mayLoad = 1 in
3965 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3966 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3969 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3970 X86MemOperand x86memop> {
3971 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3972 (ins srcRC:$src1, i32i8imm:$src2),
3973 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3975 let hasSideEffects = 0, mayStore = 1 in
3976 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3977 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3978 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3981 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3982 EVEX_CD8<32, CD8VH>;
3983 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3984 EVEX_CD8<32, CD8VH>;
3986 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3987 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3988 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3990 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3991 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3992 (VCVTPH2PSZrr VR256X:$src)>;
3994 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3995 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3996 "ucomiss">, PS, EVEX, VEX_LIG,
3997 EVEX_CD8<32, CD8VT1>;
3998 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3999 "ucomisd">, PD, EVEX,
4000 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4001 let Pattern = []<dag> in {
4002 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4003 "comiss">, PS, EVEX, VEX_LIG,
4004 EVEX_CD8<32, CD8VT1>;
4005 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4006 "comisd">, PD, EVEX,
4007 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4009 let isCodeGenOnly = 1 in {
4010 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4011 load, "ucomiss">, PS, EVEX, VEX_LIG,
4012 EVEX_CD8<32, CD8VT1>;
4013 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4014 load, "ucomisd">, PD, EVEX,
4015 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4017 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4018 load, "comiss">, PS, EVEX, VEX_LIG,
4019 EVEX_CD8<32, CD8VT1>;
4020 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4021 load, "comisd">, PD, EVEX,
4022 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4026 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4027 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4028 X86MemOperand x86memop> {
4029 let hasSideEffects = 0 in {
4030 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4031 (ins RC:$src1, RC:$src2),
4032 !strconcat(OpcodeStr,
4033 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4034 let mayLoad = 1 in {
4035 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4036 (ins RC:$src1, x86memop:$src2),
4037 !strconcat(OpcodeStr,
4038 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4043 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4044 EVEX_CD8<32, CD8VT1>;
4045 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4046 VEX_W, EVEX_CD8<64, CD8VT1>;
4047 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4048 EVEX_CD8<32, CD8VT1>;
4049 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4050 VEX_W, EVEX_CD8<64, CD8VT1>;
4052 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4053 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4054 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4055 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4057 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4058 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4059 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4060 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4062 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4063 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4064 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4065 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4067 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4068 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4069 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4070 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4072 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4073 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4074 X86VectorVTInfo _> {
4075 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4076 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4077 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4078 let mayLoad = 1 in {
4079 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4080 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4082 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4083 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4084 (ins _.ScalarMemOp:$src), OpcodeStr,
4085 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4087 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4092 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4093 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4094 EVEX_V512, EVEX_CD8<32, CD8VF>;
4095 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4096 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4098 // Define only if AVX512VL feature is present.
4099 let Predicates = [HasVLX] in {
4100 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4101 OpNode, v4f32x_info>,
4102 EVEX_V128, EVEX_CD8<32, CD8VF>;
4103 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4104 OpNode, v8f32x_info>,
4105 EVEX_V256, EVEX_CD8<32, CD8VF>;
4106 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4107 OpNode, v2f64x_info>,
4108 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4109 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4110 OpNode, v4f64x_info>,
4111 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4115 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4116 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4118 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4119 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4120 (VRSQRT14PSZr VR512:$src)>;
4121 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4122 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4123 (VRSQRT14PDZr VR512:$src)>;
4125 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4126 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4127 (VRCP14PSZr VR512:$src)>;
4128 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4129 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4130 (VRCP14PDZr VR512:$src)>;
4132 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4133 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4134 X86MemOperand x86memop> {
4135 let hasSideEffects = 0, Predicates = [HasERI] in {
4136 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4137 (ins RC:$src1, RC:$src2),
4138 !strconcat(OpcodeStr,
4139 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4140 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4141 (ins RC:$src1, RC:$src2),
4142 !strconcat(OpcodeStr,
4143 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
4144 []>, EVEX_4V, EVEX_B;
4145 let mayLoad = 1 in {
4146 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4147 (ins RC:$src1, x86memop:$src2),
4148 !strconcat(OpcodeStr,
4149 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4154 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4155 EVEX_CD8<32, CD8VT1>;
4156 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4157 VEX_W, EVEX_CD8<64, CD8VT1>;
4158 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4159 EVEX_CD8<32, CD8VT1>;
4160 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4161 VEX_W, EVEX_CD8<64, CD8VT1>;
4163 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4164 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4166 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4167 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4169 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4170 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4172 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4173 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4175 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4176 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4178 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4179 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4181 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4182 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4184 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4185 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4187 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4189 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4192 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4193 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4194 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4196 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4197 (ins _.RC:$src), OpcodeStr,
4199 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4201 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4202 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4204 (bitconvert (_.LdFrag addr:$src))), (i32 FROUND_CURRENT))>;
4206 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4207 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4209 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4210 (i32 FROUND_CURRENT))>, EVEX_B;
4213 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4214 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4215 EVEX_CD8<32, CD8VF>;
4216 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4217 VEX_W, EVEX_CD8<32, CD8VF>;
4220 let Predicates = [HasERI], hasSideEffects = 0 in {
4222 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4223 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4224 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4227 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4228 SDNode OpNode, X86VectorVTInfo _>{
4229 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4230 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4231 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4232 let mayLoad = 1 in {
4233 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4234 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4236 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4238 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4239 (ins _.ScalarMemOp:$src), OpcodeStr,
4240 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4242 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4247 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4248 Intrinsic F32Int, Intrinsic F64Int,
4249 OpndItins itins_s, OpndItins itins_d> {
4250 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4251 (ins FR32X:$src1, FR32X:$src2),
4252 !strconcat(OpcodeStr,
4253 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4254 [], itins_s.rr>, XS, EVEX_4V;
4255 let isCodeGenOnly = 1 in
4256 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4257 (ins VR128X:$src1, VR128X:$src2),
4258 !strconcat(OpcodeStr,
4259 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4261 (F32Int VR128X:$src1, VR128X:$src2))],
4262 itins_s.rr>, XS, EVEX_4V;
4263 let mayLoad = 1 in {
4264 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4265 (ins FR32X:$src1, f32mem:$src2),
4266 !strconcat(OpcodeStr,
4267 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4268 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4269 let isCodeGenOnly = 1 in
4270 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4271 (ins VR128X:$src1, ssmem:$src2),
4272 !strconcat(OpcodeStr,
4273 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4275 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4276 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4278 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4279 (ins FR64X:$src1, FR64X:$src2),
4280 !strconcat(OpcodeStr,
4281 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4283 let isCodeGenOnly = 1 in
4284 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4285 (ins VR128X:$src1, VR128X:$src2),
4286 !strconcat(OpcodeStr,
4287 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4289 (F64Int VR128X:$src1, VR128X:$src2))],
4290 itins_s.rr>, XD, EVEX_4V, VEX_W;
4291 let mayLoad = 1 in {
4292 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4293 (ins FR64X:$src1, f64mem:$src2),
4294 !strconcat(OpcodeStr,
4295 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4296 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4297 let isCodeGenOnly = 1 in
4298 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4299 (ins VR128X:$src1, sdmem:$src2),
4300 !strconcat(OpcodeStr,
4301 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4303 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4304 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4308 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4310 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4312 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4313 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4315 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4316 // Define only if AVX512VL feature is present.
4317 let Predicates = [HasVLX] in {
4318 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4319 OpNode, v4f32x_info>,
4320 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4321 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4322 OpNode, v8f32x_info>,
4323 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4324 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4325 OpNode, v2f64x_info>,
4326 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4327 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4328 OpNode, v4f64x_info>,
4329 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4333 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4335 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4336 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4337 SSE_SQRTSS, SSE_SQRTSD>;
4339 let Predicates = [HasAVX512] in {
4340 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4341 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4342 (VSQRTPSZr VR512:$src1)>;
4343 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4344 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4345 (VSQRTPDZr VR512:$src1)>;
4347 def : Pat<(f32 (fsqrt FR32X:$src)),
4348 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4349 def : Pat<(f32 (fsqrt (load addr:$src))),
4350 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4351 Requires<[OptForSize]>;
4352 def : Pat<(f64 (fsqrt FR64X:$src)),
4353 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4354 def : Pat<(f64 (fsqrt (load addr:$src))),
4355 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4356 Requires<[OptForSize]>;
4358 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4359 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4360 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4361 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4362 Requires<[OptForSize]>;
4364 def : Pat<(f32 (X86frcp FR32X:$src)),
4365 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4366 def : Pat<(f32 (X86frcp (load addr:$src))),
4367 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4368 Requires<[OptForSize]>;
4370 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4371 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4372 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4374 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4375 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4377 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4378 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4379 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4381 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4382 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4386 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4387 X86MemOperand x86memop, RegisterClass RC,
4388 PatFrag mem_frag32, PatFrag mem_frag64,
4389 Intrinsic V4F32Int, Intrinsic V2F64Int,
4391 let ExeDomain = SSEPackedSingle in {
4392 // Intrinsic operation, reg.
4393 // Vector intrinsic operation, reg
4394 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4395 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4396 !strconcat(OpcodeStr,
4397 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4398 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4400 // Vector intrinsic operation, mem
4401 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4402 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4403 !strconcat(OpcodeStr,
4404 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4406 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4407 EVEX_CD8<32, VForm>;
4408 } // ExeDomain = SSEPackedSingle
4410 let ExeDomain = SSEPackedDouble in {
4411 // Vector intrinsic operation, reg
4412 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4413 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4414 !strconcat(OpcodeStr,
4415 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4416 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4418 // Vector intrinsic operation, mem
4419 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4420 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4421 !strconcat(OpcodeStr,
4422 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4424 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4425 EVEX_CD8<64, VForm>;
4426 } // ExeDomain = SSEPackedDouble
4429 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4433 let ExeDomain = GenericDomain in {
4435 let hasSideEffects = 0 in
4436 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4437 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4438 !strconcat(OpcodeStr,
4439 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4442 // Intrinsic operation, reg.
4443 let isCodeGenOnly = 1 in
4444 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4445 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4446 !strconcat(OpcodeStr,
4447 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4448 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4450 // Intrinsic operation, mem.
4451 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4452 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4453 !strconcat(OpcodeStr,
4454 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4455 [(set VR128X:$dst, (F32Int VR128X:$src1,
4456 sse_load_f32:$src2, imm:$src3))]>,
4457 EVEX_CD8<32, CD8VT1>;
4460 let hasSideEffects = 0 in
4461 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4462 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4463 !strconcat(OpcodeStr,
4464 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4467 // Intrinsic operation, reg.
4468 let isCodeGenOnly = 1 in
4469 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4470 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4471 !strconcat(OpcodeStr,
4472 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4473 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4476 // Intrinsic operation, mem.
4477 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4478 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4479 !strconcat(OpcodeStr,
4480 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4482 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4483 VEX_W, EVEX_CD8<64, CD8VT1>;
4484 } // ExeDomain = GenericDomain
4487 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4488 X86MemOperand x86memop, RegisterClass RC,
4489 PatFrag mem_frag, Domain d> {
4490 let ExeDomain = d in {
4491 // Intrinsic operation, reg.
4492 // Vector intrinsic operation, reg
4493 def r : AVX512AIi8<opc, MRMSrcReg,
4494 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4495 !strconcat(OpcodeStr,
4496 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4499 // Vector intrinsic operation, mem
4500 def m : AVX512AIi8<opc, MRMSrcMem,
4501 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4502 !strconcat(OpcodeStr,
4503 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4509 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4510 memopv16f32, SSEPackedSingle>, EVEX_V512,
4511 EVEX_CD8<32, CD8VF>;
4513 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4514 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4516 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4519 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4520 memopv8f64, SSEPackedDouble>, EVEX_V512,
4521 VEX_W, EVEX_CD8<64, CD8VF>;
4523 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4524 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4526 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4528 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4529 Operand x86memop, RegisterClass RC, Domain d> {
4530 let ExeDomain = d in {
4531 def r : AVX512AIi8<opc, MRMSrcReg,
4532 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4533 !strconcat(OpcodeStr,
4534 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4537 def m : AVX512AIi8<opc, MRMSrcMem,
4538 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4539 !strconcat(OpcodeStr,
4540 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4545 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4546 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4548 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4549 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4551 def : Pat<(ffloor FR32X:$src),
4552 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4553 def : Pat<(f64 (ffloor FR64X:$src)),
4554 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4555 def : Pat<(f32 (fnearbyint FR32X:$src)),
4556 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4557 def : Pat<(f64 (fnearbyint FR64X:$src)),
4558 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4559 def : Pat<(f32 (fceil FR32X:$src)),
4560 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4561 def : Pat<(f64 (fceil FR64X:$src)),
4562 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4563 def : Pat<(f32 (frint FR32X:$src)),
4564 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4565 def : Pat<(f64 (frint FR64X:$src)),
4566 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4567 def : Pat<(f32 (ftrunc FR32X:$src)),
4568 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4569 def : Pat<(f64 (ftrunc FR64X:$src)),
4570 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4572 def : Pat<(v16f32 (ffloor VR512:$src)),
4573 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4574 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4575 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4576 def : Pat<(v16f32 (fceil VR512:$src)),
4577 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4578 def : Pat<(v16f32 (frint VR512:$src)),
4579 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4580 def : Pat<(v16f32 (ftrunc VR512:$src)),
4581 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4583 def : Pat<(v8f64 (ffloor VR512:$src)),
4584 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4585 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4586 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4587 def : Pat<(v8f64 (fceil VR512:$src)),
4588 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4589 def : Pat<(v8f64 (frint VR512:$src)),
4590 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4591 def : Pat<(v8f64 (ftrunc VR512:$src)),
4592 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4594 //-------------------------------------------------
4595 // Integer truncate and extend operations
4596 //-------------------------------------------------
4598 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4599 RegisterClass dstRC, RegisterClass srcRC,
4600 RegisterClass KRC, X86MemOperand x86memop> {
4601 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4603 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4606 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4607 (ins KRC:$mask, srcRC:$src),
4608 !strconcat(OpcodeStr,
4609 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4612 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4613 (ins KRC:$mask, srcRC:$src),
4614 !strconcat(OpcodeStr,
4615 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4618 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4619 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4622 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4623 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4624 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4628 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4629 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4630 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4631 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4632 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4633 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4634 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4635 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4636 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4637 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4638 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4639 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4640 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4641 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4642 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4643 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4644 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4645 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4646 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4647 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4648 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4649 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4650 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4651 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4652 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4653 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4654 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4655 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4656 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4657 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4659 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4660 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4661 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4662 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4663 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4665 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4666 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4667 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4668 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4669 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4670 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4671 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4672 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4675 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4676 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4677 PatFrag mem_frag, X86MemOperand x86memop,
4678 ValueType OpVT, ValueType InVT> {
4680 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4682 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4683 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4685 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4686 (ins KRC:$mask, SrcRC:$src),
4687 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4690 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4691 (ins KRC:$mask, SrcRC:$src),
4692 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4695 let mayLoad = 1 in {
4696 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4697 (ins x86memop:$src),
4698 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4700 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4703 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4704 (ins KRC:$mask, x86memop:$src),
4705 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4709 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4710 (ins KRC:$mask, x86memop:$src),
4711 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4717 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4718 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4720 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4721 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4723 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4724 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4725 EVEX_CD8<16, CD8VH>;
4726 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4727 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4728 EVEX_CD8<16, CD8VQ>;
4729 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4730 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4731 EVEX_CD8<32, CD8VH>;
4733 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4734 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4736 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4737 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4739 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4740 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4741 EVEX_CD8<16, CD8VH>;
4742 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4743 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4744 EVEX_CD8<16, CD8VQ>;
4745 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4746 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4747 EVEX_CD8<32, CD8VH>;
4749 //===----------------------------------------------------------------------===//
4750 // GATHER - SCATTER Operations
4752 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4753 RegisterClass RC, X86MemOperand memop> {
4755 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4756 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4757 (ins RC:$src1, KRC:$mask, memop:$src2),
4758 !strconcat(OpcodeStr,
4759 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4763 let ExeDomain = SSEPackedDouble in {
4764 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4765 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4766 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4767 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4770 let ExeDomain = SSEPackedSingle in {
4771 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4772 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4773 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4774 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4777 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4778 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4779 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4780 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4782 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4783 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4784 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4785 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4787 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4788 RegisterClass RC, X86MemOperand memop> {
4789 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4790 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4791 (ins memop:$dst, KRC:$mask, RC:$src2),
4792 !strconcat(OpcodeStr,
4793 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4797 let ExeDomain = SSEPackedDouble in {
4798 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4799 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4800 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4801 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4804 let ExeDomain = SSEPackedSingle in {
4805 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4806 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4807 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4808 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4811 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4812 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4813 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4814 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4816 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4817 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4818 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4819 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4822 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4823 RegisterClass KRC, X86MemOperand memop> {
4824 let Predicates = [HasPFI], hasSideEffects = 1 in
4825 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4826 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4830 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4831 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4833 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4834 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4836 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4837 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4839 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4840 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4842 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4843 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4845 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4846 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4848 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4849 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4851 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4852 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4854 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4855 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4857 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4858 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4860 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4861 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4863 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4864 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4866 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4867 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4869 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4870 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4872 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4873 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4875 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4876 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4877 //===----------------------------------------------------------------------===//
4878 // VSHUFPS - VSHUFPD Operations
4880 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4881 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4883 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4884 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4885 !strconcat(OpcodeStr,
4886 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4887 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4888 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4889 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4890 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4891 (ins RC:$src1, RC:$src2, i8imm:$src3),
4892 !strconcat(OpcodeStr,
4893 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4894 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4895 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4896 EVEX_4V, Sched<[WriteShuffle]>;
4899 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4900 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4901 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4902 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4904 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4905 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4906 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4907 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4908 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4910 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4911 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4912 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4913 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4914 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4916 multiclass avx512_valign<X86VectorVTInfo _> {
4917 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4918 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4920 "$src3, $src2, $src1", "$src1, $src2, $src3",
4921 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4923 AVX512AIi8Base, EVEX_4V;
4925 // Also match valign of packed floats.
4926 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4927 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4930 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4931 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4932 !strconcat("valign"##_.Suffix,
4933 " \t{$src3, $src2, $src1, $dst|"
4934 "$dst, $src1, $src2, $src3}"),
4937 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4938 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4940 // Helper fragments to match sext vXi1 to vXiY.
4941 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4942 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4944 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4945 RegisterClass KRC, RegisterClass RC,
4946 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4948 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4949 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4951 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4952 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4954 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4955 !strconcat(OpcodeStr,
4956 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4958 let mayLoad = 1 in {
4959 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4960 (ins x86memop:$src),
4961 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4963 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4964 (ins KRC:$mask, x86memop:$src),
4965 !strconcat(OpcodeStr,
4966 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4968 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4969 (ins KRC:$mask, x86memop:$src),
4970 !strconcat(OpcodeStr,
4971 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4973 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4974 (ins x86scalar_mop:$src),
4975 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4976 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4978 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4979 (ins KRC:$mask, x86scalar_mop:$src),
4980 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4981 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4982 []>, EVEX, EVEX_B, EVEX_K;
4983 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4984 (ins KRC:$mask, x86scalar_mop:$src),
4985 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4986 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4988 []>, EVEX, EVEX_B, EVEX_KZ;
4992 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4993 i512mem, i32mem, "{1to16}">, EVEX_V512,
4994 EVEX_CD8<32, CD8VF>;
4995 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4996 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4997 EVEX_CD8<64, CD8VF>;
5000 (bc_v16i32 (v16i1sextv16i32)),
5001 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5002 (VPABSDZrr VR512:$src)>;
5004 (bc_v8i64 (v8i1sextv8i64)),
5005 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5006 (VPABSQZrr VR512:$src)>;
5008 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5009 (v16i32 immAllZerosV), (i16 -1))),
5010 (VPABSDZrr VR512:$src)>;
5011 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5012 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5013 (VPABSQZrr VR512:$src)>;
5015 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5016 RegisterClass RC, RegisterClass KRC,
5017 X86MemOperand x86memop,
5018 X86MemOperand x86scalar_mop, string BrdcstStr> {
5019 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5021 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
5023 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5024 (ins x86memop:$src),
5025 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
5027 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5028 (ins x86scalar_mop:$src),
5029 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5030 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5032 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5033 (ins KRC:$mask, RC:$src),
5034 !strconcat(OpcodeStr,
5035 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5037 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5038 (ins KRC:$mask, x86memop:$src),
5039 !strconcat(OpcodeStr,
5040 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5042 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5043 (ins KRC:$mask, x86scalar_mop:$src),
5044 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5045 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5047 []>, EVEX, EVEX_KZ, EVEX_B;
5049 let Constraints = "$src1 = $dst" in {
5050 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5051 (ins RC:$src1, KRC:$mask, RC:$src2),
5052 !strconcat(OpcodeStr,
5053 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5055 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5056 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5057 !strconcat(OpcodeStr,
5058 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5060 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5061 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5062 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
5063 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5064 []>, EVEX, EVEX_K, EVEX_B;
5068 let Predicates = [HasCDI] in {
5069 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5070 i512mem, i32mem, "{1to16}">,
5071 EVEX_V512, EVEX_CD8<32, CD8VF>;
5074 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5075 i512mem, i64mem, "{1to8}">,
5076 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5080 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5082 (VPCONFLICTDrrk VR512:$src1,
5083 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5085 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5087 (VPCONFLICTQrrk VR512:$src1,
5088 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5090 let Predicates = [HasCDI] in {
5091 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5092 i512mem, i32mem, "{1to16}">,
5093 EVEX_V512, EVEX_CD8<32, CD8VF>;
5096 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5097 i512mem, i64mem, "{1to8}">,
5098 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5102 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5104 (VPLZCNTDrrk VR512:$src1,
5105 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5107 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5109 (VPLZCNTQrrk VR512:$src1,
5110 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5112 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5113 (VPLZCNTDrm addr:$src)>;
5114 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5115 (VPLZCNTDrr VR512:$src)>;
5116 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5117 (VPLZCNTQrm addr:$src)>;
5118 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5119 (VPLZCNTQrr VR512:$src)>;
5121 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5122 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5123 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5125 def : Pat<(store VK1:$src, addr:$dst),
5126 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5128 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5129 (truncstore node:$val, node:$ptr), [{
5130 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5133 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5134 (MOV8mr addr:$dst, GR8:$src)>;
5136 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5137 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5138 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
5139 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5142 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5143 string OpcodeStr, Predicate prd> {
5144 let Predicates = [prd] in
5145 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5147 let Predicates = [prd, HasVLX] in {
5148 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5149 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5153 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5154 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5156 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5158 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5160 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5164 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;