1 multiclass AVX512_masking<bits<8> O, Format F, dag Outs, dag Ins,
3 string AttSrcAsm, string IntelSrcAsm,
4 dag RHS, ValueType OpVT,
5 RegisterClass RC, RegisterClass KRC> {
6 def NAME: AVX512<O, F, Outs, Ins,
7 OpcodeStr#" \t{"#AttSrcAsm#", $dst|"#
8 "$dst, "#IntelSrcAsm#"}",
11 // Prefer over VMOV*rrk Pat<>
12 let Constraints = "$src0 = $dst", AddedComplexity = 20 in
13 def NAME#k: AVX512<O, F, Outs,
14 !con((ins RC:$src0, KRC:$mask), Ins),
15 OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}}|"#
16 "$dst {${mask}}, "#IntelSrcAsm#"}",
18 (vselect KRC:$mask, RHS, RC:$src0))]>,
20 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
21 def NAME#kz: AVX512<O, F, Outs,
22 !con((ins KRC:$mask), Ins),
23 OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
24 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
26 (vselect KRC:$mask, RHS,
28 (v16i32 immAllZerosV)))))]>,
32 // Bitcasts between 512-bit vector types. Return the original type since
33 // no instruction is needed for the conversion
34 let Predicates = [HasAVX512] in {
35 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
36 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
37 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
38 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
39 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
40 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
41 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
42 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
43 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
44 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
45 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
46 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
47 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
48 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
49 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
50 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
51 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
52 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
53 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
54 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
55 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
56 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
57 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
58 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
59 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
60 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
61 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
62 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
63 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
64 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
66 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
67 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
68 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
69 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
70 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
71 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
72 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
73 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
74 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
75 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
76 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
77 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
78 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
79 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
80 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
81 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
82 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
83 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
84 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
85 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
86 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
87 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
88 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
89 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
90 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
91 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
92 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
93 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
94 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
95 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
97 // Bitcasts between 256-bit vector types. Return the original type since
98 // no instruction is needed for the conversion
99 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
100 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
101 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
102 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
103 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
104 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
105 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
106 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
107 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
108 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
109 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
110 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
111 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
112 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
113 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
114 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
115 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
116 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
117 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
118 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
119 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
120 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
121 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
122 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
123 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
124 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
125 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
126 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
127 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
128 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
132 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
135 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
136 isPseudo = 1, Predicates = [HasAVX512] in {
137 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
138 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
141 let Predicates = [HasAVX512] in {
142 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
143 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
144 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
147 //===----------------------------------------------------------------------===//
148 // AVX-512 - VECTOR INSERT
151 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
152 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
153 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
154 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
155 []>, EVEX_4V, EVEX_V512;
157 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
158 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
159 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
160 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
163 // -- 64x4 fp form --
164 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
165 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
166 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
167 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
168 []>, EVEX_4V, EVEX_V512, VEX_W;
170 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
171 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
172 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
173 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
175 // -- 32x4 integer form --
176 let hasSideEffects = 0 in {
177 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
178 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
179 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
180 []>, EVEX_4V, EVEX_V512;
182 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
183 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
184 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
185 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
188 let hasSideEffects = 0 in {
190 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
191 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
192 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
193 []>, EVEX_4V, EVEX_V512, VEX_W;
195 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
196 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
197 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
198 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
201 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
202 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
203 (INSERT_get_vinsert128_imm VR512:$ins))>;
204 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
205 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
206 (INSERT_get_vinsert128_imm VR512:$ins))>;
207 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
208 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
209 (INSERT_get_vinsert128_imm VR512:$ins))>;
210 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
211 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
212 (INSERT_get_vinsert128_imm VR512:$ins))>;
214 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
215 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
216 (INSERT_get_vinsert128_imm VR512:$ins))>;
217 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
218 (bc_v4i32 (loadv2i64 addr:$src2)),
219 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
220 (INSERT_get_vinsert128_imm VR512:$ins))>;
221 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
222 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
223 (INSERT_get_vinsert128_imm VR512:$ins))>;
224 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
225 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
226 (INSERT_get_vinsert128_imm VR512:$ins))>;
228 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
229 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
230 (INSERT_get_vinsert256_imm VR512:$ins))>;
231 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
232 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
233 (INSERT_get_vinsert256_imm VR512:$ins))>;
234 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
235 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
236 (INSERT_get_vinsert256_imm VR512:$ins))>;
237 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
238 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
239 (INSERT_get_vinsert256_imm VR512:$ins))>;
241 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
242 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
243 (INSERT_get_vinsert256_imm VR512:$ins))>;
244 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
245 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
246 (INSERT_get_vinsert256_imm VR512:$ins))>;
247 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
248 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
249 (INSERT_get_vinsert256_imm VR512:$ins))>;
250 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
251 (bc_v8i32 (loadv4i64 addr:$src2)),
252 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
253 (INSERT_get_vinsert256_imm VR512:$ins))>;
255 // vinsertps - insert f32 to XMM
256 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
257 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
258 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
259 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
261 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
262 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
263 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
264 [(set VR128X:$dst, (X86insertps VR128X:$src1,
265 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
266 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
268 //===----------------------------------------------------------------------===//
269 // AVX-512 VECTOR EXTRACT
271 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
273 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
274 (ins VR512:$src1, i8imm:$src2),
275 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
276 []>, EVEX, EVEX_V512;
277 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
278 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
279 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
280 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
283 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
284 (ins VR512:$src1, i8imm:$src2),
285 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
286 []>, EVEX, EVEX_V512, VEX_W;
288 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
289 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
290 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
291 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
294 let hasSideEffects = 0 in {
296 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
297 (ins VR512:$src1, i8imm:$src2),
298 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
299 []>, EVEX, EVEX_V512;
300 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
301 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
302 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
303 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
306 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
307 (ins VR512:$src1, i8imm:$src2),
308 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
309 []>, EVEX, EVEX_V512, VEX_W;
311 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
312 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
313 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
314 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
317 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
318 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
319 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
321 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
322 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
323 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
325 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
326 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
327 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
329 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
330 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
331 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
334 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
335 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
336 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
338 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
339 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
340 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
342 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
343 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
344 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
346 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
347 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
348 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
350 // A 256-bit subvector extract from the first 512-bit vector position
351 // is a subregister copy that needs no instruction.
352 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
353 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
354 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
355 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
356 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
357 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
358 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
359 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
362 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
363 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
364 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
365 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
366 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
367 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
368 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
369 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
372 // A 128-bit subvector insert to the first 512-bit vector position
373 // is a subregister copy that needs no instruction.
374 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
375 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
376 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
378 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
379 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
380 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
382 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
383 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
384 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
386 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
387 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
388 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
391 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
392 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
393 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
394 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
395 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
396 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
397 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
398 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
400 // vextractps - extract 32 bits from XMM
401 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
402 (ins VR128X:$src1, u32u8imm:$src2),
403 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
404 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
407 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
408 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
409 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
410 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
411 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
413 //===---------------------------------------------------------------------===//
416 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
417 RegisterClass DestRC,
418 RegisterClass SrcRC, X86MemOperand x86memop> {
419 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
420 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
422 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
423 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
425 let ExeDomain = SSEPackedSingle in {
426 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
428 EVEX_V512, EVEX_CD8<32, CD8VT1>;
431 let ExeDomain = SSEPackedDouble in {
432 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
434 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
437 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
438 (VBROADCASTSSZrm addr:$src)>;
439 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
440 (VBROADCASTSDZrm addr:$src)>;
442 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
443 (VBROADCASTSSZrm addr:$src)>;
444 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
445 (VBROADCASTSDZrm addr:$src)>;
447 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
448 RegisterClass SrcRC, RegisterClass KRC> {
449 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
450 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
451 []>, EVEX, EVEX_V512;
452 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
453 (ins KRC:$mask, SrcRC:$src),
454 !strconcat(OpcodeStr,
455 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
456 []>, EVEX, EVEX_V512, EVEX_KZ;
459 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
460 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
463 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
464 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
466 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
467 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
469 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
470 (VPBROADCASTDrZrr GR32:$src)>;
471 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
472 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
473 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
474 (VPBROADCASTQrZrr GR64:$src)>;
475 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
476 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
478 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
479 (VPBROADCASTDrZrr GR32:$src)>;
480 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
481 (VPBROADCASTQrZrr GR64:$src)>;
483 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
484 (v16i32 immAllZerosV), (i16 GR16:$mask))),
485 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
486 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
487 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
488 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
490 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
491 X86MemOperand x86memop, PatFrag ld_frag,
492 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
494 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
495 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
497 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
498 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
500 !strconcat(OpcodeStr,
501 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
503 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
506 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
507 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
509 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
510 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
512 !strconcat(OpcodeStr,
513 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
514 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
515 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
519 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
520 loadi32, VR512, v16i32, v4i32, VK16WM>,
521 EVEX_V512, EVEX_CD8<32, CD8VT1>;
522 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
523 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
524 EVEX_CD8<64, CD8VT1>;
526 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
527 X86MemOperand x86memop, PatFrag ld_frag,
530 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
531 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
533 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
535 !strconcat(OpcodeStr,
536 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
541 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
542 i128mem, loadv2i64, VK16WM>,
543 EVEX_V512, EVEX_CD8<32, CD8VT4>;
544 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
545 i256mem, loadv4i64, VK16WM>, VEX_W,
546 EVEX_V512, EVEX_CD8<64, CD8VT4>;
548 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
549 (VPBROADCASTDZrr VR128X:$src)>;
550 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
551 (VPBROADCASTQZrr VR128X:$src)>;
553 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
554 (VBROADCASTSSZrr VR128X:$src)>;
555 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
556 (VBROADCASTSDZrr VR128X:$src)>;
558 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
559 (VBROADCASTSSZrr VR128X:$src)>;
560 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
561 (VBROADCASTSDZrr VR128X:$src)>;
563 // Provide fallback in case the load node that is used in the patterns above
564 // is used by additional users, which prevents the pattern selection.
565 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
566 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
567 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
568 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
571 let Predicates = [HasAVX512] in {
572 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
574 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
575 addr:$src)), sub_ymm)>;
577 //===----------------------------------------------------------------------===//
578 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
581 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
582 RegisterClass DstRC, RegisterClass KRC,
583 ValueType OpVT, ValueType SrcVT> {
584 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
585 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
589 let Predicates = [HasCDI] in {
590 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
591 VK16, v16i32, v16i1>, EVEX_V512;
592 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
593 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
596 //===----------------------------------------------------------------------===//
599 // -- immediate form --
600 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
601 SDNode OpNode, PatFrag mem_frag,
602 X86MemOperand x86memop, ValueType OpVT> {
603 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
604 (ins RC:$src1, i8imm:$src2),
605 !strconcat(OpcodeStr,
606 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
608 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
610 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
611 (ins x86memop:$src1, i8imm:$src2),
612 !strconcat(OpcodeStr,
613 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
615 (OpVT (OpNode (mem_frag addr:$src1),
616 (i8 imm:$src2))))]>, EVEX;
619 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
620 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
621 let ExeDomain = SSEPackedDouble in
622 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
623 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
625 // -- VPERM - register form --
626 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
627 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
629 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
630 (ins RC:$src1, RC:$src2),
631 !strconcat(OpcodeStr,
632 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
634 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
636 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
637 (ins RC:$src1, x86memop:$src2),
638 !strconcat(OpcodeStr,
639 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
641 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
645 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
646 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
647 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
648 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
649 let ExeDomain = SSEPackedSingle in
650 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
651 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
652 let ExeDomain = SSEPackedDouble in
653 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
654 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
656 // -- VPERM2I - 3 source operands form --
657 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
658 PatFrag mem_frag, X86MemOperand x86memop,
659 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
660 let Constraints = "$src1 = $dst" in {
661 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
662 (ins RC:$src1, RC:$src2, RC:$src3),
663 !strconcat(OpcodeStr,
664 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
666 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
669 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
670 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
671 !strconcat(OpcodeStr,
672 " \t{$src3, $src2, $dst {${mask}}|"
673 "$dst {${mask}}, $src2, $src3}"),
674 [(set RC:$dst, (OpVT (vselect KRC:$mask,
675 (OpNode RC:$src1, RC:$src2,
680 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
681 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
682 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
683 !strconcat(OpcodeStr,
684 " \t{$src3, $src2, $dst {${mask}} {z} |",
685 "$dst {${mask}} {z}, $src2, $src3}"),
686 [(set RC:$dst, (OpVT (vselect KRC:$mask,
687 (OpNode RC:$src1, RC:$src2,
690 (v16i32 immAllZerosV))))))]>,
693 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
694 (ins RC:$src1, RC:$src2, x86memop:$src3),
695 !strconcat(OpcodeStr,
696 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
698 (OpVT (OpNode RC:$src1, RC:$src2,
699 (mem_frag addr:$src3))))]>, EVEX_4V;
701 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
702 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
703 !strconcat(OpcodeStr,
704 " \t{$src3, $src2, $dst {${mask}}|"
705 "$dst {${mask}}, $src2, $src3}"),
707 (OpVT (vselect KRC:$mask,
708 (OpNode RC:$src1, RC:$src2,
709 (mem_frag addr:$src3)),
713 let AddedComplexity = 10 in // Prefer over the rrkz variant
714 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
715 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
716 !strconcat(OpcodeStr,
717 " \t{$src3, $src2, $dst {${mask}} {z}|"
718 "$dst {${mask}} {z}, $src2, $src3}"),
720 (OpVT (vselect KRC:$mask,
721 (OpNode RC:$src1, RC:$src2,
722 (mem_frag addr:$src3)),
724 (v16i32 immAllZerosV))))))]>,
728 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
729 i512mem, X86VPermiv3, v16i32, VK16WM>,
730 EVEX_V512, EVEX_CD8<32, CD8VF>;
731 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
732 i512mem, X86VPermiv3, v8i64, VK8WM>,
733 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
734 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
735 i512mem, X86VPermiv3, v16f32, VK16WM>,
736 EVEX_V512, EVEX_CD8<32, CD8VF>;
737 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
738 i512mem, X86VPermiv3, v8f64, VK8WM>,
739 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
741 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
742 PatFrag mem_frag, X86MemOperand x86memop,
743 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
744 ValueType MaskVT, RegisterClass MRC> :
745 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
747 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
748 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
749 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
751 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
752 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
753 (!cast<Instruction>(NAME#rrk) VR512:$src1,
754 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
757 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
758 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
759 EVEX_V512, EVEX_CD8<32, CD8VF>;
760 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
761 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
762 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
763 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
764 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
765 EVEX_V512, EVEX_CD8<32, CD8VF>;
766 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
767 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
768 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
770 //===----------------------------------------------------------------------===//
771 // AVX-512 - BLEND using mask
773 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
774 RegisterClass KRC, RegisterClass RC,
775 X86MemOperand x86memop, PatFrag mem_frag,
776 SDNode OpNode, ValueType vt> {
777 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
778 (ins KRC:$mask, RC:$src1, RC:$src2),
779 !strconcat(OpcodeStr,
780 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
781 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
782 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
784 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
785 (ins KRC:$mask, RC:$src1, x86memop:$src2),
786 !strconcat(OpcodeStr,
787 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
788 []>, EVEX_4V, EVEX_K;
791 let ExeDomain = SSEPackedSingle in
792 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
793 VK16WM, VR512, f512mem,
794 memopv16f32, vselect, v16f32>,
795 EVEX_CD8<32, CD8VF>, EVEX_V512;
796 let ExeDomain = SSEPackedDouble in
797 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
798 VK8WM, VR512, f512mem,
799 memopv8f64, vselect, v8f64>,
800 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
802 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
803 (v16f32 VR512:$src2), (i16 GR16:$mask))),
804 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
805 VR512:$src1, VR512:$src2)>;
807 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
808 (v8f64 VR512:$src2), (i8 GR8:$mask))),
809 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
810 VR512:$src1, VR512:$src2)>;
812 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
813 VK16WM, VR512, f512mem,
814 memopv16i32, vselect, v16i32>,
815 EVEX_CD8<32, CD8VF>, EVEX_V512;
817 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
818 VK8WM, VR512, f512mem,
819 memopv8i64, vselect, v8i64>,
820 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
822 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
823 (v16i32 VR512:$src2), (i16 GR16:$mask))),
824 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
825 VR512:$src1, VR512:$src2)>;
827 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
828 (v8i64 VR512:$src2), (i8 GR8:$mask))),
829 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
830 VR512:$src1, VR512:$src2)>;
832 let Predicates = [HasAVX512] in {
833 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
834 (v8f32 VR256X:$src2))),
836 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
837 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
838 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
840 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
841 (v8i32 VR256X:$src2))),
843 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
844 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
845 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
847 //===----------------------------------------------------------------------===//
848 // Compare Instructions
849 //===----------------------------------------------------------------------===//
851 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
852 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
853 Operand CC, SDNode OpNode, ValueType VT,
854 PatFrag ld_frag, string asm, string asm_alt> {
855 def rr : AVX512Ii8<0xC2, MRMSrcReg,
856 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
857 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
858 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
859 def rm : AVX512Ii8<0xC2, MRMSrcMem,
860 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
861 [(set VK1:$dst, (OpNode (VT RC:$src1),
862 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
863 let isAsmParserOnly = 1, hasSideEffects = 0 in {
864 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
865 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
866 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
867 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
868 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
869 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
873 let Predicates = [HasAVX512] in {
874 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
875 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
876 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
878 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
879 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
880 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
884 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
885 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
886 SDNode OpNode, ValueType vt> {
887 def rr : AVX512BI<opc, MRMSrcReg,
888 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
889 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
890 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
891 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
892 def rm : AVX512BI<opc, MRMSrcMem,
893 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
894 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
895 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
896 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
899 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
900 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
902 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
903 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
904 VEX_W, EVEX_CD8<64, CD8VF>;
906 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
907 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
909 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
910 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
911 VEX_W, EVEX_CD8<64, CD8VF>;
913 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
914 (COPY_TO_REGCLASS (VPCMPGTDZrr
915 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
916 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
918 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
919 (COPY_TO_REGCLASS (VPCMPEQDZrr
920 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
921 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
923 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass WMRC, RegisterClass KRC,
924 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
925 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
926 def rri : AVX512AIi8<opc, MRMSrcReg,
927 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
928 !strconcat("vpcmp${cc}", Suffix,
929 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
930 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
931 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
932 def rmi : AVX512AIi8<opc, MRMSrcMem,
933 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
934 !strconcat("vpcmp${cc}", Suffix,
935 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
936 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
937 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
938 // Accept explicit immediate argument form instead of comparison code.
939 let isAsmParserOnly = 1, hasSideEffects = 0 in {
940 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
941 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
942 !strconcat("vpcmp", Suffix,
943 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
944 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
945 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
946 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, RC:$src2, i8imm:$cc),
947 !strconcat("vpcmp", Suffix,
948 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
949 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
950 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
951 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
952 !strconcat("vpcmp", Suffix,
953 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
954 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
955 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
956 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, x86memop:$src2, i8imm:$cc),
957 !strconcat("vpcmp", Suffix,
958 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
959 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
963 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16WM, VK16, VR512, i512mem, memopv16i32,
964 X86cmpm, v16i32, AVXCC, "d">,
965 EVEX_V512, EVEX_CD8<32, CD8VF>;
966 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16WM, VK16, VR512, i512mem, memopv16i32,
967 X86cmpmu, v16i32, AVXCC, "ud">,
968 EVEX_V512, EVEX_CD8<32, CD8VF>;
970 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8WM, VK8, VR512, i512mem, memopv8i64,
971 X86cmpm, v8i64, AVXCC, "q">,
972 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
973 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8WM, VK8, VR512, i512mem, memopv8i64,
974 X86cmpmu, v8i64, AVXCC, "uq">,
975 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
977 // avx512_cmp_packed - compare packed instructions
978 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
979 X86MemOperand x86memop, ValueType vt,
980 string suffix, Domain d> {
981 def rri : AVX512PIi8<0xC2, MRMSrcReg,
982 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
983 !strconcat("vcmp${cc}", suffix,
984 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
985 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
986 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
987 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
988 !strconcat("vcmp${cc}", suffix,
989 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
991 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
992 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
993 !strconcat("vcmp${cc}", suffix,
994 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
996 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
998 // Accept explicit immediate argument form instead of comparison code.
999 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1000 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1001 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1002 !strconcat("vcmp", suffix,
1003 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1004 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1005 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1006 !strconcat("vcmp", suffix,
1007 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1011 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1012 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1013 EVEX_CD8<32, CD8VF>;
1014 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1015 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1016 EVEX_CD8<64, CD8VF>;
1018 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1019 (COPY_TO_REGCLASS (VCMPPSZrri
1020 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1021 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1023 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1024 (COPY_TO_REGCLASS (VPCMPDZrri
1025 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1026 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1028 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1029 (COPY_TO_REGCLASS (VPCMPUDZrri
1030 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1031 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1034 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1035 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1037 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1038 (I8Imm imm:$cc)), GR16)>;
1040 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1041 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1043 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1044 (I8Imm imm:$cc)), GR8)>;
1046 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1047 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1049 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1050 (I8Imm imm:$cc)), GR16)>;
1052 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1053 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1055 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1056 (I8Imm imm:$cc)), GR8)>;
1058 // Mask register copy, including
1059 // - copy between mask registers
1060 // - load/store mask registers
1061 // - copy from GPR to mask register and vice versa
1063 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1064 string OpcodeStr, RegisterClass KRC,
1065 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1066 let hasSideEffects = 0 in {
1067 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1068 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1070 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1071 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1072 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1074 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1075 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1079 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1081 RegisterClass KRC, RegisterClass GRC> {
1082 let hasSideEffects = 0 in {
1083 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1084 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1085 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1086 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1090 let Predicates = [HasDQI] in
1091 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1093 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1096 let Predicates = [HasAVX512] in
1097 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1099 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1102 let Predicates = [HasBWI] in {
1103 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1104 i32mem>, VEX, PD, VEX_W;
1105 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1109 let Predicates = [HasBWI] in {
1110 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1111 i64mem>, VEX, PS, VEX_W;
1112 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1116 // GR from/to mask register
1117 let Predicates = [HasDQI] in {
1118 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1119 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1120 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1121 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1123 let Predicates = [HasAVX512] in {
1124 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1125 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1126 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1127 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1129 let Predicates = [HasBWI] in {
1130 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1131 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1133 let Predicates = [HasBWI] in {
1134 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1135 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1139 let Predicates = [HasDQI] in {
1140 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1141 (KMOVBmk addr:$dst, VK8:$src)>;
1143 let Predicates = [HasAVX512] in {
1144 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1145 (KMOVWmk addr:$dst, VK16:$src)>;
1146 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1147 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1148 def : Pat<(i1 (load addr:$src)),
1149 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1150 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1151 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1153 let Predicates = [HasBWI] in {
1154 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1155 (KMOVDmk addr:$dst, VK32:$src)>;
1157 let Predicates = [HasBWI] in {
1158 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1159 (KMOVQmk addr:$dst, VK64:$src)>;
1162 let Predicates = [HasAVX512] in {
1163 def : Pat<(i1 (trunc (i32 GR32:$src))),
1164 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1166 def : Pat<(i1 (trunc (i8 GR8:$src))),
1168 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1170 def : Pat<(i1 (trunc (i16 GR16:$src))),
1172 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1175 def : Pat<(i32 (zext VK1:$src)),
1176 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1177 def : Pat<(i8 (zext VK1:$src)),
1180 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1181 def : Pat<(i64 (zext VK1:$src)),
1182 (AND64ri8 (SUBREG_TO_REG (i64 0),
1183 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1184 def : Pat<(i16 (zext VK1:$src)),
1186 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1188 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1189 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1190 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1191 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1193 let Predicates = [HasBWI] in {
1194 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1195 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1196 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1197 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1201 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1202 let Predicates = [HasAVX512] in {
1203 // GR from/to 8-bit mask without native support
1204 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1206 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1208 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1210 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1213 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1214 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1215 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1216 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1218 let Predicates = [HasBWI] in {
1219 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1220 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1221 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1222 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1225 // Mask unary operation
1227 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1228 RegisterClass KRC, SDPatternOperator OpNode,
1230 let Predicates = [prd] in
1231 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1232 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1233 [(set KRC:$dst, (OpNode KRC:$src))]>;
1236 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1237 SDPatternOperator OpNode> {
1238 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1240 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1241 HasAVX512>, VEX, PS;
1242 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1243 HasBWI>, VEX, PD, VEX_W;
1244 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1245 HasBWI>, VEX, PS, VEX_W;
1248 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1250 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1251 let Predicates = [HasAVX512] in
1252 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1254 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1255 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1257 defm : avx512_mask_unop_int<"knot", "KNOT">;
1259 let Predicates = [HasDQI] in
1260 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1261 let Predicates = [HasAVX512] in
1262 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1263 let Predicates = [HasBWI] in
1264 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1265 let Predicates = [HasBWI] in
1266 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1268 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1269 let Predicates = [HasAVX512] in {
1270 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1271 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1273 def : Pat<(not VK8:$src),
1275 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1278 // Mask binary operation
1279 // - KAND, KANDN, KOR, KXNOR, KXOR
1280 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1281 RegisterClass KRC, SDPatternOperator OpNode,
1283 let Predicates = [prd] in
1284 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1285 !strconcat(OpcodeStr,
1286 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1287 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1290 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1291 SDPatternOperator OpNode> {
1292 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1293 HasDQI>, VEX_4V, VEX_L, PD;
1294 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1295 HasAVX512>, VEX_4V, VEX_L, PS;
1296 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1297 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1298 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1299 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1302 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1303 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1305 let isCommutable = 1 in {
1306 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1307 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1308 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1309 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1311 let isCommutable = 0 in
1312 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1314 def : Pat<(xor VK1:$src1, VK1:$src2),
1315 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1316 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1318 def : Pat<(or VK1:$src1, VK1:$src2),
1319 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1320 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1322 def : Pat<(and VK1:$src1, VK1:$src2),
1323 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1324 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1326 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1327 let Predicates = [HasAVX512] in
1328 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1329 (i16 GR16:$src1), (i16 GR16:$src2)),
1330 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1331 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1332 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1335 defm : avx512_mask_binop_int<"kand", "KAND">;
1336 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1337 defm : avx512_mask_binop_int<"kor", "KOR">;
1338 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1339 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1341 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1342 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1343 let Predicates = [HasAVX512] in
1344 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1346 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1347 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1350 defm : avx512_binop_pat<and, KANDWrr>;
1351 defm : avx512_binop_pat<andn, KANDNWrr>;
1352 defm : avx512_binop_pat<or, KORWrr>;
1353 defm : avx512_binop_pat<xnor, KXNORWrr>;
1354 defm : avx512_binop_pat<xor, KXORWrr>;
1357 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1358 RegisterClass KRC> {
1359 let Predicates = [HasAVX512] in
1360 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1361 !strconcat(OpcodeStr,
1362 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1365 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1366 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1370 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1371 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1372 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1373 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1376 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1377 let Predicates = [HasAVX512] in
1378 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1379 (i16 GR16:$src1), (i16 GR16:$src2)),
1380 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1381 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1382 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1384 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1387 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1389 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1390 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1391 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1392 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1395 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1396 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1400 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1402 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1403 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1404 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1407 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1409 let Predicates = [HasAVX512] in
1410 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1411 !strconcat(OpcodeStr,
1412 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1413 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1416 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1418 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1422 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1423 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1425 // Mask setting all 0s or 1s
1426 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1427 let Predicates = [HasAVX512] in
1428 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1429 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1430 [(set KRC:$dst, (VT Val))]>;
1433 multiclass avx512_mask_setop_w<PatFrag Val> {
1434 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1435 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1438 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1439 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1441 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1442 let Predicates = [HasAVX512] in {
1443 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1444 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1445 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1446 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1447 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1449 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1450 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1452 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1453 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1455 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1456 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1458 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1459 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1461 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1462 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1463 //===----------------------------------------------------------------------===//
1464 // AVX-512 - Aligned and unaligned load and store
1467 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1468 RegisterClass KRC, RegisterClass RC,
1469 ValueType vt, ValueType zvt, X86MemOperand memop,
1470 Domain d, bit IsReMaterializable = 1> {
1471 let hasSideEffects = 0 in {
1472 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1473 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1475 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1476 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1477 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1479 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1480 SchedRW = [WriteLoad] in
1481 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1483 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1486 let AddedComplexity = 20 in {
1487 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1488 let hasSideEffects = 0 in
1489 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1490 (ins RC:$src0, KRC:$mask, RC:$src1),
1491 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1492 "${dst} {${mask}}, $src1}"),
1493 [(set RC:$dst, (vt (vselect KRC:$mask,
1497 let mayLoad = 1, SchedRW = [WriteLoad] in
1498 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1499 (ins RC:$src0, KRC:$mask, memop:$src1),
1500 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1501 "${dst} {${mask}}, $src1}"),
1504 (vt (bitconvert (ld_frag addr:$src1))),
1508 let mayLoad = 1, SchedRW = [WriteLoad] in
1509 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1510 (ins KRC:$mask, memop:$src),
1511 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1512 "${dst} {${mask}} {z}, $src}"),
1515 (vt (bitconvert (ld_frag addr:$src))),
1516 (vt (bitconvert (zvt immAllZerosV))))))],
1521 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1522 string elty, string elsz, string vsz512,
1523 string vsz256, string vsz128, Domain d,
1524 Predicate prd, bit IsReMaterializable = 1> {
1525 let Predicates = [prd] in
1526 defm Z : avx512_load<opc, OpcodeStr,
1527 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1528 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1529 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1530 !cast<X86MemOperand>(elty##"512mem"), d,
1531 IsReMaterializable>, EVEX_V512;
1533 let Predicates = [prd, HasVLX] in {
1534 defm Z256 : avx512_load<opc, OpcodeStr,
1535 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1536 "v"##vsz256##elty##elsz, "v4i64")),
1537 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1538 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1539 !cast<X86MemOperand>(elty##"256mem"), d,
1540 IsReMaterializable>, EVEX_V256;
1542 defm Z128 : avx512_load<opc, OpcodeStr,
1543 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1544 "v"##vsz128##elty##elsz, "v2i64")),
1545 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1546 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1547 !cast<X86MemOperand>(elty##"128mem"), d,
1548 IsReMaterializable>, EVEX_V128;
1553 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1554 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1555 X86MemOperand memop, Domain d> {
1556 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1557 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1558 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1560 let Constraints = "$src1 = $dst" in
1561 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1562 (ins RC:$src1, KRC:$mask, RC:$src2),
1563 !strconcat(OpcodeStr,
1564 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1566 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1567 (ins KRC:$mask, RC:$src),
1568 !strconcat(OpcodeStr,
1569 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1570 [], d>, EVEX, EVEX_KZ;
1572 let mayStore = 1 in {
1573 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1575 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1576 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1577 (ins memop:$dst, KRC:$mask, RC:$src),
1578 !strconcat(OpcodeStr,
1579 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1580 [], d>, EVEX, EVEX_K;
1585 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1586 string st_suff_512, string st_suff_256,
1587 string st_suff_128, string elty, string elsz,
1588 string vsz512, string vsz256, string vsz128,
1589 Domain d, Predicate prd> {
1590 let Predicates = [prd] in
1591 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1592 !cast<ValueType>("v"##vsz512##elty##elsz),
1593 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1594 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1596 let Predicates = [prd, HasVLX] in {
1597 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1598 !cast<ValueType>("v"##vsz256##elty##elsz),
1599 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1600 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1602 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1603 !cast<ValueType>("v"##vsz128##elty##elsz),
1604 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1605 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1609 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1610 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1611 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1612 "512", "256", "", "f", "32", "16", "8", "4",
1613 SSEPackedSingle, HasAVX512>,
1614 PS, EVEX_CD8<32, CD8VF>;
1616 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1617 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1618 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1619 "512", "256", "", "f", "64", "8", "4", "2",
1620 SSEPackedDouble, HasAVX512>,
1621 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1623 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1624 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1625 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1626 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1627 PS, EVEX_CD8<32, CD8VF>;
1629 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1630 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1631 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1632 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1633 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1635 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1636 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1637 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1639 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1640 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1641 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1643 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1645 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1647 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1649 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1652 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1653 "16", "8", "4", SSEPackedInt, HasAVX512>,
1654 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1655 "512", "256", "", "i", "32", "16", "8", "4",
1656 SSEPackedInt, HasAVX512>,
1657 PD, EVEX_CD8<32, CD8VF>;
1659 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1660 "8", "4", "2", SSEPackedInt, HasAVX512>,
1661 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1662 "512", "256", "", "i", "64", "8", "4", "2",
1663 SSEPackedInt, HasAVX512>,
1664 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1666 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1667 "64", "32", "16", SSEPackedInt, HasBWI>,
1668 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1669 "i", "8", "64", "32", "16", SSEPackedInt,
1670 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1672 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1673 "32", "16", "8", SSEPackedInt, HasBWI>,
1674 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1675 "i", "16", "32", "16", "8", SSEPackedInt,
1676 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1678 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1679 "16", "8", "4", SSEPackedInt, HasAVX512>,
1680 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1681 "i", "32", "16", "8", "4", SSEPackedInt,
1682 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1684 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1685 "8", "4", "2", SSEPackedInt, HasAVX512>,
1686 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1687 "i", "64", "8", "4", "2", SSEPackedInt,
1688 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
1690 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1691 (v16i32 immAllZerosV), GR16:$mask)),
1692 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1694 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1695 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1696 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1698 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1700 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1702 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1704 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1707 let AddedComplexity = 20 in {
1708 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1709 (bc_v8i64 (v16i32 immAllZerosV)))),
1710 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
1712 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1713 (v8i64 VR512:$src))),
1714 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1717 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1718 (v16i32 immAllZerosV))),
1719 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
1721 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1722 (v16i32 VR512:$src))),
1723 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1726 // Move Int Doubleword to Packed Double Int
1728 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1729 "vmovd\t{$src, $dst|$dst, $src}",
1731 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1733 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1734 "vmovd\t{$src, $dst|$dst, $src}",
1736 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1737 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1738 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1739 "vmovq\t{$src, $dst|$dst, $src}",
1741 (v2i64 (scalar_to_vector GR64:$src)))],
1742 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1743 let isCodeGenOnly = 1 in {
1744 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1745 "vmovq\t{$src, $dst|$dst, $src}",
1746 [(set FR64:$dst, (bitconvert GR64:$src))],
1747 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1748 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1749 "vmovq\t{$src, $dst|$dst, $src}",
1750 [(set GR64:$dst, (bitconvert FR64:$src))],
1751 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1753 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1754 "vmovq\t{$src, $dst|$dst, $src}",
1755 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1756 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1757 EVEX_CD8<64, CD8VT1>;
1759 // Move Int Doubleword to Single Scalar
1761 let isCodeGenOnly = 1 in {
1762 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1763 "vmovd\t{$src, $dst|$dst, $src}",
1764 [(set FR32X:$dst, (bitconvert GR32:$src))],
1765 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1767 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1768 "vmovd\t{$src, $dst|$dst, $src}",
1769 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1770 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1773 // Move doubleword from xmm register to r/m32
1775 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1776 "vmovd\t{$src, $dst|$dst, $src}",
1777 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1778 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1780 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1781 (ins i32mem:$dst, VR128X:$src),
1782 "vmovd\t{$src, $dst|$dst, $src}",
1783 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1784 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1785 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1787 // Move quadword from xmm1 register to r/m64
1789 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1790 "vmovq\t{$src, $dst|$dst, $src}",
1791 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1793 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1794 Requires<[HasAVX512, In64BitMode]>;
1796 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1797 (ins i64mem:$dst, VR128X:$src),
1798 "vmovq\t{$src, $dst|$dst, $src}",
1799 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1800 addr:$dst)], IIC_SSE_MOVDQ>,
1801 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1802 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1804 // Move Scalar Single to Double Int
1806 let isCodeGenOnly = 1 in {
1807 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1809 "vmovd\t{$src, $dst|$dst, $src}",
1810 [(set GR32:$dst, (bitconvert FR32X:$src))],
1811 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1812 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1813 (ins i32mem:$dst, FR32X:$src),
1814 "vmovd\t{$src, $dst|$dst, $src}",
1815 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1816 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1819 // Move Quadword Int to Packed Quadword Int
1821 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1823 "vmovq\t{$src, $dst|$dst, $src}",
1825 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1826 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1828 //===----------------------------------------------------------------------===//
1829 // AVX-512 MOVSS, MOVSD
1830 //===----------------------------------------------------------------------===//
1832 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1833 SDNode OpNode, ValueType vt,
1834 X86MemOperand x86memop, PatFrag mem_pat> {
1835 let hasSideEffects = 0 in {
1836 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1837 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1838 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1839 (scalar_to_vector RC:$src2))))],
1840 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1841 let Constraints = "$src1 = $dst" in
1842 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1843 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1845 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1846 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1847 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1848 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1849 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1851 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1852 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1853 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1855 } //hasSideEffects = 0
1858 let ExeDomain = SSEPackedSingle in
1859 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1860 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1862 let ExeDomain = SSEPackedDouble in
1863 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1864 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1866 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1867 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1868 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1870 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1871 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1872 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1874 // For the disassembler
1875 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1876 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1877 (ins VR128X:$src1, FR32X:$src2),
1878 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1880 XS, EVEX_4V, VEX_LIG;
1881 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1882 (ins VR128X:$src1, FR64X:$src2),
1883 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1885 XD, EVEX_4V, VEX_LIG, VEX_W;
1888 let Predicates = [HasAVX512] in {
1889 let AddedComplexity = 15 in {
1890 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1891 // MOVS{S,D} to the lower bits.
1892 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1893 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1894 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1895 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1896 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1897 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1898 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1899 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1901 // Move low f32 and clear high bits.
1902 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1903 (SUBREG_TO_REG (i32 0),
1904 (VMOVSSZrr (v4f32 (V_SET0)),
1905 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1906 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1907 (SUBREG_TO_REG (i32 0),
1908 (VMOVSSZrr (v4i32 (V_SET0)),
1909 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1912 let AddedComplexity = 20 in {
1913 // MOVSSrm zeros the high parts of the register; represent this
1914 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1915 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1916 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1917 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1918 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1919 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1920 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1922 // MOVSDrm zeros the high parts of the register; represent this
1923 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1924 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1925 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1926 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1927 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1928 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1929 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1930 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1931 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1932 def : Pat<(v2f64 (X86vzload addr:$src)),
1933 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1935 // Represent the same patterns above but in the form they appear for
1937 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1938 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1939 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1940 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1941 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1942 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1943 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1944 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1945 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1947 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1948 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1949 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1950 FR32X:$src)), sub_xmm)>;
1951 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1952 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1953 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1954 FR64X:$src)), sub_xmm)>;
1955 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1956 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1957 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1959 // Move low f64 and clear high bits.
1960 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1961 (SUBREG_TO_REG (i32 0),
1962 (VMOVSDZrr (v2f64 (V_SET0)),
1963 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1965 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1966 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1967 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1969 // Extract and store.
1970 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1972 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1973 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1975 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1977 // Shuffle with VMOVSS
1978 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1979 (VMOVSSZrr (v4i32 VR128X:$src1),
1980 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1981 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1982 (VMOVSSZrr (v4f32 VR128X:$src1),
1983 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1986 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1987 (SUBREG_TO_REG (i32 0),
1988 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1989 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1991 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1992 (SUBREG_TO_REG (i32 0),
1993 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1994 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1997 // Shuffle with VMOVSD
1998 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1999 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2000 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2001 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2002 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2003 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2004 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2005 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2008 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2009 (SUBREG_TO_REG (i32 0),
2010 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2011 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2013 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2014 (SUBREG_TO_REG (i32 0),
2015 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2016 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2019 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2020 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2021 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2022 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2023 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2024 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2025 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2026 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2029 let AddedComplexity = 15 in
2030 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2032 "vmovq\t{$src, $dst|$dst, $src}",
2033 [(set VR128X:$dst, (v2i64 (X86vzmovl
2034 (v2i64 VR128X:$src))))],
2035 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2037 let AddedComplexity = 20 in
2038 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2040 "vmovq\t{$src, $dst|$dst, $src}",
2041 [(set VR128X:$dst, (v2i64 (X86vzmovl
2042 (loadv2i64 addr:$src))))],
2043 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2044 EVEX_CD8<8, CD8VT8>;
2046 let Predicates = [HasAVX512] in {
2047 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2048 let AddedComplexity = 20 in {
2049 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2050 (VMOVDI2PDIZrm addr:$src)>;
2051 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2052 (VMOV64toPQIZrr GR64:$src)>;
2053 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2054 (VMOVDI2PDIZrr GR32:$src)>;
2056 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2057 (VMOVDI2PDIZrm addr:$src)>;
2058 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2059 (VMOVDI2PDIZrm addr:$src)>;
2060 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2061 (VMOVZPQILo2PQIZrm addr:$src)>;
2062 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2063 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2064 def : Pat<(v2i64 (X86vzload addr:$src)),
2065 (VMOVZPQILo2PQIZrm addr:$src)>;
2068 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2069 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2070 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2071 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2072 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2073 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2074 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2077 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2078 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2080 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2081 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2083 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2084 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2086 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2087 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2089 //===----------------------------------------------------------------------===//
2090 // AVX-512 - Non-temporals
2091 //===----------------------------------------------------------------------===//
2093 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
2095 "vmovntdqa\t{$src, $dst|$dst, $src}",
2097 (int_x86_avx512_movntdqa addr:$src))]>,
2098 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2100 // Prefer non-temporal over temporal versions
2101 let AddedComplexity = 400, SchedRW = [WriteStore] in {
2103 def VMOVNTPSZmr : AVX512PSI<0x2B, MRMDestMem, (outs),
2104 (ins f512mem:$dst, VR512:$src),
2105 "vmovntps\t{$src, $dst|$dst, $src}",
2106 [(alignednontemporalstore (v16f32 VR512:$src),
2109 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2111 def VMOVNTPDZmr : AVX512PDI<0x2B, MRMDestMem, (outs),
2112 (ins f512mem:$dst, VR512:$src),
2113 "vmovntpd\t{$src, $dst|$dst, $src}",
2114 [(alignednontemporalstore (v8f64 VR512:$src),
2117 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2120 def VMOVNTDQZmr : AVX512BI<0xE7, MRMDestMem, (outs),
2121 (ins i512mem:$dst, VR512:$src),
2122 "vmovntdq\t{$src, $dst|$dst, $src}",
2123 [(alignednontemporalstore (v8i64 VR512:$src),
2126 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2129 //===----------------------------------------------------------------------===//
2130 // AVX-512 - Integer arithmetic
2132 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2133 ValueType OpVT, RegisterClass KRC,
2134 RegisterClass RC, PatFrag memop_frag,
2135 X86MemOperand x86memop, PatFrag scalar_mfrag,
2136 X86MemOperand x86scalar_mop, string BrdcstStr,
2137 OpndItins itins, bit IsCommutable = 0> {
2138 let isCommutable = IsCommutable in
2139 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2140 (ins RC:$src1, RC:$src2),
2141 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2142 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2144 let AddedComplexity = 30 in {
2145 let Constraints = "$src0 = $dst" in
2146 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2147 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
2148 !strconcat(OpcodeStr,
2149 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2150 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2151 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2153 itins.rr>, EVEX_4V, EVEX_K;
2154 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2155 (ins KRC:$mask, RC:$src1, RC:$src2),
2156 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2157 "|$dst {${mask}} {z}, $src1, $src2}"),
2158 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2159 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2160 (OpVT immAllZerosV))))],
2161 itins.rr>, EVEX_4V, EVEX_KZ;
2164 let mayLoad = 1 in {
2165 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2166 (ins RC:$src1, x86memop:$src2),
2167 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2168 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
2170 let AddedComplexity = 30 in {
2171 let Constraints = "$src0 = $dst" in
2172 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2173 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
2174 !strconcat(OpcodeStr,
2175 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2176 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2177 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2179 itins.rm>, EVEX_4V, EVEX_K;
2180 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2181 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2182 !strconcat(OpcodeStr,
2183 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2184 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2185 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2186 (OpVT immAllZerosV))))],
2187 itins.rm>, EVEX_4V, EVEX_KZ;
2189 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2190 (ins RC:$src1, x86scalar_mop:$src2),
2191 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2192 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2193 [(set RC:$dst, (OpNode RC:$src1,
2194 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2195 itins.rm>, EVEX_4V, EVEX_B;
2196 let AddedComplexity = 30 in {
2197 let Constraints = "$src0 = $dst" in
2198 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2199 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2200 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2201 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2203 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2204 (OpNode (OpVT RC:$src1),
2205 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2207 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2208 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2209 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2210 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2211 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2213 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2214 (OpNode (OpVT RC:$src1),
2215 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2216 (OpVT immAllZerosV))))],
2217 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2222 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2223 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2224 PatFrag memop_frag, X86MemOperand x86memop,
2225 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2226 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2227 let isCommutable = IsCommutable in
2229 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2230 (ins RC:$src1, RC:$src2),
2231 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2233 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2234 (ins KRC:$mask, RC:$src1, RC:$src2),
2235 !strconcat(OpcodeStr,
2236 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2237 [], itins.rr>, EVEX_4V, EVEX_K;
2238 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2239 (ins KRC:$mask, RC:$src1, RC:$src2),
2240 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2241 "|$dst {${mask}} {z}, $src1, $src2}"),
2242 [], itins.rr>, EVEX_4V, EVEX_KZ;
2244 let mayLoad = 1 in {
2245 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2246 (ins RC:$src1, x86memop:$src2),
2247 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2249 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2250 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2251 !strconcat(OpcodeStr,
2252 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2253 [], itins.rm>, EVEX_4V, EVEX_K;
2254 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2255 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2256 !strconcat(OpcodeStr,
2257 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2258 [], itins.rm>, EVEX_4V, EVEX_KZ;
2259 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2260 (ins RC:$src1, x86scalar_mop:$src2),
2261 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2262 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2263 [], itins.rm>, EVEX_4V, EVEX_B;
2264 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2265 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2266 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2267 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2269 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2270 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2271 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2272 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2273 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2275 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2279 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2280 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2281 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2283 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2284 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2285 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2287 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2288 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2289 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2291 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2292 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2293 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2295 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2296 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2297 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2299 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2300 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2301 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2302 EVEX_CD8<64, CD8VF>, VEX_W;
2304 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2305 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2306 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2308 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2309 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2311 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2312 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2313 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2314 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2315 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2316 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2318 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2319 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2320 SSE_INTALU_ITINS_P, 1>,
2321 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2322 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2323 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2324 SSE_INTALU_ITINS_P, 0>,
2325 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2327 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2328 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2329 SSE_INTALU_ITINS_P, 1>,
2330 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2331 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2332 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2333 SSE_INTALU_ITINS_P, 0>,
2334 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2336 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2337 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2338 SSE_INTALU_ITINS_P, 1>,
2339 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2340 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2341 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2342 SSE_INTALU_ITINS_P, 0>,
2343 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2345 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2346 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2347 SSE_INTALU_ITINS_P, 1>,
2348 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2349 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2350 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2351 SSE_INTALU_ITINS_P, 0>,
2352 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2354 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2355 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2356 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2357 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2358 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2359 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2360 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2361 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2362 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2363 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2364 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2365 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2366 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2367 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2368 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2369 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2370 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2371 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2372 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2373 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2374 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2375 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2376 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2377 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2378 //===----------------------------------------------------------------------===//
2379 // AVX-512 - Unpack Instructions
2380 //===----------------------------------------------------------------------===//
2382 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2383 PatFrag mem_frag, RegisterClass RC,
2384 X86MemOperand x86memop, string asm,
2386 def rr : AVX512PI<opc, MRMSrcReg,
2387 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2389 (vt (OpNode RC:$src1, RC:$src2)))],
2391 def rm : AVX512PI<opc, MRMSrcMem,
2392 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2394 (vt (OpNode RC:$src1,
2395 (bitconvert (mem_frag addr:$src2)))))],
2399 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2400 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2401 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2402 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2403 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2404 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2405 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2406 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2407 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2408 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2409 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2410 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2412 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2413 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2414 X86MemOperand x86memop> {
2415 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2416 (ins RC:$src1, RC:$src2),
2417 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2418 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2419 IIC_SSE_UNPCK>, EVEX_4V;
2420 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2421 (ins RC:$src1, x86memop:$src2),
2422 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2423 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2424 (bitconvert (memop_frag addr:$src2)))))],
2425 IIC_SSE_UNPCK>, EVEX_4V;
2427 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2428 VR512, memopv16i32, i512mem>, EVEX_V512,
2429 EVEX_CD8<32, CD8VF>;
2430 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2431 VR512, memopv8i64, i512mem>, EVEX_V512,
2432 VEX_W, EVEX_CD8<64, CD8VF>;
2433 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2434 VR512, memopv16i32, i512mem>, EVEX_V512,
2435 EVEX_CD8<32, CD8VF>;
2436 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2437 VR512, memopv8i64, i512mem>, EVEX_V512,
2438 VEX_W, EVEX_CD8<64, CD8VF>;
2439 //===----------------------------------------------------------------------===//
2443 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2444 SDNode OpNode, PatFrag mem_frag,
2445 X86MemOperand x86memop, ValueType OpVT> {
2446 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2447 (ins RC:$src1, i8imm:$src2),
2448 !strconcat(OpcodeStr,
2449 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2451 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2453 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2454 (ins x86memop:$src1, i8imm:$src2),
2455 !strconcat(OpcodeStr,
2456 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2458 (OpVT (OpNode (mem_frag addr:$src1),
2459 (i8 imm:$src2))))]>, EVEX;
2462 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2463 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2465 let ExeDomain = SSEPackedSingle in
2466 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2467 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2468 EVEX_CD8<32, CD8VF>;
2469 let ExeDomain = SSEPackedDouble in
2470 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2471 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2472 VEX_W, EVEX_CD8<32, CD8VF>;
2474 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2475 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2476 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2477 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2479 //===----------------------------------------------------------------------===//
2480 // AVX-512 Logical Instructions
2481 //===----------------------------------------------------------------------===//
2483 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2484 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2485 EVEX_V512, EVEX_CD8<32, CD8VF>;
2486 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2487 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2488 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2489 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2490 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2491 EVEX_V512, EVEX_CD8<32, CD8VF>;
2492 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2493 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2494 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2495 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2496 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2497 EVEX_V512, EVEX_CD8<32, CD8VF>;
2498 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2499 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2500 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2501 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2502 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2503 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2504 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2505 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2506 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2508 //===----------------------------------------------------------------------===//
2509 // AVX-512 FP arithmetic
2510 //===----------------------------------------------------------------------===//
2512 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2514 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2515 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2516 EVEX_CD8<32, CD8VT1>;
2517 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2518 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2519 EVEX_CD8<64, CD8VT1>;
2522 let isCommutable = 1 in {
2523 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2524 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2525 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2526 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2528 let isCommutable = 0 in {
2529 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2530 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2533 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2535 RegisterClass RC, ValueType vt,
2536 X86MemOperand x86memop, PatFrag mem_frag,
2537 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2539 Domain d, OpndItins itins, bit commutable> {
2540 let isCommutable = commutable in {
2541 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2542 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2543 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2546 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2547 !strconcat(OpcodeStr,
2548 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2549 [], itins.rr, d>, EVEX_4V, EVEX_K;
2551 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2552 !strconcat(OpcodeStr,
2553 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2554 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2557 let mayLoad = 1 in {
2558 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2559 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2560 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2561 itins.rm, d>, EVEX_4V;
2563 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2564 (ins RC:$src1, x86scalar_mop:$src2),
2565 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2566 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2567 [(set RC:$dst, (OpNode RC:$src1,
2568 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2569 itins.rm, d>, EVEX_4V, EVEX_B;
2571 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2572 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2573 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2574 [], itins.rm, d>, EVEX_4V, EVEX_K;
2576 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2577 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2578 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2579 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2581 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2582 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2583 " \t{${src2}", BrdcstStr,
2584 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2585 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2587 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2588 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2589 " \t{${src2}", BrdcstStr,
2590 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2592 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2596 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2597 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2598 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2600 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2601 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2602 SSE_ALU_ITINS_P.d, 1>,
2603 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2605 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2606 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2607 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2608 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2609 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2610 SSE_ALU_ITINS_P.d, 1>,
2611 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2613 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2614 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2615 SSE_ALU_ITINS_P.s, 1>,
2616 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2617 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2618 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2619 SSE_ALU_ITINS_P.s, 1>,
2620 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2622 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2623 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2624 SSE_ALU_ITINS_P.d, 1>,
2625 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2626 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2627 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2628 SSE_ALU_ITINS_P.d, 1>,
2629 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2631 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2632 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2633 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2634 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2635 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2636 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2638 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2639 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2640 SSE_ALU_ITINS_P.d, 0>,
2641 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2642 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2643 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2644 SSE_ALU_ITINS_P.d, 0>,
2645 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2647 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2648 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2649 (i16 -1), FROUND_CURRENT)),
2650 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2652 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2653 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2654 (i8 -1), FROUND_CURRENT)),
2655 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2657 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2658 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2659 (i16 -1), FROUND_CURRENT)),
2660 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2662 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2663 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2664 (i8 -1), FROUND_CURRENT)),
2665 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2666 //===----------------------------------------------------------------------===//
2667 // AVX-512 VPTESTM instructions
2668 //===----------------------------------------------------------------------===//
2670 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2671 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2672 SDNode OpNode, ValueType vt> {
2673 def rr : AVX512PI<opc, MRMSrcReg,
2674 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2675 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2676 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2677 SSEPackedInt>, EVEX_4V;
2678 def rm : AVX512PI<opc, MRMSrcMem,
2679 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2680 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2681 [(set KRC:$dst, (OpNode (vt RC:$src1),
2682 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2685 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2686 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2687 EVEX_CD8<32, CD8VF>;
2688 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2689 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2690 EVEX_CD8<64, CD8VF>;
2692 let Predicates = [HasCDI] in {
2693 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2694 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2695 EVEX_CD8<32, CD8VF>;
2696 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2697 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2698 EVEX_CD8<64, CD8VF>;
2701 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2702 (v16i32 VR512:$src2), (i16 -1))),
2703 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2705 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2706 (v8i64 VR512:$src2), (i8 -1))),
2707 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2708 //===----------------------------------------------------------------------===//
2709 // AVX-512 Shift instructions
2710 //===----------------------------------------------------------------------===//
2711 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2712 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2713 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2714 RegisterClass KRC> {
2715 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2716 (ins RC:$src1, i8imm:$src2),
2717 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2718 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2719 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2720 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2721 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2722 !strconcat(OpcodeStr,
2723 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2724 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2725 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2726 (ins x86memop:$src1, i8imm:$src2),
2727 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2728 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2729 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2730 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2731 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2732 !strconcat(OpcodeStr,
2733 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2734 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2737 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2738 RegisterClass RC, ValueType vt, ValueType SrcVT,
2739 PatFrag bc_frag, RegisterClass KRC> {
2740 // src2 is always 128-bit
2741 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2742 (ins RC:$src1, VR128X:$src2),
2743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2744 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2745 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2746 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2747 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2748 !strconcat(OpcodeStr,
2749 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2750 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2751 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2752 (ins RC:$src1, i128mem:$src2),
2753 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2754 [(set RC:$dst, (vt (OpNode RC:$src1,
2755 (bc_frag (memopv2i64 addr:$src2)))))],
2756 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2757 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2758 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2759 !strconcat(OpcodeStr,
2760 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2761 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2764 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2765 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2766 EVEX_V512, EVEX_CD8<32, CD8VF>;
2767 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2768 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2769 EVEX_CD8<32, CD8VQ>;
2771 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2772 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2773 EVEX_CD8<64, CD8VF>, VEX_W;
2774 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2775 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2776 EVEX_CD8<64, CD8VQ>, VEX_W;
2778 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2779 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2780 EVEX_CD8<32, CD8VF>;
2781 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2782 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2783 EVEX_CD8<32, CD8VQ>;
2785 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2786 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2787 EVEX_CD8<64, CD8VF>, VEX_W;
2788 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2789 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2790 EVEX_CD8<64, CD8VQ>, VEX_W;
2792 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2793 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2794 EVEX_V512, EVEX_CD8<32, CD8VF>;
2795 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2796 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2797 EVEX_CD8<32, CD8VQ>;
2799 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2800 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2801 EVEX_CD8<64, CD8VF>, VEX_W;
2802 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2803 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2804 EVEX_CD8<64, CD8VQ>, VEX_W;
2806 //===-------------------------------------------------------------------===//
2807 // Variable Bit Shifts
2808 //===-------------------------------------------------------------------===//
2809 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2810 RegisterClass RC, ValueType vt,
2811 X86MemOperand x86memop, PatFrag mem_frag> {
2812 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2813 (ins RC:$src1, RC:$src2),
2814 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2816 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2818 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2819 (ins RC:$src1, x86memop:$src2),
2820 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2822 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2826 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2827 i512mem, memopv16i32>, EVEX_V512,
2828 EVEX_CD8<32, CD8VF>;
2829 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2830 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2831 EVEX_CD8<64, CD8VF>;
2832 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2833 i512mem, memopv16i32>, EVEX_V512,
2834 EVEX_CD8<32, CD8VF>;
2835 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2836 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2837 EVEX_CD8<64, CD8VF>;
2838 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2839 i512mem, memopv16i32>, EVEX_V512,
2840 EVEX_CD8<32, CD8VF>;
2841 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2842 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2843 EVEX_CD8<64, CD8VF>;
2845 //===----------------------------------------------------------------------===//
2846 // AVX-512 - MOVDDUP
2847 //===----------------------------------------------------------------------===//
2849 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2850 X86MemOperand x86memop, PatFrag memop_frag> {
2851 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2852 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2853 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2854 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2855 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2857 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2860 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2861 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2862 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2863 (VMOVDDUPZrm addr:$src)>;
2865 //===---------------------------------------------------------------------===//
2866 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2867 //===---------------------------------------------------------------------===//
2868 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2869 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2870 X86MemOperand x86memop> {
2871 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2872 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2873 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2875 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2876 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2877 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2880 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2881 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2882 EVEX_CD8<32, CD8VF>;
2883 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2884 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2885 EVEX_CD8<32, CD8VF>;
2887 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2888 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2889 (VMOVSHDUPZrm addr:$src)>;
2890 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2891 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2892 (VMOVSLDUPZrm addr:$src)>;
2894 //===----------------------------------------------------------------------===//
2895 // Move Low to High and High to Low packed FP Instructions
2896 //===----------------------------------------------------------------------===//
2897 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2898 (ins VR128X:$src1, VR128X:$src2),
2899 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2900 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2901 IIC_SSE_MOV_LH>, EVEX_4V;
2902 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2903 (ins VR128X:$src1, VR128X:$src2),
2904 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2905 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2906 IIC_SSE_MOV_LH>, EVEX_4V;
2908 let Predicates = [HasAVX512] in {
2910 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2911 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2912 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2913 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2916 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2917 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2920 //===----------------------------------------------------------------------===//
2921 // FMA - Fused Multiply Operations
2923 let Constraints = "$src1 = $dst" in {
2924 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2925 RegisterClass RC, X86MemOperand x86memop,
2926 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2927 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2928 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2929 (ins RC:$src1, RC:$src2, RC:$src3),
2930 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2931 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2934 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2935 (ins RC:$src1, RC:$src2, x86memop:$src3),
2936 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2937 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2938 (mem_frag addr:$src3))))]>;
2939 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2940 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2941 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2942 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2943 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2944 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2946 } // Constraints = "$src1 = $dst"
2948 let ExeDomain = SSEPackedSingle in {
2949 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2950 memopv16f32, f32mem, loadf32, "{1to16}",
2951 X86Fmadd, v16f32>, EVEX_V512,
2952 EVEX_CD8<32, CD8VF>;
2953 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2954 memopv16f32, f32mem, loadf32, "{1to16}",
2955 X86Fmsub, v16f32>, EVEX_V512,
2956 EVEX_CD8<32, CD8VF>;
2957 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2958 memopv16f32, f32mem, loadf32, "{1to16}",
2959 X86Fmaddsub, v16f32>,
2960 EVEX_V512, EVEX_CD8<32, CD8VF>;
2961 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2962 memopv16f32, f32mem, loadf32, "{1to16}",
2963 X86Fmsubadd, v16f32>,
2964 EVEX_V512, EVEX_CD8<32, CD8VF>;
2965 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2966 memopv16f32, f32mem, loadf32, "{1to16}",
2967 X86Fnmadd, v16f32>, EVEX_V512,
2968 EVEX_CD8<32, CD8VF>;
2969 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2970 memopv16f32, f32mem, loadf32, "{1to16}",
2971 X86Fnmsub, v16f32>, EVEX_V512,
2972 EVEX_CD8<32, CD8VF>;
2974 let ExeDomain = SSEPackedDouble in {
2975 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2976 memopv8f64, f64mem, loadf64, "{1to8}",
2977 X86Fmadd, v8f64>, EVEX_V512,
2978 VEX_W, EVEX_CD8<64, CD8VF>;
2979 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2980 memopv8f64, f64mem, loadf64, "{1to8}",
2981 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2982 EVEX_CD8<64, CD8VF>;
2983 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2984 memopv8f64, f64mem, loadf64, "{1to8}",
2985 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2986 EVEX_CD8<64, CD8VF>;
2987 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2988 memopv8f64, f64mem, loadf64, "{1to8}",
2989 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2990 EVEX_CD8<64, CD8VF>;
2991 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2992 memopv8f64, f64mem, loadf64, "{1to8}",
2993 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2994 EVEX_CD8<64, CD8VF>;
2995 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2996 memopv8f64, f64mem, loadf64, "{1to8}",
2997 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2998 EVEX_CD8<64, CD8VF>;
3001 let Constraints = "$src1 = $dst" in {
3002 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
3003 RegisterClass RC, X86MemOperand x86memop,
3004 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
3005 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
3007 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3008 (ins RC:$src1, RC:$src3, x86memop:$src2),
3009 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3010 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
3011 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3012 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
3013 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3014 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
3015 [(set RC:$dst, (OpNode RC:$src1,
3016 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
3018 } // Constraints = "$src1 = $dst"
3021 let ExeDomain = SSEPackedSingle in {
3022 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
3023 memopv16f32, f32mem, loadf32, "{1to16}",
3024 X86Fmadd, v16f32>, EVEX_V512,
3025 EVEX_CD8<32, CD8VF>;
3026 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
3027 memopv16f32, f32mem, loadf32, "{1to16}",
3028 X86Fmsub, v16f32>, EVEX_V512,
3029 EVEX_CD8<32, CD8VF>;
3030 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
3031 memopv16f32, f32mem, loadf32, "{1to16}",
3032 X86Fmaddsub, v16f32>,
3033 EVEX_V512, EVEX_CD8<32, CD8VF>;
3034 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
3035 memopv16f32, f32mem, loadf32, "{1to16}",
3036 X86Fmsubadd, v16f32>,
3037 EVEX_V512, EVEX_CD8<32, CD8VF>;
3038 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
3039 memopv16f32, f32mem, loadf32, "{1to16}",
3040 X86Fnmadd, v16f32>, EVEX_V512,
3041 EVEX_CD8<32, CD8VF>;
3042 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
3043 memopv16f32, f32mem, loadf32, "{1to16}",
3044 X86Fnmsub, v16f32>, EVEX_V512,
3045 EVEX_CD8<32, CD8VF>;
3047 let ExeDomain = SSEPackedDouble in {
3048 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
3049 memopv8f64, f64mem, loadf64, "{1to8}",
3050 X86Fmadd, v8f64>, EVEX_V512,
3051 VEX_W, EVEX_CD8<64, CD8VF>;
3052 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
3053 memopv8f64, f64mem, loadf64, "{1to8}",
3054 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
3055 EVEX_CD8<64, CD8VF>;
3056 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
3057 memopv8f64, f64mem, loadf64, "{1to8}",
3058 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
3059 EVEX_CD8<64, CD8VF>;
3060 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
3061 memopv8f64, f64mem, loadf64, "{1to8}",
3062 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
3063 EVEX_CD8<64, CD8VF>;
3064 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
3065 memopv8f64, f64mem, loadf64, "{1to8}",
3066 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
3067 EVEX_CD8<64, CD8VF>;
3068 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
3069 memopv8f64, f64mem, loadf64, "{1to8}",
3070 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
3071 EVEX_CD8<64, CD8VF>;
3075 let Constraints = "$src1 = $dst" in {
3076 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3077 RegisterClass RC, ValueType OpVT,
3078 X86MemOperand x86memop, Operand memop,
3080 let isCommutable = 1 in
3081 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3082 (ins RC:$src1, RC:$src2, RC:$src3),
3083 !strconcat(OpcodeStr,
3084 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3086 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3088 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3089 (ins RC:$src1, RC:$src2, f128mem:$src3),
3090 !strconcat(OpcodeStr,
3091 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3093 (OpVT (OpNode RC:$src2, RC:$src1,
3094 (mem_frag addr:$src3))))]>;
3097 } // Constraints = "$src1 = $dst"
3099 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3100 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3101 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3102 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3103 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3104 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3105 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3106 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3107 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3108 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3109 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3110 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3111 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3112 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3113 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3114 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3116 //===----------------------------------------------------------------------===//
3117 // AVX-512 Scalar convert from sign integer to float/double
3118 //===----------------------------------------------------------------------===//
3120 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3121 X86MemOperand x86memop, string asm> {
3122 let hasSideEffects = 0 in {
3123 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3124 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3127 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3128 (ins DstRC:$src1, x86memop:$src),
3129 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3131 } // hasSideEffects = 0
3133 let Predicates = [HasAVX512] in {
3134 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3135 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3136 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3137 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3138 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3139 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3140 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3141 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3143 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3144 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3145 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3146 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3147 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3148 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3149 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3150 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3152 def : Pat<(f32 (sint_to_fp GR32:$src)),
3153 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3154 def : Pat<(f32 (sint_to_fp GR64:$src)),
3155 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3156 def : Pat<(f64 (sint_to_fp GR32:$src)),
3157 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3158 def : Pat<(f64 (sint_to_fp GR64:$src)),
3159 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3161 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3162 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3163 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3164 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3165 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3166 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3167 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3168 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3170 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3171 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3172 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3173 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3174 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3175 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3176 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3177 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3179 def : Pat<(f32 (uint_to_fp GR32:$src)),
3180 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3181 def : Pat<(f32 (uint_to_fp GR64:$src)),
3182 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3183 def : Pat<(f64 (uint_to_fp GR32:$src)),
3184 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3185 def : Pat<(f64 (uint_to_fp GR64:$src)),
3186 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3189 //===----------------------------------------------------------------------===//
3190 // AVX-512 Scalar convert from float/double to integer
3191 //===----------------------------------------------------------------------===//
3192 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3193 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3195 let hasSideEffects = 0 in {
3196 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3197 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3198 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3199 Requires<[HasAVX512]>;
3201 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3202 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3203 Requires<[HasAVX512]>;
3204 } // hasSideEffects = 0
3206 let Predicates = [HasAVX512] in {
3207 // Convert float/double to signed/unsigned int 32/64
3208 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3209 ssmem, sse_load_f32, "cvtss2si">,
3210 XS, EVEX_CD8<32, CD8VT1>;
3211 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3212 ssmem, sse_load_f32, "cvtss2si">,
3213 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3214 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3215 ssmem, sse_load_f32, "cvtss2usi">,
3216 XS, EVEX_CD8<32, CD8VT1>;
3217 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3218 int_x86_avx512_cvtss2usi64, ssmem,
3219 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3220 EVEX_CD8<32, CD8VT1>;
3221 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3222 sdmem, sse_load_f64, "cvtsd2si">,
3223 XD, EVEX_CD8<64, CD8VT1>;
3224 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3225 sdmem, sse_load_f64, "cvtsd2si">,
3226 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3227 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3228 sdmem, sse_load_f64, "cvtsd2usi">,
3229 XD, EVEX_CD8<64, CD8VT1>;
3230 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3231 int_x86_avx512_cvtsd2usi64, sdmem,
3232 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3233 EVEX_CD8<64, CD8VT1>;
3235 let isCodeGenOnly = 1 in {
3236 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3237 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3238 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3239 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3240 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3241 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3242 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3243 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3244 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3245 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3246 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3247 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3249 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3250 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3251 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3252 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3253 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3254 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3255 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3256 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3257 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3258 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3259 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3260 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3261 } // isCodeGenOnly = 1
3263 // Convert float/double to signed/unsigned int 32/64 with truncation
3264 let isCodeGenOnly = 1 in {
3265 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3266 ssmem, sse_load_f32, "cvttss2si">,
3267 XS, EVEX_CD8<32, CD8VT1>;
3268 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3269 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3270 "cvttss2si">, XS, VEX_W,
3271 EVEX_CD8<32, CD8VT1>;
3272 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3273 sdmem, sse_load_f64, "cvttsd2si">, XD,
3274 EVEX_CD8<64, CD8VT1>;
3275 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3276 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3277 "cvttsd2si">, XD, VEX_W,
3278 EVEX_CD8<64, CD8VT1>;
3279 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3280 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3281 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3282 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3283 int_x86_avx512_cvttss2usi64, ssmem,
3284 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3285 EVEX_CD8<32, CD8VT1>;
3286 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3287 int_x86_avx512_cvttsd2usi,
3288 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3289 EVEX_CD8<64, CD8VT1>;
3290 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3291 int_x86_avx512_cvttsd2usi64, sdmem,
3292 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3293 EVEX_CD8<64, CD8VT1>;
3294 } // isCodeGenOnly = 1
3296 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3297 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3299 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3300 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3301 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3302 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3303 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3304 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3307 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3308 loadf32, "cvttss2si">, XS,
3309 EVEX_CD8<32, CD8VT1>;
3310 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3311 loadf32, "cvttss2usi">, XS,
3312 EVEX_CD8<32, CD8VT1>;
3313 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3314 loadf32, "cvttss2si">, XS, VEX_W,
3315 EVEX_CD8<32, CD8VT1>;
3316 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3317 loadf32, "cvttss2usi">, XS, VEX_W,
3318 EVEX_CD8<32, CD8VT1>;
3319 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3320 loadf64, "cvttsd2si">, XD,
3321 EVEX_CD8<64, CD8VT1>;
3322 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3323 loadf64, "cvttsd2usi">, XD,
3324 EVEX_CD8<64, CD8VT1>;
3325 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3326 loadf64, "cvttsd2si">, XD, VEX_W,
3327 EVEX_CD8<64, CD8VT1>;
3328 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3329 loadf64, "cvttsd2usi">, XD, VEX_W,
3330 EVEX_CD8<64, CD8VT1>;
3332 //===----------------------------------------------------------------------===//
3333 // AVX-512 Convert form float to double and back
3334 //===----------------------------------------------------------------------===//
3335 let hasSideEffects = 0 in {
3336 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3337 (ins FR32X:$src1, FR32X:$src2),
3338 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3339 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3341 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3342 (ins FR32X:$src1, f32mem:$src2),
3343 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3344 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3345 EVEX_CD8<32, CD8VT1>;
3347 // Convert scalar double to scalar single
3348 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3349 (ins FR64X:$src1, FR64X:$src2),
3350 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3351 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3353 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3354 (ins FR64X:$src1, f64mem:$src2),
3355 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3356 []>, EVEX_4V, VEX_LIG, VEX_W,
3357 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3360 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3361 Requires<[HasAVX512]>;
3362 def : Pat<(fextend (loadf32 addr:$src)),
3363 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3365 def : Pat<(extloadf32 addr:$src),
3366 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3367 Requires<[HasAVX512, OptForSize]>;
3369 def : Pat<(extloadf32 addr:$src),
3370 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3371 Requires<[HasAVX512, OptForSpeed]>;
3373 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3374 Requires<[HasAVX512]>;
3376 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3377 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3378 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3380 let hasSideEffects = 0 in {
3381 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3382 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3384 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3385 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3386 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3387 [], d>, EVEX, EVEX_B, EVEX_RC;
3389 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3390 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3392 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3393 } // hasSideEffects = 0
3396 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3397 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3398 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3400 let hasSideEffects = 0 in {
3401 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3402 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3404 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3406 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3407 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3409 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3410 } // hasSideEffects = 0
3413 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3414 memopv8f64, f512mem, v8f32, v8f64,
3415 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3416 EVEX_CD8<64, CD8VF>;
3418 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3419 memopv4f64, f256mem, v8f64, v8f32,
3420 SSEPackedDouble>, EVEX_V512, PS,
3421 EVEX_CD8<32, CD8VH>;
3422 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3423 (VCVTPS2PDZrm addr:$src)>;
3425 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3426 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3427 (VCVTPD2PSZrr VR512:$src)>;
3429 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3430 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3431 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3433 //===----------------------------------------------------------------------===//
3434 // AVX-512 Vector convert from sign integer to float/double
3435 //===----------------------------------------------------------------------===//
3437 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3438 memopv8i64, i512mem, v16f32, v16i32,
3439 SSEPackedSingle>, EVEX_V512, PS,
3440 EVEX_CD8<32, CD8VF>;
3442 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3443 memopv4i64, i256mem, v8f64, v8i32,
3444 SSEPackedDouble>, EVEX_V512, XS,
3445 EVEX_CD8<32, CD8VH>;
3447 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3448 memopv16f32, f512mem, v16i32, v16f32,
3449 SSEPackedSingle>, EVEX_V512, XS,
3450 EVEX_CD8<32, CD8VF>;
3452 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3453 memopv8f64, f512mem, v8i32, v8f64,
3454 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3455 EVEX_CD8<64, CD8VF>;
3457 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3458 memopv16f32, f512mem, v16i32, v16f32,
3459 SSEPackedSingle>, EVEX_V512, PS,
3460 EVEX_CD8<32, CD8VF>;
3462 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3463 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3464 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3465 (VCVTTPS2UDQZrr VR512:$src)>;
3467 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3468 memopv8f64, f512mem, v8i32, v8f64,
3469 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3470 EVEX_CD8<64, CD8VF>;
3472 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3473 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3474 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3475 (VCVTTPD2UDQZrr VR512:$src)>;
3477 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3478 memopv4i64, f256mem, v8f64, v8i32,
3479 SSEPackedDouble>, EVEX_V512, XS,
3480 EVEX_CD8<32, CD8VH>;
3482 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3483 memopv16i32, f512mem, v16f32, v16i32,
3484 SSEPackedSingle>, EVEX_V512, XD,
3485 EVEX_CD8<32, CD8VF>;
3487 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3488 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3489 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3491 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3492 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3493 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3495 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3496 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3497 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3499 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3500 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3501 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3503 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3504 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3505 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3507 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3508 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3509 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3510 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3511 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3512 (VCVTDQ2PDZrr VR256X:$src)>;
3513 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3514 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3515 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3516 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3517 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3518 (VCVTUDQ2PDZrr VR256X:$src)>;
3520 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3521 RegisterClass DstRC, PatFrag mem_frag,
3522 X86MemOperand x86memop, Domain d> {
3523 let hasSideEffects = 0 in {
3524 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3525 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3527 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3528 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3529 [], d>, EVEX, EVEX_B, EVEX_RC;
3531 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3532 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3534 } // hasSideEffects = 0
3537 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3538 memopv16f32, f512mem, SSEPackedSingle>, PD,
3539 EVEX_V512, EVEX_CD8<32, CD8VF>;
3540 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3541 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3542 EVEX_V512, EVEX_CD8<64, CD8VF>;
3544 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3545 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3546 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3548 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3549 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3550 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3552 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3553 memopv16f32, f512mem, SSEPackedSingle>,
3554 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3555 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3556 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3557 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3559 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3560 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3561 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3563 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3564 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3565 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3567 let Predicates = [HasAVX512] in {
3568 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3569 (VCVTPD2PSZrm addr:$src)>;
3570 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3571 (VCVTPS2PDZrm addr:$src)>;
3574 //===----------------------------------------------------------------------===//
3575 // Half precision conversion instructions
3576 //===----------------------------------------------------------------------===//
3577 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3578 X86MemOperand x86memop> {
3579 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3580 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3582 let hasSideEffects = 0, mayLoad = 1 in
3583 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3584 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3587 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3588 X86MemOperand x86memop> {
3589 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3590 (ins srcRC:$src1, i32i8imm:$src2),
3591 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3593 let hasSideEffects = 0, mayStore = 1 in
3594 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3595 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3596 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3599 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3600 EVEX_CD8<32, CD8VH>;
3601 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3602 EVEX_CD8<32, CD8VH>;
3604 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3605 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3606 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3608 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3609 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3610 (VCVTPH2PSZrr VR256X:$src)>;
3612 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3613 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3614 "ucomiss">, PS, EVEX, VEX_LIG,
3615 EVEX_CD8<32, CD8VT1>;
3616 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3617 "ucomisd">, PD, EVEX,
3618 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3619 let Pattern = []<dag> in {
3620 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3621 "comiss">, PS, EVEX, VEX_LIG,
3622 EVEX_CD8<32, CD8VT1>;
3623 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3624 "comisd">, PD, EVEX,
3625 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3627 let isCodeGenOnly = 1 in {
3628 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3629 load, "ucomiss">, PS, EVEX, VEX_LIG,
3630 EVEX_CD8<32, CD8VT1>;
3631 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3632 load, "ucomisd">, PD, EVEX,
3633 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3635 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3636 load, "comiss">, PS, EVEX, VEX_LIG,
3637 EVEX_CD8<32, CD8VT1>;
3638 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3639 load, "comisd">, PD, EVEX,
3640 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3644 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3645 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3646 X86MemOperand x86memop> {
3647 let hasSideEffects = 0 in {
3648 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3649 (ins RC:$src1, RC:$src2),
3650 !strconcat(OpcodeStr,
3651 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3652 let mayLoad = 1 in {
3653 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3654 (ins RC:$src1, x86memop:$src2),
3655 !strconcat(OpcodeStr,
3656 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3661 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3662 EVEX_CD8<32, CD8VT1>;
3663 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3664 VEX_W, EVEX_CD8<64, CD8VT1>;
3665 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3666 EVEX_CD8<32, CD8VT1>;
3667 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3668 VEX_W, EVEX_CD8<64, CD8VT1>;
3670 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3671 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3672 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3673 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3675 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3676 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3677 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3678 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3680 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3681 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3682 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3683 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3685 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3686 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3687 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3688 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3690 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3691 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3692 RegisterClass RC, X86MemOperand x86memop,
3693 PatFrag mem_frag, ValueType OpVt> {
3694 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3695 !strconcat(OpcodeStr,
3696 " \t{$src, $dst|$dst, $src}"),
3697 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3699 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3700 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3701 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3704 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3705 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3706 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3707 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3708 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3709 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3710 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3711 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3713 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3714 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3715 (VRSQRT14PSZr VR512:$src)>;
3716 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3717 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3718 (VRSQRT14PDZr VR512:$src)>;
3720 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3721 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3722 (VRCP14PSZr VR512:$src)>;
3723 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3724 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3725 (VRCP14PDZr VR512:$src)>;
3727 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3728 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3729 X86MemOperand x86memop> {
3730 let hasSideEffects = 0, Predicates = [HasERI] in {
3731 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3732 (ins RC:$src1, RC:$src2),
3733 !strconcat(OpcodeStr,
3734 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3735 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3736 (ins RC:$src1, RC:$src2),
3737 !strconcat(OpcodeStr,
3738 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3739 []>, EVEX_4V, EVEX_B;
3740 let mayLoad = 1 in {
3741 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3742 (ins RC:$src1, x86memop:$src2),
3743 !strconcat(OpcodeStr,
3744 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3749 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3750 EVEX_CD8<32, CD8VT1>;
3751 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3752 VEX_W, EVEX_CD8<64, CD8VT1>;
3753 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3754 EVEX_CD8<32, CD8VT1>;
3755 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3756 VEX_W, EVEX_CD8<64, CD8VT1>;
3758 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3759 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3761 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3762 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3764 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3765 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3767 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3768 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3770 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3771 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3773 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3774 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3776 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3777 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3779 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3780 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3782 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3783 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3784 RegisterClass RC, X86MemOperand x86memop> {
3785 let hasSideEffects = 0, Predicates = [HasERI] in {
3786 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3787 !strconcat(OpcodeStr,
3788 " \t{$src, $dst|$dst, $src}"),
3790 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3791 !strconcat(OpcodeStr,
3792 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3794 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3795 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3799 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3800 EVEX_V512, EVEX_CD8<32, CD8VF>;
3801 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3802 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3803 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3804 EVEX_V512, EVEX_CD8<32, CD8VF>;
3805 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3806 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3808 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3809 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3810 (VRSQRT28PSZrb VR512:$src)>;
3811 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3812 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3813 (VRSQRT28PDZrb VR512:$src)>;
3815 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3816 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3817 (VRCP28PSZrb VR512:$src)>;
3818 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3819 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3820 (VRCP28PDZrb VR512:$src)>;
3822 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3823 OpndItins itins_s, OpndItins itins_d> {
3824 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3825 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3826 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3830 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3831 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3833 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3834 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3836 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3837 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3838 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3842 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3843 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3844 [(set VR512:$dst, (OpNode
3845 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3846 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3850 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3851 Intrinsic F32Int, Intrinsic F64Int,
3852 OpndItins itins_s, OpndItins itins_d> {
3853 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3854 (ins FR32X:$src1, FR32X:$src2),
3855 !strconcat(OpcodeStr,
3856 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3857 [], itins_s.rr>, XS, EVEX_4V;
3858 let isCodeGenOnly = 1 in
3859 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3860 (ins VR128X:$src1, VR128X:$src2),
3861 !strconcat(OpcodeStr,
3862 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3864 (F32Int VR128X:$src1, VR128X:$src2))],
3865 itins_s.rr>, XS, EVEX_4V;
3866 let mayLoad = 1 in {
3867 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3868 (ins FR32X:$src1, f32mem:$src2),
3869 !strconcat(OpcodeStr,
3870 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3871 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3872 let isCodeGenOnly = 1 in
3873 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3874 (ins VR128X:$src1, ssmem:$src2),
3875 !strconcat(OpcodeStr,
3876 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3878 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3879 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3881 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3882 (ins FR64X:$src1, FR64X:$src2),
3883 !strconcat(OpcodeStr,
3884 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3886 let isCodeGenOnly = 1 in
3887 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3888 (ins VR128X:$src1, VR128X:$src2),
3889 !strconcat(OpcodeStr,
3890 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3892 (F64Int VR128X:$src1, VR128X:$src2))],
3893 itins_s.rr>, XD, EVEX_4V, VEX_W;
3894 let mayLoad = 1 in {
3895 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3896 (ins FR64X:$src1, f64mem:$src2),
3897 !strconcat(OpcodeStr,
3898 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3899 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3900 let isCodeGenOnly = 1 in
3901 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3902 (ins VR128X:$src1, sdmem:$src2),
3903 !strconcat(OpcodeStr,
3904 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3906 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3907 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3912 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3913 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3914 SSE_SQRTSS, SSE_SQRTSD>,
3915 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3916 SSE_SQRTPS, SSE_SQRTPD>;
3918 let Predicates = [HasAVX512] in {
3919 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
3920 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
3921 (VSQRTPSZrr VR512:$src1)>;
3922 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
3923 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
3924 (VSQRTPDZrr VR512:$src1)>;
3926 def : Pat<(f32 (fsqrt FR32X:$src)),
3927 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3928 def : Pat<(f32 (fsqrt (load addr:$src))),
3929 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3930 Requires<[OptForSize]>;
3931 def : Pat<(f64 (fsqrt FR64X:$src)),
3932 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3933 def : Pat<(f64 (fsqrt (load addr:$src))),
3934 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3935 Requires<[OptForSize]>;
3937 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3938 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3939 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3940 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3941 Requires<[OptForSize]>;
3943 def : Pat<(f32 (X86frcp FR32X:$src)),
3944 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3945 def : Pat<(f32 (X86frcp (load addr:$src))),
3946 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3947 Requires<[OptForSize]>;
3949 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3950 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3951 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3953 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3954 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3956 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3957 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3958 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3960 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3961 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3965 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3966 X86MemOperand x86memop, RegisterClass RC,
3967 PatFrag mem_frag32, PatFrag mem_frag64,
3968 Intrinsic V4F32Int, Intrinsic V2F64Int,
3970 let ExeDomain = SSEPackedSingle in {
3971 // Intrinsic operation, reg.
3972 // Vector intrinsic operation, reg
3973 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3974 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3975 !strconcat(OpcodeStr,
3976 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3977 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3979 // Vector intrinsic operation, mem
3980 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3981 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3982 !strconcat(OpcodeStr,
3983 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3985 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3986 EVEX_CD8<32, VForm>;
3987 } // ExeDomain = SSEPackedSingle
3989 let ExeDomain = SSEPackedDouble in {
3990 // Vector intrinsic operation, reg
3991 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3992 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3993 !strconcat(OpcodeStr,
3994 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3995 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3997 // Vector intrinsic operation, mem
3998 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3999 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4000 !strconcat(OpcodeStr,
4001 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4003 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4004 EVEX_CD8<64, VForm>;
4005 } // ExeDomain = SSEPackedDouble
4008 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4012 let ExeDomain = GenericDomain in {
4014 let hasSideEffects = 0 in
4015 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4016 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4017 !strconcat(OpcodeStr,
4018 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4021 // Intrinsic operation, reg.
4022 let isCodeGenOnly = 1 in
4023 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4024 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4025 !strconcat(OpcodeStr,
4026 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4027 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4029 // Intrinsic operation, mem.
4030 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4031 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4032 !strconcat(OpcodeStr,
4033 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4034 [(set VR128X:$dst, (F32Int VR128X:$src1,
4035 sse_load_f32:$src2, imm:$src3))]>,
4036 EVEX_CD8<32, CD8VT1>;
4039 let hasSideEffects = 0 in
4040 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4041 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4042 !strconcat(OpcodeStr,
4043 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4046 // Intrinsic operation, reg.
4047 let isCodeGenOnly = 1 in
4048 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4049 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4050 !strconcat(OpcodeStr,
4051 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4052 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4055 // Intrinsic operation, mem.
4056 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4057 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4058 !strconcat(OpcodeStr,
4059 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4061 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4062 VEX_W, EVEX_CD8<64, CD8VT1>;
4063 } // ExeDomain = GenericDomain
4066 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4067 X86MemOperand x86memop, RegisterClass RC,
4068 PatFrag mem_frag, Domain d> {
4069 let ExeDomain = d in {
4070 // Intrinsic operation, reg.
4071 // Vector intrinsic operation, reg
4072 def r : AVX512AIi8<opc, MRMSrcReg,
4073 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4074 !strconcat(OpcodeStr,
4075 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4078 // Vector intrinsic operation, mem
4079 def m : AVX512AIi8<opc, MRMSrcMem,
4080 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4081 !strconcat(OpcodeStr,
4082 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4088 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4089 memopv16f32, SSEPackedSingle>, EVEX_V512,
4090 EVEX_CD8<32, CD8VF>;
4092 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4093 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4095 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4098 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4099 memopv8f64, SSEPackedDouble>, EVEX_V512,
4100 VEX_W, EVEX_CD8<64, CD8VF>;
4102 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4103 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4105 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4107 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4108 Operand x86memop, RegisterClass RC, Domain d> {
4109 let ExeDomain = d in {
4110 def r : AVX512AIi8<opc, MRMSrcReg,
4111 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4112 !strconcat(OpcodeStr,
4113 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4116 def m : AVX512AIi8<opc, MRMSrcMem,
4117 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4118 !strconcat(OpcodeStr,
4119 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4124 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4125 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4127 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4128 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4130 def : Pat<(ffloor FR32X:$src),
4131 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4132 def : Pat<(f64 (ffloor FR64X:$src)),
4133 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4134 def : Pat<(f32 (fnearbyint FR32X:$src)),
4135 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4136 def : Pat<(f64 (fnearbyint FR64X:$src)),
4137 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4138 def : Pat<(f32 (fceil FR32X:$src)),
4139 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4140 def : Pat<(f64 (fceil FR64X:$src)),
4141 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4142 def : Pat<(f32 (frint FR32X:$src)),
4143 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4144 def : Pat<(f64 (frint FR64X:$src)),
4145 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4146 def : Pat<(f32 (ftrunc FR32X:$src)),
4147 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4148 def : Pat<(f64 (ftrunc FR64X:$src)),
4149 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4151 def : Pat<(v16f32 (ffloor VR512:$src)),
4152 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4153 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4154 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4155 def : Pat<(v16f32 (fceil VR512:$src)),
4156 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4157 def : Pat<(v16f32 (frint VR512:$src)),
4158 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4159 def : Pat<(v16f32 (ftrunc VR512:$src)),
4160 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4162 def : Pat<(v8f64 (ffloor VR512:$src)),
4163 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4164 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4165 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4166 def : Pat<(v8f64 (fceil VR512:$src)),
4167 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4168 def : Pat<(v8f64 (frint VR512:$src)),
4169 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4170 def : Pat<(v8f64 (ftrunc VR512:$src)),
4171 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4173 //-------------------------------------------------
4174 // Integer truncate and extend operations
4175 //-------------------------------------------------
4177 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4178 RegisterClass dstRC, RegisterClass srcRC,
4179 RegisterClass KRC, X86MemOperand x86memop> {
4180 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4182 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4185 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4186 (ins KRC:$mask, srcRC:$src),
4187 !strconcat(OpcodeStr,
4188 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4191 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4192 (ins KRC:$mask, srcRC:$src),
4193 !strconcat(OpcodeStr,
4194 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4197 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4198 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4201 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4202 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4203 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4207 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4208 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4209 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4210 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4211 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4212 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4213 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4214 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4215 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4216 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4217 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4218 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4219 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4220 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4221 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4222 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4223 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4224 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4225 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4226 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4227 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4228 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4229 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4230 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4231 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4232 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4233 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4234 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4235 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4236 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4238 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4239 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4240 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4241 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4242 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4244 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4245 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4246 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4247 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4248 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4249 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4250 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4251 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4254 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4255 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4256 PatFrag mem_frag, X86MemOperand x86memop,
4257 ValueType OpVT, ValueType InVT> {
4259 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4261 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4262 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4264 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4265 (ins KRC:$mask, SrcRC:$src),
4266 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4269 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4270 (ins KRC:$mask, SrcRC:$src),
4271 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4274 let mayLoad = 1 in {
4275 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4276 (ins x86memop:$src),
4277 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4279 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4282 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4283 (ins KRC:$mask, x86memop:$src),
4284 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4288 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4289 (ins KRC:$mask, x86memop:$src),
4290 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4296 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4297 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4299 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4300 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4302 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4303 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4304 EVEX_CD8<16, CD8VH>;
4305 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4306 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4307 EVEX_CD8<16, CD8VQ>;
4308 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4309 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4310 EVEX_CD8<32, CD8VH>;
4312 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4313 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4315 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4316 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4318 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4319 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4320 EVEX_CD8<16, CD8VH>;
4321 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4322 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4323 EVEX_CD8<16, CD8VQ>;
4324 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4325 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4326 EVEX_CD8<32, CD8VH>;
4328 //===----------------------------------------------------------------------===//
4329 // GATHER - SCATTER Operations
4331 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4332 RegisterClass RC, X86MemOperand memop> {
4334 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4335 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4336 (ins RC:$src1, KRC:$mask, memop:$src2),
4337 !strconcat(OpcodeStr,
4338 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4342 let ExeDomain = SSEPackedDouble in {
4343 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4344 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4345 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4346 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4349 let ExeDomain = SSEPackedSingle in {
4350 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4351 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4352 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4353 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4356 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4357 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4358 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4359 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4361 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4362 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4363 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4364 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4366 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4367 RegisterClass RC, X86MemOperand memop> {
4368 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4369 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4370 (ins memop:$dst, KRC:$mask, RC:$src2),
4371 !strconcat(OpcodeStr,
4372 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4376 let ExeDomain = SSEPackedDouble in {
4377 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4378 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4379 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4380 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4383 let ExeDomain = SSEPackedSingle in {
4384 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4385 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4386 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4387 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4390 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4391 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4392 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4393 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4395 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4396 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4397 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4398 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4401 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4402 RegisterClass KRC, X86MemOperand memop> {
4403 let Predicates = [HasPFI], hasSideEffects = 1 in
4404 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4405 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4409 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4410 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4412 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4413 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4415 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4416 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4418 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4419 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4421 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4422 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4424 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4425 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4427 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4428 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4430 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4431 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4433 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4434 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4436 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4437 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4439 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4440 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4442 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4443 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4445 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4446 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4448 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4449 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4451 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4452 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4454 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4455 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4456 //===----------------------------------------------------------------------===//
4457 // VSHUFPS - VSHUFPD Operations
4459 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4460 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4462 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4463 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4464 !strconcat(OpcodeStr,
4465 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4466 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4467 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4468 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4469 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4470 (ins RC:$src1, RC:$src2, i8imm:$src3),
4471 !strconcat(OpcodeStr,
4472 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4473 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4474 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4475 EVEX_4V, Sched<[WriteShuffle]>;
4478 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4479 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4480 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4481 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4483 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4484 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4485 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4486 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4487 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4489 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4490 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4491 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4492 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4493 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4495 multiclass avx512_valign<string Suffix, RegisterClass RC, RegisterClass KRC,
4496 RegisterClass MRC, X86MemOperand x86memop,
4497 ValueType IntVT, ValueType FloatVT> {
4498 defm rri : AVX512_masking<0x03, MRMSrcReg, (outs RC:$dst),
4499 (ins RC:$src1, RC:$src2, i8imm:$src3),
4501 "$src3, $src2, $src1", "$src1, $src2, $src3",
4502 (IntVT (X86VAlign RC:$src2, RC:$src1,
4505 AVX512AIi8Base, EVEX_4V;
4507 // Also match valign of packed floats.
4508 def : Pat<(FloatVT (X86VAlign RC:$src1, RC:$src2, (i8 imm:$imm))),
4509 (!cast<Instruction>(NAME##rri) RC:$src2, RC:$src1, imm:$imm)>;
4511 // Non-masking intrinsic call.
4513 (!cast<Intrinsic>("int_x86_avx512_mask_valign_"##Suffix##"_512")
4514 RC:$src1, RC:$src2, imm:$src3,
4515 (IntVT (bitconvert (v16i32 immAllZerosV))), -1)),
4516 (!cast<Instruction>(NAME#rri) RC:$src1, RC:$src2, imm:$src3)>;
4518 // Masking intrinsic call.
4520 (!cast<Intrinsic>("int_x86_avx512_mask_valign_"##Suffix##"_512")
4521 RC:$src1, RC:$src2, imm:$src3,
4522 RC:$src4, MRC:$mask)),
4523 (!cast<Instruction>(NAME#rrik) RC:$src4,
4524 (COPY_TO_REGCLASS MRC:$mask, KRC), RC:$src1,
4525 RC:$src2, imm:$src3)>;
4528 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4529 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4530 !strconcat("valign"##Suffix,
4531 " \t{$src3, $src2, $src1, $dst|"
4532 "$dst, $src1, $src2, $src3}"),
4535 defm VALIGND : avx512_valign<"d", VR512, VK16WM, GR16, i512mem, v16i32, v16f32>,
4536 EVEX_V512, EVEX_CD8<32, CD8VF>;
4537 defm VALIGNQ : avx512_valign<"q", VR512, VK8WM, GR8, i512mem, v8i64, v8f64>,
4538 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4540 // Helper fragments to match sext vXi1 to vXiY.
4541 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4542 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4544 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4545 RegisterClass KRC, RegisterClass RC,
4546 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4548 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4549 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4551 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4552 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4554 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4555 !strconcat(OpcodeStr,
4556 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4558 let mayLoad = 1 in {
4559 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4560 (ins x86memop:$src),
4561 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4563 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4564 (ins KRC:$mask, x86memop:$src),
4565 !strconcat(OpcodeStr,
4566 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4568 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4569 (ins KRC:$mask, x86memop:$src),
4570 !strconcat(OpcodeStr,
4571 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4573 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4574 (ins x86scalar_mop:$src),
4575 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4576 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4578 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4579 (ins KRC:$mask, x86scalar_mop:$src),
4580 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4581 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4582 []>, EVEX, EVEX_B, EVEX_K;
4583 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4584 (ins KRC:$mask, x86scalar_mop:$src),
4585 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4586 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4588 []>, EVEX, EVEX_B, EVEX_KZ;
4592 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4593 i512mem, i32mem, "{1to16}">, EVEX_V512,
4594 EVEX_CD8<32, CD8VF>;
4595 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4596 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4597 EVEX_CD8<64, CD8VF>;
4600 (bc_v16i32 (v16i1sextv16i32)),
4601 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4602 (VPABSDZrr VR512:$src)>;
4604 (bc_v8i64 (v8i1sextv8i64)),
4605 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4606 (VPABSQZrr VR512:$src)>;
4608 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4609 (v16i32 immAllZerosV), (i16 -1))),
4610 (VPABSDZrr VR512:$src)>;
4611 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4612 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4613 (VPABSQZrr VR512:$src)>;
4615 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4616 RegisterClass RC, RegisterClass KRC,
4617 X86MemOperand x86memop,
4618 X86MemOperand x86scalar_mop, string BrdcstStr> {
4619 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4621 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4623 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4624 (ins x86memop:$src),
4625 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4627 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4628 (ins x86scalar_mop:$src),
4629 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4630 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4632 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4633 (ins KRC:$mask, RC:$src),
4634 !strconcat(OpcodeStr,
4635 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4637 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4638 (ins KRC:$mask, x86memop:$src),
4639 !strconcat(OpcodeStr,
4640 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4642 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4643 (ins KRC:$mask, x86scalar_mop:$src),
4644 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4645 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4647 []>, EVEX, EVEX_KZ, EVEX_B;
4649 let Constraints = "$src1 = $dst" in {
4650 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4651 (ins RC:$src1, KRC:$mask, RC:$src2),
4652 !strconcat(OpcodeStr,
4653 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4655 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4656 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4657 !strconcat(OpcodeStr,
4658 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4660 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4661 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4662 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4663 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4664 []>, EVEX, EVEX_K, EVEX_B;
4668 let Predicates = [HasCDI] in {
4669 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4670 i512mem, i32mem, "{1to16}">,
4671 EVEX_V512, EVEX_CD8<32, CD8VF>;
4674 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4675 i512mem, i64mem, "{1to8}">,
4676 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4680 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4682 (VPCONFLICTDrrk VR512:$src1,
4683 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4685 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4687 (VPCONFLICTQrrk VR512:$src1,
4688 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4690 let Predicates = [HasCDI] in {
4691 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4692 i512mem, i32mem, "{1to16}">,
4693 EVEX_V512, EVEX_CD8<32, CD8VF>;
4696 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4697 i512mem, i64mem, "{1to8}">,
4698 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4702 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4704 (VPLZCNTDrrk VR512:$src1,
4705 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4707 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4709 (VPLZCNTQrrk VR512:$src1,
4710 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4712 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4713 (VPLZCNTDrm addr:$src)>;
4714 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4715 (VPLZCNTDrr VR512:$src)>;
4716 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4717 (VPLZCNTQrm addr:$src)>;
4718 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4719 (VPLZCNTQrr VR512:$src)>;
4721 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4722 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4723 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4725 def : Pat<(store VK1:$src, addr:$dst),
4726 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4728 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4729 (truncstore node:$val, node:$ptr), [{
4730 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4733 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4734 (MOV8mr addr:$dst, GR8:$src)>;