1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
26 string VTName = "v" # NumElts # EltVT;
29 ValueType VT = !cast<ValueType>(VTName);
31 string EltTypeName = !cast<string>(EltVT);
32 // Size of the element type in bits, e.g. 32 for v16i32.
33 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
34 int EltSize = EltVT.Size;
36 // "i" for integer types and "f" for floating-point types
37 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
39 // Size of RC in bits, e.g. 512 for VR512.
42 // The corresponding memory operand, e.g. i512mem for VR512.
43 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
44 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
47 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
48 // due to load promotion during legalization
49 PatFrag LdFrag = !cast<PatFrag>("load" #
50 !if (!eq (TypeVariantName, "i"),
51 !if (!eq (Size, 128), "v2i64",
52 !if (!eq (Size, 256), "v4i64",
54 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
56 // Load patterns used for memory operands. We only have this defined in
57 // case of i64 element types for sub-512 integer vectors. For now, keep
58 // MemOpFrag undefined in these cases.
60 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
62 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
64 // The corresponding float type, e.g. v16f32 for v16i32
65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
89 // A vector type of the same width with element type i32. This is used to
90 // create the canonical constant zero node ImmAllZerosV.
91 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
92 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
95 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
96 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
97 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
98 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
99 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
100 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
102 // "x" in v32i8x_info means RC = VR256X
103 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
104 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
105 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
106 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
107 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
108 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
110 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
111 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
112 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
113 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
114 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
115 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
117 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
118 X86VectorVTInfo i128> {
119 X86VectorVTInfo info512 = i512;
120 X86VectorVTInfo info256 = i256;
121 X86VectorVTInfo info128 = i128;
124 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
126 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
128 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
130 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
132 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
134 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
137 // This multiclass generates the masking variants from the non-masking
138 // variant. It only provides the assembly pieces for the masking variants.
139 // It assumes custom ISel patterns for masking which can be provided as
140 // template arguments.
141 multiclass AVX512_maskable_custom<bits<8> O, Format F,
143 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
145 string AttSrcAsm, string IntelSrcAsm,
147 list<dag> MaskingPattern,
148 list<dag> ZeroMaskingPattern,
150 string MaskingConstraint = "",
151 InstrItinClass itin = NoItinerary,
152 bit IsCommutable = 0> {
153 let isCommutable = IsCommutable in
154 def NAME: AVX512<O, F, Outs, Ins,
155 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
156 "$dst "#Round#", "#IntelSrcAsm#"}",
159 // Prefer over VMOV*rrk Pat<>
160 let AddedComplexity = 20 in
161 def NAME#k: AVX512<O, F, Outs, MaskingIns,
162 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
163 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
164 MaskingPattern, itin>,
166 // In case of the 3src subclass this is overridden with a let.
167 string Constraints = MaskingConstraint;
169 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
170 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
171 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
172 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
179 // Common base class of AVX512_maskable and AVX512_maskable_3src.
180 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
182 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
184 string AttSrcAsm, string IntelSrcAsm,
185 dag RHS, dag MaskingRHS,
187 string MaskingConstraint = "",
188 InstrItinClass itin = NoItinerary,
189 bit IsCommutable = 0> :
190 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
191 AttSrcAsm, IntelSrcAsm,
192 [(set _.RC:$dst, RHS)],
193 [(set _.RC:$dst, MaskingRHS)],
195 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
196 Round, MaskingConstraint, NoItinerary, IsCommutable>;
198 // This multiclass generates the unconditional/non-masking, the masking and
199 // the zero-masking variant of the instruction. In the masking case, the
200 // perserved vector elements come from a new dummy input operand tied to $dst.
201 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
202 dag Outs, dag Ins, string OpcodeStr,
203 string AttSrcAsm, string IntelSrcAsm,
204 dag RHS, string Round = "",
205 InstrItinClass itin = NoItinerary,
206 bit IsCommutable = 0> :
207 AVX512_maskable_common<O, F, _, Outs, Ins,
208 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
209 !con((ins _.KRCWM:$mask), Ins),
210 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
211 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), Round,
212 "$src0 = $dst", itin, IsCommutable>;
214 // Similar to AVX512_maskable but in this case one of the source operands
215 // ($src1) is already tied to $dst so we just use that for the preserved
216 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
218 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
219 dag Outs, dag NonTiedIns, string OpcodeStr,
220 string AttSrcAsm, string IntelSrcAsm,
222 AVX512_maskable_common<O, F, _, Outs,
223 !con((ins _.RC:$src1), NonTiedIns),
224 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
225 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
226 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
227 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
230 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
233 string AttSrcAsm, string IntelSrcAsm,
235 AVX512_maskable_custom<O, F, Outs, Ins,
236 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
237 !con((ins _.KRCWM:$mask), Ins),
238 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
241 // Bitcasts between 512-bit vector types. Return the original type since
242 // no instruction is needed for the conversion
243 let Predicates = [HasAVX512] in {
244 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
245 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
246 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
247 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
248 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
249 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
250 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
251 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
252 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
253 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
254 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
255 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
256 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
257 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
258 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
259 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
260 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
261 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
262 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
263 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
264 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
265 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
266 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
267 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
268 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
269 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
270 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
271 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
272 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
273 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
274 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
276 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
277 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
278 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
279 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
280 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
281 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
282 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
283 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
284 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
285 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
286 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
287 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
288 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
289 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
290 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
291 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
292 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
293 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
294 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
295 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
296 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
297 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
298 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
299 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
300 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
301 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
302 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
303 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
304 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
305 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
307 // Bitcasts between 256-bit vector types. Return the original type since
308 // no instruction is needed for the conversion
309 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
310 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
311 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
312 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
313 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
314 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
315 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
316 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
317 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
318 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
319 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
320 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
321 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
322 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
323 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
324 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
325 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
326 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
327 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
328 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
329 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
330 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
331 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
332 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
333 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
334 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
335 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
336 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
337 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
338 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
342 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
345 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
346 isPseudo = 1, Predicates = [HasAVX512] in {
347 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
348 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
351 let Predicates = [HasAVX512] in {
352 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
353 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
354 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
357 //===----------------------------------------------------------------------===//
358 // AVX-512 - VECTOR INSERT
361 multiclass vinsert_for_size_no_alt<int Opcode,
362 X86VectorVTInfo From, X86VectorVTInfo To,
363 PatFrag vinsert_insert,
364 SDNodeXForm INSERT_get_vinsert_imm> {
365 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
366 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
367 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
368 "vinsert" # From.EltTypeName # "x" # From.NumElts #
369 "\t{$src3, $src2, $src1, $dst|"
370 "$dst, $src1, $src2, $src3}",
371 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
372 (From.VT From.RC:$src2),
377 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
378 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
379 "vinsert" # From.EltTypeName # "x" # From.NumElts #
380 "\t{$src3, $src2, $src1, $dst|"
381 "$dst, $src1, $src2, $src3}",
383 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
387 multiclass vinsert_for_size<int Opcode,
388 X86VectorVTInfo From, X86VectorVTInfo To,
389 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
390 PatFrag vinsert_insert,
391 SDNodeXForm INSERT_get_vinsert_imm> :
392 vinsert_for_size_no_alt<Opcode, From, To,
393 vinsert_insert, INSERT_get_vinsert_imm> {
394 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
395 // vinserti32x4. Only add this if 64x2 and friends are not supported
396 // natively via AVX512DQ.
397 let Predicates = [NoDQI] in
398 def : Pat<(vinsert_insert:$ins
399 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
400 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
401 VR512:$src1, From.RC:$src2,
402 (INSERT_get_vinsert_imm VR512:$ins)))>;
405 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
406 ValueType EltVT64, int Opcode256> {
407 defm NAME # "32x4" : vinsert_for_size<Opcode128,
408 X86VectorVTInfo< 4, EltVT32, VR128X>,
409 X86VectorVTInfo<16, EltVT32, VR512>,
410 X86VectorVTInfo< 2, EltVT64, VR128X>,
411 X86VectorVTInfo< 8, EltVT64, VR512>,
413 INSERT_get_vinsert128_imm>;
414 let Predicates = [HasDQI] in
415 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
416 X86VectorVTInfo< 2, EltVT64, VR128X>,
417 X86VectorVTInfo< 8, EltVT64, VR512>,
419 INSERT_get_vinsert128_imm>, VEX_W;
420 defm NAME # "64x4" : vinsert_for_size<Opcode256,
421 X86VectorVTInfo< 4, EltVT64, VR256X>,
422 X86VectorVTInfo< 8, EltVT64, VR512>,
423 X86VectorVTInfo< 8, EltVT32, VR256>,
424 X86VectorVTInfo<16, EltVT32, VR512>,
426 INSERT_get_vinsert256_imm>, VEX_W;
427 let Predicates = [HasDQI] in
428 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
429 X86VectorVTInfo< 8, EltVT32, VR256X>,
430 X86VectorVTInfo<16, EltVT32, VR512>,
432 INSERT_get_vinsert256_imm>;
435 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
436 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
438 // vinsertps - insert f32 to XMM
439 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
440 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
441 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
442 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
444 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
445 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
446 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
447 [(set VR128X:$dst, (X86insertps VR128X:$src1,
448 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
449 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
451 //===----------------------------------------------------------------------===//
452 // AVX-512 VECTOR EXTRACT
455 multiclass vextract_for_size<int Opcode,
456 X86VectorVTInfo From, X86VectorVTInfo To,
457 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
458 PatFrag vextract_extract,
459 SDNodeXForm EXTRACT_get_vextract_imm> {
460 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
461 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
462 (ins VR512:$src1, i8imm:$idx),
463 "vextract" # To.EltTypeName # "x4",
464 "$idx, $src1", "$src1, $idx",
465 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
467 AVX512AIi8Base, EVEX, EVEX_V512;
469 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
470 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
471 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
472 "$dst, $src1, $src2}",
473 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
476 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
478 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
479 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
481 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
483 // A 128/256-bit subvector extract from the first 512-bit vector position is
484 // a subregister copy that needs no instruction.
485 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
487 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
489 // And for the alternative types.
490 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
492 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
494 // Intrinsic call with masking.
495 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
497 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
498 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
499 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
500 VR512:$src1, imm:$idx)>;
502 // Intrinsic call with zero-masking.
503 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
505 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
506 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
507 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
508 VR512:$src1, imm:$idx)>;
510 // Intrinsic call without masking.
511 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
513 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
514 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
515 VR512:$src1, imm:$idx)>;
518 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
519 ValueType EltVT64, int Opcode64> {
520 defm NAME # "32x4" : vextract_for_size<Opcode32,
521 X86VectorVTInfo<16, EltVT32, VR512>,
522 X86VectorVTInfo< 4, EltVT32, VR128X>,
523 X86VectorVTInfo< 8, EltVT64, VR512>,
524 X86VectorVTInfo< 2, EltVT64, VR128X>,
526 EXTRACT_get_vextract128_imm>;
527 defm NAME # "64x4" : vextract_for_size<Opcode64,
528 X86VectorVTInfo< 8, EltVT64, VR512>,
529 X86VectorVTInfo< 4, EltVT64, VR256X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 X86VectorVTInfo< 8, EltVT32, VR256>,
533 EXTRACT_get_vextract256_imm>, VEX_W;
536 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
537 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
539 // A 128-bit subvector insert to the first 512-bit vector position
540 // is a subregister copy that needs no instruction.
541 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
542 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
543 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
545 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
546 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
547 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
549 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
550 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
551 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
553 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
554 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
555 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
558 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
559 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
560 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
561 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
562 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
563 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
564 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
565 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
567 // vextractps - extract 32 bits from XMM
568 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
569 (ins VR128X:$src1, i32i8imm:$src2),
570 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
571 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
574 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
575 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
576 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
577 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
578 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
580 //===---------------------------------------------------------------------===//
583 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
584 ValueType svt, X86VectorVTInfo _> {
585 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
586 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
587 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
591 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
592 (ins _.ScalarMemOp:$src),
593 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
594 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
599 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
600 AVX512VLVectorVTInfo _> {
601 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
604 let Predicates = [HasVLX] in {
605 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
610 let ExeDomain = SSEPackedSingle in {
611 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
612 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
613 let Predicates = [HasVLX] in {
614 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
615 v4f32, v4f32x_info>, EVEX_V128,
616 EVEX_CD8<32, CD8VT1>;
620 let ExeDomain = SSEPackedDouble in {
621 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
622 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
625 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
626 (VBROADCASTSSZm addr:$src)>;
627 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
628 (VBROADCASTSDZm addr:$src)>;
630 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
631 (VBROADCASTSSZm addr:$src)>;
632 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
633 (VBROADCASTSDZm addr:$src)>;
635 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
636 RegisterClass SrcRC, RegisterClass KRC> {
637 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
638 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
639 []>, EVEX, EVEX_V512;
640 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
641 (ins KRC:$mask, SrcRC:$src),
642 !strconcat(OpcodeStr,
643 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
644 []>, EVEX, EVEX_V512, EVEX_KZ;
647 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
648 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
651 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
652 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
654 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
655 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
657 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
658 (VPBROADCASTDrZrr GR32:$src)>;
659 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
660 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
661 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
662 (VPBROADCASTQrZrr GR64:$src)>;
663 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
664 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
666 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
667 (VPBROADCASTDrZrr GR32:$src)>;
668 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
669 (VPBROADCASTQrZrr GR64:$src)>;
671 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
672 (v16i32 immAllZerosV), (i16 GR16:$mask))),
673 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
674 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
675 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
676 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
678 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
679 X86MemOperand x86memop, PatFrag ld_frag,
680 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
682 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
683 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
685 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
686 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
688 !strconcat(OpcodeStr,
689 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
691 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
694 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
695 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
697 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
698 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
700 !strconcat(OpcodeStr,
701 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
702 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
703 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
707 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
708 loadi32, VR512, v16i32, v4i32, VK16WM>,
709 EVEX_V512, EVEX_CD8<32, CD8VT1>;
710 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
711 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
712 EVEX_CD8<64, CD8VT1>;
714 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
715 X86MemOperand x86memop, PatFrag ld_frag,
718 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
719 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
721 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
723 !strconcat(OpcodeStr,
724 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
729 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
730 i128mem, loadv2i64, VK16WM>,
731 EVEX_V512, EVEX_CD8<32, CD8VT4>;
732 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
733 i256mem, loadv4i64, VK16WM>, VEX_W,
734 EVEX_V512, EVEX_CD8<64, CD8VT4>;
736 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
737 (VPBROADCASTDZrr VR128X:$src)>;
738 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
739 (VPBROADCASTQZrr VR128X:$src)>;
741 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
742 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
743 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
744 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
746 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
747 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
748 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
749 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
751 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
752 (VBROADCASTSSZr VR128X:$src)>;
753 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
754 (VBROADCASTSDZr VR128X:$src)>;
756 // Provide fallback in case the load node that is used in the patterns above
757 // is used by additional users, which prevents the pattern selection.
758 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
759 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
760 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
761 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
764 let Predicates = [HasAVX512] in {
765 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
767 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
768 addr:$src)), sub_ymm)>;
770 //===----------------------------------------------------------------------===//
771 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
774 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
776 let Predicates = [HasCDI] in
777 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
778 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
779 []>, EVEX, EVEX_V512;
781 let Predicates = [HasCDI, HasVLX] in {
782 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
783 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
784 []>, EVEX, EVEX_V128;
785 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
786 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
787 []>, EVEX, EVEX_V256;
791 let Predicates = [HasCDI] in {
792 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
794 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
798 //===----------------------------------------------------------------------===//
801 // -- immediate form --
802 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
804 let ExeDomain = _.ExeDomain in {
805 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
806 (ins _.RC:$src1, i8imm:$src2),
807 !strconcat(OpcodeStr,
808 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
810 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
812 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
813 (ins _.MemOp:$src1, i8imm:$src2),
814 !strconcat(OpcodeStr,
815 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
817 (_.VT (OpNode (_.MemOpFrag addr:$src1),
819 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
823 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
824 X86VectorVTInfo Ctrl> :
825 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
826 let ExeDomain = _.ExeDomain in {
827 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
828 (ins _.RC:$src1, _.RC:$src2),
829 !strconcat("vpermil" # _.Suffix,
830 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
832 (_.VT (X86VPermilpv _.RC:$src1,
833 (Ctrl.VT Ctrl.RC:$src2))))]>,
835 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
836 (ins _.RC:$src1, Ctrl.MemOp:$src2),
837 !strconcat("vpermil" # _.Suffix,
838 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
840 (_.VT (X86VPermilpv _.RC:$src1,
841 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
846 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
848 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
851 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
853 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
856 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
857 (VPERMILPSZri VR512:$src1, imm:$imm)>;
858 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
859 (VPERMILPDZri VR512:$src1, imm:$imm)>;
861 // -- VPERM - register form --
862 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
863 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
865 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
866 (ins RC:$src1, RC:$src2),
867 !strconcat(OpcodeStr,
868 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
870 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
872 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
873 (ins RC:$src1, x86memop:$src2),
874 !strconcat(OpcodeStr,
875 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
877 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
881 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
882 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
883 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
884 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
885 let ExeDomain = SSEPackedSingle in
886 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
887 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
888 let ExeDomain = SSEPackedDouble in
889 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
890 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
892 // -- VPERM2I - 3 source operands form --
893 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
894 PatFrag mem_frag, X86MemOperand x86memop,
895 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
896 let Constraints = "$src1 = $dst" in {
897 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
898 (ins RC:$src1, RC:$src2, RC:$src3),
899 !strconcat(OpcodeStr,
900 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
902 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
905 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
906 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
907 !strconcat(OpcodeStr,
908 " \t{$src3, $src2, $dst {${mask}}|"
909 "$dst {${mask}}, $src2, $src3}"),
910 [(set RC:$dst, (OpVT (vselect KRC:$mask,
911 (OpNode RC:$src1, RC:$src2,
916 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
917 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
918 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
919 !strconcat(OpcodeStr,
920 " \t{$src3, $src2, $dst {${mask}} {z} |",
921 "$dst {${mask}} {z}, $src2, $src3}"),
922 [(set RC:$dst, (OpVT (vselect KRC:$mask,
923 (OpNode RC:$src1, RC:$src2,
926 (v16i32 immAllZerosV))))))]>,
929 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
930 (ins RC:$src1, RC:$src2, x86memop:$src3),
931 !strconcat(OpcodeStr,
932 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
934 (OpVT (OpNode RC:$src1, RC:$src2,
935 (mem_frag addr:$src3))))]>, EVEX_4V;
937 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
938 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
939 !strconcat(OpcodeStr,
940 " \t{$src3, $src2, $dst {${mask}}|"
941 "$dst {${mask}}, $src2, $src3}"),
943 (OpVT (vselect KRC:$mask,
944 (OpNode RC:$src1, RC:$src2,
945 (mem_frag addr:$src3)),
949 let AddedComplexity = 10 in // Prefer over the rrkz variant
950 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
951 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
952 !strconcat(OpcodeStr,
953 " \t{$src3, $src2, $dst {${mask}} {z}|"
954 "$dst {${mask}} {z}, $src2, $src3}"),
956 (OpVT (vselect KRC:$mask,
957 (OpNode RC:$src1, RC:$src2,
958 (mem_frag addr:$src3)),
960 (v16i32 immAllZerosV))))))]>,
964 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
965 i512mem, X86VPermiv3, v16i32, VK16WM>,
966 EVEX_V512, EVEX_CD8<32, CD8VF>;
967 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
968 i512mem, X86VPermiv3, v8i64, VK8WM>,
969 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
970 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
971 i512mem, X86VPermiv3, v16f32, VK16WM>,
972 EVEX_V512, EVEX_CD8<32, CD8VF>;
973 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
974 i512mem, X86VPermiv3, v8f64, VK8WM>,
975 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
977 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
978 PatFrag mem_frag, X86MemOperand x86memop,
979 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
980 ValueType MaskVT, RegisterClass MRC> :
981 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
983 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
984 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
985 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
987 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
988 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
989 (!cast<Instruction>(NAME#rrk) VR512:$src1,
990 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
993 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
994 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
995 EVEX_V512, EVEX_CD8<32, CD8VF>;
996 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
997 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
998 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
999 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1000 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1001 EVEX_V512, EVEX_CD8<32, CD8VF>;
1002 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1003 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1004 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1006 //===----------------------------------------------------------------------===//
1007 // AVX-512 - BLEND using mask
1009 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
1010 RegisterClass KRC, RegisterClass RC,
1011 X86MemOperand x86memop, PatFrag mem_frag,
1012 SDNode OpNode, ValueType vt> {
1013 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1014 (ins KRC:$mask, RC:$src1, RC:$src2),
1015 !strconcat(OpcodeStr,
1016 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1017 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
1018 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
1020 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1021 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1022 !strconcat(OpcodeStr,
1023 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1024 []>, EVEX_4V, EVEX_K;
1027 let ExeDomain = SSEPackedSingle in
1028 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1029 VK16WM, VR512, f512mem,
1030 memopv16f32, vselect, v16f32>,
1031 EVEX_CD8<32, CD8VF>, EVEX_V512;
1032 let ExeDomain = SSEPackedDouble in
1033 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1034 VK8WM, VR512, f512mem,
1035 memopv8f64, vselect, v8f64>,
1036 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1038 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1039 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1040 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1041 VR512:$src1, VR512:$src2)>;
1043 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1044 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1045 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1046 VR512:$src1, VR512:$src2)>;
1048 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1049 VK16WM, VR512, f512mem,
1050 memopv16i32, vselect, v16i32>,
1051 EVEX_CD8<32, CD8VF>, EVEX_V512;
1053 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1054 VK8WM, VR512, f512mem,
1055 memopv8i64, vselect, v8i64>,
1056 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1058 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1059 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1060 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1061 VR512:$src1, VR512:$src2)>;
1063 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1064 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1065 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1066 VR512:$src1, VR512:$src2)>;
1068 let Predicates = [HasAVX512] in {
1069 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1070 (v8f32 VR256X:$src2))),
1072 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1073 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1074 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1076 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1077 (v8i32 VR256X:$src2))),
1079 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1080 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1081 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1083 //===----------------------------------------------------------------------===//
1084 // Compare Instructions
1085 //===----------------------------------------------------------------------===//
1087 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1088 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1089 Operand CC, SDNode OpNode, ValueType VT,
1090 PatFrag ld_frag, string asm, string asm_alt> {
1091 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1092 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1093 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1094 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1095 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1096 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1097 [(set VK1:$dst, (OpNode (VT RC:$src1),
1098 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1099 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1100 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1101 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1102 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1103 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1104 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1105 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1109 let Predicates = [HasAVX512] in {
1110 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1111 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1112 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1114 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1115 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1116 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1120 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1121 X86VectorVTInfo _> {
1122 def rr : AVX512BI<opc, MRMSrcReg,
1123 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1124 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1125 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1126 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1128 def rm : AVX512BI<opc, MRMSrcMem,
1129 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1130 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1131 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1132 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1133 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1134 def rrk : AVX512BI<opc, MRMSrcReg,
1135 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1136 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1137 "$dst {${mask}}, $src1, $src2}"),
1138 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1139 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1140 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1142 def rmk : AVX512BI<opc, MRMSrcMem,
1143 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1144 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1145 "$dst {${mask}}, $src1, $src2}"),
1146 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1147 (OpNode (_.VT _.RC:$src1),
1149 (_.LdFrag addr:$src2))))))],
1150 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1153 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1154 X86VectorVTInfo _> :
1155 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1156 let mayLoad = 1 in {
1157 def rmb : AVX512BI<opc, MRMSrcMem,
1158 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1159 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1160 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1161 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1162 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1163 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1164 def rmbk : AVX512BI<opc, MRMSrcMem,
1165 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1166 _.ScalarMemOp:$src2),
1167 !strconcat(OpcodeStr,
1168 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1169 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1170 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1171 (OpNode (_.VT _.RC:$src1),
1173 (_.ScalarLdFrag addr:$src2)))))],
1174 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1178 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1179 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1180 let Predicates = [prd] in
1181 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1184 let Predicates = [prd, HasVLX] in {
1185 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1187 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1192 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1193 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1195 let Predicates = [prd] in
1196 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1199 let Predicates = [prd, HasVLX] in {
1200 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1202 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1207 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1208 avx512vl_i8_info, HasBWI>,
1211 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1212 avx512vl_i16_info, HasBWI>,
1213 EVEX_CD8<16, CD8VF>;
1215 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1216 avx512vl_i32_info, HasAVX512>,
1217 EVEX_CD8<32, CD8VF>;
1219 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1220 avx512vl_i64_info, HasAVX512>,
1221 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1223 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1224 avx512vl_i8_info, HasBWI>,
1227 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1228 avx512vl_i16_info, HasBWI>,
1229 EVEX_CD8<16, CD8VF>;
1231 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1232 avx512vl_i32_info, HasAVX512>,
1233 EVEX_CD8<32, CD8VF>;
1235 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1236 avx512vl_i64_info, HasAVX512>,
1237 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1239 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1240 (COPY_TO_REGCLASS (VPCMPGTDZrr
1241 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1242 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1244 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1245 (COPY_TO_REGCLASS (VPCMPEQDZrr
1246 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1247 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1249 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1250 X86VectorVTInfo _> {
1251 def rri : AVX512AIi8<opc, MRMSrcReg,
1252 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1253 !strconcat("vpcmp${cc}", Suffix,
1254 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1255 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1257 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1259 def rmi : AVX512AIi8<opc, MRMSrcMem,
1260 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1261 !strconcat("vpcmp${cc}", Suffix,
1262 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1263 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1264 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1266 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1267 def rrik : AVX512AIi8<opc, MRMSrcReg,
1268 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1270 !strconcat("vpcmp${cc}", Suffix,
1271 "\t{$src2, $src1, $dst {${mask}}|",
1272 "$dst {${mask}}, $src1, $src2}"),
1273 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1274 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1276 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1278 def rmik : AVX512AIi8<opc, MRMSrcMem,
1279 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1281 !strconcat("vpcmp${cc}", Suffix,
1282 "\t{$src2, $src1, $dst {${mask}}|",
1283 "$dst {${mask}}, $src1, $src2}"),
1284 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1285 (OpNode (_.VT _.RC:$src1),
1286 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1288 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1290 // Accept explicit immediate argument form instead of comparison code.
1291 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1292 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1293 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1294 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1295 "$dst, $src1, $src2, $cc}"),
1296 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1297 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1298 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1299 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1300 "$dst, $src1, $src2, $cc}"),
1301 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1302 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1303 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1305 !strconcat("vpcmp", Suffix,
1306 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1307 "$dst {${mask}}, $src1, $src2, $cc}"),
1308 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1309 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1310 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1312 !strconcat("vpcmp", Suffix,
1313 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1314 "$dst {${mask}}, $src1, $src2, $cc}"),
1315 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1319 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1320 X86VectorVTInfo _> :
1321 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1322 let mayLoad = 1 in {
1323 def rmib : AVX512AIi8<opc, MRMSrcMem,
1324 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1326 !strconcat("vpcmp${cc}", Suffix,
1327 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1328 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1329 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1330 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1332 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1333 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1334 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1335 _.ScalarMemOp:$src2, AVXCC:$cc),
1336 !strconcat("vpcmp${cc}", Suffix,
1337 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1338 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1339 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1340 (OpNode (_.VT _.RC:$src1),
1341 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1343 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1346 // Accept explicit immediate argument form instead of comparison code.
1347 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1348 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1349 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1351 !strconcat("vpcmp", Suffix,
1352 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1353 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1354 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1355 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1356 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1357 _.ScalarMemOp:$src2, i8imm:$cc),
1358 !strconcat("vpcmp", Suffix,
1359 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1360 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1361 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1365 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1366 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1367 let Predicates = [prd] in
1368 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1370 let Predicates = [prd, HasVLX] in {
1371 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1372 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1376 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1377 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1378 let Predicates = [prd] in
1379 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1382 let Predicates = [prd, HasVLX] in {
1383 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1385 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1390 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1391 HasBWI>, EVEX_CD8<8, CD8VF>;
1392 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1393 HasBWI>, EVEX_CD8<8, CD8VF>;
1395 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1396 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1397 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1398 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1400 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1401 HasAVX512>, EVEX_CD8<32, CD8VF>;
1402 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1403 HasAVX512>, EVEX_CD8<32, CD8VF>;
1405 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1406 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1407 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1408 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1410 // avx512_cmp_packed - compare packed instructions
1411 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1412 X86MemOperand x86memop, ValueType vt,
1413 string suffix, Domain d> {
1414 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1415 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1416 !strconcat("vcmp${cc}", suffix,
1417 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1418 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1419 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1420 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1421 !strconcat("vcmp${cc}", suffix,
1422 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1424 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1425 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1426 !strconcat("vcmp${cc}", suffix,
1427 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1429 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1431 // Accept explicit immediate argument form instead of comparison code.
1432 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1433 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1434 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1435 !strconcat("vcmp", suffix,
1436 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1437 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1438 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1439 !strconcat("vcmp", suffix,
1440 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1444 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1445 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1446 EVEX_CD8<32, CD8VF>;
1447 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1448 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1449 EVEX_CD8<64, CD8VF>;
1451 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1452 (COPY_TO_REGCLASS (VCMPPSZrri
1453 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1454 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1456 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1457 (COPY_TO_REGCLASS (VPCMPDZrri
1458 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1459 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1461 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1462 (COPY_TO_REGCLASS (VPCMPUDZrri
1463 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1464 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1467 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1468 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1470 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1471 (I8Imm imm:$cc)), GR16)>;
1473 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1474 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1476 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1477 (I8Imm imm:$cc)), GR8)>;
1479 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1480 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1482 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1483 (I8Imm imm:$cc)), GR16)>;
1485 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1486 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1488 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1489 (I8Imm imm:$cc)), GR8)>;
1491 // Mask register copy, including
1492 // - copy between mask registers
1493 // - load/store mask registers
1494 // - copy from GPR to mask register and vice versa
1496 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1497 string OpcodeStr, RegisterClass KRC,
1498 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1499 let hasSideEffects = 0 in {
1500 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1501 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1503 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1504 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1505 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1507 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1508 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1512 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1514 RegisterClass KRC, RegisterClass GRC> {
1515 let hasSideEffects = 0 in {
1516 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1517 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1518 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1519 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1523 let Predicates = [HasDQI] in
1524 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1526 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1529 let Predicates = [HasAVX512] in
1530 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1532 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1535 let Predicates = [HasBWI] in {
1536 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1537 i32mem>, VEX, PD, VEX_W;
1538 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1542 let Predicates = [HasBWI] in {
1543 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1544 i64mem>, VEX, PS, VEX_W;
1545 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1549 // GR from/to mask register
1550 let Predicates = [HasDQI] in {
1551 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1552 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1553 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1554 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1556 let Predicates = [HasAVX512] in {
1557 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1558 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1559 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1560 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1562 let Predicates = [HasBWI] in {
1563 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1564 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1566 let Predicates = [HasBWI] in {
1567 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1568 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1572 let Predicates = [HasDQI] in {
1573 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1574 (KMOVBmk addr:$dst, VK8:$src)>;
1576 let Predicates = [HasAVX512] in {
1577 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1578 (KMOVWmk addr:$dst, VK16:$src)>;
1579 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1580 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1581 def : Pat<(i1 (load addr:$src)),
1582 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1583 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1584 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1586 let Predicates = [HasBWI] in {
1587 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1588 (KMOVDmk addr:$dst, VK32:$src)>;
1590 let Predicates = [HasBWI] in {
1591 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1592 (KMOVQmk addr:$dst, VK64:$src)>;
1595 let Predicates = [HasAVX512] in {
1596 def : Pat<(i1 (trunc (i64 GR64:$src))),
1597 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1600 def : Pat<(i1 (trunc (i32 GR32:$src))),
1601 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1603 def : Pat<(i1 (trunc (i8 GR8:$src))),
1605 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1607 def : Pat<(i1 (trunc (i16 GR16:$src))),
1609 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1612 def : Pat<(i32 (zext VK1:$src)),
1613 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1614 def : Pat<(i8 (zext VK1:$src)),
1617 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1618 def : Pat<(i64 (zext VK1:$src)),
1619 (AND64ri8 (SUBREG_TO_REG (i64 0),
1620 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1621 def : Pat<(i16 (zext VK1:$src)),
1623 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1625 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1626 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1627 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1628 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1630 let Predicates = [HasBWI] in {
1631 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1632 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1633 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1634 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1638 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1639 let Predicates = [HasAVX512] in {
1640 // GR from/to 8-bit mask without native support
1641 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1643 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1645 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1647 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1650 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1651 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1652 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1653 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1655 let Predicates = [HasBWI] in {
1656 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1657 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1658 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1659 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1662 // Mask unary operation
1664 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1665 RegisterClass KRC, SDPatternOperator OpNode,
1667 let Predicates = [prd] in
1668 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1669 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1670 [(set KRC:$dst, (OpNode KRC:$src))]>;
1673 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1674 SDPatternOperator OpNode> {
1675 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1677 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1678 HasAVX512>, VEX, PS;
1679 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1680 HasBWI>, VEX, PD, VEX_W;
1681 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1682 HasBWI>, VEX, PS, VEX_W;
1685 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1687 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1688 let Predicates = [HasAVX512] in
1689 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1691 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1692 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1694 defm : avx512_mask_unop_int<"knot", "KNOT">;
1696 let Predicates = [HasDQI] in
1697 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1698 let Predicates = [HasAVX512] in
1699 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1700 let Predicates = [HasBWI] in
1701 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1702 let Predicates = [HasBWI] in
1703 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1705 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1706 let Predicates = [HasAVX512] in {
1707 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1708 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1710 def : Pat<(not VK8:$src),
1712 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1715 // Mask binary operation
1716 // - KAND, KANDN, KOR, KXNOR, KXOR
1717 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1718 RegisterClass KRC, SDPatternOperator OpNode,
1720 let Predicates = [prd] in
1721 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1722 !strconcat(OpcodeStr,
1723 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1724 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1727 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1728 SDPatternOperator OpNode> {
1729 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1730 HasDQI>, VEX_4V, VEX_L, PD;
1731 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1732 HasAVX512>, VEX_4V, VEX_L, PS;
1733 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1734 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1735 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1736 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1739 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1740 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1742 let isCommutable = 1 in {
1743 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1744 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1745 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1746 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1748 let isCommutable = 0 in
1749 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1751 def : Pat<(xor VK1:$src1, VK1:$src2),
1752 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1753 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1755 def : Pat<(or VK1:$src1, VK1:$src2),
1756 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1757 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1759 def : Pat<(and VK1:$src1, VK1:$src2),
1760 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1761 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1763 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1764 let Predicates = [HasAVX512] in
1765 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1766 (i16 GR16:$src1), (i16 GR16:$src2)),
1767 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1768 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1769 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1772 defm : avx512_mask_binop_int<"kand", "KAND">;
1773 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1774 defm : avx512_mask_binop_int<"kor", "KOR">;
1775 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1776 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1778 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1779 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1780 let Predicates = [HasAVX512] in
1781 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1783 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1784 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1787 defm : avx512_binop_pat<and, KANDWrr>;
1788 defm : avx512_binop_pat<andn, KANDNWrr>;
1789 defm : avx512_binop_pat<or, KORWrr>;
1790 defm : avx512_binop_pat<xnor, KXNORWrr>;
1791 defm : avx512_binop_pat<xor, KXORWrr>;
1794 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1795 RegisterClass KRC> {
1796 let Predicates = [HasAVX512] in
1797 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1798 !strconcat(OpcodeStr,
1799 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1802 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1803 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1807 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1808 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1809 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1810 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1813 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1814 let Predicates = [HasAVX512] in
1815 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1816 (i16 GR16:$src1), (i16 GR16:$src2)),
1817 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1818 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1819 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1821 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1824 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1826 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1827 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1828 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1829 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1832 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1833 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1837 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1839 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1840 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1841 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1844 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1846 let Predicates = [HasAVX512] in
1847 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1848 !strconcat(OpcodeStr,
1849 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1850 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1853 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1855 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1859 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1860 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1862 // Mask setting all 0s or 1s
1863 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1864 let Predicates = [HasAVX512] in
1865 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1866 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1867 [(set KRC:$dst, (VT Val))]>;
1870 multiclass avx512_mask_setop_w<PatFrag Val> {
1871 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1872 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1875 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1876 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1878 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1879 let Predicates = [HasAVX512] in {
1880 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1881 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1882 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1883 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1884 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1886 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1887 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1889 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1890 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1892 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1893 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1895 let Predicates = [HasVLX] in {
1896 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1897 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1898 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1899 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1900 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1901 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1902 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1903 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1906 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1907 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1909 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1910 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1911 //===----------------------------------------------------------------------===//
1912 // AVX-512 - Aligned and unaligned load and store
1915 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1916 RegisterClass KRC, RegisterClass RC,
1917 ValueType vt, ValueType zvt, X86MemOperand memop,
1918 Domain d, bit IsReMaterializable = 1> {
1919 let hasSideEffects = 0 in {
1920 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1921 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1923 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1924 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1925 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1927 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1928 SchedRW = [WriteLoad] in
1929 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1930 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1931 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1934 let AddedComplexity = 20 in {
1935 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1936 let hasSideEffects = 0 in
1937 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1938 (ins RC:$src0, KRC:$mask, RC:$src1),
1939 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1940 "${dst} {${mask}}, $src1}"),
1941 [(set RC:$dst, (vt (vselect KRC:$mask,
1945 let mayLoad = 1, SchedRW = [WriteLoad] in
1946 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1947 (ins RC:$src0, KRC:$mask, memop:$src1),
1948 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1949 "${dst} {${mask}}, $src1}"),
1952 (vt (bitconvert (ld_frag addr:$src1))),
1956 let mayLoad = 1, SchedRW = [WriteLoad] in
1957 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1958 (ins KRC:$mask, memop:$src),
1959 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1960 "${dst} {${mask}} {z}, $src}"),
1963 (vt (bitconvert (ld_frag addr:$src))),
1964 (vt (bitconvert (zvt immAllZerosV))))))],
1969 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1970 string elty, string elsz, string vsz512,
1971 string vsz256, string vsz128, Domain d,
1972 Predicate prd, bit IsReMaterializable = 1> {
1973 let Predicates = [prd] in
1974 defm Z : avx512_load<opc, OpcodeStr,
1975 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1976 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1977 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1978 !cast<X86MemOperand>(elty##"512mem"), d,
1979 IsReMaterializable>, EVEX_V512;
1981 let Predicates = [prd, HasVLX] in {
1982 defm Z256 : avx512_load<opc, OpcodeStr,
1983 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1984 "v"##vsz256##elty##elsz, "v4i64")),
1985 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1986 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1987 !cast<X86MemOperand>(elty##"256mem"), d,
1988 IsReMaterializable>, EVEX_V256;
1990 defm Z128 : avx512_load<opc, OpcodeStr,
1991 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1992 "v"##vsz128##elty##elsz, "v2i64")),
1993 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1994 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1995 !cast<X86MemOperand>(elty##"128mem"), d,
1996 IsReMaterializable>, EVEX_V128;
2001 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2002 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2003 X86MemOperand memop, Domain d> {
2004 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2005 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2006 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2008 let Constraints = "$src1 = $dst" in
2009 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2010 (ins RC:$src1, KRC:$mask, RC:$src2),
2011 !strconcat(OpcodeStr,
2012 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2014 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2015 (ins KRC:$mask, RC:$src),
2016 !strconcat(OpcodeStr,
2017 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2018 [], d>, EVEX, EVEX_KZ;
2020 let mayStore = 1 in {
2021 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2022 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2023 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2024 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2025 (ins memop:$dst, KRC:$mask, RC:$src),
2026 !strconcat(OpcodeStr,
2027 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2028 [], d>, EVEX, EVEX_K;
2033 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2034 string st_suff_512, string st_suff_256,
2035 string st_suff_128, string elty, string elsz,
2036 string vsz512, string vsz256, string vsz128,
2037 Domain d, Predicate prd> {
2038 let Predicates = [prd] in
2039 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2040 !cast<ValueType>("v"##vsz512##elty##elsz),
2041 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2042 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2044 let Predicates = [prd, HasVLX] in {
2045 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2046 !cast<ValueType>("v"##vsz256##elty##elsz),
2047 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2048 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2050 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2051 !cast<ValueType>("v"##vsz128##elty##elsz),
2052 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2053 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2057 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2058 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2059 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2060 "512", "256", "", "f", "32", "16", "8", "4",
2061 SSEPackedSingle, HasAVX512>,
2062 PS, EVEX_CD8<32, CD8VF>;
2064 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2065 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2066 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2067 "512", "256", "", "f", "64", "8", "4", "2",
2068 SSEPackedDouble, HasAVX512>,
2069 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2071 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2072 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2073 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2074 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2075 PS, EVEX_CD8<32, CD8VF>;
2077 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2078 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2079 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2080 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2081 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2083 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2084 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2085 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2087 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2088 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2089 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2091 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2093 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2095 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2097 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2100 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2101 (VMOVUPSZmrk addr:$ptr,
2102 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2103 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2105 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2106 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2107 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2109 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2110 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2112 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2113 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2115 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2116 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2118 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2119 (bc_v16f32 (v16i32 immAllZerosV)))),
2120 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2122 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2123 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2125 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2126 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2128 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2129 (bc_v8f64 (v16i32 immAllZerosV)))),
2130 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2132 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2133 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2135 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2136 "16", "8", "4", SSEPackedInt, HasAVX512>,
2137 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2138 "512", "256", "", "i", "32", "16", "8", "4",
2139 SSEPackedInt, HasAVX512>,
2140 PD, EVEX_CD8<32, CD8VF>;
2142 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2143 "8", "4", "2", SSEPackedInt, HasAVX512>,
2144 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2145 "512", "256", "", "i", "64", "8", "4", "2",
2146 SSEPackedInt, HasAVX512>,
2147 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2149 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2150 "64", "32", "16", SSEPackedInt, HasBWI>,
2151 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2152 "i", "8", "64", "32", "16", SSEPackedInt,
2153 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2155 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2156 "32", "16", "8", SSEPackedInt, HasBWI>,
2157 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2158 "i", "16", "32", "16", "8", SSEPackedInt,
2159 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2161 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2162 "16", "8", "4", SSEPackedInt, HasAVX512>,
2163 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2164 "i", "32", "16", "8", "4", SSEPackedInt,
2165 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2167 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2168 "8", "4", "2", SSEPackedInt, HasAVX512>,
2169 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2170 "i", "64", "8", "4", "2", SSEPackedInt,
2171 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2173 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2174 (v16i32 immAllZerosV), GR16:$mask)),
2175 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2177 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2178 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2179 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2181 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2183 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2185 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2187 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2190 let AddedComplexity = 20 in {
2191 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2192 (bc_v8i64 (v16i32 immAllZerosV)))),
2193 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2195 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2196 (v8i64 VR512:$src))),
2197 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2200 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2201 (v16i32 immAllZerosV))),
2202 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2204 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2205 (v16i32 VR512:$src))),
2206 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2209 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2210 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2212 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2213 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2215 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2216 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2218 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2219 (bc_v8i64 (v16i32 immAllZerosV)))),
2220 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2222 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2223 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2225 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2226 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2228 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2229 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2231 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2232 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2235 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2236 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2239 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2240 (VMOVDQU32Zmrk addr:$ptr,
2241 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2242 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2244 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2245 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2246 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2249 // Move Int Doubleword to Packed Double Int
2251 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2252 "vmovd\t{$src, $dst|$dst, $src}",
2254 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2256 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2257 "vmovd\t{$src, $dst|$dst, $src}",
2259 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2260 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2261 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2262 "vmovq\t{$src, $dst|$dst, $src}",
2264 (v2i64 (scalar_to_vector GR64:$src)))],
2265 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2266 let isCodeGenOnly = 1 in {
2267 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2268 "vmovq\t{$src, $dst|$dst, $src}",
2269 [(set FR64:$dst, (bitconvert GR64:$src))],
2270 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2271 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2272 "vmovq\t{$src, $dst|$dst, $src}",
2273 [(set GR64:$dst, (bitconvert FR64:$src))],
2274 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2276 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2277 "vmovq\t{$src, $dst|$dst, $src}",
2278 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2279 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2280 EVEX_CD8<64, CD8VT1>;
2282 // Move Int Doubleword to Single Scalar
2284 let isCodeGenOnly = 1 in {
2285 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2286 "vmovd\t{$src, $dst|$dst, $src}",
2287 [(set FR32X:$dst, (bitconvert GR32:$src))],
2288 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2290 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2291 "vmovd\t{$src, $dst|$dst, $src}",
2292 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2293 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2296 // Move doubleword from xmm register to r/m32
2298 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2299 "vmovd\t{$src, $dst|$dst, $src}",
2300 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2301 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2303 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2304 (ins i32mem:$dst, VR128X:$src),
2305 "vmovd\t{$src, $dst|$dst, $src}",
2306 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2307 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2308 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2310 // Move quadword from xmm1 register to r/m64
2312 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2313 "vmovq\t{$src, $dst|$dst, $src}",
2314 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2316 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2317 Requires<[HasAVX512, In64BitMode]>;
2319 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2320 (ins i64mem:$dst, VR128X:$src),
2321 "vmovq\t{$src, $dst|$dst, $src}",
2322 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2323 addr:$dst)], IIC_SSE_MOVDQ>,
2324 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2325 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2327 // Move Scalar Single to Double Int
2329 let isCodeGenOnly = 1 in {
2330 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2332 "vmovd\t{$src, $dst|$dst, $src}",
2333 [(set GR32:$dst, (bitconvert FR32X:$src))],
2334 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2335 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2336 (ins i32mem:$dst, FR32X:$src),
2337 "vmovd\t{$src, $dst|$dst, $src}",
2338 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2339 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2342 // Move Quadword Int to Packed Quadword Int
2344 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2346 "vmovq\t{$src, $dst|$dst, $src}",
2348 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2349 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2351 //===----------------------------------------------------------------------===//
2352 // AVX-512 MOVSS, MOVSD
2353 //===----------------------------------------------------------------------===//
2355 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2356 SDNode OpNode, ValueType vt,
2357 X86MemOperand x86memop, PatFrag mem_pat> {
2358 let hasSideEffects = 0 in {
2359 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2360 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2361 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2362 (scalar_to_vector RC:$src2))))],
2363 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2364 let Constraints = "$src1 = $dst" in
2365 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2366 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2368 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2369 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2370 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2371 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2372 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2374 let mayStore = 1 in {
2375 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2376 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2377 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2379 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2380 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2381 [], IIC_SSE_MOV_S_MR>,
2382 EVEX, VEX_LIG, EVEX_K;
2384 } //hasSideEffects = 0
2387 let ExeDomain = SSEPackedSingle in
2388 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2389 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2391 let ExeDomain = SSEPackedDouble in
2392 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2393 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2395 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2396 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2397 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2399 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2400 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2401 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2403 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2404 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2405 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2407 // For the disassembler
2408 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2409 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2410 (ins VR128X:$src1, FR32X:$src2),
2411 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2413 XS, EVEX_4V, VEX_LIG;
2414 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2415 (ins VR128X:$src1, FR64X:$src2),
2416 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2418 XD, EVEX_4V, VEX_LIG, VEX_W;
2421 let Predicates = [HasAVX512] in {
2422 let AddedComplexity = 15 in {
2423 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2424 // MOVS{S,D} to the lower bits.
2425 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2426 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2427 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2428 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2429 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2430 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2431 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2432 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2434 // Move low f32 and clear high bits.
2435 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2436 (SUBREG_TO_REG (i32 0),
2437 (VMOVSSZrr (v4f32 (V_SET0)),
2438 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2439 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2440 (SUBREG_TO_REG (i32 0),
2441 (VMOVSSZrr (v4i32 (V_SET0)),
2442 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2445 let AddedComplexity = 20 in {
2446 // MOVSSrm zeros the high parts of the register; represent this
2447 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2448 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2449 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2450 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2451 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2452 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2453 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2455 // MOVSDrm zeros the high parts of the register; represent this
2456 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2457 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2458 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2459 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2460 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2461 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2462 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2463 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2464 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2465 def : Pat<(v2f64 (X86vzload addr:$src)),
2466 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2468 // Represent the same patterns above but in the form they appear for
2470 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2471 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2472 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2473 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2474 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2475 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2476 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2477 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2478 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2480 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2481 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2482 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2483 FR32X:$src)), sub_xmm)>;
2484 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2485 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2486 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2487 FR64X:$src)), sub_xmm)>;
2488 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2489 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2490 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2492 // Move low f64 and clear high bits.
2493 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2494 (SUBREG_TO_REG (i32 0),
2495 (VMOVSDZrr (v2f64 (V_SET0)),
2496 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2498 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2499 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2500 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2502 // Extract and store.
2503 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2505 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2506 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2508 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2510 // Shuffle with VMOVSS
2511 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2512 (VMOVSSZrr (v4i32 VR128X:$src1),
2513 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2514 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2515 (VMOVSSZrr (v4f32 VR128X:$src1),
2516 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2519 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2520 (SUBREG_TO_REG (i32 0),
2521 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2522 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2524 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2525 (SUBREG_TO_REG (i32 0),
2526 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2527 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2530 // Shuffle with VMOVSD
2531 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2532 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2533 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2534 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2535 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2536 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2537 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2538 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2541 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2542 (SUBREG_TO_REG (i32 0),
2543 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2544 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2546 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2547 (SUBREG_TO_REG (i32 0),
2548 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2549 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2552 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2553 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2554 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2555 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2556 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2557 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2558 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2559 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2562 let AddedComplexity = 15 in
2563 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2565 "vmovq\t{$src, $dst|$dst, $src}",
2566 [(set VR128X:$dst, (v2i64 (X86vzmovl
2567 (v2i64 VR128X:$src))))],
2568 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2570 let AddedComplexity = 20 in
2571 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2573 "vmovq\t{$src, $dst|$dst, $src}",
2574 [(set VR128X:$dst, (v2i64 (X86vzmovl
2575 (loadv2i64 addr:$src))))],
2576 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2577 EVEX_CD8<8, CD8VT8>;
2579 let Predicates = [HasAVX512] in {
2580 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2581 let AddedComplexity = 20 in {
2582 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2583 (VMOVDI2PDIZrm addr:$src)>;
2584 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2585 (VMOV64toPQIZrr GR64:$src)>;
2586 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2587 (VMOVDI2PDIZrr GR32:$src)>;
2589 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2590 (VMOVDI2PDIZrm addr:$src)>;
2591 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2592 (VMOVDI2PDIZrm addr:$src)>;
2593 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2594 (VMOVZPQILo2PQIZrm addr:$src)>;
2595 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2596 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2597 def : Pat<(v2i64 (X86vzload addr:$src)),
2598 (VMOVZPQILo2PQIZrm addr:$src)>;
2601 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2602 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2603 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2604 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2605 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2606 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2607 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2610 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2611 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2613 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2614 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2616 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2617 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2619 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2620 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2622 //===----------------------------------------------------------------------===//
2623 // AVX-512 - Non-temporals
2624 //===----------------------------------------------------------------------===//
2625 let SchedRW = [WriteLoad] in {
2626 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2627 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2628 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2629 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2630 EVEX_CD8<64, CD8VF>;
2632 let Predicates = [HasAVX512, HasVLX] in {
2633 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2635 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2636 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2637 EVEX_CD8<64, CD8VF>;
2639 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2641 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2642 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2643 EVEX_CD8<64, CD8VF>;
2647 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2648 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2649 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2650 let SchedRW = [WriteStore], mayStore = 1,
2651 AddedComplexity = 400 in
2652 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2653 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2654 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2657 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2658 string elty, string elsz, string vsz512,
2659 string vsz256, string vsz128, Domain d,
2660 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2661 let Predicates = [prd] in
2662 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2663 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2664 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2667 let Predicates = [prd, HasVLX] in {
2668 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2669 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2670 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2673 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2674 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2675 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2680 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2681 "i", "64", "8", "4", "2", SSEPackedInt,
2682 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2684 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2685 "f", "64", "8", "4", "2", SSEPackedDouble,
2686 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2688 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2689 "f", "32", "16", "8", "4", SSEPackedSingle,
2690 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2692 //===----------------------------------------------------------------------===//
2693 // AVX-512 - Integer arithmetic
2695 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2696 X86VectorVTInfo _, OpndItins itins,
2697 bit IsCommutable = 0> {
2698 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2699 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2700 "$src2, $src1", "$src1, $src2",
2701 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2702 "", itins.rr, IsCommutable>,
2703 AVX512BIBase, EVEX_4V;
2706 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2707 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2708 "$src2, $src1", "$src1, $src2",
2709 (_.VT (OpNode _.RC:$src1,
2710 (bitconvert (_.LdFrag addr:$src2)))),
2712 AVX512BIBase, EVEX_4V;
2715 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2716 X86VectorVTInfo _, OpndItins itins,
2717 bit IsCommutable = 0> :
2718 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2720 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2721 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2722 "${src2}"##_.BroadcastStr##", $src1",
2723 "$src1, ${src2}"##_.BroadcastStr,
2724 (_.VT (OpNode _.RC:$src1,
2726 (_.ScalarLdFrag addr:$src2)))),
2728 AVX512BIBase, EVEX_4V, EVEX_B;
2731 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2732 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2733 Predicate prd, bit IsCommutable = 0> {
2734 let Predicates = [prd] in
2735 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2736 IsCommutable>, EVEX_V512;
2738 let Predicates = [prd, HasVLX] in {
2739 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2740 IsCommutable>, EVEX_V256;
2741 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2742 IsCommutable>, EVEX_V128;
2746 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2747 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2748 Predicate prd, bit IsCommutable = 0> {
2749 let Predicates = [prd] in
2750 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2751 IsCommutable>, EVEX_V512;
2753 let Predicates = [prd, HasVLX] in {
2754 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2755 IsCommutable>, EVEX_V256;
2756 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2757 IsCommutable>, EVEX_V128;
2761 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2762 OpndItins itins, Predicate prd,
2763 bit IsCommutable = 0> {
2764 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2765 itins, prd, IsCommutable>,
2766 VEX_W, EVEX_CD8<64, CD8VF>;
2769 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2770 OpndItins itins, Predicate prd,
2771 bit IsCommutable = 0> {
2772 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2773 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2776 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2777 OpndItins itins, Predicate prd,
2778 bit IsCommutable = 0> {
2779 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2780 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2783 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2784 OpndItins itins, Predicate prd,
2785 bit IsCommutable = 0> {
2786 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2787 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2790 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2791 SDNode OpNode, OpndItins itins, Predicate prd,
2792 bit IsCommutable = 0> {
2793 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2796 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2800 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2801 SDNode OpNode, OpndItins itins, Predicate prd,
2802 bit IsCommutable = 0> {
2803 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2806 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2810 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2811 bits<8> opc_d, bits<8> opc_q,
2812 string OpcodeStr, SDNode OpNode,
2813 OpndItins itins, bit IsCommutable = 0> {
2814 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2815 itins, HasAVX512, IsCommutable>,
2816 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2817 itins, HasBWI, IsCommutable>;
2820 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2821 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2822 PatFrag memop_frag, X86MemOperand x86memop,
2823 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2824 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2825 let isCommutable = IsCommutable in
2827 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2828 (ins RC:$src1, RC:$src2),
2829 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2831 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2832 (ins KRC:$mask, RC:$src1, RC:$src2),
2833 !strconcat(OpcodeStr,
2834 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2835 [], itins.rr>, EVEX_4V, EVEX_K;
2836 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2837 (ins KRC:$mask, RC:$src1, RC:$src2),
2838 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2839 "|$dst {${mask}} {z}, $src1, $src2}"),
2840 [], itins.rr>, EVEX_4V, EVEX_KZ;
2842 let mayLoad = 1 in {
2843 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2844 (ins RC:$src1, x86memop:$src2),
2845 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2847 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2848 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2849 !strconcat(OpcodeStr,
2850 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2851 [], itins.rm>, EVEX_4V, EVEX_K;
2852 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2853 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2854 !strconcat(OpcodeStr,
2855 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2856 [], itins.rm>, EVEX_4V, EVEX_KZ;
2857 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2858 (ins RC:$src1, x86scalar_mop:$src2),
2859 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2860 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2861 [], itins.rm>, EVEX_4V, EVEX_B;
2862 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2863 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2864 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2865 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2867 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2868 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2869 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2870 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2871 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2873 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2877 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2878 SSE_INTALU_ITINS_P, 1>;
2879 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2880 SSE_INTALU_ITINS_P, 0>;
2881 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2882 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2883 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2884 SSE_INTALU_ITINS_P, HasBWI, 1>;
2885 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2886 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2888 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2889 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2890 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2891 EVEX_CD8<64, CD8VF>, VEX_W;
2893 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2894 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2895 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2897 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2898 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2900 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2901 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2902 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2903 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2904 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2905 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2907 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2908 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2909 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2910 SSE_INTALU_ITINS_P, HasBWI, 1>;
2911 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2912 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2914 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2915 SSE_INTALU_ITINS_P, HasBWI, 1>;
2916 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2917 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2918 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2919 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2921 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2922 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2923 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2924 SSE_INTALU_ITINS_P, HasBWI, 1>;
2925 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2926 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2928 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2929 SSE_INTALU_ITINS_P, HasBWI, 1>;
2930 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2931 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2932 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2933 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2935 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2936 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2937 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2938 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2939 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2940 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2941 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2942 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2943 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2944 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2945 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2946 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2947 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2948 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2949 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2950 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2951 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2952 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2953 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2954 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2955 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2956 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2957 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2958 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2959 //===----------------------------------------------------------------------===//
2960 // AVX-512 - Unpack Instructions
2961 //===----------------------------------------------------------------------===//
2963 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2964 PatFrag mem_frag, RegisterClass RC,
2965 X86MemOperand x86memop, string asm,
2967 def rr : AVX512PI<opc, MRMSrcReg,
2968 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2970 (vt (OpNode RC:$src1, RC:$src2)))],
2972 def rm : AVX512PI<opc, MRMSrcMem,
2973 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2975 (vt (OpNode RC:$src1,
2976 (bitconvert (mem_frag addr:$src2)))))],
2980 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2981 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2982 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2983 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2984 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2985 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2986 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2987 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2988 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2989 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2990 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2991 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2993 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2994 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2995 X86MemOperand x86memop> {
2996 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2997 (ins RC:$src1, RC:$src2),
2998 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2999 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3000 IIC_SSE_UNPCK>, EVEX_4V;
3001 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3002 (ins RC:$src1, x86memop:$src2),
3003 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3004 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3005 (bitconvert (memop_frag addr:$src2)))))],
3006 IIC_SSE_UNPCK>, EVEX_4V;
3008 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3009 VR512, memopv16i32, i512mem>, EVEX_V512,
3010 EVEX_CD8<32, CD8VF>;
3011 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3012 VR512, memopv8i64, i512mem>, EVEX_V512,
3013 VEX_W, EVEX_CD8<64, CD8VF>;
3014 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3015 VR512, memopv16i32, i512mem>, EVEX_V512,
3016 EVEX_CD8<32, CD8VF>;
3017 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3018 VR512, memopv8i64, i512mem>, EVEX_V512,
3019 VEX_W, EVEX_CD8<64, CD8VF>;
3020 //===----------------------------------------------------------------------===//
3024 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3025 SDNode OpNode, PatFrag mem_frag,
3026 X86MemOperand x86memop, ValueType OpVT> {
3027 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3028 (ins RC:$src1, i8imm:$src2),
3029 !strconcat(OpcodeStr,
3030 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3032 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3034 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3035 (ins x86memop:$src1, i8imm:$src2),
3036 !strconcat(OpcodeStr,
3037 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3039 (OpVT (OpNode (mem_frag addr:$src1),
3040 (i8 imm:$src2))))]>, EVEX;
3043 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3044 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3046 //===----------------------------------------------------------------------===//
3047 // AVX-512 Logical Instructions
3048 //===----------------------------------------------------------------------===//
3050 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3051 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3052 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3053 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3054 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3055 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3056 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3057 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3059 //===----------------------------------------------------------------------===//
3060 // AVX-512 FP arithmetic
3061 //===----------------------------------------------------------------------===//
3063 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3065 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3066 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3067 EVEX_CD8<32, CD8VT1>;
3068 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3069 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3070 EVEX_CD8<64, CD8VT1>;
3073 let isCommutable = 1 in {
3074 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3075 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3076 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3077 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3079 let isCommutable = 0 in {
3080 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3081 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3084 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3085 X86VectorVTInfo _, bit IsCommutable> {
3086 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3087 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3088 "$src2, $src1", "$src1, $src2",
3089 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3090 let mayLoad = 1 in {
3091 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3092 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3093 "$src2, $src1", "$src1, $src2",
3094 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3095 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3096 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3097 "${src2}"##_.BroadcastStr##", $src1",
3098 "$src1, ${src2}"##_.BroadcastStr,
3099 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3100 (_.ScalarLdFrag addr:$src2))))>,
3105 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3106 bit IsCommutable = 0> {
3107 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3108 IsCommutable>, EVEX_V512, PS,
3109 EVEX_CD8<32, CD8VF>;
3110 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3111 IsCommutable>, EVEX_V512, PD, VEX_W,
3112 EVEX_CD8<64, CD8VF>;
3114 // Define only if AVX512VL feature is present.
3115 let Predicates = [HasVLX] in {
3116 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3117 IsCommutable>, EVEX_V128, PS,
3118 EVEX_CD8<32, CD8VF>;
3119 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3120 IsCommutable>, EVEX_V256, PS,
3121 EVEX_CD8<32, CD8VF>;
3122 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3123 IsCommutable>, EVEX_V128, PD, VEX_W,
3124 EVEX_CD8<64, CD8VF>;
3125 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3126 IsCommutable>, EVEX_V256, PD, VEX_W,
3127 EVEX_CD8<64, CD8VF>;
3131 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3132 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3133 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3134 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3135 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3136 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3138 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3139 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3140 (i16 -1), FROUND_CURRENT)),
3141 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3143 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3144 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3145 (i8 -1), FROUND_CURRENT)),
3146 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3148 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3149 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3150 (i16 -1), FROUND_CURRENT)),
3151 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3153 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3154 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3155 (i8 -1), FROUND_CURRENT)),
3156 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3157 //===----------------------------------------------------------------------===//
3158 // AVX-512 VPTESTM instructions
3159 //===----------------------------------------------------------------------===//
3161 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3162 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3163 SDNode OpNode, ValueType vt> {
3164 def rr : AVX512PI<opc, MRMSrcReg,
3165 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3166 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3167 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3168 SSEPackedInt>, EVEX_4V;
3169 def rm : AVX512PI<opc, MRMSrcMem,
3170 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3171 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3172 [(set KRC:$dst, (OpNode (vt RC:$src1),
3173 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3176 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3177 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3178 EVEX_CD8<32, CD8VF>;
3179 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3180 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3181 EVEX_CD8<64, CD8VF>;
3183 let Predicates = [HasCDI] in {
3184 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3185 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3186 EVEX_CD8<32, CD8VF>;
3187 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3188 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3189 EVEX_CD8<64, CD8VF>;
3192 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3193 (v16i32 VR512:$src2), (i16 -1))),
3194 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3196 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3197 (v8i64 VR512:$src2), (i8 -1))),
3198 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3199 //===----------------------------------------------------------------------===//
3200 // AVX-512 Shift instructions
3201 //===----------------------------------------------------------------------===//
3202 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3203 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3204 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3205 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3206 "$src2, $src1", "$src1, $src2",
3207 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3208 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3209 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3210 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3211 "$src2, $src1", "$src1, $src2",
3212 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3213 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3216 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3217 RegisterClass RC, ValueType vt, ValueType SrcVT,
3218 PatFrag bc_frag, RegisterClass KRC> {
3219 // src2 is always 128-bit
3220 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3221 (ins RC:$src1, VR128X:$src2),
3222 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3223 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3224 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3225 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3226 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3227 !strconcat(OpcodeStr,
3228 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3229 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3230 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3231 (ins RC:$src1, i128mem:$src2),
3232 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3233 [(set RC:$dst, (vt (OpNode RC:$src1,
3234 (bc_frag (memopv2i64 addr:$src2)))))],
3235 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3236 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3237 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3238 !strconcat(OpcodeStr,
3239 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3240 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3243 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3245 EVEX_V512, EVEX_CD8<32, CD8VF>;
3246 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3247 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3248 EVEX_CD8<32, CD8VQ>;
3250 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3251 v8i64_info>, EVEX_V512,
3252 EVEX_CD8<64, CD8VF>, VEX_W;
3253 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3254 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3255 EVEX_CD8<64, CD8VQ>, VEX_W;
3257 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3258 v16i32_info>, EVEX_V512,
3259 EVEX_CD8<32, CD8VF>;
3260 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3261 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3262 EVEX_CD8<32, CD8VQ>;
3264 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3265 v8i64_info>, EVEX_V512,
3266 EVEX_CD8<64, CD8VF>, VEX_W;
3267 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3268 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3269 EVEX_CD8<64, CD8VQ>, VEX_W;
3271 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3273 EVEX_V512, EVEX_CD8<32, CD8VF>;
3274 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3275 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3276 EVEX_CD8<32, CD8VQ>;
3278 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3279 v8i64_info>, EVEX_V512,
3280 EVEX_CD8<64, CD8VF>, VEX_W;
3281 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3282 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3283 EVEX_CD8<64, CD8VQ>, VEX_W;
3285 //===-------------------------------------------------------------------===//
3286 // Variable Bit Shifts
3287 //===-------------------------------------------------------------------===//
3288 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3289 RegisterClass RC, ValueType vt,
3290 X86MemOperand x86memop, PatFrag mem_frag> {
3291 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3292 (ins RC:$src1, RC:$src2),
3293 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3295 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3297 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3298 (ins RC:$src1, x86memop:$src2),
3299 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3301 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3305 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3306 i512mem, memopv16i32>, EVEX_V512,
3307 EVEX_CD8<32, CD8VF>;
3308 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3309 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3310 EVEX_CD8<64, CD8VF>;
3311 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3312 i512mem, memopv16i32>, EVEX_V512,
3313 EVEX_CD8<32, CD8VF>;
3314 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3315 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3316 EVEX_CD8<64, CD8VF>;
3317 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3318 i512mem, memopv16i32>, EVEX_V512,
3319 EVEX_CD8<32, CD8VF>;
3320 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3321 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3322 EVEX_CD8<64, CD8VF>;
3324 //===----------------------------------------------------------------------===//
3325 // AVX-512 - MOVDDUP
3326 //===----------------------------------------------------------------------===//
3328 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3329 X86MemOperand x86memop, PatFrag memop_frag> {
3330 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3331 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3332 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3333 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3334 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3336 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3339 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3340 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3341 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3342 (VMOVDDUPZrm addr:$src)>;
3344 //===---------------------------------------------------------------------===//
3345 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3346 //===---------------------------------------------------------------------===//
3347 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3348 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3349 X86MemOperand x86memop> {
3350 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3351 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3352 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3354 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3355 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3356 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3359 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3360 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3361 EVEX_CD8<32, CD8VF>;
3362 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3363 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3364 EVEX_CD8<32, CD8VF>;
3366 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3367 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3368 (VMOVSHDUPZrm addr:$src)>;
3369 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3370 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3371 (VMOVSLDUPZrm addr:$src)>;
3373 //===----------------------------------------------------------------------===//
3374 // Move Low to High and High to Low packed FP Instructions
3375 //===----------------------------------------------------------------------===//
3376 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3377 (ins VR128X:$src1, VR128X:$src2),
3378 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3379 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3380 IIC_SSE_MOV_LH>, EVEX_4V;
3381 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3382 (ins VR128X:$src1, VR128X:$src2),
3383 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3384 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3385 IIC_SSE_MOV_LH>, EVEX_4V;
3387 let Predicates = [HasAVX512] in {
3389 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3390 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3391 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3392 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3395 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3396 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3399 //===----------------------------------------------------------------------===//
3400 // FMA - Fused Multiply Operations
3403 let Constraints = "$src1 = $dst" in {
3404 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3405 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3406 SDPatternOperator OpNode = null_frag> {
3407 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3408 (ins _.RC:$src2, _.RC:$src3),
3409 OpcodeStr, "$src3, $src2", "$src2, $src3",
3410 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3414 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3415 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3416 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3417 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3418 (_.MemOpFrag addr:$src3))))]>;
3419 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3420 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3421 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3422 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3423 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3424 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3426 } // Constraints = "$src1 = $dst"
3428 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3429 string OpcodeStr, X86VectorVTInfo VTI,
3430 SDPatternOperator OpNode> {
3431 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3433 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3435 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3437 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3440 let ExeDomain = SSEPackedSingle in {
3441 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3442 v16f32_info, X86Fmadd>;
3443 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3444 v16f32_info, X86Fmsub>;
3445 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3446 v16f32_info, X86Fmaddsub>;
3447 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3448 v16f32_info, X86Fmsubadd>;
3449 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3450 v16f32_info, X86Fnmadd>;
3451 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3452 v16f32_info, X86Fnmsub>;
3454 let ExeDomain = SSEPackedDouble in {
3455 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3456 v8f64_info, X86Fmadd>, VEX_W;
3457 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3458 v8f64_info, X86Fmsub>, VEX_W;
3459 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3460 v8f64_info, X86Fmaddsub>, VEX_W;
3461 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3462 v8f64_info, X86Fmsubadd>, VEX_W;
3463 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3464 v8f64_info, X86Fnmadd>, VEX_W;
3465 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3466 v8f64_info, X86Fnmsub>, VEX_W;
3469 let Constraints = "$src1 = $dst" in {
3470 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3471 X86VectorVTInfo _> {
3473 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3474 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3475 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3476 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3478 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3479 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3480 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3481 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3483 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3484 (_.ScalarLdFrag addr:$src2))),
3485 _.RC:$src3))]>, EVEX_B;
3487 } // Constraints = "$src1 = $dst"
3490 let ExeDomain = SSEPackedSingle in {
3491 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3493 EVEX_V512, EVEX_CD8<32, CD8VF>;
3494 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3496 EVEX_V512, EVEX_CD8<32, CD8VF>;
3497 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3499 EVEX_V512, EVEX_CD8<32, CD8VF>;
3500 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3502 EVEX_V512, EVEX_CD8<32, CD8VF>;
3503 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3505 EVEX_V512, EVEX_CD8<32, CD8VF>;
3506 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3508 EVEX_V512, EVEX_CD8<32, CD8VF>;
3510 let ExeDomain = SSEPackedDouble in {
3511 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3513 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3514 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3516 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3517 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3519 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3520 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3522 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3523 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3525 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3526 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3528 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3532 let Constraints = "$src1 = $dst" in {
3533 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3534 RegisterClass RC, ValueType OpVT,
3535 X86MemOperand x86memop, Operand memop,
3537 let isCommutable = 1 in
3538 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3539 (ins RC:$src1, RC:$src2, RC:$src3),
3540 !strconcat(OpcodeStr,
3541 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3543 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3545 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3546 (ins RC:$src1, RC:$src2, f128mem:$src3),
3547 !strconcat(OpcodeStr,
3548 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3550 (OpVT (OpNode RC:$src2, RC:$src1,
3551 (mem_frag addr:$src3))))]>;
3554 } // Constraints = "$src1 = $dst"
3556 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3557 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3558 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3559 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3560 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3561 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3562 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3563 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3564 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3565 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3566 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3567 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3568 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3569 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3570 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3571 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3573 //===----------------------------------------------------------------------===//
3574 // AVX-512 Scalar convert from sign integer to float/double
3575 //===----------------------------------------------------------------------===//
3577 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3578 X86MemOperand x86memop, string asm> {
3579 let hasSideEffects = 0 in {
3580 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3581 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3584 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3585 (ins DstRC:$src1, x86memop:$src),
3586 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3588 } // hasSideEffects = 0
3590 let Predicates = [HasAVX512] in {
3591 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3592 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3593 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3594 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3595 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3596 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3597 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3598 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3600 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3601 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3602 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3603 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3604 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3605 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3606 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3607 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3609 def : Pat<(f32 (sint_to_fp GR32:$src)),
3610 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3611 def : Pat<(f32 (sint_to_fp GR64:$src)),
3612 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3613 def : Pat<(f64 (sint_to_fp GR32:$src)),
3614 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3615 def : Pat<(f64 (sint_to_fp GR64:$src)),
3616 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3618 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3619 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3620 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3621 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3622 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3623 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3624 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3625 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3627 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3628 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3629 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3630 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3631 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3632 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3633 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3634 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3636 def : Pat<(f32 (uint_to_fp GR32:$src)),
3637 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3638 def : Pat<(f32 (uint_to_fp GR64:$src)),
3639 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3640 def : Pat<(f64 (uint_to_fp GR32:$src)),
3641 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3642 def : Pat<(f64 (uint_to_fp GR64:$src)),
3643 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3646 //===----------------------------------------------------------------------===//
3647 // AVX-512 Scalar convert from float/double to integer
3648 //===----------------------------------------------------------------------===//
3649 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3650 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3652 let hasSideEffects = 0 in {
3653 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3654 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3655 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3656 Requires<[HasAVX512]>;
3658 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3659 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3660 Requires<[HasAVX512]>;
3661 } // hasSideEffects = 0
3663 let Predicates = [HasAVX512] in {
3664 // Convert float/double to signed/unsigned int 32/64
3665 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3666 ssmem, sse_load_f32, "cvtss2si">,
3667 XS, EVEX_CD8<32, CD8VT1>;
3668 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3669 ssmem, sse_load_f32, "cvtss2si">,
3670 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3671 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3672 ssmem, sse_load_f32, "cvtss2usi">,
3673 XS, EVEX_CD8<32, CD8VT1>;
3674 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3675 int_x86_avx512_cvtss2usi64, ssmem,
3676 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3677 EVEX_CD8<32, CD8VT1>;
3678 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3679 sdmem, sse_load_f64, "cvtsd2si">,
3680 XD, EVEX_CD8<64, CD8VT1>;
3681 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3682 sdmem, sse_load_f64, "cvtsd2si">,
3683 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3684 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3685 sdmem, sse_load_f64, "cvtsd2usi">,
3686 XD, EVEX_CD8<64, CD8VT1>;
3687 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3688 int_x86_avx512_cvtsd2usi64, sdmem,
3689 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3690 EVEX_CD8<64, CD8VT1>;
3692 let isCodeGenOnly = 1 in {
3693 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3694 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3695 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3696 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3697 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3698 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3699 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3700 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3701 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3702 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3703 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3704 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3706 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3707 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3708 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3709 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3710 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3711 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3712 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3713 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3714 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3715 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3716 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3717 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3718 } // isCodeGenOnly = 1
3720 // Convert float/double to signed/unsigned int 32/64 with truncation
3721 let isCodeGenOnly = 1 in {
3722 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3723 ssmem, sse_load_f32, "cvttss2si">,
3724 XS, EVEX_CD8<32, CD8VT1>;
3725 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3726 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3727 "cvttss2si">, XS, VEX_W,
3728 EVEX_CD8<32, CD8VT1>;
3729 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3730 sdmem, sse_load_f64, "cvttsd2si">, XD,
3731 EVEX_CD8<64, CD8VT1>;
3732 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3733 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3734 "cvttsd2si">, XD, VEX_W,
3735 EVEX_CD8<64, CD8VT1>;
3736 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3737 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3738 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3739 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3740 int_x86_avx512_cvttss2usi64, ssmem,
3741 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3742 EVEX_CD8<32, CD8VT1>;
3743 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3744 int_x86_avx512_cvttsd2usi,
3745 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3746 EVEX_CD8<64, CD8VT1>;
3747 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3748 int_x86_avx512_cvttsd2usi64, sdmem,
3749 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3750 EVEX_CD8<64, CD8VT1>;
3751 } // isCodeGenOnly = 1
3753 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3754 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3756 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3757 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3758 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3759 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3760 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3761 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3764 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3765 loadf32, "cvttss2si">, XS,
3766 EVEX_CD8<32, CD8VT1>;
3767 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3768 loadf32, "cvttss2usi">, XS,
3769 EVEX_CD8<32, CD8VT1>;
3770 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3771 loadf32, "cvttss2si">, XS, VEX_W,
3772 EVEX_CD8<32, CD8VT1>;
3773 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3774 loadf32, "cvttss2usi">, XS, VEX_W,
3775 EVEX_CD8<32, CD8VT1>;
3776 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3777 loadf64, "cvttsd2si">, XD,
3778 EVEX_CD8<64, CD8VT1>;
3779 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3780 loadf64, "cvttsd2usi">, XD,
3781 EVEX_CD8<64, CD8VT1>;
3782 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3783 loadf64, "cvttsd2si">, XD, VEX_W,
3784 EVEX_CD8<64, CD8VT1>;
3785 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3786 loadf64, "cvttsd2usi">, XD, VEX_W,
3787 EVEX_CD8<64, CD8VT1>;
3789 //===----------------------------------------------------------------------===//
3790 // AVX-512 Convert form float to double and back
3791 //===----------------------------------------------------------------------===//
3792 let hasSideEffects = 0 in {
3793 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3794 (ins FR32X:$src1, FR32X:$src2),
3795 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3796 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3798 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3799 (ins FR32X:$src1, f32mem:$src2),
3800 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3801 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3802 EVEX_CD8<32, CD8VT1>;
3804 // Convert scalar double to scalar single
3805 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3806 (ins FR64X:$src1, FR64X:$src2),
3807 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3808 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3810 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3811 (ins FR64X:$src1, f64mem:$src2),
3812 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3813 []>, EVEX_4V, VEX_LIG, VEX_W,
3814 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3817 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3818 Requires<[HasAVX512]>;
3819 def : Pat<(fextend (loadf32 addr:$src)),
3820 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3822 def : Pat<(extloadf32 addr:$src),
3823 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3824 Requires<[HasAVX512, OptForSize]>;
3826 def : Pat<(extloadf32 addr:$src),
3827 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3828 Requires<[HasAVX512, OptForSpeed]>;
3830 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3831 Requires<[HasAVX512]>;
3833 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3834 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3835 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3837 let hasSideEffects = 0 in {
3838 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3839 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3841 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3842 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3843 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3844 [], d>, EVEX, EVEX_B, EVEX_RC;
3846 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3847 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3849 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3850 } // hasSideEffects = 0
3853 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3854 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3855 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3857 let hasSideEffects = 0 in {
3858 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3859 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3861 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3863 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3864 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3866 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3867 } // hasSideEffects = 0
3870 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3871 memopv8f64, f512mem, v8f32, v8f64,
3872 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3873 EVEX_CD8<64, CD8VF>;
3875 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3876 memopv4f64, f256mem, v8f64, v8f32,
3877 SSEPackedDouble>, EVEX_V512, PS,
3878 EVEX_CD8<32, CD8VH>;
3879 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3880 (VCVTPS2PDZrm addr:$src)>;
3882 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3883 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3884 (VCVTPD2PSZrr VR512:$src)>;
3886 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3887 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3888 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3890 //===----------------------------------------------------------------------===//
3891 // AVX-512 Vector convert from sign integer to float/double
3892 //===----------------------------------------------------------------------===//
3894 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3895 memopv8i64, i512mem, v16f32, v16i32,
3896 SSEPackedSingle>, EVEX_V512, PS,
3897 EVEX_CD8<32, CD8VF>;
3899 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3900 memopv4i64, i256mem, v8f64, v8i32,
3901 SSEPackedDouble>, EVEX_V512, XS,
3902 EVEX_CD8<32, CD8VH>;
3904 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3905 memopv16f32, f512mem, v16i32, v16f32,
3906 SSEPackedSingle>, EVEX_V512, XS,
3907 EVEX_CD8<32, CD8VF>;
3909 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3910 memopv8f64, f512mem, v8i32, v8f64,
3911 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3912 EVEX_CD8<64, CD8VF>;
3914 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3915 memopv16f32, f512mem, v16i32, v16f32,
3916 SSEPackedSingle>, EVEX_V512, PS,
3917 EVEX_CD8<32, CD8VF>;
3919 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3920 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3921 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3922 (VCVTTPS2UDQZrr VR512:$src)>;
3924 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3925 memopv8f64, f512mem, v8i32, v8f64,
3926 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3927 EVEX_CD8<64, CD8VF>;
3929 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3930 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3931 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3932 (VCVTTPD2UDQZrr VR512:$src)>;
3934 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3935 memopv4i64, f256mem, v8f64, v8i32,
3936 SSEPackedDouble>, EVEX_V512, XS,
3937 EVEX_CD8<32, CD8VH>;
3939 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3940 memopv16i32, f512mem, v16f32, v16i32,
3941 SSEPackedSingle>, EVEX_V512, XD,
3942 EVEX_CD8<32, CD8VF>;
3944 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3945 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3946 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3948 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3949 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3950 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3952 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3953 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3954 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3956 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3957 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3958 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3960 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3961 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3962 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3964 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3965 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3966 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3967 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3968 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3969 (VCVTDQ2PDZrr VR256X:$src)>;
3970 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3971 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3972 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3973 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3974 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3975 (VCVTUDQ2PDZrr VR256X:$src)>;
3977 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3978 RegisterClass DstRC, PatFrag mem_frag,
3979 X86MemOperand x86memop, Domain d> {
3980 let hasSideEffects = 0 in {
3981 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3982 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3984 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3985 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3986 [], d>, EVEX, EVEX_B, EVEX_RC;
3988 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3989 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3991 } // hasSideEffects = 0
3994 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3995 memopv16f32, f512mem, SSEPackedSingle>, PD,
3996 EVEX_V512, EVEX_CD8<32, CD8VF>;
3997 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3998 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3999 EVEX_V512, EVEX_CD8<64, CD8VF>;
4001 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4002 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4003 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4005 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4006 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4007 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4009 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4010 memopv16f32, f512mem, SSEPackedSingle>,
4011 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4012 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4013 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4014 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4016 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4017 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4018 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4020 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4021 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4022 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4024 let Predicates = [HasAVX512] in {
4025 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4026 (VCVTPD2PSZrm addr:$src)>;
4027 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4028 (VCVTPS2PDZrm addr:$src)>;
4031 //===----------------------------------------------------------------------===//
4032 // Half precision conversion instructions
4033 //===----------------------------------------------------------------------===//
4034 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4035 X86MemOperand x86memop> {
4036 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4037 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4039 let hasSideEffects = 0, mayLoad = 1 in
4040 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4041 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4044 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4045 X86MemOperand x86memop> {
4046 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4047 (ins srcRC:$src1, i32i8imm:$src2),
4048 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4050 let hasSideEffects = 0, mayStore = 1 in
4051 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4052 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
4053 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4056 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4057 EVEX_CD8<32, CD8VH>;
4058 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4059 EVEX_CD8<32, CD8VH>;
4061 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4062 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4063 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4065 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4066 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4067 (VCVTPH2PSZrr VR256X:$src)>;
4069 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4070 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4071 "ucomiss">, PS, EVEX, VEX_LIG,
4072 EVEX_CD8<32, CD8VT1>;
4073 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4074 "ucomisd">, PD, EVEX,
4075 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4076 let Pattern = []<dag> in {
4077 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4078 "comiss">, PS, EVEX, VEX_LIG,
4079 EVEX_CD8<32, CD8VT1>;
4080 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4081 "comisd">, PD, EVEX,
4082 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4084 let isCodeGenOnly = 1 in {
4085 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4086 load, "ucomiss">, PS, EVEX, VEX_LIG,
4087 EVEX_CD8<32, CD8VT1>;
4088 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4089 load, "ucomisd">, PD, EVEX,
4090 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4092 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4093 load, "comiss">, PS, EVEX, VEX_LIG,
4094 EVEX_CD8<32, CD8VT1>;
4095 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4096 load, "comisd">, PD, EVEX,
4097 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4101 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4102 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4103 X86MemOperand x86memop> {
4104 let hasSideEffects = 0 in {
4105 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4106 (ins RC:$src1, RC:$src2),
4107 !strconcat(OpcodeStr,
4108 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4109 let mayLoad = 1 in {
4110 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4111 (ins RC:$src1, x86memop:$src2),
4112 !strconcat(OpcodeStr,
4113 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4118 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4119 EVEX_CD8<32, CD8VT1>;
4120 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4121 VEX_W, EVEX_CD8<64, CD8VT1>;
4122 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4123 EVEX_CD8<32, CD8VT1>;
4124 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4125 VEX_W, EVEX_CD8<64, CD8VT1>;
4127 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4128 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4129 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4130 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4132 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4133 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4134 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4135 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4137 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4138 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4139 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4140 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4142 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4143 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4144 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4145 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4147 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4148 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4149 X86VectorVTInfo _> {
4150 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4151 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4152 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4153 let mayLoad = 1 in {
4154 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4155 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4157 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4158 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4159 (ins _.ScalarMemOp:$src), OpcodeStr,
4160 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4162 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4167 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4168 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4169 EVEX_V512, EVEX_CD8<32, CD8VF>;
4170 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4171 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4173 // Define only if AVX512VL feature is present.
4174 let Predicates = [HasVLX] in {
4175 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4176 OpNode, v4f32x_info>,
4177 EVEX_V128, EVEX_CD8<32, CD8VF>;
4178 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4179 OpNode, v8f32x_info>,
4180 EVEX_V256, EVEX_CD8<32, CD8VF>;
4181 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4182 OpNode, v2f64x_info>,
4183 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4184 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4185 OpNode, v4f64x_info>,
4186 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4190 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4191 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4193 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4194 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4195 (VRSQRT14PSZr VR512:$src)>;
4196 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4197 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4198 (VRSQRT14PDZr VR512:$src)>;
4200 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4201 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4202 (VRCP14PSZr VR512:$src)>;
4203 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4204 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4205 (VRCP14PDZr VR512:$src)>;
4207 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4208 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4209 X86MemOperand x86memop> {
4210 let hasSideEffects = 0, Predicates = [HasERI] in {
4211 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4212 (ins RC:$src1, RC:$src2),
4213 !strconcat(OpcodeStr,
4214 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4215 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4216 (ins RC:$src1, RC:$src2),
4217 !strconcat(OpcodeStr,
4218 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
4219 []>, EVEX_4V, EVEX_B;
4220 let mayLoad = 1 in {
4221 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4222 (ins RC:$src1, x86memop:$src2),
4223 !strconcat(OpcodeStr,
4224 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4229 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4230 EVEX_CD8<32, CD8VT1>;
4231 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4232 VEX_W, EVEX_CD8<64, CD8VT1>;
4233 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4234 EVEX_CD8<32, CD8VT1>;
4235 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4236 VEX_W, EVEX_CD8<64, CD8VT1>;
4238 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4239 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4241 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4242 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4244 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4245 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4247 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4248 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4250 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4251 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4253 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4254 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4256 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4257 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4259 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4260 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4262 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4264 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4267 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4268 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4269 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4271 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4272 (ins _.RC:$src), OpcodeStr,
4274 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4276 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4277 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4279 (bitconvert (_.LdFrag addr:$src))), (i32 FROUND_CURRENT))>;
4281 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4282 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4284 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4285 (i32 FROUND_CURRENT))>, EVEX_B;
4288 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4289 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4290 EVEX_CD8<32, CD8VF>;
4291 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4292 VEX_W, EVEX_CD8<32, CD8VF>;
4295 let Predicates = [HasERI], hasSideEffects = 0 in {
4297 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4298 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4299 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4302 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4303 SDNode OpNode, X86VectorVTInfo _>{
4304 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4305 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4306 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4307 let mayLoad = 1 in {
4308 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4309 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4311 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4313 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4314 (ins _.ScalarMemOp:$src), OpcodeStr,
4315 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4317 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4322 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4323 Intrinsic F32Int, Intrinsic F64Int,
4324 OpndItins itins_s, OpndItins itins_d> {
4325 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4326 (ins FR32X:$src1, FR32X:$src2),
4327 !strconcat(OpcodeStr,
4328 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4329 [], itins_s.rr>, XS, EVEX_4V;
4330 let isCodeGenOnly = 1 in
4331 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4332 (ins VR128X:$src1, VR128X:$src2),
4333 !strconcat(OpcodeStr,
4334 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4336 (F32Int VR128X:$src1, VR128X:$src2))],
4337 itins_s.rr>, XS, EVEX_4V;
4338 let mayLoad = 1 in {
4339 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4340 (ins FR32X:$src1, f32mem:$src2),
4341 !strconcat(OpcodeStr,
4342 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4343 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4344 let isCodeGenOnly = 1 in
4345 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4346 (ins VR128X:$src1, ssmem:$src2),
4347 !strconcat(OpcodeStr,
4348 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4350 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4351 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4353 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4354 (ins FR64X:$src1, FR64X:$src2),
4355 !strconcat(OpcodeStr,
4356 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4358 let isCodeGenOnly = 1 in
4359 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4360 (ins VR128X:$src1, VR128X:$src2),
4361 !strconcat(OpcodeStr,
4362 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4364 (F64Int VR128X:$src1, VR128X:$src2))],
4365 itins_s.rr>, XD, EVEX_4V, VEX_W;
4366 let mayLoad = 1 in {
4367 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4368 (ins FR64X:$src1, f64mem:$src2),
4369 !strconcat(OpcodeStr,
4370 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4371 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4372 let isCodeGenOnly = 1 in
4373 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4374 (ins VR128X:$src1, sdmem:$src2),
4375 !strconcat(OpcodeStr,
4376 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4378 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4379 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4383 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4385 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4387 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4388 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4390 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4391 // Define only if AVX512VL feature is present.
4392 let Predicates = [HasVLX] in {
4393 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4394 OpNode, v4f32x_info>,
4395 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4396 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4397 OpNode, v8f32x_info>,
4398 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4399 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4400 OpNode, v2f64x_info>,
4401 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4402 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4403 OpNode, v4f64x_info>,
4404 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4408 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4410 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4411 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4412 SSE_SQRTSS, SSE_SQRTSD>;
4414 let Predicates = [HasAVX512] in {
4415 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4416 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4417 (VSQRTPSZr VR512:$src1)>;
4418 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4419 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4420 (VSQRTPDZr VR512:$src1)>;
4422 def : Pat<(f32 (fsqrt FR32X:$src)),
4423 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4424 def : Pat<(f32 (fsqrt (load addr:$src))),
4425 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4426 Requires<[OptForSize]>;
4427 def : Pat<(f64 (fsqrt FR64X:$src)),
4428 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4429 def : Pat<(f64 (fsqrt (load addr:$src))),
4430 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4431 Requires<[OptForSize]>;
4433 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4434 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4435 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4436 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4437 Requires<[OptForSize]>;
4439 def : Pat<(f32 (X86frcp FR32X:$src)),
4440 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4441 def : Pat<(f32 (X86frcp (load addr:$src))),
4442 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4443 Requires<[OptForSize]>;
4445 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4446 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4447 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4449 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4450 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4452 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4453 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4454 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4456 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4457 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4461 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4462 X86MemOperand x86memop, RegisterClass RC,
4463 PatFrag mem_frag32, PatFrag mem_frag64,
4464 Intrinsic V4F32Int, Intrinsic V2F64Int,
4466 let ExeDomain = SSEPackedSingle in {
4467 // Intrinsic operation, reg.
4468 // Vector intrinsic operation, reg
4469 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4470 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4471 !strconcat(OpcodeStr,
4472 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4473 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4475 // Vector intrinsic operation, mem
4476 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4477 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4478 !strconcat(OpcodeStr,
4479 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4481 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4482 EVEX_CD8<32, VForm>;
4483 } // ExeDomain = SSEPackedSingle
4485 let ExeDomain = SSEPackedDouble in {
4486 // Vector intrinsic operation, reg
4487 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4488 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4489 !strconcat(OpcodeStr,
4490 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4491 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4493 // Vector intrinsic operation, mem
4494 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4495 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4496 !strconcat(OpcodeStr,
4497 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4499 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4500 EVEX_CD8<64, VForm>;
4501 } // ExeDomain = SSEPackedDouble
4504 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4508 let ExeDomain = GenericDomain in {
4510 let hasSideEffects = 0 in
4511 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4512 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4513 !strconcat(OpcodeStr,
4514 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4517 // Intrinsic operation, reg.
4518 let isCodeGenOnly = 1 in
4519 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4520 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4521 !strconcat(OpcodeStr,
4522 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4523 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4525 // Intrinsic operation, mem.
4526 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4527 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4528 !strconcat(OpcodeStr,
4529 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4530 [(set VR128X:$dst, (F32Int VR128X:$src1,
4531 sse_load_f32:$src2, imm:$src3))]>,
4532 EVEX_CD8<32, CD8VT1>;
4535 let hasSideEffects = 0 in
4536 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4537 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4538 !strconcat(OpcodeStr,
4539 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4542 // Intrinsic operation, reg.
4543 let isCodeGenOnly = 1 in
4544 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4545 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4546 !strconcat(OpcodeStr,
4547 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4548 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4551 // Intrinsic operation, mem.
4552 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4553 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4554 !strconcat(OpcodeStr,
4555 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4557 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4558 VEX_W, EVEX_CD8<64, CD8VT1>;
4559 } // ExeDomain = GenericDomain
4562 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4563 X86MemOperand x86memop, RegisterClass RC,
4564 PatFrag mem_frag, Domain d> {
4565 let ExeDomain = d in {
4566 // Intrinsic operation, reg.
4567 // Vector intrinsic operation, reg
4568 def r : AVX512AIi8<opc, MRMSrcReg,
4569 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4570 !strconcat(OpcodeStr,
4571 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4574 // Vector intrinsic operation, mem
4575 def m : AVX512AIi8<opc, MRMSrcMem,
4576 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4577 !strconcat(OpcodeStr,
4578 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4584 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4585 memopv16f32, SSEPackedSingle>, EVEX_V512,
4586 EVEX_CD8<32, CD8VF>;
4588 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4589 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4591 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4594 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4595 memopv8f64, SSEPackedDouble>, EVEX_V512,
4596 VEX_W, EVEX_CD8<64, CD8VF>;
4598 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4599 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4601 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4603 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4604 Operand x86memop, RegisterClass RC, Domain d> {
4605 let ExeDomain = d in {
4606 def r : AVX512AIi8<opc, MRMSrcReg,
4607 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4608 !strconcat(OpcodeStr,
4609 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4612 def m : AVX512AIi8<opc, MRMSrcMem,
4613 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4614 !strconcat(OpcodeStr,
4615 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4620 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4621 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4623 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4624 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4626 def : Pat<(ffloor FR32X:$src),
4627 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4628 def : Pat<(f64 (ffloor FR64X:$src)),
4629 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4630 def : Pat<(f32 (fnearbyint FR32X:$src)),
4631 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4632 def : Pat<(f64 (fnearbyint FR64X:$src)),
4633 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4634 def : Pat<(f32 (fceil FR32X:$src)),
4635 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4636 def : Pat<(f64 (fceil FR64X:$src)),
4637 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4638 def : Pat<(f32 (frint FR32X:$src)),
4639 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4640 def : Pat<(f64 (frint FR64X:$src)),
4641 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4642 def : Pat<(f32 (ftrunc FR32X:$src)),
4643 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4644 def : Pat<(f64 (ftrunc FR64X:$src)),
4645 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4647 def : Pat<(v16f32 (ffloor VR512:$src)),
4648 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4649 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4650 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4651 def : Pat<(v16f32 (fceil VR512:$src)),
4652 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4653 def : Pat<(v16f32 (frint VR512:$src)),
4654 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4655 def : Pat<(v16f32 (ftrunc VR512:$src)),
4656 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4658 def : Pat<(v8f64 (ffloor VR512:$src)),
4659 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4660 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4661 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4662 def : Pat<(v8f64 (fceil VR512:$src)),
4663 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4664 def : Pat<(v8f64 (frint VR512:$src)),
4665 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4666 def : Pat<(v8f64 (ftrunc VR512:$src)),
4667 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4669 //-------------------------------------------------
4670 // Integer truncate and extend operations
4671 //-------------------------------------------------
4673 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4674 RegisterClass dstRC, RegisterClass srcRC,
4675 RegisterClass KRC, X86MemOperand x86memop> {
4676 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4678 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4681 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4682 (ins KRC:$mask, srcRC:$src),
4683 !strconcat(OpcodeStr,
4684 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4687 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4688 (ins KRC:$mask, srcRC:$src),
4689 !strconcat(OpcodeStr,
4690 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4693 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4694 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4697 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4698 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4699 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4703 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4704 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4705 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4706 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4707 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4708 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4709 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4710 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4711 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4712 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4713 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4714 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4715 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4716 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4717 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4718 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4719 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4720 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4721 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4722 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4723 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4724 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4725 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4726 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4727 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4728 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4729 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4730 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4731 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4732 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4734 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4735 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4736 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4737 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4738 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4740 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4741 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4742 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4743 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4744 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4745 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4746 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4747 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4750 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4751 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4752 PatFrag mem_frag, X86MemOperand x86memop,
4753 ValueType OpVT, ValueType InVT> {
4755 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4757 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4758 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4760 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4761 (ins KRC:$mask, SrcRC:$src),
4762 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4765 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4766 (ins KRC:$mask, SrcRC:$src),
4767 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4770 let mayLoad = 1 in {
4771 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4772 (ins x86memop:$src),
4773 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4775 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4778 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4779 (ins KRC:$mask, x86memop:$src),
4780 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4784 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4785 (ins KRC:$mask, x86memop:$src),
4786 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4792 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4793 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4795 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4796 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4798 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4799 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4800 EVEX_CD8<16, CD8VH>;
4801 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4802 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4803 EVEX_CD8<16, CD8VQ>;
4804 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4805 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4806 EVEX_CD8<32, CD8VH>;
4808 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4809 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4811 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4812 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4814 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4815 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4816 EVEX_CD8<16, CD8VH>;
4817 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4818 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4819 EVEX_CD8<16, CD8VQ>;
4820 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4821 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4822 EVEX_CD8<32, CD8VH>;
4824 //===----------------------------------------------------------------------===//
4825 // GATHER - SCATTER Operations
4827 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4828 RegisterClass RC, X86MemOperand memop> {
4830 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4831 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4832 (ins RC:$src1, KRC:$mask, memop:$src2),
4833 !strconcat(OpcodeStr,
4834 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4838 let ExeDomain = SSEPackedDouble in {
4839 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4840 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4841 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4842 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4845 let ExeDomain = SSEPackedSingle in {
4846 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4847 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4848 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4849 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4852 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4853 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4854 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4855 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4857 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4858 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4859 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4860 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4862 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4863 RegisterClass RC, X86MemOperand memop> {
4864 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4865 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4866 (ins memop:$dst, KRC:$mask, RC:$src2),
4867 !strconcat(OpcodeStr,
4868 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4872 let ExeDomain = SSEPackedDouble in {
4873 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4874 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4875 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4876 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4879 let ExeDomain = SSEPackedSingle in {
4880 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4881 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4882 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4883 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4886 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4887 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4888 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4889 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4891 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4892 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4893 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4894 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4897 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4898 RegisterClass KRC, X86MemOperand memop> {
4899 let Predicates = [HasPFI], hasSideEffects = 1 in
4900 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4901 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4905 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4906 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4908 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4909 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4911 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4912 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4914 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4915 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4917 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4918 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4920 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4921 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4923 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4924 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4926 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4927 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4929 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4930 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4932 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4933 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4935 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4936 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4938 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4939 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4941 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4942 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4944 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4945 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4947 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4948 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4950 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4951 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4952 //===----------------------------------------------------------------------===//
4953 // VSHUFPS - VSHUFPD Operations
4955 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4956 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4958 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4959 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4960 !strconcat(OpcodeStr,
4961 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4962 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4963 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4964 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4965 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4966 (ins RC:$src1, RC:$src2, i8imm:$src3),
4967 !strconcat(OpcodeStr,
4968 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4969 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4970 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4971 EVEX_4V, Sched<[WriteShuffle]>;
4974 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4975 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4976 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4977 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4979 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4980 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4981 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4982 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4983 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4985 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4986 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4987 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4988 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4989 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4991 multiclass avx512_valign<X86VectorVTInfo _> {
4992 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4993 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4995 "$src3, $src2, $src1", "$src1, $src2, $src3",
4996 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4998 AVX512AIi8Base, EVEX_4V;
5000 // Also match valign of packed floats.
5001 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5002 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5005 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5006 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
5007 !strconcat("valign"##_.Suffix,
5008 " \t{$src3, $src2, $src1, $dst|"
5009 "$dst, $src1, $src2, $src3}"),
5012 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5013 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5015 // Helper fragments to match sext vXi1 to vXiY.
5016 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5017 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5019 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5020 RegisterClass KRC, RegisterClass RC,
5021 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5023 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5024 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
5026 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5027 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5029 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5030 !strconcat(OpcodeStr,
5031 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5033 let mayLoad = 1 in {
5034 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5035 (ins x86memop:$src),
5036 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
5038 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5039 (ins KRC:$mask, x86memop:$src),
5040 !strconcat(OpcodeStr,
5041 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5043 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5044 (ins KRC:$mask, x86memop:$src),
5045 !strconcat(OpcodeStr,
5046 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5048 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5049 (ins x86scalar_mop:$src),
5050 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5051 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5053 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5054 (ins KRC:$mask, x86scalar_mop:$src),
5055 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5056 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5057 []>, EVEX, EVEX_B, EVEX_K;
5058 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5059 (ins KRC:$mask, x86scalar_mop:$src),
5060 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5061 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5063 []>, EVEX, EVEX_B, EVEX_KZ;
5067 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5068 i512mem, i32mem, "{1to16}">, EVEX_V512,
5069 EVEX_CD8<32, CD8VF>;
5070 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5071 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5072 EVEX_CD8<64, CD8VF>;
5075 (bc_v16i32 (v16i1sextv16i32)),
5076 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5077 (VPABSDZrr VR512:$src)>;
5079 (bc_v8i64 (v8i1sextv8i64)),
5080 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5081 (VPABSQZrr VR512:$src)>;
5083 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5084 (v16i32 immAllZerosV), (i16 -1))),
5085 (VPABSDZrr VR512:$src)>;
5086 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5087 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5088 (VPABSQZrr VR512:$src)>;
5090 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5091 RegisterClass RC, RegisterClass KRC,
5092 X86MemOperand x86memop,
5093 X86MemOperand x86scalar_mop, string BrdcstStr> {
5094 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5096 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
5098 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5099 (ins x86memop:$src),
5100 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
5102 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5103 (ins x86scalar_mop:$src),
5104 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5105 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5107 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5108 (ins KRC:$mask, RC:$src),
5109 !strconcat(OpcodeStr,
5110 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5112 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5113 (ins KRC:$mask, x86memop:$src),
5114 !strconcat(OpcodeStr,
5115 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5117 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5118 (ins KRC:$mask, x86scalar_mop:$src),
5119 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5120 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5122 []>, EVEX, EVEX_KZ, EVEX_B;
5124 let Constraints = "$src1 = $dst" in {
5125 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5126 (ins RC:$src1, KRC:$mask, RC:$src2),
5127 !strconcat(OpcodeStr,
5128 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5130 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5131 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5132 !strconcat(OpcodeStr,
5133 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5135 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5136 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5137 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
5138 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5139 []>, EVEX, EVEX_K, EVEX_B;
5143 let Predicates = [HasCDI] in {
5144 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5145 i512mem, i32mem, "{1to16}">,
5146 EVEX_V512, EVEX_CD8<32, CD8VF>;
5149 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5150 i512mem, i64mem, "{1to8}">,
5151 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5155 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5157 (VPCONFLICTDrrk VR512:$src1,
5158 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5160 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5162 (VPCONFLICTQrrk VR512:$src1,
5163 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5165 let Predicates = [HasCDI] in {
5166 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5167 i512mem, i32mem, "{1to16}">,
5168 EVEX_V512, EVEX_CD8<32, CD8VF>;
5171 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5172 i512mem, i64mem, "{1to8}">,
5173 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5177 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5179 (VPLZCNTDrrk VR512:$src1,
5180 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5182 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5184 (VPLZCNTQrrk VR512:$src1,
5185 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5187 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5188 (VPLZCNTDrm addr:$src)>;
5189 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5190 (VPLZCNTDrr VR512:$src)>;
5191 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5192 (VPLZCNTQrm addr:$src)>;
5193 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5194 (VPLZCNTQrr VR512:$src)>;
5196 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5197 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5198 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5200 def : Pat<(store VK1:$src, addr:$dst),
5201 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5203 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5204 (truncstore node:$val, node:$ptr), [{
5205 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5208 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5209 (MOV8mr addr:$dst, GR8:$src)>;
5211 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5212 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5213 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
5214 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5217 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5218 string OpcodeStr, Predicate prd> {
5219 let Predicates = [prd] in
5220 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5222 let Predicates = [prd, HasVLX] in {
5223 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5224 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5228 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5229 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5231 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5233 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5235 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5239 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;