1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
280 dag Outs, dag NonTiedIns, string OpcodeStr,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_common<O, F, _, Outs,
284 !con((ins _.RC:$src1), NonTiedIns),
285 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
288 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
290 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
293 string AttSrcAsm, string IntelSrcAsm,
295 AVX512_maskable_custom<O, F, Outs, Ins,
296 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
297 !con((ins _.KRCWM:$mask), Ins),
298 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
302 // Instruction with mask that puts result in mask register,
303 // like "compare" and "vptest"
304 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
306 dag Ins, dag MaskingIns,
308 string AttSrcAsm, string IntelSrcAsm,
310 list<dag> MaskingPattern,
312 InstrItinClass itin = NoItinerary> {
313 def NAME: AVX512<O, F, Outs, Ins,
314 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
315 "$dst "#Round#", "#IntelSrcAsm#"}",
318 def NAME#k: AVX512<O, F, Outs, MaskingIns,
319 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
320 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
321 MaskingPattern, itin>, EVEX_K;
324 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
326 dag Ins, dag MaskingIns,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, dag MaskingRHS,
331 InstrItinClass itin = NoItinerary> :
332 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
333 AttSrcAsm, IntelSrcAsm,
334 [(set _.KRC:$dst, RHS)],
335 [(set _.KRC:$dst, MaskingRHS)],
338 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
339 dag Outs, dag Ins, string OpcodeStr,
340 string AttSrcAsm, string IntelSrcAsm,
341 dag RHS, string Round = "",
342 InstrItinClass itin = NoItinerary> :
343 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
344 !con((ins _.KRCWM:$mask), Ins),
345 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
346 (and _.KRCWM:$mask, RHS),
349 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
350 dag Outs, dag Ins, string OpcodeStr,
351 string AttSrcAsm, string IntelSrcAsm> :
352 AVX512_maskable_custom_cmp<O, F, Outs,
353 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
354 AttSrcAsm, IntelSrcAsm,
355 [],[],"", NoItinerary>;
357 // Bitcasts between 512-bit vector types. Return the original type since
358 // no instruction is needed for the conversion
359 let Predicates = [HasAVX512] in {
360 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
364 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
369 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
374 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
379 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
385 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
389 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
396 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
401 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
406 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
411 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
416 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
420 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
421 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
423 // Bitcasts between 256-bit vector types. Return the original type since
424 // no instruction is needed for the conversion
425 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
429 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
434 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
439 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
444 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
449 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
453 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
454 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
458 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
461 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
462 isPseudo = 1, Predicates = [HasAVX512] in {
463 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
464 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
467 let Predicates = [HasAVX512] in {
468 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
469 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
470 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
473 //===----------------------------------------------------------------------===//
474 // AVX-512 - VECTOR INSERT
476 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert> {
478 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
479 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
480 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
481 "vinsert" # From.EltTypeName # "x" # From.NumElts,
482 "$src3, $src2, $src1", "$src1, $src2, $src3",
483 (vinsert_insert:$src3 (To.VT To.RC:$src1),
484 (From.VT From.RC:$src2),
485 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
488 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
489 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
490 "vinsert" # From.EltTypeName # "x" # From.NumElts,
491 "$src3, $src2, $src1", "$src1, $src2, $src3",
492 (vinsert_insert:$src3 (To.VT To.RC:$src1),
493 (From.VT (bitconvert (From.LdFrag addr:$src2))),
494 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
495 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
499 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
500 X86VectorVTInfo To, PatFrag vinsert_insert,
501 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
502 let Predicates = p in {
503 def : Pat<(vinsert_insert:$ins
504 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
505 (To.VT (!cast<Instruction>(InstrStr#"rr")
506 To.RC:$src1, From.RC:$src2,
507 (INSERT_get_vinsert_imm To.RC:$ins)))>;
509 def : Pat<(vinsert_insert:$ins
511 (From.VT (bitconvert (From.LdFrag addr:$src2))),
513 (To.VT (!cast<Instruction>(InstrStr#"rm")
514 To.RC:$src1, addr:$src2,
515 (INSERT_get_vinsert_imm To.RC:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
522 let Predicates = [HasVLX] in
523 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
524 X86VectorVTInfo< 4, EltVT32, VR128X>,
525 X86VectorVTInfo< 8, EltVT32, VR256X>,
526 vinsert128_insert>, EVEX_V256;
528 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
529 X86VectorVTInfo< 4, EltVT32, VR128X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 vinsert128_insert>, EVEX_V512;
533 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
534 X86VectorVTInfo< 4, EltVT64, VR256X>,
535 X86VectorVTInfo< 8, EltVT64, VR512>,
536 vinsert256_insert>, VEX_W, EVEX_V512;
538 let Predicates = [HasVLX, HasDQI] in
539 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 2, EltVT64, VR128X>,
541 X86VectorVTInfo< 4, EltVT64, VR256X>,
542 vinsert128_insert>, VEX_W, EVEX_V256;
544 let Predicates = [HasDQI] in {
545 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
546 X86VectorVTInfo< 2, EltVT64, VR128X>,
547 X86VectorVTInfo< 8, EltVT64, VR512>,
548 vinsert128_insert>, VEX_W, EVEX_V512;
550 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
551 X86VectorVTInfo< 8, EltVT32, VR256X>,
552 X86VectorVTInfo<16, EltVT32, VR512>,
553 vinsert256_insert>, EVEX_V512;
557 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
558 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
560 // Codegen pattern with the alternative types,
561 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
562 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
563 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
564 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
565 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
567 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
568 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
569 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
570 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
572 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
573 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
574 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
575 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
577 // Codegen pattern with the alternative types insert VEC128 into VEC256
578 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
582 // Codegen pattern with the alternative types insert VEC128 into VEC512
583 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
587 // Codegen pattern with the alternative types insert VEC256 into VEC512
588 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
593 // vinsertps - insert f32 to XMM
594 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
595 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
596 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
597 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
599 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
600 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
601 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
602 [(set VR128X:$dst, (X86insertps VR128X:$src1,
603 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
604 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
606 //===----------------------------------------------------------------------===//
607 // AVX-512 VECTOR EXTRACT
610 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
611 X86VectorVTInfo To> {
612 // A subvector extract from the first vector position is
613 // a subregister copy that needs no instruction.
614 def NAME # To.NumElts:
615 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
616 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
619 multiclass vextract_for_size<int Opcode,
620 X86VectorVTInfo From, X86VectorVTInfo To,
621 PatFrag vextract_extract> :
622 vextract_for_size_first_position_lowering<From, To> {
624 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
625 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
626 // vextract_extract), we interesting only in patterns without mask,
627 // intrinsics pattern match generated bellow.
628 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
629 (ins From.RC:$src1, i32u8imm:$idx),
630 "vextract" # To.EltTypeName # "x" # To.NumElts,
631 "$idx, $src1", "$src1, $idx",
632 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
634 AVX512AIi8Base, EVEX;
635 let mayStore = 1 in {
636 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
637 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
638 "vextract" # To.EltTypeName # "x" # To.NumElts #
639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
643 (ins To.MemOp:$dst, To.KRCWM:$mask,
644 From.RC:$src1, i32u8imm:$src2),
645 "vextract" # To.EltTypeName # "x" # To.NumElts #
646 "\t{$src2, $src1, $dst {${mask}}|"
647 "$dst {${mask}}, $src1, $src2}",
652 // Intrinsic call with masking.
653 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
654 "x" # To.NumElts # "_" # From.Size)
655 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
656 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
657 From.ZSuffix # "rrk")
659 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
660 From.RC:$src1, imm:$idx)>;
662 // Intrinsic call with zero-masking.
663 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
664 "x" # To.NumElts # "_" # From.Size)
665 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
666 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
667 From.ZSuffix # "rrkz")
668 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
669 From.RC:$src1, imm:$idx)>;
671 // Intrinsic call without masking.
672 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
673 "x" # To.NumElts # "_" # From.Size)
674 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
675 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
677 From.RC:$src1, imm:$idx)>;
680 // This multiclass generates patterns for matching vextract with common types
681 // (X86VectorVTInfo From , X86VectorVTInfo To) and alternative types
682 // (X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo)
683 multiclass vextract_for_size_all<int Opcode,
684 X86VectorVTInfo From, X86VectorVTInfo To,
685 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
686 PatFrag vextract_extract,
687 SDNodeXForm EXTRACT_get_vextract_imm> :
688 vextract_for_size<Opcode, From, To, vextract_extract>,
689 vextract_for_size_first_position_lowering<AltFrom, AltTo> {
691 // Codegen pattern with the alternative types.
692 // Only add this if operation not supported natively via AVX512DQ
693 let Predicates = [NoDQI] in
694 def : Pat<(vextract_extract:$ext (AltFrom.VT AltFrom.RC:$src1), (iPTR imm)),
695 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x" #
696 To.NumElts # From.ZSuffix # "rr")
698 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
701 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
702 ValueType EltVT64, int Opcode256> {
703 defm NAME # "32x4Z" : vextract_for_size_all<Opcode128,
704 X86VectorVTInfo<16, EltVT32, VR512>,
705 X86VectorVTInfo< 4, EltVT32, VR128X>,
706 X86VectorVTInfo< 8, EltVT64, VR512>,
707 X86VectorVTInfo< 2, EltVT64, VR128X>,
709 EXTRACT_get_vextract128_imm>,
710 EVEX_V512, EVEX_CD8<32, CD8VT4>;
711 defm NAME # "64x4Z" : vextract_for_size_all<Opcode256,
712 X86VectorVTInfo< 8, EltVT64, VR512>,
713 X86VectorVTInfo< 4, EltVT64, VR256X>,
714 X86VectorVTInfo<16, EltVT32, VR512>,
715 X86VectorVTInfo< 8, EltVT32, VR256>,
717 EXTRACT_get_vextract256_imm>,
718 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
719 let Predicates = [HasVLX] in
720 defm NAME # "32x4Z256" : vextract_for_size_all<Opcode128,
721 X86VectorVTInfo< 8, EltVT32, VR256X>,
722 X86VectorVTInfo< 4, EltVT32, VR128X>,
723 X86VectorVTInfo< 4, EltVT64, VR256X>,
724 X86VectorVTInfo< 2, EltVT64, VR128X>,
726 EXTRACT_get_vextract128_imm>,
727 EVEX_V256, EVEX_CD8<32, CD8VT4>;
728 let Predicates = [HasVLX, HasDQI] in
729 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
730 X86VectorVTInfo< 4, EltVT64, VR256X>,
731 X86VectorVTInfo< 2, EltVT64, VR128X>,
732 vextract128_extract>,
733 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
734 let Predicates = [HasDQI] in {
735 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
736 X86VectorVTInfo< 8, EltVT64, VR512>,
737 X86VectorVTInfo< 2, EltVT64, VR128X>,
738 vextract128_extract>,
739 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
740 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
741 X86VectorVTInfo<16, EltVT32, VR512>,
742 X86VectorVTInfo< 8, EltVT32, VR256X>,
743 vextract256_extract>,
744 EVEX_V512, EVEX_CD8<32, CD8VT8>;
748 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
749 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
751 // A 128-bit subvector insert to the first 512-bit vector position
752 // is a subregister copy that needs no instruction.
753 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
754 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
755 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
757 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
758 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
759 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
761 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
762 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
763 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
765 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
766 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
767 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
770 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
771 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
772 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
773 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
774 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
775 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
776 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
777 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
779 // vextractps - extract 32 bits from XMM
780 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
781 (ins VR128X:$src1, u8imm:$src2),
782 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
783 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
786 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
787 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
788 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
789 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
790 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
792 //===---------------------------------------------------------------------===//
795 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
796 ValueType svt, X86VectorVTInfo _> {
797 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
798 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
799 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
803 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
804 (ins _.ScalarMemOp:$src),
805 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
806 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
811 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
812 AVX512VLVectorVTInfo _> {
813 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
816 let Predicates = [HasVLX] in {
817 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
822 let ExeDomain = SSEPackedSingle in {
823 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
824 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
825 let Predicates = [HasVLX] in {
826 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
827 v4f32, v4f32x_info>, EVEX_V128,
828 EVEX_CD8<32, CD8VT1>;
832 let ExeDomain = SSEPackedDouble in {
833 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
834 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
837 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
838 // Later, we can canonize broadcast instructions before ISel phase and
839 // eliminate additional patterns on ISel.
840 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
841 // representations of source
842 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
843 X86VectorVTInfo _, RegisterClass SrcRC_v,
844 RegisterClass SrcRC_s> {
845 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
846 (!cast<Instruction>(InstName##"r")
847 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
849 let AddedComplexity = 30 in {
850 def : Pat<(_.VT (vselect _.KRCWM:$mask,
851 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
852 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
853 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
855 def : Pat<(_.VT(vselect _.KRCWM:$mask,
856 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
857 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
858 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
862 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
864 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
867 let Predicates = [HasVLX] in {
868 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
869 v8f32x_info, VR128X, FR32X>;
870 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
871 v4f32x_info, VR128X, FR32X>;
872 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
873 v4f64x_info, VR128X, FR64X>;
876 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
877 (VBROADCASTSSZm addr:$src)>;
878 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
879 (VBROADCASTSDZm addr:$src)>;
881 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
882 (VBROADCASTSSZm addr:$src)>;
883 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
884 (VBROADCASTSDZm addr:$src)>;
886 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
887 RegisterClass SrcRC> {
888 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
889 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
890 "$src", "$src", []>, T8PD, EVEX;
893 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
894 RegisterClass SrcRC, Predicate prd> {
895 let Predicates = [prd] in
896 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
897 let Predicates = [prd, HasVLX] in {
898 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
899 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
903 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
905 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
907 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
909 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
912 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
913 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
915 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
916 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
918 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
919 (VPBROADCASTDrZr GR32:$src)>;
920 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
921 (VPBROADCASTQrZr GR64:$src)>;
923 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
924 (VPBROADCASTDrZr GR32:$src)>;
925 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
926 (VPBROADCASTQrZr GR64:$src)>;
928 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
929 (v16i32 immAllZerosV), (i16 GR16:$mask))),
930 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
931 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
932 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
933 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
935 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
936 X86MemOperand x86memop, PatFrag ld_frag,
937 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
939 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
940 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
942 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
943 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
945 !strconcat(OpcodeStr,
946 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
948 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
950 !strconcat(OpcodeStr,
951 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
954 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
957 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
958 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
960 !strconcat(OpcodeStr,
961 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
963 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
965 !strconcat(OpcodeStr,
966 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
967 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
968 (X86VBroadcast (ld_frag addr:$src)),
969 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
973 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
974 loadi32, VR512, v16i32, v4i32, VK16WM>,
975 EVEX_V512, EVEX_CD8<32, CD8VT1>;
976 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
977 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
978 EVEX_CD8<64, CD8VT1>;
980 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
981 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
983 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
984 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
986 (_Dst.VT (X86SubVBroadcast
987 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
988 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
990 !strconcat(OpcodeStr,
991 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
993 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
995 !strconcat(OpcodeStr,
996 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1001 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1002 v16i32_info, v4i32x_info>,
1003 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1004 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1005 v16f32_info, v4f32x_info>,
1006 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1007 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1008 v8i64_info, v4i64x_info>, VEX_W,
1009 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1010 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1011 v8f64_info, v4f64x_info>, VEX_W,
1012 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1014 let Predicates = [HasVLX] in {
1015 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1016 v8i32x_info, v4i32x_info>,
1017 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1018 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1019 v8f32x_info, v4f32x_info>,
1020 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1022 let Predicates = [HasVLX, HasDQI] in {
1023 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1024 v4i64x_info, v2i64x_info>, VEX_W,
1025 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1026 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1027 v4f64x_info, v2f64x_info>, VEX_W,
1028 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1030 let Predicates = [HasDQI] in {
1031 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1032 v8i64_info, v2i64x_info>, VEX_W,
1033 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1034 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1035 v16i32_info, v8i32x_info>,
1036 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1037 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1038 v8f64_info, v2f64x_info>, VEX_W,
1039 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1040 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1041 v16f32_info, v8f32x_info>,
1042 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1045 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
1046 (VPBROADCASTDZrr VR128X:$src)>;
1047 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
1048 (VPBROADCASTQZrr VR128X:$src)>;
1050 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1051 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1052 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1053 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1055 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1056 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1057 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1058 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1060 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
1061 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
1062 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
1063 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
1065 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
1066 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
1067 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
1068 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
1070 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1071 (VBROADCASTSSZr VR128X:$src)>;
1072 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1073 (VBROADCASTSDZr VR128X:$src)>;
1075 // Provide fallback in case the load node that is used in the patterns above
1076 // is used by additional users, which prevents the pattern selection.
1077 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1078 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1079 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1080 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1083 //===----------------------------------------------------------------------===//
1084 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1087 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1088 RegisterClass KRC> {
1089 let Predicates = [HasCDI] in
1090 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
1091 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1092 []>, EVEX, EVEX_V512;
1094 let Predicates = [HasCDI, HasVLX] in {
1095 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
1096 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1097 []>, EVEX, EVEX_V128;
1098 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
1099 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1100 []>, EVEX, EVEX_V256;
1104 let Predicates = [HasCDI] in {
1105 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1107 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1111 //===----------------------------------------------------------------------===//
1114 // -- immediate form --
1115 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1116 X86VectorVTInfo _> {
1117 let ExeDomain = _.ExeDomain in {
1118 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
1119 (ins _.RC:$src1, u8imm:$src2),
1120 !strconcat(OpcodeStr,
1121 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1123 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
1125 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
1126 (ins _.MemOp:$src1, u8imm:$src2),
1127 !strconcat(OpcodeStr,
1128 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1130 (_.VT (OpNode (_.LdFrag addr:$src1),
1131 (i8 imm:$src2))))]>,
1132 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
1136 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
1137 X86VectorVTInfo Ctrl> :
1138 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
1139 let ExeDomain = _.ExeDomain in {
1140 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
1141 (ins _.RC:$src1, _.RC:$src2),
1142 !strconcat("vpermil" # _.Suffix,
1143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1145 (_.VT (X86VPermilpv _.RC:$src1,
1146 (Ctrl.VT Ctrl.RC:$src2))))]>,
1148 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
1149 (ins _.RC:$src1, Ctrl.MemOp:$src2),
1150 !strconcat("vpermil" # _.Suffix,
1151 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1153 (_.VT (X86VPermilpv _.RC:$src1,
1154 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
1158 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
1160 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1163 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1164 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1165 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1166 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1168 // -- VPERM2I - 3 source operands form --
1169 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1170 SDNode OpNode, X86VectorVTInfo _> {
1171 let Constraints = "$src1 = $dst" in {
1172 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1173 (ins _.RC:$src2, _.RC:$src3),
1174 OpcodeStr, "$src3, $src2", "$src2, $src3",
1175 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1179 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1180 (ins _.RC:$src2, _.MemOp:$src3),
1181 OpcodeStr, "$src3, $src2", "$src2, $src3",
1182 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1183 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1184 EVEX_4V, AVX5128IBase;
1187 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1188 SDNode OpNode, X86VectorVTInfo _> {
1189 let mayLoad = 1, Constraints = "$src1 = $dst" in
1190 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1191 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1192 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1193 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1194 (_.VT (OpNode _.RC:$src1,
1195 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1196 AVX5128IBase, EVEX_4V, EVEX_B;
1199 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1200 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1201 let Predicates = [HasAVX512] in
1202 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1203 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1204 let Predicates = [HasVLX] in {
1205 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1206 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1208 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1209 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1213 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1214 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1215 let Predicates = [HasBWI] in
1216 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1217 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1219 let Predicates = [HasBWI, HasVLX] in {
1220 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1221 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1223 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1224 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1228 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1229 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1230 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1231 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1232 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1233 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1234 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1235 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1237 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1238 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1239 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1240 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1241 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1242 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1243 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1244 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1246 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1247 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1248 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1249 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1251 //===----------------------------------------------------------------------===//
1252 // AVX-512 - BLEND using mask
1254 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1255 let ExeDomain = _.ExeDomain in {
1256 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1257 (ins _.RC:$src1, _.RC:$src2),
1258 !strconcat(OpcodeStr,
1259 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1261 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1262 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1263 !strconcat(OpcodeStr,
1264 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1265 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1266 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1267 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1268 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1269 !strconcat(OpcodeStr,
1270 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1271 []>, EVEX_4V, EVEX_KZ;
1272 let mayLoad = 1 in {
1273 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1274 (ins _.RC:$src1, _.MemOp:$src2),
1275 !strconcat(OpcodeStr,
1276 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1277 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1278 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1279 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1280 !strconcat(OpcodeStr,
1281 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1282 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1283 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1284 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1285 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1286 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1287 !strconcat(OpcodeStr,
1288 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1289 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1293 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1295 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1296 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1297 !strconcat(OpcodeStr,
1298 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1299 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1300 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1301 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1302 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1304 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1305 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1306 !strconcat(OpcodeStr,
1307 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1308 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1309 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1313 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1314 AVX512VLVectorVTInfo VTInfo> {
1315 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1316 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1318 let Predicates = [HasVLX] in {
1319 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1320 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1321 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1322 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1326 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1327 AVX512VLVectorVTInfo VTInfo> {
1328 let Predicates = [HasBWI] in
1329 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1331 let Predicates = [HasBWI, HasVLX] in {
1332 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1333 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1338 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1339 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1340 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1341 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1342 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1343 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1346 let Predicates = [HasAVX512] in {
1347 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1348 (v8f32 VR256X:$src2))),
1350 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1351 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1352 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1354 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1355 (v8i32 VR256X:$src2))),
1357 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1358 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1359 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1361 //===----------------------------------------------------------------------===//
1362 // Compare Instructions
1363 //===----------------------------------------------------------------------===//
1365 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1367 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1369 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1371 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1372 "vcmp${cc}"#_.Suffix,
1373 "$src2, $src1", "$src1, $src2",
1374 (OpNode (_.VT _.RC:$src1),
1378 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1380 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1381 "vcmp${cc}"#_.Suffix,
1382 "$src2, $src1", "$src1, $src2",
1383 (OpNode (_.VT _.RC:$src1),
1384 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1385 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1387 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1389 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1390 "vcmp${cc}"#_.Suffix,
1391 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1392 (OpNodeRnd (_.VT _.RC:$src1),
1395 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1396 // Accept explicit immediate argument form instead of comparison code.
1397 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1398 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1400 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1402 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1403 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1405 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1407 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1408 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1410 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1412 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1414 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1416 }// let isAsmParserOnly = 1, hasSideEffects = 0
1418 let isCodeGenOnly = 1 in {
1419 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1420 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1421 !strconcat("vcmp${cc}", _.Suffix,
1422 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1423 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1426 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1428 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1430 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1431 !strconcat("vcmp${cc}", _.Suffix,
1432 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1433 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1434 (_.ScalarLdFrag addr:$src2),
1436 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1440 let Predicates = [HasAVX512] in {
1441 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1443 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1444 AVX512XDIi8Base, VEX_W;
1447 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1448 X86VectorVTInfo _> {
1449 def rr : AVX512BI<opc, MRMSrcReg,
1450 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1451 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1452 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1453 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1455 def rm : AVX512BI<opc, MRMSrcMem,
1456 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1457 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1458 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1459 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1460 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1461 def rrk : AVX512BI<opc, MRMSrcReg,
1462 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1463 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1464 "$dst {${mask}}, $src1, $src2}"),
1465 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1466 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1467 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1469 def rmk : AVX512BI<opc, MRMSrcMem,
1470 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1471 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1472 "$dst {${mask}}, $src1, $src2}"),
1473 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1474 (OpNode (_.VT _.RC:$src1),
1476 (_.LdFrag addr:$src2))))))],
1477 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1480 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1481 X86VectorVTInfo _> :
1482 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1483 let mayLoad = 1 in {
1484 def rmb : AVX512BI<opc, MRMSrcMem,
1485 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1486 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1487 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1488 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1489 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1490 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1491 def rmbk : AVX512BI<opc, MRMSrcMem,
1492 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1493 _.ScalarMemOp:$src2),
1494 !strconcat(OpcodeStr,
1495 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1496 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1497 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1498 (OpNode (_.VT _.RC:$src1),
1500 (_.ScalarLdFrag addr:$src2)))))],
1501 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1505 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1506 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1507 let Predicates = [prd] in
1508 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1511 let Predicates = [prd, HasVLX] in {
1512 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1514 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1519 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1520 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1522 let Predicates = [prd] in
1523 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1526 let Predicates = [prd, HasVLX] in {
1527 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1529 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1534 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1535 avx512vl_i8_info, HasBWI>,
1538 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1539 avx512vl_i16_info, HasBWI>,
1540 EVEX_CD8<16, CD8VF>;
1542 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1543 avx512vl_i32_info, HasAVX512>,
1544 EVEX_CD8<32, CD8VF>;
1546 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1547 avx512vl_i64_info, HasAVX512>,
1548 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1550 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1551 avx512vl_i8_info, HasBWI>,
1554 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1555 avx512vl_i16_info, HasBWI>,
1556 EVEX_CD8<16, CD8VF>;
1558 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1559 avx512vl_i32_info, HasAVX512>,
1560 EVEX_CD8<32, CD8VF>;
1562 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1563 avx512vl_i64_info, HasAVX512>,
1564 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1566 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1567 (COPY_TO_REGCLASS (VPCMPGTDZrr
1568 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1569 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1571 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1572 (COPY_TO_REGCLASS (VPCMPEQDZrr
1573 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1574 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1576 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1577 X86VectorVTInfo _> {
1578 def rri : AVX512AIi8<opc, MRMSrcReg,
1579 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1580 !strconcat("vpcmp${cc}", Suffix,
1581 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1582 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1584 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1586 def rmi : AVX512AIi8<opc, MRMSrcMem,
1587 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1588 !strconcat("vpcmp${cc}", Suffix,
1589 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1590 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1591 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1593 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1594 def rrik : AVX512AIi8<opc, MRMSrcReg,
1595 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1597 !strconcat("vpcmp${cc}", Suffix,
1598 "\t{$src2, $src1, $dst {${mask}}|",
1599 "$dst {${mask}}, $src1, $src2}"),
1600 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1601 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1603 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1605 def rmik : AVX512AIi8<opc, MRMSrcMem,
1606 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1608 !strconcat("vpcmp${cc}", Suffix,
1609 "\t{$src2, $src1, $dst {${mask}}|",
1610 "$dst {${mask}}, $src1, $src2}"),
1611 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1612 (OpNode (_.VT _.RC:$src1),
1613 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1615 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1617 // Accept explicit immediate argument form instead of comparison code.
1618 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1619 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1620 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1621 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1622 "$dst, $src1, $src2, $cc}"),
1623 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1625 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1626 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1627 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1628 "$dst, $src1, $src2, $cc}"),
1629 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1630 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1631 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1633 !strconcat("vpcmp", Suffix,
1634 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1635 "$dst {${mask}}, $src1, $src2, $cc}"),
1636 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1638 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1639 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1641 !strconcat("vpcmp", Suffix,
1642 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1643 "$dst {${mask}}, $src1, $src2, $cc}"),
1644 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1648 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1649 X86VectorVTInfo _> :
1650 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1651 def rmib : AVX512AIi8<opc, MRMSrcMem,
1652 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1654 !strconcat("vpcmp${cc}", Suffix,
1655 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1656 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1657 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1658 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1660 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1661 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1662 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1663 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1664 !strconcat("vpcmp${cc}", Suffix,
1665 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1666 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1667 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1668 (OpNode (_.VT _.RC:$src1),
1669 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1671 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1673 // Accept explicit immediate argument form instead of comparison code.
1674 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1675 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1676 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1678 !strconcat("vpcmp", Suffix,
1679 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1680 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1681 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1682 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1683 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1684 _.ScalarMemOp:$src2, u8imm:$cc),
1685 !strconcat("vpcmp", Suffix,
1686 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1687 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1688 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1692 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1693 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1694 let Predicates = [prd] in
1695 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1697 let Predicates = [prd, HasVLX] in {
1698 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1699 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1703 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1704 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1705 let Predicates = [prd] in
1706 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1709 let Predicates = [prd, HasVLX] in {
1710 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1712 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1717 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1718 HasBWI>, EVEX_CD8<8, CD8VF>;
1719 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1720 HasBWI>, EVEX_CD8<8, CD8VF>;
1722 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1723 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1724 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1725 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1727 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1728 HasAVX512>, EVEX_CD8<32, CD8VF>;
1729 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1730 HasAVX512>, EVEX_CD8<32, CD8VF>;
1732 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1733 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1734 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1735 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1737 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1739 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1740 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1741 "vcmp${cc}"#_.Suffix,
1742 "$src2, $src1", "$src1, $src2",
1743 (X86cmpm (_.VT _.RC:$src1),
1747 let mayLoad = 1 in {
1748 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1749 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1750 "vcmp${cc}"#_.Suffix,
1751 "$src2, $src1", "$src1, $src2",
1752 (X86cmpm (_.VT _.RC:$src1),
1753 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1756 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1758 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1759 "vcmp${cc}"#_.Suffix,
1760 "${src2}"##_.BroadcastStr##", $src1",
1761 "$src1, ${src2}"##_.BroadcastStr,
1762 (X86cmpm (_.VT _.RC:$src1),
1763 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1766 // Accept explicit immediate argument form instead of comparison code.
1767 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1768 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1770 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1772 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1774 let mayLoad = 1 in {
1775 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1777 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1779 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1781 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1783 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1785 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1786 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1791 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1792 // comparison code form (VCMP[EQ/LT/LE/...]
1793 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1794 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1795 "vcmp${cc}"#_.Suffix,
1796 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1797 (X86cmpmRnd (_.VT _.RC:$src1),
1800 (i32 FROUND_NO_EXC))>, EVEX_B;
1802 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1803 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1805 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1807 "$cc,{sae}, $src2, $src1",
1808 "$src1, $src2,{sae}, $cc">, EVEX_B;
1812 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1813 let Predicates = [HasAVX512] in {
1814 defm Z : avx512_vcmp_common<_.info512>,
1815 avx512_vcmp_sae<_.info512>, EVEX_V512;
1818 let Predicates = [HasAVX512,HasVLX] in {
1819 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1820 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1824 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1825 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1826 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1827 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1829 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1830 (COPY_TO_REGCLASS (VCMPPSZrri
1831 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1832 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1834 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1835 (COPY_TO_REGCLASS (VPCMPDZrri
1836 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1837 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1839 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1840 (COPY_TO_REGCLASS (VPCMPUDZrri
1841 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1842 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1845 // ----------------------------------------------------------------
1847 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1848 // fpclass(reg_vec, mem_vec, imm)
1849 // fpclass(reg_vec, broadcast(eltVt), imm)
1850 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1851 X86VectorVTInfo _, string mem, string broadcast>{
1852 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1853 (ins _.RC:$src1, i32u8imm:$src2),
1854 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1855 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1856 (i32 imm:$src2)))], NoItinerary>;
1857 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1858 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1859 OpcodeStr##_.Suffix#
1860 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1861 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1862 (OpNode (_.VT _.RC:$src1),
1863 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1864 let mayLoad = 1 in {
1865 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1866 (ins _.MemOp:$src1, i32u8imm:$src2),
1867 OpcodeStr##_.Suffix##mem#
1868 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1869 [(set _.KRC:$dst,(OpNode
1870 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1871 (i32 imm:$src2)))], NoItinerary>;
1872 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1873 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1874 OpcodeStr##_.Suffix##mem#
1875 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1876 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1877 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1878 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1879 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1880 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1881 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1882 _.BroadcastStr##", $dst | $dst, ${src1}"
1883 ##_.BroadcastStr##", $src2}",
1884 [(set _.KRC:$dst,(OpNode
1885 (_.VT (X86VBroadcast
1886 (_.ScalarLdFrag addr:$src1))),
1887 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1888 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1889 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1890 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1891 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1892 _.BroadcastStr##", $src2}",
1893 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1894 (_.VT (X86VBroadcast
1895 (_.ScalarLdFrag addr:$src1))),
1896 (i32 imm:$src2))))], NoItinerary>,
1902 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1903 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1905 let Predicates = [prd] in {
1906 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1907 broadcast>, EVEX_V512;
1909 let Predicates = [prd, HasVLX] in {
1910 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1911 broadcast>, EVEX_V128;
1912 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1913 broadcast>, EVEX_V256;
1917 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1918 SDNode OpNode, Predicate prd>{
1919 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1920 OpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1921 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1922 OpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1925 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, X86Vfpclass, HasDQI>,
1926 AVX512AIi8Base,EVEX;
1928 //-----------------------------------------------------------------
1929 // Mask register copy, including
1930 // - copy between mask registers
1931 // - load/store mask registers
1932 // - copy from GPR to mask register and vice versa
1934 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1935 string OpcodeStr, RegisterClass KRC,
1936 ValueType vvt, X86MemOperand x86memop> {
1937 let hasSideEffects = 0 in {
1938 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1939 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1941 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1942 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1943 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1945 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1946 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1947 [(store KRC:$src, addr:$dst)]>;
1951 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1953 RegisterClass KRC, RegisterClass GRC> {
1954 let hasSideEffects = 0 in {
1955 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1956 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1957 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1958 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1962 let Predicates = [HasDQI] in
1963 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1964 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1967 let Predicates = [HasAVX512] in
1968 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1969 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1972 let Predicates = [HasBWI] in {
1973 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1975 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1979 let Predicates = [HasBWI] in {
1980 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1982 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1986 // GR from/to mask register
1987 let Predicates = [HasDQI] in {
1988 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1989 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1990 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1991 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1993 let Predicates = [HasAVX512] in {
1994 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1995 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1996 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1997 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1999 let Predicates = [HasBWI] in {
2000 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2001 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2003 let Predicates = [HasBWI] in {
2004 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2005 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2009 let Predicates = [HasDQI] in {
2010 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2011 (KMOVBmk addr:$dst, VK8:$src)>;
2012 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2013 (KMOVBkm addr:$src)>;
2015 def : Pat<(store VK4:$src, addr:$dst),
2016 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2017 def : Pat<(store VK2:$src, addr:$dst),
2018 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2020 let Predicates = [HasAVX512, NoDQI] in {
2021 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2022 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2023 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2024 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2026 let Predicates = [HasAVX512] in {
2027 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2028 (KMOVWmk addr:$dst, VK16:$src)>;
2029 def : Pat<(i1 (load addr:$src)),
2030 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2031 (MOV8rm addr:$src), sub_8bit)),
2033 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2034 (KMOVWkm addr:$src)>;
2036 let Predicates = [HasBWI] in {
2037 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2038 (KMOVDmk addr:$dst, VK32:$src)>;
2039 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2040 (KMOVDkm addr:$src)>;
2042 let Predicates = [HasBWI] in {
2043 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2044 (KMOVQmk addr:$dst, VK64:$src)>;
2045 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2046 (KMOVQkm addr:$src)>;
2049 let Predicates = [HasAVX512] in {
2050 def : Pat<(i1 (trunc (i64 GR64:$src))),
2051 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2054 def : Pat<(i1 (trunc (i32 GR32:$src))),
2055 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2057 def : Pat<(i1 (trunc (i8 GR8:$src))),
2059 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2061 def : Pat<(i1 (trunc (i16 GR16:$src))),
2063 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2066 def : Pat<(i32 (zext VK1:$src)),
2067 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2068 def : Pat<(i32 (anyext VK1:$src)),
2069 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2071 def : Pat<(i8 (zext VK1:$src)),
2074 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2075 def : Pat<(i8 (anyext VK1:$src)),
2077 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2079 def : Pat<(i64 (zext VK1:$src)),
2080 (AND64ri8 (SUBREG_TO_REG (i64 0),
2081 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2082 def : Pat<(i16 (zext VK1:$src)),
2084 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2086 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2087 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2088 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2089 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2091 let Predicates = [HasBWI] in {
2092 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2093 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2094 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2095 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2099 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2100 let Predicates = [HasAVX512, NoDQI] in {
2101 // GR from/to 8-bit mask without native support
2102 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2104 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2105 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2107 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2111 let Predicates = [HasAVX512] in {
2112 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2113 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2114 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2115 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2117 let Predicates = [HasBWI] in {
2118 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2119 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2120 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2121 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2124 // Mask unary operation
2126 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2127 RegisterClass KRC, SDPatternOperator OpNode,
2129 let Predicates = [prd] in
2130 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2131 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2132 [(set KRC:$dst, (OpNode KRC:$src))]>;
2135 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2136 SDPatternOperator OpNode> {
2137 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2139 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2140 HasAVX512>, VEX, PS;
2141 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2142 HasBWI>, VEX, PD, VEX_W;
2143 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2144 HasBWI>, VEX, PS, VEX_W;
2147 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2149 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2150 let Predicates = [HasAVX512] in
2151 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2153 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2154 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2156 defm : avx512_mask_unop_int<"knot", "KNOT">;
2158 let Predicates = [HasDQI] in
2159 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2160 let Predicates = [HasAVX512] in
2161 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2162 let Predicates = [HasBWI] in
2163 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2164 let Predicates = [HasBWI] in
2165 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2167 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2168 let Predicates = [HasAVX512, NoDQI] in {
2169 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2170 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2171 def : Pat<(not VK8:$src),
2173 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2175 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2176 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2177 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2178 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2180 // Mask binary operation
2181 // - KAND, KANDN, KOR, KXNOR, KXOR
2182 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2183 RegisterClass KRC, SDPatternOperator OpNode,
2184 Predicate prd, bit IsCommutable> {
2185 let Predicates = [prd], isCommutable = IsCommutable in
2186 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2187 !strconcat(OpcodeStr,
2188 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2189 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2192 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2193 SDPatternOperator OpNode, bit IsCommutable,
2194 Predicate prdW = HasAVX512> {
2195 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2196 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2197 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2198 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2199 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2200 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2201 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2202 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2205 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2206 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2208 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2209 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2210 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2211 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2212 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2213 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2215 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2216 let Predicates = [HasAVX512] in
2217 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2218 (i16 GR16:$src1), (i16 GR16:$src2)),
2219 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2220 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2221 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2224 defm : avx512_mask_binop_int<"kand", "KAND">;
2225 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2226 defm : avx512_mask_binop_int<"kor", "KOR">;
2227 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2228 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2230 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2231 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2232 // for the DQI set, this type is legal and KxxxB instruction is used
2233 let Predicates = [NoDQI] in
2234 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2236 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2237 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2239 // All types smaller than 8 bits require conversion anyway
2240 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2241 (COPY_TO_REGCLASS (Inst
2242 (COPY_TO_REGCLASS VK1:$src1, VK16),
2243 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2244 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2245 (COPY_TO_REGCLASS (Inst
2246 (COPY_TO_REGCLASS VK2:$src1, VK16),
2247 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2248 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2249 (COPY_TO_REGCLASS (Inst
2250 (COPY_TO_REGCLASS VK4:$src1, VK16),
2251 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2254 defm : avx512_binop_pat<and, KANDWrr>;
2255 defm : avx512_binop_pat<andn, KANDNWrr>;
2256 defm : avx512_binop_pat<or, KORWrr>;
2257 defm : avx512_binop_pat<xnor, KXNORWrr>;
2258 defm : avx512_binop_pat<xor, KXORWrr>;
2260 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2261 (KXNORWrr VK16:$src1, VK16:$src2)>;
2262 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2263 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2264 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2265 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2266 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2267 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2269 let Predicates = [NoDQI] in
2270 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2271 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2272 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2274 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2275 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2276 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2278 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2279 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2280 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2282 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2283 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2284 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2287 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2288 RegisterClass KRCSrc, Predicate prd> {
2289 let Predicates = [prd] in {
2290 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2291 (ins KRC:$src1, KRC:$src2),
2292 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2295 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2296 (!cast<Instruction>(NAME##rr)
2297 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2298 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2302 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2303 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2304 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2306 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2307 let Predicates = [HasAVX512] in
2308 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2309 (i16 GR16:$src1), (i16 GR16:$src2)),
2310 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2311 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2312 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2314 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2317 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2318 SDNode OpNode, Predicate prd> {
2319 let Predicates = [prd], Defs = [EFLAGS] in
2320 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2321 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2322 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2325 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2326 Predicate prdW = HasAVX512> {
2327 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2329 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2331 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2333 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2337 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2338 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2341 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2343 let Predicates = [HasAVX512] in
2344 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2345 !strconcat(OpcodeStr,
2346 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2347 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2350 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2352 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2354 let Predicates = [HasDQI] in
2355 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2357 let Predicates = [HasBWI] in {
2358 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2360 let Predicates = [HasDQI] in
2361 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2366 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2367 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2369 // Mask setting all 0s or 1s
2370 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2371 let Predicates = [HasAVX512] in
2372 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2373 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2374 [(set KRC:$dst, (VT Val))]>;
2377 multiclass avx512_mask_setop_w<PatFrag Val> {
2378 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2379 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2380 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2381 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2384 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2385 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2387 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2388 let Predicates = [HasAVX512] in {
2389 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2390 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2391 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2392 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2393 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2394 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2395 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2397 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2398 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2400 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2401 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2403 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2404 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2406 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2407 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2409 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2410 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2412 let Predicates = [HasVLX] in {
2413 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2414 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2415 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2416 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2417 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2418 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2419 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2420 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2421 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2422 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2425 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2426 (v8i1 (COPY_TO_REGCLASS
2427 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2428 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2430 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2431 (v8i1 (COPY_TO_REGCLASS
2432 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2433 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2435 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2436 (v4i1 (COPY_TO_REGCLASS
2437 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2438 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2440 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2441 (v4i1 (COPY_TO_REGCLASS
2442 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2443 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2445 //===----------------------------------------------------------------------===//
2446 // AVX-512 - Aligned and unaligned load and store
2450 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2451 PatFrag ld_frag, PatFrag mload,
2452 bit IsReMaterializable = 1> {
2453 let hasSideEffects = 0 in {
2454 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2455 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2457 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2458 (ins _.KRCWM:$mask, _.RC:$src),
2459 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2460 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2463 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2464 SchedRW = [WriteLoad] in
2465 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2466 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2467 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2470 let Constraints = "$src0 = $dst" in {
2471 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2472 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2473 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2474 "${dst} {${mask}}, $src1}"),
2475 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2477 (_.VT _.RC:$src0))))], _.ExeDomain>,
2479 let mayLoad = 1, SchedRW = [WriteLoad] in
2480 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2481 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2482 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2483 "${dst} {${mask}}, $src1}"),
2484 [(set _.RC:$dst, (_.VT
2485 (vselect _.KRCWM:$mask,
2486 (_.VT (bitconvert (ld_frag addr:$src1))),
2487 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2489 let mayLoad = 1, SchedRW = [WriteLoad] in
2490 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2491 (ins _.KRCWM:$mask, _.MemOp:$src),
2492 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2493 "${dst} {${mask}} {z}, $src}",
2494 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2495 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2496 _.ExeDomain>, EVEX, EVEX_KZ;
2498 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2499 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2501 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2502 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2504 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2505 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2506 _.KRCWM:$mask, addr:$ptr)>;
2509 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2510 AVX512VLVectorVTInfo _,
2512 bit IsReMaterializable = 1> {
2513 let Predicates = [prd] in
2514 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2515 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2517 let Predicates = [prd, HasVLX] in {
2518 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2519 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2520 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2521 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2525 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2526 AVX512VLVectorVTInfo _,
2528 bit IsReMaterializable = 1> {
2529 let Predicates = [prd] in
2530 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2531 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2533 let Predicates = [prd, HasVLX] in {
2534 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2535 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2536 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2537 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2541 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2542 PatFrag st_frag, PatFrag mstore> {
2543 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2544 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2545 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2547 let Constraints = "$src1 = $dst" in
2548 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2549 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2551 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2552 [], _.ExeDomain>, EVEX, EVEX_K;
2553 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2554 (ins _.KRCWM:$mask, _.RC:$src),
2556 "\t{$src, ${dst} {${mask}} {z}|" #
2557 "${dst} {${mask}} {z}, $src}",
2558 [], _.ExeDomain>, EVEX, EVEX_KZ;
2560 let mayStore = 1 in {
2561 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2562 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2563 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2564 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2565 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2566 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2567 [], _.ExeDomain>, EVEX, EVEX_K;
2570 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2571 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2572 _.KRCWM:$mask, _.RC:$src)>;
2576 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2577 AVX512VLVectorVTInfo _, Predicate prd> {
2578 let Predicates = [prd] in
2579 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2580 masked_store_unaligned>, EVEX_V512;
2582 let Predicates = [prd, HasVLX] in {
2583 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2584 masked_store_unaligned>, EVEX_V256;
2585 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2586 masked_store_unaligned>, EVEX_V128;
2590 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2591 AVX512VLVectorVTInfo _, Predicate prd> {
2592 let Predicates = [prd] in
2593 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2594 masked_store_aligned512>, EVEX_V512;
2596 let Predicates = [prd, HasVLX] in {
2597 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2598 masked_store_aligned256>, EVEX_V256;
2599 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2600 masked_store_aligned128>, EVEX_V128;
2604 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2606 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2607 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2609 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2611 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2612 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2614 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2615 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2616 PS, EVEX_CD8<32, CD8VF>;
2618 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2619 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2620 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2622 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2623 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2624 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2626 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2627 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2628 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2630 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2631 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2632 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2634 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2635 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2636 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2638 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2639 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2640 (VMOVAPDZrm addr:$ptr)>;
2642 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2643 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2644 (VMOVAPSZrm addr:$ptr)>;
2646 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2648 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2650 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2652 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2655 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2657 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2659 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2661 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2664 let Predicates = [HasAVX512, NoVLX] in {
2665 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2666 (VMOVUPSZmrk addr:$ptr,
2667 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2668 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2670 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2671 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2672 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2674 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2675 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2676 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2677 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2680 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2682 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2683 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2685 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2687 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2688 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2690 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2691 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2692 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2694 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2695 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2696 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2698 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2699 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2700 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2702 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2703 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2704 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2706 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2707 (v16i32 immAllZerosV), GR16:$mask)),
2708 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2710 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2711 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2712 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2714 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2716 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2718 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2720 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2723 let AddedComplexity = 20 in {
2724 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2725 (bc_v8i64 (v16i32 immAllZerosV)))),
2726 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2728 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2729 (v8i64 VR512:$src))),
2730 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2733 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2734 (v16i32 immAllZerosV))),
2735 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2737 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2738 (v16i32 VR512:$src))),
2739 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2742 let Predicates = [HasAVX512, NoVLX] in {
2743 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2744 (VMOVDQU32Zmrk addr:$ptr,
2745 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2746 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2748 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2749 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2750 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2753 // Move Int Doubleword to Packed Double Int
2755 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2756 "vmovd\t{$src, $dst|$dst, $src}",
2758 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2760 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2761 "vmovd\t{$src, $dst|$dst, $src}",
2763 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2764 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2765 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2766 "vmovq\t{$src, $dst|$dst, $src}",
2768 (v2i64 (scalar_to_vector GR64:$src)))],
2769 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2770 let isCodeGenOnly = 1 in {
2771 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2772 "vmovq\t{$src, $dst|$dst, $src}",
2773 [(set FR64:$dst, (bitconvert GR64:$src))],
2774 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2775 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2776 "vmovq\t{$src, $dst|$dst, $src}",
2777 [(set GR64:$dst, (bitconvert FR64:$src))],
2778 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2780 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2781 "vmovq\t{$src, $dst|$dst, $src}",
2782 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2783 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2784 EVEX_CD8<64, CD8VT1>;
2786 // Move Int Doubleword to Single Scalar
2788 let isCodeGenOnly = 1 in {
2789 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2790 "vmovd\t{$src, $dst|$dst, $src}",
2791 [(set FR32X:$dst, (bitconvert GR32:$src))],
2792 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2794 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2795 "vmovd\t{$src, $dst|$dst, $src}",
2796 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2797 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2800 // Move doubleword from xmm register to r/m32
2802 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2803 "vmovd\t{$src, $dst|$dst, $src}",
2804 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2805 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2807 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2808 (ins i32mem:$dst, VR128X:$src),
2809 "vmovd\t{$src, $dst|$dst, $src}",
2810 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2811 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2812 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2814 // Move quadword from xmm1 register to r/m64
2816 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2817 "vmovq\t{$src, $dst|$dst, $src}",
2818 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2820 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2821 Requires<[HasAVX512, In64BitMode]>;
2823 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2824 (ins i64mem:$dst, VR128X:$src),
2825 "vmovq\t{$src, $dst|$dst, $src}",
2826 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2827 addr:$dst)], IIC_SSE_MOVDQ>,
2828 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2829 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2831 // Move Scalar Single to Double Int
2833 let isCodeGenOnly = 1 in {
2834 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2836 "vmovd\t{$src, $dst|$dst, $src}",
2837 [(set GR32:$dst, (bitconvert FR32X:$src))],
2838 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2839 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2840 (ins i32mem:$dst, FR32X:$src),
2841 "vmovd\t{$src, $dst|$dst, $src}",
2842 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2843 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2846 // Move Quadword Int to Packed Quadword Int
2848 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2850 "vmovq\t{$src, $dst|$dst, $src}",
2852 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2853 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2855 //===----------------------------------------------------------------------===//
2856 // AVX-512 MOVSS, MOVSD
2857 //===----------------------------------------------------------------------===//
2859 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2860 SDNode OpNode, ValueType vt,
2861 X86MemOperand x86memop, PatFrag mem_pat> {
2862 let hasSideEffects = 0 in {
2863 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2864 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2865 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2866 (scalar_to_vector RC:$src2))))],
2867 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2868 let Constraints = "$src1 = $dst" in
2869 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2870 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2872 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2873 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2874 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2875 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2876 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2878 let mayStore = 1 in {
2879 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2880 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2881 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2883 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2884 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2885 [], IIC_SSE_MOV_S_MR>,
2886 EVEX, VEX_LIG, EVEX_K;
2888 } //hasSideEffects = 0
2891 let ExeDomain = SSEPackedSingle in
2892 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2893 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2895 let ExeDomain = SSEPackedDouble in
2896 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2897 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2899 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2900 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2901 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2903 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2904 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2905 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2907 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2908 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2909 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2911 // For the disassembler
2912 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2913 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2914 (ins VR128X:$src1, FR32X:$src2),
2915 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2917 XS, EVEX_4V, VEX_LIG;
2918 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2919 (ins VR128X:$src1, FR64X:$src2),
2920 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2922 XD, EVEX_4V, VEX_LIG, VEX_W;
2925 let Predicates = [HasAVX512] in {
2926 let AddedComplexity = 15 in {
2927 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2928 // MOVS{S,D} to the lower bits.
2929 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2930 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2931 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2932 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2933 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2934 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2935 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2936 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2938 // Move low f32 and clear high bits.
2939 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2940 (SUBREG_TO_REG (i32 0),
2941 (VMOVSSZrr (v4f32 (V_SET0)),
2942 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2943 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2944 (SUBREG_TO_REG (i32 0),
2945 (VMOVSSZrr (v4i32 (V_SET0)),
2946 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2949 let AddedComplexity = 20 in {
2950 // MOVSSrm zeros the high parts of the register; represent this
2951 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2952 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2953 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2954 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2955 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2956 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2957 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2959 // MOVSDrm zeros the high parts of the register; represent this
2960 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2961 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2962 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2963 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2964 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2965 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2966 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2967 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2968 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2969 def : Pat<(v2f64 (X86vzload addr:$src)),
2970 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2972 // Represent the same patterns above but in the form they appear for
2974 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2975 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2976 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2977 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2978 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2979 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2980 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2981 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2982 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2984 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2985 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2986 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2987 FR32X:$src)), sub_xmm)>;
2988 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2989 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2990 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2991 FR64X:$src)), sub_xmm)>;
2992 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2993 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2994 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2996 // Move low f64 and clear high bits.
2997 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2998 (SUBREG_TO_REG (i32 0),
2999 (VMOVSDZrr (v2f64 (V_SET0)),
3000 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3002 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3003 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3004 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3006 // Extract and store.
3007 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
3009 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3010 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
3012 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3014 // Shuffle with VMOVSS
3015 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3016 (VMOVSSZrr (v4i32 VR128X:$src1),
3017 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3018 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3019 (VMOVSSZrr (v4f32 VR128X:$src1),
3020 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3023 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3024 (SUBREG_TO_REG (i32 0),
3025 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3026 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3028 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3029 (SUBREG_TO_REG (i32 0),
3030 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3031 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3034 // Shuffle with VMOVSD
3035 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3036 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3037 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3038 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3039 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3040 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3041 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3042 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3045 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3046 (SUBREG_TO_REG (i32 0),
3047 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3048 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3050 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3051 (SUBREG_TO_REG (i32 0),
3052 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3053 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3056 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3057 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3058 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3059 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3060 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3061 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3062 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3063 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3066 let AddedComplexity = 15 in
3067 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3069 "vmovq\t{$src, $dst|$dst, $src}",
3070 [(set VR128X:$dst, (v2i64 (X86vzmovl
3071 (v2i64 VR128X:$src))))],
3072 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3074 let AddedComplexity = 20 in
3075 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3077 "vmovq\t{$src, $dst|$dst, $src}",
3078 [(set VR128X:$dst, (v2i64 (X86vzmovl
3079 (loadv2i64 addr:$src))))],
3080 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3081 EVEX_CD8<8, CD8VT8>;
3083 let Predicates = [HasAVX512] in {
3084 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3085 let AddedComplexity = 20 in {
3086 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3087 (VMOVDI2PDIZrm addr:$src)>;
3088 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3089 (VMOV64toPQIZrr GR64:$src)>;
3090 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3091 (VMOVDI2PDIZrr GR32:$src)>;
3093 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3094 (VMOVDI2PDIZrm addr:$src)>;
3095 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3096 (VMOVDI2PDIZrm addr:$src)>;
3097 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3098 (VMOVZPQILo2PQIZrm addr:$src)>;
3099 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3100 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3101 def : Pat<(v2i64 (X86vzload addr:$src)),
3102 (VMOVZPQILo2PQIZrm addr:$src)>;
3105 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3106 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3107 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3108 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3109 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3110 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3111 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3114 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3115 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3117 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3118 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3120 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3121 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3123 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3124 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3126 //===----------------------------------------------------------------------===//
3127 // AVX-512 - Non-temporals
3128 //===----------------------------------------------------------------------===//
3129 let SchedRW = [WriteLoad] in {
3130 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3131 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3132 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3133 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3134 EVEX_CD8<64, CD8VF>;
3136 let Predicates = [HasAVX512, HasVLX] in {
3137 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3139 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3140 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3141 EVEX_CD8<64, CD8VF>;
3143 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3145 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3146 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3147 EVEX_CD8<64, CD8VF>;
3151 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3152 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3153 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3154 let SchedRW = [WriteStore], mayStore = 1,
3155 AddedComplexity = 400 in
3156 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3157 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3158 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3161 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3162 string elty, string elsz, string vsz512,
3163 string vsz256, string vsz128, Domain d,
3164 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3165 let Predicates = [prd] in
3166 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3167 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3168 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3171 let Predicates = [prd, HasVLX] in {
3172 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3173 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3174 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3177 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3178 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3179 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3184 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3185 "i", "64", "8", "4", "2", SSEPackedInt,
3186 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3188 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3189 "f", "64", "8", "4", "2", SSEPackedDouble,
3190 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3192 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3193 "f", "32", "16", "8", "4", SSEPackedSingle,
3194 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3196 //===----------------------------------------------------------------------===//
3197 // AVX-512 - Integer arithmetic
3199 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3200 X86VectorVTInfo _, OpndItins itins,
3201 bit IsCommutable = 0> {
3202 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3203 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3204 "$src2, $src1", "$src1, $src2",
3205 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3206 itins.rr, IsCommutable>,
3207 AVX512BIBase, EVEX_4V;
3210 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3211 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3212 "$src2, $src1", "$src1, $src2",
3213 (_.VT (OpNode _.RC:$src1,
3214 (bitconvert (_.LdFrag addr:$src2)))),
3216 AVX512BIBase, EVEX_4V;
3219 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3220 X86VectorVTInfo _, OpndItins itins,
3221 bit IsCommutable = 0> :
3222 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3224 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3225 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3226 "${src2}"##_.BroadcastStr##", $src1",
3227 "$src1, ${src2}"##_.BroadcastStr,
3228 (_.VT (OpNode _.RC:$src1,
3230 (_.ScalarLdFrag addr:$src2)))),
3232 AVX512BIBase, EVEX_4V, EVEX_B;
3235 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3236 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3237 Predicate prd, bit IsCommutable = 0> {
3238 let Predicates = [prd] in
3239 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3240 IsCommutable>, EVEX_V512;
3242 let Predicates = [prd, HasVLX] in {
3243 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3244 IsCommutable>, EVEX_V256;
3245 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3246 IsCommutable>, EVEX_V128;
3250 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3251 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3252 Predicate prd, bit IsCommutable = 0> {
3253 let Predicates = [prd] in
3254 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3255 IsCommutable>, EVEX_V512;
3257 let Predicates = [prd, HasVLX] in {
3258 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3259 IsCommutable>, EVEX_V256;
3260 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3261 IsCommutable>, EVEX_V128;
3265 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3266 OpndItins itins, Predicate prd,
3267 bit IsCommutable = 0> {
3268 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3269 itins, prd, IsCommutable>,
3270 VEX_W, EVEX_CD8<64, CD8VF>;
3273 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3274 OpndItins itins, Predicate prd,
3275 bit IsCommutable = 0> {
3276 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3277 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3280 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3281 OpndItins itins, Predicate prd,
3282 bit IsCommutable = 0> {
3283 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3284 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3287 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3288 OpndItins itins, Predicate prd,
3289 bit IsCommutable = 0> {
3290 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3291 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3294 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3295 SDNode OpNode, OpndItins itins, Predicate prd,
3296 bit IsCommutable = 0> {
3297 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3300 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3304 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3305 SDNode OpNode, OpndItins itins, Predicate prd,
3306 bit IsCommutable = 0> {
3307 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3310 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3314 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3315 bits<8> opc_d, bits<8> opc_q,
3316 string OpcodeStr, SDNode OpNode,
3317 OpndItins itins, bit IsCommutable = 0> {
3318 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3319 itins, HasAVX512, IsCommutable>,
3320 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3321 itins, HasBWI, IsCommutable>;
3324 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3325 SDNode OpNode,X86VectorVTInfo _Src,
3326 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3327 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3328 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3329 "$src2, $src1","$src1, $src2",
3331 (_Src.VT _Src.RC:$src1),
3332 (_Src.VT _Src.RC:$src2))),
3333 itins.rr, IsCommutable>,
3334 AVX512BIBase, EVEX_4V;
3335 let mayLoad = 1 in {
3336 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3337 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3338 "$src2, $src1", "$src1, $src2",
3339 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3340 (bitconvert (_Src.LdFrag addr:$src2)))),
3342 AVX512BIBase, EVEX_4V;
3344 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3345 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3347 "${src2}"##_Dst.BroadcastStr##", $src1",
3348 "$src1, ${src2}"##_Dst.BroadcastStr,
3349 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3350 (_Dst.VT (X86VBroadcast
3351 (_Dst.ScalarLdFrag addr:$src2)))))),
3353 AVX512BIBase, EVEX_4V, EVEX_B;
3357 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3358 SSE_INTALU_ITINS_P, 1>;
3359 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3360 SSE_INTALU_ITINS_P, 0>;
3361 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3362 SSE_INTALU_ITINS_P, HasBWI, 1>;
3363 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3364 SSE_INTALU_ITINS_P, HasBWI, 0>;
3365 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3366 SSE_INTALU_ITINS_P, HasBWI, 1>;
3367 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3368 SSE_INTALU_ITINS_P, HasBWI, 0>;
3369 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3370 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3371 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3372 SSE_INTALU_ITINS_P, HasBWI, 1>;
3373 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3374 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3375 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3377 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3379 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3381 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3382 SSE_INTALU_ITINS_P, HasBWI, 1>;
3384 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3385 SDNode OpNode, bit IsCommutable = 0> {
3387 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3388 v16i32_info, v8i64_info, IsCommutable>,
3389 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3390 let Predicates = [HasVLX] in {
3391 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3392 v8i32x_info, v4i64x_info, IsCommutable>,
3393 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3394 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3395 v4i32x_info, v2i64x_info, IsCommutable>,
3396 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3400 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3402 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3405 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3406 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3407 let mayLoad = 1 in {
3408 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3409 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3411 "${src2}"##_Src.BroadcastStr##", $src1",
3412 "$src1, ${src2}"##_Src.BroadcastStr,
3413 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3414 (_Src.VT (X86VBroadcast
3415 (_Src.ScalarLdFrag addr:$src2))))))>,
3416 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3420 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3421 SDNode OpNode,X86VectorVTInfo _Src,
3422 X86VectorVTInfo _Dst> {
3423 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3424 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3425 "$src2, $src1","$src1, $src2",
3427 (_Src.VT _Src.RC:$src1),
3428 (_Src.VT _Src.RC:$src2)))>,
3429 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3430 let mayLoad = 1 in {
3431 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3432 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3433 "$src2, $src1", "$src1, $src2",
3434 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3435 (bitconvert (_Src.LdFrag addr:$src2))))>,
3436 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3440 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3442 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3444 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3445 v32i16_info>, EVEX_V512;
3446 let Predicates = [HasVLX] in {
3447 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3449 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3450 v16i16x_info>, EVEX_V256;
3451 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3453 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3454 v8i16x_info>, EVEX_V128;
3457 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3459 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3460 v64i8_info>, EVEX_V512;
3461 let Predicates = [HasVLX] in {
3462 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3463 v32i8x_info>, EVEX_V256;
3464 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3465 v16i8x_info>, EVEX_V128;
3469 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3470 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3471 AVX512VLVectorVTInfo _Dst> {
3472 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3473 _Dst.info512>, EVEX_V512;
3474 let Predicates = [HasVLX] in {
3475 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3476 _Dst.info256>, EVEX_V256;
3477 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3478 _Dst.info128>, EVEX_V128;
3482 let Predicates = [HasBWI] in {
3483 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3484 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3485 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3486 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3488 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3489 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3490 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3491 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3494 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3495 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3496 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3497 SSE_INTALU_ITINS_P, HasBWI, 1>;
3498 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3499 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3501 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3502 SSE_INTALU_ITINS_P, HasBWI, 1>;
3503 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3504 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3505 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3506 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3508 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3509 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3510 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3511 SSE_INTALU_ITINS_P, HasBWI, 1>;
3512 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3513 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3515 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3516 SSE_INTALU_ITINS_P, HasBWI, 1>;
3517 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3518 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3519 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3520 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3521 //===----------------------------------------------------------------------===//
3522 // AVX-512 Logical Instructions
3523 //===----------------------------------------------------------------------===//
3525 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3526 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3527 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3528 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3529 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3530 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3531 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3532 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3534 //===----------------------------------------------------------------------===//
3535 // AVX-512 FP arithmetic
3536 //===----------------------------------------------------------------------===//
3537 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3538 SDNode OpNode, SDNode VecNode, OpndItins itins,
3541 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3542 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3543 "$src2, $src1", "$src1, $src2",
3544 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3545 (i32 FROUND_CURRENT)),
3546 itins.rr, IsCommutable>;
3548 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3549 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3550 "$src2, $src1", "$src1, $src2",
3551 (VecNode (_.VT _.RC:$src1),
3552 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3553 (i32 FROUND_CURRENT)),
3554 itins.rm, IsCommutable>;
3555 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3556 Predicates = [HasAVX512] in {
3557 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3558 (ins _.FRC:$src1, _.FRC:$src2),
3559 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3560 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3562 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3563 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3564 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3565 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3566 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3570 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3571 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3573 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3574 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3575 "$rc, $src2, $src1", "$src1, $src2, $rc",
3576 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3577 (i32 imm:$rc)), itins.rr, IsCommutable>,
3580 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3581 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3583 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3584 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3585 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3586 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3587 (i32 FROUND_NO_EXC))>, EVEX_B;
3590 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3592 SizeItins itins, bit IsCommutable> {
3593 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3594 itins.s, IsCommutable>,
3595 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3596 itins.s, IsCommutable>,
3597 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3598 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3599 itins.d, IsCommutable>,
3600 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3601 itins.d, IsCommutable>,
3602 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3605 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3607 SizeItins itins, bit IsCommutable> {
3608 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3609 itins.s, IsCommutable>,
3610 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3611 itins.s, IsCommutable>,
3612 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3613 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3614 itins.d, IsCommutable>,
3615 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3616 itins.d, IsCommutable>,
3617 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3619 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3620 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3621 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3622 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3623 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3624 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3626 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3627 X86VectorVTInfo _, bit IsCommutable> {
3628 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3629 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3630 "$src2, $src1", "$src1, $src2",
3631 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3632 let mayLoad = 1 in {
3633 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3634 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3635 "$src2, $src1", "$src1, $src2",
3636 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3637 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3638 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3639 "${src2}"##_.BroadcastStr##", $src1",
3640 "$src1, ${src2}"##_.BroadcastStr,
3641 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3642 (_.ScalarLdFrag addr:$src2))))>,
3647 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3648 X86VectorVTInfo _> {
3649 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3650 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3651 "$rc, $src2, $src1", "$src1, $src2, $rc",
3652 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3653 EVEX_4V, EVEX_B, EVEX_RC;
3657 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3658 X86VectorVTInfo _> {
3659 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3660 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3661 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3662 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3666 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3667 bit IsCommutable = 0> {
3668 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3669 IsCommutable>, EVEX_V512, PS,
3670 EVEX_CD8<32, CD8VF>;
3671 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3672 IsCommutable>, EVEX_V512, PD, VEX_W,
3673 EVEX_CD8<64, CD8VF>;
3675 // Define only if AVX512VL feature is present.
3676 let Predicates = [HasVLX] in {
3677 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3678 IsCommutable>, EVEX_V128, PS,
3679 EVEX_CD8<32, CD8VF>;
3680 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3681 IsCommutable>, EVEX_V256, PS,
3682 EVEX_CD8<32, CD8VF>;
3683 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3684 IsCommutable>, EVEX_V128, PD, VEX_W,
3685 EVEX_CD8<64, CD8VF>;
3686 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3687 IsCommutable>, EVEX_V256, PD, VEX_W,
3688 EVEX_CD8<64, CD8VF>;
3692 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3693 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3694 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3695 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3696 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3699 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3700 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3701 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3702 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3703 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3706 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3707 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3708 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3709 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3710 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3711 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3712 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3713 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3714 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3715 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3716 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3717 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3718 let Predicates = [HasDQI] in {
3719 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3720 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3721 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3722 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3725 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3726 X86VectorVTInfo _> {
3727 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3728 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3729 "$src2, $src1", "$src1, $src2",
3730 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3731 let mayLoad = 1 in {
3732 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3733 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3734 "$src2, $src1", "$src1, $src2",
3735 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3736 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3737 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3738 "${src2}"##_.BroadcastStr##", $src1",
3739 "$src1, ${src2}"##_.BroadcastStr,
3740 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3741 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3746 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3747 X86VectorVTInfo _> {
3748 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3749 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3750 "$src2, $src1", "$src1, $src2",
3751 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3752 let mayLoad = 1 in {
3753 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3754 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3755 "$src2, $src1", "$src1, $src2",
3756 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3760 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3761 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3762 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3763 EVEX_V512, EVEX_CD8<32, CD8VF>;
3764 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3765 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3766 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3767 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3768 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3769 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3770 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3771 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3772 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3774 // Define only if AVX512VL feature is present.
3775 let Predicates = [HasVLX] in {
3776 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3777 EVEX_V128, EVEX_CD8<32, CD8VF>;
3778 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3779 EVEX_V256, EVEX_CD8<32, CD8VF>;
3780 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3781 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3782 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3783 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3786 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3788 //===----------------------------------------------------------------------===//
3789 // AVX-512 VPTESTM instructions
3790 //===----------------------------------------------------------------------===//
3792 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3793 X86VectorVTInfo _> {
3794 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3795 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3796 "$src2, $src1", "$src1, $src2",
3797 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3800 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3801 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3802 "$src2, $src1", "$src1, $src2",
3803 (OpNode (_.VT _.RC:$src1),
3804 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3806 EVEX_CD8<_.EltSize, CD8VF>;
3809 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3810 X86VectorVTInfo _> {
3812 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3813 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3814 "${src2}"##_.BroadcastStr##", $src1",
3815 "$src1, ${src2}"##_.BroadcastStr,
3816 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3817 (_.ScalarLdFrag addr:$src2))))>,
3818 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3820 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3821 AVX512VLVectorVTInfo _> {
3822 let Predicates = [HasAVX512] in
3823 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3824 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3826 let Predicates = [HasAVX512, HasVLX] in {
3827 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3828 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3829 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3830 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3834 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3835 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3837 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3838 avx512vl_i64_info>, VEX_W;
3841 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3843 let Predicates = [HasBWI] in {
3844 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3846 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3849 let Predicates = [HasVLX, HasBWI] in {
3851 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3853 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3855 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3857 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3862 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3864 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3865 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3867 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3868 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3870 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3871 (v16i32 VR512:$src2), (i16 -1))),
3872 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3874 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3875 (v8i64 VR512:$src2), (i8 -1))),
3876 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3878 //===----------------------------------------------------------------------===//
3879 // AVX-512 Shift instructions
3880 //===----------------------------------------------------------------------===//
3881 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3882 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3883 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3884 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3885 "$src2, $src1", "$src1, $src2",
3886 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3887 SSE_INTSHIFT_ITINS_P.rr>;
3889 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3890 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3891 "$src2, $src1", "$src1, $src2",
3892 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3894 SSE_INTSHIFT_ITINS_P.rm>;
3897 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3898 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3900 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3901 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3902 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3903 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3904 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3907 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3908 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3909 // src2 is always 128-bit
3910 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3911 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3912 "$src2, $src1", "$src1, $src2",
3913 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3914 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3915 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3916 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3917 "$src2, $src1", "$src1, $src2",
3918 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3919 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3923 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3924 ValueType SrcVT, PatFrag bc_frag,
3925 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3926 let Predicates = [prd] in
3927 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3928 VTInfo.info512>, EVEX_V512,
3929 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3930 let Predicates = [prd, HasVLX] in {
3931 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3932 VTInfo.info256>, EVEX_V256,
3933 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3934 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3935 VTInfo.info128>, EVEX_V128,
3936 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3940 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3941 string OpcodeStr, SDNode OpNode> {
3942 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3943 avx512vl_i32_info, HasAVX512>;
3944 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3945 avx512vl_i64_info, HasAVX512>, VEX_W;
3946 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3947 avx512vl_i16_info, HasBWI>;
3950 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3951 string OpcodeStr, SDNode OpNode,
3952 AVX512VLVectorVTInfo VTInfo> {
3953 let Predicates = [HasAVX512] in
3954 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3956 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3957 VTInfo.info512>, EVEX_V512;
3958 let Predicates = [HasAVX512, HasVLX] in {
3959 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3961 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3962 VTInfo.info256>, EVEX_V256;
3963 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3965 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3966 VTInfo.info128>, EVEX_V128;
3970 multiclass avx512_shift_rmi_w<bits<8> opcw,
3971 Format ImmFormR, Format ImmFormM,
3972 string OpcodeStr, SDNode OpNode> {
3973 let Predicates = [HasBWI] in
3974 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3975 v32i16_info>, EVEX_V512;
3976 let Predicates = [HasVLX, HasBWI] in {
3977 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3978 v16i16x_info>, EVEX_V256;
3979 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3980 v8i16x_info>, EVEX_V128;
3984 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3985 Format ImmFormR, Format ImmFormM,
3986 string OpcodeStr, SDNode OpNode> {
3987 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3988 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3989 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3990 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3993 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3994 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3996 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3997 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3999 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4000 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4002 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4003 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4005 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4006 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4007 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4009 //===-------------------------------------------------------------------===//
4010 // Variable Bit Shifts
4011 //===-------------------------------------------------------------------===//
4012 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4013 X86VectorVTInfo _> {
4014 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4015 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4016 "$src2, $src1", "$src1, $src2",
4017 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4018 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4020 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4021 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4022 "$src2, $src1", "$src1, $src2",
4023 (_.VT (OpNode _.RC:$src1,
4024 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4025 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4026 EVEX_CD8<_.EltSize, CD8VF>;
4029 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4030 X86VectorVTInfo _> {
4032 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4033 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4034 "${src2}"##_.BroadcastStr##", $src1",
4035 "$src1, ${src2}"##_.BroadcastStr,
4036 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4037 (_.ScalarLdFrag addr:$src2))))),
4038 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4039 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4041 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4042 AVX512VLVectorVTInfo _> {
4043 let Predicates = [HasAVX512] in
4044 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4045 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4047 let Predicates = [HasAVX512, HasVLX] in {
4048 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4049 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4050 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4051 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4055 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4057 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4059 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4060 avx512vl_i64_info>, VEX_W;
4063 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4065 let Predicates = [HasBWI] in
4066 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4068 let Predicates = [HasVLX, HasBWI] in {
4070 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4072 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4077 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4078 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4079 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4080 avx512_var_shift_w<0x11, "vpsravw", sra>;
4081 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4082 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4083 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4084 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4086 //===-------------------------------------------------------------------===//
4087 // 1-src variable permutation VPERMW/D/Q
4088 //===-------------------------------------------------------------------===//
4089 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4090 AVX512VLVectorVTInfo _> {
4091 let Predicates = [HasAVX512] in
4092 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4093 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4095 let Predicates = [HasAVX512, HasVLX] in
4096 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4097 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4100 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4101 string OpcodeStr, SDNode OpNode,
4102 AVX512VLVectorVTInfo VTInfo> {
4103 let Predicates = [HasAVX512] in
4104 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4106 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4107 VTInfo.info512>, EVEX_V512;
4108 let Predicates = [HasAVX512, HasVLX] in
4109 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4111 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4112 VTInfo.info256>, EVEX_V256;
4116 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4118 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4120 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4121 avx512vl_i64_info>, VEX_W;
4122 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4124 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4125 avx512vl_f64_info>, VEX_W;
4127 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4128 X86VPermi, avx512vl_i64_info>,
4129 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4130 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4131 X86VPermi, avx512vl_f64_info>,
4132 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4134 //===----------------------------------------------------------------------===//
4135 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4136 //===----------------------------------------------------------------------===//
4138 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4139 X86PShufd, avx512vl_i32_info>,
4140 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4141 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4142 X86PShufhw>, EVEX, AVX512XSIi8Base, VEX_W;
4143 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4144 X86PShuflw>, EVEX, AVX512XDIi8Base, VEX_W;
4146 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4147 let Predicates = [HasBWI] in
4148 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4150 let Predicates = [HasVLX, HasBWI] in {
4151 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4152 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4156 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4158 //===----------------------------------------------------------------------===//
4159 // AVX-512 - MOVDDUP
4160 //===----------------------------------------------------------------------===//
4162 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
4163 X86MemOperand x86memop, PatFrag memop_frag> {
4164 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4165 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4166 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
4167 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4168 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4170 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
4173 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
4174 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4175 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
4176 (VMOVDDUPZrm addr:$src)>;
4178 //===---------------------------------------------------------------------===//
4179 // Replicate Single FP - MOVSHDUP and MOVSLDUP
4180 //===---------------------------------------------------------------------===//
4181 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4182 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4183 X86MemOperand x86memop> {
4184 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4185 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4186 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
4188 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4189 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4190 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
4193 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4194 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4195 EVEX_CD8<32, CD8VF>;
4196 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4197 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4198 EVEX_CD8<32, CD8VF>;
4200 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
4201 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
4202 (VMOVSHDUPZrm addr:$src)>;
4203 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
4204 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
4205 (VMOVSLDUPZrm addr:$src)>;
4207 //===----------------------------------------------------------------------===//
4208 // Move Low to High and High to Low packed FP Instructions
4209 //===----------------------------------------------------------------------===//
4210 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4211 (ins VR128X:$src1, VR128X:$src2),
4212 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4213 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4214 IIC_SSE_MOV_LH>, EVEX_4V;
4215 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4216 (ins VR128X:$src1, VR128X:$src2),
4217 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4218 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4219 IIC_SSE_MOV_LH>, EVEX_4V;
4221 let Predicates = [HasAVX512] in {
4223 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4224 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4225 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4226 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4229 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4230 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4233 //===----------------------------------------------------------------------===//
4234 // FMA - Fused Multiply Operations
4237 let Constraints = "$src1 = $dst" in {
4238 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4239 X86VectorVTInfo _> {
4240 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4241 (ins _.RC:$src2, _.RC:$src3),
4242 OpcodeStr, "$src3, $src2", "$src2, $src3",
4243 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4246 let mayLoad = 1 in {
4247 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4248 (ins _.RC:$src2, _.MemOp:$src3),
4249 OpcodeStr, "$src3, $src2", "$src2, $src3",
4250 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4253 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4254 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4255 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4256 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4258 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4259 AVX512FMA3Base, EVEX_B;
4263 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4264 X86VectorVTInfo _> {
4265 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4266 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4267 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4268 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4269 AVX512FMA3Base, EVEX_B, EVEX_RC;
4271 } // Constraints = "$src1 = $dst"
4273 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4274 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4275 let Predicates = [HasAVX512] in {
4276 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4277 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4278 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4280 let Predicates = [HasVLX, HasAVX512] in {
4281 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4282 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4283 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4284 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4288 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4289 SDNode OpNodeRnd > {
4290 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4292 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4293 avx512vl_f64_info>, VEX_W;
4296 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4297 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4298 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4299 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4300 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4301 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4304 let Constraints = "$src1 = $dst" in {
4305 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4306 X86VectorVTInfo _> {
4307 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4308 (ins _.RC:$src2, _.RC:$src3),
4309 OpcodeStr, "$src3, $src2", "$src2, $src3",
4310 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4313 let mayLoad = 1 in {
4314 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4315 (ins _.RC:$src2, _.MemOp:$src3),
4316 OpcodeStr, "$src3, $src2", "$src2, $src3",
4317 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4320 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4321 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4322 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4323 "$src2, ${src3}"##_.BroadcastStr,
4324 (_.VT (OpNode _.RC:$src2,
4325 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4326 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4330 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4331 X86VectorVTInfo _> {
4332 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4333 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4334 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4335 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4336 AVX512FMA3Base, EVEX_B, EVEX_RC;
4338 } // Constraints = "$src1 = $dst"
4340 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4341 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4342 let Predicates = [HasAVX512] in {
4343 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4344 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4345 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4347 let Predicates = [HasVLX, HasAVX512] in {
4348 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4349 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4350 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4351 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4355 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4356 SDNode OpNodeRnd > {
4357 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4359 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4360 avx512vl_f64_info>, VEX_W;
4363 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4364 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4365 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4366 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4367 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4368 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4370 let Constraints = "$src1 = $dst" in {
4371 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4372 X86VectorVTInfo _> {
4373 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4374 (ins _.RC:$src3, _.RC:$src2),
4375 OpcodeStr, "$src2, $src3", "$src3, $src2",
4376 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4379 let mayLoad = 1 in {
4380 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4381 (ins _.RC:$src3, _.MemOp:$src2),
4382 OpcodeStr, "$src2, $src3", "$src3, $src2",
4383 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4386 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4387 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4388 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4389 "$src3, ${src2}"##_.BroadcastStr,
4390 (_.VT (OpNode _.RC:$src1,
4391 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4392 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4396 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4397 X86VectorVTInfo _> {
4398 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4399 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4400 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4401 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4402 AVX512FMA3Base, EVEX_B, EVEX_RC;
4404 } // Constraints = "$src1 = $dst"
4406 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4407 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4408 let Predicates = [HasAVX512] in {
4409 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4410 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4411 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4413 let Predicates = [HasVLX, HasAVX512] in {
4414 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4415 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4416 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4417 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4421 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4422 SDNode OpNodeRnd > {
4423 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4425 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4426 avx512vl_f64_info>, VEX_W;
4429 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4430 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4431 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4432 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4433 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4434 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4437 let Constraints = "$src1 = $dst" in {
4438 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4439 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4440 dag RHS_r, dag RHS_m > {
4441 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4442 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4443 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4446 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4447 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4448 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4450 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4451 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4452 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4453 AVX512FMA3Base, EVEX_B, EVEX_RC;
4455 let isCodeGenOnly = 1 in {
4456 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4457 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4458 !strconcat(OpcodeStr,
4459 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4462 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4463 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4464 !strconcat(OpcodeStr,
4465 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4467 }// isCodeGenOnly = 1
4469 }// Constraints = "$src1 = $dst"
4471 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4472 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4475 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4476 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4477 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4478 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4479 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4481 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4483 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4484 (_.ScalarLdFrag addr:$src3))))>;
4486 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4487 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4488 (_.VT (OpNode _.RC:$src2,
4489 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4491 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4493 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4495 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4496 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4498 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4499 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4500 (_.VT (OpNode _.RC:$src1,
4501 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4503 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4505 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4507 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4508 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4511 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4512 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4513 let Predicates = [HasAVX512] in {
4514 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4515 OpNodeRnd, f32x_info, "SS">,
4516 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4517 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4518 OpNodeRnd, f64x_info, "SD">,
4519 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4523 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4524 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4525 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4526 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4528 //===----------------------------------------------------------------------===//
4529 // AVX-512 Scalar convert from sign integer to float/double
4530 //===----------------------------------------------------------------------===//
4532 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4533 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4534 PatFrag ld_frag, string asm> {
4535 let hasSideEffects = 0 in {
4536 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4537 (ins DstVT.FRC:$src1, SrcRC:$src),
4538 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4541 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4542 (ins DstVT.FRC:$src1, x86memop:$src),
4543 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4545 } // hasSideEffects = 0
4546 let isCodeGenOnly = 1 in {
4547 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4548 (ins DstVT.RC:$src1, SrcRC:$src2),
4549 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4550 [(set DstVT.RC:$dst,
4551 (OpNode (DstVT.VT DstVT.RC:$src1),
4553 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4555 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4556 (ins DstVT.RC:$src1, x86memop:$src2),
4557 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4558 [(set DstVT.RC:$dst,
4559 (OpNode (DstVT.VT DstVT.RC:$src1),
4560 (ld_frag addr:$src2),
4561 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4562 }//isCodeGenOnly = 1
4565 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4566 X86VectorVTInfo DstVT, string asm> {
4567 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4568 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4570 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4571 [(set DstVT.RC:$dst,
4572 (OpNode (DstVT.VT DstVT.RC:$src1),
4574 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4577 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4578 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4579 PatFrag ld_frag, string asm> {
4580 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4581 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4585 let Predicates = [HasAVX512] in {
4586 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4587 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4588 XS, EVEX_CD8<32, CD8VT1>;
4589 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4590 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4591 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4592 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4593 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4594 XD, EVEX_CD8<32, CD8VT1>;
4595 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4596 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4597 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4599 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4600 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4601 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4602 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4603 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4604 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4605 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4606 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4608 def : Pat<(f32 (sint_to_fp GR32:$src)),
4609 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4610 def : Pat<(f32 (sint_to_fp GR64:$src)),
4611 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4612 def : Pat<(f64 (sint_to_fp GR32:$src)),
4613 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4614 def : Pat<(f64 (sint_to_fp GR64:$src)),
4615 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4617 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4618 v4f32x_info, i32mem, loadi32,
4619 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4620 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4621 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4622 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4623 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4624 i32mem, loadi32, "cvtusi2sd{l}">,
4625 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4626 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4627 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4628 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4630 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4631 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4632 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4633 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4634 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4635 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4636 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4637 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4639 def : Pat<(f32 (uint_to_fp GR32:$src)),
4640 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4641 def : Pat<(f32 (uint_to_fp GR64:$src)),
4642 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4643 def : Pat<(f64 (uint_to_fp GR32:$src)),
4644 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4645 def : Pat<(f64 (uint_to_fp GR64:$src)),
4646 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4649 //===----------------------------------------------------------------------===//
4650 // AVX-512 Scalar convert from float/double to integer
4651 //===----------------------------------------------------------------------===//
4652 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4653 RegisterClass DstRC, Intrinsic Int,
4654 Operand memop, ComplexPattern mem_cpat, string asm> {
4655 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4656 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4657 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4658 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4659 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4660 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4661 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4663 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4664 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4665 } // hasSideEffects = 0, Predicates = [HasAVX512]
4668 // Convert float/double to signed/unsigned int 32/64
4669 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4670 ssmem, sse_load_f32, "cvtss2si">,
4671 XS, EVEX_CD8<32, CD8VT1>;
4672 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4673 int_x86_sse_cvtss2si64,
4674 ssmem, sse_load_f32, "cvtss2si">,
4675 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4676 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4677 int_x86_avx512_cvtss2usi,
4678 ssmem, sse_load_f32, "cvtss2usi">,
4679 XS, EVEX_CD8<32, CD8VT1>;
4680 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4681 int_x86_avx512_cvtss2usi64, ssmem,
4682 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4683 EVEX_CD8<32, CD8VT1>;
4684 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4685 sdmem, sse_load_f64, "cvtsd2si">,
4686 XD, EVEX_CD8<64, CD8VT1>;
4687 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4688 int_x86_sse2_cvtsd2si64,
4689 sdmem, sse_load_f64, "cvtsd2si">,
4690 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4691 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4692 int_x86_avx512_cvtsd2usi,
4693 sdmem, sse_load_f64, "cvtsd2usi">,
4694 XD, EVEX_CD8<64, CD8VT1>;
4695 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4696 int_x86_avx512_cvtsd2usi64, sdmem,
4697 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4698 EVEX_CD8<64, CD8VT1>;
4700 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4701 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4702 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4703 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4704 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4705 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4706 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4707 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4708 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4709 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4710 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4711 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4712 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4714 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4715 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4716 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4717 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4719 // Convert float/double to signed/unsigned int 32/64 with truncation
4720 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4721 X86VectorVTInfo _DstRC, SDNode OpNode,
4723 let Predicates = [HasAVX512] in {
4724 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4725 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4726 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4727 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4728 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4730 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4731 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4732 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4735 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4736 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4737 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4738 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4739 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4740 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4741 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4742 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4743 (i32 FROUND_NO_EXC)))]>,
4744 EVEX,VEX_LIG , EVEX_B;
4746 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4747 (ins _SrcRC.MemOp:$src),
4748 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4751 } // isCodeGenOnly = 1, hasSideEffects = 0
4756 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4757 fp_to_sint,X86cvttss2IntRnd>,
4758 XS, EVEX_CD8<32, CD8VT1>;
4759 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4760 fp_to_sint,X86cvttss2IntRnd>,
4761 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4762 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4763 fp_to_sint,X86cvttsd2IntRnd>,
4764 XD, EVEX_CD8<64, CD8VT1>;
4765 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4766 fp_to_sint,X86cvttsd2IntRnd>,
4767 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4769 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
4770 fp_to_uint,X86cvttss2UIntRnd>,
4771 XS, EVEX_CD8<32, CD8VT1>;
4772 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
4773 fp_to_uint,X86cvttss2UIntRnd>,
4774 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
4775 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
4776 fp_to_uint,X86cvttsd2UIntRnd>,
4777 XD, EVEX_CD8<64, CD8VT1>;
4778 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
4779 fp_to_uint,X86cvttsd2UIntRnd>,
4780 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4781 let Predicates = [HasAVX512] in {
4782 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
4783 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4784 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
4785 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4786 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
4787 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4788 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
4789 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4792 //===----------------------------------------------------------------------===//
4793 // AVX-512 Convert form float to double and back
4794 //===----------------------------------------------------------------------===//
4795 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4796 X86VectorVTInfo _Src, SDNode OpNode> {
4797 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4798 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4799 "$src2, $src1", "$src1, $src2",
4800 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4801 (_Src.VT _Src.RC:$src2)))>,
4802 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4803 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4804 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4805 "$src2, $src1", "$src1, $src2",
4806 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4807 (_Src.VT (scalar_to_vector
4808 (_Src.ScalarLdFrag addr:$src2)))))>,
4809 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
4812 // Scalar Coversion with SAE - suppress all exceptions
4813 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4814 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4815 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4816 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4817 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4818 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4819 (_Src.VT _Src.RC:$src2),
4820 (i32 FROUND_NO_EXC)))>,
4821 EVEX_4V, VEX_LIG, EVEX_B;
4824 // Scalar Conversion with rounding control (RC)
4825 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4826 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4827 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4828 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
4829 "$rc, $src2, $src1", "$src1, $src2, $rc",
4830 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4831 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
4832 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4835 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
4836 SDNode OpNodeRnd, X86VectorVTInfo _src,
4837 X86VectorVTInfo _dst> {
4838 let Predicates = [HasAVX512] in {
4839 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4840 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
4841 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
4846 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4847 SDNode OpNodeRnd, X86VectorVTInfo _src,
4848 X86VectorVTInfo _dst> {
4849 let Predicates = [HasAVX512] in {
4850 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4851 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
4852 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
4855 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
4856 X86froundRnd, f64x_info, f32x_info>;
4857 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
4858 X86fpextRnd,f32x_info, f64x_info >;
4860 def : Pat<(f64 (fextend FR32X:$src)),
4861 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
4862 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
4863 Requires<[HasAVX512]>;
4864 def : Pat<(f64 (fextend (loadf32 addr:$src))),
4865 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4866 Requires<[HasAVX512]>;
4868 def : Pat<(f64 (extloadf32 addr:$src)),
4869 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4870 Requires<[HasAVX512, OptForSize]>;
4872 def : Pat<(f64 (extloadf32 addr:$src)),
4873 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
4874 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
4875 Requires<[HasAVX512, OptForSpeed]>;
4877 def : Pat<(f32 (fround FR64X:$src)),
4878 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
4879 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
4880 Requires<[HasAVX512]>;
4881 //===----------------------------------------------------------------------===//
4882 // AVX-512 Vector convert from signed/unsigned integer to float/double
4883 // and from float/double to signed/unsigned integer
4884 //===----------------------------------------------------------------------===//
4886 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4887 X86VectorVTInfo _Src, SDNode OpNode,
4888 string Broadcast = _.BroadcastStr,
4889 string Alias = ""> {
4891 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4892 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
4893 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
4895 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4896 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
4897 (_.VT (OpNode (_Src.VT
4898 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
4900 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4901 (ins _Src.MemOp:$src), OpcodeStr,
4902 "${src}"##Broadcast, "${src}"##Broadcast,
4903 (_.VT (OpNode (_Src.VT
4904 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
4907 // Coversion with SAE - suppress all exceptions
4908 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4909 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4910 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4911 (ins _Src.RC:$src), OpcodeStr,
4912 "{sae}, $src", "$src, {sae}",
4913 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
4914 (i32 FROUND_NO_EXC)))>,
4918 // Conversion with rounding control (RC)
4919 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4920 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4921 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4922 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
4923 "$rc, $src", "$src, $rc",
4924 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
4925 EVEX, EVEX_B, EVEX_RC;
4928 // Extend Float to Double
4929 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
4930 let Predicates = [HasAVX512] in {
4931 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
4932 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
4933 X86vfpextRnd>, EVEX_V512;
4935 let Predicates = [HasVLX] in {
4936 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
4937 X86vfpext, "{1to2}">, EVEX_V128;
4938 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
4943 // Truncate Double to Float
4944 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
4945 let Predicates = [HasAVX512] in {
4946 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
4947 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
4948 X86vfproundRnd>, EVEX_V512;
4950 let Predicates = [HasVLX] in {
4951 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
4952 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
4953 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
4954 "{1to4}", "{y}">, EVEX_V256;
4958 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
4959 VEX_W, PD, EVEX_CD8<64, CD8VF>;
4960 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
4961 PS, EVEX_CD8<32, CD8VH>;
4963 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4964 (VCVTPS2PDZrm addr:$src)>;
4966 let Predicates = [HasVLX] in {
4967 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
4968 (VCVTPS2PDZ256rm addr:$src)>;
4971 // Convert Signed/Unsigned Doubleword to Double
4972 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4974 // No rounding in this op
4975 let Predicates = [HasAVX512] in
4976 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
4979 let Predicates = [HasVLX] in {
4980 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
4981 OpNode128, "{1to2}">, EVEX_V128;
4982 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
4987 // Convert Signed/Unsigned Doubleword to Float
4988 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
4990 let Predicates = [HasAVX512] in
4991 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
4992 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
4993 OpNodeRnd>, EVEX_V512;
4995 let Predicates = [HasVLX] in {
4996 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
4998 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5003 // Convert Float to Signed/Unsigned Doubleword with truncation
5004 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5005 SDNode OpNode, SDNode OpNodeRnd> {
5006 let Predicates = [HasAVX512] in {
5007 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5008 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5009 OpNodeRnd>, EVEX_V512;
5011 let Predicates = [HasVLX] in {
5012 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5014 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5019 // Convert Float to Signed/Unsigned Doubleword
5020 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5021 SDNode OpNode, SDNode OpNodeRnd> {
5022 let Predicates = [HasAVX512] in {
5023 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5024 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5025 OpNodeRnd>, EVEX_V512;
5027 let Predicates = [HasVLX] in {
5028 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5030 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5035 // Convert Double to Signed/Unsigned Doubleword with truncation
5036 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5037 SDNode OpNode, SDNode OpNodeRnd> {
5038 let Predicates = [HasAVX512] in {
5039 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5040 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5041 OpNodeRnd>, EVEX_V512;
5043 let Predicates = [HasVLX] in {
5044 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5045 // memory forms of these instructions in Asm Parcer. They have the same
5046 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5047 // due to the same reason.
5048 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5049 "{1to2}", "{x}">, EVEX_V128;
5050 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5051 "{1to4}", "{y}">, EVEX_V256;
5055 // Convert Double to Signed/Unsigned Doubleword
5056 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5057 SDNode OpNode, SDNode OpNodeRnd> {
5058 let Predicates = [HasAVX512] in {
5059 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5060 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5061 OpNodeRnd>, EVEX_V512;
5063 let Predicates = [HasVLX] in {
5064 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5065 // memory forms of these instructions in Asm Parcer. They have the same
5066 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5067 // due to the same reason.
5068 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5069 "{1to2}", "{x}">, EVEX_V128;
5070 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5071 "{1to4}", "{y}">, EVEX_V256;
5075 // Convert Double to Signed/Unsigned Quardword
5076 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5077 SDNode OpNode, SDNode OpNodeRnd> {
5078 let Predicates = [HasDQI] in {
5079 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5080 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5081 OpNodeRnd>, EVEX_V512;
5083 let Predicates = [HasDQI, HasVLX] in {
5084 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5086 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5091 // Convert Double to Signed/Unsigned Quardword with truncation
5092 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5093 SDNode OpNode, SDNode OpNodeRnd> {
5094 let Predicates = [HasDQI] in {
5095 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5096 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5097 OpNodeRnd>, EVEX_V512;
5099 let Predicates = [HasDQI, HasVLX] in {
5100 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5102 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5107 // Convert Signed/Unsigned Quardword to Double
5108 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5109 SDNode OpNode, SDNode OpNodeRnd> {
5110 let Predicates = [HasDQI] in {
5111 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5112 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5113 OpNodeRnd>, EVEX_V512;
5115 let Predicates = [HasDQI, HasVLX] in {
5116 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5118 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5123 // Convert Float to Signed/Unsigned Quardword
5124 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5125 SDNode OpNode, SDNode OpNodeRnd> {
5126 let Predicates = [HasDQI] in {
5127 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5128 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5129 OpNodeRnd>, EVEX_V512;
5131 let Predicates = [HasDQI, HasVLX] in {
5132 // Explicitly specified broadcast string, since we take only 2 elements
5133 // from v4f32x_info source
5134 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5135 "{1to2}">, EVEX_V128;
5136 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5141 // Convert Float to Signed/Unsigned Quardword with truncation
5142 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5143 SDNode OpNode, SDNode OpNodeRnd> {
5144 let Predicates = [HasDQI] in {
5145 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5146 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5147 OpNodeRnd>, EVEX_V512;
5149 let Predicates = [HasDQI, HasVLX] in {
5150 // Explicitly specified broadcast string, since we take only 2 elements
5151 // from v4f32x_info source
5152 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5153 "{1to2}">, EVEX_V128;
5154 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5159 // Convert Signed/Unsigned Quardword to Float
5160 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5161 SDNode OpNode, SDNode OpNodeRnd> {
5162 let Predicates = [HasDQI] in {
5163 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5164 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5165 OpNodeRnd>, EVEX_V512;
5167 let Predicates = [HasDQI, HasVLX] in {
5168 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5169 // memory forms of these instructions in Asm Parcer. They have the same
5170 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5171 // due to the same reason.
5172 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5173 "{1to2}", "{x}">, EVEX_V128;
5174 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5175 "{1to4}", "{y}">, EVEX_V256;
5179 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5180 EVEX_CD8<32, CD8VH>;
5182 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5184 PS, EVEX_CD8<32, CD8VF>;
5186 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5188 XS, EVEX_CD8<32, CD8VF>;
5190 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5192 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5194 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5195 X86VFpToUintRnd>, PS,
5196 EVEX_CD8<32, CD8VF>;
5198 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5199 X86VFpToUintRnd>, PS, VEX_W,
5200 EVEX_CD8<64, CD8VF>;
5202 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5203 XS, EVEX_CD8<32, CD8VH>;
5205 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5206 X86VUintToFpRnd>, XD,
5207 EVEX_CD8<32, CD8VF>;
5209 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5210 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5212 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5213 X86cvtpd2IntRnd>, XD, VEX_W,
5214 EVEX_CD8<64, CD8VF>;
5216 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5218 PS, EVEX_CD8<32, CD8VF>;
5219 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5220 X86cvtpd2UIntRnd>, VEX_W,
5221 PS, EVEX_CD8<64, CD8VF>;
5223 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5224 X86cvtpd2IntRnd>, VEX_W,
5225 PD, EVEX_CD8<64, CD8VF>;
5227 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5228 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5230 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5231 X86cvtpd2UIntRnd>, VEX_W,
5232 PD, EVEX_CD8<64, CD8VF>;
5234 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5235 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5237 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5238 X86VFpToSlongRnd>, VEX_W,
5239 PD, EVEX_CD8<64, CD8VF>;
5241 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5242 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5244 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5245 X86VFpToUlongRnd>, VEX_W,
5246 PD, EVEX_CD8<64, CD8VF>;
5248 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5249 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5251 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5252 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5254 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5255 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5257 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5258 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5260 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5261 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5263 let Predicates = [NoVLX] in {
5264 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5265 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5266 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5268 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5269 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5270 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5272 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5273 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5274 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5276 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5277 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5278 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5280 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5281 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5282 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5285 let Predicates = [HasAVX512] in {
5286 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5287 (VCVTPD2PSZrm addr:$src)>;
5288 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5289 (VCVTPS2PDZrm addr:$src)>;
5292 //===----------------------------------------------------------------------===//
5293 // Half precision conversion instructions
5294 //===----------------------------------------------------------------------===//
5295 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
5296 X86MemOperand x86memop> {
5297 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
5298 "vcvtph2ps\t{$src, $dst|$dst, $src}",
5300 let hasSideEffects = 0, mayLoad = 1 in
5301 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
5302 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
5305 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
5306 X86MemOperand x86memop> {
5307 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
5308 (ins srcRC:$src1, i32u8imm:$src2),
5309 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5311 let hasSideEffects = 0, mayStore = 1 in
5312 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5313 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
5314 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
5317 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
5318 EVEX_CD8<32, CD8VH>;
5319 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
5320 EVEX_CD8<32, CD8VH>;
5322 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
5323 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
5324 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
5326 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
5327 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
5328 (VCVTPH2PSZrr VR256X:$src)>;
5330 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5331 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5332 "ucomiss">, PS, EVEX, VEX_LIG,
5333 EVEX_CD8<32, CD8VT1>;
5334 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5335 "ucomisd">, PD, EVEX,
5336 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5337 let Pattern = []<dag> in {
5338 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5339 "comiss">, PS, EVEX, VEX_LIG,
5340 EVEX_CD8<32, CD8VT1>;
5341 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5342 "comisd">, PD, EVEX,
5343 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5345 let isCodeGenOnly = 1 in {
5346 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5347 load, "ucomiss">, PS, EVEX, VEX_LIG,
5348 EVEX_CD8<32, CD8VT1>;
5349 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5350 load, "ucomisd">, PD, EVEX,
5351 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5353 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5354 load, "comiss">, PS, EVEX, VEX_LIG,
5355 EVEX_CD8<32, CD8VT1>;
5356 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5357 load, "comisd">, PD, EVEX,
5358 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5362 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5363 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
5364 X86MemOperand x86memop> {
5365 let hasSideEffects = 0 in {
5366 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5367 (ins RC:$src1, RC:$src2),
5368 !strconcat(OpcodeStr,
5369 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
5370 let mayLoad = 1 in {
5371 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5372 (ins RC:$src1, x86memop:$src2),
5373 !strconcat(OpcodeStr,
5374 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
5379 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
5380 EVEX_CD8<32, CD8VT1>;
5381 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
5382 VEX_W, EVEX_CD8<64, CD8VT1>;
5383 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
5384 EVEX_CD8<32, CD8VT1>;
5385 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
5386 VEX_W, EVEX_CD8<64, CD8VT1>;
5388 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
5389 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
5390 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
5391 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
5393 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
5394 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
5395 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
5396 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
5398 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
5399 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
5400 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
5401 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
5403 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
5404 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
5405 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
5406 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
5408 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5409 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5410 X86VectorVTInfo _> {
5411 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5412 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5413 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5414 let mayLoad = 1 in {
5415 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5416 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5418 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5419 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5420 (ins _.ScalarMemOp:$src), OpcodeStr,
5421 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5423 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5428 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5429 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5430 EVEX_V512, EVEX_CD8<32, CD8VF>;
5431 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5432 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5434 // Define only if AVX512VL feature is present.
5435 let Predicates = [HasVLX] in {
5436 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5437 OpNode, v4f32x_info>,
5438 EVEX_V128, EVEX_CD8<32, CD8VF>;
5439 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5440 OpNode, v8f32x_info>,
5441 EVEX_V256, EVEX_CD8<32, CD8VF>;
5442 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5443 OpNode, v2f64x_info>,
5444 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5445 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5446 OpNode, v4f64x_info>,
5447 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5451 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5452 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5454 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5455 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5456 (VRSQRT14PSZr VR512:$src)>;
5457 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5458 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5459 (VRSQRT14PDZr VR512:$src)>;
5461 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5462 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5463 (VRCP14PSZr VR512:$src)>;
5464 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5465 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5466 (VRCP14PDZr VR512:$src)>;
5468 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5469 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5472 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5473 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5474 "$src2, $src1", "$src1, $src2",
5475 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5476 (i32 FROUND_CURRENT))>;
5478 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5479 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5480 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5481 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5482 (i32 FROUND_NO_EXC))>, EVEX_B;
5484 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5485 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5486 "$src2, $src1", "$src1, $src2",
5487 (OpNode (_.VT _.RC:$src1),
5488 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5489 (i32 FROUND_CURRENT))>;
5492 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5493 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5494 EVEX_CD8<32, CD8VT1>;
5495 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5496 EVEX_CD8<64, CD8VT1>, VEX_W;
5499 let hasSideEffects = 0, Predicates = [HasERI] in {
5500 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5501 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5504 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5505 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5507 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5510 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5511 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5512 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5514 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5515 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5517 (bitconvert (_.LdFrag addr:$src))),
5518 (i32 FROUND_CURRENT))>;
5520 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5521 (ins _.MemOp:$src), OpcodeStr,
5522 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5524 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5525 (i32 FROUND_CURRENT))>, EVEX_B;
5527 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5529 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5530 (ins _.RC:$src), OpcodeStr,
5531 "{sae}, $src", "$src, {sae}",
5532 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5535 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5536 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5537 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5538 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5539 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5540 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5541 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5544 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5546 // Define only if AVX512VL feature is present.
5547 let Predicates = [HasVLX] in {
5548 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5549 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5550 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5551 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5552 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5553 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5554 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5555 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5558 let Predicates = [HasERI], hasSideEffects = 0 in {
5560 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5561 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5562 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5564 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5565 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5567 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5568 SDNode OpNodeRnd, X86VectorVTInfo _>{
5569 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5570 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5571 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5572 EVEX, EVEX_B, EVEX_RC;
5575 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5576 SDNode OpNode, X86VectorVTInfo _>{
5577 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5578 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5579 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5580 let mayLoad = 1 in {
5581 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5582 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5584 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5586 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5587 (ins _.ScalarMemOp:$src), OpcodeStr,
5588 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5590 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5595 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5597 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5599 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5600 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5602 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5603 // Define only if AVX512VL feature is present.
5604 let Predicates = [HasVLX] in {
5605 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5606 OpNode, v4f32x_info>,
5607 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5608 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5609 OpNode, v8f32x_info>,
5610 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5611 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5612 OpNode, v2f64x_info>,
5613 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5614 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5615 OpNode, v4f64x_info>,
5616 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5620 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5622 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5623 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5624 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5625 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5628 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5629 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5631 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5632 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5633 "$src2, $src1", "$src1, $src2",
5634 (OpNodeRnd (_.VT _.RC:$src1),
5636 (i32 FROUND_CURRENT))>;
5638 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5639 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5640 "$src2, $src1", "$src1, $src2",
5641 (OpNodeRnd (_.VT _.RC:$src1),
5642 (_.VT (scalar_to_vector
5643 (_.ScalarLdFrag addr:$src2))),
5644 (i32 FROUND_CURRENT))>;
5646 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5647 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5648 "$rc, $src2, $src1", "$src1, $src2, $rc",
5649 (OpNodeRnd (_.VT _.RC:$src1),
5654 let isCodeGenOnly = 1 in {
5655 def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst),
5656 (ins _.FRC:$src1, _.FRC:$src2),
5657 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5660 def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst),
5661 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5662 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5665 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5666 (!cast<Instruction>(NAME#SUFF#Zr)
5667 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5669 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5670 (!cast<Instruction>(NAME#SUFF#Zm)
5671 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5674 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5675 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5676 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5677 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5678 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5681 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5682 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5684 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5686 let Predicates = [HasAVX512] in {
5687 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5688 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5689 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5690 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5691 Requires<[OptForSize]>;
5693 def : Pat<(f32 (X86frcp FR32X:$src)),
5694 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5695 def : Pat<(f32 (X86frcp (load addr:$src))),
5696 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5697 Requires<[OptForSize]>;
5701 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5703 let ExeDomain = _.ExeDomain in {
5704 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5705 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5706 "$src3, $src2, $src1", "$src1, $src2, $src3",
5707 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5708 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5710 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5711 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5712 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5713 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5714 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5717 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5718 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5719 "$src3, $src2, $src1", "$src1, $src2, $src3",
5720 (_.VT (X86RndScales (_.VT _.RC:$src1),
5721 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5722 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5724 let Predicates = [HasAVX512] in {
5725 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5726 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5727 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5728 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5729 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5730 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5731 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5732 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5733 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5734 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5735 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5736 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5737 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5738 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5739 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5741 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5742 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5743 addr:$src, (i32 0x1))), _.FRC)>;
5744 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5745 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5746 addr:$src, (i32 0x2))), _.FRC)>;
5747 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5748 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5749 addr:$src, (i32 0x3))), _.FRC)>;
5750 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5751 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5752 addr:$src, (i32 0x4))), _.FRC)>;
5753 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5754 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5755 addr:$src, (i32 0xc))), _.FRC)>;
5759 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5760 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5762 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5763 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5765 //-------------------------------------------------
5766 // Integer truncate and extend operations
5767 //-------------------------------------------------
5769 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5770 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5771 X86MemOperand x86memop> {
5773 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5774 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5775 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5778 // for intrinsic patter match
5779 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5780 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5782 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5785 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5786 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5787 DestInfo.ImmAllZerosV)),
5788 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5791 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5792 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5793 DestInfo.RC:$src0)),
5794 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5795 DestInfo.KRCWM:$mask ,
5798 let mayStore = 1 in {
5799 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5800 (ins x86memop:$dst, SrcInfo.RC:$src),
5801 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5804 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5805 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5806 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5811 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5812 X86VectorVTInfo DestInfo,
5813 PatFrag truncFrag, PatFrag mtruncFrag > {
5815 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5816 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5817 addr:$dst, SrcInfo.RC:$src)>;
5819 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5820 (SrcInfo.VT SrcInfo.RC:$src)),
5821 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5822 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
5825 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
5826 X86VectorVTInfo DestInfo, string sat > {
5828 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5829 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5830 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
5831 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
5832 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
5833 (SrcInfo.VT SrcInfo.RC:$src))>;
5835 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5836 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5837 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
5838 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
5839 (SrcInfo.VT SrcInfo.RC:$src))>;
5842 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
5843 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5844 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5845 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5846 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
5847 Predicate prd = HasAVX512>{
5849 let Predicates = [HasVLX, prd] in {
5850 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5851 DestInfoZ128, x86memopZ128>,
5852 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5853 truncFrag, mtruncFrag>, EVEX_V128;
5855 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5856 DestInfoZ256, x86memopZ256>,
5857 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5858 truncFrag, mtruncFrag>, EVEX_V256;
5860 let Predicates = [prd] in
5861 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5862 DestInfoZ, x86memopZ>,
5863 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5864 truncFrag, mtruncFrag>, EVEX_V512;
5867 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
5868 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5869 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5870 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5871 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
5873 let Predicates = [HasVLX, prd] in {
5874 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5875 DestInfoZ128, x86memopZ128>,
5876 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5879 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5880 DestInfoZ256, x86memopZ256>,
5881 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5884 let Predicates = [prd] in
5885 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5886 DestInfoZ, x86memopZ>,
5887 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5891 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5892 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5893 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5894 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
5896 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
5897 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
5898 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5899 sat>, EVEX_CD8<8, CD8VO>;
5902 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5903 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5904 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5905 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
5907 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
5908 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
5909 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5910 sat>, EVEX_CD8<16, CD8VQ>;
5913 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5914 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5915 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5916 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
5918 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
5919 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
5920 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5921 sat>, EVEX_CD8<32, CD8VH>;
5924 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5925 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5926 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5927 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
5929 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
5930 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
5931 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5932 sat>, EVEX_CD8<8, CD8VQ>;
5935 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5936 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5937 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5938 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
5940 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
5941 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
5942 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5943 sat>, EVEX_CD8<16, CD8VH>;
5946 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5947 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
5948 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5949 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
5951 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
5952 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
5953 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5954 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
5957 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
5958 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
5959 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
5961 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
5962 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
5963 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
5965 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
5966 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
5967 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
5969 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
5970 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
5971 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
5973 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
5974 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
5975 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
5977 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
5978 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
5979 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
5981 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
5982 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
5983 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
5985 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
5986 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
5987 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
5990 let mayLoad = 1 in {
5991 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
5992 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
5993 (DestInfo.VT (LdFrag addr:$src))>,
5998 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
5999 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6000 let Predicates = [HasVLX, HasBWI] in {
6001 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6002 v16i8x_info, i64mem, LdFrag, OpNode>,
6003 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6005 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6006 v16i8x_info, i128mem, LdFrag, OpNode>,
6007 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6009 let Predicates = [HasBWI] in {
6010 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6011 v32i8x_info, i256mem, LdFrag, OpNode>,
6012 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6016 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6017 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6018 let Predicates = [HasVLX, HasAVX512] in {
6019 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6020 v16i8x_info, i32mem, LdFrag, OpNode>,
6021 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6023 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6024 v16i8x_info, i64mem, LdFrag, OpNode>,
6025 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6027 let Predicates = [HasAVX512] in {
6028 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6029 v16i8x_info, i128mem, LdFrag, OpNode>,
6030 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6034 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6035 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6036 let Predicates = [HasVLX, HasAVX512] in {
6037 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6038 v16i8x_info, i16mem, LdFrag, OpNode>,
6039 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6041 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6042 v16i8x_info, i32mem, LdFrag, OpNode>,
6043 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6045 let Predicates = [HasAVX512] in {
6046 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6047 v16i8x_info, i64mem, LdFrag, OpNode>,
6048 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6052 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6053 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6054 let Predicates = [HasVLX, HasAVX512] in {
6055 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6056 v8i16x_info, i64mem, LdFrag, OpNode>,
6057 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6059 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6060 v8i16x_info, i128mem, LdFrag, OpNode>,
6061 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6063 let Predicates = [HasAVX512] in {
6064 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6065 v16i16x_info, i256mem, LdFrag, OpNode>,
6066 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6070 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6071 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6072 let Predicates = [HasVLX, HasAVX512] in {
6073 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6074 v8i16x_info, i32mem, LdFrag, OpNode>,
6075 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6077 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6078 v8i16x_info, i64mem, LdFrag, OpNode>,
6079 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6081 let Predicates = [HasAVX512] in {
6082 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6083 v8i16x_info, i128mem, LdFrag, OpNode>,
6084 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6088 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6089 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6091 let Predicates = [HasVLX, HasAVX512] in {
6092 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6093 v4i32x_info, i64mem, LdFrag, OpNode>,
6094 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6096 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6097 v4i32x_info, i128mem, LdFrag, OpNode>,
6098 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6100 let Predicates = [HasAVX512] in {
6101 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6102 v8i32x_info, i256mem, LdFrag, OpNode>,
6103 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6107 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6108 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6109 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6110 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6111 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6112 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6115 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6116 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6117 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6118 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6119 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6120 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6122 //===----------------------------------------------------------------------===//
6123 // GATHER - SCATTER Operations
6125 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6126 X86MemOperand memop, PatFrag GatherNode> {
6127 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6128 ExeDomain = _.ExeDomain in
6129 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6130 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6131 !strconcat(OpcodeStr#_.Suffix,
6132 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6133 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6134 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6135 vectoraddr:$src2))]>, EVEX, EVEX_K,
6136 EVEX_CD8<_.EltSize, CD8VT1>;
6139 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6140 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6141 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6142 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6143 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6144 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6145 let Predicates = [HasVLX] in {
6146 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6147 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6148 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6149 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6150 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6151 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6152 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6153 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6157 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6158 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6159 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6160 mgatherv16i32>, EVEX_V512;
6161 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6162 mgatherv8i64>, EVEX_V512;
6163 let Predicates = [HasVLX] in {
6164 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6165 vy32xmem, mgatherv8i32>, EVEX_V256;
6166 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6167 vy64xmem, mgatherv4i64>, EVEX_V256;
6168 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6169 vx32xmem, mgatherv4i32>, EVEX_V128;
6170 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6171 vx64xmem, mgatherv2i64>, EVEX_V128;
6176 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6177 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6179 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6180 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6182 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6183 X86MemOperand memop, PatFrag ScatterNode> {
6185 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6187 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6188 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6189 !strconcat(OpcodeStr#_.Suffix,
6190 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6191 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6192 _.KRCWM:$mask, vectoraddr:$dst))]>,
6193 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6196 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6197 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6198 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6199 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6200 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6201 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6202 let Predicates = [HasVLX] in {
6203 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6204 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6205 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6206 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6207 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6208 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6209 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6210 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6214 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6215 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6216 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6217 mscatterv16i32>, EVEX_V512;
6218 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6219 mscatterv8i64>, EVEX_V512;
6220 let Predicates = [HasVLX] in {
6221 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6222 vy32xmem, mscatterv8i32>, EVEX_V256;
6223 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6224 vy64xmem, mscatterv4i64>, EVEX_V256;
6225 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6226 vx32xmem, mscatterv4i32>, EVEX_V128;
6227 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6228 vx64xmem, mscatterv2i64>, EVEX_V128;
6232 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6233 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6235 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6236 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6239 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6240 RegisterClass KRC, X86MemOperand memop> {
6241 let Predicates = [HasPFI], hasSideEffects = 1 in
6242 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6243 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6247 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6248 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6250 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6251 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6253 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6254 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6256 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6257 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6259 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6260 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6262 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6263 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6265 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6266 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6268 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6269 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6271 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6272 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6274 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6275 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6277 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6278 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6280 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6281 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6283 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6284 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6286 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6287 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6289 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6290 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6292 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6293 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6295 // Helper fragments to match sext vXi1 to vXiY.
6296 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6297 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6299 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6300 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6301 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6303 def : Pat<(store VK1:$src, addr:$dst),
6305 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6306 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6308 def : Pat<(store VK8:$src, addr:$dst),
6310 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6311 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6313 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6314 (truncstore node:$val, node:$ptr), [{
6315 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6318 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6319 (MOV8mr addr:$dst, GR8:$src)>;
6321 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6322 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6323 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6324 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6327 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6328 string OpcodeStr, Predicate prd> {
6329 let Predicates = [prd] in
6330 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6332 let Predicates = [prd, HasVLX] in {
6333 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6334 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6338 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6339 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6341 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6343 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6345 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6349 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6351 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6352 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6353 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6354 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6357 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6358 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6359 let Predicates = [prd] in
6360 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6363 let Predicates = [prd, HasVLX] in {
6364 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6366 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6371 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6372 avx512vl_i8_info, HasBWI>;
6373 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6374 avx512vl_i16_info, HasBWI>, VEX_W;
6375 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6376 avx512vl_i32_info, HasDQI>;
6377 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6378 avx512vl_i64_info, HasDQI>, VEX_W;
6380 //===----------------------------------------------------------------------===//
6381 // AVX-512 - COMPRESS and EXPAND
6384 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6386 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6387 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6388 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6390 let mayStore = 1 in {
6391 def mr : AVX5128I<opc, MRMDestMem, (outs),
6392 (ins _.MemOp:$dst, _.RC:$src),
6393 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6394 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6396 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6397 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6398 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6399 [(store (_.VT (vselect _.KRCWM:$mask,
6400 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6402 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6406 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6407 AVX512VLVectorVTInfo VTInfo> {
6408 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6410 let Predicates = [HasVLX] in {
6411 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6412 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6416 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6418 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6420 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6422 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6426 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6428 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6429 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6430 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6433 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6434 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6435 (_.VT (X86expand (_.VT (bitconvert
6436 (_.LdFrag addr:$src1)))))>,
6437 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6440 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6441 AVX512VLVectorVTInfo VTInfo> {
6442 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6444 let Predicates = [HasVLX] in {
6445 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6446 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6450 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6452 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6454 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6456 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6459 //handle instruction reg_vec1 = op(reg_vec,imm)
6461 // op(broadcast(eltVt),imm)
6462 //all instruction created with FROUND_CURRENT
6463 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6465 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6466 (ins _.RC:$src1, i32u8imm:$src2),
6467 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6468 (OpNode (_.VT _.RC:$src1),
6470 (i32 FROUND_CURRENT))>;
6471 let mayLoad = 1 in {
6472 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6473 (ins _.MemOp:$src1, i32u8imm:$src2),
6474 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6475 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6477 (i32 FROUND_CURRENT))>;
6478 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6479 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6480 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6481 "${src1}"##_.BroadcastStr##", $src2",
6482 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6484 (i32 FROUND_CURRENT))>, EVEX_B;
6488 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6489 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6490 SDNode OpNode, X86VectorVTInfo _>{
6491 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6492 (ins _.RC:$src1, i32u8imm:$src2),
6493 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6494 "$src1, {sae}, $src2",
6495 (OpNode (_.VT _.RC:$src1),
6497 (i32 FROUND_NO_EXC))>, EVEX_B;
6500 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6501 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6502 let Predicates = [prd] in {
6503 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6504 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6507 let Predicates = [prd, HasVLX] in {
6508 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6510 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6515 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6516 // op(reg_vec2,mem_vec,imm)
6517 // op(reg_vec2,broadcast(eltVt),imm)
6518 //all instruction created with FROUND_CURRENT
6519 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6521 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6522 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6523 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6524 (OpNode (_.VT _.RC:$src1),
6527 (i32 FROUND_CURRENT))>;
6528 let mayLoad = 1 in {
6529 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6530 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6531 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6532 (OpNode (_.VT _.RC:$src1),
6533 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6535 (i32 FROUND_CURRENT))>;
6536 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6537 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6538 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6539 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6540 (OpNode (_.VT _.RC:$src1),
6541 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6543 (i32 FROUND_CURRENT))>, EVEX_B;
6547 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6548 // op(reg_vec2,mem_vec,imm)
6549 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6550 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6552 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6553 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6554 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6555 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6556 (SrcInfo.VT SrcInfo.RC:$src2),
6559 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6560 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6561 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6562 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6563 (SrcInfo.VT (bitconvert
6564 (SrcInfo.LdFrag addr:$src2))),
6568 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6569 // op(reg_vec2,mem_vec,imm)
6570 // op(reg_vec2,broadcast(eltVt),imm)
6571 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6573 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6576 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6577 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6578 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6579 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6580 (OpNode (_.VT _.RC:$src1),
6581 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6582 (i8 imm:$src3))>, EVEX_B;
6585 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6586 // op(reg_vec2,mem_scalar,imm)
6587 //all instruction created with FROUND_CURRENT
6588 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6589 X86VectorVTInfo _> {
6591 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6592 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6593 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6594 (OpNode (_.VT _.RC:$src1),
6597 (i32 FROUND_CURRENT))>;
6598 let mayLoad = 1 in {
6599 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6600 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6601 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6602 (OpNode (_.VT _.RC:$src1),
6603 (_.VT (scalar_to_vector
6604 (_.ScalarLdFrag addr:$src2))),
6606 (i32 FROUND_CURRENT))>;
6608 let isAsmParserOnly = 1 in {
6609 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6610 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6611 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6617 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6618 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6619 SDNode OpNode, X86VectorVTInfo _>{
6620 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6621 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6622 OpcodeStr, "$src3,{sae}, $src2, $src1",
6623 "$src1, $src2,{sae}, $src3",
6624 (OpNode (_.VT _.RC:$src1),
6627 (i32 FROUND_NO_EXC))>, EVEX_B;
6629 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6630 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6631 SDNode OpNode, X86VectorVTInfo _> {
6632 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6633 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6634 OpcodeStr, "$src3,{sae}, $src2, $src1",
6635 "$src1, $src2,{sae}, $src3",
6636 (OpNode (_.VT _.RC:$src1),
6639 (i32 FROUND_NO_EXC))>, EVEX_B;
6642 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6643 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6644 let Predicates = [prd] in {
6645 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6646 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6650 let Predicates = [prd, HasVLX] in {
6651 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6653 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6658 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6659 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6660 let Predicates = [HasBWI] in {
6661 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6662 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6664 let Predicates = [HasBWI, HasVLX] in {
6665 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6666 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6667 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6668 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6672 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6673 bits<8> opc, SDNode OpNode>{
6674 let Predicates = [HasAVX512] in {
6675 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6677 let Predicates = [HasAVX512, HasVLX] in {
6678 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6679 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6683 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6684 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6685 let Predicates = [prd] in {
6686 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6687 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6691 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6692 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6693 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6694 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6695 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6696 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6699 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6700 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6701 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6702 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6703 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6704 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6706 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6707 0x55, X86VFixupimm, HasAVX512>,
6708 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6709 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6710 0x55, X86VFixupimm, HasAVX512>,
6711 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6713 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6714 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6715 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6716 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6717 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6718 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6721 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6722 0x50, X86VRange, HasDQI>,
6723 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6724 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6725 0x50, X86VRange, HasDQI>,
6726 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6728 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6729 0x51, X86VRange, HasDQI>,
6730 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6731 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6732 0x51, X86VRange, HasDQI>,
6733 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6735 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6736 0x57, X86Reduces, HasDQI>,
6737 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6738 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6739 0x57, X86Reduces, HasDQI>,
6740 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6742 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
6743 0x27, X86GetMants, HasAVX512>,
6744 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6745 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
6746 0x27, X86GetMants, HasAVX512>,
6747 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6749 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6750 bits<8> opc, SDNode OpNode = X86Shuf128>{
6751 let Predicates = [HasAVX512] in {
6752 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6755 let Predicates = [HasAVX512, HasVLX] in {
6756 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6759 let Predicates = [HasAVX512] in {
6760 def : Pat<(v16f32 (ffloor VR512:$src)),
6761 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6762 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6763 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6764 def : Pat<(v16f32 (fceil VR512:$src)),
6765 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6766 def : Pat<(v16f32 (frint VR512:$src)),
6767 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6768 def : Pat<(v16f32 (ftrunc VR512:$src)),
6769 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6771 def : Pat<(v8f64 (ffloor VR512:$src)),
6772 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6773 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6774 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6775 def : Pat<(v8f64 (fceil VR512:$src)),
6776 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6777 def : Pat<(v8f64 (frint VR512:$src)),
6778 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6779 def : Pat<(v8f64 (ftrunc VR512:$src)),
6780 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6783 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6784 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6785 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6786 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6787 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6788 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6789 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6790 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6792 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6793 AVX512VLVectorVTInfo VTInfo_FP>{
6794 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6795 AVX512AIi8Base, EVEX_4V;
6796 let isCodeGenOnly = 1 in {
6797 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6798 AVX512AIi8Base, EVEX_4V;
6802 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6803 EVEX_CD8<32, CD8VF>;
6804 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6805 EVEX_CD8<64, CD8VF>, VEX_W;
6807 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
6808 let Predicates = p in
6809 def NAME#_.VTName#rri:
6810 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
6811 (!cast<Instruction>(NAME#_.ZSuffix#rri)
6812 _.RC:$src1, _.RC:$src2, imm:$imm)>;
6815 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
6816 avx512_vpalign_lowering<_.info512, [HasBWI]>,
6817 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
6818 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
6820 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
6821 avx512vl_i8_info, avx512vl_i8_info>,
6822 avx512_vpalign_lowering_common<avx512vl_i16_info>,
6823 avx512_vpalign_lowering_common<avx512vl_i32_info>,
6824 avx512_vpalign_lowering_common<avx512vl_f32_info>,
6825 avx512_vpalign_lowering_common<avx512vl_i64_info>,
6826 avx512_vpalign_lowering_common<avx512vl_f64_info>,
6829 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
6830 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
6832 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6833 X86VectorVTInfo _> {
6834 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6835 (ins _.RC:$src1), OpcodeStr##_.Suffix,
6837 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
6840 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6841 (ins _.MemOp:$src1), OpcodeStr##_.Suffix,
6843 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
6844 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
6847 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
6848 X86VectorVTInfo _> :
6849 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
6851 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6852 (ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
6853 "${src1}"##_.BroadcastStr,
6854 "${src1}"##_.BroadcastStr,
6855 (_.VT (OpNode (X86VBroadcast
6856 (_.ScalarLdFrag addr:$src1))))>,
6857 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
6860 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6861 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6862 let Predicates = [prd] in
6863 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
6865 let Predicates = [prd, HasVLX] in {
6866 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
6868 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
6873 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6874 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6875 let Predicates = [prd] in
6876 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
6879 let Predicates = [prd, HasVLX] in {
6880 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
6882 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
6887 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
6888 SDNode OpNode, Predicate prd> {
6889 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
6891 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
6894 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
6895 SDNode OpNode, Predicate prd> {
6896 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
6897 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
6900 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
6901 bits<8> opc_d, bits<8> opc_q,
6902 string OpcodeStr, SDNode OpNode> {
6903 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
6905 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
6909 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
6912 (bc_v16i32 (v16i1sextv16i32)),
6913 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
6914 (VPABSDZrr VR512:$src)>;
6916 (bc_v8i64 (v8i1sextv8i64)),
6917 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
6918 (VPABSQZrr VR512:$src)>;
6920 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
6922 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
6923 let isCodeGenOnly = 1 in
6924 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
6925 ctlz_zero_undef, prd>;
6928 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
6929 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
6931 //===----------------------------------------------------------------------===//
6932 // AVX-512 - Unpack Instructions
6933 //===----------------------------------------------------------------------===//
6934 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
6935 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
6937 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
6938 SSE_INTALU_ITINS_P, HasBWI>;
6939 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
6940 SSE_INTALU_ITINS_P, HasBWI>;
6941 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
6942 SSE_INTALU_ITINS_P, HasBWI>;
6943 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
6944 SSE_INTALU_ITINS_P, HasBWI>;
6946 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
6947 SSE_INTALU_ITINS_P, HasAVX512>;
6948 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
6949 SSE_INTALU_ITINS_P, HasAVX512>;
6950 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
6951 SSE_INTALU_ITINS_P, HasAVX512>;
6952 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
6953 SSE_INTALU_ITINS_P, HasAVX512>;
6954 //===----------------------------------------------------------------------===//
6955 // VSHUFPS - VSHUFPD Operations
6956 //===----------------------------------------------------------------------===//
6957 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6958 AVX512VLVectorVTInfo VTInfo_FP>{
6959 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
6960 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
6961 AVX512AIi8Base, EVEX_4V;
6962 let isCodeGenOnly = 1 in {
6963 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
6964 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
6965 AVX512AIi8Base, EVEX_4V;
6969 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
6970 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
6971 //===----------------------------------------------------------------------===//
6972 // AVX-512 - Byte shift Left/Right
6973 //===----------------------------------------------------------------------===//
6975 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
6976 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
6977 def rr : AVX512<opc, MRMr,
6978 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
6979 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6980 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
6982 def rm : AVX512<opc, MRMm,
6983 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
6984 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6985 [(set _.RC:$dst,(_.VT (OpNode
6986 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
6989 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
6990 Format MRMm, string OpcodeStr, Predicate prd>{
6991 let Predicates = [prd] in
6992 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
6993 OpcodeStr, v8i64_info>, EVEX_V512;
6994 let Predicates = [prd, HasVLX] in {
6995 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
6996 OpcodeStr, v4i64x_info>, EVEX_V256;
6997 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
6998 OpcodeStr, v2i64x_info>, EVEX_V128;
7001 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7002 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7003 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7004 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7007 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7008 string OpcodeStr, X86VectorVTInfo _src>{
7009 def rr : AVX512BI<opc, MRMSrcReg,
7010 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7012 [(set _src.RC:$dst,(_src.VT
7013 (OpNode _src.RC:$src1, _src.RC:$src2)))]>;
7015 def rm : AVX512BI<opc, MRMSrcMem,
7016 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7017 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7018 [(set _src.RC:$dst,(_src.VT
7019 (OpNode _src.RC:$src1,
7020 (_src.VT (bitconvert
7021 (_src.LdFrag addr:$src2))))))]>;
7024 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7025 string OpcodeStr, Predicate prd> {
7026 let Predicates = [prd] in
7027 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v64i8_info>,
7029 let Predicates = [prd, HasVLX] in {
7030 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v32i8x_info>,
7032 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v16i8x_info>,
7037 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",