1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
26 string VTName = "v" # NumElts # EltVT;
29 ValueType VT = !cast<ValueType>(VTName);
31 string EltTypeName = !cast<string>(EltVT);
32 // Size of the element type in bits, e.g. 32 for v16i32.
33 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
34 int EltSize = EltVT.Size;
36 // "i" for integer types and "f" for floating-point types
37 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
39 // Size of RC in bits, e.g. 512 for VR512.
42 // The corresponding memory operand, e.g. i512mem for VR512.
43 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
44 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
47 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
48 // due to load promotion during legalization
49 PatFrag LdFrag = !cast<PatFrag>("load" #
50 !if (!eq (TypeVariantName, "i"),
51 !if (!eq (Size, 128), "v2i64",
52 !if (!eq (Size, 256), "v4i64",
54 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
56 // Load patterns used for memory operands. We only have this defined in
57 // case of i64 element types for sub-512 integer vectors. For now, keep
58 // MemOpFrag undefined in these cases.
60 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
62 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
64 // The corresponding float type, e.g. v16f32 for v16i32
65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
89 // A vector type of the same width with element type i32. This is used to
90 // create the canonical constant zero node ImmAllZerosV.
91 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
92 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
95 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
96 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
97 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
98 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
99 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
100 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
102 // "x" in v32i8x_info means RC = VR256X
103 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
104 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
105 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
106 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
107 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
108 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
110 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
111 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
112 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
113 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
114 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
115 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
117 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
118 X86VectorVTInfo i128> {
119 X86VectorVTInfo info512 = i512;
120 X86VectorVTInfo info256 = i256;
121 X86VectorVTInfo info128 = i128;
124 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
126 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
128 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
130 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
132 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
134 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
137 // This multiclass generates the masking variants from the non-masking
138 // variant. It only provides the assembly pieces for the masking variants.
139 // It assumes custom ISel patterns for masking which can be provided as
140 // template arguments.
141 multiclass AVX512_maskable_custom<bits<8> O, Format F,
143 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
145 string AttSrcAsm, string IntelSrcAsm,
147 list<dag> MaskingPattern,
148 list<dag> ZeroMaskingPattern,
150 string MaskingConstraint = "",
151 InstrItinClass itin = NoItinerary,
152 bit IsCommutable = 0> {
153 let isCommutable = IsCommutable in
154 def NAME: AVX512<O, F, Outs, Ins,
155 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
156 "$dst "#Round#", "#IntelSrcAsm#"}",
159 // Prefer over VMOV*rrk Pat<>
160 let AddedComplexity = 20 in
161 def NAME#k: AVX512<O, F, Outs, MaskingIns,
162 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
163 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
164 MaskingPattern, itin>,
166 // In case of the 3src subclass this is overridden with a let.
167 string Constraints = MaskingConstraint;
169 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
170 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
171 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
172 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
179 // Common base class of AVX512_maskable and AVX512_maskable_3src.
180 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
182 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
184 string AttSrcAsm, string IntelSrcAsm,
185 dag RHS, dag MaskingRHS,
187 string MaskingConstraint = "",
188 InstrItinClass itin = NoItinerary,
189 bit IsCommutable = 0> :
190 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
191 AttSrcAsm, IntelSrcAsm,
192 [(set _.RC:$dst, RHS)],
193 [(set _.RC:$dst, MaskingRHS)],
195 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
196 Round, MaskingConstraint, NoItinerary, IsCommutable>;
198 // This multiclass generates the unconditional/non-masking, the masking and
199 // the zero-masking variant of the instruction. In the masking case, the
200 // perserved vector elements come from a new dummy input operand tied to $dst.
201 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
202 dag Outs, dag Ins, string OpcodeStr,
203 string AttSrcAsm, string IntelSrcAsm,
204 dag RHS, string Round = "",
205 InstrItinClass itin = NoItinerary,
206 bit IsCommutable = 0> :
207 AVX512_maskable_common<O, F, _, Outs, Ins,
208 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
209 !con((ins _.KRCWM:$mask), Ins),
210 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
211 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), Round,
212 "$src0 = $dst", itin, IsCommutable>;
214 // Similar to AVX512_maskable but in this case one of the source operands
215 // ($src1) is already tied to $dst so we just use that for the preserved
216 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
218 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
219 dag Outs, dag NonTiedIns, string OpcodeStr,
220 string AttSrcAsm, string IntelSrcAsm,
222 AVX512_maskable_common<O, F, _, Outs,
223 !con((ins _.RC:$src1), NonTiedIns),
224 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
225 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
226 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
227 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
230 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
233 string AttSrcAsm, string IntelSrcAsm,
235 AVX512_maskable_custom<O, F, Outs, Ins,
236 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
237 !con((ins _.KRCWM:$mask), Ins),
238 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
241 // Bitcasts between 512-bit vector types. Return the original type since
242 // no instruction is needed for the conversion
243 let Predicates = [HasAVX512] in {
244 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
245 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
246 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
247 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
248 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
249 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
250 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
251 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
252 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
253 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
254 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
255 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
256 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
257 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
258 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
259 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
260 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
261 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
262 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
263 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
264 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
265 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
266 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
267 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
268 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
269 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
270 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
271 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
272 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
273 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
274 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
276 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
277 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
278 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
279 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
280 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
281 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
282 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
283 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
284 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
285 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
286 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
287 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
288 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
289 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
290 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
291 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
292 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
293 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
294 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
295 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
296 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
297 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
298 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
299 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
300 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
301 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
302 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
303 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
304 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
305 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
307 // Bitcasts between 256-bit vector types. Return the original type since
308 // no instruction is needed for the conversion
309 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
310 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
311 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
312 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
313 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
314 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
315 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
316 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
317 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
318 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
319 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
320 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
321 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
322 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
323 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
324 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
325 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
326 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
327 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
328 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
329 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
330 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
331 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
332 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
333 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
334 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
335 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
336 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
337 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
338 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
342 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
345 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
346 isPseudo = 1, Predicates = [HasAVX512] in {
347 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
348 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
351 let Predicates = [HasAVX512] in {
352 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
353 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
354 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
357 //===----------------------------------------------------------------------===//
358 // AVX-512 - VECTOR INSERT
361 multiclass vinsert_for_size_no_alt<int Opcode,
362 X86VectorVTInfo From, X86VectorVTInfo To,
363 PatFrag vinsert_insert,
364 SDNodeXForm INSERT_get_vinsert_imm> {
365 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
366 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
367 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
368 "vinsert" # From.EltTypeName # "x" # From.NumElts #
369 "\t{$src3, $src2, $src1, $dst|"
370 "$dst, $src1, $src2, $src3}",
371 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
372 (From.VT From.RC:$src2),
377 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
378 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
379 "vinsert" # From.EltTypeName # "x" # From.NumElts #
380 "\t{$src3, $src2, $src1, $dst|"
381 "$dst, $src1, $src2, $src3}",
383 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
387 multiclass vinsert_for_size<int Opcode,
388 X86VectorVTInfo From, X86VectorVTInfo To,
389 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
390 PatFrag vinsert_insert,
391 SDNodeXForm INSERT_get_vinsert_imm> :
392 vinsert_for_size_no_alt<Opcode, From, To,
393 vinsert_insert, INSERT_get_vinsert_imm> {
394 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
395 // vinserti32x4. Only add this if 64x2 and friends are not supported
396 // natively via AVX512DQ.
397 let Predicates = [NoDQI] in
398 def : Pat<(vinsert_insert:$ins
399 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
400 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
401 VR512:$src1, From.RC:$src2,
402 (INSERT_get_vinsert_imm VR512:$ins)))>;
405 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
406 ValueType EltVT64, int Opcode256> {
407 defm NAME # "32x4" : vinsert_for_size<Opcode128,
408 X86VectorVTInfo< 4, EltVT32, VR128X>,
409 X86VectorVTInfo<16, EltVT32, VR512>,
410 X86VectorVTInfo< 2, EltVT64, VR128X>,
411 X86VectorVTInfo< 8, EltVT64, VR512>,
413 INSERT_get_vinsert128_imm>;
414 let Predicates = [HasDQI] in
415 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
416 X86VectorVTInfo< 2, EltVT64, VR128X>,
417 X86VectorVTInfo< 8, EltVT64, VR512>,
419 INSERT_get_vinsert128_imm>, VEX_W;
420 defm NAME # "64x4" : vinsert_for_size<Opcode256,
421 X86VectorVTInfo< 4, EltVT64, VR256X>,
422 X86VectorVTInfo< 8, EltVT64, VR512>,
423 X86VectorVTInfo< 8, EltVT32, VR256>,
424 X86VectorVTInfo<16, EltVT32, VR512>,
426 INSERT_get_vinsert256_imm>, VEX_W;
427 let Predicates = [HasDQI] in
428 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
429 X86VectorVTInfo< 8, EltVT32, VR256X>,
430 X86VectorVTInfo<16, EltVT32, VR512>,
432 INSERT_get_vinsert256_imm>;
435 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
436 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
438 // vinsertps - insert f32 to XMM
439 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
440 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
441 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
442 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
444 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
445 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
446 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
447 [(set VR128X:$dst, (X86insertps VR128X:$src1,
448 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
449 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
451 //===----------------------------------------------------------------------===//
452 // AVX-512 VECTOR EXTRACT
455 multiclass vextract_for_size<int Opcode,
456 X86VectorVTInfo From, X86VectorVTInfo To,
457 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
458 PatFrag vextract_extract,
459 SDNodeXForm EXTRACT_get_vextract_imm> {
460 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
461 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
462 (ins VR512:$src1, i8imm:$idx),
463 "vextract" # To.EltTypeName # "x4",
464 "$idx, $src1", "$src1, $idx",
465 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
467 AVX512AIi8Base, EVEX, EVEX_V512;
469 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
470 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
471 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
472 "$dst, $src1, $src2}",
473 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
476 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
478 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
479 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
481 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
483 // A 128/256-bit subvector extract from the first 512-bit vector position is
484 // a subregister copy that needs no instruction.
485 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
487 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
489 // And for the alternative types.
490 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
492 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
494 // Intrinsic call with masking.
495 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
497 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
498 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
499 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
500 VR512:$src1, imm:$idx)>;
502 // Intrinsic call with zero-masking.
503 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
505 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
506 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
507 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
508 VR512:$src1, imm:$idx)>;
510 // Intrinsic call without masking.
511 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
513 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
514 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
515 VR512:$src1, imm:$idx)>;
518 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
519 ValueType EltVT64, int Opcode64> {
520 defm NAME # "32x4" : vextract_for_size<Opcode32,
521 X86VectorVTInfo<16, EltVT32, VR512>,
522 X86VectorVTInfo< 4, EltVT32, VR128X>,
523 X86VectorVTInfo< 8, EltVT64, VR512>,
524 X86VectorVTInfo< 2, EltVT64, VR128X>,
526 EXTRACT_get_vextract128_imm>;
527 defm NAME # "64x4" : vextract_for_size<Opcode64,
528 X86VectorVTInfo< 8, EltVT64, VR512>,
529 X86VectorVTInfo< 4, EltVT64, VR256X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 X86VectorVTInfo< 8, EltVT32, VR256>,
533 EXTRACT_get_vextract256_imm>, VEX_W;
536 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
537 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
539 // A 128-bit subvector insert to the first 512-bit vector position
540 // is a subregister copy that needs no instruction.
541 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
542 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
543 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
545 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
546 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
547 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
549 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
550 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
551 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
553 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
554 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
555 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
558 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
559 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
560 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
561 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
562 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
563 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
564 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
565 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
567 // vextractps - extract 32 bits from XMM
568 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
569 (ins VR128X:$src1, i32i8imm:$src2),
570 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
571 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
574 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
575 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
576 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
577 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
578 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
580 //===---------------------------------------------------------------------===//
583 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
584 ValueType svt, X86VectorVTInfo _> {
585 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
586 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
587 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
591 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
592 (ins _.ScalarMemOp:$src),
593 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
594 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
599 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
600 AVX512VLVectorVTInfo _> {
601 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
604 let Predicates = [HasVLX] in {
605 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
610 let ExeDomain = SSEPackedSingle in {
611 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
612 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
613 let Predicates = [HasVLX] in {
614 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
615 v4f32, v4f32x_info>, EVEX_V128,
616 EVEX_CD8<32, CD8VT1>;
620 let ExeDomain = SSEPackedDouble in {
621 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
622 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
625 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
626 (VBROADCASTSSZm addr:$src)>;
627 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
628 (VBROADCASTSDZm addr:$src)>;
630 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
631 (VBROADCASTSSZm addr:$src)>;
632 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
633 (VBROADCASTSDZm addr:$src)>;
635 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
636 RegisterClass SrcRC, RegisterClass KRC> {
637 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
638 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
639 []>, EVEX, EVEX_V512;
640 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
641 (ins KRC:$mask, SrcRC:$src),
642 !strconcat(OpcodeStr,
643 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
644 []>, EVEX, EVEX_V512, EVEX_KZ;
647 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
648 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
651 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
652 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
654 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
655 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
657 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
658 (VPBROADCASTDrZrr GR32:$src)>;
659 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
660 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
661 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
662 (VPBROADCASTQrZrr GR64:$src)>;
663 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
664 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
666 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
667 (VPBROADCASTDrZrr GR32:$src)>;
668 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
669 (VPBROADCASTQrZrr GR64:$src)>;
671 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
672 (v16i32 immAllZerosV), (i16 GR16:$mask))),
673 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
674 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
675 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
676 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
678 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
679 X86MemOperand x86memop, PatFrag ld_frag,
680 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
682 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
683 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
685 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
686 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
688 !strconcat(OpcodeStr,
689 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
691 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
694 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
695 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
697 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
698 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
700 !strconcat(OpcodeStr,
701 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
702 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
703 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
707 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
708 loadi32, VR512, v16i32, v4i32, VK16WM>,
709 EVEX_V512, EVEX_CD8<32, CD8VT1>;
710 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
711 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
712 EVEX_CD8<64, CD8VT1>;
714 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
715 X86MemOperand x86memop, PatFrag ld_frag,
718 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
719 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
721 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
723 !strconcat(OpcodeStr,
724 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
729 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
730 i128mem, loadv2i64, VK16WM>,
731 EVEX_V512, EVEX_CD8<32, CD8VT4>;
732 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
733 i256mem, loadv4i64, VK16WM>, VEX_W,
734 EVEX_V512, EVEX_CD8<64, CD8VT4>;
736 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
737 (VPBROADCASTDZrr VR128X:$src)>;
738 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
739 (VPBROADCASTQZrr VR128X:$src)>;
741 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
742 (VBROADCASTSSZr VR128X:$src)>;
743 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
744 (VBROADCASTSDZr VR128X:$src)>;
746 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
747 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
748 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
749 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
751 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
752 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
753 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
754 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
756 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
757 (VBROADCASTSSZr VR128X:$src)>;
758 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
759 (VBROADCASTSDZr VR128X:$src)>;
761 // Provide fallback in case the load node that is used in the patterns above
762 // is used by additional users, which prevents the pattern selection.
763 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
764 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
765 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
766 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
769 let Predicates = [HasAVX512] in {
770 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
772 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
773 addr:$src)), sub_ymm)>;
775 //===----------------------------------------------------------------------===//
776 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
779 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
781 let Predicates = [HasCDI] in
782 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
783 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
784 []>, EVEX, EVEX_V512;
786 let Predicates = [HasCDI, HasVLX] in {
787 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
788 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
789 []>, EVEX, EVEX_V128;
790 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
791 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
792 []>, EVEX, EVEX_V256;
796 let Predicates = [HasCDI] in {
797 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
799 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
803 //===----------------------------------------------------------------------===//
806 // -- immediate form --
807 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
809 let ExeDomain = _.ExeDomain in {
810 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
811 (ins _.RC:$src1, i8imm:$src2),
812 !strconcat(OpcodeStr,
813 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
815 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
817 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
818 (ins _.MemOp:$src1, i8imm:$src2),
819 !strconcat(OpcodeStr,
820 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
822 (_.VT (OpNode (_.MemOpFrag addr:$src1),
824 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
828 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
829 X86VectorVTInfo Ctrl> :
830 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
831 let ExeDomain = _.ExeDomain in {
832 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
833 (ins _.RC:$src1, _.RC:$src2),
834 !strconcat("vpermil" # _.Suffix,
835 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
837 (_.VT (X86VPermilpv _.RC:$src1,
838 (Ctrl.VT Ctrl.RC:$src2))))]>,
840 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
841 (ins _.RC:$src1, Ctrl.MemOp:$src2),
842 !strconcat("vpermil" # _.Suffix,
843 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
845 (_.VT (X86VPermilpv _.RC:$src1,
846 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
851 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
853 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
856 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
858 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
861 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
862 (VPERMILPSZri VR512:$src1, imm:$imm)>;
863 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
864 (VPERMILPDZri VR512:$src1, imm:$imm)>;
866 // -- VPERM - register form --
867 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
868 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
870 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
871 (ins RC:$src1, RC:$src2),
872 !strconcat(OpcodeStr,
873 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
875 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
877 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
878 (ins RC:$src1, x86memop:$src2),
879 !strconcat(OpcodeStr,
880 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
882 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
886 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
887 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
888 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
889 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
890 let ExeDomain = SSEPackedSingle in
891 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
892 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
893 let ExeDomain = SSEPackedDouble in
894 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
895 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
897 // -- VPERM2I - 3 source operands form --
898 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
899 PatFrag mem_frag, X86MemOperand x86memop,
900 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
901 let Constraints = "$src1 = $dst" in {
902 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
903 (ins RC:$src1, RC:$src2, RC:$src3),
904 !strconcat(OpcodeStr,
905 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
907 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
910 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
911 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
912 !strconcat(OpcodeStr,
913 " \t{$src3, $src2, $dst {${mask}}|"
914 "$dst {${mask}}, $src2, $src3}"),
915 [(set RC:$dst, (OpVT (vselect KRC:$mask,
916 (OpNode RC:$src1, RC:$src2,
921 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
922 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
923 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
924 !strconcat(OpcodeStr,
925 " \t{$src3, $src2, $dst {${mask}} {z} |",
926 "$dst {${mask}} {z}, $src2, $src3}"),
927 [(set RC:$dst, (OpVT (vselect KRC:$mask,
928 (OpNode RC:$src1, RC:$src2,
931 (v16i32 immAllZerosV))))))]>,
934 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
935 (ins RC:$src1, RC:$src2, x86memop:$src3),
936 !strconcat(OpcodeStr,
937 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
939 (OpVT (OpNode RC:$src1, RC:$src2,
940 (mem_frag addr:$src3))))]>, EVEX_4V;
942 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
943 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
944 !strconcat(OpcodeStr,
945 " \t{$src3, $src2, $dst {${mask}}|"
946 "$dst {${mask}}, $src2, $src3}"),
948 (OpVT (vselect KRC:$mask,
949 (OpNode RC:$src1, RC:$src2,
950 (mem_frag addr:$src3)),
954 let AddedComplexity = 10 in // Prefer over the rrkz variant
955 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
956 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
957 !strconcat(OpcodeStr,
958 " \t{$src3, $src2, $dst {${mask}} {z}|"
959 "$dst {${mask}} {z}, $src2, $src3}"),
961 (OpVT (vselect KRC:$mask,
962 (OpNode RC:$src1, RC:$src2,
963 (mem_frag addr:$src3)),
965 (v16i32 immAllZerosV))))))]>,
969 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
970 i512mem, X86VPermiv3, v16i32, VK16WM>,
971 EVEX_V512, EVEX_CD8<32, CD8VF>;
972 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
973 i512mem, X86VPermiv3, v8i64, VK8WM>,
974 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
975 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
976 i512mem, X86VPermiv3, v16f32, VK16WM>,
977 EVEX_V512, EVEX_CD8<32, CD8VF>;
978 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
979 i512mem, X86VPermiv3, v8f64, VK8WM>,
980 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
982 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
983 PatFrag mem_frag, X86MemOperand x86memop,
984 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
985 ValueType MaskVT, RegisterClass MRC> :
986 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
988 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
989 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
990 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
992 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
993 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
994 (!cast<Instruction>(NAME#rrk) VR512:$src1,
995 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
998 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
999 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1000 EVEX_V512, EVEX_CD8<32, CD8VF>;
1001 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1002 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1003 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1004 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1005 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1006 EVEX_V512, EVEX_CD8<32, CD8VF>;
1007 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1008 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1009 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1011 //===----------------------------------------------------------------------===//
1012 // AVX-512 - BLEND using mask
1014 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
1015 RegisterClass KRC, RegisterClass RC,
1016 X86MemOperand x86memop, PatFrag mem_frag,
1017 SDNode OpNode, ValueType vt> {
1018 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1019 (ins KRC:$mask, RC:$src1, RC:$src2),
1020 !strconcat(OpcodeStr,
1021 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1022 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
1023 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
1025 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1026 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1027 !strconcat(OpcodeStr,
1028 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1029 []>, EVEX_4V, EVEX_K;
1032 let ExeDomain = SSEPackedSingle in
1033 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1034 VK16WM, VR512, f512mem,
1035 memopv16f32, vselect, v16f32>,
1036 EVEX_CD8<32, CD8VF>, EVEX_V512;
1037 let ExeDomain = SSEPackedDouble in
1038 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1039 VK8WM, VR512, f512mem,
1040 memopv8f64, vselect, v8f64>,
1041 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1043 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1044 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1045 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1046 VR512:$src1, VR512:$src2)>;
1048 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1049 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1050 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1051 VR512:$src1, VR512:$src2)>;
1053 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1054 VK16WM, VR512, f512mem,
1055 memopv16i32, vselect, v16i32>,
1056 EVEX_CD8<32, CD8VF>, EVEX_V512;
1058 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1059 VK8WM, VR512, f512mem,
1060 memopv8i64, vselect, v8i64>,
1061 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1063 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1064 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1065 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1066 VR512:$src1, VR512:$src2)>;
1068 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1069 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1070 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1071 VR512:$src1, VR512:$src2)>;
1073 let Predicates = [HasAVX512] in {
1074 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1075 (v8f32 VR256X:$src2))),
1077 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1078 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1079 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1081 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1082 (v8i32 VR256X:$src2))),
1084 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1085 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1086 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1088 //===----------------------------------------------------------------------===//
1089 // Compare Instructions
1090 //===----------------------------------------------------------------------===//
1092 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1093 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1094 Operand CC, SDNode OpNode, ValueType VT,
1095 PatFrag ld_frag, string asm, string asm_alt> {
1096 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1097 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1098 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1099 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1100 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1101 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1102 [(set VK1:$dst, (OpNode (VT RC:$src1),
1103 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1104 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1105 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1106 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1107 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1108 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1109 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1110 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1114 let Predicates = [HasAVX512] in {
1115 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1116 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1117 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1119 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1120 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1121 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1125 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1126 X86VectorVTInfo _> {
1127 def rr : AVX512BI<opc, MRMSrcReg,
1128 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1129 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1130 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1131 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1133 def rm : AVX512BI<opc, MRMSrcMem,
1134 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1135 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1136 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1137 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1138 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1139 def rrk : AVX512BI<opc, MRMSrcReg,
1140 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1141 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1142 "$dst {${mask}}, $src1, $src2}"),
1143 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1144 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1145 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1147 def rmk : AVX512BI<opc, MRMSrcMem,
1148 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1149 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1150 "$dst {${mask}}, $src1, $src2}"),
1151 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1152 (OpNode (_.VT _.RC:$src1),
1154 (_.LdFrag addr:$src2))))))],
1155 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1158 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1159 X86VectorVTInfo _> :
1160 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1161 let mayLoad = 1 in {
1162 def rmb : AVX512BI<opc, MRMSrcMem,
1163 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1164 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1165 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1166 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1167 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1168 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1169 def rmbk : AVX512BI<opc, MRMSrcMem,
1170 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1171 _.ScalarMemOp:$src2),
1172 !strconcat(OpcodeStr,
1173 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1174 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1175 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1176 (OpNode (_.VT _.RC:$src1),
1178 (_.ScalarLdFrag addr:$src2)))))],
1179 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1183 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1184 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1185 let Predicates = [prd] in
1186 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1189 let Predicates = [prd, HasVLX] in {
1190 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1192 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1197 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1198 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1200 let Predicates = [prd] in
1201 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1204 let Predicates = [prd, HasVLX] in {
1205 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1207 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1212 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1213 avx512vl_i8_info, HasBWI>,
1216 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1217 avx512vl_i16_info, HasBWI>,
1218 EVEX_CD8<16, CD8VF>;
1220 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1221 avx512vl_i32_info, HasAVX512>,
1222 EVEX_CD8<32, CD8VF>;
1224 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1225 avx512vl_i64_info, HasAVX512>,
1226 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1228 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1229 avx512vl_i8_info, HasBWI>,
1232 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1233 avx512vl_i16_info, HasBWI>,
1234 EVEX_CD8<16, CD8VF>;
1236 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1237 avx512vl_i32_info, HasAVX512>,
1238 EVEX_CD8<32, CD8VF>;
1240 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1241 avx512vl_i64_info, HasAVX512>,
1242 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1244 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1245 (COPY_TO_REGCLASS (VPCMPGTDZrr
1246 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1247 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1249 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1250 (COPY_TO_REGCLASS (VPCMPEQDZrr
1251 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1252 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1254 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1255 X86VectorVTInfo _> {
1256 def rri : AVX512AIi8<opc, MRMSrcReg,
1257 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1258 !strconcat("vpcmp${cc}", Suffix,
1259 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1260 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1262 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1264 def rmi : AVX512AIi8<opc, MRMSrcMem,
1265 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1266 !strconcat("vpcmp${cc}", Suffix,
1267 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1268 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1269 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1271 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1272 def rrik : AVX512AIi8<opc, MRMSrcReg,
1273 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1275 !strconcat("vpcmp${cc}", Suffix,
1276 "\t{$src2, $src1, $dst {${mask}}|",
1277 "$dst {${mask}}, $src1, $src2}"),
1278 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1279 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1281 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1283 def rmik : AVX512AIi8<opc, MRMSrcMem,
1284 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1286 !strconcat("vpcmp${cc}", Suffix,
1287 "\t{$src2, $src1, $dst {${mask}}|",
1288 "$dst {${mask}}, $src1, $src2}"),
1289 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1290 (OpNode (_.VT _.RC:$src1),
1291 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1293 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1295 // Accept explicit immediate argument form instead of comparison code.
1296 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1297 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1298 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1299 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1300 "$dst, $src1, $src2, $cc}"),
1301 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1302 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1303 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1304 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1305 "$dst, $src1, $src2, $cc}"),
1306 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1307 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1308 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1310 !strconcat("vpcmp", Suffix,
1311 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1312 "$dst {${mask}}, $src1, $src2, $cc}"),
1313 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1314 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1315 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1317 !strconcat("vpcmp", Suffix,
1318 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1319 "$dst {${mask}}, $src1, $src2, $cc}"),
1320 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1324 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1325 X86VectorVTInfo _> :
1326 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1327 let mayLoad = 1 in {
1328 def rmib : AVX512AIi8<opc, MRMSrcMem,
1329 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1331 !strconcat("vpcmp${cc}", Suffix,
1332 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1333 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1334 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1335 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1337 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1338 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1339 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1340 _.ScalarMemOp:$src2, AVXCC:$cc),
1341 !strconcat("vpcmp${cc}", Suffix,
1342 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1343 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1344 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1345 (OpNode (_.VT _.RC:$src1),
1346 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1348 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1351 // Accept explicit immediate argument form instead of comparison code.
1352 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1353 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1354 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1356 !strconcat("vpcmp", Suffix,
1357 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1358 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1359 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1360 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1361 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1362 _.ScalarMemOp:$src2, i8imm:$cc),
1363 !strconcat("vpcmp", Suffix,
1364 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1365 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1366 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1370 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1371 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1372 let Predicates = [prd] in
1373 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1375 let Predicates = [prd, HasVLX] in {
1376 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1377 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1381 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1382 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1383 let Predicates = [prd] in
1384 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1387 let Predicates = [prd, HasVLX] in {
1388 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1390 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1395 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1396 HasBWI>, EVEX_CD8<8, CD8VF>;
1397 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1398 HasBWI>, EVEX_CD8<8, CD8VF>;
1400 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1401 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1402 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1403 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1405 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1406 HasAVX512>, EVEX_CD8<32, CD8VF>;
1407 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1408 HasAVX512>, EVEX_CD8<32, CD8VF>;
1410 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1411 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1412 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1413 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1415 // avx512_cmp_packed - compare packed instructions
1416 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1417 X86MemOperand x86memop, ValueType vt,
1418 string suffix, Domain d> {
1419 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1420 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1421 !strconcat("vcmp${cc}", suffix,
1422 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1423 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1424 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1425 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1426 !strconcat("vcmp${cc}", suffix,
1427 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1429 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1430 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1431 !strconcat("vcmp${cc}", suffix,
1432 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1434 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1436 // Accept explicit immediate argument form instead of comparison code.
1437 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1438 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1439 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1440 !strconcat("vcmp", suffix,
1441 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1442 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1443 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1444 !strconcat("vcmp", suffix,
1445 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1449 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1450 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1451 EVEX_CD8<32, CD8VF>;
1452 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1453 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1454 EVEX_CD8<64, CD8VF>;
1456 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1457 (COPY_TO_REGCLASS (VCMPPSZrri
1458 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1459 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1461 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1462 (COPY_TO_REGCLASS (VPCMPDZrri
1463 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1464 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1466 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1467 (COPY_TO_REGCLASS (VPCMPUDZrri
1468 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1469 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1472 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1473 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1475 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1476 (I8Imm imm:$cc)), GR16)>;
1478 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1479 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1481 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1482 (I8Imm imm:$cc)), GR8)>;
1484 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1485 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1487 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1488 (I8Imm imm:$cc)), GR16)>;
1490 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1491 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1493 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1494 (I8Imm imm:$cc)), GR8)>;
1496 // Mask register copy, including
1497 // - copy between mask registers
1498 // - load/store mask registers
1499 // - copy from GPR to mask register and vice versa
1501 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1502 string OpcodeStr, RegisterClass KRC,
1503 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1504 let hasSideEffects = 0 in {
1505 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1506 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1508 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1509 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1510 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1512 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1513 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1517 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1519 RegisterClass KRC, RegisterClass GRC> {
1520 let hasSideEffects = 0 in {
1521 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1522 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1523 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1524 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1528 let Predicates = [HasDQI] in
1529 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1531 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1534 let Predicates = [HasAVX512] in
1535 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1537 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1540 let Predicates = [HasBWI] in {
1541 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1542 i32mem>, VEX, PD, VEX_W;
1543 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1547 let Predicates = [HasBWI] in {
1548 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1549 i64mem>, VEX, PS, VEX_W;
1550 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1554 // GR from/to mask register
1555 let Predicates = [HasDQI] in {
1556 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1557 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1558 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1559 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1561 let Predicates = [HasAVX512] in {
1562 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1563 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1564 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1565 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1567 let Predicates = [HasBWI] in {
1568 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1569 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1571 let Predicates = [HasBWI] in {
1572 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1573 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1577 let Predicates = [HasDQI] in {
1578 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1579 (KMOVBmk addr:$dst, VK8:$src)>;
1581 let Predicates = [HasAVX512] in {
1582 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1583 (KMOVWmk addr:$dst, VK16:$src)>;
1584 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1585 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1586 def : Pat<(i1 (load addr:$src)),
1587 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1588 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1589 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1591 let Predicates = [HasBWI] in {
1592 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1593 (KMOVDmk addr:$dst, VK32:$src)>;
1595 let Predicates = [HasBWI] in {
1596 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1597 (KMOVQmk addr:$dst, VK64:$src)>;
1600 let Predicates = [HasAVX512] in {
1601 def : Pat<(i1 (trunc (i64 GR64:$src))),
1602 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1605 def : Pat<(i1 (trunc (i32 GR32:$src))),
1606 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1608 def : Pat<(i1 (trunc (i8 GR8:$src))),
1610 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1612 def : Pat<(i1 (trunc (i16 GR16:$src))),
1614 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1617 def : Pat<(i32 (zext VK1:$src)),
1618 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1619 def : Pat<(i8 (zext VK1:$src)),
1622 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1623 def : Pat<(i64 (zext VK1:$src)),
1624 (AND64ri8 (SUBREG_TO_REG (i64 0),
1625 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1626 def : Pat<(i16 (zext VK1:$src)),
1628 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1630 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1631 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1632 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1633 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1635 let Predicates = [HasBWI] in {
1636 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1637 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1638 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1639 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1643 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1644 let Predicates = [HasAVX512] in {
1645 // GR from/to 8-bit mask without native support
1646 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1648 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1650 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1652 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1655 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1656 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1657 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1658 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1660 let Predicates = [HasBWI] in {
1661 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1662 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1663 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1664 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1667 // Mask unary operation
1669 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1670 RegisterClass KRC, SDPatternOperator OpNode,
1672 let Predicates = [prd] in
1673 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1674 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1675 [(set KRC:$dst, (OpNode KRC:$src))]>;
1678 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1679 SDPatternOperator OpNode> {
1680 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1682 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1683 HasAVX512>, VEX, PS;
1684 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1685 HasBWI>, VEX, PD, VEX_W;
1686 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1687 HasBWI>, VEX, PS, VEX_W;
1690 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1692 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1693 let Predicates = [HasAVX512] in
1694 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1696 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1697 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1699 defm : avx512_mask_unop_int<"knot", "KNOT">;
1701 let Predicates = [HasDQI] in
1702 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1703 let Predicates = [HasAVX512] in
1704 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1705 let Predicates = [HasBWI] in
1706 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1707 let Predicates = [HasBWI] in
1708 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1710 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1711 let Predicates = [HasAVX512] in {
1712 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1713 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1715 def : Pat<(not VK8:$src),
1717 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1720 // Mask binary operation
1721 // - KAND, KANDN, KOR, KXNOR, KXOR
1722 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1723 RegisterClass KRC, SDPatternOperator OpNode,
1725 let Predicates = [prd] in
1726 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1727 !strconcat(OpcodeStr,
1728 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1729 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1732 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1733 SDPatternOperator OpNode> {
1734 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1735 HasDQI>, VEX_4V, VEX_L, PD;
1736 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1737 HasAVX512>, VEX_4V, VEX_L, PS;
1738 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1739 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1740 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1741 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1744 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1745 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1747 let isCommutable = 1 in {
1748 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1749 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1750 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1751 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1753 let isCommutable = 0 in
1754 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1756 def : Pat<(xor VK1:$src1, VK1:$src2),
1757 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1758 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1760 def : Pat<(or VK1:$src1, VK1:$src2),
1761 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1762 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1764 def : Pat<(and VK1:$src1, VK1:$src2),
1765 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1766 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1768 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1769 let Predicates = [HasAVX512] in
1770 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1771 (i16 GR16:$src1), (i16 GR16:$src2)),
1772 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1773 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1774 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1777 defm : avx512_mask_binop_int<"kand", "KAND">;
1778 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1779 defm : avx512_mask_binop_int<"kor", "KOR">;
1780 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1781 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1783 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1784 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1785 let Predicates = [HasAVX512] in
1786 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1788 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1789 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1792 defm : avx512_binop_pat<and, KANDWrr>;
1793 defm : avx512_binop_pat<andn, KANDNWrr>;
1794 defm : avx512_binop_pat<or, KORWrr>;
1795 defm : avx512_binop_pat<xnor, KXNORWrr>;
1796 defm : avx512_binop_pat<xor, KXORWrr>;
1799 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1800 RegisterClass KRC> {
1801 let Predicates = [HasAVX512] in
1802 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1803 !strconcat(OpcodeStr,
1804 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1807 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1808 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1812 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1813 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1814 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1815 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1818 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1819 let Predicates = [HasAVX512] in
1820 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1821 (i16 GR16:$src1), (i16 GR16:$src2)),
1822 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1823 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1824 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1826 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1829 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1831 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1832 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1833 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1834 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1837 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1838 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1842 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1844 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1845 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1846 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1849 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1851 let Predicates = [HasAVX512] in
1852 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1853 !strconcat(OpcodeStr,
1854 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1855 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1858 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1860 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1864 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1865 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1867 // Mask setting all 0s or 1s
1868 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1869 let Predicates = [HasAVX512] in
1870 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1871 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1872 [(set KRC:$dst, (VT Val))]>;
1875 multiclass avx512_mask_setop_w<PatFrag Val> {
1876 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1877 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1880 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1881 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1883 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1884 let Predicates = [HasAVX512] in {
1885 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1886 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1887 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1888 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1889 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1891 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1892 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1894 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1895 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1897 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1898 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1900 let Predicates = [HasVLX] in {
1901 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1902 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1903 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1904 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1905 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1906 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1907 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1908 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1911 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1912 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1914 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1915 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1916 //===----------------------------------------------------------------------===//
1917 // AVX-512 - Aligned and unaligned load and store
1920 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1921 RegisterClass KRC, RegisterClass RC,
1922 ValueType vt, ValueType zvt, X86MemOperand memop,
1923 Domain d, bit IsReMaterializable = 1> {
1924 let hasSideEffects = 0 in {
1925 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1926 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1928 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1929 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1930 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1932 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1933 SchedRW = [WriteLoad] in
1934 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1935 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1936 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1939 let AddedComplexity = 20 in {
1940 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1941 let hasSideEffects = 0 in
1942 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1943 (ins RC:$src0, KRC:$mask, RC:$src1),
1944 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1945 "${dst} {${mask}}, $src1}"),
1946 [(set RC:$dst, (vt (vselect KRC:$mask,
1950 let mayLoad = 1, SchedRW = [WriteLoad] in
1951 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1952 (ins RC:$src0, KRC:$mask, memop:$src1),
1953 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1954 "${dst} {${mask}}, $src1}"),
1957 (vt (bitconvert (ld_frag addr:$src1))),
1961 let mayLoad = 1, SchedRW = [WriteLoad] in
1962 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1963 (ins KRC:$mask, memop:$src),
1964 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1965 "${dst} {${mask}} {z}, $src}"),
1968 (vt (bitconvert (ld_frag addr:$src))),
1969 (vt (bitconvert (zvt immAllZerosV))))))],
1974 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1975 string elty, string elsz, string vsz512,
1976 string vsz256, string vsz128, Domain d,
1977 Predicate prd, bit IsReMaterializable = 1> {
1978 let Predicates = [prd] in
1979 defm Z : avx512_load<opc, OpcodeStr,
1980 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1981 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1982 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1983 !cast<X86MemOperand>(elty##"512mem"), d,
1984 IsReMaterializable>, EVEX_V512;
1986 let Predicates = [prd, HasVLX] in {
1987 defm Z256 : avx512_load<opc, OpcodeStr,
1988 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1989 "v"##vsz256##elty##elsz, "v4i64")),
1990 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1991 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1992 !cast<X86MemOperand>(elty##"256mem"), d,
1993 IsReMaterializable>, EVEX_V256;
1995 defm Z128 : avx512_load<opc, OpcodeStr,
1996 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1997 "v"##vsz128##elty##elsz, "v2i64")),
1998 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1999 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2000 !cast<X86MemOperand>(elty##"128mem"), d,
2001 IsReMaterializable>, EVEX_V128;
2006 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2007 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2008 X86MemOperand memop, Domain d> {
2009 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2010 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2011 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2013 let Constraints = "$src1 = $dst" in
2014 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2015 (ins RC:$src1, KRC:$mask, RC:$src2),
2016 !strconcat(OpcodeStr,
2017 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2019 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2020 (ins KRC:$mask, RC:$src),
2021 !strconcat(OpcodeStr,
2022 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2023 [], d>, EVEX, EVEX_KZ;
2025 let mayStore = 1 in {
2026 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2027 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2028 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2029 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2030 (ins memop:$dst, KRC:$mask, RC:$src),
2031 !strconcat(OpcodeStr,
2032 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2033 [], d>, EVEX, EVEX_K;
2038 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2039 string st_suff_512, string st_suff_256,
2040 string st_suff_128, string elty, string elsz,
2041 string vsz512, string vsz256, string vsz128,
2042 Domain d, Predicate prd> {
2043 let Predicates = [prd] in
2044 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2045 !cast<ValueType>("v"##vsz512##elty##elsz),
2046 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2047 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2049 let Predicates = [prd, HasVLX] in {
2050 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2051 !cast<ValueType>("v"##vsz256##elty##elsz),
2052 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2053 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2055 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2056 !cast<ValueType>("v"##vsz128##elty##elsz),
2057 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2058 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2062 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2063 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2064 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2065 "512", "256", "", "f", "32", "16", "8", "4",
2066 SSEPackedSingle, HasAVX512>,
2067 PS, EVEX_CD8<32, CD8VF>;
2069 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2070 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2071 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2072 "512", "256", "", "f", "64", "8", "4", "2",
2073 SSEPackedDouble, HasAVX512>,
2074 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2076 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2077 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2078 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2079 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2080 PS, EVEX_CD8<32, CD8VF>;
2082 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2083 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2084 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2085 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2086 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2088 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2089 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2090 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2092 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2093 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2094 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2096 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2098 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2100 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2102 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2105 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2106 "16", "8", "4", SSEPackedInt, HasAVX512>,
2107 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2108 "512", "256", "", "i", "32", "16", "8", "4",
2109 SSEPackedInt, HasAVX512>,
2110 PD, EVEX_CD8<32, CD8VF>;
2112 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2113 "8", "4", "2", SSEPackedInt, HasAVX512>,
2114 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2115 "512", "256", "", "i", "64", "8", "4", "2",
2116 SSEPackedInt, HasAVX512>,
2117 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2119 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2120 "64", "32", "16", SSEPackedInt, HasBWI>,
2121 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2122 "i", "8", "64", "32", "16", SSEPackedInt,
2123 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2125 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2126 "32", "16", "8", SSEPackedInt, HasBWI>,
2127 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2128 "i", "16", "32", "16", "8", SSEPackedInt,
2129 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2131 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2132 "16", "8", "4", SSEPackedInt, HasAVX512>,
2133 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2134 "i", "32", "16", "8", "4", SSEPackedInt,
2135 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2137 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2138 "8", "4", "2", SSEPackedInt, HasAVX512>,
2139 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2140 "i", "64", "8", "4", "2", SSEPackedInt,
2141 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2143 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2144 (v16i32 immAllZerosV), GR16:$mask)),
2145 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2147 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2148 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2149 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2151 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2153 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2155 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2157 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2160 let AddedComplexity = 20 in {
2161 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2162 (bc_v8i64 (v16i32 immAllZerosV)))),
2163 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2165 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2166 (v8i64 VR512:$src))),
2167 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2170 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2171 (v16i32 immAllZerosV))),
2172 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2174 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2175 (v16i32 VR512:$src))),
2176 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2179 // Move Int Doubleword to Packed Double Int
2181 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2182 "vmovd\t{$src, $dst|$dst, $src}",
2184 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2186 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2187 "vmovd\t{$src, $dst|$dst, $src}",
2189 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2190 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2191 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2192 "vmovq\t{$src, $dst|$dst, $src}",
2194 (v2i64 (scalar_to_vector GR64:$src)))],
2195 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2196 let isCodeGenOnly = 1 in {
2197 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2198 "vmovq\t{$src, $dst|$dst, $src}",
2199 [(set FR64:$dst, (bitconvert GR64:$src))],
2200 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2201 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2202 "vmovq\t{$src, $dst|$dst, $src}",
2203 [(set GR64:$dst, (bitconvert FR64:$src))],
2204 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2206 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2207 "vmovq\t{$src, $dst|$dst, $src}",
2208 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2209 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2210 EVEX_CD8<64, CD8VT1>;
2212 // Move Int Doubleword to Single Scalar
2214 let isCodeGenOnly = 1 in {
2215 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2216 "vmovd\t{$src, $dst|$dst, $src}",
2217 [(set FR32X:$dst, (bitconvert GR32:$src))],
2218 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2220 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2221 "vmovd\t{$src, $dst|$dst, $src}",
2222 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2223 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2226 // Move doubleword from xmm register to r/m32
2228 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2229 "vmovd\t{$src, $dst|$dst, $src}",
2230 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2231 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2233 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2234 (ins i32mem:$dst, VR128X:$src),
2235 "vmovd\t{$src, $dst|$dst, $src}",
2236 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2237 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2238 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2240 // Move quadword from xmm1 register to r/m64
2242 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2243 "vmovq\t{$src, $dst|$dst, $src}",
2244 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2246 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2247 Requires<[HasAVX512, In64BitMode]>;
2249 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2250 (ins i64mem:$dst, VR128X:$src),
2251 "vmovq\t{$src, $dst|$dst, $src}",
2252 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2253 addr:$dst)], IIC_SSE_MOVDQ>,
2254 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2255 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2257 // Move Scalar Single to Double Int
2259 let isCodeGenOnly = 1 in {
2260 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2262 "vmovd\t{$src, $dst|$dst, $src}",
2263 [(set GR32:$dst, (bitconvert FR32X:$src))],
2264 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2265 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2266 (ins i32mem:$dst, FR32X:$src),
2267 "vmovd\t{$src, $dst|$dst, $src}",
2268 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2269 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2272 // Move Quadword Int to Packed Quadword Int
2274 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2276 "vmovq\t{$src, $dst|$dst, $src}",
2278 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2279 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2281 //===----------------------------------------------------------------------===//
2282 // AVX-512 MOVSS, MOVSD
2283 //===----------------------------------------------------------------------===//
2285 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2286 SDNode OpNode, ValueType vt,
2287 X86MemOperand x86memop, PatFrag mem_pat> {
2288 let hasSideEffects = 0 in {
2289 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2290 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2291 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2292 (scalar_to_vector RC:$src2))))],
2293 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2294 let Constraints = "$src1 = $dst" in
2295 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2296 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2298 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2299 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2300 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2301 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2302 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2304 let mayStore = 1 in {
2305 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2306 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
2307 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2309 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2310 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2311 [], IIC_SSE_MOV_S_MR>,
2312 EVEX, VEX_LIG, EVEX_K;
2314 } //hasSideEffects = 0
2317 let ExeDomain = SSEPackedSingle in
2318 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2319 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2321 let ExeDomain = SSEPackedDouble in
2322 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2323 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2325 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2326 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2327 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2329 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2330 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2331 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2333 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2334 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2335 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2337 // For the disassembler
2338 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2339 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2340 (ins VR128X:$src1, FR32X:$src2),
2341 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2343 XS, EVEX_4V, VEX_LIG;
2344 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2345 (ins VR128X:$src1, FR64X:$src2),
2346 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2348 XD, EVEX_4V, VEX_LIG, VEX_W;
2351 let Predicates = [HasAVX512] in {
2352 let AddedComplexity = 15 in {
2353 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2354 // MOVS{S,D} to the lower bits.
2355 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2356 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2357 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2358 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2359 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2360 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2361 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2362 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2364 // Move low f32 and clear high bits.
2365 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2366 (SUBREG_TO_REG (i32 0),
2367 (VMOVSSZrr (v4f32 (V_SET0)),
2368 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2369 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2370 (SUBREG_TO_REG (i32 0),
2371 (VMOVSSZrr (v4i32 (V_SET0)),
2372 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2375 let AddedComplexity = 20 in {
2376 // MOVSSrm zeros the high parts of the register; represent this
2377 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2378 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2379 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2380 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2381 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2382 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2383 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2385 // MOVSDrm zeros the high parts of the register; represent this
2386 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2387 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2388 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2389 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2390 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2391 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2392 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2393 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2394 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2395 def : Pat<(v2f64 (X86vzload addr:$src)),
2396 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2398 // Represent the same patterns above but in the form they appear for
2400 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2401 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2402 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2403 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2404 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2405 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2406 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2407 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2408 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2410 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2411 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2412 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2413 FR32X:$src)), sub_xmm)>;
2414 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2415 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2416 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2417 FR64X:$src)), sub_xmm)>;
2418 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2419 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2420 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2422 // Move low f64 and clear high bits.
2423 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2424 (SUBREG_TO_REG (i32 0),
2425 (VMOVSDZrr (v2f64 (V_SET0)),
2426 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2428 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2429 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2430 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2432 // Extract and store.
2433 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2435 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2436 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2438 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2440 // Shuffle with VMOVSS
2441 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2442 (VMOVSSZrr (v4i32 VR128X:$src1),
2443 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2444 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2445 (VMOVSSZrr (v4f32 VR128X:$src1),
2446 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2449 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2450 (SUBREG_TO_REG (i32 0),
2451 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2452 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2454 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2455 (SUBREG_TO_REG (i32 0),
2456 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2457 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2460 // Shuffle with VMOVSD
2461 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2462 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2463 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2464 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2465 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2466 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2467 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2468 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2471 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2472 (SUBREG_TO_REG (i32 0),
2473 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2474 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2476 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2477 (SUBREG_TO_REG (i32 0),
2478 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2479 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2482 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2483 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2484 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2485 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2486 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2487 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2488 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2489 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2492 let AddedComplexity = 15 in
2493 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2495 "vmovq\t{$src, $dst|$dst, $src}",
2496 [(set VR128X:$dst, (v2i64 (X86vzmovl
2497 (v2i64 VR128X:$src))))],
2498 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2500 let AddedComplexity = 20 in
2501 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2503 "vmovq\t{$src, $dst|$dst, $src}",
2504 [(set VR128X:$dst, (v2i64 (X86vzmovl
2505 (loadv2i64 addr:$src))))],
2506 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2507 EVEX_CD8<8, CD8VT8>;
2509 let Predicates = [HasAVX512] in {
2510 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2511 let AddedComplexity = 20 in {
2512 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2513 (VMOVDI2PDIZrm addr:$src)>;
2514 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2515 (VMOV64toPQIZrr GR64:$src)>;
2516 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2517 (VMOVDI2PDIZrr GR32:$src)>;
2519 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2520 (VMOVDI2PDIZrm addr:$src)>;
2521 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2522 (VMOVDI2PDIZrm addr:$src)>;
2523 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2524 (VMOVZPQILo2PQIZrm addr:$src)>;
2525 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2526 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2527 def : Pat<(v2i64 (X86vzload addr:$src)),
2528 (VMOVZPQILo2PQIZrm addr:$src)>;
2531 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2532 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2533 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2534 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2535 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2536 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2537 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2540 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2541 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2543 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2544 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2546 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2547 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2549 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2550 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2552 //===----------------------------------------------------------------------===//
2553 // AVX-512 - Non-temporals
2554 //===----------------------------------------------------------------------===//
2555 let SchedRW = [WriteLoad] in {
2556 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2557 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2558 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2559 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2560 EVEX_CD8<64, CD8VF>;
2562 let Predicates = [HasAVX512, HasVLX] in {
2563 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2565 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2566 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2567 EVEX_CD8<64, CD8VF>;
2569 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2571 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2572 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2573 EVEX_CD8<64, CD8VF>;
2577 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2578 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2579 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2580 let SchedRW = [WriteStore], mayStore = 1,
2581 AddedComplexity = 400 in
2582 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2583 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2584 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2587 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2588 string elty, string elsz, string vsz512,
2589 string vsz256, string vsz128, Domain d,
2590 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2591 let Predicates = [prd] in
2592 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2593 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2594 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2597 let Predicates = [prd, HasVLX] in {
2598 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2599 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2600 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2603 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2604 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2605 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2610 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2611 "i", "64", "8", "4", "2", SSEPackedInt,
2612 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2614 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2615 "f", "64", "8", "4", "2", SSEPackedDouble,
2616 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2618 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2619 "f", "32", "16", "8", "4", SSEPackedSingle,
2620 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2622 //===----------------------------------------------------------------------===//
2623 // AVX-512 - Integer arithmetic
2625 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2626 X86VectorVTInfo _, OpndItins itins,
2627 bit IsCommutable = 0> {
2628 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2629 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2630 "$src2, $src1", "$src1, $src2",
2631 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2632 "", itins.rr, IsCommutable>,
2633 AVX512BIBase, EVEX_4V;
2636 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2637 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2638 "$src2, $src1", "$src1, $src2",
2639 (_.VT (OpNode _.RC:$src1,
2640 (bitconvert (_.LdFrag addr:$src2)))),
2642 AVX512BIBase, EVEX_4V;
2645 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2646 X86VectorVTInfo _, OpndItins itins,
2647 bit IsCommutable = 0> :
2648 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2650 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2651 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2652 "${src2}"##_.BroadcastStr##", $src1",
2653 "$src1, ${src2}"##_.BroadcastStr,
2654 (_.VT (OpNode _.RC:$src1,
2656 (_.ScalarLdFrag addr:$src2)))),
2658 AVX512BIBase, EVEX_4V, EVEX_B;
2661 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2662 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2663 Predicate prd, bit IsCommutable = 0> {
2664 let Predicates = [prd] in
2665 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2666 IsCommutable>, EVEX_V512;
2668 let Predicates = [prd, HasVLX] in {
2669 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2670 IsCommutable>, EVEX_V256;
2671 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2672 IsCommutable>, EVEX_V128;
2676 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2677 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2678 Predicate prd, bit IsCommutable = 0> {
2679 let Predicates = [prd] in
2680 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2681 IsCommutable>, EVEX_V512;
2683 let Predicates = [prd, HasVLX] in {
2684 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2685 IsCommutable>, EVEX_V256;
2686 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2687 IsCommutable>, EVEX_V128;
2691 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2692 OpndItins itins, Predicate prd,
2693 bit IsCommutable = 0> {
2694 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2695 itins, prd, IsCommutable>,
2696 VEX_W, EVEX_CD8<64, CD8VF>;
2699 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2700 OpndItins itins, Predicate prd,
2701 bit IsCommutable = 0> {
2702 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2703 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2706 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2707 OpndItins itins, Predicate prd,
2708 bit IsCommutable = 0> {
2709 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2710 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2713 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2714 OpndItins itins, Predicate prd,
2715 bit IsCommutable = 0> {
2716 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2717 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2720 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2721 SDNode OpNode, OpndItins itins, Predicate prd,
2722 bit IsCommutable = 0> {
2723 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2726 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2730 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2731 SDNode OpNode, OpndItins itins, Predicate prd,
2732 bit IsCommutable = 0> {
2733 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2736 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2740 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2741 bits<8> opc_d, bits<8> opc_q,
2742 string OpcodeStr, SDNode OpNode,
2743 OpndItins itins, bit IsCommutable = 0> {
2744 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2745 itins, HasAVX512, IsCommutable>,
2746 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2747 itins, HasBWI, IsCommutable>;
2750 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2751 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2752 PatFrag memop_frag, X86MemOperand x86memop,
2753 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2754 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2755 let isCommutable = IsCommutable in
2757 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2758 (ins RC:$src1, RC:$src2),
2759 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2761 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2762 (ins KRC:$mask, RC:$src1, RC:$src2),
2763 !strconcat(OpcodeStr,
2764 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2765 [], itins.rr>, EVEX_4V, EVEX_K;
2766 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2767 (ins KRC:$mask, RC:$src1, RC:$src2),
2768 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2769 "|$dst {${mask}} {z}, $src1, $src2}"),
2770 [], itins.rr>, EVEX_4V, EVEX_KZ;
2772 let mayLoad = 1 in {
2773 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2774 (ins RC:$src1, x86memop:$src2),
2775 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2777 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2778 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2779 !strconcat(OpcodeStr,
2780 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2781 [], itins.rm>, EVEX_4V, EVEX_K;
2782 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2783 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2784 !strconcat(OpcodeStr,
2785 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2786 [], itins.rm>, EVEX_4V, EVEX_KZ;
2787 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2788 (ins RC:$src1, x86scalar_mop:$src2),
2789 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2790 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2791 [], itins.rm>, EVEX_4V, EVEX_B;
2792 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2793 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2794 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2795 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2797 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2798 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2799 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2800 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2801 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2803 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2807 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2808 SSE_INTALU_ITINS_P, 1>;
2809 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2810 SSE_INTALU_ITINS_P, 0>;
2811 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2812 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2813 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2814 SSE_INTALU_ITINS_P, HasBWI, 1>;
2815 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2816 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2818 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2819 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2820 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2821 EVEX_CD8<64, CD8VF>, VEX_W;
2823 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2824 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2825 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2827 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2828 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2830 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2831 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2832 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2833 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2834 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2835 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2837 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2838 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2839 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2840 SSE_INTALU_ITINS_P, HasBWI, 1>;
2841 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2842 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2844 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2845 SSE_INTALU_ITINS_P, HasBWI, 1>;
2846 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2847 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2848 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2849 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2851 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2852 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2853 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2854 SSE_INTALU_ITINS_P, HasBWI, 1>;
2855 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2856 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2858 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2859 SSE_INTALU_ITINS_P, HasBWI, 1>;
2860 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2861 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2862 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2863 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2865 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2866 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2867 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2868 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2869 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2870 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2871 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2872 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2873 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2874 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2875 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2876 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2877 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2878 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2879 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2880 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2881 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2882 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2883 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2884 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2885 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2886 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2887 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2888 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2889 //===----------------------------------------------------------------------===//
2890 // AVX-512 - Unpack Instructions
2891 //===----------------------------------------------------------------------===//
2893 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2894 PatFrag mem_frag, RegisterClass RC,
2895 X86MemOperand x86memop, string asm,
2897 def rr : AVX512PI<opc, MRMSrcReg,
2898 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2900 (vt (OpNode RC:$src1, RC:$src2)))],
2902 def rm : AVX512PI<opc, MRMSrcMem,
2903 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2905 (vt (OpNode RC:$src1,
2906 (bitconvert (mem_frag addr:$src2)))))],
2910 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2911 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2912 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2913 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2914 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2915 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2916 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2917 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2918 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2919 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2920 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2921 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2923 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2924 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2925 X86MemOperand x86memop> {
2926 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2927 (ins RC:$src1, RC:$src2),
2928 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2929 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2930 IIC_SSE_UNPCK>, EVEX_4V;
2931 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2932 (ins RC:$src1, x86memop:$src2),
2933 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2934 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2935 (bitconvert (memop_frag addr:$src2)))))],
2936 IIC_SSE_UNPCK>, EVEX_4V;
2938 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2939 VR512, memopv16i32, i512mem>, EVEX_V512,
2940 EVEX_CD8<32, CD8VF>;
2941 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2942 VR512, memopv8i64, i512mem>, EVEX_V512,
2943 VEX_W, EVEX_CD8<64, CD8VF>;
2944 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2945 VR512, memopv16i32, i512mem>, EVEX_V512,
2946 EVEX_CD8<32, CD8VF>;
2947 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2948 VR512, memopv8i64, i512mem>, EVEX_V512,
2949 VEX_W, EVEX_CD8<64, CD8VF>;
2950 //===----------------------------------------------------------------------===//
2954 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2955 SDNode OpNode, PatFrag mem_frag,
2956 X86MemOperand x86memop, ValueType OpVT> {
2957 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2958 (ins RC:$src1, i8imm:$src2),
2959 !strconcat(OpcodeStr,
2960 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2962 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2964 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2965 (ins x86memop:$src1, i8imm:$src2),
2966 !strconcat(OpcodeStr,
2967 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2969 (OpVT (OpNode (mem_frag addr:$src1),
2970 (i8 imm:$src2))))]>, EVEX;
2973 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2974 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2976 //===----------------------------------------------------------------------===//
2977 // AVX-512 Logical Instructions
2978 //===----------------------------------------------------------------------===//
2980 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
2981 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2982 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
2983 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2984 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
2985 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2986 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
2987 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2989 //===----------------------------------------------------------------------===//
2990 // AVX-512 FP arithmetic
2991 //===----------------------------------------------------------------------===//
2993 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2995 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2996 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2997 EVEX_CD8<32, CD8VT1>;
2998 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2999 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3000 EVEX_CD8<64, CD8VT1>;
3003 let isCommutable = 1 in {
3004 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3005 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3006 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3007 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3009 let isCommutable = 0 in {
3010 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3011 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3014 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3015 X86VectorVTInfo _, bit IsCommutable> {
3016 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3017 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3018 "$src2, $src1", "$src1, $src2",
3019 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3020 let mayLoad = 1 in {
3021 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3022 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3023 "$src2, $src1", "$src1, $src2",
3024 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3025 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3026 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3027 "${src2}"##_.BroadcastStr##", $src1",
3028 "$src1, ${src2}"##_.BroadcastStr,
3029 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3030 (_.ScalarLdFrag addr:$src2))))>,
3035 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3036 bit IsCommutable = 0> {
3037 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3038 IsCommutable>, EVEX_V512, PS,
3039 EVEX_CD8<32, CD8VF>;
3040 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3041 IsCommutable>, EVEX_V512, PD, VEX_W,
3042 EVEX_CD8<64, CD8VF>;
3044 // Define only if AVX512VL feature is present.
3045 let Predicates = [HasVLX] in {
3046 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3047 IsCommutable>, EVEX_V128, PS,
3048 EVEX_CD8<32, CD8VF>;
3049 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3050 IsCommutable>, EVEX_V256, PS,
3051 EVEX_CD8<32, CD8VF>;
3052 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3053 IsCommutable>, EVEX_V128, PD, VEX_W,
3054 EVEX_CD8<64, CD8VF>;
3055 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3056 IsCommutable>, EVEX_V256, PD, VEX_W,
3057 EVEX_CD8<64, CD8VF>;
3061 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3062 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3063 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3064 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3065 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3066 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3068 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3069 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3070 (i16 -1), FROUND_CURRENT)),
3071 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3073 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3074 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3075 (i8 -1), FROUND_CURRENT)),
3076 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3078 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3079 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3080 (i16 -1), FROUND_CURRENT)),
3081 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3083 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3084 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3085 (i8 -1), FROUND_CURRENT)),
3086 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3087 //===----------------------------------------------------------------------===//
3088 // AVX-512 VPTESTM instructions
3089 //===----------------------------------------------------------------------===//
3091 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3092 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3093 SDNode OpNode, ValueType vt> {
3094 def rr : AVX512PI<opc, MRMSrcReg,
3095 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3096 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3097 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3098 SSEPackedInt>, EVEX_4V;
3099 def rm : AVX512PI<opc, MRMSrcMem,
3100 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3101 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3102 [(set KRC:$dst, (OpNode (vt RC:$src1),
3103 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3106 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3107 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3108 EVEX_CD8<32, CD8VF>;
3109 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3110 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3111 EVEX_CD8<64, CD8VF>;
3113 let Predicates = [HasCDI] in {
3114 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3115 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3116 EVEX_CD8<32, CD8VF>;
3117 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3118 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3119 EVEX_CD8<64, CD8VF>;
3122 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3123 (v16i32 VR512:$src2), (i16 -1))),
3124 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3126 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3127 (v8i64 VR512:$src2), (i8 -1))),
3128 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3129 //===----------------------------------------------------------------------===//
3130 // AVX-512 Shift instructions
3131 //===----------------------------------------------------------------------===//
3132 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3133 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3134 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3135 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3136 "$src2, $src1", "$src1, $src2",
3137 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3138 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3139 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3140 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3141 "$src2, $src1", "$src1, $src2",
3142 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3143 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3146 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3147 RegisterClass RC, ValueType vt, ValueType SrcVT,
3148 PatFrag bc_frag, RegisterClass KRC> {
3149 // src2 is always 128-bit
3150 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3151 (ins RC:$src1, VR128X:$src2),
3152 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3153 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3154 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3155 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3156 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3157 !strconcat(OpcodeStr,
3158 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3159 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3160 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3161 (ins RC:$src1, i128mem:$src2),
3162 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3163 [(set RC:$dst, (vt (OpNode RC:$src1,
3164 (bc_frag (memopv2i64 addr:$src2)))))],
3165 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3166 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3167 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3168 !strconcat(OpcodeStr,
3169 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3170 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3173 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3175 EVEX_V512, EVEX_CD8<32, CD8VF>;
3176 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3177 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3178 EVEX_CD8<32, CD8VQ>;
3180 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3181 v8i64_info>, EVEX_V512,
3182 EVEX_CD8<64, CD8VF>, VEX_W;
3183 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3184 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3185 EVEX_CD8<64, CD8VQ>, VEX_W;
3187 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3188 v16i32_info>, EVEX_V512,
3189 EVEX_CD8<32, CD8VF>;
3190 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3191 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3192 EVEX_CD8<32, CD8VQ>;
3194 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3195 v8i64_info>, EVEX_V512,
3196 EVEX_CD8<64, CD8VF>, VEX_W;
3197 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3198 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3199 EVEX_CD8<64, CD8VQ>, VEX_W;
3201 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3203 EVEX_V512, EVEX_CD8<32, CD8VF>;
3204 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3205 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3206 EVEX_CD8<32, CD8VQ>;
3208 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3209 v8i64_info>, EVEX_V512,
3210 EVEX_CD8<64, CD8VF>, VEX_W;
3211 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3212 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3213 EVEX_CD8<64, CD8VQ>, VEX_W;
3215 //===-------------------------------------------------------------------===//
3216 // Variable Bit Shifts
3217 //===-------------------------------------------------------------------===//
3218 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3219 RegisterClass RC, ValueType vt,
3220 X86MemOperand x86memop, PatFrag mem_frag> {
3221 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3222 (ins RC:$src1, RC:$src2),
3223 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3225 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3227 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3228 (ins RC:$src1, x86memop:$src2),
3229 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3231 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3235 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3236 i512mem, memopv16i32>, EVEX_V512,
3237 EVEX_CD8<32, CD8VF>;
3238 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3239 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3240 EVEX_CD8<64, CD8VF>;
3241 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3242 i512mem, memopv16i32>, EVEX_V512,
3243 EVEX_CD8<32, CD8VF>;
3244 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3245 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3246 EVEX_CD8<64, CD8VF>;
3247 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3248 i512mem, memopv16i32>, EVEX_V512,
3249 EVEX_CD8<32, CD8VF>;
3250 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3251 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3252 EVEX_CD8<64, CD8VF>;
3254 //===----------------------------------------------------------------------===//
3255 // AVX-512 - MOVDDUP
3256 //===----------------------------------------------------------------------===//
3258 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3259 X86MemOperand x86memop, PatFrag memop_frag> {
3260 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3261 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3262 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3263 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3264 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3266 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3269 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3270 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3271 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3272 (VMOVDDUPZrm addr:$src)>;
3274 //===---------------------------------------------------------------------===//
3275 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3276 //===---------------------------------------------------------------------===//
3277 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3278 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3279 X86MemOperand x86memop> {
3280 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3281 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3282 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3284 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3285 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3286 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3289 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3290 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3291 EVEX_CD8<32, CD8VF>;
3292 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3293 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3294 EVEX_CD8<32, CD8VF>;
3296 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3297 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3298 (VMOVSHDUPZrm addr:$src)>;
3299 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3300 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3301 (VMOVSLDUPZrm addr:$src)>;
3303 //===----------------------------------------------------------------------===//
3304 // Move Low to High and High to Low packed FP Instructions
3305 //===----------------------------------------------------------------------===//
3306 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3307 (ins VR128X:$src1, VR128X:$src2),
3308 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3309 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3310 IIC_SSE_MOV_LH>, EVEX_4V;
3311 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3312 (ins VR128X:$src1, VR128X:$src2),
3313 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3314 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3315 IIC_SSE_MOV_LH>, EVEX_4V;
3317 let Predicates = [HasAVX512] in {
3319 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3320 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3321 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3322 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3325 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3326 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3329 //===----------------------------------------------------------------------===//
3330 // FMA - Fused Multiply Operations
3333 let Constraints = "$src1 = $dst" in {
3334 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3335 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3336 SDPatternOperator OpNode = null_frag> {
3337 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3338 (ins _.RC:$src2, _.RC:$src3),
3339 OpcodeStr, "$src3, $src2", "$src2, $src3",
3340 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3344 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3345 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3346 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3347 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3348 (_.MemOpFrag addr:$src3))))]>;
3349 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3350 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3351 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3352 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3353 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3354 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3356 } // Constraints = "$src1 = $dst"
3358 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3359 string OpcodeStr, X86VectorVTInfo VTI,
3360 SDPatternOperator OpNode> {
3361 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3363 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3365 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3367 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3370 let ExeDomain = SSEPackedSingle in {
3371 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3372 v16f32_info, X86Fmadd>;
3373 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3374 v16f32_info, X86Fmsub>;
3375 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3376 v16f32_info, X86Fmaddsub>;
3377 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3378 v16f32_info, X86Fmsubadd>;
3379 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3380 v16f32_info, X86Fnmadd>;
3381 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3382 v16f32_info, X86Fnmsub>;
3384 let ExeDomain = SSEPackedDouble in {
3385 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3386 v8f64_info, X86Fmadd>, VEX_W;
3387 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3388 v8f64_info, X86Fmsub>, VEX_W;
3389 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3390 v8f64_info, X86Fmaddsub>, VEX_W;
3391 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3392 v8f64_info, X86Fmsubadd>, VEX_W;
3393 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3394 v8f64_info, X86Fnmadd>, VEX_W;
3395 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3396 v8f64_info, X86Fnmsub>, VEX_W;
3399 let Constraints = "$src1 = $dst" in {
3400 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3401 X86VectorVTInfo _> {
3403 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3404 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3405 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3406 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3408 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3409 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3410 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3411 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3413 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3414 (_.ScalarLdFrag addr:$src2))),
3415 _.RC:$src3))]>, EVEX_B;
3417 } // Constraints = "$src1 = $dst"
3420 let ExeDomain = SSEPackedSingle in {
3421 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3423 EVEX_V512, EVEX_CD8<32, CD8VF>;
3424 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3426 EVEX_V512, EVEX_CD8<32, CD8VF>;
3427 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3429 EVEX_V512, EVEX_CD8<32, CD8VF>;
3430 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3432 EVEX_V512, EVEX_CD8<32, CD8VF>;
3433 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3435 EVEX_V512, EVEX_CD8<32, CD8VF>;
3436 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3438 EVEX_V512, EVEX_CD8<32, CD8VF>;
3440 let ExeDomain = SSEPackedDouble in {
3441 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3443 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3444 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3446 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3447 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3449 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3450 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3452 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3453 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3455 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3456 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3458 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3462 let Constraints = "$src1 = $dst" in {
3463 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3464 RegisterClass RC, ValueType OpVT,
3465 X86MemOperand x86memop, Operand memop,
3467 let isCommutable = 1 in
3468 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3469 (ins RC:$src1, RC:$src2, RC:$src3),
3470 !strconcat(OpcodeStr,
3471 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3473 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3475 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3476 (ins RC:$src1, RC:$src2, f128mem:$src3),
3477 !strconcat(OpcodeStr,
3478 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3480 (OpVT (OpNode RC:$src2, RC:$src1,
3481 (mem_frag addr:$src3))))]>;
3484 } // Constraints = "$src1 = $dst"
3486 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3487 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3488 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3489 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3490 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3491 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3492 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3493 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3494 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3495 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3496 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3497 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3498 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3499 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3500 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3501 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3503 //===----------------------------------------------------------------------===//
3504 // AVX-512 Scalar convert from sign integer to float/double
3505 //===----------------------------------------------------------------------===//
3507 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3508 X86MemOperand x86memop, string asm> {
3509 let hasSideEffects = 0 in {
3510 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3511 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3514 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3515 (ins DstRC:$src1, x86memop:$src),
3516 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3518 } // hasSideEffects = 0
3520 let Predicates = [HasAVX512] in {
3521 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3522 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3523 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3524 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3525 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3526 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3527 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3528 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3530 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3531 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3532 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3533 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3534 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3535 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3536 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3537 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3539 def : Pat<(f32 (sint_to_fp GR32:$src)),
3540 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3541 def : Pat<(f32 (sint_to_fp GR64:$src)),
3542 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3543 def : Pat<(f64 (sint_to_fp GR32:$src)),
3544 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3545 def : Pat<(f64 (sint_to_fp GR64:$src)),
3546 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3548 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3549 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3550 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3551 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3552 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3553 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3554 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3555 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3557 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3558 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3559 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3560 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3561 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3562 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3563 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3564 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3566 def : Pat<(f32 (uint_to_fp GR32:$src)),
3567 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3568 def : Pat<(f32 (uint_to_fp GR64:$src)),
3569 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3570 def : Pat<(f64 (uint_to_fp GR32:$src)),
3571 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3572 def : Pat<(f64 (uint_to_fp GR64:$src)),
3573 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3576 //===----------------------------------------------------------------------===//
3577 // AVX-512 Scalar convert from float/double to integer
3578 //===----------------------------------------------------------------------===//
3579 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3580 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3582 let hasSideEffects = 0 in {
3583 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3584 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3585 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3586 Requires<[HasAVX512]>;
3588 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3589 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3590 Requires<[HasAVX512]>;
3591 } // hasSideEffects = 0
3593 let Predicates = [HasAVX512] in {
3594 // Convert float/double to signed/unsigned int 32/64
3595 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3596 ssmem, sse_load_f32, "cvtss2si">,
3597 XS, EVEX_CD8<32, CD8VT1>;
3598 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3599 ssmem, sse_load_f32, "cvtss2si">,
3600 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3601 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3602 ssmem, sse_load_f32, "cvtss2usi">,
3603 XS, EVEX_CD8<32, CD8VT1>;
3604 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3605 int_x86_avx512_cvtss2usi64, ssmem,
3606 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3607 EVEX_CD8<32, CD8VT1>;
3608 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3609 sdmem, sse_load_f64, "cvtsd2si">,
3610 XD, EVEX_CD8<64, CD8VT1>;
3611 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3612 sdmem, sse_load_f64, "cvtsd2si">,
3613 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3614 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3615 sdmem, sse_load_f64, "cvtsd2usi">,
3616 XD, EVEX_CD8<64, CD8VT1>;
3617 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3618 int_x86_avx512_cvtsd2usi64, sdmem,
3619 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3620 EVEX_CD8<64, CD8VT1>;
3622 let isCodeGenOnly = 1 in {
3623 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3624 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3625 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3626 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3627 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3628 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3629 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3630 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3631 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3632 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3633 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3634 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3636 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3637 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3638 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3639 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3640 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3641 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3642 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3643 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3644 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3645 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3646 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3647 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3648 } // isCodeGenOnly = 1
3650 // Convert float/double to signed/unsigned int 32/64 with truncation
3651 let isCodeGenOnly = 1 in {
3652 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3653 ssmem, sse_load_f32, "cvttss2si">,
3654 XS, EVEX_CD8<32, CD8VT1>;
3655 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3656 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3657 "cvttss2si">, XS, VEX_W,
3658 EVEX_CD8<32, CD8VT1>;
3659 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3660 sdmem, sse_load_f64, "cvttsd2si">, XD,
3661 EVEX_CD8<64, CD8VT1>;
3662 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3663 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3664 "cvttsd2si">, XD, VEX_W,
3665 EVEX_CD8<64, CD8VT1>;
3666 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3667 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3668 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3669 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3670 int_x86_avx512_cvttss2usi64, ssmem,
3671 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3672 EVEX_CD8<32, CD8VT1>;
3673 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3674 int_x86_avx512_cvttsd2usi,
3675 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3676 EVEX_CD8<64, CD8VT1>;
3677 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3678 int_x86_avx512_cvttsd2usi64, sdmem,
3679 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3680 EVEX_CD8<64, CD8VT1>;
3681 } // isCodeGenOnly = 1
3683 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3684 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3686 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3687 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3688 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3689 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3690 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3691 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3694 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3695 loadf32, "cvttss2si">, XS,
3696 EVEX_CD8<32, CD8VT1>;
3697 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3698 loadf32, "cvttss2usi">, XS,
3699 EVEX_CD8<32, CD8VT1>;
3700 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3701 loadf32, "cvttss2si">, XS, VEX_W,
3702 EVEX_CD8<32, CD8VT1>;
3703 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3704 loadf32, "cvttss2usi">, XS, VEX_W,
3705 EVEX_CD8<32, CD8VT1>;
3706 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3707 loadf64, "cvttsd2si">, XD,
3708 EVEX_CD8<64, CD8VT1>;
3709 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3710 loadf64, "cvttsd2usi">, XD,
3711 EVEX_CD8<64, CD8VT1>;
3712 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3713 loadf64, "cvttsd2si">, XD, VEX_W,
3714 EVEX_CD8<64, CD8VT1>;
3715 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3716 loadf64, "cvttsd2usi">, XD, VEX_W,
3717 EVEX_CD8<64, CD8VT1>;
3719 //===----------------------------------------------------------------------===//
3720 // AVX-512 Convert form float to double and back
3721 //===----------------------------------------------------------------------===//
3722 let hasSideEffects = 0 in {
3723 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3724 (ins FR32X:$src1, FR32X:$src2),
3725 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3726 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3728 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3729 (ins FR32X:$src1, f32mem:$src2),
3730 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3731 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3732 EVEX_CD8<32, CD8VT1>;
3734 // Convert scalar double to scalar single
3735 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3736 (ins FR64X:$src1, FR64X:$src2),
3737 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3738 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3740 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3741 (ins FR64X:$src1, f64mem:$src2),
3742 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3743 []>, EVEX_4V, VEX_LIG, VEX_W,
3744 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3747 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3748 Requires<[HasAVX512]>;
3749 def : Pat<(fextend (loadf32 addr:$src)),
3750 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3752 def : Pat<(extloadf32 addr:$src),
3753 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3754 Requires<[HasAVX512, OptForSize]>;
3756 def : Pat<(extloadf32 addr:$src),
3757 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3758 Requires<[HasAVX512, OptForSpeed]>;
3760 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3761 Requires<[HasAVX512]>;
3763 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3764 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3765 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3767 let hasSideEffects = 0 in {
3768 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3769 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3771 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3772 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3773 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3774 [], d>, EVEX, EVEX_B, EVEX_RC;
3776 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3777 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3779 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3780 } // hasSideEffects = 0
3783 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3784 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3785 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3787 let hasSideEffects = 0 in {
3788 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3789 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3791 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3793 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3794 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3796 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3797 } // hasSideEffects = 0
3800 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3801 memopv8f64, f512mem, v8f32, v8f64,
3802 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3803 EVEX_CD8<64, CD8VF>;
3805 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3806 memopv4f64, f256mem, v8f64, v8f32,
3807 SSEPackedDouble>, EVEX_V512, PS,
3808 EVEX_CD8<32, CD8VH>;
3809 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3810 (VCVTPS2PDZrm addr:$src)>;
3812 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3813 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3814 (VCVTPD2PSZrr VR512:$src)>;
3816 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3817 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3818 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3820 //===----------------------------------------------------------------------===//
3821 // AVX-512 Vector convert from sign integer to float/double
3822 //===----------------------------------------------------------------------===//
3824 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3825 memopv8i64, i512mem, v16f32, v16i32,
3826 SSEPackedSingle>, EVEX_V512, PS,
3827 EVEX_CD8<32, CD8VF>;
3829 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3830 memopv4i64, i256mem, v8f64, v8i32,
3831 SSEPackedDouble>, EVEX_V512, XS,
3832 EVEX_CD8<32, CD8VH>;
3834 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3835 memopv16f32, f512mem, v16i32, v16f32,
3836 SSEPackedSingle>, EVEX_V512, XS,
3837 EVEX_CD8<32, CD8VF>;
3839 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3840 memopv8f64, f512mem, v8i32, v8f64,
3841 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3842 EVEX_CD8<64, CD8VF>;
3844 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3845 memopv16f32, f512mem, v16i32, v16f32,
3846 SSEPackedSingle>, EVEX_V512, PS,
3847 EVEX_CD8<32, CD8VF>;
3849 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3850 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3851 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3852 (VCVTTPS2UDQZrr VR512:$src)>;
3854 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3855 memopv8f64, f512mem, v8i32, v8f64,
3856 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3857 EVEX_CD8<64, CD8VF>;
3859 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3860 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3861 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3862 (VCVTTPD2UDQZrr VR512:$src)>;
3864 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3865 memopv4i64, f256mem, v8f64, v8i32,
3866 SSEPackedDouble>, EVEX_V512, XS,
3867 EVEX_CD8<32, CD8VH>;
3869 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3870 memopv16i32, f512mem, v16f32, v16i32,
3871 SSEPackedSingle>, EVEX_V512, XD,
3872 EVEX_CD8<32, CD8VF>;
3874 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3875 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3876 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3878 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3879 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3880 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3882 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3883 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3884 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3886 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3887 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3888 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3890 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3891 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3892 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3894 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3895 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3896 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3897 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3898 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3899 (VCVTDQ2PDZrr VR256X:$src)>;
3900 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3901 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3902 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3903 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3904 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3905 (VCVTUDQ2PDZrr VR256X:$src)>;
3907 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3908 RegisterClass DstRC, PatFrag mem_frag,
3909 X86MemOperand x86memop, Domain d> {
3910 let hasSideEffects = 0 in {
3911 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3912 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3914 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3915 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3916 [], d>, EVEX, EVEX_B, EVEX_RC;
3918 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3919 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3921 } // hasSideEffects = 0
3924 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3925 memopv16f32, f512mem, SSEPackedSingle>, PD,
3926 EVEX_V512, EVEX_CD8<32, CD8VF>;
3927 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3928 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3929 EVEX_V512, EVEX_CD8<64, CD8VF>;
3931 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3932 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3933 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3935 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3936 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3937 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3939 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3940 memopv16f32, f512mem, SSEPackedSingle>,
3941 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3942 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3943 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3944 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3946 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3947 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3948 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3950 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3951 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3952 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3954 let Predicates = [HasAVX512] in {
3955 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3956 (VCVTPD2PSZrm addr:$src)>;
3957 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3958 (VCVTPS2PDZrm addr:$src)>;
3961 //===----------------------------------------------------------------------===//
3962 // Half precision conversion instructions
3963 //===----------------------------------------------------------------------===//
3964 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3965 X86MemOperand x86memop> {
3966 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3967 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3969 let hasSideEffects = 0, mayLoad = 1 in
3970 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3971 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3974 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3975 X86MemOperand x86memop> {
3976 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3977 (ins srcRC:$src1, i32i8imm:$src2),
3978 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3980 let hasSideEffects = 0, mayStore = 1 in
3981 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3982 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3983 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3986 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3987 EVEX_CD8<32, CD8VH>;
3988 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3989 EVEX_CD8<32, CD8VH>;
3991 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3992 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3993 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3995 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3996 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3997 (VCVTPH2PSZrr VR256X:$src)>;
3999 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4000 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4001 "ucomiss">, PS, EVEX, VEX_LIG,
4002 EVEX_CD8<32, CD8VT1>;
4003 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4004 "ucomisd">, PD, EVEX,
4005 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4006 let Pattern = []<dag> in {
4007 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4008 "comiss">, PS, EVEX, VEX_LIG,
4009 EVEX_CD8<32, CD8VT1>;
4010 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4011 "comisd">, PD, EVEX,
4012 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4014 let isCodeGenOnly = 1 in {
4015 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4016 load, "ucomiss">, PS, EVEX, VEX_LIG,
4017 EVEX_CD8<32, CD8VT1>;
4018 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4019 load, "ucomisd">, PD, EVEX,
4020 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4022 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4023 load, "comiss">, PS, EVEX, VEX_LIG,
4024 EVEX_CD8<32, CD8VT1>;
4025 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4026 load, "comisd">, PD, EVEX,
4027 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4031 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4032 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4033 X86MemOperand x86memop> {
4034 let hasSideEffects = 0 in {
4035 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4036 (ins RC:$src1, RC:$src2),
4037 !strconcat(OpcodeStr,
4038 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4039 let mayLoad = 1 in {
4040 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4041 (ins RC:$src1, x86memop:$src2),
4042 !strconcat(OpcodeStr,
4043 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4048 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4049 EVEX_CD8<32, CD8VT1>;
4050 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4051 VEX_W, EVEX_CD8<64, CD8VT1>;
4052 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4053 EVEX_CD8<32, CD8VT1>;
4054 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4055 VEX_W, EVEX_CD8<64, CD8VT1>;
4057 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4058 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4059 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4060 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4062 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4063 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4064 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4065 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4067 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4068 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4069 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4070 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4072 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4073 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4074 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4075 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4077 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4078 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4079 X86VectorVTInfo _> {
4080 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4081 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4082 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4083 let mayLoad = 1 in {
4084 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4085 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4087 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4088 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4089 (ins _.ScalarMemOp:$src), OpcodeStr,
4090 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4092 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4097 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4098 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4099 EVEX_V512, EVEX_CD8<32, CD8VF>;
4100 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4101 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4103 // Define only if AVX512VL feature is present.
4104 let Predicates = [HasVLX] in {
4105 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4106 OpNode, v4f32x_info>,
4107 EVEX_V128, EVEX_CD8<32, CD8VF>;
4108 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4109 OpNode, v8f32x_info>,
4110 EVEX_V256, EVEX_CD8<32, CD8VF>;
4111 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4112 OpNode, v2f64x_info>,
4113 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4114 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4115 OpNode, v4f64x_info>,
4116 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4120 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4121 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4123 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4124 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4125 (VRSQRT14PSZr VR512:$src)>;
4126 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4127 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4128 (VRSQRT14PDZr VR512:$src)>;
4130 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4131 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4132 (VRCP14PSZr VR512:$src)>;
4133 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4134 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4135 (VRCP14PDZr VR512:$src)>;
4137 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4138 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4139 X86MemOperand x86memop> {
4140 let hasSideEffects = 0, Predicates = [HasERI] in {
4141 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4142 (ins RC:$src1, RC:$src2),
4143 !strconcat(OpcodeStr,
4144 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4145 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4146 (ins RC:$src1, RC:$src2),
4147 !strconcat(OpcodeStr,
4148 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
4149 []>, EVEX_4V, EVEX_B;
4150 let mayLoad = 1 in {
4151 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4152 (ins RC:$src1, x86memop:$src2),
4153 !strconcat(OpcodeStr,
4154 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4159 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4160 EVEX_CD8<32, CD8VT1>;
4161 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4162 VEX_W, EVEX_CD8<64, CD8VT1>;
4163 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4164 EVEX_CD8<32, CD8VT1>;
4165 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4166 VEX_W, EVEX_CD8<64, CD8VT1>;
4168 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4169 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4171 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4172 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4174 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4175 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4177 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4178 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4180 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4181 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4183 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4184 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4186 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4187 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4189 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4190 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4192 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4194 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4197 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4198 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4199 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4201 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4202 (ins _.RC:$src), OpcodeStr,
4204 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4206 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4207 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4209 (bitconvert (_.LdFrag addr:$src))), (i32 FROUND_CURRENT))>;
4211 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4212 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4214 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4215 (i32 FROUND_CURRENT))>, EVEX_B;
4218 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4219 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4220 EVEX_CD8<32, CD8VF>;
4221 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4222 VEX_W, EVEX_CD8<32, CD8VF>;
4225 let Predicates = [HasERI], hasSideEffects = 0 in {
4227 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4228 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4229 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4232 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4233 SDNode OpNode, X86VectorVTInfo _>{
4234 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4235 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4236 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4237 let mayLoad = 1 in {
4238 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4239 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4241 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4243 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4244 (ins _.ScalarMemOp:$src), OpcodeStr,
4245 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4247 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4252 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4253 Intrinsic F32Int, Intrinsic F64Int,
4254 OpndItins itins_s, OpndItins itins_d> {
4255 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4256 (ins FR32X:$src1, FR32X:$src2),
4257 !strconcat(OpcodeStr,
4258 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4259 [], itins_s.rr>, XS, EVEX_4V;
4260 let isCodeGenOnly = 1 in
4261 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4262 (ins VR128X:$src1, VR128X:$src2),
4263 !strconcat(OpcodeStr,
4264 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4266 (F32Int VR128X:$src1, VR128X:$src2))],
4267 itins_s.rr>, XS, EVEX_4V;
4268 let mayLoad = 1 in {
4269 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4270 (ins FR32X:$src1, f32mem:$src2),
4271 !strconcat(OpcodeStr,
4272 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4273 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4274 let isCodeGenOnly = 1 in
4275 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4276 (ins VR128X:$src1, ssmem:$src2),
4277 !strconcat(OpcodeStr,
4278 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4280 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4281 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4283 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4284 (ins FR64X:$src1, FR64X:$src2),
4285 !strconcat(OpcodeStr,
4286 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4288 let isCodeGenOnly = 1 in
4289 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4290 (ins VR128X:$src1, VR128X:$src2),
4291 !strconcat(OpcodeStr,
4292 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4294 (F64Int VR128X:$src1, VR128X:$src2))],
4295 itins_s.rr>, XD, EVEX_4V, VEX_W;
4296 let mayLoad = 1 in {
4297 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4298 (ins FR64X:$src1, f64mem:$src2),
4299 !strconcat(OpcodeStr,
4300 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4301 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4302 let isCodeGenOnly = 1 in
4303 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4304 (ins VR128X:$src1, sdmem:$src2),
4305 !strconcat(OpcodeStr,
4306 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4308 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4309 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4313 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4315 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4317 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4318 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4320 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4321 // Define only if AVX512VL feature is present.
4322 let Predicates = [HasVLX] in {
4323 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4324 OpNode, v4f32x_info>,
4325 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4326 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4327 OpNode, v8f32x_info>,
4328 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4329 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4330 OpNode, v2f64x_info>,
4331 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4332 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4333 OpNode, v4f64x_info>,
4334 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4338 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4340 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4341 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4342 SSE_SQRTSS, SSE_SQRTSD>;
4344 let Predicates = [HasAVX512] in {
4345 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4346 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4347 (VSQRTPSZr VR512:$src1)>;
4348 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4349 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4350 (VSQRTPDZr VR512:$src1)>;
4352 def : Pat<(f32 (fsqrt FR32X:$src)),
4353 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4354 def : Pat<(f32 (fsqrt (load addr:$src))),
4355 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4356 Requires<[OptForSize]>;
4357 def : Pat<(f64 (fsqrt FR64X:$src)),
4358 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4359 def : Pat<(f64 (fsqrt (load addr:$src))),
4360 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4361 Requires<[OptForSize]>;
4363 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4364 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4365 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4366 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4367 Requires<[OptForSize]>;
4369 def : Pat<(f32 (X86frcp FR32X:$src)),
4370 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4371 def : Pat<(f32 (X86frcp (load addr:$src))),
4372 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4373 Requires<[OptForSize]>;
4375 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4376 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4377 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4379 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4380 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4382 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4383 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4384 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4386 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4387 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4391 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4392 X86MemOperand x86memop, RegisterClass RC,
4393 PatFrag mem_frag32, PatFrag mem_frag64,
4394 Intrinsic V4F32Int, Intrinsic V2F64Int,
4396 let ExeDomain = SSEPackedSingle in {
4397 // Intrinsic operation, reg.
4398 // Vector intrinsic operation, reg
4399 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4400 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4401 !strconcat(OpcodeStr,
4402 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4403 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4405 // Vector intrinsic operation, mem
4406 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4407 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4408 !strconcat(OpcodeStr,
4409 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4411 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4412 EVEX_CD8<32, VForm>;
4413 } // ExeDomain = SSEPackedSingle
4415 let ExeDomain = SSEPackedDouble in {
4416 // Vector intrinsic operation, reg
4417 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4418 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4419 !strconcat(OpcodeStr,
4420 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4421 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4423 // Vector intrinsic operation, mem
4424 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4425 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4426 !strconcat(OpcodeStr,
4427 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4429 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4430 EVEX_CD8<64, VForm>;
4431 } // ExeDomain = SSEPackedDouble
4434 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4438 let ExeDomain = GenericDomain in {
4440 let hasSideEffects = 0 in
4441 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4442 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4443 !strconcat(OpcodeStr,
4444 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4447 // Intrinsic operation, reg.
4448 let isCodeGenOnly = 1 in
4449 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4450 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4451 !strconcat(OpcodeStr,
4452 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4453 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4455 // Intrinsic operation, mem.
4456 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4457 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4458 !strconcat(OpcodeStr,
4459 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4460 [(set VR128X:$dst, (F32Int VR128X:$src1,
4461 sse_load_f32:$src2, imm:$src3))]>,
4462 EVEX_CD8<32, CD8VT1>;
4465 let hasSideEffects = 0 in
4466 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4467 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4468 !strconcat(OpcodeStr,
4469 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4472 // Intrinsic operation, reg.
4473 let isCodeGenOnly = 1 in
4474 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4475 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4476 !strconcat(OpcodeStr,
4477 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4478 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4481 // Intrinsic operation, mem.
4482 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4483 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4484 !strconcat(OpcodeStr,
4485 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4487 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4488 VEX_W, EVEX_CD8<64, CD8VT1>;
4489 } // ExeDomain = GenericDomain
4492 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4493 X86MemOperand x86memop, RegisterClass RC,
4494 PatFrag mem_frag, Domain d> {
4495 let ExeDomain = d in {
4496 // Intrinsic operation, reg.
4497 // Vector intrinsic operation, reg
4498 def r : AVX512AIi8<opc, MRMSrcReg,
4499 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4500 !strconcat(OpcodeStr,
4501 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4504 // Vector intrinsic operation, mem
4505 def m : AVX512AIi8<opc, MRMSrcMem,
4506 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4507 !strconcat(OpcodeStr,
4508 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4514 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4515 memopv16f32, SSEPackedSingle>, EVEX_V512,
4516 EVEX_CD8<32, CD8VF>;
4518 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4519 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4521 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4524 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4525 memopv8f64, SSEPackedDouble>, EVEX_V512,
4526 VEX_W, EVEX_CD8<64, CD8VF>;
4528 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4529 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4531 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4533 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4534 Operand x86memop, RegisterClass RC, Domain d> {
4535 let ExeDomain = d in {
4536 def r : AVX512AIi8<opc, MRMSrcReg,
4537 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4538 !strconcat(OpcodeStr,
4539 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4542 def m : AVX512AIi8<opc, MRMSrcMem,
4543 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4544 !strconcat(OpcodeStr,
4545 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4550 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4551 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4553 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4554 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4556 def : Pat<(ffloor FR32X:$src),
4557 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4558 def : Pat<(f64 (ffloor FR64X:$src)),
4559 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4560 def : Pat<(f32 (fnearbyint FR32X:$src)),
4561 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4562 def : Pat<(f64 (fnearbyint FR64X:$src)),
4563 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4564 def : Pat<(f32 (fceil FR32X:$src)),
4565 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4566 def : Pat<(f64 (fceil FR64X:$src)),
4567 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4568 def : Pat<(f32 (frint FR32X:$src)),
4569 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4570 def : Pat<(f64 (frint FR64X:$src)),
4571 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4572 def : Pat<(f32 (ftrunc FR32X:$src)),
4573 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4574 def : Pat<(f64 (ftrunc FR64X:$src)),
4575 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4577 def : Pat<(v16f32 (ffloor VR512:$src)),
4578 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4579 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4580 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4581 def : Pat<(v16f32 (fceil VR512:$src)),
4582 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4583 def : Pat<(v16f32 (frint VR512:$src)),
4584 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4585 def : Pat<(v16f32 (ftrunc VR512:$src)),
4586 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4588 def : Pat<(v8f64 (ffloor VR512:$src)),
4589 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4590 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4591 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4592 def : Pat<(v8f64 (fceil VR512:$src)),
4593 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4594 def : Pat<(v8f64 (frint VR512:$src)),
4595 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4596 def : Pat<(v8f64 (ftrunc VR512:$src)),
4597 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4599 //-------------------------------------------------
4600 // Integer truncate and extend operations
4601 //-------------------------------------------------
4603 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4604 RegisterClass dstRC, RegisterClass srcRC,
4605 RegisterClass KRC, X86MemOperand x86memop> {
4606 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4608 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4611 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4612 (ins KRC:$mask, srcRC:$src),
4613 !strconcat(OpcodeStr,
4614 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4617 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4618 (ins KRC:$mask, srcRC:$src),
4619 !strconcat(OpcodeStr,
4620 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4623 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4624 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4627 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4628 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4629 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4633 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4634 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4635 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4636 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4637 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4638 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4639 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4640 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4641 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4642 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4643 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4644 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4645 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4646 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4647 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4648 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4649 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4650 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4651 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4652 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4653 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4654 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4655 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4656 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4657 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4658 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4659 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4660 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4661 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4662 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4664 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4665 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4666 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4667 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4668 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4670 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4671 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4672 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4673 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4674 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4675 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4676 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4677 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4680 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4681 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4682 PatFrag mem_frag, X86MemOperand x86memop,
4683 ValueType OpVT, ValueType InVT> {
4685 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4687 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4688 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4690 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4691 (ins KRC:$mask, SrcRC:$src),
4692 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4695 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4696 (ins KRC:$mask, SrcRC:$src),
4697 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4700 let mayLoad = 1 in {
4701 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4702 (ins x86memop:$src),
4703 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4705 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4708 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4709 (ins KRC:$mask, x86memop:$src),
4710 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4714 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4715 (ins KRC:$mask, x86memop:$src),
4716 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4722 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4723 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4725 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4726 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4728 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4729 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4730 EVEX_CD8<16, CD8VH>;
4731 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4732 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4733 EVEX_CD8<16, CD8VQ>;
4734 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4735 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4736 EVEX_CD8<32, CD8VH>;
4738 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4739 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4741 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4742 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4744 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4745 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4746 EVEX_CD8<16, CD8VH>;
4747 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4748 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4749 EVEX_CD8<16, CD8VQ>;
4750 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4751 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4752 EVEX_CD8<32, CD8VH>;
4754 //===----------------------------------------------------------------------===//
4755 // GATHER - SCATTER Operations
4757 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4758 RegisterClass RC, X86MemOperand memop> {
4760 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4761 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4762 (ins RC:$src1, KRC:$mask, memop:$src2),
4763 !strconcat(OpcodeStr,
4764 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4768 let ExeDomain = SSEPackedDouble in {
4769 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4770 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4771 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4772 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4775 let ExeDomain = SSEPackedSingle in {
4776 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4777 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4778 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4779 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4782 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4783 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4784 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4785 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4787 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4788 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4789 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4790 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4792 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4793 RegisterClass RC, X86MemOperand memop> {
4794 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4795 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4796 (ins memop:$dst, KRC:$mask, RC:$src2),
4797 !strconcat(OpcodeStr,
4798 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4802 let ExeDomain = SSEPackedDouble in {
4803 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4804 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4805 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4806 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4809 let ExeDomain = SSEPackedSingle in {
4810 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4811 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4812 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4813 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4816 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4817 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4818 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4819 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4821 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4822 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4823 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4824 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4827 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4828 RegisterClass KRC, X86MemOperand memop> {
4829 let Predicates = [HasPFI], hasSideEffects = 1 in
4830 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4831 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4835 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4836 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4838 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4839 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4841 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4842 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4844 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4845 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4847 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4848 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4850 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4851 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4853 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4854 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4856 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4857 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4859 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4860 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4862 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4863 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4865 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4866 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4868 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4869 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4871 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4872 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4874 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4875 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4877 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4878 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4880 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4881 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4882 //===----------------------------------------------------------------------===//
4883 // VSHUFPS - VSHUFPD Operations
4885 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4886 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4888 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4889 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4890 !strconcat(OpcodeStr,
4891 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4892 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4893 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4894 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4895 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4896 (ins RC:$src1, RC:$src2, i8imm:$src3),
4897 !strconcat(OpcodeStr,
4898 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4899 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4900 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4901 EVEX_4V, Sched<[WriteShuffle]>;
4904 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4905 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4906 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4907 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4909 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4910 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4911 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4912 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4913 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4915 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4916 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4917 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4918 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4919 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4921 multiclass avx512_valign<X86VectorVTInfo _> {
4922 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4923 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4925 "$src3, $src2, $src1", "$src1, $src2, $src3",
4926 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
4928 AVX512AIi8Base, EVEX_4V;
4930 // Also match valign of packed floats.
4931 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4932 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
4935 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4936 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4937 !strconcat("valign"##_.Suffix,
4938 " \t{$src3, $src2, $src1, $dst|"
4939 "$dst, $src1, $src2, $src3}"),
4942 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4943 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4945 // Helper fragments to match sext vXi1 to vXiY.
4946 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4947 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4949 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4950 RegisterClass KRC, RegisterClass RC,
4951 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4953 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4954 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4956 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4957 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4959 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4960 !strconcat(OpcodeStr,
4961 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4963 let mayLoad = 1 in {
4964 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4965 (ins x86memop:$src),
4966 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4968 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4969 (ins KRC:$mask, x86memop:$src),
4970 !strconcat(OpcodeStr,
4971 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4973 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4974 (ins KRC:$mask, x86memop:$src),
4975 !strconcat(OpcodeStr,
4976 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4978 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4979 (ins x86scalar_mop:$src),
4980 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4981 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4983 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4984 (ins KRC:$mask, x86scalar_mop:$src),
4985 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4986 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4987 []>, EVEX, EVEX_B, EVEX_K;
4988 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4989 (ins KRC:$mask, x86scalar_mop:$src),
4990 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4991 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4993 []>, EVEX, EVEX_B, EVEX_KZ;
4997 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4998 i512mem, i32mem, "{1to16}">, EVEX_V512,
4999 EVEX_CD8<32, CD8VF>;
5000 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5001 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5002 EVEX_CD8<64, CD8VF>;
5005 (bc_v16i32 (v16i1sextv16i32)),
5006 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5007 (VPABSDZrr VR512:$src)>;
5009 (bc_v8i64 (v8i1sextv8i64)),
5010 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5011 (VPABSQZrr VR512:$src)>;
5013 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5014 (v16i32 immAllZerosV), (i16 -1))),
5015 (VPABSDZrr VR512:$src)>;
5016 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5017 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5018 (VPABSQZrr VR512:$src)>;
5020 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5021 RegisterClass RC, RegisterClass KRC,
5022 X86MemOperand x86memop,
5023 X86MemOperand x86scalar_mop, string BrdcstStr> {
5024 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5026 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
5028 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5029 (ins x86memop:$src),
5030 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
5032 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5033 (ins x86scalar_mop:$src),
5034 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5035 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5037 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5038 (ins KRC:$mask, RC:$src),
5039 !strconcat(OpcodeStr,
5040 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5042 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5043 (ins KRC:$mask, x86memop:$src),
5044 !strconcat(OpcodeStr,
5045 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5047 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5048 (ins KRC:$mask, x86scalar_mop:$src),
5049 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
5050 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5052 []>, EVEX, EVEX_KZ, EVEX_B;
5054 let Constraints = "$src1 = $dst" in {
5055 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5056 (ins RC:$src1, KRC:$mask, RC:$src2),
5057 !strconcat(OpcodeStr,
5058 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5060 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5061 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5062 !strconcat(OpcodeStr,
5063 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5065 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5066 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5067 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
5068 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5069 []>, EVEX, EVEX_K, EVEX_B;
5073 let Predicates = [HasCDI] in {
5074 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5075 i512mem, i32mem, "{1to16}">,
5076 EVEX_V512, EVEX_CD8<32, CD8VF>;
5079 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5080 i512mem, i64mem, "{1to8}">,
5081 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5085 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5087 (VPCONFLICTDrrk VR512:$src1,
5088 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5090 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5092 (VPCONFLICTQrrk VR512:$src1,
5093 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5095 let Predicates = [HasCDI] in {
5096 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5097 i512mem, i32mem, "{1to16}">,
5098 EVEX_V512, EVEX_CD8<32, CD8VF>;
5101 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5102 i512mem, i64mem, "{1to8}">,
5103 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5107 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5109 (VPLZCNTDrrk VR512:$src1,
5110 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5112 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5114 (VPLZCNTQrrk VR512:$src1,
5115 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5117 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5118 (VPLZCNTDrm addr:$src)>;
5119 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5120 (VPLZCNTDrr VR512:$src)>;
5121 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5122 (VPLZCNTQrm addr:$src)>;
5123 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5124 (VPLZCNTQrr VR512:$src)>;
5126 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5127 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5128 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5130 def : Pat<(store VK1:$src, addr:$dst),
5131 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5133 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5134 (truncstore node:$val, node:$ptr), [{
5135 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5138 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5139 (MOV8mr addr:$dst, GR8:$src)>;
5141 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5142 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5143 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
5144 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5147 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5148 string OpcodeStr, Predicate prd> {
5149 let Predicates = [prd] in
5150 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5152 let Predicates = [prd, HasVLX] in {
5153 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5154 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5158 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5159 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5161 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5163 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5165 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5169 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;