1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
9 ValueType EltVT = eltvt;
10 int NumElts = numelts;
12 // Corresponding mask register class.
13 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
15 // Corresponding write-mask register class.
16 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
18 // The GPR register class that can hold the write mask. Use GR8 for fewer
19 // than 8 elements. Use shift-right and equal to work around the lack of
22 !cast<RegisterClass>("GR" #
23 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
25 // Suffix used in the instruction mnemonic.
26 string Suffix = suffix;
28 // VTName is a string name for vector VT. For vector types it will be
29 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
30 // It is a little bit complex for scalar types, where NumElts = 1.
31 // In this case we build v4f32 or v2f64
32 string VTName = "v" # !if (!eq (NumElts, 1),
33 !if (!eq (EltVT.Size, 32), 4,
34 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
37 ValueType VT = !cast<ValueType>(VTName);
39 string EltTypeName = !cast<string>(EltVT);
40 // Size of the element type in bits, e.g. 32 for v16i32.
41 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
42 int EltSize = EltVT.Size;
44 // "i" for integer types and "f" for floating-point types
45 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
47 // Size of RC in bits, e.g. 512 for VR512.
50 // The corresponding memory operand, e.g. i512mem for VR512.
51 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
52 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
55 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
56 // due to load promotion during legalization
57 PatFrag LdFrag = !cast<PatFrag>("load" #
58 !if (!eq (TypeVariantName, "i"),
59 !if (!eq (Size, 128), "v2i64",
60 !if (!eq (Size, 256), "v4i64",
62 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
64 // Load patterns used for memory operands. We only have this defined in
65 // case of i64 element types for sub-512 integer vectors. For now, keep
66 // MemOpFrag undefined in these cases.
68 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
69 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
70 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
71 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
72 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
74 // The corresponding float type, e.g. v16f32 for v16i32
75 // Note: For EltSize < 32, FloatVT is illegal and TableGen
76 // fails to compile, so we choose FloatVT = VT
77 ValueType FloatVT = !cast<ValueType>(
78 !if (!eq (!srl(EltSize,5),0),
80 !if (!eq(TypeVariantName, "i"),
81 "v" # NumElts # "f" # EltSize,
84 // The string to specify embedded broadcast in assembly.
85 string BroadcastStr = "{1to" # NumElts # "}";
87 // 8-bit compressed displacement tuple/subvector format. This is only
88 // defined for NumElts <= 8.
89 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
90 !cast<CD8VForm>("CD8VT" # NumElts), ?);
92 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
93 !if (!eq (Size, 256), sub_ymm, ?));
95 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
96 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
99 // A vector type of the same width with element type i32. This is used to
100 // create the canonical constant zero node ImmAllZerosV.
101 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
102 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
105 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
106 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
107 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
108 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
109 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
110 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
112 // "x" in v32i8x_info means RC = VR256X
113 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
114 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
115 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
116 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
117 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
118 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
120 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
121 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
122 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
123 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
124 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
125 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
127 // We map scalar types to the smallest (128-bit) vector type
128 // with the appropriate element type. This allows to use the same masking logic.
129 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
130 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
132 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
133 X86VectorVTInfo i128> {
134 X86VectorVTInfo info512 = i512;
135 X86VectorVTInfo info256 = i256;
136 X86VectorVTInfo info128 = i128;
139 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
141 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
143 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
145 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
147 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
149 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
152 // This multiclass generates the masking variants from the non-masking
153 // variant. It only provides the assembly pieces for the masking variants.
154 // It assumes custom ISel patterns for masking which can be provided as
155 // template arguments.
156 multiclass AVX512_maskable_custom<bits<8> O, Format F,
158 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
160 string AttSrcAsm, string IntelSrcAsm,
162 list<dag> MaskingPattern,
163 list<dag> ZeroMaskingPattern,
165 string MaskingConstraint = "",
166 InstrItinClass itin = NoItinerary,
167 bit IsCommutable = 0> {
168 let isCommutable = IsCommutable in
169 def NAME: AVX512<O, F, Outs, Ins,
170 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
171 "$dst "#Round#", "#IntelSrcAsm#"}",
174 // Prefer over VMOV*rrk Pat<>
175 let AddedComplexity = 20 in
176 def NAME#k: AVX512<O, F, Outs, MaskingIns,
177 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
178 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
179 MaskingPattern, itin>,
181 // In case of the 3src subclass this is overridden with a let.
182 string Constraints = MaskingConstraint;
184 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
185 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
186 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
187 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
194 // Common base class of AVX512_maskable and AVX512_maskable_3src.
195 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
197 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
199 string AttSrcAsm, string IntelSrcAsm,
200 dag RHS, dag MaskingRHS,
201 SDNode Select = vselect, string Round = "",
202 string MaskingConstraint = "",
203 InstrItinClass itin = NoItinerary,
204 bit IsCommutable = 0> :
205 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
206 AttSrcAsm, IntelSrcAsm,
207 [(set _.RC:$dst, RHS)],
208 [(set _.RC:$dst, MaskingRHS)],
210 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
211 Round, MaskingConstraint, NoItinerary, IsCommutable>;
213 // This multiclass generates the unconditional/non-masking, the masking and
214 // the zero-masking variant of the vector instruction. In the masking case, the
215 // perserved vector elements come from a new dummy input operand tied to $dst.
216 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Outs, dag Ins, string OpcodeStr,
218 string AttSrcAsm, string IntelSrcAsm,
219 dag RHS, string Round = "",
220 InstrItinClass itin = NoItinerary,
221 bit IsCommutable = 0> :
222 AVX512_maskable_common<O, F, _, Outs, Ins,
223 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
224 !con((ins _.KRCWM:$mask), Ins),
225 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
226 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
227 Round, "$src0 = $dst", itin, IsCommutable>;
229 // This multiclass generates the unconditional/non-masking, the masking and
230 // the zero-masking variant of the scalar instruction.
231 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
232 dag Outs, dag Ins, string OpcodeStr,
233 string AttSrcAsm, string IntelSrcAsm,
234 dag RHS, string Round = "",
235 InstrItinClass itin = NoItinerary,
236 bit IsCommutable = 0> :
237 AVX512_maskable_common<O, F, _, Outs, Ins,
238 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
239 !con((ins _.KRCWM:$mask), Ins),
240 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
241 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
242 Round, "$src0 = $dst", itin, IsCommutable>;
244 // Similar to AVX512_maskable but in this case one of the source operands
245 // ($src1) is already tied to $dst so we just use that for the preserved
246 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
248 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
249 dag Outs, dag NonTiedIns, string OpcodeStr,
250 string AttSrcAsm, string IntelSrcAsm,
252 AVX512_maskable_common<O, F, _, Outs,
253 !con((ins _.RC:$src1), NonTiedIns),
254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
255 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
256 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
257 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
260 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
263 string AttSrcAsm, string IntelSrcAsm,
265 AVX512_maskable_custom<O, F, Outs, Ins,
266 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
267 !con((ins _.KRCWM:$mask), Ins),
268 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
271 // Bitcasts between 512-bit vector types. Return the original type since
272 // no instruction is needed for the conversion
273 let Predicates = [HasAVX512] in {
274 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
275 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
276 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
277 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
278 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
279 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
280 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
281 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
282 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
283 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
284 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
285 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
286 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
287 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
288 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
289 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
290 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
291 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
292 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
293 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
296 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
297 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
299 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
300 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
302 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
303 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
304 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
306 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
307 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
308 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
309 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
310 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
311 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
312 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
313 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
314 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
315 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
316 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
317 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
318 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
319 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
320 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
321 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
322 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
323 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
324 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
325 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
326 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
327 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
328 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
329 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
330 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
331 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
332 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
333 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
334 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
335 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
337 // Bitcasts between 256-bit vector types. Return the original type since
338 // no instruction is needed for the conversion
339 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
340 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
341 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
342 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
343 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
344 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
346 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
347 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
348 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
350 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
351 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
352 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
353 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
355 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
357 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
358 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
359 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
360 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
361 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
363 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
365 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
367 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
368 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
372 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
375 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
376 isPseudo = 1, Predicates = [HasAVX512] in {
377 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
378 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
381 let Predicates = [HasAVX512] in {
382 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
383 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
384 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
387 //===----------------------------------------------------------------------===//
388 // AVX-512 - VECTOR INSERT
391 multiclass vinsert_for_size_no_alt<int Opcode,
392 X86VectorVTInfo From, X86VectorVTInfo To,
393 PatFrag vinsert_insert,
394 SDNodeXForm INSERT_get_vinsert_imm> {
395 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
396 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
397 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
398 "vinsert" # From.EltTypeName # "x" # From.NumElts #
399 "\t{$src3, $src2, $src1, $dst|"
400 "$dst, $src1, $src2, $src3}",
401 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
402 (From.VT From.RC:$src2),
407 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
408 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
409 "vinsert" # From.EltTypeName # "x" # From.NumElts #
410 "\t{$src3, $src2, $src1, $dst|"
411 "$dst, $src1, $src2, $src3}",
413 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
417 multiclass vinsert_for_size<int Opcode,
418 X86VectorVTInfo From, X86VectorVTInfo To,
419 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
420 PatFrag vinsert_insert,
421 SDNodeXForm INSERT_get_vinsert_imm> :
422 vinsert_for_size_no_alt<Opcode, From, To,
423 vinsert_insert, INSERT_get_vinsert_imm> {
424 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
425 // vinserti32x4. Only add this if 64x2 and friends are not supported
426 // natively via AVX512DQ.
427 let Predicates = [NoDQI] in
428 def : Pat<(vinsert_insert:$ins
429 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
430 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
431 VR512:$src1, From.RC:$src2,
432 (INSERT_get_vinsert_imm VR512:$ins)))>;
435 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
436 ValueType EltVT64, int Opcode256> {
437 defm NAME # "32x4" : vinsert_for_size<Opcode128,
438 X86VectorVTInfo< 4, EltVT32, VR128X>,
439 X86VectorVTInfo<16, EltVT32, VR512>,
440 X86VectorVTInfo< 2, EltVT64, VR128X>,
441 X86VectorVTInfo< 8, EltVT64, VR512>,
443 INSERT_get_vinsert128_imm>;
444 let Predicates = [HasDQI] in
445 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
446 X86VectorVTInfo< 2, EltVT64, VR128X>,
447 X86VectorVTInfo< 8, EltVT64, VR512>,
449 INSERT_get_vinsert128_imm>, VEX_W;
450 defm NAME # "64x4" : vinsert_for_size<Opcode256,
451 X86VectorVTInfo< 4, EltVT64, VR256X>,
452 X86VectorVTInfo< 8, EltVT64, VR512>,
453 X86VectorVTInfo< 8, EltVT32, VR256>,
454 X86VectorVTInfo<16, EltVT32, VR512>,
456 INSERT_get_vinsert256_imm>, VEX_W;
457 let Predicates = [HasDQI] in
458 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
459 X86VectorVTInfo< 8, EltVT32, VR256X>,
460 X86VectorVTInfo<16, EltVT32, VR512>,
462 INSERT_get_vinsert256_imm>;
465 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
466 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
468 // vinsertps - insert f32 to XMM
469 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
470 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
471 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
472 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
474 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
475 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
476 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
477 [(set VR128X:$dst, (X86insertps VR128X:$src1,
478 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
479 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
481 //===----------------------------------------------------------------------===//
482 // AVX-512 VECTOR EXTRACT
485 multiclass vextract_for_size<int Opcode,
486 X86VectorVTInfo From, X86VectorVTInfo To,
487 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
488 PatFrag vextract_extract,
489 SDNodeXForm EXTRACT_get_vextract_imm> {
490 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
491 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
492 (ins VR512:$src1, i8imm:$idx),
493 "vextract" # To.EltTypeName # "x4",
494 "$idx, $src1", "$src1, $idx",
495 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
497 AVX512AIi8Base, EVEX, EVEX_V512;
499 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
500 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
501 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
502 "$dst, $src1, $src2}",
503 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
506 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
508 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
509 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
511 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
513 // A 128/256-bit subvector extract from the first 512-bit vector position is
514 // a subregister copy that needs no instruction.
515 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
517 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
519 // And for the alternative types.
520 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
522 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
524 // Intrinsic call with masking.
525 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
527 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
528 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
529 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
530 VR512:$src1, imm:$idx)>;
532 // Intrinsic call with zero-masking.
533 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
535 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
536 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
537 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
538 VR512:$src1, imm:$idx)>;
540 // Intrinsic call without masking.
541 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
543 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
544 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
545 VR512:$src1, imm:$idx)>;
548 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
549 ValueType EltVT64, int Opcode64> {
550 defm NAME # "32x4" : vextract_for_size<Opcode32,
551 X86VectorVTInfo<16, EltVT32, VR512>,
552 X86VectorVTInfo< 4, EltVT32, VR128X>,
553 X86VectorVTInfo< 8, EltVT64, VR512>,
554 X86VectorVTInfo< 2, EltVT64, VR128X>,
556 EXTRACT_get_vextract128_imm>;
557 defm NAME # "64x4" : vextract_for_size<Opcode64,
558 X86VectorVTInfo< 8, EltVT64, VR512>,
559 X86VectorVTInfo< 4, EltVT64, VR256X>,
560 X86VectorVTInfo<16, EltVT32, VR512>,
561 X86VectorVTInfo< 8, EltVT32, VR256>,
563 EXTRACT_get_vextract256_imm>, VEX_W;
566 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
567 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
569 // A 128-bit subvector insert to the first 512-bit vector position
570 // is a subregister copy that needs no instruction.
571 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
572 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
573 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
575 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
576 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
577 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
579 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
580 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
581 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
583 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
584 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
585 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
588 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
589 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
590 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
591 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
592 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
593 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
594 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
595 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
597 // vextractps - extract 32 bits from XMM
598 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
599 (ins VR128X:$src1, i32i8imm:$src2),
600 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
601 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
604 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
605 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
606 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
607 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
608 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
610 //===---------------------------------------------------------------------===//
613 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
614 ValueType svt, X86VectorVTInfo _> {
615 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
616 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
617 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
621 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
622 (ins _.ScalarMemOp:$src),
623 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
624 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
629 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
630 AVX512VLVectorVTInfo _> {
631 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
634 let Predicates = [HasVLX] in {
635 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
640 let ExeDomain = SSEPackedSingle in {
641 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
642 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
643 let Predicates = [HasVLX] in {
644 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
645 v4f32, v4f32x_info>, EVEX_V128,
646 EVEX_CD8<32, CD8VT1>;
650 let ExeDomain = SSEPackedDouble in {
651 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
652 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
655 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
656 // representations of source
657 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
658 X86VectorVTInfo _, RegisterClass SrcRC_v,
659 RegisterClass SrcRC_s> {
660 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
661 (!cast<Instruction>(InstName##"r")
662 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
664 let AddedComplexity = 30 in {
665 def : Pat<(_.VT (vselect _.KRCWM:$mask,
666 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
667 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
668 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
670 def : Pat<(_.VT(vselect _.KRCWM:$mask,
671 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
672 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
673 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
677 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
679 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
682 let Predicates = [HasVLX] in {
683 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
684 v8f32x_info, VR128X, FR32X>;
685 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
686 v4f32x_info, VR128X, FR32X>;
687 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
688 v4f64x_info, VR128X, FR64X>;
691 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
692 (VBROADCASTSSZm addr:$src)>;
693 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
694 (VBROADCASTSDZm addr:$src)>;
696 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
697 (VBROADCASTSSZm addr:$src)>;
698 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
699 (VBROADCASTSDZm addr:$src)>;
701 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
702 RegisterClass SrcRC> {
703 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
704 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
705 "$src", "$src", []>, T8PD, EVEX;
708 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
709 RegisterClass SrcRC, Predicate prd> {
710 let Predicates = [prd] in
711 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
712 let Predicates = [prd, HasVLX] in {
713 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
714 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
718 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
720 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
722 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
724 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
727 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
728 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
730 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
731 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
733 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
734 (VPBROADCASTDrZr GR32:$src)>;
735 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
736 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
737 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
738 (VPBROADCASTQrZr GR64:$src)>;
739 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
740 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
742 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
743 (VPBROADCASTDrZr GR32:$src)>;
744 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
745 (VPBROADCASTQrZr GR64:$src)>;
747 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
748 (v16i32 immAllZerosV), (i16 GR16:$mask))),
749 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
750 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
751 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
752 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
754 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
755 X86MemOperand x86memop, PatFrag ld_frag,
756 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
758 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
759 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
761 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
762 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
764 !strconcat(OpcodeStr,
765 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
767 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
770 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
771 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
773 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
774 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
776 !strconcat(OpcodeStr,
777 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
778 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
779 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
783 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
784 loadi32, VR512, v16i32, v4i32, VK16WM>,
785 EVEX_V512, EVEX_CD8<32, CD8VT1>;
786 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
787 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
788 EVEX_CD8<64, CD8VT1>;
790 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
791 X86MemOperand x86memop, PatFrag ld_frag,
794 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
795 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
797 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
799 !strconcat(OpcodeStr,
800 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
805 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
806 i128mem, loadv2i64, VK16WM>,
807 EVEX_V512, EVEX_CD8<32, CD8VT4>;
808 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
809 i256mem, loadv4i64, VK16WM>, VEX_W,
810 EVEX_V512, EVEX_CD8<64, CD8VT4>;
812 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
813 (VPBROADCASTDZrr VR128X:$src)>;
814 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
815 (VPBROADCASTQZrr VR128X:$src)>;
817 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
818 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
819 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
820 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
822 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
823 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
824 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
825 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
827 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
828 (VBROADCASTSSZr VR128X:$src)>;
829 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
830 (VBROADCASTSDZr VR128X:$src)>;
832 // Provide fallback in case the load node that is used in the patterns above
833 // is used by additional users, which prevents the pattern selection.
834 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
835 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
836 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
837 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
840 let Predicates = [HasAVX512] in {
841 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
843 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
844 addr:$src)), sub_ymm)>;
846 //===----------------------------------------------------------------------===//
847 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
850 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
852 let Predicates = [HasCDI] in
853 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
854 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
855 []>, EVEX, EVEX_V512;
857 let Predicates = [HasCDI, HasVLX] in {
858 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
859 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
860 []>, EVEX, EVEX_V128;
861 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
862 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
863 []>, EVEX, EVEX_V256;
867 let Predicates = [HasCDI] in {
868 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
870 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
874 //===----------------------------------------------------------------------===//
877 // -- immediate form --
878 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
880 let ExeDomain = _.ExeDomain in {
881 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
882 (ins _.RC:$src1, i8imm:$src2),
883 !strconcat(OpcodeStr,
884 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
886 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
888 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
889 (ins _.MemOp:$src1, i8imm:$src2),
890 !strconcat(OpcodeStr,
891 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
893 (_.VT (OpNode (_.MemOpFrag addr:$src1),
895 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
899 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
900 X86VectorVTInfo Ctrl> :
901 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
902 let ExeDomain = _.ExeDomain in {
903 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
904 (ins _.RC:$src1, _.RC:$src2),
905 !strconcat("vpermil" # _.Suffix,
906 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
908 (_.VT (X86VPermilpv _.RC:$src1,
909 (Ctrl.VT Ctrl.RC:$src2))))]>,
911 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
912 (ins _.RC:$src1, Ctrl.MemOp:$src2),
913 !strconcat("vpermil" # _.Suffix,
914 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
916 (_.VT (X86VPermilpv _.RC:$src1,
917 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
922 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
924 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
927 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
929 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
932 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
933 (VPERMILPSZri VR512:$src1, imm:$imm)>;
934 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
935 (VPERMILPDZri VR512:$src1, imm:$imm)>;
937 // -- VPERM - register form --
938 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
939 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
941 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
942 (ins RC:$src1, RC:$src2),
943 !strconcat(OpcodeStr,
944 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
946 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
948 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
949 (ins RC:$src1, x86memop:$src2),
950 !strconcat(OpcodeStr,
951 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
953 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
957 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
958 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
959 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
960 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
961 let ExeDomain = SSEPackedSingle in
962 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
963 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
964 let ExeDomain = SSEPackedDouble in
965 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
966 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
968 // -- VPERM2I - 3 source operands form --
969 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
970 PatFrag mem_frag, X86MemOperand x86memop,
971 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
972 let Constraints = "$src1 = $dst" in {
973 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
974 (ins RC:$src1, RC:$src2, RC:$src3),
975 !strconcat(OpcodeStr,
976 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
978 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
981 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
982 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
983 !strconcat(OpcodeStr,
984 "\t{$src3, $src2, $dst {${mask}}|"
985 "$dst {${mask}}, $src2, $src3}"),
986 [(set RC:$dst, (OpVT (vselect KRC:$mask,
987 (OpNode RC:$src1, RC:$src2,
992 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
993 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
994 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
995 !strconcat(OpcodeStr,
996 "\t{$src3, $src2, $dst {${mask}} {z} |",
997 "$dst {${mask}} {z}, $src2, $src3}"),
998 [(set RC:$dst, (OpVT (vselect KRC:$mask,
999 (OpNode RC:$src1, RC:$src2,
1002 (v16i32 immAllZerosV))))))]>,
1005 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1006 (ins RC:$src1, RC:$src2, x86memop:$src3),
1007 !strconcat(OpcodeStr,
1008 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1010 (OpVT (OpNode RC:$src1, RC:$src2,
1011 (mem_frag addr:$src3))))]>, EVEX_4V;
1013 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1014 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1015 !strconcat(OpcodeStr,
1016 "\t{$src3, $src2, $dst {${mask}}|"
1017 "$dst {${mask}}, $src2, $src3}"),
1019 (OpVT (vselect KRC:$mask,
1020 (OpNode RC:$src1, RC:$src2,
1021 (mem_frag addr:$src3)),
1025 let AddedComplexity = 10 in // Prefer over the rrkz variant
1026 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1027 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1028 !strconcat(OpcodeStr,
1029 "\t{$src3, $src2, $dst {${mask}} {z}|"
1030 "$dst {${mask}} {z}, $src2, $src3}"),
1032 (OpVT (vselect KRC:$mask,
1033 (OpNode RC:$src1, RC:$src2,
1034 (mem_frag addr:$src3)),
1036 (v16i32 immAllZerosV))))))]>,
1040 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
1041 i512mem, X86VPermiv3, v16i32, VK16WM>,
1042 EVEX_V512, EVEX_CD8<32, CD8VF>;
1043 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
1044 i512mem, X86VPermiv3, v8i64, VK8WM>,
1045 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1046 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
1047 i512mem, X86VPermiv3, v16f32, VK16WM>,
1048 EVEX_V512, EVEX_CD8<32, CD8VF>;
1049 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
1050 i512mem, X86VPermiv3, v8f64, VK8WM>,
1051 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1053 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1054 PatFrag mem_frag, X86MemOperand x86memop,
1055 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1056 ValueType MaskVT, RegisterClass MRC> :
1057 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1059 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1060 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1061 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1063 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1064 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1065 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1066 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1069 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1070 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1071 EVEX_V512, EVEX_CD8<32, CD8VF>;
1072 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1073 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1074 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1075 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1076 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1077 EVEX_V512, EVEX_CD8<32, CD8VF>;
1078 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1079 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1080 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1082 //===----------------------------------------------------------------------===//
1083 // AVX-512 - BLEND using mask
1085 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
1086 RegisterClass KRC, RegisterClass RC,
1087 X86MemOperand x86memop, PatFrag mem_frag,
1088 SDNode OpNode, ValueType vt> {
1089 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1090 (ins KRC:$mask, RC:$src1, RC:$src2),
1091 !strconcat(OpcodeStr,
1092 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1093 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
1094 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
1096 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1097 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1098 !strconcat(OpcodeStr,
1099 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1100 []>, EVEX_4V, EVEX_K;
1103 let ExeDomain = SSEPackedSingle in
1104 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1105 VK16WM, VR512, f512mem,
1106 memopv16f32, vselect, v16f32>,
1107 EVEX_CD8<32, CD8VF>, EVEX_V512;
1108 let ExeDomain = SSEPackedDouble in
1109 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1110 VK8WM, VR512, f512mem,
1111 memopv8f64, vselect, v8f64>,
1112 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1114 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1115 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1116 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1117 VR512:$src1, VR512:$src2)>;
1119 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1120 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1121 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1122 VR512:$src1, VR512:$src2)>;
1124 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1125 VK16WM, VR512, f512mem,
1126 memopv16i32, vselect, v16i32>,
1127 EVEX_CD8<32, CD8VF>, EVEX_V512;
1129 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1130 VK8WM, VR512, f512mem,
1131 memopv8i64, vselect, v8i64>,
1132 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1134 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1135 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1136 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1137 VR512:$src1, VR512:$src2)>;
1139 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1140 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1141 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1142 VR512:$src1, VR512:$src2)>;
1144 let Predicates = [HasAVX512] in {
1145 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1146 (v8f32 VR256X:$src2))),
1148 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1149 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1150 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1152 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1153 (v8i32 VR256X:$src2))),
1155 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1156 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1157 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1159 //===----------------------------------------------------------------------===//
1160 // Compare Instructions
1161 //===----------------------------------------------------------------------===//
1163 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1164 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1165 Operand CC, SDNode OpNode, ValueType VT,
1166 PatFrag ld_frag, string asm, string asm_alt> {
1167 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1168 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1169 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1170 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1171 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1172 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1173 [(set VK1:$dst, (OpNode (VT RC:$src1),
1174 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1175 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1176 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1177 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1178 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1179 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1180 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1181 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1185 let Predicates = [HasAVX512] in {
1186 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1187 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1188 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1190 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1191 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1192 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1196 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1197 X86VectorVTInfo _> {
1198 def rr : AVX512BI<opc, MRMSrcReg,
1199 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1200 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1201 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1202 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1204 def rm : AVX512BI<opc, MRMSrcMem,
1205 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1206 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1207 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1208 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1209 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1210 def rrk : AVX512BI<opc, MRMSrcReg,
1211 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1213 "$dst {${mask}}, $src1, $src2}"),
1214 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1215 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1216 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1218 def rmk : AVX512BI<opc, MRMSrcMem,
1219 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1220 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1221 "$dst {${mask}}, $src1, $src2}"),
1222 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1223 (OpNode (_.VT _.RC:$src1),
1225 (_.LdFrag addr:$src2))))))],
1226 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1229 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1230 X86VectorVTInfo _> :
1231 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1232 let mayLoad = 1 in {
1233 def rmb : AVX512BI<opc, MRMSrcMem,
1234 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1235 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1236 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1237 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1238 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1239 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1240 def rmbk : AVX512BI<opc, MRMSrcMem,
1241 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1242 _.ScalarMemOp:$src2),
1243 !strconcat(OpcodeStr,
1244 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1245 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1246 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1247 (OpNode (_.VT _.RC:$src1),
1249 (_.ScalarLdFrag addr:$src2)))))],
1250 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1254 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1255 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1256 let Predicates = [prd] in
1257 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1260 let Predicates = [prd, HasVLX] in {
1261 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1263 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1268 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1269 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1271 let Predicates = [prd] in
1272 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1275 let Predicates = [prd, HasVLX] in {
1276 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1278 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1283 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1284 avx512vl_i8_info, HasBWI>,
1287 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1288 avx512vl_i16_info, HasBWI>,
1289 EVEX_CD8<16, CD8VF>;
1291 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1292 avx512vl_i32_info, HasAVX512>,
1293 EVEX_CD8<32, CD8VF>;
1295 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1296 avx512vl_i64_info, HasAVX512>,
1297 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1299 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1300 avx512vl_i8_info, HasBWI>,
1303 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1304 avx512vl_i16_info, HasBWI>,
1305 EVEX_CD8<16, CD8VF>;
1307 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1308 avx512vl_i32_info, HasAVX512>,
1309 EVEX_CD8<32, CD8VF>;
1311 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1312 avx512vl_i64_info, HasAVX512>,
1313 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1315 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1316 (COPY_TO_REGCLASS (VPCMPGTDZrr
1317 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1318 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1320 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1321 (COPY_TO_REGCLASS (VPCMPEQDZrr
1322 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1323 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1325 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1326 X86VectorVTInfo _> {
1327 def rri : AVX512AIi8<opc, MRMSrcReg,
1328 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1329 !strconcat("vpcmp${cc}", Suffix,
1330 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1331 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1333 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1335 def rmi : AVX512AIi8<opc, MRMSrcMem,
1336 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1337 !strconcat("vpcmp${cc}", Suffix,
1338 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1339 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1340 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1342 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1343 def rrik : AVX512AIi8<opc, MRMSrcReg,
1344 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1346 !strconcat("vpcmp${cc}", Suffix,
1347 "\t{$src2, $src1, $dst {${mask}}|",
1348 "$dst {${mask}}, $src1, $src2}"),
1349 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1350 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1352 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1354 def rmik : AVX512AIi8<opc, MRMSrcMem,
1355 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1357 !strconcat("vpcmp${cc}", Suffix,
1358 "\t{$src2, $src1, $dst {${mask}}|",
1359 "$dst {${mask}}, $src1, $src2}"),
1360 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1361 (OpNode (_.VT _.RC:$src1),
1362 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1364 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1366 // Accept explicit immediate argument form instead of comparison code.
1367 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1368 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1369 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1370 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1371 "$dst, $src1, $src2, $cc}"),
1372 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1373 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1374 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1375 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1376 "$dst, $src1, $src2, $cc}"),
1377 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1378 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1379 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1381 !strconcat("vpcmp", Suffix,
1382 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1383 "$dst {${mask}}, $src1, $src2, $cc}"),
1384 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1385 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1386 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1388 !strconcat("vpcmp", Suffix,
1389 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1390 "$dst {${mask}}, $src1, $src2, $cc}"),
1391 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1395 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1396 X86VectorVTInfo _> :
1397 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1398 let mayLoad = 1 in {
1399 def rmib : AVX512AIi8<opc, MRMSrcMem,
1400 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1402 !strconcat("vpcmp${cc}", Suffix,
1403 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1404 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1405 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1406 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1408 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1409 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1410 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1411 _.ScalarMemOp:$src2, AVXCC:$cc),
1412 !strconcat("vpcmp${cc}", Suffix,
1413 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1414 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1415 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1416 (OpNode (_.VT _.RC:$src1),
1417 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1419 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1422 // Accept explicit immediate argument form instead of comparison code.
1423 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1424 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1425 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1427 !strconcat("vpcmp", Suffix,
1428 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1429 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1430 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1431 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1432 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1433 _.ScalarMemOp:$src2, i8imm:$cc),
1434 !strconcat("vpcmp", Suffix,
1435 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1436 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1437 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1441 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1442 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1443 let Predicates = [prd] in
1444 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1446 let Predicates = [prd, HasVLX] in {
1447 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1448 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1452 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1453 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1454 let Predicates = [prd] in
1455 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1458 let Predicates = [prd, HasVLX] in {
1459 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1461 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1466 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1467 HasBWI>, EVEX_CD8<8, CD8VF>;
1468 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1469 HasBWI>, EVEX_CD8<8, CD8VF>;
1471 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1472 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1473 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1474 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1476 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1477 HasAVX512>, EVEX_CD8<32, CD8VF>;
1478 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1479 HasAVX512>, EVEX_CD8<32, CD8VF>;
1481 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1482 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1483 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1484 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1486 // avx512_cmp_packed - compare packed instructions
1487 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1488 X86MemOperand x86memop, ValueType vt,
1489 string suffix, Domain d> {
1490 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1491 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1492 !strconcat("vcmp${cc}", suffix,
1493 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1494 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1495 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1496 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1497 !strconcat("vcmp${cc}", suffix,
1498 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1500 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1501 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1502 !strconcat("vcmp${cc}", suffix,
1503 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1505 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1507 // Accept explicit immediate argument form instead of comparison code.
1508 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1509 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1510 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1511 !strconcat("vcmp", suffix,
1512 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1513 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1514 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1515 !strconcat("vcmp", suffix,
1516 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1520 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1521 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1522 EVEX_CD8<32, CD8VF>;
1523 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1524 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1525 EVEX_CD8<64, CD8VF>;
1527 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1528 (COPY_TO_REGCLASS (VCMPPSZrri
1529 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1530 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1532 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1533 (COPY_TO_REGCLASS (VPCMPDZrri
1534 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1535 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1537 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1538 (COPY_TO_REGCLASS (VPCMPUDZrri
1539 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1540 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1543 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1544 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1546 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1547 (I8Imm imm:$cc)), GR16)>;
1549 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1550 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1552 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1553 (I8Imm imm:$cc)), GR8)>;
1555 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1556 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1558 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1559 (I8Imm imm:$cc)), GR16)>;
1561 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1562 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1564 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1565 (I8Imm imm:$cc)), GR8)>;
1567 // Mask register copy, including
1568 // - copy between mask registers
1569 // - load/store mask registers
1570 // - copy from GPR to mask register and vice versa
1572 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1573 string OpcodeStr, RegisterClass KRC,
1574 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1575 let hasSideEffects = 0 in {
1576 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1577 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1579 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1581 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1583 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1588 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1590 RegisterClass KRC, RegisterClass GRC> {
1591 let hasSideEffects = 0 in {
1592 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1593 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1594 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1595 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1599 let Predicates = [HasDQI] in
1600 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1602 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1605 let Predicates = [HasAVX512] in
1606 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1608 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1611 let Predicates = [HasBWI] in {
1612 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1613 i32mem>, VEX, PD, VEX_W;
1614 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1618 let Predicates = [HasBWI] in {
1619 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1620 i64mem>, VEX, PS, VEX_W;
1621 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1625 // GR from/to mask register
1626 let Predicates = [HasDQI] in {
1627 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1628 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1629 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1630 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1632 let Predicates = [HasAVX512] in {
1633 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1634 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1635 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1636 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1638 let Predicates = [HasBWI] in {
1639 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1640 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1642 let Predicates = [HasBWI] in {
1643 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1644 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1648 let Predicates = [HasDQI] in {
1649 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1650 (KMOVBmk addr:$dst, VK8:$src)>;
1652 let Predicates = [HasAVX512] in {
1653 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1654 (KMOVWmk addr:$dst, VK16:$src)>;
1655 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1656 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1657 def : Pat<(i1 (load addr:$src)),
1658 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1659 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1660 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1662 let Predicates = [HasBWI] in {
1663 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1664 (KMOVDmk addr:$dst, VK32:$src)>;
1666 let Predicates = [HasBWI] in {
1667 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1668 (KMOVQmk addr:$dst, VK64:$src)>;
1671 let Predicates = [HasAVX512] in {
1672 def : Pat<(i1 (trunc (i64 GR64:$src))),
1673 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1676 def : Pat<(i1 (trunc (i32 GR32:$src))),
1677 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1679 def : Pat<(i1 (trunc (i8 GR8:$src))),
1681 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1683 def : Pat<(i1 (trunc (i16 GR16:$src))),
1685 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1688 def : Pat<(i32 (zext VK1:$src)),
1689 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1690 def : Pat<(i8 (zext VK1:$src)),
1693 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1694 def : Pat<(i64 (zext VK1:$src)),
1695 (AND64ri8 (SUBREG_TO_REG (i64 0),
1696 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1697 def : Pat<(i16 (zext VK1:$src)),
1699 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1701 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1702 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1703 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1704 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1706 let Predicates = [HasBWI] in {
1707 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1708 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1709 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1710 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1714 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1715 let Predicates = [HasAVX512] in {
1716 // GR from/to 8-bit mask without native support
1717 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1719 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1721 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1723 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1726 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1727 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1728 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1729 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1731 let Predicates = [HasBWI] in {
1732 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1733 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1734 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1735 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1738 // Mask unary operation
1740 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1741 RegisterClass KRC, SDPatternOperator OpNode,
1743 let Predicates = [prd] in
1744 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1745 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1746 [(set KRC:$dst, (OpNode KRC:$src))]>;
1749 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1750 SDPatternOperator OpNode> {
1751 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1753 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1754 HasAVX512>, VEX, PS;
1755 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1756 HasBWI>, VEX, PD, VEX_W;
1757 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1758 HasBWI>, VEX, PS, VEX_W;
1761 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1763 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1764 let Predicates = [HasAVX512] in
1765 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1767 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1768 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1770 defm : avx512_mask_unop_int<"knot", "KNOT">;
1772 let Predicates = [HasDQI] in
1773 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1774 let Predicates = [HasAVX512] in
1775 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1776 let Predicates = [HasBWI] in
1777 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1778 let Predicates = [HasBWI] in
1779 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1781 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1782 let Predicates = [HasAVX512] in {
1783 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1784 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1786 def : Pat<(not VK8:$src),
1788 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1791 // Mask binary operation
1792 // - KAND, KANDN, KOR, KXNOR, KXOR
1793 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1794 RegisterClass KRC, SDPatternOperator OpNode,
1796 let Predicates = [prd] in
1797 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1798 !strconcat(OpcodeStr,
1799 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1800 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1803 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1804 SDPatternOperator OpNode> {
1805 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1806 HasDQI>, VEX_4V, VEX_L, PD;
1807 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1808 HasAVX512>, VEX_4V, VEX_L, PS;
1809 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1810 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1811 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1812 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1815 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1816 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1818 let isCommutable = 1 in {
1819 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1820 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1821 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1822 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1824 let isCommutable = 0 in
1825 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1827 def : Pat<(xor VK1:$src1, VK1:$src2),
1828 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1829 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1831 def : Pat<(or VK1:$src1, VK1:$src2),
1832 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1833 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1835 def : Pat<(and VK1:$src1, VK1:$src2),
1836 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1837 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1839 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1840 let Predicates = [HasAVX512] in
1841 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1842 (i16 GR16:$src1), (i16 GR16:$src2)),
1843 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1844 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1845 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1848 defm : avx512_mask_binop_int<"kand", "KAND">;
1849 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1850 defm : avx512_mask_binop_int<"kor", "KOR">;
1851 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1852 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1854 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1855 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1856 let Predicates = [HasAVX512] in
1857 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1859 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1860 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1863 defm : avx512_binop_pat<and, KANDWrr>;
1864 defm : avx512_binop_pat<andn, KANDNWrr>;
1865 defm : avx512_binop_pat<or, KORWrr>;
1866 defm : avx512_binop_pat<xnor, KXNORWrr>;
1867 defm : avx512_binop_pat<xor, KXORWrr>;
1870 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1871 RegisterClass KRC> {
1872 let Predicates = [HasAVX512] in
1873 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1874 !strconcat(OpcodeStr,
1875 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1878 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1879 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1883 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1884 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1885 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1886 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1889 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1890 let Predicates = [HasAVX512] in
1891 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1892 (i16 GR16:$src1), (i16 GR16:$src2)),
1893 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1894 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1895 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1897 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1900 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1902 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1903 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1904 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1905 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1908 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1909 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1913 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1915 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1916 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1917 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1920 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1922 let Predicates = [HasAVX512] in
1923 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1924 !strconcat(OpcodeStr,
1925 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1926 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1929 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1931 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1935 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1936 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1938 // Mask setting all 0s or 1s
1939 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1940 let Predicates = [HasAVX512] in
1941 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1942 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1943 [(set KRC:$dst, (VT Val))]>;
1946 multiclass avx512_mask_setop_w<PatFrag Val> {
1947 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1948 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1951 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1952 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1954 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1955 let Predicates = [HasAVX512] in {
1956 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1957 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1958 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1959 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1960 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1962 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1963 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1965 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1966 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1968 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1969 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1971 let Predicates = [HasVLX] in {
1972 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1973 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1974 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1975 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1976 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1977 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1978 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1979 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1982 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1983 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1985 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1986 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1987 //===----------------------------------------------------------------------===//
1988 // AVX-512 - Aligned and unaligned load and store
1991 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1992 RegisterClass KRC, RegisterClass RC,
1993 ValueType vt, ValueType zvt, X86MemOperand memop,
1994 Domain d, bit IsReMaterializable = 1> {
1995 let hasSideEffects = 0 in {
1996 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1997 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1999 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2000 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2001 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2003 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2004 SchedRW = [WriteLoad] in
2005 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2006 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2007 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2010 let AddedComplexity = 20 in {
2011 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2012 let hasSideEffects = 0 in
2013 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2014 (ins RC:$src0, KRC:$mask, RC:$src1),
2015 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2016 "${dst} {${mask}}, $src1}"),
2017 [(set RC:$dst, (vt (vselect KRC:$mask,
2021 let mayLoad = 1, SchedRW = [WriteLoad] in
2022 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2023 (ins RC:$src0, KRC:$mask, memop:$src1),
2024 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2025 "${dst} {${mask}}, $src1}"),
2028 (vt (bitconvert (ld_frag addr:$src1))),
2032 let mayLoad = 1, SchedRW = [WriteLoad] in
2033 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2034 (ins KRC:$mask, memop:$src),
2035 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2036 "${dst} {${mask}} {z}, $src}"),
2039 (vt (bitconvert (ld_frag addr:$src))),
2040 (vt (bitconvert (zvt immAllZerosV))))))],
2045 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2046 string elty, string elsz, string vsz512,
2047 string vsz256, string vsz128, Domain d,
2048 Predicate prd, bit IsReMaterializable = 1> {
2049 let Predicates = [prd] in
2050 defm Z : avx512_load<opc, OpcodeStr,
2051 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2052 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2053 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2054 !cast<X86MemOperand>(elty##"512mem"), d,
2055 IsReMaterializable>, EVEX_V512;
2057 let Predicates = [prd, HasVLX] in {
2058 defm Z256 : avx512_load<opc, OpcodeStr,
2059 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2060 "v"##vsz256##elty##elsz, "v4i64")),
2061 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2062 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2063 !cast<X86MemOperand>(elty##"256mem"), d,
2064 IsReMaterializable>, EVEX_V256;
2066 defm Z128 : avx512_load<opc, OpcodeStr,
2067 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2068 "v"##vsz128##elty##elsz, "v2i64")),
2069 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2070 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2071 !cast<X86MemOperand>(elty##"128mem"), d,
2072 IsReMaterializable>, EVEX_V128;
2077 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2078 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2079 X86MemOperand memop, Domain d> {
2080 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2081 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2082 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2084 let Constraints = "$src1 = $dst" in
2085 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2086 (ins RC:$src1, KRC:$mask, RC:$src2),
2087 !strconcat(OpcodeStr,
2088 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2090 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2091 (ins KRC:$mask, RC:$src),
2092 !strconcat(OpcodeStr,
2093 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2094 [], d>, EVEX, EVEX_KZ;
2096 let mayStore = 1 in {
2097 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2098 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2099 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2100 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2101 (ins memop:$dst, KRC:$mask, RC:$src),
2102 !strconcat(OpcodeStr,
2103 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2104 [], d>, EVEX, EVEX_K;
2109 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2110 string st_suff_512, string st_suff_256,
2111 string st_suff_128, string elty, string elsz,
2112 string vsz512, string vsz256, string vsz128,
2113 Domain d, Predicate prd> {
2114 let Predicates = [prd] in
2115 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2116 !cast<ValueType>("v"##vsz512##elty##elsz),
2117 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2118 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2120 let Predicates = [prd, HasVLX] in {
2121 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2122 !cast<ValueType>("v"##vsz256##elty##elsz),
2123 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2124 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2126 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2127 !cast<ValueType>("v"##vsz128##elty##elsz),
2128 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2129 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2133 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2134 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2135 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2136 "512", "256", "", "f", "32", "16", "8", "4",
2137 SSEPackedSingle, HasAVX512>,
2138 PS, EVEX_CD8<32, CD8VF>;
2140 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2141 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2142 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2143 "512", "256", "", "f", "64", "8", "4", "2",
2144 SSEPackedDouble, HasAVX512>,
2145 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2147 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2148 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2149 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2150 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2151 PS, EVEX_CD8<32, CD8VF>;
2153 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2154 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2155 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2156 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2157 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2159 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2160 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2161 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2163 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2164 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2165 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2167 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2169 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2171 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2173 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2176 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2177 (VMOVUPSZmrk addr:$ptr,
2178 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2179 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2181 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2182 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2183 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2185 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2186 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2188 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2189 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2191 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2192 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2194 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2195 (bc_v16f32 (v16i32 immAllZerosV)))),
2196 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2198 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2199 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2201 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2202 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2204 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2205 (bc_v8f64 (v16i32 immAllZerosV)))),
2206 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2208 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2209 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2211 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2212 "16", "8", "4", SSEPackedInt, HasAVX512>,
2213 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2214 "512", "256", "", "i", "32", "16", "8", "4",
2215 SSEPackedInt, HasAVX512>,
2216 PD, EVEX_CD8<32, CD8VF>;
2218 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2219 "8", "4", "2", SSEPackedInt, HasAVX512>,
2220 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2221 "512", "256", "", "i", "64", "8", "4", "2",
2222 SSEPackedInt, HasAVX512>,
2223 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2225 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2226 "64", "32", "16", SSEPackedInt, HasBWI>,
2227 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2228 "i", "8", "64", "32", "16", SSEPackedInt,
2229 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2231 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2232 "32", "16", "8", SSEPackedInt, HasBWI>,
2233 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2234 "i", "16", "32", "16", "8", SSEPackedInt,
2235 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2237 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2238 "16", "8", "4", SSEPackedInt, HasAVX512>,
2239 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2240 "i", "32", "16", "8", "4", SSEPackedInt,
2241 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2243 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2244 "8", "4", "2", SSEPackedInt, HasAVX512>,
2245 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2246 "i", "64", "8", "4", "2", SSEPackedInt,
2247 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2249 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2250 (v16i32 immAllZerosV), GR16:$mask)),
2251 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2253 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2254 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2255 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2257 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2259 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2261 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2263 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2266 let AddedComplexity = 20 in {
2267 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2268 (bc_v8i64 (v16i32 immAllZerosV)))),
2269 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2271 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2272 (v8i64 VR512:$src))),
2273 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2276 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2277 (v16i32 immAllZerosV))),
2278 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2280 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2281 (v16i32 VR512:$src))),
2282 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2285 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2286 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2288 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2289 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2291 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2292 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2294 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2295 (bc_v8i64 (v16i32 immAllZerosV)))),
2296 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2298 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2299 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2301 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2302 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2304 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2305 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2307 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2308 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2311 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2312 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2315 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2316 (VMOVDQU32Zmrk addr:$ptr,
2317 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2318 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2320 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2321 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2322 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2325 // Move Int Doubleword to Packed Double Int
2327 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2328 "vmovd\t{$src, $dst|$dst, $src}",
2330 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2332 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2333 "vmovd\t{$src, $dst|$dst, $src}",
2335 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2336 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2337 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2338 "vmovq\t{$src, $dst|$dst, $src}",
2340 (v2i64 (scalar_to_vector GR64:$src)))],
2341 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2342 let isCodeGenOnly = 1 in {
2343 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2344 "vmovq\t{$src, $dst|$dst, $src}",
2345 [(set FR64:$dst, (bitconvert GR64:$src))],
2346 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2347 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2348 "vmovq\t{$src, $dst|$dst, $src}",
2349 [(set GR64:$dst, (bitconvert FR64:$src))],
2350 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2352 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2353 "vmovq\t{$src, $dst|$dst, $src}",
2354 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2355 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2356 EVEX_CD8<64, CD8VT1>;
2358 // Move Int Doubleword to Single Scalar
2360 let isCodeGenOnly = 1 in {
2361 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2362 "vmovd\t{$src, $dst|$dst, $src}",
2363 [(set FR32X:$dst, (bitconvert GR32:$src))],
2364 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2366 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2367 "vmovd\t{$src, $dst|$dst, $src}",
2368 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2369 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2372 // Move doubleword from xmm register to r/m32
2374 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2375 "vmovd\t{$src, $dst|$dst, $src}",
2376 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2377 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2379 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2380 (ins i32mem:$dst, VR128X:$src),
2381 "vmovd\t{$src, $dst|$dst, $src}",
2382 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2383 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2384 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2386 // Move quadword from xmm1 register to r/m64
2388 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2389 "vmovq\t{$src, $dst|$dst, $src}",
2390 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2392 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2393 Requires<[HasAVX512, In64BitMode]>;
2395 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2396 (ins i64mem:$dst, VR128X:$src),
2397 "vmovq\t{$src, $dst|$dst, $src}",
2398 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2399 addr:$dst)], IIC_SSE_MOVDQ>,
2400 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2401 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2403 // Move Scalar Single to Double Int
2405 let isCodeGenOnly = 1 in {
2406 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2408 "vmovd\t{$src, $dst|$dst, $src}",
2409 [(set GR32:$dst, (bitconvert FR32X:$src))],
2410 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2411 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2412 (ins i32mem:$dst, FR32X:$src),
2413 "vmovd\t{$src, $dst|$dst, $src}",
2414 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2415 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2418 // Move Quadword Int to Packed Quadword Int
2420 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2422 "vmovq\t{$src, $dst|$dst, $src}",
2424 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2425 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2427 //===----------------------------------------------------------------------===//
2428 // AVX-512 MOVSS, MOVSD
2429 //===----------------------------------------------------------------------===//
2431 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2432 SDNode OpNode, ValueType vt,
2433 X86MemOperand x86memop, PatFrag mem_pat> {
2434 let hasSideEffects = 0 in {
2435 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2436 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2437 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2438 (scalar_to_vector RC:$src2))))],
2439 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2440 let Constraints = "$src1 = $dst" in
2441 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2442 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2444 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2445 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2446 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2447 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2448 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2450 let mayStore = 1 in {
2451 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2452 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2453 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2455 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2456 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2457 [], IIC_SSE_MOV_S_MR>,
2458 EVEX, VEX_LIG, EVEX_K;
2460 } //hasSideEffects = 0
2463 let ExeDomain = SSEPackedSingle in
2464 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2465 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2467 let ExeDomain = SSEPackedDouble in
2468 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2469 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2471 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2472 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2473 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2475 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2476 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2477 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2479 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2480 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2481 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2483 // For the disassembler
2484 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2485 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2486 (ins VR128X:$src1, FR32X:$src2),
2487 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2489 XS, EVEX_4V, VEX_LIG;
2490 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2491 (ins VR128X:$src1, FR64X:$src2),
2492 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2494 XD, EVEX_4V, VEX_LIG, VEX_W;
2497 let Predicates = [HasAVX512] in {
2498 let AddedComplexity = 15 in {
2499 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2500 // MOVS{S,D} to the lower bits.
2501 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2502 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2503 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2504 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2505 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2506 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2507 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2508 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2510 // Move low f32 and clear high bits.
2511 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2512 (SUBREG_TO_REG (i32 0),
2513 (VMOVSSZrr (v4f32 (V_SET0)),
2514 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2515 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2516 (SUBREG_TO_REG (i32 0),
2517 (VMOVSSZrr (v4i32 (V_SET0)),
2518 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2521 let AddedComplexity = 20 in {
2522 // MOVSSrm zeros the high parts of the register; represent this
2523 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2524 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2525 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2526 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2527 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2528 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2529 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2531 // MOVSDrm zeros the high parts of the register; represent this
2532 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2533 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2534 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2535 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2536 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2537 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2538 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2539 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2540 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2541 def : Pat<(v2f64 (X86vzload addr:$src)),
2542 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2544 // Represent the same patterns above but in the form they appear for
2546 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2547 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2548 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2549 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2550 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2551 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2552 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2553 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2554 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2556 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2557 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2558 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2559 FR32X:$src)), sub_xmm)>;
2560 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2561 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2562 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2563 FR64X:$src)), sub_xmm)>;
2564 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2565 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2566 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2568 // Move low f64 and clear high bits.
2569 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2570 (SUBREG_TO_REG (i32 0),
2571 (VMOVSDZrr (v2f64 (V_SET0)),
2572 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2574 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2575 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2576 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2578 // Extract and store.
2579 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2581 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2582 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2584 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2586 // Shuffle with VMOVSS
2587 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2588 (VMOVSSZrr (v4i32 VR128X:$src1),
2589 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2590 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2591 (VMOVSSZrr (v4f32 VR128X:$src1),
2592 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2595 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2596 (SUBREG_TO_REG (i32 0),
2597 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2598 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2600 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2601 (SUBREG_TO_REG (i32 0),
2602 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2603 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2606 // Shuffle with VMOVSD
2607 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2608 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2609 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2610 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2611 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2612 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2613 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2614 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2617 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2618 (SUBREG_TO_REG (i32 0),
2619 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2620 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2622 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2623 (SUBREG_TO_REG (i32 0),
2624 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2625 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2628 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2629 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2630 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2631 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2632 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2633 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2634 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2635 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2638 let AddedComplexity = 15 in
2639 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2641 "vmovq\t{$src, $dst|$dst, $src}",
2642 [(set VR128X:$dst, (v2i64 (X86vzmovl
2643 (v2i64 VR128X:$src))))],
2644 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2646 let AddedComplexity = 20 in
2647 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2649 "vmovq\t{$src, $dst|$dst, $src}",
2650 [(set VR128X:$dst, (v2i64 (X86vzmovl
2651 (loadv2i64 addr:$src))))],
2652 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2653 EVEX_CD8<8, CD8VT8>;
2655 let Predicates = [HasAVX512] in {
2656 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2657 let AddedComplexity = 20 in {
2658 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2659 (VMOVDI2PDIZrm addr:$src)>;
2660 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2661 (VMOV64toPQIZrr GR64:$src)>;
2662 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2663 (VMOVDI2PDIZrr GR32:$src)>;
2665 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2666 (VMOVDI2PDIZrm addr:$src)>;
2667 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2668 (VMOVDI2PDIZrm addr:$src)>;
2669 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2670 (VMOVZPQILo2PQIZrm addr:$src)>;
2671 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2672 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2673 def : Pat<(v2i64 (X86vzload addr:$src)),
2674 (VMOVZPQILo2PQIZrm addr:$src)>;
2677 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2678 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2679 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2680 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2681 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2682 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2683 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2686 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2687 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2689 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2690 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2692 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2693 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2695 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2696 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2698 //===----------------------------------------------------------------------===//
2699 // AVX-512 - Non-temporals
2700 //===----------------------------------------------------------------------===//
2701 let SchedRW = [WriteLoad] in {
2702 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2703 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2704 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2705 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2706 EVEX_CD8<64, CD8VF>;
2708 let Predicates = [HasAVX512, HasVLX] in {
2709 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2711 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2712 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2713 EVEX_CD8<64, CD8VF>;
2715 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2717 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2718 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2719 EVEX_CD8<64, CD8VF>;
2723 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2724 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2725 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2726 let SchedRW = [WriteStore], mayStore = 1,
2727 AddedComplexity = 400 in
2728 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2729 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2730 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2733 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2734 string elty, string elsz, string vsz512,
2735 string vsz256, string vsz128, Domain d,
2736 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2737 let Predicates = [prd] in
2738 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2739 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2740 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2743 let Predicates = [prd, HasVLX] in {
2744 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2745 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2746 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2749 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2750 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2751 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2756 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2757 "i", "64", "8", "4", "2", SSEPackedInt,
2758 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2760 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2761 "f", "64", "8", "4", "2", SSEPackedDouble,
2762 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2764 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2765 "f", "32", "16", "8", "4", SSEPackedSingle,
2766 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2768 //===----------------------------------------------------------------------===//
2769 // AVX-512 - Integer arithmetic
2771 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2772 X86VectorVTInfo _, OpndItins itins,
2773 bit IsCommutable = 0> {
2774 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2775 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2776 "$src2, $src1", "$src1, $src2",
2777 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2778 "", itins.rr, IsCommutable>,
2779 AVX512BIBase, EVEX_4V;
2782 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2783 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2784 "$src2, $src1", "$src1, $src2",
2785 (_.VT (OpNode _.RC:$src1,
2786 (bitconvert (_.LdFrag addr:$src2)))),
2788 AVX512BIBase, EVEX_4V;
2791 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2792 X86VectorVTInfo _, OpndItins itins,
2793 bit IsCommutable = 0> :
2794 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2796 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2797 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2798 "${src2}"##_.BroadcastStr##", $src1",
2799 "$src1, ${src2}"##_.BroadcastStr,
2800 (_.VT (OpNode _.RC:$src1,
2802 (_.ScalarLdFrag addr:$src2)))),
2804 AVX512BIBase, EVEX_4V, EVEX_B;
2807 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2808 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2809 Predicate prd, bit IsCommutable = 0> {
2810 let Predicates = [prd] in
2811 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2812 IsCommutable>, EVEX_V512;
2814 let Predicates = [prd, HasVLX] in {
2815 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2816 IsCommutable>, EVEX_V256;
2817 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2818 IsCommutable>, EVEX_V128;
2822 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2823 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2824 Predicate prd, bit IsCommutable = 0> {
2825 let Predicates = [prd] in
2826 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2827 IsCommutable>, EVEX_V512;
2829 let Predicates = [prd, HasVLX] in {
2830 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2831 IsCommutable>, EVEX_V256;
2832 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2833 IsCommutable>, EVEX_V128;
2837 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2838 OpndItins itins, Predicate prd,
2839 bit IsCommutable = 0> {
2840 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2841 itins, prd, IsCommutable>,
2842 VEX_W, EVEX_CD8<64, CD8VF>;
2845 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2846 OpndItins itins, Predicate prd,
2847 bit IsCommutable = 0> {
2848 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2849 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2852 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2853 OpndItins itins, Predicate prd,
2854 bit IsCommutable = 0> {
2855 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2856 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2859 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2860 OpndItins itins, Predicate prd,
2861 bit IsCommutable = 0> {
2862 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2863 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2866 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2867 SDNode OpNode, OpndItins itins, Predicate prd,
2868 bit IsCommutable = 0> {
2869 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2872 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2876 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2877 SDNode OpNode, OpndItins itins, Predicate prd,
2878 bit IsCommutable = 0> {
2879 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2882 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2886 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2887 bits<8> opc_d, bits<8> opc_q,
2888 string OpcodeStr, SDNode OpNode,
2889 OpndItins itins, bit IsCommutable = 0> {
2890 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2891 itins, HasAVX512, IsCommutable>,
2892 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2893 itins, HasBWI, IsCommutable>;
2896 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2897 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2898 PatFrag memop_frag, X86MemOperand x86memop,
2899 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2900 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2901 let isCommutable = IsCommutable in
2903 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2904 (ins RC:$src1, RC:$src2),
2905 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2907 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2908 (ins KRC:$mask, RC:$src1, RC:$src2),
2909 !strconcat(OpcodeStr,
2910 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2911 [], itins.rr>, EVEX_4V, EVEX_K;
2912 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2913 (ins KRC:$mask, RC:$src1, RC:$src2),
2914 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
2915 "|$dst {${mask}} {z}, $src1, $src2}"),
2916 [], itins.rr>, EVEX_4V, EVEX_KZ;
2918 let mayLoad = 1 in {
2919 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2920 (ins RC:$src1, x86memop:$src2),
2921 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2923 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2924 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2925 !strconcat(OpcodeStr,
2926 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2927 [], itins.rm>, EVEX_4V, EVEX_K;
2928 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2929 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2930 !strconcat(OpcodeStr,
2931 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2932 [], itins.rm>, EVEX_4V, EVEX_KZ;
2933 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2934 (ins RC:$src1, x86scalar_mop:$src2),
2935 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2936 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2937 [], itins.rm>, EVEX_4V, EVEX_B;
2938 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2939 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2940 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2941 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2943 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2944 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2945 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2946 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2947 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2949 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2953 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2954 SSE_INTALU_ITINS_P, 1>;
2955 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2956 SSE_INTALU_ITINS_P, 0>;
2957 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2958 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2959 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2960 SSE_INTALU_ITINS_P, HasBWI, 1>;
2961 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2962 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2964 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2965 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2966 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2967 EVEX_CD8<64, CD8VF>, VEX_W;
2969 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2970 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2971 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2973 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2974 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2976 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2977 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2978 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2979 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2980 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2981 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2983 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2984 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2985 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2986 SSE_INTALU_ITINS_P, HasBWI, 1>;
2987 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2988 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2990 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2991 SSE_INTALU_ITINS_P, HasBWI, 1>;
2992 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2993 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2994 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2995 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2997 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2998 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2999 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3000 SSE_INTALU_ITINS_P, HasBWI, 1>;
3001 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3002 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3004 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3005 SSE_INTALU_ITINS_P, HasBWI, 1>;
3006 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3007 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3008 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3009 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3011 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3012 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3013 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3014 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3015 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3016 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3017 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3018 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3019 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3020 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3021 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3022 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3023 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3024 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3025 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3026 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3027 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3028 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3029 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3030 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3031 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3032 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3033 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3034 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3035 //===----------------------------------------------------------------------===//
3036 // AVX-512 - Unpack Instructions
3037 //===----------------------------------------------------------------------===//
3039 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3040 PatFrag mem_frag, RegisterClass RC,
3041 X86MemOperand x86memop, string asm,
3043 def rr : AVX512PI<opc, MRMSrcReg,
3044 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3046 (vt (OpNode RC:$src1, RC:$src2)))],
3048 def rm : AVX512PI<opc, MRMSrcMem,
3049 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3051 (vt (OpNode RC:$src1,
3052 (bitconvert (mem_frag addr:$src2)))))],
3056 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3057 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3058 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3059 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3060 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3061 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3062 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3063 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3064 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3065 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3066 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3067 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3069 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3070 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3071 X86MemOperand x86memop> {
3072 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3073 (ins RC:$src1, RC:$src2),
3074 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3075 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3076 IIC_SSE_UNPCK>, EVEX_4V;
3077 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3078 (ins RC:$src1, x86memop:$src2),
3079 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3080 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3081 (bitconvert (memop_frag addr:$src2)))))],
3082 IIC_SSE_UNPCK>, EVEX_4V;
3084 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3085 VR512, memopv16i32, i512mem>, EVEX_V512,
3086 EVEX_CD8<32, CD8VF>;
3087 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3088 VR512, memopv8i64, i512mem>, EVEX_V512,
3089 VEX_W, EVEX_CD8<64, CD8VF>;
3090 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3091 VR512, memopv16i32, i512mem>, EVEX_V512,
3092 EVEX_CD8<32, CD8VF>;
3093 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3094 VR512, memopv8i64, i512mem>, EVEX_V512,
3095 VEX_W, EVEX_CD8<64, CD8VF>;
3096 //===----------------------------------------------------------------------===//
3100 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3101 SDNode OpNode, PatFrag mem_frag,
3102 X86MemOperand x86memop, ValueType OpVT> {
3103 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3104 (ins RC:$src1, i8imm:$src2),
3105 !strconcat(OpcodeStr,
3106 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3108 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3110 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3111 (ins x86memop:$src1, i8imm:$src2),
3112 !strconcat(OpcodeStr,
3113 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3115 (OpVT (OpNode (mem_frag addr:$src1),
3116 (i8 imm:$src2))))]>, EVEX;
3119 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3120 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3122 //===----------------------------------------------------------------------===//
3123 // AVX-512 Logical Instructions
3124 //===----------------------------------------------------------------------===//
3126 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3127 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3128 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3129 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3130 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3131 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3132 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3133 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3135 //===----------------------------------------------------------------------===//
3136 // AVX-512 FP arithmetic
3137 //===----------------------------------------------------------------------===//
3139 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3141 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3142 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3143 EVEX_CD8<32, CD8VT1>;
3144 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3145 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3146 EVEX_CD8<64, CD8VT1>;
3149 let isCommutable = 1 in {
3150 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3151 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3152 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3153 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3155 let isCommutable = 0 in {
3156 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3157 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3160 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3161 X86VectorVTInfo _, bit IsCommutable> {
3162 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3163 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3164 "$src2, $src1", "$src1, $src2",
3165 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3166 let mayLoad = 1 in {
3167 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3168 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3169 "$src2, $src1", "$src1, $src2",
3170 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3171 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3172 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3173 "${src2}"##_.BroadcastStr##", $src1",
3174 "$src1, ${src2}"##_.BroadcastStr,
3175 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3176 (_.ScalarLdFrag addr:$src2))))>,
3181 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3182 bit IsCommutable = 0> {
3183 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3184 IsCommutable>, EVEX_V512, PS,
3185 EVEX_CD8<32, CD8VF>;
3186 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3187 IsCommutable>, EVEX_V512, PD, VEX_W,
3188 EVEX_CD8<64, CD8VF>;
3190 // Define only if AVX512VL feature is present.
3191 let Predicates = [HasVLX] in {
3192 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3193 IsCommutable>, EVEX_V128, PS,
3194 EVEX_CD8<32, CD8VF>;
3195 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3196 IsCommutable>, EVEX_V256, PS,
3197 EVEX_CD8<32, CD8VF>;
3198 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3199 IsCommutable>, EVEX_V128, PD, VEX_W,
3200 EVEX_CD8<64, CD8VF>;
3201 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3202 IsCommutable>, EVEX_V256, PD, VEX_W,
3203 EVEX_CD8<64, CD8VF>;
3207 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3208 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3209 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3210 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3211 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3212 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3214 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3215 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3216 (i16 -1), FROUND_CURRENT)),
3217 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3219 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3220 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3221 (i8 -1), FROUND_CURRENT)),
3222 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3224 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3225 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3226 (i16 -1), FROUND_CURRENT)),
3227 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3229 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3230 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3231 (i8 -1), FROUND_CURRENT)),
3232 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3233 //===----------------------------------------------------------------------===//
3234 // AVX-512 VPTESTM instructions
3235 //===----------------------------------------------------------------------===//
3237 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3238 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3239 SDNode OpNode, ValueType vt> {
3240 def rr : AVX512PI<opc, MRMSrcReg,
3241 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3242 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3243 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3244 SSEPackedInt>, EVEX_4V;
3245 def rm : AVX512PI<opc, MRMSrcMem,
3246 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3247 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3248 [(set KRC:$dst, (OpNode (vt RC:$src1),
3249 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3252 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3253 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3254 EVEX_CD8<32, CD8VF>;
3255 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3256 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3257 EVEX_CD8<64, CD8VF>;
3259 let Predicates = [HasCDI] in {
3260 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3261 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3262 EVEX_CD8<32, CD8VF>;
3263 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3264 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3265 EVEX_CD8<64, CD8VF>;
3268 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3269 (v16i32 VR512:$src2), (i16 -1))),
3270 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3272 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3273 (v8i64 VR512:$src2), (i8 -1))),
3274 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3276 //===----------------------------------------------------------------------===//
3277 // AVX-512 Shift instructions
3278 //===----------------------------------------------------------------------===//
3279 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3280 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3281 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3282 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3283 "$src2, $src1", "$src1, $src2",
3284 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3285 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3286 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3287 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3288 "$src2, $src1", "$src1, $src2",
3289 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3290 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3293 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3294 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3295 // src2 is always 128-bit
3296 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3297 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3298 "$src2, $src1", "$src1, $src2",
3299 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3300 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3301 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3302 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3303 "$src2, $src1", "$src1, $src2",
3304 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3305 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3308 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3309 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3310 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3313 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3315 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3316 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3317 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3318 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3321 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3323 EVEX_V512, EVEX_CD8<32, CD8VF>;
3324 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3325 v8i64_info>, EVEX_V512,
3326 EVEX_CD8<64, CD8VF>, VEX_W;
3328 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3329 v16i32_info>, EVEX_V512,
3330 EVEX_CD8<32, CD8VF>;
3331 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3332 v8i64_info>, EVEX_V512,
3333 EVEX_CD8<64, CD8VF>, VEX_W;
3335 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3337 EVEX_V512, EVEX_CD8<32, CD8VF>;
3338 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3339 v8i64_info>, EVEX_V512,
3340 EVEX_CD8<64, CD8VF>, VEX_W;
3342 defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3343 defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3344 defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3346 //===-------------------------------------------------------------------===//
3347 // Variable Bit Shifts
3348 //===-------------------------------------------------------------------===//
3349 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3350 X86VectorVTInfo _> {
3351 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3352 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3353 "$src2, $src1", "$src1, $src2",
3354 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3355 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3356 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3357 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3358 "$src2, $src1", "$src1, $src2",
3359 (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2))),
3360 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
3363 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3364 AVX512VLVectorVTInfo _> {
3365 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3368 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3370 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3371 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
3372 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3373 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3376 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
3377 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
3378 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
3380 //===----------------------------------------------------------------------===//
3381 // AVX-512 - MOVDDUP
3382 //===----------------------------------------------------------------------===//
3384 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3385 X86MemOperand x86memop, PatFrag memop_frag> {
3386 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3387 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3388 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3389 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3390 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3392 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3395 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3396 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3397 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3398 (VMOVDDUPZrm addr:$src)>;
3400 //===---------------------------------------------------------------------===//
3401 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3402 //===---------------------------------------------------------------------===//
3403 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3404 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3405 X86MemOperand x86memop> {
3406 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3407 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3408 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3410 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3411 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3412 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3415 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3416 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3417 EVEX_CD8<32, CD8VF>;
3418 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3419 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3420 EVEX_CD8<32, CD8VF>;
3422 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3423 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3424 (VMOVSHDUPZrm addr:$src)>;
3425 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3426 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3427 (VMOVSLDUPZrm addr:$src)>;
3429 //===----------------------------------------------------------------------===//
3430 // Move Low to High and High to Low packed FP Instructions
3431 //===----------------------------------------------------------------------===//
3432 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3433 (ins VR128X:$src1, VR128X:$src2),
3434 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3435 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3436 IIC_SSE_MOV_LH>, EVEX_4V;
3437 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3438 (ins VR128X:$src1, VR128X:$src2),
3439 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3440 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3441 IIC_SSE_MOV_LH>, EVEX_4V;
3443 let Predicates = [HasAVX512] in {
3445 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3446 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3447 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3448 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3451 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3452 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3455 //===----------------------------------------------------------------------===//
3456 // FMA - Fused Multiply Operations
3459 let Constraints = "$src1 = $dst" in {
3460 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3461 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3462 SDPatternOperator OpNode = null_frag> {
3463 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3464 (ins _.RC:$src2, _.RC:$src3),
3465 OpcodeStr, "$src3, $src2", "$src2, $src3",
3466 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3470 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3471 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3472 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3473 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3474 (_.MemOpFrag addr:$src3))))]>;
3475 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3476 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3477 !strconcat(OpcodeStr, "\t{${src3}", _.BroadcastStr,
3478 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3479 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3480 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3482 } // Constraints = "$src1 = $dst"
3484 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3485 string OpcodeStr, X86VectorVTInfo VTI,
3486 SDPatternOperator OpNode> {
3487 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3489 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3491 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3493 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3496 let ExeDomain = SSEPackedSingle in {
3497 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3498 v16f32_info, X86Fmadd>;
3499 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3500 v16f32_info, X86Fmsub>;
3501 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3502 v16f32_info, X86Fmaddsub>;
3503 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3504 v16f32_info, X86Fmsubadd>;
3505 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3506 v16f32_info, X86Fnmadd>;
3507 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3508 v16f32_info, X86Fnmsub>;
3510 let ExeDomain = SSEPackedDouble in {
3511 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3512 v8f64_info, X86Fmadd>, VEX_W;
3513 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3514 v8f64_info, X86Fmsub>, VEX_W;
3515 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3516 v8f64_info, X86Fmaddsub>, VEX_W;
3517 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3518 v8f64_info, X86Fmsubadd>, VEX_W;
3519 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3520 v8f64_info, X86Fnmadd>, VEX_W;
3521 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3522 v8f64_info, X86Fnmsub>, VEX_W;
3525 let Constraints = "$src1 = $dst" in {
3526 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3527 X86VectorVTInfo _> {
3529 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3530 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3531 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3532 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3534 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3535 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3536 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3537 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3539 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3540 (_.ScalarLdFrag addr:$src2))),
3541 _.RC:$src3))]>, EVEX_B;
3543 } // Constraints = "$src1 = $dst"
3546 let ExeDomain = SSEPackedSingle in {
3547 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3549 EVEX_V512, EVEX_CD8<32, CD8VF>;
3550 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3552 EVEX_V512, EVEX_CD8<32, CD8VF>;
3553 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3555 EVEX_V512, EVEX_CD8<32, CD8VF>;
3556 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3558 EVEX_V512, EVEX_CD8<32, CD8VF>;
3559 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3561 EVEX_V512, EVEX_CD8<32, CD8VF>;
3562 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3564 EVEX_V512, EVEX_CD8<32, CD8VF>;
3566 let ExeDomain = SSEPackedDouble in {
3567 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3569 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3570 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3572 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3573 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3575 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3576 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3578 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3579 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3581 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3582 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3584 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3588 let Constraints = "$src1 = $dst" in {
3589 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3590 RegisterClass RC, ValueType OpVT,
3591 X86MemOperand x86memop, Operand memop,
3593 let isCommutable = 1 in
3594 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3595 (ins RC:$src1, RC:$src2, RC:$src3),
3596 !strconcat(OpcodeStr,
3597 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3599 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3601 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3602 (ins RC:$src1, RC:$src2, f128mem:$src3),
3603 !strconcat(OpcodeStr,
3604 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3606 (OpVT (OpNode RC:$src2, RC:$src1,
3607 (mem_frag addr:$src3))))]>;
3610 } // Constraints = "$src1 = $dst"
3612 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3613 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3614 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3615 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3616 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3617 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3618 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3619 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3620 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3621 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3622 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3623 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3624 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3625 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3626 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3627 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3629 //===----------------------------------------------------------------------===//
3630 // AVX-512 Scalar convert from sign integer to float/double
3631 //===----------------------------------------------------------------------===//
3633 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3634 X86MemOperand x86memop, string asm> {
3635 let hasSideEffects = 0 in {
3636 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3637 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3640 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3641 (ins DstRC:$src1, x86memop:$src),
3642 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3644 } // hasSideEffects = 0
3646 let Predicates = [HasAVX512] in {
3647 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3648 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3649 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3650 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3651 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3652 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3653 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3654 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3656 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3657 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3658 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3659 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3660 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3661 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3662 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3663 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3665 def : Pat<(f32 (sint_to_fp GR32:$src)),
3666 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3667 def : Pat<(f32 (sint_to_fp GR64:$src)),
3668 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3669 def : Pat<(f64 (sint_to_fp GR32:$src)),
3670 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3671 def : Pat<(f64 (sint_to_fp GR64:$src)),
3672 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3674 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3675 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3676 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3677 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3678 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3679 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3680 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3681 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3683 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3684 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3685 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3686 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3687 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3688 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3689 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3690 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3692 def : Pat<(f32 (uint_to_fp GR32:$src)),
3693 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3694 def : Pat<(f32 (uint_to_fp GR64:$src)),
3695 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3696 def : Pat<(f64 (uint_to_fp GR32:$src)),
3697 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3698 def : Pat<(f64 (uint_to_fp GR64:$src)),
3699 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3702 //===----------------------------------------------------------------------===//
3703 // AVX-512 Scalar convert from float/double to integer
3704 //===----------------------------------------------------------------------===//
3705 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3706 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3708 let hasSideEffects = 0 in {
3709 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3710 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3711 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3712 Requires<[HasAVX512]>;
3714 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3715 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3716 Requires<[HasAVX512]>;
3717 } // hasSideEffects = 0
3719 let Predicates = [HasAVX512] in {
3720 // Convert float/double to signed/unsigned int 32/64
3721 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3722 ssmem, sse_load_f32, "cvtss2si">,
3723 XS, EVEX_CD8<32, CD8VT1>;
3724 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3725 ssmem, sse_load_f32, "cvtss2si">,
3726 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3727 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3728 ssmem, sse_load_f32, "cvtss2usi">,
3729 XS, EVEX_CD8<32, CD8VT1>;
3730 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3731 int_x86_avx512_cvtss2usi64, ssmem,
3732 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3733 EVEX_CD8<32, CD8VT1>;
3734 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3735 sdmem, sse_load_f64, "cvtsd2si">,
3736 XD, EVEX_CD8<64, CD8VT1>;
3737 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3738 sdmem, sse_load_f64, "cvtsd2si">,
3739 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3740 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3741 sdmem, sse_load_f64, "cvtsd2usi">,
3742 XD, EVEX_CD8<64, CD8VT1>;
3743 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3744 int_x86_avx512_cvtsd2usi64, sdmem,
3745 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3746 EVEX_CD8<64, CD8VT1>;
3748 let isCodeGenOnly = 1 in {
3749 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3750 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3751 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3752 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3753 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3754 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3755 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3756 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3757 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3758 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3759 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3760 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3762 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3763 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3764 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3765 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3766 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3767 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3768 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3769 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3770 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3771 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3772 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3773 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3774 } // isCodeGenOnly = 1
3776 // Convert float/double to signed/unsigned int 32/64 with truncation
3777 let isCodeGenOnly = 1 in {
3778 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3779 ssmem, sse_load_f32, "cvttss2si">,
3780 XS, EVEX_CD8<32, CD8VT1>;
3781 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3782 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3783 "cvttss2si">, XS, VEX_W,
3784 EVEX_CD8<32, CD8VT1>;
3785 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3786 sdmem, sse_load_f64, "cvttsd2si">, XD,
3787 EVEX_CD8<64, CD8VT1>;
3788 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3789 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3790 "cvttsd2si">, XD, VEX_W,
3791 EVEX_CD8<64, CD8VT1>;
3792 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3793 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3794 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3795 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3796 int_x86_avx512_cvttss2usi64, ssmem,
3797 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3798 EVEX_CD8<32, CD8VT1>;
3799 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3800 int_x86_avx512_cvttsd2usi,
3801 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3802 EVEX_CD8<64, CD8VT1>;
3803 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3804 int_x86_avx512_cvttsd2usi64, sdmem,
3805 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3806 EVEX_CD8<64, CD8VT1>;
3807 } // isCodeGenOnly = 1
3809 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3810 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3812 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3813 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3814 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3815 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3816 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3817 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3820 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3821 loadf32, "cvttss2si">, XS,
3822 EVEX_CD8<32, CD8VT1>;
3823 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3824 loadf32, "cvttss2usi">, XS,
3825 EVEX_CD8<32, CD8VT1>;
3826 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3827 loadf32, "cvttss2si">, XS, VEX_W,
3828 EVEX_CD8<32, CD8VT1>;
3829 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3830 loadf32, "cvttss2usi">, XS, VEX_W,
3831 EVEX_CD8<32, CD8VT1>;
3832 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3833 loadf64, "cvttsd2si">, XD,
3834 EVEX_CD8<64, CD8VT1>;
3835 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3836 loadf64, "cvttsd2usi">, XD,
3837 EVEX_CD8<64, CD8VT1>;
3838 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3839 loadf64, "cvttsd2si">, XD, VEX_W,
3840 EVEX_CD8<64, CD8VT1>;
3841 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3842 loadf64, "cvttsd2usi">, XD, VEX_W,
3843 EVEX_CD8<64, CD8VT1>;
3845 //===----------------------------------------------------------------------===//
3846 // AVX-512 Convert form float to double and back
3847 //===----------------------------------------------------------------------===//
3848 let hasSideEffects = 0 in {
3849 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3850 (ins FR32X:$src1, FR32X:$src2),
3851 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3852 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3854 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3855 (ins FR32X:$src1, f32mem:$src2),
3856 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3857 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3858 EVEX_CD8<32, CD8VT1>;
3860 // Convert scalar double to scalar single
3861 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3862 (ins FR64X:$src1, FR64X:$src2),
3863 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3864 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3866 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3867 (ins FR64X:$src1, f64mem:$src2),
3868 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3869 []>, EVEX_4V, VEX_LIG, VEX_W,
3870 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3873 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3874 Requires<[HasAVX512]>;
3875 def : Pat<(fextend (loadf32 addr:$src)),
3876 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3878 def : Pat<(extloadf32 addr:$src),
3879 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3880 Requires<[HasAVX512, OptForSize]>;
3882 def : Pat<(extloadf32 addr:$src),
3883 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3884 Requires<[HasAVX512, OptForSpeed]>;
3886 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3887 Requires<[HasAVX512]>;
3889 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3890 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3891 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3893 let hasSideEffects = 0 in {
3894 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3895 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3897 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3898 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3899 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3900 [], d>, EVEX, EVEX_B, EVEX_RC;
3902 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3903 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3905 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3906 } // hasSideEffects = 0
3909 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3910 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3911 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3913 let hasSideEffects = 0 in {
3914 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3915 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3917 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3919 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3920 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3922 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3923 } // hasSideEffects = 0
3926 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3927 memopv8f64, f512mem, v8f32, v8f64,
3928 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3929 EVEX_CD8<64, CD8VF>;
3931 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3932 memopv4f64, f256mem, v8f64, v8f32,
3933 SSEPackedDouble>, EVEX_V512, PS,
3934 EVEX_CD8<32, CD8VH>;
3935 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3936 (VCVTPS2PDZrm addr:$src)>;
3938 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3939 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3940 (VCVTPD2PSZrr VR512:$src)>;
3942 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3943 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3944 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3946 //===----------------------------------------------------------------------===//
3947 // AVX-512 Vector convert from sign integer to float/double
3948 //===----------------------------------------------------------------------===//
3950 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3951 memopv8i64, i512mem, v16f32, v16i32,
3952 SSEPackedSingle>, EVEX_V512, PS,
3953 EVEX_CD8<32, CD8VF>;
3955 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3956 memopv4i64, i256mem, v8f64, v8i32,
3957 SSEPackedDouble>, EVEX_V512, XS,
3958 EVEX_CD8<32, CD8VH>;
3960 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3961 memopv16f32, f512mem, v16i32, v16f32,
3962 SSEPackedSingle>, EVEX_V512, XS,
3963 EVEX_CD8<32, CD8VF>;
3965 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3966 memopv8f64, f512mem, v8i32, v8f64,
3967 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3968 EVEX_CD8<64, CD8VF>;
3970 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3971 memopv16f32, f512mem, v16i32, v16f32,
3972 SSEPackedSingle>, EVEX_V512, PS,
3973 EVEX_CD8<32, CD8VF>;
3975 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3976 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3977 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3978 (VCVTTPS2UDQZrr VR512:$src)>;
3980 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3981 memopv8f64, f512mem, v8i32, v8f64,
3982 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3983 EVEX_CD8<64, CD8VF>;
3985 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3986 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3987 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3988 (VCVTTPD2UDQZrr VR512:$src)>;
3990 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3991 memopv4i64, f256mem, v8f64, v8i32,
3992 SSEPackedDouble>, EVEX_V512, XS,
3993 EVEX_CD8<32, CD8VH>;
3995 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3996 memopv16i32, f512mem, v16f32, v16i32,
3997 SSEPackedSingle>, EVEX_V512, XD,
3998 EVEX_CD8<32, CD8VF>;
4000 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4001 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4002 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4004 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4005 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4006 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4008 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4009 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4010 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4012 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4013 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4014 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4016 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4017 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4018 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4020 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4021 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4022 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4023 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4024 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4025 (VCVTDQ2PDZrr VR256X:$src)>;
4026 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4027 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4028 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4029 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4030 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4031 (VCVTUDQ2PDZrr VR256X:$src)>;
4033 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4034 RegisterClass DstRC, PatFrag mem_frag,
4035 X86MemOperand x86memop, Domain d> {
4036 let hasSideEffects = 0 in {
4037 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4038 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4040 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4041 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4042 [], d>, EVEX, EVEX_B, EVEX_RC;
4044 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4045 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4047 } // hasSideEffects = 0
4050 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4051 memopv16f32, f512mem, SSEPackedSingle>, PD,
4052 EVEX_V512, EVEX_CD8<32, CD8VF>;
4053 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4054 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4055 EVEX_V512, EVEX_CD8<64, CD8VF>;
4057 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4058 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4059 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4061 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4062 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4063 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4065 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4066 memopv16f32, f512mem, SSEPackedSingle>,
4067 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4068 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4069 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4070 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4072 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4073 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4074 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4076 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4077 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4078 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4080 let Predicates = [HasAVX512] in {
4081 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4082 (VCVTPD2PSZrm addr:$src)>;
4083 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4084 (VCVTPS2PDZrm addr:$src)>;
4087 //===----------------------------------------------------------------------===//
4088 // Half precision conversion instructions
4089 //===----------------------------------------------------------------------===//
4090 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4091 X86MemOperand x86memop> {
4092 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4093 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4095 let hasSideEffects = 0, mayLoad = 1 in
4096 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4097 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4100 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4101 X86MemOperand x86memop> {
4102 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4103 (ins srcRC:$src1, i32i8imm:$src2),
4104 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4106 let hasSideEffects = 0, mayStore = 1 in
4107 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4108 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
4109 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4112 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4113 EVEX_CD8<32, CD8VH>;
4114 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4115 EVEX_CD8<32, CD8VH>;
4117 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4118 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4119 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4121 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4122 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4123 (VCVTPH2PSZrr VR256X:$src)>;
4125 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4126 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4127 "ucomiss">, PS, EVEX, VEX_LIG,
4128 EVEX_CD8<32, CD8VT1>;
4129 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4130 "ucomisd">, PD, EVEX,
4131 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4132 let Pattern = []<dag> in {
4133 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4134 "comiss">, PS, EVEX, VEX_LIG,
4135 EVEX_CD8<32, CD8VT1>;
4136 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4137 "comisd">, PD, EVEX,
4138 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4140 let isCodeGenOnly = 1 in {
4141 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4142 load, "ucomiss">, PS, EVEX, VEX_LIG,
4143 EVEX_CD8<32, CD8VT1>;
4144 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4145 load, "ucomisd">, PD, EVEX,
4146 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4148 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4149 load, "comiss">, PS, EVEX, VEX_LIG,
4150 EVEX_CD8<32, CD8VT1>;
4151 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4152 load, "comisd">, PD, EVEX,
4153 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4157 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4158 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4159 X86MemOperand x86memop> {
4160 let hasSideEffects = 0 in {
4161 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4162 (ins RC:$src1, RC:$src2),
4163 !strconcat(OpcodeStr,
4164 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4165 let mayLoad = 1 in {
4166 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4167 (ins RC:$src1, x86memop:$src2),
4168 !strconcat(OpcodeStr,
4169 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4174 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4175 EVEX_CD8<32, CD8VT1>;
4176 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4177 VEX_W, EVEX_CD8<64, CD8VT1>;
4178 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4179 EVEX_CD8<32, CD8VT1>;
4180 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4181 VEX_W, EVEX_CD8<64, CD8VT1>;
4183 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4184 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4185 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4186 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4188 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4189 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4190 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4191 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4193 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4194 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4195 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4196 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4198 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4199 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4200 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4201 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4203 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4204 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4205 X86VectorVTInfo _> {
4206 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4207 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4208 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4209 let mayLoad = 1 in {
4210 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4211 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4213 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4214 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4215 (ins _.ScalarMemOp:$src), OpcodeStr,
4216 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4218 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4223 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4224 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4225 EVEX_V512, EVEX_CD8<32, CD8VF>;
4226 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4227 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4229 // Define only if AVX512VL feature is present.
4230 let Predicates = [HasVLX] in {
4231 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4232 OpNode, v4f32x_info>,
4233 EVEX_V128, EVEX_CD8<32, CD8VF>;
4234 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4235 OpNode, v8f32x_info>,
4236 EVEX_V256, EVEX_CD8<32, CD8VF>;
4237 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4238 OpNode, v2f64x_info>,
4239 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4240 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4241 OpNode, v4f64x_info>,
4242 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4246 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4247 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4249 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4250 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4251 (VRSQRT14PSZr VR512:$src)>;
4252 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4253 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4254 (VRSQRT14PDZr VR512:$src)>;
4256 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4257 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4258 (VRCP14PSZr VR512:$src)>;
4259 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4260 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4261 (VRCP14PDZr VR512:$src)>;
4263 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4264 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4267 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4268 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4269 "$src2, $src1", "$src1, $src2",
4270 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4271 (i32 FROUND_CURRENT))>;
4273 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4274 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4275 "$src2, $src1", "$src1, $src2",
4276 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4277 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4279 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4280 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4281 "$src2, $src1", "$src1, $src2",
4282 (OpNode (_.VT _.RC:$src1),
4283 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4284 (i32 FROUND_CURRENT))>;
4287 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4288 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4289 EVEX_CD8<32, CD8VT1>;
4290 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4291 EVEX_CD8<64, CD8VT1>, VEX_W;
4294 let hasSideEffects = 0, Predicates = [HasERI] in {
4295 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4296 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4298 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4300 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4303 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4304 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4305 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4307 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4308 (ins _.RC:$src), OpcodeStr,
4310 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4313 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4314 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4316 (bitconvert (_.LdFrag addr:$src))),
4317 (i32 FROUND_CURRENT))>;
4319 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4320 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4322 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4323 (i32 FROUND_CURRENT))>, EVEX_B;
4326 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4327 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4328 EVEX_CD8<32, CD8VF>;
4329 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4330 VEX_W, EVEX_CD8<32, CD8VF>;
4333 let Predicates = [HasERI], hasSideEffects = 0 in {
4335 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4336 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4337 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4340 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4341 SDNode OpNode, X86VectorVTInfo _>{
4342 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4343 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4344 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4345 let mayLoad = 1 in {
4346 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4347 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4349 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4351 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4352 (ins _.ScalarMemOp:$src), OpcodeStr,
4353 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4355 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4360 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4361 Intrinsic F32Int, Intrinsic F64Int,
4362 OpndItins itins_s, OpndItins itins_d> {
4363 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4364 (ins FR32X:$src1, FR32X:$src2),
4365 !strconcat(OpcodeStr,
4366 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4367 [], itins_s.rr>, XS, EVEX_4V;
4368 let isCodeGenOnly = 1 in
4369 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4370 (ins VR128X:$src1, VR128X:$src2),
4371 !strconcat(OpcodeStr,
4372 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4374 (F32Int VR128X:$src1, VR128X:$src2))],
4375 itins_s.rr>, XS, EVEX_4V;
4376 let mayLoad = 1 in {
4377 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4378 (ins FR32X:$src1, f32mem:$src2),
4379 !strconcat(OpcodeStr,
4380 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4381 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4382 let isCodeGenOnly = 1 in
4383 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4384 (ins VR128X:$src1, ssmem:$src2),
4385 !strconcat(OpcodeStr,
4386 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4388 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4389 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4391 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4392 (ins FR64X:$src1, FR64X:$src2),
4393 !strconcat(OpcodeStr,
4394 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4396 let isCodeGenOnly = 1 in
4397 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4398 (ins VR128X:$src1, VR128X:$src2),
4399 !strconcat(OpcodeStr,
4400 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4402 (F64Int VR128X:$src1, VR128X:$src2))],
4403 itins_s.rr>, XD, EVEX_4V, VEX_W;
4404 let mayLoad = 1 in {
4405 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4406 (ins FR64X:$src1, f64mem:$src2),
4407 !strconcat(OpcodeStr,
4408 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4409 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4410 let isCodeGenOnly = 1 in
4411 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4412 (ins VR128X:$src1, sdmem:$src2),
4413 !strconcat(OpcodeStr,
4414 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4416 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4417 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4421 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4423 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4425 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4426 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4428 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4429 // Define only if AVX512VL feature is present.
4430 let Predicates = [HasVLX] in {
4431 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4432 OpNode, v4f32x_info>,
4433 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4434 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4435 OpNode, v8f32x_info>,
4436 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4437 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4438 OpNode, v2f64x_info>,
4439 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4440 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4441 OpNode, v4f64x_info>,
4442 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4446 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4448 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4449 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4450 SSE_SQRTSS, SSE_SQRTSD>;
4452 let Predicates = [HasAVX512] in {
4453 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4454 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4455 (VSQRTPSZr VR512:$src1)>;
4456 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4457 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4458 (VSQRTPDZr VR512:$src1)>;
4460 def : Pat<(f32 (fsqrt FR32X:$src)),
4461 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4462 def : Pat<(f32 (fsqrt (load addr:$src))),
4463 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4464 Requires<[OptForSize]>;
4465 def : Pat<(f64 (fsqrt FR64X:$src)),
4466 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4467 def : Pat<(f64 (fsqrt (load addr:$src))),
4468 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4469 Requires<[OptForSize]>;
4471 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4472 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4473 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4474 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4475 Requires<[OptForSize]>;
4477 def : Pat<(f32 (X86frcp FR32X:$src)),
4478 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4479 def : Pat<(f32 (X86frcp (load addr:$src))),
4480 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4481 Requires<[OptForSize]>;
4483 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4484 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4485 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4487 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4488 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4490 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4491 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4492 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4494 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4495 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4499 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4500 X86MemOperand x86memop, RegisterClass RC,
4501 PatFrag mem_frag32, PatFrag mem_frag64,
4502 Intrinsic V4F32Int, Intrinsic V2F64Int,
4504 let ExeDomain = SSEPackedSingle in {
4505 // Intrinsic operation, reg.
4506 // Vector intrinsic operation, reg
4507 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4508 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4509 !strconcat(OpcodeStr,
4510 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4511 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4513 // Vector intrinsic operation, mem
4514 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4515 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4516 !strconcat(OpcodeStr,
4517 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4519 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4520 EVEX_CD8<32, VForm>;
4521 } // ExeDomain = SSEPackedSingle
4523 let ExeDomain = SSEPackedDouble in {
4524 // Vector intrinsic operation, reg
4525 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4526 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4527 !strconcat(OpcodeStr,
4528 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4529 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4531 // Vector intrinsic operation, mem
4532 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4533 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4534 !strconcat(OpcodeStr,
4535 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4537 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4538 EVEX_CD8<64, VForm>;
4539 } // ExeDomain = SSEPackedDouble
4542 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4546 let ExeDomain = GenericDomain in {
4548 let hasSideEffects = 0 in
4549 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4550 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4551 !strconcat(OpcodeStr,
4552 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4555 // Intrinsic operation, reg.
4556 let isCodeGenOnly = 1 in
4557 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4558 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4559 !strconcat(OpcodeStr,
4560 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4561 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4563 // Intrinsic operation, mem.
4564 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4565 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4566 !strconcat(OpcodeStr,
4567 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4568 [(set VR128X:$dst, (F32Int VR128X:$src1,
4569 sse_load_f32:$src2, imm:$src3))]>,
4570 EVEX_CD8<32, CD8VT1>;
4573 let hasSideEffects = 0 in
4574 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4575 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4576 !strconcat(OpcodeStr,
4577 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4580 // Intrinsic operation, reg.
4581 let isCodeGenOnly = 1 in
4582 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4583 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4584 !strconcat(OpcodeStr,
4585 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4586 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4589 // Intrinsic operation, mem.
4590 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4591 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4592 !strconcat(OpcodeStr,
4593 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4595 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4596 VEX_W, EVEX_CD8<64, CD8VT1>;
4597 } // ExeDomain = GenericDomain
4600 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4601 X86MemOperand x86memop, RegisterClass RC,
4602 PatFrag mem_frag, Domain d> {
4603 let ExeDomain = d in {
4604 // Intrinsic operation, reg.
4605 // Vector intrinsic operation, reg
4606 def r : AVX512AIi8<opc, MRMSrcReg,
4607 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4608 !strconcat(OpcodeStr,
4609 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4612 // Vector intrinsic operation, mem
4613 def m : AVX512AIi8<opc, MRMSrcMem,
4614 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4615 !strconcat(OpcodeStr,
4616 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4622 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4623 memopv16f32, SSEPackedSingle>, EVEX_V512,
4624 EVEX_CD8<32, CD8VF>;
4626 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4627 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4629 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4632 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4633 memopv8f64, SSEPackedDouble>, EVEX_V512,
4634 VEX_W, EVEX_CD8<64, CD8VF>;
4636 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4637 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4639 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4641 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4642 Operand x86memop, RegisterClass RC, Domain d> {
4643 let ExeDomain = d in {
4644 def r : AVX512AIi8<opc, MRMSrcReg,
4645 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4646 !strconcat(OpcodeStr,
4647 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4650 def m : AVX512AIi8<opc, MRMSrcMem,
4651 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4652 !strconcat(OpcodeStr,
4653 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4658 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4659 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4661 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4662 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4664 def : Pat<(ffloor FR32X:$src),
4665 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4666 def : Pat<(f64 (ffloor FR64X:$src)),
4667 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4668 def : Pat<(f32 (fnearbyint FR32X:$src)),
4669 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4670 def : Pat<(f64 (fnearbyint FR64X:$src)),
4671 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4672 def : Pat<(f32 (fceil FR32X:$src)),
4673 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4674 def : Pat<(f64 (fceil FR64X:$src)),
4675 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4676 def : Pat<(f32 (frint FR32X:$src)),
4677 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4678 def : Pat<(f64 (frint FR64X:$src)),
4679 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4680 def : Pat<(f32 (ftrunc FR32X:$src)),
4681 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4682 def : Pat<(f64 (ftrunc FR64X:$src)),
4683 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4685 def : Pat<(v16f32 (ffloor VR512:$src)),
4686 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4687 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4688 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4689 def : Pat<(v16f32 (fceil VR512:$src)),
4690 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4691 def : Pat<(v16f32 (frint VR512:$src)),
4692 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4693 def : Pat<(v16f32 (ftrunc VR512:$src)),
4694 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4696 def : Pat<(v8f64 (ffloor VR512:$src)),
4697 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4698 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4699 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4700 def : Pat<(v8f64 (fceil VR512:$src)),
4701 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4702 def : Pat<(v8f64 (frint VR512:$src)),
4703 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4704 def : Pat<(v8f64 (ftrunc VR512:$src)),
4705 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4707 //-------------------------------------------------
4708 // Integer truncate and extend operations
4709 //-------------------------------------------------
4711 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4712 RegisterClass dstRC, RegisterClass srcRC,
4713 RegisterClass KRC, X86MemOperand x86memop> {
4714 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4716 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4719 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4720 (ins KRC:$mask, srcRC:$src),
4721 !strconcat(OpcodeStr,
4722 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4725 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4726 (ins KRC:$mask, srcRC:$src),
4727 !strconcat(OpcodeStr,
4728 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4731 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4732 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4735 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4736 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4737 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4741 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4742 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4743 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4744 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4745 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4746 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4747 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4748 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4749 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4750 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4751 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4752 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4753 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4754 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4755 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4756 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4757 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4758 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4759 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4760 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4761 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4762 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4763 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4764 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4765 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4766 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4767 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4768 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4769 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4770 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4772 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4773 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4774 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4775 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4776 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4778 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4779 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4780 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4781 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4782 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4783 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4784 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4785 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4788 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4789 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4790 PatFrag mem_frag, X86MemOperand x86memop,
4791 ValueType OpVT, ValueType InVT> {
4793 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4795 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4796 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4798 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4799 (ins KRC:$mask, SrcRC:$src),
4800 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4803 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4804 (ins KRC:$mask, SrcRC:$src),
4805 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4808 let mayLoad = 1 in {
4809 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4810 (ins x86memop:$src),
4811 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4813 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4816 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4817 (ins KRC:$mask, x86memop:$src),
4818 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4822 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4823 (ins KRC:$mask, x86memop:$src),
4824 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4830 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4831 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4833 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4834 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4836 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4837 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4838 EVEX_CD8<16, CD8VH>;
4839 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4840 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4841 EVEX_CD8<16, CD8VQ>;
4842 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4843 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4844 EVEX_CD8<32, CD8VH>;
4846 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4847 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4849 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4850 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4852 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4853 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4854 EVEX_CD8<16, CD8VH>;
4855 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4856 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4857 EVEX_CD8<16, CD8VQ>;
4858 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4859 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4860 EVEX_CD8<32, CD8VH>;
4862 //===----------------------------------------------------------------------===//
4863 // GATHER - SCATTER Operations
4865 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4866 RegisterClass RC, X86MemOperand memop> {
4868 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4869 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4870 (ins RC:$src1, KRC:$mask, memop:$src2),
4871 !strconcat(OpcodeStr,
4872 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4876 let ExeDomain = SSEPackedDouble in {
4877 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4878 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4879 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4880 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4883 let ExeDomain = SSEPackedSingle in {
4884 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4885 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4886 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4887 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4890 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4891 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4892 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4893 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4895 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4896 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4897 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4898 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4900 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4901 RegisterClass RC, X86MemOperand memop> {
4902 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4903 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4904 (ins memop:$dst, KRC:$mask, RC:$src2),
4905 !strconcat(OpcodeStr,
4906 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4910 let ExeDomain = SSEPackedDouble in {
4911 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4912 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4913 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4914 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4917 let ExeDomain = SSEPackedSingle in {
4918 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4919 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4920 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4921 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4924 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4925 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4926 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4927 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4929 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4930 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4931 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4932 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4935 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4936 RegisterClass KRC, X86MemOperand memop> {
4937 let Predicates = [HasPFI], hasSideEffects = 1 in
4938 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4939 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4943 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4944 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4946 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4947 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4949 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4950 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4952 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4953 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4955 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4956 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4958 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4959 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4961 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4962 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4964 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4965 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4967 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4968 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4970 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4971 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4973 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4974 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4976 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4977 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4979 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4980 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4982 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4983 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4985 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4986 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4988 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4989 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4990 //===----------------------------------------------------------------------===//
4991 // VSHUFPS - VSHUFPD Operations
4993 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4994 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4996 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4997 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4998 !strconcat(OpcodeStr,
4999 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5000 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5001 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5002 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5003 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5004 (ins RC:$src1, RC:$src2, i8imm:$src3),
5005 !strconcat(OpcodeStr,
5006 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5007 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5008 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5009 EVEX_4V, Sched<[WriteShuffle]>;
5012 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
5013 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5014 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
5015 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5017 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5018 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5019 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5020 (memopv16i32 addr:$src2), (i8 imm:$imm))),
5021 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5023 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5024 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5025 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5026 (memopv8i64 addr:$src2), (i8 imm:$imm))),
5027 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5029 multiclass avx512_valign<X86VectorVTInfo _> {
5030 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5031 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
5033 "$src3, $src2, $src1", "$src1, $src2, $src3",
5034 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5036 AVX512AIi8Base, EVEX_4V;
5038 // Also match valign of packed floats.
5039 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5040 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5043 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5044 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
5045 !strconcat("valign"##_.Suffix,
5046 "\t{$src3, $src2, $src1, $dst|"
5047 "$dst, $src1, $src2, $src3}"),
5050 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5051 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5053 // Helper fragments to match sext vXi1 to vXiY.
5054 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5055 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5057 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5058 RegisterClass KRC, RegisterClass RC,
5059 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5061 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5062 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5064 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5065 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5067 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5068 !strconcat(OpcodeStr,
5069 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5071 let mayLoad = 1 in {
5072 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5073 (ins x86memop:$src),
5074 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5076 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5077 (ins KRC:$mask, x86memop:$src),
5078 !strconcat(OpcodeStr,
5079 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5081 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5082 (ins KRC:$mask, x86memop:$src),
5083 !strconcat(OpcodeStr,
5084 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5086 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5087 (ins x86scalar_mop:$src),
5088 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5089 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5091 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5092 (ins KRC:$mask, x86scalar_mop:$src),
5093 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5094 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5095 []>, EVEX, EVEX_B, EVEX_K;
5096 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5097 (ins KRC:$mask, x86scalar_mop:$src),
5098 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5099 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5101 []>, EVEX, EVEX_B, EVEX_KZ;
5105 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5106 i512mem, i32mem, "{1to16}">, EVEX_V512,
5107 EVEX_CD8<32, CD8VF>;
5108 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5109 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5110 EVEX_CD8<64, CD8VF>;
5113 (bc_v16i32 (v16i1sextv16i32)),
5114 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5115 (VPABSDZrr VR512:$src)>;
5117 (bc_v8i64 (v8i1sextv8i64)),
5118 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5119 (VPABSQZrr VR512:$src)>;
5121 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5122 (v16i32 immAllZerosV), (i16 -1))),
5123 (VPABSDZrr VR512:$src)>;
5124 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5125 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5126 (VPABSQZrr VR512:$src)>;
5128 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5129 RegisterClass RC, RegisterClass KRC,
5130 X86MemOperand x86memop,
5131 X86MemOperand x86scalar_mop, string BrdcstStr> {
5132 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5134 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5136 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5137 (ins x86memop:$src),
5138 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5140 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5141 (ins x86scalar_mop:$src),
5142 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5143 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5145 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5146 (ins KRC:$mask, RC:$src),
5147 !strconcat(OpcodeStr,
5148 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5150 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5151 (ins KRC:$mask, x86memop:$src),
5152 !strconcat(OpcodeStr,
5153 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5155 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5156 (ins KRC:$mask, x86scalar_mop:$src),
5157 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5158 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5160 []>, EVEX, EVEX_KZ, EVEX_B;
5162 let Constraints = "$src1 = $dst" in {
5163 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5164 (ins RC:$src1, KRC:$mask, RC:$src2),
5165 !strconcat(OpcodeStr,
5166 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5168 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5169 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5170 !strconcat(OpcodeStr,
5171 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5173 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5174 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5175 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5176 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5177 []>, EVEX, EVEX_K, EVEX_B;
5181 let Predicates = [HasCDI] in {
5182 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5183 i512mem, i32mem, "{1to16}">,
5184 EVEX_V512, EVEX_CD8<32, CD8VF>;
5187 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5188 i512mem, i64mem, "{1to8}">,
5189 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5193 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5195 (VPCONFLICTDrrk VR512:$src1,
5196 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5198 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5200 (VPCONFLICTQrrk VR512:$src1,
5201 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5203 let Predicates = [HasCDI] in {
5204 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5205 i512mem, i32mem, "{1to16}">,
5206 EVEX_V512, EVEX_CD8<32, CD8VF>;
5209 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5210 i512mem, i64mem, "{1to8}">,
5211 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5215 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5217 (VPLZCNTDrrk VR512:$src1,
5218 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5220 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5222 (VPLZCNTQrrk VR512:$src1,
5223 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5225 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5226 (VPLZCNTDrm addr:$src)>;
5227 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5228 (VPLZCNTDrr VR512:$src)>;
5229 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5230 (VPLZCNTQrm addr:$src)>;
5231 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5232 (VPLZCNTQrr VR512:$src)>;
5234 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5235 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5236 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5238 def : Pat<(store VK1:$src, addr:$dst),
5239 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5241 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5242 (truncstore node:$val, node:$ptr), [{
5243 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5246 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5247 (MOV8mr addr:$dst, GR8:$src)>;
5249 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5250 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5251 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5252 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5255 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5256 string OpcodeStr, Predicate prd> {
5257 let Predicates = [prd] in
5258 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5260 let Predicates = [prd, HasVLX] in {
5261 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5262 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5266 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5267 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5269 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5271 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5273 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5277 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5279 //===----------------------------------------------------------------------===//
5280 // AVX-512 - COMPRESS and EXPAND
5282 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5284 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5285 (ins _.KRCWM:$mask, _.RC:$src),
5286 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5287 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5288 _.ImmAllZerosV)))]>, EVEX_KZ;
5290 let Constraints = "$src0 = $dst" in
5291 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5292 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5293 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5294 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5295 _.RC:$src0)))]>, EVEX_K;
5297 let mayStore = 1 in {
5298 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5299 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5300 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5301 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5303 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5307 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5308 AVX512VLVectorVTInfo VTInfo> {
5309 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5311 let Predicates = [HasVLX] in {
5312 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5313 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5317 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5319 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5321 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5323 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,