1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
183 string MaskingConstraint = "",
184 InstrItinClass itin = NoItinerary,
185 bit IsCommutable = 0> {
186 let isCommutable = IsCommutable in
187 def NAME: AVX512<O, F, Outs, Ins,
188 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
189 "$dst , "#IntelSrcAsm#"}",
192 // Prefer over VMOV*rrk Pat<>
193 let AddedComplexity = 20 in
194 def NAME#k: AVX512<O, F, Outs, MaskingIns,
195 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
196 "$dst {${mask}}, "#IntelSrcAsm#"}",
197 MaskingPattern, itin>,
199 // In case of the 3src subclass this is overridden with a let.
200 string Constraints = MaskingConstraint;
202 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
203 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
204 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
205 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
212 // Common base class of AVX512_maskable and AVX512_maskable_3src.
213 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
215 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, dag MaskingRHS,
219 SDNode Select = vselect,
220 string MaskingConstraint = "",
221 InstrItinClass itin = NoItinerary,
222 bit IsCommutable = 0> :
223 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
224 AttSrcAsm, IntelSrcAsm,
225 [(set _.RC:$dst, RHS)],
226 [(set _.RC:$dst, MaskingRHS)],
228 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
229 MaskingConstraint, NoItinerary, IsCommutable>;
231 // This multiclass generates the unconditional/non-masking, the masking and
232 // the zero-masking variant of the vector instruction. In the masking case, the
233 // perserved vector elements come from a new dummy input operand tied to $dst.
234 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
235 dag Outs, dag Ins, string OpcodeStr,
236 string AttSrcAsm, string IntelSrcAsm,
238 InstrItinClass itin = NoItinerary,
239 bit IsCommutable = 0> :
240 AVX512_maskable_common<O, F, _, Outs, Ins,
241 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
242 !con((ins _.KRCWM:$mask), Ins),
243 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
244 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
245 "$src0 = $dst", itin, IsCommutable>;
247 // This multiclass generates the unconditional/non-masking, the masking and
248 // the zero-masking variant of the scalar instruction.
249 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
250 dag Outs, dag Ins, string OpcodeStr,
251 string AttSrcAsm, string IntelSrcAsm,
253 InstrItinClass itin = NoItinerary,
254 bit IsCommutable = 0> :
255 AVX512_maskable_common<O, F, _, Outs, Ins,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
257 !con((ins _.KRCWM:$mask), Ins),
258 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
259 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
260 "$src0 = $dst", itin, IsCommutable>;
262 // Similar to AVX512_maskable but in this case one of the source operands
263 // ($src1) is already tied to $dst so we just use that for the preserved
264 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
266 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
267 dag Outs, dag NonTiedIns, string OpcodeStr,
268 string AttSrcAsm, string IntelSrcAsm,
270 AVX512_maskable_common<O, F, _, Outs,
271 !con((ins _.RC:$src1), NonTiedIns),
272 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
275 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
277 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
278 dag Outs, dag NonTiedIns, string OpcodeStr,
279 string AttSrcAsm, string IntelSrcAsm,
281 AVX512_maskable_common<O, F, _, Outs,
282 !con((ins _.RC:$src1), NonTiedIns),
283 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
284 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
285 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
286 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
288 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
291 string AttSrcAsm, string IntelSrcAsm,
293 AVX512_maskable_custom<O, F, Outs, Ins,
294 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
295 !con((ins _.KRCWM:$mask), Ins),
296 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
300 // Instruction with mask that puts result in mask register,
301 // like "compare" and "vptest"
302 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
304 dag Ins, dag MaskingIns,
306 string AttSrcAsm, string IntelSrcAsm,
308 list<dag> MaskingPattern,
310 InstrItinClass itin = NoItinerary> {
311 def NAME: AVX512<O, F, Outs, Ins,
312 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
313 "$dst "#Round#", "#IntelSrcAsm#"}",
316 def NAME#k: AVX512<O, F, Outs, MaskingIns,
317 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
318 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
319 MaskingPattern, itin>, EVEX_K;
322 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
324 dag Ins, dag MaskingIns,
326 string AttSrcAsm, string IntelSrcAsm,
327 dag RHS, dag MaskingRHS,
329 InstrItinClass itin = NoItinerary> :
330 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
331 AttSrcAsm, IntelSrcAsm,
332 [(set _.KRC:$dst, RHS)],
333 [(set _.KRC:$dst, MaskingRHS)],
336 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
337 dag Outs, dag Ins, string OpcodeStr,
338 string AttSrcAsm, string IntelSrcAsm,
339 dag RHS, string Round = "",
340 InstrItinClass itin = NoItinerary> :
341 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
342 !con((ins _.KRCWM:$mask), Ins),
343 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
344 (and _.KRCWM:$mask, RHS),
347 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
348 dag Outs, dag Ins, string OpcodeStr,
349 string AttSrcAsm, string IntelSrcAsm> :
350 AVX512_maskable_custom_cmp<O, F, Outs,
351 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
352 AttSrcAsm, IntelSrcAsm,
353 [],[],"", NoItinerary>;
355 // Bitcasts between 512-bit vector types. Return the original type since
356 // no instruction is needed for the conversion
357 let Predicates = [HasAVX512] in {
358 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
359 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
360 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
364 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
369 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
374 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
379 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
385 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
391 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
392 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
396 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
401 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
406 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
411 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
416 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
421 // Bitcasts between 256-bit vector types. Return the original type since
422 // no instruction is needed for the conversion
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
456 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
459 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
460 isPseudo = 1, Predicates = [HasAVX512] in {
461 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
462 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
465 let Predicates = [HasAVX512] in {
466 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
467 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
468 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
471 //===----------------------------------------------------------------------===//
472 // AVX-512 - VECTOR INSERT
475 multiclass vinsert_for_size_no_alt<int Opcode,
476 X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert,
478 SDNodeXForm INSERT_get_vinsert_imm> {
479 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
480 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
481 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
482 "vinsert" # From.EltTypeName # "x" # From.NumElts #
483 "\t{$src3, $src2, $src1, $dst|"
484 "$dst, $src1, $src2, $src3}",
485 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
486 (From.VT From.RC:$src2),
491 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
492 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
493 "vinsert" # From.EltTypeName # "x" # From.NumElts #
494 "\t{$src3, $src2, $src1, $dst|"
495 "$dst, $src1, $src2, $src3}",
497 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
501 multiclass vinsert_for_size<int Opcode,
502 X86VectorVTInfo From, X86VectorVTInfo To,
503 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
504 PatFrag vinsert_insert,
505 SDNodeXForm INSERT_get_vinsert_imm> :
506 vinsert_for_size_no_alt<Opcode, From, To,
507 vinsert_insert, INSERT_get_vinsert_imm> {
508 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
509 // vinserti32x4. Only add this if 64x2 and friends are not supported
510 // natively via AVX512DQ.
511 let Predicates = [NoDQI] in
512 def : Pat<(vinsert_insert:$ins
513 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
514 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
515 VR512:$src1, From.RC:$src2,
516 (INSERT_get_vinsert_imm VR512:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
521 defm NAME # "32x4" : vinsert_for_size<Opcode128,
522 X86VectorVTInfo< 4, EltVT32, VR128X>,
523 X86VectorVTInfo<16, EltVT32, VR512>,
524 X86VectorVTInfo< 2, EltVT64, VR128X>,
525 X86VectorVTInfo< 8, EltVT64, VR512>,
527 INSERT_get_vinsert128_imm>;
528 let Predicates = [HasDQI] in
529 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
530 X86VectorVTInfo< 2, EltVT64, VR128X>,
531 X86VectorVTInfo< 8, EltVT64, VR512>,
533 INSERT_get_vinsert128_imm>, VEX_W;
534 defm NAME # "64x4" : vinsert_for_size<Opcode256,
535 X86VectorVTInfo< 4, EltVT64, VR256X>,
536 X86VectorVTInfo< 8, EltVT64, VR512>,
537 X86VectorVTInfo< 8, EltVT32, VR256>,
538 X86VectorVTInfo<16, EltVT32, VR512>,
540 INSERT_get_vinsert256_imm>, VEX_W;
541 let Predicates = [HasDQI] in
542 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
543 X86VectorVTInfo< 8, EltVT32, VR256X>,
544 X86VectorVTInfo<16, EltVT32, VR512>,
546 INSERT_get_vinsert256_imm>;
549 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
550 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
552 // vinsertps - insert f32 to XMM
553 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
554 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
555 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
556 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
558 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
559 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
560 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
561 [(set VR128X:$dst, (X86insertps VR128X:$src1,
562 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
563 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
565 //===----------------------------------------------------------------------===//
566 // AVX-512 VECTOR EXTRACT
569 multiclass vextract_for_size<int Opcode,
570 X86VectorVTInfo From, X86VectorVTInfo To,
571 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
572 PatFrag vextract_extract,
573 SDNodeXForm EXTRACT_get_vextract_imm> {
574 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
575 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
576 (ins VR512:$src1, u8imm:$idx),
577 "vextract" # To.EltTypeName # "x4",
578 "$idx, $src1", "$src1, $idx",
579 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
581 AVX512AIi8Base, EVEX, EVEX_V512;
583 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
584 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
585 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
586 "$dst, $src1, $src2}",
587 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
590 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
592 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
593 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
595 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
597 // A 128/256-bit subvector extract from the first 512-bit vector position is
598 // a subregister copy that needs no instruction.
599 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
601 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
603 // And for the alternative types.
604 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
606 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
608 // Intrinsic call with masking.
609 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
611 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
612 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
613 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
614 VR512:$src1, imm:$idx)>;
616 // Intrinsic call with zero-masking.
617 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
619 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
620 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
621 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
622 VR512:$src1, imm:$idx)>;
624 // Intrinsic call without masking.
625 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
627 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
628 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
629 VR512:$src1, imm:$idx)>;
632 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
633 ValueType EltVT64, int Opcode64> {
634 defm NAME # "32x4" : vextract_for_size<Opcode32,
635 X86VectorVTInfo<16, EltVT32, VR512>,
636 X86VectorVTInfo< 4, EltVT32, VR128X>,
637 X86VectorVTInfo< 8, EltVT64, VR512>,
638 X86VectorVTInfo< 2, EltVT64, VR128X>,
640 EXTRACT_get_vextract128_imm>;
641 defm NAME # "64x4" : vextract_for_size<Opcode64,
642 X86VectorVTInfo< 8, EltVT64, VR512>,
643 X86VectorVTInfo< 4, EltVT64, VR256X>,
644 X86VectorVTInfo<16, EltVT32, VR512>,
645 X86VectorVTInfo< 8, EltVT32, VR256>,
647 EXTRACT_get_vextract256_imm>, VEX_W;
650 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
651 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
653 // A 128-bit subvector insert to the first 512-bit vector position
654 // is a subregister copy that needs no instruction.
655 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
656 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
657 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
659 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
660 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
661 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
663 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
664 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
665 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
667 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
668 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
669 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
672 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
673 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
674 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
675 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
676 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
677 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
678 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
679 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
681 // vextractps - extract 32 bits from XMM
682 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
683 (ins VR128X:$src1, u8imm:$src2),
684 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
685 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
688 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
689 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
690 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
691 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
692 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
694 //===---------------------------------------------------------------------===//
697 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
698 ValueType svt, X86VectorVTInfo _> {
699 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
700 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
701 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
705 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
706 (ins _.ScalarMemOp:$src),
707 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
708 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
713 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
714 AVX512VLVectorVTInfo _> {
715 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
718 let Predicates = [HasVLX] in {
719 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
724 let ExeDomain = SSEPackedSingle in {
725 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
726 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
727 let Predicates = [HasVLX] in {
728 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
729 v4f32, v4f32x_info>, EVEX_V128,
730 EVEX_CD8<32, CD8VT1>;
734 let ExeDomain = SSEPackedDouble in {
735 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
736 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
739 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
740 // Later, we can canonize broadcast instructions before ISel phase and
741 // eliminate additional patterns on ISel.
742 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
743 // representations of source
744 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
745 X86VectorVTInfo _, RegisterClass SrcRC_v,
746 RegisterClass SrcRC_s> {
747 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
748 (!cast<Instruction>(InstName##"r")
749 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
751 let AddedComplexity = 30 in {
752 def : Pat<(_.VT (vselect _.KRCWM:$mask,
753 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
754 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
755 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
757 def : Pat<(_.VT(vselect _.KRCWM:$mask,
758 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
759 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
760 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
764 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
766 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
769 let Predicates = [HasVLX] in {
770 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
771 v8f32x_info, VR128X, FR32X>;
772 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
773 v4f32x_info, VR128X, FR32X>;
774 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
775 v4f64x_info, VR128X, FR64X>;
778 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
779 (VBROADCASTSSZm addr:$src)>;
780 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
781 (VBROADCASTSDZm addr:$src)>;
783 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
784 (VBROADCASTSSZm addr:$src)>;
785 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
786 (VBROADCASTSDZm addr:$src)>;
788 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
789 RegisterClass SrcRC> {
790 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
791 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
792 "$src", "$src", []>, T8PD, EVEX;
795 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
796 RegisterClass SrcRC, Predicate prd> {
797 let Predicates = [prd] in
798 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
799 let Predicates = [prd, HasVLX] in {
800 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
801 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
805 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
807 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
809 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
811 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
814 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
815 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
817 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
818 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
820 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
821 (VPBROADCASTDrZr GR32:$src)>;
822 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
823 (VPBROADCASTQrZr GR64:$src)>;
825 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
826 (VPBROADCASTDrZr GR32:$src)>;
827 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
828 (VPBROADCASTQrZr GR64:$src)>;
830 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
831 (v16i32 immAllZerosV), (i16 GR16:$mask))),
832 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
833 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
834 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
835 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
837 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
838 X86MemOperand x86memop, PatFrag ld_frag,
839 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
841 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
842 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
844 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
845 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
847 !strconcat(OpcodeStr,
848 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
850 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
852 !strconcat(OpcodeStr,
853 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
856 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
859 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
860 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
862 !strconcat(OpcodeStr,
863 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
865 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
867 !strconcat(OpcodeStr,
868 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
869 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
870 (X86VBroadcast (ld_frag addr:$src)),
871 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
875 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
876 loadi32, VR512, v16i32, v4i32, VK16WM>,
877 EVEX_V512, EVEX_CD8<32, CD8VT1>;
878 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
879 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
880 EVEX_CD8<64, CD8VT1>;
882 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
883 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
885 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
886 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
888 (_Dst.VT (X86SubVBroadcast
889 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
890 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
892 !strconcat(OpcodeStr,
893 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
895 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
897 !strconcat(OpcodeStr,
898 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
903 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
904 v16i32_info, v4i32x_info>,
905 EVEX_V512, EVEX_CD8<32, CD8VT4>;
906 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
907 v16f32_info, v4f32x_info>,
908 EVEX_V512, EVEX_CD8<32, CD8VT4>;
909 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
910 v8i64_info, v4i64x_info>, VEX_W,
911 EVEX_V512, EVEX_CD8<64, CD8VT4>;
912 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
913 v8f64_info, v4f64x_info>, VEX_W,
914 EVEX_V512, EVEX_CD8<64, CD8VT4>;
916 let Predicates = [HasVLX] in {
917 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
918 v8i32x_info, v4i32x_info>,
919 EVEX_V256, EVEX_CD8<32, CD8VT4>;
920 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
921 v8f32x_info, v4f32x_info>,
922 EVEX_V256, EVEX_CD8<32, CD8VT4>;
924 let Predicates = [HasVLX, HasDQI] in {
925 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
926 v4i64x_info, v2i64x_info>, VEX_W,
927 EVEX_V256, EVEX_CD8<64, CD8VT2>;
928 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
929 v4f64x_info, v2f64x_info>, VEX_W,
930 EVEX_V256, EVEX_CD8<64, CD8VT2>;
932 let Predicates = [HasDQI] in {
933 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
934 v8i64_info, v2i64x_info>, VEX_W,
935 EVEX_V512, EVEX_CD8<64, CD8VT2>;
936 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
937 v16i32_info, v8i32x_info>,
938 EVEX_V512, EVEX_CD8<32, CD8VT8>;
939 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
940 v8f64_info, v2f64x_info>, VEX_W,
941 EVEX_V512, EVEX_CD8<64, CD8VT2>;
942 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
943 v16f32_info, v8f32x_info>,
944 EVEX_V512, EVEX_CD8<32, CD8VT8>;
947 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
948 (VPBROADCASTDZrr VR128X:$src)>;
949 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
950 (VPBROADCASTQZrr VR128X:$src)>;
952 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
953 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
954 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
955 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
957 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
958 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
959 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
960 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
962 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
963 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
964 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
965 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
967 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
968 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
969 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
970 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
972 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
973 (VBROADCASTSSZr VR128X:$src)>;
974 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
975 (VBROADCASTSDZr VR128X:$src)>;
977 // Provide fallback in case the load node that is used in the patterns above
978 // is used by additional users, which prevents the pattern selection.
979 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
980 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
981 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
982 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
985 //===----------------------------------------------------------------------===//
986 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
989 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
991 let Predicates = [HasCDI] in
992 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
993 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
994 []>, EVEX, EVEX_V512;
996 let Predicates = [HasCDI, HasVLX] in {
997 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
998 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
999 []>, EVEX, EVEX_V128;
1000 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
1001 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1002 []>, EVEX, EVEX_V256;
1006 let Predicates = [HasCDI] in {
1007 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1009 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1013 //===----------------------------------------------------------------------===//
1016 // -- immediate form --
1017 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1018 X86VectorVTInfo _> {
1019 let ExeDomain = _.ExeDomain in {
1020 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
1021 (ins _.RC:$src1, u8imm:$src2),
1022 !strconcat(OpcodeStr,
1023 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1025 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
1027 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
1028 (ins _.MemOp:$src1, u8imm:$src2),
1029 !strconcat(OpcodeStr,
1030 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1032 (_.VT (OpNode (_.LdFrag addr:$src1),
1033 (i8 imm:$src2))))]>,
1034 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
1038 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
1039 X86VectorVTInfo Ctrl> :
1040 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
1041 let ExeDomain = _.ExeDomain in {
1042 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
1043 (ins _.RC:$src1, _.RC:$src2),
1044 !strconcat("vpermil" # _.Suffix,
1045 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1047 (_.VT (X86VPermilpv _.RC:$src1,
1048 (Ctrl.VT Ctrl.RC:$src2))))]>,
1050 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
1051 (ins _.RC:$src1, Ctrl.MemOp:$src2),
1052 !strconcat("vpermil" # _.Suffix,
1053 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1055 (_.VT (X86VPermilpv _.RC:$src1,
1056 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
1060 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
1062 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1065 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1066 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1067 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1068 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1070 // -- VPERM2I - 3 source operands form --
1071 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1072 SDNode OpNode, X86VectorVTInfo _> {
1073 let Constraints = "$src1 = $dst" in {
1074 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1075 (ins _.RC:$src2, _.RC:$src3),
1076 OpcodeStr, "$src3, $src2", "$src2, $src3",
1077 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1081 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1082 (ins _.RC:$src2, _.MemOp:$src3),
1083 OpcodeStr, "$src3, $src2", "$src2, $src3",
1084 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1085 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1086 EVEX_4V, AVX5128IBase;
1089 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1090 SDNode OpNode, X86VectorVTInfo _> {
1091 let mayLoad = 1, Constraints = "$src1 = $dst" in
1092 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1093 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1094 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1095 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1096 (_.VT (OpNode _.RC:$src1,
1097 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1098 AVX5128IBase, EVEX_4V, EVEX_B;
1101 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1102 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1103 let Predicates = [HasAVX512] in
1104 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1105 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1106 let Predicates = [HasVLX] in {
1107 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1108 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1110 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1111 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1115 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1116 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1117 let Predicates = [HasBWI] in
1118 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1119 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1121 let Predicates = [HasBWI, HasVLX] in {
1122 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1123 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1125 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1126 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1130 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1131 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1132 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1133 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1134 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1135 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1136 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1137 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1139 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1140 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1141 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1142 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1143 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1144 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1145 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1146 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1148 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1149 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1150 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1151 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1153 //===----------------------------------------------------------------------===//
1154 // AVX-512 - BLEND using mask
1156 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1157 let ExeDomain = _.ExeDomain in {
1158 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1159 (ins _.RC:$src1, _.RC:$src2),
1160 !strconcat(OpcodeStr,
1161 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1163 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1164 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1165 !strconcat(OpcodeStr,
1166 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1167 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1168 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1169 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1170 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1171 !strconcat(OpcodeStr,
1172 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1173 []>, EVEX_4V, EVEX_KZ;
1174 let mayLoad = 1 in {
1175 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1176 (ins _.RC:$src1, _.MemOp:$src2),
1177 !strconcat(OpcodeStr,
1178 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1179 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1180 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1181 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1182 !strconcat(OpcodeStr,
1183 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1184 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1185 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1186 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1187 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1188 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1189 !strconcat(OpcodeStr,
1190 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1191 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1195 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1197 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1198 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1199 !strconcat(OpcodeStr,
1200 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1201 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1202 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1203 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1204 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1206 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1207 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1208 !strconcat(OpcodeStr,
1209 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1210 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1211 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1215 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1216 AVX512VLVectorVTInfo VTInfo> {
1217 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1218 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1220 let Predicates = [HasVLX] in {
1221 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1222 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1223 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1224 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1228 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1229 AVX512VLVectorVTInfo VTInfo> {
1230 let Predicates = [HasBWI] in
1231 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1233 let Predicates = [HasBWI, HasVLX] in {
1234 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1235 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1240 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1241 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1242 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1243 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1244 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1245 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1248 let Predicates = [HasAVX512] in {
1249 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1250 (v8f32 VR256X:$src2))),
1252 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1253 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1254 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1256 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1257 (v8i32 VR256X:$src2))),
1259 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1260 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1261 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1263 //===----------------------------------------------------------------------===//
1264 // Compare Instructions
1265 //===----------------------------------------------------------------------===//
1267 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1268 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1269 SDNode OpNode, ValueType VT,
1270 PatFrag ld_frag, string Suffix> {
1271 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1272 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1273 !strconcat("vcmp${cc}", Suffix,
1274 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1275 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1276 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1277 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1278 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1279 !strconcat("vcmp${cc}", Suffix,
1280 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1281 [(set VK1:$dst, (OpNode (VT RC:$src1),
1282 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1283 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1284 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1285 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1286 !strconcat("vcmp", Suffix,
1287 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1288 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1290 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1291 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1292 !strconcat("vcmp", Suffix,
1293 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1294 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1298 let Predicates = [HasAVX512] in {
1299 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1301 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1305 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1306 X86VectorVTInfo _> {
1307 def rr : AVX512BI<opc, MRMSrcReg,
1308 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1310 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1311 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1313 def rm : AVX512BI<opc, MRMSrcMem,
1314 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1315 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1316 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1317 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1318 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1319 def rrk : AVX512BI<opc, MRMSrcReg,
1320 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1322 "$dst {${mask}}, $src1, $src2}"),
1323 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1324 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1325 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1327 def rmk : AVX512BI<opc, MRMSrcMem,
1328 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1329 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1330 "$dst {${mask}}, $src1, $src2}"),
1331 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1332 (OpNode (_.VT _.RC:$src1),
1334 (_.LdFrag addr:$src2))))))],
1335 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1338 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1339 X86VectorVTInfo _> :
1340 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1341 let mayLoad = 1 in {
1342 def rmb : AVX512BI<opc, MRMSrcMem,
1343 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1344 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1345 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1346 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1347 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1348 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1349 def rmbk : AVX512BI<opc, MRMSrcMem,
1350 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1351 _.ScalarMemOp:$src2),
1352 !strconcat(OpcodeStr,
1353 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1354 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1355 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1356 (OpNode (_.VT _.RC:$src1),
1358 (_.ScalarLdFrag addr:$src2)))))],
1359 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1363 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1364 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1365 let Predicates = [prd] in
1366 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1369 let Predicates = [prd, HasVLX] in {
1370 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1372 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1377 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1378 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1380 let Predicates = [prd] in
1381 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1384 let Predicates = [prd, HasVLX] in {
1385 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1387 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1392 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1393 avx512vl_i8_info, HasBWI>,
1396 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1397 avx512vl_i16_info, HasBWI>,
1398 EVEX_CD8<16, CD8VF>;
1400 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1401 avx512vl_i32_info, HasAVX512>,
1402 EVEX_CD8<32, CD8VF>;
1404 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1405 avx512vl_i64_info, HasAVX512>,
1406 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1408 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1409 avx512vl_i8_info, HasBWI>,
1412 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1413 avx512vl_i16_info, HasBWI>,
1414 EVEX_CD8<16, CD8VF>;
1416 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1417 avx512vl_i32_info, HasAVX512>,
1418 EVEX_CD8<32, CD8VF>;
1420 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1421 avx512vl_i64_info, HasAVX512>,
1422 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1424 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1425 (COPY_TO_REGCLASS (VPCMPGTDZrr
1426 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1427 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1429 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1430 (COPY_TO_REGCLASS (VPCMPEQDZrr
1431 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1432 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1434 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1435 X86VectorVTInfo _> {
1436 def rri : AVX512AIi8<opc, MRMSrcReg,
1437 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1438 !strconcat("vpcmp${cc}", Suffix,
1439 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1440 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1442 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1444 def rmi : AVX512AIi8<opc, MRMSrcMem,
1445 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1446 !strconcat("vpcmp${cc}", Suffix,
1447 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1448 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1449 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1451 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1452 def rrik : AVX512AIi8<opc, MRMSrcReg,
1453 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1455 !strconcat("vpcmp${cc}", Suffix,
1456 "\t{$src2, $src1, $dst {${mask}}|",
1457 "$dst {${mask}}, $src1, $src2}"),
1458 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1459 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1461 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1463 def rmik : AVX512AIi8<opc, MRMSrcMem,
1464 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1466 !strconcat("vpcmp${cc}", Suffix,
1467 "\t{$src2, $src1, $dst {${mask}}|",
1468 "$dst {${mask}}, $src1, $src2}"),
1469 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1470 (OpNode (_.VT _.RC:$src1),
1471 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1473 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1475 // Accept explicit immediate argument form instead of comparison code.
1476 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1477 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1478 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1479 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1480 "$dst, $src1, $src2, $cc}"),
1481 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1483 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1484 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1485 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1486 "$dst, $src1, $src2, $cc}"),
1487 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1488 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1489 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1491 !strconcat("vpcmp", Suffix,
1492 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1493 "$dst {${mask}}, $src1, $src2, $cc}"),
1494 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1496 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1497 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1499 !strconcat("vpcmp", Suffix,
1500 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1501 "$dst {${mask}}, $src1, $src2, $cc}"),
1502 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1506 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1507 X86VectorVTInfo _> :
1508 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1509 def rmib : AVX512AIi8<opc, MRMSrcMem,
1510 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1512 !strconcat("vpcmp${cc}", Suffix,
1513 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1514 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1515 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1516 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1518 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1519 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1520 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1521 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1522 !strconcat("vpcmp${cc}", Suffix,
1523 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1524 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1525 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1526 (OpNode (_.VT _.RC:$src1),
1527 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1529 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1531 // Accept explicit immediate argument form instead of comparison code.
1532 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1533 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1534 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1536 !strconcat("vpcmp", Suffix,
1537 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1538 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1539 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1540 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1541 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1542 _.ScalarMemOp:$src2, u8imm:$cc),
1543 !strconcat("vpcmp", Suffix,
1544 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1545 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1546 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1550 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1551 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1552 let Predicates = [prd] in
1553 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1555 let Predicates = [prd, HasVLX] in {
1556 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1557 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1561 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1562 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1563 let Predicates = [prd] in
1564 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1567 let Predicates = [prd, HasVLX] in {
1568 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1570 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1575 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1576 HasBWI>, EVEX_CD8<8, CD8VF>;
1577 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1578 HasBWI>, EVEX_CD8<8, CD8VF>;
1580 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1581 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1582 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1583 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1585 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1586 HasAVX512>, EVEX_CD8<32, CD8VF>;
1587 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1588 HasAVX512>, EVEX_CD8<32, CD8VF>;
1590 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1591 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1592 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1593 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1595 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1597 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1598 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1599 "vcmp${cc}"#_.Suffix,
1600 "$src2, $src1", "$src1, $src2",
1601 (X86cmpm (_.VT _.RC:$src1),
1605 let mayLoad = 1 in {
1606 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1607 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1608 "vcmp${cc}"#_.Suffix,
1609 "$src2, $src1", "$src1, $src2",
1610 (X86cmpm (_.VT _.RC:$src1),
1611 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1614 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1616 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1617 "vcmp${cc}"#_.Suffix,
1618 "${src2}"##_.BroadcastStr##", $src1",
1619 "$src1, ${src2}"##_.BroadcastStr,
1620 (X86cmpm (_.VT _.RC:$src1),
1621 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1624 // Accept explicit immediate argument form instead of comparison code.
1625 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1626 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1628 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1630 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1632 let mayLoad = 1 in {
1633 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1635 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1637 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1639 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1641 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1643 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1644 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1649 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1650 // comparison code form (VCMP[EQ/LT/LE/...]
1651 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1652 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1653 "vcmp${cc}"#_.Suffix,
1654 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1655 (X86cmpmRnd (_.VT _.RC:$src1),
1658 (i32 FROUND_NO_EXC))>, EVEX_B;
1660 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1661 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1663 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1665 "$cc,{sae}, $src2, $src1",
1666 "$src1, $src2,{sae}, $cc">, EVEX_B;
1670 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1671 let Predicates = [HasAVX512] in {
1672 defm Z : avx512_vcmp_common<_.info512>,
1673 avx512_vcmp_sae<_.info512>, EVEX_V512;
1676 let Predicates = [HasAVX512,HasVLX] in {
1677 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1678 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1682 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1683 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1684 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1685 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1687 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1688 (COPY_TO_REGCLASS (VCMPPSZrri
1689 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1690 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1692 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1693 (COPY_TO_REGCLASS (VPCMPDZrri
1694 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1695 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1697 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1698 (COPY_TO_REGCLASS (VPCMPUDZrri
1699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1700 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1703 //-----------------------------------------------------------------
1704 // Mask register copy, including
1705 // - copy between mask registers
1706 // - load/store mask registers
1707 // - copy from GPR to mask register and vice versa
1709 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1710 string OpcodeStr, RegisterClass KRC,
1711 ValueType vvt, X86MemOperand x86memop> {
1712 let hasSideEffects = 0 in {
1713 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1714 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1716 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1717 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1718 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1720 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1721 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1722 [(store KRC:$src, addr:$dst)]>;
1726 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1728 RegisterClass KRC, RegisterClass GRC> {
1729 let hasSideEffects = 0 in {
1730 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1731 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1732 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1733 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1737 let Predicates = [HasDQI] in
1738 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1739 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1742 let Predicates = [HasAVX512] in
1743 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1744 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1747 let Predicates = [HasBWI] in {
1748 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1750 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1754 let Predicates = [HasBWI] in {
1755 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1757 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1761 // GR from/to mask register
1762 let Predicates = [HasDQI] in {
1763 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1764 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1765 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1766 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1768 let Predicates = [HasAVX512] in {
1769 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1770 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1771 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1772 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1774 let Predicates = [HasBWI] in {
1775 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1776 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1778 let Predicates = [HasBWI] in {
1779 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1780 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1784 let Predicates = [HasDQI] in {
1785 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1786 (KMOVBmk addr:$dst, VK8:$src)>;
1787 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1788 (KMOVBkm addr:$src)>;
1790 let Predicates = [HasAVX512, NoDQI] in {
1791 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1792 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1793 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1794 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1796 let Predicates = [HasAVX512] in {
1797 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1798 (KMOVWmk addr:$dst, VK16:$src)>;
1799 def : Pat<(i1 (load addr:$src)),
1800 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
1801 (MOV8rm addr:$src), sub_8bit)),
1803 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1804 (KMOVWkm addr:$src)>;
1806 let Predicates = [HasBWI] in {
1807 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1808 (KMOVDmk addr:$dst, VK32:$src)>;
1809 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1810 (KMOVDkm addr:$src)>;
1812 let Predicates = [HasBWI] in {
1813 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1814 (KMOVQmk addr:$dst, VK64:$src)>;
1815 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1816 (KMOVQkm addr:$src)>;
1819 let Predicates = [HasAVX512] in {
1820 def : Pat<(i1 (trunc (i64 GR64:$src))),
1821 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1824 def : Pat<(i1 (trunc (i32 GR32:$src))),
1825 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1827 def : Pat<(i1 (trunc (i8 GR8:$src))),
1829 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1831 def : Pat<(i1 (trunc (i16 GR16:$src))),
1833 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1836 def : Pat<(i32 (zext VK1:$src)),
1837 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1838 def : Pat<(i32 (anyext VK1:$src)),
1839 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
1840 def : Pat<(i8 (zext VK1:$src)),
1843 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1844 def : Pat<(i64 (zext VK1:$src)),
1845 (AND64ri8 (SUBREG_TO_REG (i64 0),
1846 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1847 def : Pat<(i16 (zext VK1:$src)),
1849 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1851 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1852 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1853 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1854 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1856 let Predicates = [HasBWI] in {
1857 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1858 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1859 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1860 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1864 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1865 let Predicates = [HasAVX512, NoDQI] in {
1866 // GR from/to 8-bit mask without native support
1867 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1869 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
1870 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1872 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1876 let Predicates = [HasAVX512] in {
1877 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1878 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1879 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1880 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1882 let Predicates = [HasBWI] in {
1883 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1884 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1885 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1886 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1889 // Mask unary operation
1891 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1892 RegisterClass KRC, SDPatternOperator OpNode,
1894 let Predicates = [prd] in
1895 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1896 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1897 [(set KRC:$dst, (OpNode KRC:$src))]>;
1900 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1901 SDPatternOperator OpNode> {
1902 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1904 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1905 HasAVX512>, VEX, PS;
1906 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1907 HasBWI>, VEX, PD, VEX_W;
1908 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1909 HasBWI>, VEX, PS, VEX_W;
1912 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1914 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1915 let Predicates = [HasAVX512] in
1916 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1918 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1919 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1921 defm : avx512_mask_unop_int<"knot", "KNOT">;
1923 let Predicates = [HasDQI] in
1924 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1925 let Predicates = [HasAVX512] in
1926 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1927 let Predicates = [HasBWI] in
1928 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1929 let Predicates = [HasBWI] in
1930 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1932 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1933 let Predicates = [HasAVX512, NoDQI] in {
1934 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1935 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1936 def : Pat<(not VK8:$src),
1938 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1940 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
1941 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
1942 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
1943 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
1945 // Mask binary operation
1946 // - KAND, KANDN, KOR, KXNOR, KXOR
1947 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1948 RegisterClass KRC, SDPatternOperator OpNode,
1949 Predicate prd, bit IsCommutable> {
1950 let Predicates = [prd], isCommutable = IsCommutable in
1951 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1952 !strconcat(OpcodeStr,
1953 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1954 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1957 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1958 SDPatternOperator OpNode, bit IsCommutable,
1959 Predicate prdW = HasAVX512> {
1960 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1961 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
1962 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1963 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
1964 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1965 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
1966 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1967 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
1970 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1971 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1973 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
1974 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
1975 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
1976 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
1977 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
1978 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
1980 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1981 let Predicates = [HasAVX512] in
1982 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1983 (i16 GR16:$src1), (i16 GR16:$src2)),
1984 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1985 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1986 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1989 defm : avx512_mask_binop_int<"kand", "KAND">;
1990 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1991 defm : avx512_mask_binop_int<"kor", "KOR">;
1992 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1993 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1995 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1996 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
1997 // for the DQI set, this type is legal and KxxxB instruction is used
1998 let Predicates = [NoDQI] in
1999 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2001 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2002 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2004 // All types smaller than 8 bits require conversion anyway
2005 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2006 (COPY_TO_REGCLASS (Inst
2007 (COPY_TO_REGCLASS VK1:$src1, VK16),
2008 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2009 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2010 (COPY_TO_REGCLASS (Inst
2011 (COPY_TO_REGCLASS VK2:$src1, VK16),
2012 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2013 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2014 (COPY_TO_REGCLASS (Inst
2015 (COPY_TO_REGCLASS VK4:$src1, VK16),
2016 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2019 defm : avx512_binop_pat<and, KANDWrr>;
2020 defm : avx512_binop_pat<andn, KANDNWrr>;
2021 defm : avx512_binop_pat<or, KORWrr>;
2022 defm : avx512_binop_pat<xnor, KXNORWrr>;
2023 defm : avx512_binop_pat<xor, KXORWrr>;
2025 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2026 (KXNORWrr VK16:$src1, VK16:$src2)>;
2027 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2028 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2029 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2030 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2031 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2032 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2034 let Predicates = [NoDQI] in
2035 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2036 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2037 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2039 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2040 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2041 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2043 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2044 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2045 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2047 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2048 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2049 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2052 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
2053 RegisterClass KRC> {
2054 let Predicates = [HasAVX512] in
2055 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2056 !strconcat(OpcodeStr,
2057 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2060 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
2061 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
2065 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
2066 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
2067 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
2068 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
2071 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2072 let Predicates = [HasAVX512] in
2073 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2074 (i16 GR16:$src1), (i16 GR16:$src2)),
2075 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2076 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2077 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2079 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2082 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2084 let Predicates = [HasAVX512], Defs = [EFLAGS] in
2085 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2086 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2087 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2090 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2091 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2093 let Predicates = [HasDQI] in
2094 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2096 let Predicates = [HasBWI] in {
2097 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2099 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2104 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2107 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2109 let Predicates = [HasAVX512] in
2110 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2111 !strconcat(OpcodeStr,
2112 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2113 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2116 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2118 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2120 let Predicates = [HasDQI] in
2121 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2123 let Predicates = [HasBWI] in {
2124 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2126 let Predicates = [HasDQI] in
2127 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2132 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2133 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2135 // Mask setting all 0s or 1s
2136 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2137 let Predicates = [HasAVX512] in
2138 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2139 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2140 [(set KRC:$dst, (VT Val))]>;
2143 multiclass avx512_mask_setop_w<PatFrag Val> {
2144 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2145 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2146 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2147 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2150 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2151 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2153 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2154 let Predicates = [HasAVX512] in {
2155 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2156 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2157 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2158 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2159 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2160 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2161 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2163 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2164 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2166 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2167 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2169 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2170 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2172 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2173 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2175 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2176 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2178 let Predicates = [HasVLX] in {
2179 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2180 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2181 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2182 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2183 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2184 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2185 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2186 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2187 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2188 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2191 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2192 (v8i1 (COPY_TO_REGCLASS
2193 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2194 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2196 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2197 (v8i1 (COPY_TO_REGCLASS
2198 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2199 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2201 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2202 (v4i1 (COPY_TO_REGCLASS
2203 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2204 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2206 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2207 (v4i1 (COPY_TO_REGCLASS
2208 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2209 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2211 //===----------------------------------------------------------------------===//
2212 // AVX-512 - Aligned and unaligned load and store
2216 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2217 PatFrag ld_frag, PatFrag mload,
2218 bit IsReMaterializable = 1> {
2219 let hasSideEffects = 0 in {
2220 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2221 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2223 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2224 (ins _.KRCWM:$mask, _.RC:$src),
2225 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2226 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2229 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2230 SchedRW = [WriteLoad] in
2231 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2232 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2233 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2236 let Constraints = "$src0 = $dst" in {
2237 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2238 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2239 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2240 "${dst} {${mask}}, $src1}"),
2241 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2243 (_.VT _.RC:$src0))))], _.ExeDomain>,
2245 let mayLoad = 1, SchedRW = [WriteLoad] in
2246 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2247 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2248 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2249 "${dst} {${mask}}, $src1}"),
2250 [(set _.RC:$dst, (_.VT
2251 (vselect _.KRCWM:$mask,
2252 (_.VT (bitconvert (ld_frag addr:$src1))),
2253 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2255 let mayLoad = 1, SchedRW = [WriteLoad] in
2256 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2257 (ins _.KRCWM:$mask, _.MemOp:$src),
2258 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2259 "${dst} {${mask}} {z}, $src}",
2260 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2261 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2262 _.ExeDomain>, EVEX, EVEX_KZ;
2264 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2265 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2267 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2268 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2270 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2271 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2272 _.KRCWM:$mask, addr:$ptr)>;
2275 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2276 AVX512VLVectorVTInfo _,
2278 bit IsReMaterializable = 1> {
2279 let Predicates = [prd] in
2280 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2281 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2283 let Predicates = [prd, HasVLX] in {
2284 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2285 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2286 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2287 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2291 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2292 AVX512VLVectorVTInfo _,
2294 bit IsReMaterializable = 1> {
2295 let Predicates = [prd] in
2296 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2297 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2299 let Predicates = [prd, HasVLX] in {
2300 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2301 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2302 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2303 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2307 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2308 PatFrag st_frag, PatFrag mstore> {
2309 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2310 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2311 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2313 let Constraints = "$src1 = $dst" in
2314 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2315 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2317 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2318 [], _.ExeDomain>, EVEX, EVEX_K;
2319 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2320 (ins _.KRCWM:$mask, _.RC:$src),
2322 "\t{$src, ${dst} {${mask}} {z}|" #
2323 "${dst} {${mask}} {z}, $src}",
2324 [], _.ExeDomain>, EVEX, EVEX_KZ;
2326 let mayStore = 1 in {
2327 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2328 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2329 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2330 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2331 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2332 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2333 [], _.ExeDomain>, EVEX, EVEX_K;
2336 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2337 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2338 _.KRCWM:$mask, _.RC:$src)>;
2342 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2343 AVX512VLVectorVTInfo _, Predicate prd> {
2344 let Predicates = [prd] in
2345 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2346 masked_store_unaligned>, EVEX_V512;
2348 let Predicates = [prd, HasVLX] in {
2349 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2350 masked_store_unaligned>, EVEX_V256;
2351 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2352 masked_store_unaligned>, EVEX_V128;
2356 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2357 AVX512VLVectorVTInfo _, Predicate prd> {
2358 let Predicates = [prd] in
2359 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2360 masked_store_aligned512>, EVEX_V512;
2362 let Predicates = [prd, HasVLX] in {
2363 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2364 masked_store_aligned256>, EVEX_V256;
2365 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2366 masked_store_aligned128>, EVEX_V128;
2370 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2372 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2373 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2375 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2377 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2378 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2380 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2381 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2382 PS, EVEX_CD8<32, CD8VF>;
2384 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2385 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2386 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2388 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2389 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2390 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2392 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2393 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2394 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2396 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2397 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2398 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2400 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2401 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2402 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2404 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2405 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2406 (VMOVAPDZrm addr:$ptr)>;
2408 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2409 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2410 (VMOVAPSZrm addr:$ptr)>;
2412 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2414 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2416 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2418 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2421 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2423 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2425 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2427 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2430 let Predicates = [HasAVX512, NoVLX] in {
2431 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2432 (VMOVUPSZmrk addr:$ptr,
2433 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2434 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2436 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2437 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2438 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2440 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2441 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2442 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2443 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2446 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2448 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2449 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2451 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2453 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2454 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2456 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2457 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2458 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2460 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2461 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2462 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2464 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2465 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2466 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2468 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2469 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2470 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2472 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2473 (v16i32 immAllZerosV), GR16:$mask)),
2474 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2476 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2477 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2478 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2480 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2482 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2484 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2486 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2489 let AddedComplexity = 20 in {
2490 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2491 (bc_v8i64 (v16i32 immAllZerosV)))),
2492 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2494 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2495 (v8i64 VR512:$src))),
2496 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2499 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2500 (v16i32 immAllZerosV))),
2501 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2503 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2504 (v16i32 VR512:$src))),
2505 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2508 let Predicates = [HasAVX512, NoVLX] in {
2509 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2510 (VMOVDQU32Zmrk addr:$ptr,
2511 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2512 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2514 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2515 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2516 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2519 // Move Int Doubleword to Packed Double Int
2521 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2522 "vmovd\t{$src, $dst|$dst, $src}",
2524 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2526 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2527 "vmovd\t{$src, $dst|$dst, $src}",
2529 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2530 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2531 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2532 "vmovq\t{$src, $dst|$dst, $src}",
2534 (v2i64 (scalar_to_vector GR64:$src)))],
2535 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2536 let isCodeGenOnly = 1 in {
2537 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2538 "vmovq\t{$src, $dst|$dst, $src}",
2539 [(set FR64:$dst, (bitconvert GR64:$src))],
2540 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2541 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2542 "vmovq\t{$src, $dst|$dst, $src}",
2543 [(set GR64:$dst, (bitconvert FR64:$src))],
2544 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2546 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2547 "vmovq\t{$src, $dst|$dst, $src}",
2548 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2549 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2550 EVEX_CD8<64, CD8VT1>;
2552 // Move Int Doubleword to Single Scalar
2554 let isCodeGenOnly = 1 in {
2555 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2556 "vmovd\t{$src, $dst|$dst, $src}",
2557 [(set FR32X:$dst, (bitconvert GR32:$src))],
2558 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2560 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2561 "vmovd\t{$src, $dst|$dst, $src}",
2562 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2563 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2566 // Move doubleword from xmm register to r/m32
2568 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2569 "vmovd\t{$src, $dst|$dst, $src}",
2570 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2571 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2573 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2574 (ins i32mem:$dst, VR128X:$src),
2575 "vmovd\t{$src, $dst|$dst, $src}",
2576 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2577 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2578 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2580 // Move quadword from xmm1 register to r/m64
2582 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2583 "vmovq\t{$src, $dst|$dst, $src}",
2584 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2586 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2587 Requires<[HasAVX512, In64BitMode]>;
2589 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2590 (ins i64mem:$dst, VR128X:$src),
2591 "vmovq\t{$src, $dst|$dst, $src}",
2592 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2593 addr:$dst)], IIC_SSE_MOVDQ>,
2594 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2595 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2597 // Move Scalar Single to Double Int
2599 let isCodeGenOnly = 1 in {
2600 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2602 "vmovd\t{$src, $dst|$dst, $src}",
2603 [(set GR32:$dst, (bitconvert FR32X:$src))],
2604 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2605 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2606 (ins i32mem:$dst, FR32X:$src),
2607 "vmovd\t{$src, $dst|$dst, $src}",
2608 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2609 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2612 // Move Quadword Int to Packed Quadword Int
2614 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2616 "vmovq\t{$src, $dst|$dst, $src}",
2618 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2619 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2621 //===----------------------------------------------------------------------===//
2622 // AVX-512 MOVSS, MOVSD
2623 //===----------------------------------------------------------------------===//
2625 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2626 SDNode OpNode, ValueType vt,
2627 X86MemOperand x86memop, PatFrag mem_pat> {
2628 let hasSideEffects = 0 in {
2629 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2630 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2631 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2632 (scalar_to_vector RC:$src2))))],
2633 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2634 let Constraints = "$src1 = $dst" in
2635 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2636 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2638 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2639 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2640 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2641 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2642 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2644 let mayStore = 1 in {
2645 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2646 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2647 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2649 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2650 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2651 [], IIC_SSE_MOV_S_MR>,
2652 EVEX, VEX_LIG, EVEX_K;
2654 } //hasSideEffects = 0
2657 let ExeDomain = SSEPackedSingle in
2658 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2659 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2661 let ExeDomain = SSEPackedDouble in
2662 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2663 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2665 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2666 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2667 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2669 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2670 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2671 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2673 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2674 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2675 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2677 // For the disassembler
2678 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2679 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2680 (ins VR128X:$src1, FR32X:$src2),
2681 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2683 XS, EVEX_4V, VEX_LIG;
2684 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2685 (ins VR128X:$src1, FR64X:$src2),
2686 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2688 XD, EVEX_4V, VEX_LIG, VEX_W;
2691 let Predicates = [HasAVX512] in {
2692 let AddedComplexity = 15 in {
2693 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2694 // MOVS{S,D} to the lower bits.
2695 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2696 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2697 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2698 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2699 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2700 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2701 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2702 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2704 // Move low f32 and clear high bits.
2705 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2706 (SUBREG_TO_REG (i32 0),
2707 (VMOVSSZrr (v4f32 (V_SET0)),
2708 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2709 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2710 (SUBREG_TO_REG (i32 0),
2711 (VMOVSSZrr (v4i32 (V_SET0)),
2712 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2715 let AddedComplexity = 20 in {
2716 // MOVSSrm zeros the high parts of the register; represent this
2717 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2718 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2719 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2720 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2721 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2722 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2723 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2725 // MOVSDrm zeros the high parts of the register; represent this
2726 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2727 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2728 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2729 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2730 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2731 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2732 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2733 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2734 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2735 def : Pat<(v2f64 (X86vzload addr:$src)),
2736 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2738 // Represent the same patterns above but in the form they appear for
2740 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2741 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2742 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2743 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2744 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2745 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2746 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2747 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2748 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2750 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2751 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2752 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2753 FR32X:$src)), sub_xmm)>;
2754 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2755 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2756 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2757 FR64X:$src)), sub_xmm)>;
2758 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2759 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2760 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2762 // Move low f64 and clear high bits.
2763 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2764 (SUBREG_TO_REG (i32 0),
2765 (VMOVSDZrr (v2f64 (V_SET0)),
2766 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2768 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2769 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2770 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2772 // Extract and store.
2773 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2775 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2776 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2778 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2780 // Shuffle with VMOVSS
2781 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2782 (VMOVSSZrr (v4i32 VR128X:$src1),
2783 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2784 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2785 (VMOVSSZrr (v4f32 VR128X:$src1),
2786 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2789 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2790 (SUBREG_TO_REG (i32 0),
2791 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2792 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2794 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2795 (SUBREG_TO_REG (i32 0),
2796 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2797 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2800 // Shuffle with VMOVSD
2801 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2802 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2803 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2804 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2805 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2806 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2807 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2808 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2811 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2812 (SUBREG_TO_REG (i32 0),
2813 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2814 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2816 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2817 (SUBREG_TO_REG (i32 0),
2818 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2819 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2822 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2823 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2824 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2825 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2826 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2827 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2828 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2829 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2832 let AddedComplexity = 15 in
2833 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2835 "vmovq\t{$src, $dst|$dst, $src}",
2836 [(set VR128X:$dst, (v2i64 (X86vzmovl
2837 (v2i64 VR128X:$src))))],
2838 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2840 let AddedComplexity = 20 in
2841 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2843 "vmovq\t{$src, $dst|$dst, $src}",
2844 [(set VR128X:$dst, (v2i64 (X86vzmovl
2845 (loadv2i64 addr:$src))))],
2846 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2847 EVEX_CD8<8, CD8VT8>;
2849 let Predicates = [HasAVX512] in {
2850 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2851 let AddedComplexity = 20 in {
2852 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2853 (VMOVDI2PDIZrm addr:$src)>;
2854 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2855 (VMOV64toPQIZrr GR64:$src)>;
2856 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2857 (VMOVDI2PDIZrr GR32:$src)>;
2859 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2860 (VMOVDI2PDIZrm addr:$src)>;
2861 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2862 (VMOVDI2PDIZrm addr:$src)>;
2863 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2864 (VMOVZPQILo2PQIZrm addr:$src)>;
2865 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2866 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2867 def : Pat<(v2i64 (X86vzload addr:$src)),
2868 (VMOVZPQILo2PQIZrm addr:$src)>;
2871 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2872 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2873 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2874 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2875 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2876 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2877 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2880 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2881 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2883 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2884 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2886 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2887 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2889 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2890 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2892 //===----------------------------------------------------------------------===//
2893 // AVX-512 - Non-temporals
2894 //===----------------------------------------------------------------------===//
2895 let SchedRW = [WriteLoad] in {
2896 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2897 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2898 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2899 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2900 EVEX_CD8<64, CD8VF>;
2902 let Predicates = [HasAVX512, HasVLX] in {
2903 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2905 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2906 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2907 EVEX_CD8<64, CD8VF>;
2909 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2911 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2912 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2913 EVEX_CD8<64, CD8VF>;
2917 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2918 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2919 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2920 let SchedRW = [WriteStore], mayStore = 1,
2921 AddedComplexity = 400 in
2922 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2923 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2924 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2927 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2928 string elty, string elsz, string vsz512,
2929 string vsz256, string vsz128, Domain d,
2930 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2931 let Predicates = [prd] in
2932 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2933 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2934 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2937 let Predicates = [prd, HasVLX] in {
2938 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2939 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2940 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2943 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2944 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2945 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2950 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2951 "i", "64", "8", "4", "2", SSEPackedInt,
2952 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2954 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2955 "f", "64", "8", "4", "2", SSEPackedDouble,
2956 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2958 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2959 "f", "32", "16", "8", "4", SSEPackedSingle,
2960 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2962 //===----------------------------------------------------------------------===//
2963 // AVX-512 - Integer arithmetic
2965 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2966 X86VectorVTInfo _, OpndItins itins,
2967 bit IsCommutable = 0> {
2968 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2969 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
2970 "$src2, $src1", "$src1, $src2",
2971 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2972 itins.rr, IsCommutable>,
2973 AVX512BIBase, EVEX_4V;
2976 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2977 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
2978 "$src2, $src1", "$src1, $src2",
2979 (_.VT (OpNode _.RC:$src1,
2980 (bitconvert (_.LdFrag addr:$src2)))),
2982 AVX512BIBase, EVEX_4V;
2985 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2986 X86VectorVTInfo _, OpndItins itins,
2987 bit IsCommutable = 0> :
2988 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2990 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2991 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
2992 "${src2}"##_.BroadcastStr##", $src1",
2993 "$src1, ${src2}"##_.BroadcastStr,
2994 (_.VT (OpNode _.RC:$src1,
2996 (_.ScalarLdFrag addr:$src2)))),
2998 AVX512BIBase, EVEX_4V, EVEX_B;
3001 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3002 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3003 Predicate prd, bit IsCommutable = 0> {
3004 let Predicates = [prd] in
3005 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3006 IsCommutable>, EVEX_V512;
3008 let Predicates = [prd, HasVLX] in {
3009 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3010 IsCommutable>, EVEX_V256;
3011 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3012 IsCommutable>, EVEX_V128;
3016 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3017 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3018 Predicate prd, bit IsCommutable = 0> {
3019 let Predicates = [prd] in
3020 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3021 IsCommutable>, EVEX_V512;
3023 let Predicates = [prd, HasVLX] in {
3024 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3025 IsCommutable>, EVEX_V256;
3026 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3027 IsCommutable>, EVEX_V128;
3031 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3032 OpndItins itins, Predicate prd,
3033 bit IsCommutable = 0> {
3034 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3035 itins, prd, IsCommutable>,
3036 VEX_W, EVEX_CD8<64, CD8VF>;
3039 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3040 OpndItins itins, Predicate prd,
3041 bit IsCommutable = 0> {
3042 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3043 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3046 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3047 OpndItins itins, Predicate prd,
3048 bit IsCommutable = 0> {
3049 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3050 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3053 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3054 OpndItins itins, Predicate prd,
3055 bit IsCommutable = 0> {
3056 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3057 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3060 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3061 SDNode OpNode, OpndItins itins, Predicate prd,
3062 bit IsCommutable = 0> {
3063 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3066 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3070 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3071 SDNode OpNode, OpndItins itins, Predicate prd,
3072 bit IsCommutable = 0> {
3073 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3076 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3080 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3081 bits<8> opc_d, bits<8> opc_q,
3082 string OpcodeStr, SDNode OpNode,
3083 OpndItins itins, bit IsCommutable = 0> {
3084 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3085 itins, HasAVX512, IsCommutable>,
3086 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3087 itins, HasBWI, IsCommutable>;
3090 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3091 SDNode OpNode,X86VectorVTInfo _Src,
3092 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3093 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3094 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3095 "$src2, $src1","$src1, $src2",
3097 (_Src.VT _Src.RC:$src1),
3098 (_Src.VT _Src.RC:$src2))),
3099 itins.rr, IsCommutable>,
3100 AVX512BIBase, EVEX_4V;
3101 let mayLoad = 1 in {
3102 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3103 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3104 "$src2, $src1", "$src1, $src2",
3105 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3106 (bitconvert (_Src.LdFrag addr:$src2)))),
3108 AVX512BIBase, EVEX_4V;
3110 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3111 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3113 "${src2}"##_Dst.BroadcastStr##", $src1",
3114 "$src1, ${src2}"##_Dst.BroadcastStr,
3115 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3116 (_Dst.VT (X86VBroadcast
3117 (_Dst.ScalarLdFrag addr:$src2)))))),
3119 AVX512BIBase, EVEX_4V, EVEX_B;
3123 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3124 SSE_INTALU_ITINS_P, 1>;
3125 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3126 SSE_INTALU_ITINS_P, 0>;
3127 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3128 SSE_INTALU_ITINS_P, HasBWI, 1>;
3129 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3130 SSE_INTALU_ITINS_P, HasBWI, 0>;
3131 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3132 SSE_INTALU_ITINS_P, HasBWI, 1>;
3133 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3134 SSE_INTALU_ITINS_P, HasBWI, 0>;
3135 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3136 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3137 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3138 SSE_INTALU_ITINS_P, HasBWI, 1>;
3139 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3140 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3141 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3143 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3145 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3147 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3148 SSE_INTALU_ITINS_P, HasBWI, 1>;
3150 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3151 SDNode OpNode, bit IsCommutable = 0> {
3153 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3154 v16i32_info, v8i64_info, IsCommutable>,
3155 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3156 let Predicates = [HasVLX] in {
3157 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3158 v8i32x_info, v4i64x_info, IsCommutable>,
3159 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3160 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3161 v4i32x_info, v2i64x_info, IsCommutable>,
3162 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3166 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3168 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3171 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3172 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3173 let mayLoad = 1 in {
3174 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3175 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3177 "${src2}"##_Src.BroadcastStr##", $src1",
3178 "$src1, ${src2}"##_Src.BroadcastStr,
3179 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3180 (_Src.VT (X86VBroadcast
3181 (_Src.ScalarLdFrag addr:$src2))))))>,
3182 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3186 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3187 SDNode OpNode,X86VectorVTInfo _Src,
3188 X86VectorVTInfo _Dst> {
3189 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3190 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3191 "$src2, $src1","$src1, $src2",
3193 (_Src.VT _Src.RC:$src1),
3194 (_Src.VT _Src.RC:$src2)))>,
3195 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3196 let mayLoad = 1 in {
3197 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3198 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3199 "$src2, $src1", "$src1, $src2",
3200 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3201 (bitconvert (_Src.LdFrag addr:$src2))))>,
3202 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3206 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3208 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3210 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3211 v32i16_info>, EVEX_V512;
3212 let Predicates = [HasVLX] in {
3213 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3215 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3216 v16i16x_info>, EVEX_V256;
3217 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3219 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3220 v8i16x_info>, EVEX_V128;
3223 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3225 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3226 v64i8_info>, EVEX_V512;
3227 let Predicates = [HasVLX] in {
3228 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3229 v32i8x_info>, EVEX_V256;
3230 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3231 v16i8x_info>, EVEX_V128;
3235 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3236 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3237 AVX512VLVectorVTInfo _Dst> {
3238 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3239 _Dst.info512>, EVEX_V512;
3240 let Predicates = [HasVLX] in {
3241 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3242 _Dst.info256>, EVEX_V256;
3243 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3244 _Dst.info128>, EVEX_V128;
3248 let Predicates = [HasBWI] in {
3249 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3250 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3251 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3252 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3254 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3255 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3256 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3257 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3260 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3261 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3262 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3263 SSE_INTALU_ITINS_P, HasBWI, 1>;
3264 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3265 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3267 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3268 SSE_INTALU_ITINS_P, HasBWI, 1>;
3269 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3270 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3271 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3272 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3274 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3275 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3276 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3277 SSE_INTALU_ITINS_P, HasBWI, 1>;
3278 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3279 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3281 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3282 SSE_INTALU_ITINS_P, HasBWI, 1>;
3283 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3284 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3285 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3286 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3287 //===----------------------------------------------------------------------===//
3288 // AVX-512 Logical Instructions
3289 //===----------------------------------------------------------------------===//
3291 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3292 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3293 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3294 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3295 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3296 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3297 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3298 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3300 //===----------------------------------------------------------------------===//
3301 // AVX-512 FP arithmetic
3302 //===----------------------------------------------------------------------===//
3303 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3304 SDNode OpNode, SDNode VecNode, OpndItins itins,
3307 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3308 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3309 "$src2, $src1", "$src1, $src2",
3310 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3311 (i32 FROUND_CURRENT)),
3312 itins.rr, IsCommutable>;
3314 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3315 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3316 "$src2, $src1", "$src1, $src2",
3317 (VecNode (_.VT _.RC:$src1),
3318 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3319 (i32 FROUND_CURRENT)),
3320 itins.rm, IsCommutable>;
3321 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3322 Predicates = [HasAVX512] in {
3323 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3324 (ins _.FRC:$src1, _.FRC:$src2),
3325 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3326 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3328 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3329 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3330 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3331 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3332 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3336 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3337 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3339 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3340 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3341 "$rc, $src2, $src1", "$src1, $src2, $rc",
3342 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3343 (i32 imm:$rc)), itins.rr, IsCommutable>,
3346 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3347 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3349 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3350 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3351 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3352 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3353 (i32 FROUND_NO_EXC))>, EVEX_B;
3356 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3358 SizeItins itins, bit IsCommutable> {
3359 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3360 itins.s, IsCommutable>,
3361 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3362 itins.s, IsCommutable>,
3363 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3364 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3365 itins.d, IsCommutable>,
3366 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3367 itins.d, IsCommutable>,
3368 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3371 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3373 SizeItins itins, bit IsCommutable> {
3374 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3375 itins.s, IsCommutable>,
3376 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3377 itins.s, IsCommutable>,
3378 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3379 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3380 itins.d, IsCommutable>,
3381 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3382 itins.d, IsCommutable>,
3383 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3385 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3386 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3387 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3388 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3389 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3390 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3392 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3393 X86VectorVTInfo _, bit IsCommutable> {
3394 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3395 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3396 "$src2, $src1", "$src1, $src2",
3397 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3398 let mayLoad = 1 in {
3399 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3400 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3401 "$src2, $src1", "$src1, $src2",
3402 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3403 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3404 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3405 "${src2}"##_.BroadcastStr##", $src1",
3406 "$src1, ${src2}"##_.BroadcastStr,
3407 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3408 (_.ScalarLdFrag addr:$src2))))>,
3413 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3414 X86VectorVTInfo _> {
3415 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3416 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3417 "$rc, $src2, $src1", "$src1, $src2, $rc",
3418 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3419 EVEX_4V, EVEX_B, EVEX_RC;
3423 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3424 X86VectorVTInfo _> {
3425 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3426 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3427 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3428 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3432 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3433 bit IsCommutable = 0> {
3434 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3435 IsCommutable>, EVEX_V512, PS,
3436 EVEX_CD8<32, CD8VF>;
3437 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3438 IsCommutable>, EVEX_V512, PD, VEX_W,
3439 EVEX_CD8<64, CD8VF>;
3441 // Define only if AVX512VL feature is present.
3442 let Predicates = [HasVLX] in {
3443 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3444 IsCommutable>, EVEX_V128, PS,
3445 EVEX_CD8<32, CD8VF>;
3446 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3447 IsCommutable>, EVEX_V256, PS,
3448 EVEX_CD8<32, CD8VF>;
3449 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3450 IsCommutable>, EVEX_V128, PD, VEX_W,
3451 EVEX_CD8<64, CD8VF>;
3452 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3453 IsCommutable>, EVEX_V256, PD, VEX_W,
3454 EVEX_CD8<64, CD8VF>;
3458 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3459 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3460 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3461 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3462 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3465 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3466 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3467 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3468 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3469 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3472 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3473 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3474 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3475 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3476 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3477 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3478 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3479 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3480 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3481 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3482 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3483 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3484 let Predicates = [HasDQI] in {
3485 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3486 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3487 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3488 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3491 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3492 X86VectorVTInfo _> {
3493 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3494 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3495 "$src2, $src1", "$src1, $src2",
3496 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3497 let mayLoad = 1 in {
3498 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3499 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3500 "$src2, $src1", "$src1, $src2",
3501 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3502 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3503 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3504 "${src2}"##_.BroadcastStr##", $src1",
3505 "$src1, ${src2}"##_.BroadcastStr,
3506 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3507 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3512 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3513 X86VectorVTInfo _> {
3514 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3515 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3516 "$src2, $src1", "$src1, $src2",
3517 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3518 let mayLoad = 1 in {
3519 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3520 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3521 "$src2, $src1", "$src1, $src2",
3522 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3526 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3527 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3528 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3529 EVEX_V512, EVEX_CD8<32, CD8VF>;
3530 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3531 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3532 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3533 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3534 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3535 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3536 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3537 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3538 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3540 // Define only if AVX512VL feature is present.
3541 let Predicates = [HasVLX] in {
3542 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3543 EVEX_V128, EVEX_CD8<32, CD8VF>;
3544 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3545 EVEX_V256, EVEX_CD8<32, CD8VF>;
3546 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3547 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3548 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3549 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3552 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3554 //===----------------------------------------------------------------------===//
3555 // AVX-512 VPTESTM instructions
3556 //===----------------------------------------------------------------------===//
3558 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3559 X86VectorVTInfo _> {
3560 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3561 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3562 "$src2, $src1", "$src1, $src2",
3563 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3566 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3567 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3568 "$src2, $src1", "$src1, $src2",
3569 (OpNode (_.VT _.RC:$src1),
3570 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3572 EVEX_CD8<_.EltSize, CD8VF>;
3575 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3576 X86VectorVTInfo _> {
3578 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3579 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3580 "${src2}"##_.BroadcastStr##", $src1",
3581 "$src1, ${src2}"##_.BroadcastStr,
3582 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3583 (_.ScalarLdFrag addr:$src2))))>,
3584 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3586 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3587 AVX512VLVectorVTInfo _> {
3588 let Predicates = [HasAVX512] in
3589 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3590 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3592 let Predicates = [HasAVX512, HasVLX] in {
3593 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3594 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3595 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3596 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3600 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3601 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3603 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3604 avx512vl_i64_info>, VEX_W;
3607 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3609 let Predicates = [HasBWI] in {
3610 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3612 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3615 let Predicates = [HasVLX, HasBWI] in {
3617 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3619 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3621 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3623 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3628 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3630 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3631 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3633 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3634 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3636 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3637 (v16i32 VR512:$src2), (i16 -1))),
3638 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3640 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3641 (v8i64 VR512:$src2), (i8 -1))),
3642 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3644 //===----------------------------------------------------------------------===//
3645 // AVX-512 Shift instructions
3646 //===----------------------------------------------------------------------===//
3647 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3648 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3649 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3650 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3651 "$src2, $src1", "$src1, $src2",
3652 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3653 SSE_INTSHIFT_ITINS_P.rr>;
3655 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3656 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3657 "$src2, $src1", "$src1, $src2",
3658 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3660 SSE_INTSHIFT_ITINS_P.rm>;
3663 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3664 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3666 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3667 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3668 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3669 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3670 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3673 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3674 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3675 // src2 is always 128-bit
3676 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3677 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3678 "$src2, $src1", "$src1, $src2",
3679 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3680 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3681 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3682 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3683 "$src2, $src1", "$src1, $src2",
3684 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3685 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3689 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3690 ValueType SrcVT, PatFrag bc_frag,
3691 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3692 let Predicates = [prd] in
3693 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3694 VTInfo.info512>, EVEX_V512,
3695 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3696 let Predicates = [prd, HasVLX] in {
3697 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3698 VTInfo.info256>, EVEX_V256,
3699 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3700 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3701 VTInfo.info128>, EVEX_V128,
3702 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3706 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3707 string OpcodeStr, SDNode OpNode> {
3708 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3709 avx512vl_i32_info, HasAVX512>;
3710 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3711 avx512vl_i64_info, HasAVX512>, VEX_W;
3712 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3713 avx512vl_i16_info, HasBWI>;
3716 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3717 string OpcodeStr, SDNode OpNode,
3718 AVX512VLVectorVTInfo VTInfo> {
3719 let Predicates = [HasAVX512] in
3720 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3722 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3723 VTInfo.info512>, EVEX_V512;
3724 let Predicates = [HasAVX512, HasVLX] in {
3725 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3727 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3728 VTInfo.info256>, EVEX_V256;
3729 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3731 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3732 VTInfo.info128>, EVEX_V128;
3736 multiclass avx512_shift_rmi_w<bits<8> opcw,
3737 Format ImmFormR, Format ImmFormM,
3738 string OpcodeStr, SDNode OpNode> {
3739 let Predicates = [HasBWI] in
3740 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3741 v32i16_info>, EVEX_V512;
3742 let Predicates = [HasVLX, HasBWI] in {
3743 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3744 v16i16x_info>, EVEX_V256;
3745 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3746 v8i16x_info>, EVEX_V128;
3750 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3751 Format ImmFormR, Format ImmFormM,
3752 string OpcodeStr, SDNode OpNode> {
3753 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3754 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3755 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3756 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3759 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3760 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3762 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3763 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3765 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3766 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
3768 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
3769 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
3771 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3772 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3773 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3775 //===-------------------------------------------------------------------===//
3776 // Variable Bit Shifts
3777 //===-------------------------------------------------------------------===//
3778 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3779 X86VectorVTInfo _> {
3780 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3781 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3782 "$src2, $src1", "$src1, $src2",
3783 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3784 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3786 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3787 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3788 "$src2, $src1", "$src1, $src2",
3789 (_.VT (OpNode _.RC:$src1,
3790 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
3791 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3792 EVEX_CD8<_.EltSize, CD8VF>;
3795 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3796 X86VectorVTInfo _> {
3798 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3799 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3800 "${src2}"##_.BroadcastStr##", $src1",
3801 "$src1, ${src2}"##_.BroadcastStr,
3802 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3803 (_.ScalarLdFrag addr:$src2))))),
3804 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3805 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3807 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3808 AVX512VLVectorVTInfo _> {
3809 let Predicates = [HasAVX512] in
3810 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3811 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3813 let Predicates = [HasAVX512, HasVLX] in {
3814 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3815 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3816 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3817 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3821 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3823 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3825 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3826 avx512vl_i64_info>, VEX_W;
3829 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3831 let Predicates = [HasBWI] in
3832 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3834 let Predicates = [HasVLX, HasBWI] in {
3836 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3838 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3843 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3844 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3845 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3846 avx512_var_shift_w<0x11, "vpsravw", sra>;
3847 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3848 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3849 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3850 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3852 //===-------------------------------------------------------------------===//
3853 // 1-src variable permutation VPERMW/D/Q
3854 //===-------------------------------------------------------------------===//
3855 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3856 AVX512VLVectorVTInfo _> {
3857 let Predicates = [HasAVX512] in
3858 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3859 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3861 let Predicates = [HasAVX512, HasVLX] in
3862 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3863 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3866 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3867 string OpcodeStr, SDNode OpNode,
3868 AVX512VLVectorVTInfo VTInfo> {
3869 let Predicates = [HasAVX512] in
3870 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3872 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3873 VTInfo.info512>, EVEX_V512;
3874 let Predicates = [HasAVX512, HasVLX] in
3875 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3877 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3878 VTInfo.info256>, EVEX_V256;
3882 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
3884 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
3886 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
3887 avx512vl_i64_info>, VEX_W;
3888 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
3890 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
3891 avx512vl_f64_info>, VEX_W;
3893 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
3894 X86VPermi, avx512vl_i64_info>,
3895 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3896 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
3897 X86VPermi, avx512vl_f64_info>,
3898 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3900 //===----------------------------------------------------------------------===//
3901 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
3902 //===----------------------------------------------------------------------===//
3904 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
3905 X86PShufd, avx512vl_i32_info>,
3906 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
3907 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
3908 X86PShufhw>, EVEX, AVX512XSIi8Base, VEX_W;
3909 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
3910 X86PShuflw>, EVEX, AVX512XDIi8Base, VEX_W;
3912 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3913 let Predicates = [HasBWI] in
3914 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
3916 let Predicates = [HasVLX, HasBWI] in {
3917 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
3918 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
3922 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
3924 //===----------------------------------------------------------------------===//
3925 // AVX-512 - MOVDDUP
3926 //===----------------------------------------------------------------------===//
3928 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3929 X86MemOperand x86memop, PatFrag memop_frag> {
3930 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3931 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3932 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3933 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3934 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3936 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3939 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3940 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3941 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3942 (VMOVDDUPZrm addr:$src)>;
3944 //===---------------------------------------------------------------------===//
3945 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3946 //===---------------------------------------------------------------------===//
3947 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3948 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3949 X86MemOperand x86memop> {
3950 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3951 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3952 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3954 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3955 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3956 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3959 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3960 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3961 EVEX_CD8<32, CD8VF>;
3962 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3963 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3964 EVEX_CD8<32, CD8VF>;
3966 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3967 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3968 (VMOVSHDUPZrm addr:$src)>;
3969 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3970 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3971 (VMOVSLDUPZrm addr:$src)>;
3973 //===----------------------------------------------------------------------===//
3974 // Move Low to High and High to Low packed FP Instructions
3975 //===----------------------------------------------------------------------===//
3976 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3977 (ins VR128X:$src1, VR128X:$src2),
3978 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3979 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3980 IIC_SSE_MOV_LH>, EVEX_4V;
3981 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3982 (ins VR128X:$src1, VR128X:$src2),
3983 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3984 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3985 IIC_SSE_MOV_LH>, EVEX_4V;
3987 let Predicates = [HasAVX512] in {
3989 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3990 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3991 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3992 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3995 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3996 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3999 //===----------------------------------------------------------------------===//
4000 // FMA - Fused Multiply Operations
4003 let Constraints = "$src1 = $dst" in {
4004 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4005 X86VectorVTInfo _> {
4006 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4007 (ins _.RC:$src2, _.RC:$src3),
4008 OpcodeStr, "$src3, $src2", "$src2, $src3",
4009 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4012 let mayLoad = 1 in {
4013 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4014 (ins _.RC:$src2, _.MemOp:$src3),
4015 OpcodeStr, "$src3, $src2", "$src2, $src3",
4016 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4019 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4020 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4021 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4022 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4024 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4025 AVX512FMA3Base, EVEX_B;
4029 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4030 X86VectorVTInfo _> {
4031 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4032 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4033 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4034 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4035 AVX512FMA3Base, EVEX_B, EVEX_RC;
4037 } // Constraints = "$src1 = $dst"
4039 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4040 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4041 let Predicates = [HasAVX512] in {
4042 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4043 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4044 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4046 let Predicates = [HasVLX, HasAVX512] in {
4047 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4048 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4049 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4050 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4054 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4055 SDNode OpNodeRnd > {
4056 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4058 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4059 avx512vl_f64_info>, VEX_W;
4062 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4063 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4064 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4065 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4066 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4067 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4070 let Constraints = "$src1 = $dst" in {
4071 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4072 X86VectorVTInfo _> {
4073 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4074 (ins _.RC:$src2, _.RC:$src3),
4075 OpcodeStr, "$src3, $src2", "$src2, $src3",
4076 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4079 let mayLoad = 1 in {
4080 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4081 (ins _.RC:$src2, _.MemOp:$src3),
4082 OpcodeStr, "$src3, $src2", "$src2, $src3",
4083 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4086 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4087 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4088 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4089 "$src2, ${src3}"##_.BroadcastStr,
4090 (_.VT (OpNode _.RC:$src2,
4091 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4092 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4096 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4097 X86VectorVTInfo _> {
4098 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4099 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4100 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4101 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4102 AVX512FMA3Base, EVEX_B, EVEX_RC;
4104 } // Constraints = "$src1 = $dst"
4106 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4107 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4108 let Predicates = [HasAVX512] in {
4109 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4110 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4111 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4113 let Predicates = [HasVLX, HasAVX512] in {
4114 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4115 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4116 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4117 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4121 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4122 SDNode OpNodeRnd > {
4123 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4125 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4126 avx512vl_f64_info>, VEX_W;
4129 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4130 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4131 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4132 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4133 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4134 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4136 let Constraints = "$src1 = $dst" in {
4137 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4138 X86VectorVTInfo _> {
4139 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4140 (ins _.RC:$src3, _.RC:$src2),
4141 OpcodeStr, "$src2, $src3", "$src3, $src2",
4142 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4145 let mayLoad = 1 in {
4146 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4147 (ins _.RC:$src3, _.MemOp:$src2),
4148 OpcodeStr, "$src2, $src3", "$src3, $src2",
4149 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4152 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4153 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4154 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4155 "$src3, ${src2}"##_.BroadcastStr,
4156 (_.VT (OpNode _.RC:$src1,
4157 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4158 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4162 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4163 X86VectorVTInfo _> {
4164 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4165 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4166 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4167 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4168 AVX512FMA3Base, EVEX_B, EVEX_RC;
4170 } // Constraints = "$src1 = $dst"
4172 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4173 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4174 let Predicates = [HasAVX512] in {
4175 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4176 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4177 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4179 let Predicates = [HasVLX, HasAVX512] in {
4180 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4181 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4182 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4183 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4187 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4188 SDNode OpNodeRnd > {
4189 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4191 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4192 avx512vl_f64_info>, VEX_W;
4195 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4196 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4197 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4198 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4199 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4200 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4203 let Constraints = "$src1 = $dst" in {
4204 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4205 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4206 dag RHS_r, dag RHS_m > {
4207 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4208 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4209 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4212 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4213 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4214 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4216 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4217 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4218 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4219 AVX512FMA3Base, EVEX_B, EVEX_RC;
4221 let isCodeGenOnly = 1 in {
4222 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4223 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4224 !strconcat(OpcodeStr,
4225 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4228 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4229 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4230 !strconcat(OpcodeStr,
4231 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4233 }// isCodeGenOnly = 1
4235 }// Constraints = "$src1 = $dst"
4237 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4238 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4241 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4242 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4243 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4244 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4245 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4247 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4249 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4250 (_.ScalarLdFrag addr:$src3))))>;
4252 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4253 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4254 (_.VT (OpNode _.RC:$src2,
4255 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4257 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4259 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4261 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4262 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4264 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4265 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4266 (_.VT (OpNode _.RC:$src1,
4267 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4269 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4271 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4273 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4274 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4277 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4278 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4279 let Predicates = [HasAVX512] in {
4280 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4281 OpNodeRnd, f32x_info, "SS">,
4282 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4283 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4284 OpNodeRnd, f64x_info, "SD">,
4285 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4289 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4290 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4291 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4292 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4294 //===----------------------------------------------------------------------===//
4295 // AVX-512 Scalar convert from sign integer to float/double
4296 //===----------------------------------------------------------------------===//
4298 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4299 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4300 PatFrag ld_frag, string asm> {
4301 let hasSideEffects = 0 in {
4302 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4303 (ins DstVT.FRC:$src1, SrcRC:$src),
4304 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4307 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4308 (ins DstVT.FRC:$src1, x86memop:$src),
4309 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4311 } // hasSideEffects = 0
4312 let isCodeGenOnly = 1 in {
4313 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4314 (ins DstVT.RC:$src1, SrcRC:$src2),
4315 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4316 [(set DstVT.RC:$dst,
4317 (OpNode (DstVT.VT DstVT.RC:$src1),
4319 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4321 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4322 (ins DstVT.RC:$src1, x86memop:$src2),
4323 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4324 [(set DstVT.RC:$dst,
4325 (OpNode (DstVT.VT DstVT.RC:$src1),
4326 (ld_frag addr:$src2),
4327 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4328 }//isCodeGenOnly = 1
4331 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4332 X86VectorVTInfo DstVT, string asm> {
4333 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4334 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4336 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4337 [(set DstVT.RC:$dst,
4338 (OpNode (DstVT.VT DstVT.RC:$src1),
4340 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4343 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4344 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4345 PatFrag ld_frag, string asm> {
4346 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4347 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4351 let Predicates = [HasAVX512] in {
4352 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4353 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4354 XS, EVEX_CD8<32, CD8VT1>;
4355 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4356 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4357 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4358 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4359 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4360 XD, EVEX_CD8<32, CD8VT1>;
4361 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4362 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4363 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4365 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4366 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4367 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4368 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4369 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4370 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4371 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4372 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4374 def : Pat<(f32 (sint_to_fp GR32:$src)),
4375 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4376 def : Pat<(f32 (sint_to_fp GR64:$src)),
4377 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4378 def : Pat<(f64 (sint_to_fp GR32:$src)),
4379 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4380 def : Pat<(f64 (sint_to_fp GR64:$src)),
4381 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4383 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4384 v4f32x_info, i32mem, loadi32,
4385 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4386 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4387 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4388 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4389 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4390 i32mem, loadi32, "cvtusi2sd{l}">,
4391 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4392 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4393 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4394 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4396 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4397 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4398 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4399 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4400 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4401 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4402 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4403 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4405 def : Pat<(f32 (uint_to_fp GR32:$src)),
4406 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4407 def : Pat<(f32 (uint_to_fp GR64:$src)),
4408 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4409 def : Pat<(f64 (uint_to_fp GR32:$src)),
4410 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4411 def : Pat<(f64 (uint_to_fp GR64:$src)),
4412 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4415 //===----------------------------------------------------------------------===//
4416 // AVX-512 Scalar convert from float/double to integer
4417 //===----------------------------------------------------------------------===//
4418 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4419 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
4421 let hasSideEffects = 0 in {
4422 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4423 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4424 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
4425 Requires<[HasAVX512]>;
4427 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4428 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
4429 Requires<[HasAVX512]>;
4430 } // hasSideEffects = 0
4432 let Predicates = [HasAVX512] in {
4433 // Convert float/double to signed/unsigned int 32/64
4434 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4435 ssmem, sse_load_f32, "cvtss2si">,
4436 XS, EVEX_CD8<32, CD8VT1>;
4437 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
4438 ssmem, sse_load_f32, "cvtss2si">,
4439 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4440 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
4441 ssmem, sse_load_f32, "cvtss2usi">,
4442 XS, EVEX_CD8<32, CD8VT1>;
4443 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4444 int_x86_avx512_cvtss2usi64, ssmem,
4445 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4446 EVEX_CD8<32, CD8VT1>;
4447 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4448 sdmem, sse_load_f64, "cvtsd2si">,
4449 XD, EVEX_CD8<64, CD8VT1>;
4450 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4451 sdmem, sse_load_f64, "cvtsd2si">,
4452 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4453 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4454 sdmem, sse_load_f64, "cvtsd2usi">,
4455 XD, EVEX_CD8<64, CD8VT1>;
4456 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4457 int_x86_avx512_cvtsd2usi64, sdmem,
4458 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4459 EVEX_CD8<64, CD8VT1>;
4461 let isCodeGenOnly = 1 in {
4462 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4463 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4464 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4465 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4466 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4467 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4468 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4469 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4470 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4471 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4472 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4473 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4475 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4476 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4477 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4478 } // isCodeGenOnly = 1
4480 // Convert float/double to signed/unsigned int 32/64 with truncation
4481 let isCodeGenOnly = 1 in {
4482 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4483 ssmem, sse_load_f32, "cvttss2si">,
4484 XS, EVEX_CD8<32, CD8VT1>;
4485 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4486 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4487 "cvttss2si">, XS, VEX_W,
4488 EVEX_CD8<32, CD8VT1>;
4489 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4490 sdmem, sse_load_f64, "cvttsd2si">, XD,
4491 EVEX_CD8<64, CD8VT1>;
4492 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4493 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4494 "cvttsd2si">, XD, VEX_W,
4495 EVEX_CD8<64, CD8VT1>;
4496 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4497 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4498 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4499 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4500 int_x86_avx512_cvttss2usi64, ssmem,
4501 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4502 EVEX_CD8<32, CD8VT1>;
4503 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4504 int_x86_avx512_cvttsd2usi,
4505 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4506 EVEX_CD8<64, CD8VT1>;
4507 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4508 int_x86_avx512_cvttsd2usi64, sdmem,
4509 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4510 EVEX_CD8<64, CD8VT1>;
4511 } // isCodeGenOnly = 1
4513 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4514 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4516 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4517 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4518 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4519 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4520 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4521 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4524 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4525 loadf32, "cvttss2si">, XS,
4526 EVEX_CD8<32, CD8VT1>;
4527 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4528 loadf32, "cvttss2usi">, XS,
4529 EVEX_CD8<32, CD8VT1>;
4530 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4531 loadf32, "cvttss2si">, XS, VEX_W,
4532 EVEX_CD8<32, CD8VT1>;
4533 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4534 loadf32, "cvttss2usi">, XS, VEX_W,
4535 EVEX_CD8<32, CD8VT1>;
4536 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4537 loadf64, "cvttsd2si">, XD,
4538 EVEX_CD8<64, CD8VT1>;
4539 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4540 loadf64, "cvttsd2usi">, XD,
4541 EVEX_CD8<64, CD8VT1>;
4542 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4543 loadf64, "cvttsd2si">, XD, VEX_W,
4544 EVEX_CD8<64, CD8VT1>;
4545 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4546 loadf64, "cvttsd2usi">, XD, VEX_W,
4547 EVEX_CD8<64, CD8VT1>;
4549 //===----------------------------------------------------------------------===//
4550 // AVX-512 Convert form float to double and back
4551 //===----------------------------------------------------------------------===//
4552 let hasSideEffects = 0 in {
4553 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4554 (ins FR32X:$src1, FR32X:$src2),
4555 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4556 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4558 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4559 (ins FR32X:$src1, f32mem:$src2),
4560 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4561 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4562 EVEX_CD8<32, CD8VT1>;
4564 // Convert scalar double to scalar single
4565 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4566 (ins FR64X:$src1, FR64X:$src2),
4567 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4568 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4570 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4571 (ins FR64X:$src1, f64mem:$src2),
4572 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4573 []>, EVEX_4V, VEX_LIG, VEX_W,
4574 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4577 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4578 Requires<[HasAVX512]>;
4579 def : Pat<(fextend (loadf32 addr:$src)),
4580 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4582 def : Pat<(extloadf32 addr:$src),
4583 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4584 Requires<[HasAVX512, OptForSize]>;
4586 def : Pat<(extloadf32 addr:$src),
4587 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4588 Requires<[HasAVX512, OptForSpeed]>;
4590 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4591 Requires<[HasAVX512]>;
4593 //===----------------------------------------------------------------------===//
4594 // AVX-512 Vector convert from signed/unsigned integer to float/double
4595 // and from float/double to signed/unsigned integer
4596 //===----------------------------------------------------------------------===//
4598 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4599 X86VectorVTInfo _Src, SDNode OpNode,
4600 string Broadcast = _.BroadcastStr,
4601 string Alias = ""> {
4603 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4604 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
4605 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
4607 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4608 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
4609 (_.VT (OpNode (_Src.VT
4610 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
4612 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4613 (ins _Src.MemOp:$src), OpcodeStr,
4614 "${src}"##Broadcast, "${src}"##Broadcast,
4615 (_.VT (OpNode (_Src.VT
4616 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
4619 // Coversion with SAE - suppress all exceptions
4620 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4621 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4622 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4623 (ins _Src.RC:$src), OpcodeStr,
4624 "{sae}, $src", "$src, {sae}",
4625 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
4626 (i32 FROUND_NO_EXC)))>,
4630 // Conversion with rounding control (RC)
4631 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4632 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4633 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4634 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
4635 "$rc, $src", "$src, $rc",
4636 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
4637 EVEX, EVEX_B, EVEX_RC;
4640 // Extend Float to Double
4641 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
4642 let Predicates = [HasAVX512] in {
4643 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
4644 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
4645 X86vfpextRnd>, EVEX_V512;
4647 let Predicates = [HasVLX] in {
4648 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
4649 X86vfpext, "{1to2}">, EVEX_V128;
4650 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
4655 // Truncate Double to Float
4656 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
4657 let Predicates = [HasAVX512] in {
4658 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
4659 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
4660 X86vfproundRnd>, EVEX_V512;
4662 let Predicates = [HasVLX] in {
4663 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
4664 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
4665 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
4666 "{1to4}", "{y}">, EVEX_V256;
4670 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
4671 VEX_W, PD, EVEX_CD8<64, CD8VF>;
4672 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
4673 PS, EVEX_CD8<32, CD8VH>;
4675 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4676 (VCVTPS2PDZrm addr:$src)>;
4678 let Predicates = [HasVLX] in {
4679 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
4680 (VCVTPS2PDZ256rm addr:$src)>;
4683 // Convert Signed/Unsigned Doubleword to Double
4684 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4686 // No rounding in this op
4687 let Predicates = [HasAVX512] in
4688 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
4691 let Predicates = [HasVLX] in {
4692 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
4693 OpNode128, "{1to2}">, EVEX_V128;
4694 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
4699 // Convert Signed/Unsigned Doubleword to Float
4700 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
4702 let Predicates = [HasAVX512] in
4703 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
4704 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
4705 OpNodeRnd>, EVEX_V512;
4707 let Predicates = [HasVLX] in {
4708 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
4710 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
4715 // Convert Float to Signed/Unsigned Doubleword with truncation
4716 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
4717 SDNode OpNode, SDNode OpNodeRnd> {
4718 let Predicates = [HasAVX512] in {
4719 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
4720 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
4721 OpNodeRnd>, EVEX_V512;
4723 let Predicates = [HasVLX] in {
4724 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
4726 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
4731 // Convert Float to Signed/Unsigned Doubleword
4732 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
4733 SDNode OpNode, SDNode OpNodeRnd> {
4734 let Predicates = [HasAVX512] in {
4735 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
4736 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
4737 OpNodeRnd>, EVEX_V512;
4739 let Predicates = [HasVLX] in {
4740 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
4742 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
4747 // Convert Double to Signed/Unsigned Doubleword with truncation
4748 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
4749 SDNode OpNode, SDNode OpNodeRnd> {
4750 let Predicates = [HasAVX512] in {
4751 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
4752 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
4753 OpNodeRnd>, EVEX_V512;
4755 let Predicates = [HasVLX] in {
4756 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
4757 // memory forms of these instructions in Asm Parcer. They have the same
4758 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
4759 // due to the same reason.
4760 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
4761 "{1to2}", "{x}">, EVEX_V128;
4762 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
4763 "{1to4}", "{y}">, EVEX_V256;
4767 // Convert Double to Signed/Unsigned Doubleword
4768 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
4769 SDNode OpNode, SDNode OpNodeRnd> {
4770 let Predicates = [HasAVX512] in {
4771 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
4772 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
4773 OpNodeRnd>, EVEX_V512;
4775 let Predicates = [HasVLX] in {
4776 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
4777 // memory forms of these instructions in Asm Parcer. They have the same
4778 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
4779 // due to the same reason.
4780 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
4781 "{1to2}", "{x}">, EVEX_V128;
4782 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
4783 "{1to4}", "{y}">, EVEX_V256;
4787 // Convert Double to Signed/Unsigned Quardword
4788 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
4789 SDNode OpNode, SDNode OpNodeRnd> {
4790 let Predicates = [HasDQI] in {
4791 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
4792 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
4793 OpNodeRnd>, EVEX_V512;
4795 let Predicates = [HasDQI, HasVLX] in {
4796 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
4798 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
4803 // Convert Double to Signed/Unsigned Quardword with truncation
4804 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
4805 SDNode OpNode, SDNode OpNodeRnd> {
4806 let Predicates = [HasDQI] in {
4807 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
4808 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
4809 OpNodeRnd>, EVEX_V512;
4811 let Predicates = [HasDQI, HasVLX] in {
4812 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
4814 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
4819 // Convert Signed/Unsigned Quardword to Double
4820 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
4821 SDNode OpNode, SDNode OpNodeRnd> {
4822 let Predicates = [HasDQI] in {
4823 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
4824 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
4825 OpNodeRnd>, EVEX_V512;
4827 let Predicates = [HasDQI, HasVLX] in {
4828 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
4830 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
4835 // Convert Float to Signed/Unsigned Quardword
4836 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
4837 SDNode OpNode, SDNode OpNodeRnd> {
4838 let Predicates = [HasDQI] in {
4839 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
4840 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
4841 OpNodeRnd>, EVEX_V512;
4843 let Predicates = [HasDQI, HasVLX] in {
4844 // Explicitly specified broadcast string, since we take only 2 elements
4845 // from v4f32x_info source
4846 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
4847 "{1to2}">, EVEX_V128;
4848 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
4853 // Convert Float to Signed/Unsigned Quardword with truncation
4854 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
4855 SDNode OpNode, SDNode OpNodeRnd> {
4856 let Predicates = [HasDQI] in {
4857 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
4858 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
4859 OpNodeRnd>, EVEX_V512;
4861 let Predicates = [HasDQI, HasVLX] in {
4862 // Explicitly specified broadcast string, since we take only 2 elements
4863 // from v4f32x_info source
4864 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
4865 "{1to2}">, EVEX_V128;
4866 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
4871 // Convert Signed/Unsigned Quardword to Float
4872 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
4873 SDNode OpNode, SDNode OpNodeRnd> {
4874 let Predicates = [HasDQI] in {
4875 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
4876 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
4877 OpNodeRnd>, EVEX_V512;
4879 let Predicates = [HasDQI, HasVLX] in {
4880 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
4881 // memory forms of these instructions in Asm Parcer. They have the same
4882 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
4883 // due to the same reason.
4884 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
4885 "{1to2}", "{x}">, EVEX_V128;
4886 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
4887 "{1to4}", "{y}">, EVEX_V256;
4891 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
4892 EVEX_CD8<32, CD8VH>;
4894 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
4896 PS, EVEX_CD8<32, CD8VF>;
4898 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
4900 XS, EVEX_CD8<32, CD8VF>;
4902 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
4904 PD, VEX_W, EVEX_CD8<64, CD8VF>;
4906 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
4907 X86VFpToUintRnd>, PS,
4908 EVEX_CD8<32, CD8VF>;
4910 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
4911 X86VFpToUintRnd>, PS, VEX_W,
4912 EVEX_CD8<64, CD8VF>;
4914 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
4915 XS, EVEX_CD8<32, CD8VH>;
4917 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
4918 X86VUintToFpRnd>, XD,
4919 EVEX_CD8<32, CD8VF>;
4921 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
4922 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
4924 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
4925 X86cvtpd2IntRnd>, XD, VEX_W,
4926 EVEX_CD8<64, CD8VF>;
4928 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
4930 PS, EVEX_CD8<32, CD8VF>;
4931 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
4932 X86cvtpd2UIntRnd>, VEX_W,
4933 PS, EVEX_CD8<64, CD8VF>;
4935 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
4936 X86cvtpd2IntRnd>, VEX_W,
4937 PD, EVEX_CD8<64, CD8VF>;
4939 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
4940 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
4942 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
4943 X86cvtpd2UIntRnd>, VEX_W,
4944 PD, EVEX_CD8<64, CD8VF>;
4946 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
4947 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
4949 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
4950 X86VFpToSlongRnd>, VEX_W,
4951 PD, EVEX_CD8<64, CD8VF>;
4953 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
4954 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
4956 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
4957 X86VFpToUlongRnd>, VEX_W,
4958 PD, EVEX_CD8<64, CD8VF>;
4960 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
4961 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
4963 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
4964 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
4966 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
4967 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
4969 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
4970 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
4972 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
4973 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
4975 let Predicates = [NoVLX] in {
4976 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4977 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4978 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4980 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4981 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4982 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4984 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4985 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4986 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4988 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4989 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4990 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4992 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4993 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4994 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4997 let Predicates = [HasAVX512] in {
4998 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4999 (VCVTPD2PSZrm addr:$src)>;
5000 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5001 (VCVTPS2PDZrm addr:$src)>;
5004 //===----------------------------------------------------------------------===//
5005 // Half precision conversion instructions
5006 //===----------------------------------------------------------------------===//
5007 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
5008 X86MemOperand x86memop> {
5009 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
5010 "vcvtph2ps\t{$src, $dst|$dst, $src}",
5012 let hasSideEffects = 0, mayLoad = 1 in
5013 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
5014 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
5017 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
5018 X86MemOperand x86memop> {
5019 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
5020 (ins srcRC:$src1, i32u8imm:$src2),
5021 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5023 let hasSideEffects = 0, mayStore = 1 in
5024 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5025 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
5026 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
5029 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
5030 EVEX_CD8<32, CD8VH>;
5031 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
5032 EVEX_CD8<32, CD8VH>;
5034 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
5035 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
5036 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
5038 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
5039 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
5040 (VCVTPH2PSZrr VR256X:$src)>;
5042 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5043 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5044 "ucomiss">, PS, EVEX, VEX_LIG,
5045 EVEX_CD8<32, CD8VT1>;
5046 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5047 "ucomisd">, PD, EVEX,
5048 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5049 let Pattern = []<dag> in {
5050 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5051 "comiss">, PS, EVEX, VEX_LIG,
5052 EVEX_CD8<32, CD8VT1>;
5053 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5054 "comisd">, PD, EVEX,
5055 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5057 let isCodeGenOnly = 1 in {
5058 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5059 load, "ucomiss">, PS, EVEX, VEX_LIG,
5060 EVEX_CD8<32, CD8VT1>;
5061 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5062 load, "ucomisd">, PD, EVEX,
5063 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5065 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5066 load, "comiss">, PS, EVEX, VEX_LIG,
5067 EVEX_CD8<32, CD8VT1>;
5068 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5069 load, "comisd">, PD, EVEX,
5070 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5074 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5075 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
5076 X86MemOperand x86memop> {
5077 let hasSideEffects = 0 in {
5078 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5079 (ins RC:$src1, RC:$src2),
5080 !strconcat(OpcodeStr,
5081 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
5082 let mayLoad = 1 in {
5083 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5084 (ins RC:$src1, x86memop:$src2),
5085 !strconcat(OpcodeStr,
5086 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
5091 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
5092 EVEX_CD8<32, CD8VT1>;
5093 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
5094 VEX_W, EVEX_CD8<64, CD8VT1>;
5095 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
5096 EVEX_CD8<32, CD8VT1>;
5097 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
5098 VEX_W, EVEX_CD8<64, CD8VT1>;
5100 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
5101 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
5102 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
5103 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
5105 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
5106 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
5107 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
5108 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
5110 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
5111 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
5112 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
5113 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
5115 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
5116 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
5117 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
5118 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
5120 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5121 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5122 X86VectorVTInfo _> {
5123 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5124 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5125 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5126 let mayLoad = 1 in {
5127 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5128 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5130 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5131 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5132 (ins _.ScalarMemOp:$src), OpcodeStr,
5133 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5135 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5140 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5141 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5142 EVEX_V512, EVEX_CD8<32, CD8VF>;
5143 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5144 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5146 // Define only if AVX512VL feature is present.
5147 let Predicates = [HasVLX] in {
5148 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5149 OpNode, v4f32x_info>,
5150 EVEX_V128, EVEX_CD8<32, CD8VF>;
5151 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5152 OpNode, v8f32x_info>,
5153 EVEX_V256, EVEX_CD8<32, CD8VF>;
5154 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5155 OpNode, v2f64x_info>,
5156 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5157 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5158 OpNode, v4f64x_info>,
5159 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5163 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5164 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5166 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5167 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5168 (VRSQRT14PSZr VR512:$src)>;
5169 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5170 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5171 (VRSQRT14PDZr VR512:$src)>;
5173 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5174 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5175 (VRCP14PSZr VR512:$src)>;
5176 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5177 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5178 (VRCP14PDZr VR512:$src)>;
5180 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5181 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5184 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5185 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5186 "$src2, $src1", "$src1, $src2",
5187 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5188 (i32 FROUND_CURRENT))>;
5190 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5191 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5192 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5193 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5194 (i32 FROUND_NO_EXC))>, EVEX_B;
5196 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5197 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5198 "$src2, $src1", "$src1, $src2",
5199 (OpNode (_.VT _.RC:$src1),
5200 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5201 (i32 FROUND_CURRENT))>;
5204 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5205 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5206 EVEX_CD8<32, CD8VT1>;
5207 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5208 EVEX_CD8<64, CD8VT1>, VEX_W;
5211 let hasSideEffects = 0, Predicates = [HasERI] in {
5212 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5213 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5216 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5217 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5219 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5222 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5223 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5224 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5226 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5227 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5229 (bitconvert (_.LdFrag addr:$src))),
5230 (i32 FROUND_CURRENT))>;
5232 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5233 (ins _.MemOp:$src), OpcodeStr,
5234 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5236 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5237 (i32 FROUND_CURRENT))>, EVEX_B;
5239 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5241 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5242 (ins _.RC:$src), OpcodeStr,
5243 "{sae}, $src", "$src, {sae}",
5244 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5247 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5248 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5249 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5250 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5251 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5252 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5253 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5256 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5258 // Define only if AVX512VL feature is present.
5259 let Predicates = [HasVLX] in {
5260 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5261 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5262 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5263 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5264 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5265 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5266 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5267 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5270 let Predicates = [HasERI], hasSideEffects = 0 in {
5272 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5273 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5274 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5276 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5277 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5279 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5280 SDNode OpNodeRnd, X86VectorVTInfo _>{
5281 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5282 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5283 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5284 EVEX, EVEX_B, EVEX_RC;
5287 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5288 SDNode OpNode, X86VectorVTInfo _>{
5289 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5290 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5291 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5292 let mayLoad = 1 in {
5293 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5294 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5296 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5298 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5299 (ins _.ScalarMemOp:$src), OpcodeStr,
5300 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5302 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5307 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
5308 Intrinsic F32Int, Intrinsic F64Int,
5309 OpndItins itins_s, OpndItins itins_d> {
5310 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
5311 (ins FR32X:$src1, FR32X:$src2),
5312 !strconcat(OpcodeStr,
5313 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5314 [], itins_s.rr>, XS, EVEX_4V;
5315 let isCodeGenOnly = 1 in
5316 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
5317 (ins VR128X:$src1, VR128X:$src2),
5318 !strconcat(OpcodeStr,
5319 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5321 (F32Int VR128X:$src1, VR128X:$src2))],
5322 itins_s.rr>, XS, EVEX_4V;
5323 let mayLoad = 1 in {
5324 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
5325 (ins FR32X:$src1, f32mem:$src2),
5326 !strconcat(OpcodeStr,
5327 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5328 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5329 let isCodeGenOnly = 1 in
5330 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
5331 (ins VR128X:$src1, ssmem:$src2),
5332 !strconcat(OpcodeStr,
5333 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5335 (F32Int VR128X:$src1, sse_load_f32:$src2))],
5336 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5338 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
5339 (ins FR64X:$src1, FR64X:$src2),
5340 !strconcat(OpcodeStr,
5341 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
5343 let isCodeGenOnly = 1 in
5344 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
5345 (ins VR128X:$src1, VR128X:$src2),
5346 !strconcat(OpcodeStr,
5347 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5349 (F64Int VR128X:$src1, VR128X:$src2))],
5350 itins_s.rr>, XD, EVEX_4V, VEX_W;
5351 let mayLoad = 1 in {
5352 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
5353 (ins FR64X:$src1, f64mem:$src2),
5354 !strconcat(OpcodeStr,
5355 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
5356 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
5357 let isCodeGenOnly = 1 in
5358 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
5359 (ins VR128X:$src1, sdmem:$src2),
5360 !strconcat(OpcodeStr,
5361 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5363 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
5364 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
5368 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5370 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5372 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5373 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5375 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5376 // Define only if AVX512VL feature is present.
5377 let Predicates = [HasVLX] in {
5378 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5379 OpNode, v4f32x_info>,
5380 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5381 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5382 OpNode, v8f32x_info>,
5383 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5384 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5385 OpNode, v2f64x_info>,
5386 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5387 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5388 OpNode, v4f64x_info>,
5389 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5393 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5395 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5396 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5397 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5398 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5401 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5402 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5404 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
5405 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
5406 SSE_SQRTSS, SSE_SQRTSD>;
5408 let Predicates = [HasAVX512] in {
5409 def : Pat<(f32 (fsqrt FR32X:$src)),
5410 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5411 def : Pat<(f32 (fsqrt (load addr:$src))),
5412 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
5413 Requires<[OptForSize]>;
5414 def : Pat<(f64 (fsqrt FR64X:$src)),
5415 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
5416 def : Pat<(f64 (fsqrt (load addr:$src))),
5417 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
5418 Requires<[OptForSize]>;
5420 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5421 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5422 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5423 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5424 Requires<[OptForSize]>;
5426 def : Pat<(f32 (X86frcp FR32X:$src)),
5427 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5428 def : Pat<(f32 (X86frcp (load addr:$src))),
5429 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5430 Requires<[OptForSize]>;
5432 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
5433 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
5434 (COPY_TO_REGCLASS VR128X:$src, FR32)),
5436 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
5437 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
5439 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
5440 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
5441 (COPY_TO_REGCLASS VR128X:$src, FR64)),
5443 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
5444 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
5448 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5450 let ExeDomain = _.ExeDomain in {
5451 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5452 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5453 "$src3, $src2, $src1", "$src1, $src2, $src3",
5454 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5455 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5457 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5458 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5459 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5460 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5461 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5464 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5465 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5466 "$src3, $src2, $src1", "$src1, $src2, $src3",
5467 (_.VT (X86RndScales (_.VT _.RC:$src1),
5468 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5469 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5471 let Predicates = [HasAVX512] in {
5472 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5473 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5474 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5475 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5476 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5477 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5478 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5479 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5480 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5481 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5482 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5483 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5484 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5485 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5486 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5488 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5489 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5490 addr:$src, (i32 0x1))), _.FRC)>;
5491 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5492 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5493 addr:$src, (i32 0x2))), _.FRC)>;
5494 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5495 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5496 addr:$src, (i32 0x3))), _.FRC)>;
5497 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5498 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5499 addr:$src, (i32 0x4))), _.FRC)>;
5500 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5501 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5502 addr:$src, (i32 0xc))), _.FRC)>;
5506 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5507 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5509 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5510 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5512 //-------------------------------------------------
5513 // Integer truncate and extend operations
5514 //-------------------------------------------------
5516 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5517 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5518 X86MemOperand x86memop> {
5520 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5521 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5522 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5525 // for intrinsic patter match
5526 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5527 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5529 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5532 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5533 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5534 DestInfo.ImmAllZerosV)),
5535 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5538 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5539 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5540 DestInfo.RC:$src0)),
5541 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5542 DestInfo.KRCWM:$mask ,
5545 let mayStore = 1 in {
5546 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5547 (ins x86memop:$dst, SrcInfo.RC:$src),
5548 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5551 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5552 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5553 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5558 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5559 X86VectorVTInfo DestInfo,
5560 PatFrag truncFrag, PatFrag mtruncFrag > {
5562 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5563 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5564 addr:$dst, SrcInfo.RC:$src)>;
5566 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5567 (SrcInfo.VT SrcInfo.RC:$src)),
5568 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5569 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
5572 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
5573 X86VectorVTInfo DestInfo, string sat > {
5575 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5576 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5577 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
5578 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
5579 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
5580 (SrcInfo.VT SrcInfo.RC:$src))>;
5582 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5583 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5584 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
5585 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
5586 (SrcInfo.VT SrcInfo.RC:$src))>;
5589 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
5590 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5591 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5592 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5593 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
5594 Predicate prd = HasAVX512>{
5596 let Predicates = [HasVLX, prd] in {
5597 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5598 DestInfoZ128, x86memopZ128>,
5599 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5600 truncFrag, mtruncFrag>, EVEX_V128;
5602 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5603 DestInfoZ256, x86memopZ256>,
5604 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5605 truncFrag, mtruncFrag>, EVEX_V256;
5607 let Predicates = [prd] in
5608 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5609 DestInfoZ, x86memopZ>,
5610 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5611 truncFrag, mtruncFrag>, EVEX_V512;
5614 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
5615 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5616 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5617 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5618 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
5620 let Predicates = [HasVLX, prd] in {
5621 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5622 DestInfoZ128, x86memopZ128>,
5623 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5626 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5627 DestInfoZ256, x86memopZ256>,
5628 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5631 let Predicates = [prd] in
5632 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5633 DestInfoZ, x86memopZ>,
5634 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5638 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5639 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5640 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5641 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
5643 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
5644 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
5645 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5646 sat>, EVEX_CD8<8, CD8VO>;
5649 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5650 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5651 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5652 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
5654 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
5655 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
5656 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5657 sat>, EVEX_CD8<16, CD8VQ>;
5660 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5661 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5662 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5663 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
5665 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
5666 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
5667 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5668 sat>, EVEX_CD8<32, CD8VH>;
5671 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5672 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5673 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5674 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
5676 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
5677 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
5678 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5679 sat>, EVEX_CD8<8, CD8VQ>;
5682 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5683 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5684 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5685 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
5687 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
5688 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
5689 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5690 sat>, EVEX_CD8<16, CD8VH>;
5693 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5694 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
5695 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5696 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
5698 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
5699 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
5700 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5701 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
5704 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
5705 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
5706 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
5708 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
5709 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
5710 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
5712 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
5713 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
5714 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
5716 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
5717 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
5718 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
5720 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
5721 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
5722 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
5724 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
5725 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
5726 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
5728 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
5729 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
5730 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
5732 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
5733 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
5734 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
5737 let mayLoad = 1 in {
5738 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
5739 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
5740 (DestInfo.VT (LdFrag addr:$src))>,
5745 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
5746 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5747 let Predicates = [HasVLX, HasBWI] in {
5748 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
5749 v16i8x_info, i64mem, LdFrag, OpNode>,
5750 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
5752 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
5753 v16i8x_info, i128mem, LdFrag, OpNode>,
5754 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
5756 let Predicates = [HasBWI] in {
5757 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
5758 v32i8x_info, i256mem, LdFrag, OpNode>,
5759 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
5763 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5764 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5765 let Predicates = [HasVLX, HasAVX512] in {
5766 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5767 v16i8x_info, i32mem, LdFrag, OpNode>,
5768 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
5770 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5771 v16i8x_info, i64mem, LdFrag, OpNode>,
5772 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
5774 let Predicates = [HasAVX512] in {
5775 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5776 v16i8x_info, i128mem, LdFrag, OpNode>,
5777 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
5781 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5782 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5783 let Predicates = [HasVLX, HasAVX512] in {
5784 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5785 v16i8x_info, i16mem, LdFrag, OpNode>,
5786 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
5788 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5789 v16i8x_info, i32mem, LdFrag, OpNode>,
5790 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
5792 let Predicates = [HasAVX512] in {
5793 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5794 v16i8x_info, i64mem, LdFrag, OpNode>,
5795 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
5799 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5800 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5801 let Predicates = [HasVLX, HasAVX512] in {
5802 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5803 v8i16x_info, i64mem, LdFrag, OpNode>,
5804 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
5806 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5807 v8i16x_info, i128mem, LdFrag, OpNode>,
5808 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
5810 let Predicates = [HasAVX512] in {
5811 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5812 v16i16x_info, i256mem, LdFrag, OpNode>,
5813 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
5817 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5818 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5819 let Predicates = [HasVLX, HasAVX512] in {
5820 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5821 v8i16x_info, i32mem, LdFrag, OpNode>,
5822 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
5824 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5825 v8i16x_info, i64mem, LdFrag, OpNode>,
5826 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
5828 let Predicates = [HasAVX512] in {
5829 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5830 v8i16x_info, i128mem, LdFrag, OpNode>,
5831 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
5835 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5836 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
5838 let Predicates = [HasVLX, HasAVX512] in {
5839 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5840 v4i32x_info, i64mem, LdFrag, OpNode>,
5841 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
5843 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5844 v4i32x_info, i128mem, LdFrag, OpNode>,
5845 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
5847 let Predicates = [HasAVX512] in {
5848 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5849 v8i32x_info, i256mem, LdFrag, OpNode>,
5850 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
5854 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
5855 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
5856 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
5857 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
5858 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
5859 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
5862 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
5863 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
5864 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
5865 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
5866 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
5867 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
5869 //===----------------------------------------------------------------------===//
5870 // GATHER - SCATTER Operations
5872 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5873 X86MemOperand memop, PatFrag GatherNode> {
5874 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
5875 ExeDomain = _.ExeDomain in
5876 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
5877 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
5878 !strconcat(OpcodeStr#_.Suffix,
5879 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5880 [(set _.RC:$dst, _.KRCWM:$mask_wb,
5881 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
5882 vectoraddr:$src2))]>, EVEX, EVEX_K,
5883 EVEX_CD8<_.EltSize, CD8VT1>;
5886 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
5887 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
5888 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
5889 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
5890 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
5891 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
5892 let Predicates = [HasVLX] in {
5893 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
5894 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
5895 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
5896 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
5897 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
5898 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
5899 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
5900 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
5904 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
5905 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
5906 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
5907 mgatherv16i32>, EVEX_V512;
5908 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
5909 mgatherv8i64>, EVEX_V512;
5910 let Predicates = [HasVLX] in {
5911 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
5912 vy32xmem, mgatherv8i32>, EVEX_V256;
5913 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
5914 vy64xmem, mgatherv4i64>, EVEX_V256;
5915 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
5916 vx32xmem, mgatherv4i32>, EVEX_V128;
5917 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
5918 vx64xmem, mgatherv2i64>, EVEX_V128;
5923 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
5924 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
5926 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
5927 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
5929 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5930 X86MemOperand memop, PatFrag ScatterNode> {
5932 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
5934 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
5935 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
5936 !strconcat(OpcodeStr#_.Suffix,
5937 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5938 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
5939 _.KRCWM:$mask, vectoraddr:$dst))]>,
5940 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5943 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
5944 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
5945 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
5946 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
5947 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
5948 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
5949 let Predicates = [HasVLX] in {
5950 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
5951 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
5952 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
5953 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
5954 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
5955 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
5956 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
5957 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
5961 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
5962 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
5963 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
5964 mscatterv16i32>, EVEX_V512;
5965 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
5966 mscatterv8i64>, EVEX_V512;
5967 let Predicates = [HasVLX] in {
5968 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
5969 vy32xmem, mscatterv8i32>, EVEX_V256;
5970 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
5971 vy64xmem, mscatterv4i64>, EVEX_V256;
5972 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
5973 vx32xmem, mscatterv4i32>, EVEX_V128;
5974 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
5975 vx64xmem, mscatterv2i64>, EVEX_V128;
5979 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
5980 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
5982 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
5983 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
5986 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
5987 RegisterClass KRC, X86MemOperand memop> {
5988 let Predicates = [HasPFI], hasSideEffects = 1 in
5989 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
5990 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
5994 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
5995 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5997 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5998 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6000 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6001 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6003 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6004 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6006 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6007 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6009 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6010 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6012 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6013 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6015 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6016 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6018 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6019 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6021 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6022 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6024 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6025 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6027 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6028 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6030 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6031 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6033 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6034 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6036 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6037 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6039 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6040 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6041 //===----------------------------------------------------------------------===//
6042 // VSHUFPS - VSHUFPD Operations
6044 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
6045 ValueType vt, string OpcodeStr, PatFrag mem_frag,
6047 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
6048 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6049 !strconcat(OpcodeStr,
6050 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6051 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
6052 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
6053 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
6054 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
6055 (ins RC:$src1, RC:$src2, u8imm:$src3),
6056 !strconcat(OpcodeStr,
6057 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6058 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
6059 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
6060 EVEX_4V, Sched<[WriteShuffle]>;
6063 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
6064 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
6065 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
6066 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
6068 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
6069 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
6070 def : Pat<(v16i32 (X86Shufp VR512:$src1,
6071 (loadv16i32 addr:$src2), (i8 imm:$imm))),
6072 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
6074 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
6075 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
6076 def : Pat<(v8i64 (X86Shufp VR512:$src1,
6077 (loadv8i64 addr:$src2), (i8 imm:$imm))),
6078 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
6080 // Helper fragments to match sext vXi1 to vXiY.
6081 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6082 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6084 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
6085 RegisterClass RC, RegisterClass KRC,
6086 X86MemOperand x86memop,
6087 X86MemOperand x86scalar_mop, string BrdcstStr> {
6088 let hasSideEffects = 0 in {
6089 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
6091 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
6094 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6095 (ins x86memop:$src),
6096 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
6099 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6100 (ins x86scalar_mop:$src),
6101 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
6102 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
6104 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
6105 (ins KRC:$mask, RC:$src),
6106 !strconcat(OpcodeStr,
6107 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
6110 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6111 (ins KRC:$mask, x86memop:$src),
6112 !strconcat(OpcodeStr,
6113 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
6116 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6117 (ins KRC:$mask, x86scalar_mop:$src),
6118 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
6119 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
6121 []>, EVEX, EVEX_KZ, EVEX_B;
6123 let Constraints = "$src1 = $dst" in {
6124 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
6125 (ins RC:$src1, KRC:$mask, RC:$src2),
6126 !strconcat(OpcodeStr,
6127 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6130 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6131 (ins RC:$src1, KRC:$mask, x86memop:$src2),
6132 !strconcat(OpcodeStr,
6133 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6136 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
6137 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
6138 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
6139 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
6140 []>, EVEX, EVEX_K, EVEX_B;
6145 let Predicates = [HasCDI] in {
6146 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
6147 i512mem, i32mem, "{1to16}">,
6148 EVEX_V512, EVEX_CD8<32, CD8VF>;
6151 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
6152 i512mem, i64mem, "{1to8}">,
6153 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
6157 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
6159 (VPCONFLICTDrrk VR512:$src1,
6160 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
6162 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
6164 (VPCONFLICTQrrk VR512:$src1,
6165 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
6167 let Predicates = [HasCDI] in {
6168 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
6169 i512mem, i32mem, "{1to16}">,
6170 EVEX_V512, EVEX_CD8<32, CD8VF>;
6173 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
6174 i512mem, i64mem, "{1to8}">,
6175 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
6179 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
6181 (VPLZCNTDrrk VR512:$src1,
6182 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
6184 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
6186 (VPLZCNTQrrk VR512:$src1,
6187 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
6189 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
6190 (VPLZCNTDrm addr:$src)>;
6191 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
6192 (VPLZCNTDrr VR512:$src)>;
6193 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
6194 (VPLZCNTQrm addr:$src)>;
6195 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
6196 (VPLZCNTQrr VR512:$src)>;
6198 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6199 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6200 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6202 def : Pat<(store VK1:$src, addr:$dst),
6204 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6205 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6207 def : Pat<(store VK8:$src, addr:$dst),
6209 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6210 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6212 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6213 (truncstore node:$val, node:$ptr), [{
6214 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6217 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6218 (MOV8mr addr:$dst, GR8:$src)>;
6220 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6221 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6222 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6223 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6226 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6227 string OpcodeStr, Predicate prd> {
6228 let Predicates = [prd] in
6229 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6231 let Predicates = [prd, HasVLX] in {
6232 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6233 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6237 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6238 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6240 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6242 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6244 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6248 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6250 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6251 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6252 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6253 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6256 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6257 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6258 let Predicates = [prd] in
6259 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6262 let Predicates = [prd, HasVLX] in {
6263 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6265 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6270 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6271 avx512vl_i8_info, HasBWI>;
6272 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6273 avx512vl_i16_info, HasBWI>, VEX_W;
6274 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6275 avx512vl_i32_info, HasDQI>;
6276 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6277 avx512vl_i64_info, HasDQI>, VEX_W;
6279 //===----------------------------------------------------------------------===//
6280 // AVX-512 - COMPRESS and EXPAND
6283 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6285 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6286 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6287 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6289 let mayStore = 1 in {
6290 def mr : AVX5128I<opc, MRMDestMem, (outs),
6291 (ins _.MemOp:$dst, _.RC:$src),
6292 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6293 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6295 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6296 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6297 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6298 [(store (_.VT (vselect _.KRCWM:$mask,
6299 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6301 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6305 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6306 AVX512VLVectorVTInfo VTInfo> {
6307 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6309 let Predicates = [HasVLX] in {
6310 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6311 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6315 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6317 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6319 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6321 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6325 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6327 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6328 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6329 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6332 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6333 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6334 (_.VT (X86expand (_.VT (bitconvert
6335 (_.LdFrag addr:$src1)))))>,
6336 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6339 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6340 AVX512VLVectorVTInfo VTInfo> {
6341 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6343 let Predicates = [HasVLX] in {
6344 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6345 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6349 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6351 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6353 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6355 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6358 //handle instruction reg_vec1 = op(reg_vec,imm)
6360 // op(broadcast(eltVt),imm)
6361 //all instruction created with FROUND_CURRENT
6362 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6364 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6365 (ins _.RC:$src1, i32u8imm:$src2),
6366 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6367 (OpNode (_.VT _.RC:$src1),
6369 (i32 FROUND_CURRENT))>;
6370 let mayLoad = 1 in {
6371 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6372 (ins _.MemOp:$src1, i32u8imm:$src2),
6373 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6374 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6376 (i32 FROUND_CURRENT))>;
6377 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6378 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6379 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6380 "${src1}"##_.BroadcastStr##", $src2",
6381 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6383 (i32 FROUND_CURRENT))>, EVEX_B;
6387 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6388 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6389 SDNode OpNode, X86VectorVTInfo _>{
6390 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6391 (ins _.RC:$src1, i32u8imm:$src2),
6392 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6393 "$src1, {sae}, $src2",
6394 (OpNode (_.VT _.RC:$src1),
6396 (i32 FROUND_NO_EXC))>, EVEX_B;
6399 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6400 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6401 let Predicates = [prd] in {
6402 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6403 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6406 let Predicates = [prd, HasVLX] in {
6407 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6409 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6414 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6415 // op(reg_vec2,mem_vec,imm)
6416 // op(reg_vec2,broadcast(eltVt),imm)
6417 //all instruction created with FROUND_CURRENT
6418 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6420 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6421 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6422 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6423 (OpNode (_.VT _.RC:$src1),
6426 (i32 FROUND_CURRENT))>;
6427 let mayLoad = 1 in {
6428 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6429 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6430 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6431 (OpNode (_.VT _.RC:$src1),
6432 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6434 (i32 FROUND_CURRENT))>;
6435 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6436 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6437 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6438 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6439 (OpNode (_.VT _.RC:$src1),
6440 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6442 (i32 FROUND_CURRENT))>, EVEX_B;
6446 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6447 // op(reg_vec2,mem_vec,imm)
6448 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6449 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6451 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6452 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6453 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6454 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6455 (SrcInfo.VT SrcInfo.RC:$src2),
6458 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6459 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6460 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6461 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6462 (SrcInfo.VT (bitconvert
6463 (SrcInfo.LdFrag addr:$src2))),
6467 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6468 // op(reg_vec2,mem_vec,imm)
6469 // op(reg_vec2,broadcast(eltVt),imm)
6470 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6472 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6475 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6476 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6477 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6478 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6479 (OpNode (_.VT _.RC:$src1),
6480 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6481 (i8 imm:$src3))>, EVEX_B;
6484 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6485 // op(reg_vec2,mem_scalar,imm)
6486 //all instruction created with FROUND_CURRENT
6487 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6488 X86VectorVTInfo _> {
6490 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6491 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6492 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6493 (OpNode (_.VT _.RC:$src1),
6496 (i32 FROUND_CURRENT))>;
6497 let mayLoad = 1 in {
6498 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6499 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6500 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6501 (OpNode (_.VT _.RC:$src1),
6502 (_.VT (scalar_to_vector
6503 (_.ScalarLdFrag addr:$src2))),
6505 (i32 FROUND_CURRENT))>;
6507 let isAsmParserOnly = 1 in {
6508 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6509 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6510 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6516 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6517 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6518 SDNode OpNode, X86VectorVTInfo _>{
6519 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6520 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6521 OpcodeStr, "$src3,{sae}, $src2, $src1",
6522 "$src1, $src2,{sae}, $src3",
6523 (OpNode (_.VT _.RC:$src1),
6526 (i32 FROUND_NO_EXC))>, EVEX_B;
6528 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6529 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6530 SDNode OpNode, X86VectorVTInfo _> {
6531 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6532 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6533 OpcodeStr, "$src3,{sae}, $src2, $src1",
6534 "$src1, $src2,{sae}, $src3",
6535 (OpNode (_.VT _.RC:$src1),
6538 (i32 FROUND_NO_EXC))>, EVEX_B;
6541 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6542 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6543 let Predicates = [prd] in {
6544 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6545 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6549 let Predicates = [prd, HasVLX] in {
6550 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6552 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6557 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6558 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6559 let Predicates = [HasBWI] in {
6560 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6561 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6563 let Predicates = [HasBWI, HasVLX] in {
6564 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6565 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6566 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6567 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6571 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6572 bits<8> opc, SDNode OpNode>{
6573 let Predicates = [HasAVX512] in {
6574 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6576 let Predicates = [HasAVX512, HasVLX] in {
6577 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6578 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6582 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6583 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6584 let Predicates = [prd] in {
6585 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6586 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6590 multiclass avx512_common_fp_sae_packed_imm_all<string OpcodeStr, bits<8> opcPs,
6591 bits<8> opcPd, SDNode OpNode, Predicate prd>{
6592 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info, opcPs,
6593 OpNode, prd>, EVEX_CD8<32, CD8VF>;
6594 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info, opcPd,
6595 OpNode, prd>,EVEX_CD8<64, CD8VF> , VEX_W;
6598 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6599 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6600 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6601 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6602 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6603 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6605 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6606 0x55, X86VFixupimm, HasAVX512>,
6607 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6608 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6609 0x55, X86VFixupimm, HasAVX512>,
6610 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6612 defm VREDUCE : avx512_common_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56, X86VReduce, HasDQI>,AVX512AIi8Base,EVEX;
6613 defm VRNDSCALE : avx512_common_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09, X86VRndScale, HasAVX512>,AVX512AIi8Base, EVEX;
6615 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6616 0x50, X86VRange, HasDQI>,
6617 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6618 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6619 0x50, X86VRange, HasDQI>,
6620 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6622 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6623 0x51, X86VRange, HasDQI>,
6624 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6625 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6626 0x51, X86VRange, HasDQI>,
6627 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6629 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6630 0x57, X86Reduces, HasDQI>,
6631 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6632 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6633 0x57, X86Reduces, HasDQI>,
6634 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6636 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6637 bits<8> opc, SDNode OpNode = X86Shuf128>{
6638 let Predicates = [HasAVX512] in {
6639 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6642 let Predicates = [HasAVX512, HasVLX] in {
6643 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6646 let Predicates = [HasAVX512] in {
6647 def : Pat<(v16f32 (ffloor VR512:$src)),
6648 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6649 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6650 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6651 def : Pat<(v16f32 (fceil VR512:$src)),
6652 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6653 def : Pat<(v16f32 (frint VR512:$src)),
6654 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6655 def : Pat<(v16f32 (ftrunc VR512:$src)),
6656 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6658 def : Pat<(v8f64 (ffloor VR512:$src)),
6659 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6660 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6661 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6662 def : Pat<(v8f64 (fceil VR512:$src)),
6663 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6664 def : Pat<(v8f64 (frint VR512:$src)),
6665 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6666 def : Pat<(v8f64 (ftrunc VR512:$src)),
6667 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6670 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6671 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6672 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6673 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6674 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6675 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6676 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6677 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6679 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6680 AVX512VLVectorVTInfo VTInfo_FP>{
6681 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6682 AVX512AIi8Base, EVEX_4V;
6683 let isCodeGenOnly = 1 in {
6684 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6685 AVX512AIi8Base, EVEX_4V;
6689 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6690 EVEX_CD8<32, CD8VF>;
6691 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6692 EVEX_CD8<64, CD8VF>, VEX_W;
6694 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
6695 let Predicates = p in
6696 def NAME#_.VTName#rri:
6697 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
6698 (!cast<Instruction>(NAME#_.ZSuffix#rri)
6699 _.RC:$src1, _.RC:$src2, imm:$imm)>;
6702 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
6703 avx512_vpalign_lowering<_.info512, [HasBWI]>,
6704 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
6705 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
6707 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
6708 avx512vl_i8_info, avx512vl_i8_info>,
6709 avx512_vpalign_lowering_common<avx512vl_i16_info>,
6710 avx512_vpalign_lowering_common<avx512vl_i32_info>,
6711 avx512_vpalign_lowering_common<avx512vl_f32_info>,
6712 avx512_vpalign_lowering_common<avx512vl_i64_info>,
6713 avx512_vpalign_lowering_common<avx512vl_f64_info>,
6716 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6717 X86VectorVTInfo _> {
6718 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6719 (ins _.RC:$src1), OpcodeStr##_.Suffix,
6721 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
6724 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6725 (ins _.MemOp:$src1), OpcodeStr##_.Suffix,
6727 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
6728 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
6731 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
6732 X86VectorVTInfo _> :
6733 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
6735 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6736 (ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
6737 "${src1}"##_.BroadcastStr,
6738 "${src1}"##_.BroadcastStr,
6739 (_.VT (OpNode (X86VBroadcast
6740 (_.ScalarLdFrag addr:$src1))))>,
6741 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
6744 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6745 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6746 let Predicates = [prd] in
6747 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
6749 let Predicates = [prd, HasVLX] in {
6750 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
6752 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
6757 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6758 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6759 let Predicates = [prd] in
6760 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
6763 let Predicates = [prd, HasVLX] in {
6764 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
6766 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
6771 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
6772 SDNode OpNode, Predicate prd> {
6773 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
6775 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
6778 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
6779 SDNode OpNode, Predicate prd> {
6780 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
6781 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
6784 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
6785 bits<8> opc_d, bits<8> opc_q,
6786 string OpcodeStr, SDNode OpNode> {
6787 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
6789 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
6793 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
6796 (bc_v16i32 (v16i1sextv16i32)),
6797 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
6798 (VPABSDZrr VR512:$src)>;
6800 (bc_v8i64 (v8i1sextv8i64)),
6801 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
6802 (VPABSQZrr VR512:$src)>;
6804 //===----------------------------------------------------------------------===//
6805 // AVX-512 - Unpack Instructions
6806 //===----------------------------------------------------------------------===//
6807 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
6808 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
6810 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
6811 SSE_INTALU_ITINS_P, HasBWI>;
6812 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
6813 SSE_INTALU_ITINS_P, HasBWI>;
6814 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
6815 SSE_INTALU_ITINS_P, HasBWI>;
6816 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
6817 SSE_INTALU_ITINS_P, HasBWI>;
6819 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
6820 SSE_INTALU_ITINS_P, HasAVX512>;
6821 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
6822 SSE_INTALU_ITINS_P, HasAVX512>;
6823 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
6824 SSE_INTALU_ITINS_P, HasAVX512>;
6825 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
6826 SSE_INTALU_ITINS_P, HasAVX512>;