1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
8 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
11 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
12 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
13 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
14 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
15 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
16 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
17 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
18 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
19 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
20 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
21 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
22 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
23 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
24 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
25 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
26 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
27 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
28 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
29 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
30 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
31 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
32 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
33 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
35 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
36 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
37 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
38 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
39 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
40 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
41 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
42 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
43 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
44 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
45 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
46 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
47 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
48 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
49 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
50 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
51 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
52 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
53 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
54 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
55 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
56 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
57 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
58 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
59 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
60 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
61 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
62 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
63 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
64 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
66 // Bitcasts between 256-bit vector types. Return the original type since
67 // no instruction is needed for the conversion
68 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
69 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
70 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
71 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
72 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
73 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
74 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
75 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
76 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
77 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
78 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
79 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
80 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
81 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
82 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
83 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
84 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
85 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
86 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
87 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
88 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
89 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
90 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
91 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
92 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
93 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
94 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
95 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
96 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
97 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
101 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
104 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
105 isPseudo = 1, Predicates = [HasAVX512] in {
106 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
107 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
110 let Predicates = [HasAVX512] in {
111 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
112 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
113 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
116 //===----------------------------------------------------------------------===//
117 // AVX-512 - VECTOR INSERT
120 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
121 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
122 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
123 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512;
126 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
127 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
128 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
129 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
132 // -- 64x4 fp form --
133 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
134 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
135 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
136 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, VEX_W;
139 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
140 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
141 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
142 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
144 // -- 32x4 integer form --
145 let hasSideEffects = 0 in {
146 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
147 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
148 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
149 []>, EVEX_4V, EVEX_V512;
151 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
152 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
153 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
154 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
157 let hasSideEffects = 0 in {
159 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
160 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
161 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
162 []>, EVEX_4V, EVEX_V512, VEX_W;
164 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
165 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
166 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
167 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
170 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
171 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
174 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
177 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
180 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
181 (INSERT_get_vinsert128_imm VR512:$ins))>;
183 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
184 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
185 (INSERT_get_vinsert128_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
187 (bc_v4i32 (loadv2i64 addr:$src2)),
188 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
189 (INSERT_get_vinsert128_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
191 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
192 (INSERT_get_vinsert128_imm VR512:$ins))>;
193 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
194 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert128_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
198 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
201 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
204 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
207 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
208 (INSERT_get_vinsert256_imm VR512:$ins))>;
210 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
211 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
212 (INSERT_get_vinsert256_imm VR512:$ins))>;
213 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
214 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
215 (INSERT_get_vinsert256_imm VR512:$ins))>;
216 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
217 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
218 (INSERT_get_vinsert256_imm VR512:$ins))>;
219 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
220 (bc_v8i32 (loadv4i64 addr:$src2)),
221 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
222 (INSERT_get_vinsert256_imm VR512:$ins))>;
224 // vinsertps - insert f32 to XMM
225 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
226 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
227 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
228 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
230 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
231 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
232 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
233 [(set VR128X:$dst, (X86insertps VR128X:$src1,
234 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
235 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
237 //===----------------------------------------------------------------------===//
238 // AVX-512 VECTOR EXTRACT
240 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
242 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
243 (ins VR512:$src1, i8imm:$src2),
244 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
245 []>, EVEX, EVEX_V512;
246 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
247 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
248 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
249 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
252 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
253 (ins VR512:$src1, i8imm:$src2),
254 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, VEX_W;
257 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
258 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
259 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
260 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
263 let hasSideEffects = 0 in {
265 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
266 (ins VR512:$src1, i8imm:$src2),
267 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
268 []>, EVEX, EVEX_V512;
269 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
270 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
271 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
272 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
275 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
276 (ins VR512:$src1, i8imm:$src2),
277 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
278 []>, EVEX, EVEX_V512, VEX_W;
280 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
281 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
282 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
283 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
286 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
288 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
290 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
291 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
292 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
294 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
296 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
298 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
300 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
303 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
304 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
305 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
307 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
308 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
309 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
311 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
312 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
313 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
315 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
316 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
317 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
319 // A 256-bit subvector extract from the first 512-bit vector position
320 // is a subregister copy that needs no instruction.
321 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
322 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
323 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
324 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
325 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
326 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
327 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
328 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
331 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
332 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
333 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
334 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
335 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
336 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
337 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
338 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
341 // A 128-bit subvector insert to the first 512-bit vector position
342 // is a subregister copy that needs no instruction.
343 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
345 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
347 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
349 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
351 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
352 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
353 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
355 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
356 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
357 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
360 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
361 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
362 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
364 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
365 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
366 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
369 // vextractps - extract 32 bits from XMM
370 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
371 (ins VR128X:$src1, u32u8imm:$src2),
372 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
373 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
376 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
377 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
378 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
379 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
380 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
382 //===---------------------------------------------------------------------===//
385 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
386 RegisterClass DestRC,
387 RegisterClass SrcRC, X86MemOperand x86memop> {
388 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
389 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
391 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
392 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
394 let ExeDomain = SSEPackedSingle in {
395 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
397 EVEX_V512, EVEX_CD8<32, CD8VT1>;
400 let ExeDomain = SSEPackedDouble in {
401 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
403 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
406 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
407 (VBROADCASTSSZrm addr:$src)>;
408 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
409 (VBROADCASTSDZrm addr:$src)>;
411 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
412 (VBROADCASTSSZrm addr:$src)>;
413 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
414 (VBROADCASTSDZrm addr:$src)>;
416 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
417 RegisterClass SrcRC, RegisterClass KRC> {
418 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
419 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
420 []>, EVEX, EVEX_V512;
421 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
422 (ins KRC:$mask, SrcRC:$src),
423 !strconcat(OpcodeStr,
424 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
425 []>, EVEX, EVEX_V512, EVEX_KZ;
428 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
429 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
432 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
433 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
435 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
436 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
438 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
439 (VPBROADCASTDrZrr GR32:$src)>;
440 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
441 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
442 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
443 (VPBROADCASTQrZrr GR64:$src)>;
444 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
445 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
447 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
448 (VPBROADCASTDrZrr GR32:$src)>;
449 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
450 (VPBROADCASTQrZrr GR64:$src)>;
452 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
453 (v16i32 immAllZerosV), (i16 GR16:$mask))),
454 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
455 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
456 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
457 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
459 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
460 X86MemOperand x86memop, PatFrag ld_frag,
461 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
463 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
464 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
466 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
467 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
469 !strconcat(OpcodeStr,
470 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
472 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
475 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
476 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
478 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
479 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
481 !strconcat(OpcodeStr,
482 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
483 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
484 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
488 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
489 loadi32, VR512, v16i32, v4i32, VK16WM>,
490 EVEX_V512, EVEX_CD8<32, CD8VT1>;
491 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
492 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
493 EVEX_CD8<64, CD8VT1>;
495 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
496 X86MemOperand x86memop, PatFrag ld_frag,
499 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
500 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
502 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
504 !strconcat(OpcodeStr,
505 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
510 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
511 i128mem, loadv2i64, VK16WM>,
512 EVEX_V512, EVEX_CD8<32, CD8VT4>;
513 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
514 i256mem, loadv4i64, VK16WM>, VEX_W,
515 EVEX_V512, EVEX_CD8<64, CD8VT4>;
517 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
518 (VPBROADCASTDZrr VR128X:$src)>;
519 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
520 (VPBROADCASTQZrr VR128X:$src)>;
522 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
523 (VBROADCASTSSZrr VR128X:$src)>;
524 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
525 (VBROADCASTSDZrr VR128X:$src)>;
527 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
528 (VBROADCASTSSZrr VR128X:$src)>;
529 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
530 (VBROADCASTSDZrr VR128X:$src)>;
532 // Provide fallback in case the load node that is used in the patterns above
533 // is used by additional users, which prevents the pattern selection.
534 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
535 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
536 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
537 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
540 let Predicates = [HasAVX512] in {
541 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
543 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
544 addr:$src)), sub_ymm)>;
546 //===----------------------------------------------------------------------===//
547 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
550 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
551 RegisterClass DstRC, RegisterClass KRC,
552 ValueType OpVT, ValueType SrcVT> {
553 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
554 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
558 let Predicates = [HasCDI] in {
559 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
560 VK16, v16i32, v16i1>, EVEX_V512;
561 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
562 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
565 //===----------------------------------------------------------------------===//
568 // -- immediate form --
569 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
570 SDNode OpNode, PatFrag mem_frag,
571 X86MemOperand x86memop, ValueType OpVT> {
572 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
573 (ins RC:$src1, i8imm:$src2),
574 !strconcat(OpcodeStr,
575 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
577 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
579 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
580 (ins x86memop:$src1, i8imm:$src2),
581 !strconcat(OpcodeStr,
582 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
584 (OpVT (OpNode (mem_frag addr:$src1),
585 (i8 imm:$src2))))]>, EVEX;
588 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
589 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
590 let ExeDomain = SSEPackedDouble in
591 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
592 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
594 // -- VPERM - register form --
595 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
596 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
598 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2),
600 !strconcat(OpcodeStr,
601 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
603 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
605 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
606 (ins RC:$src1, x86memop:$src2),
607 !strconcat(OpcodeStr,
608 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
610 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
614 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
615 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
616 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
617 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
618 let ExeDomain = SSEPackedSingle in
619 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
620 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
621 let ExeDomain = SSEPackedDouble in
622 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
623 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
625 // -- VPERM2I - 3 source operands form --
626 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
627 PatFrag mem_frag, X86MemOperand x86memop,
628 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
629 let Constraints = "$src1 = $dst" in {
630 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
631 (ins RC:$src1, RC:$src2, RC:$src3),
632 !strconcat(OpcodeStr,
633 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
635 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
638 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
639 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
640 !strconcat(OpcodeStr,
641 " \t{$src3, $src2, $dst {${mask}}|"
642 "$dst {${mask}}, $src2, $src3}"),
643 [(set RC:$dst, (OpVT (vselect KRC:$mask,
644 (OpNode RC:$src1, RC:$src2,
649 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
650 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
651 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
652 !strconcat(OpcodeStr,
653 " \t{$src3, $src2, $dst {${mask}} {z} |",
654 "$dst {${mask}} {z}, $src2, $src3}"),
655 [(set RC:$dst, (OpVT (vselect KRC:$mask,
656 (OpNode RC:$src1, RC:$src2,
659 (v16i32 immAllZerosV))))))]>,
662 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
663 (ins RC:$src1, RC:$src2, x86memop:$src3),
664 !strconcat(OpcodeStr,
665 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
667 (OpVT (OpNode RC:$src1, RC:$src2,
668 (mem_frag addr:$src3))))]>, EVEX_4V;
670 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
671 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
672 !strconcat(OpcodeStr,
673 " \t{$src3, $src2, $dst {${mask}}|"
674 "$dst {${mask}}, $src2, $src3}"),
676 (OpVT (vselect KRC:$mask,
677 (OpNode RC:$src1, RC:$src2,
678 (mem_frag addr:$src3)),
682 let AddedComplexity = 10 in // Prefer over the rrkz variant
683 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
684 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
685 !strconcat(OpcodeStr,
686 " \t{$src3, $src2, $dst {${mask}} {z}|"
687 "$dst {${mask}} {z}, $src2, $src3}"),
689 (OpVT (vselect KRC:$mask,
690 (OpNode RC:$src1, RC:$src2,
691 (mem_frag addr:$src3)),
693 (v16i32 immAllZerosV))))))]>,
697 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
698 i512mem, X86VPermiv3, v16i32, VK16WM>,
699 EVEX_V512, EVEX_CD8<32, CD8VF>;
700 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
701 i512mem, X86VPermiv3, v8i64, VK8WM>,
702 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
703 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
704 i512mem, X86VPermiv3, v16f32, VK16WM>,
705 EVEX_V512, EVEX_CD8<32, CD8VF>;
706 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
707 i512mem, X86VPermiv3, v8f64, VK8WM>,
708 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
710 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
711 PatFrag mem_frag, X86MemOperand x86memop,
712 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
713 ValueType MaskVT, RegisterClass MRC> :
714 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
716 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
717 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
718 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
720 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
721 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
722 (!cast<Instruction>(NAME#rrk) VR512:$src1,
723 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
726 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
727 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
728 EVEX_V512, EVEX_CD8<32, CD8VF>;
729 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
730 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
731 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
732 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
733 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
734 EVEX_V512, EVEX_CD8<32, CD8VF>;
735 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
736 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
737 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
739 //===----------------------------------------------------------------------===//
740 // AVX-512 - BLEND using mask
742 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
743 RegisterClass KRC, RegisterClass RC,
744 X86MemOperand x86memop, PatFrag mem_frag,
745 SDNode OpNode, ValueType vt> {
746 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
747 (ins KRC:$mask, RC:$src1, RC:$src2),
748 !strconcat(OpcodeStr,
749 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
750 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
751 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
753 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
754 (ins KRC:$mask, RC:$src1, x86memop:$src2),
755 !strconcat(OpcodeStr,
756 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
757 []>, EVEX_4V, EVEX_K;
760 let ExeDomain = SSEPackedSingle in
761 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
762 VK16WM, VR512, f512mem,
763 memopv16f32, vselect, v16f32>,
764 EVEX_CD8<32, CD8VF>, EVEX_V512;
765 let ExeDomain = SSEPackedDouble in
766 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
767 VK8WM, VR512, f512mem,
768 memopv8f64, vselect, v8f64>,
769 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
771 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
772 (v16f32 VR512:$src2), (i16 GR16:$mask))),
773 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
774 VR512:$src1, VR512:$src2)>;
776 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
777 (v8f64 VR512:$src2), (i8 GR8:$mask))),
778 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
779 VR512:$src1, VR512:$src2)>;
781 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
782 VK16WM, VR512, f512mem,
783 memopv16i32, vselect, v16i32>,
784 EVEX_CD8<32, CD8VF>, EVEX_V512;
786 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
787 VK8WM, VR512, f512mem,
788 memopv8i64, vselect, v8i64>,
789 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
791 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
792 (v16i32 VR512:$src2), (i16 GR16:$mask))),
793 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
794 VR512:$src1, VR512:$src2)>;
796 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
797 (v8i64 VR512:$src2), (i8 GR8:$mask))),
798 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
799 VR512:$src1, VR512:$src2)>;
801 let Predicates = [HasAVX512] in {
802 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
803 (v8f32 VR256X:$src2))),
805 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
806 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
807 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
809 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
810 (v8i32 VR256X:$src2))),
812 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
813 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
814 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
816 //===----------------------------------------------------------------------===//
817 // Compare Instructions
818 //===----------------------------------------------------------------------===//
820 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
821 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
822 Operand CC, SDNode OpNode, ValueType VT,
823 PatFrag ld_frag, string asm, string asm_alt> {
824 def rr : AVX512Ii8<0xC2, MRMSrcReg,
825 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
826 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
827 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
828 def rm : AVX512Ii8<0xC2, MRMSrcMem,
829 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
830 [(set VK1:$dst, (OpNode (VT RC:$src1),
831 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
832 let isAsmParserOnly = 1, hasSideEffects = 0 in {
833 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
834 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
835 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
836 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
837 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
838 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
842 let Predicates = [HasAVX512] in {
843 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
844 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
845 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
847 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
848 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
849 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
853 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
854 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
855 SDNode OpNode, ValueType vt> {
856 def rr : AVX512BI<opc, MRMSrcReg,
857 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
858 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
859 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
860 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
861 def rm : AVX512BI<opc, MRMSrcMem,
862 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
863 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
864 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
865 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
868 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
869 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
871 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
872 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
873 VEX_W, EVEX_CD8<64, CD8VF>;
875 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
876 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
878 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
879 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
880 VEX_W, EVEX_CD8<64, CD8VF>;
882 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
883 (COPY_TO_REGCLASS (VPCMPGTDZrr
884 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
885 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
887 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
888 (COPY_TO_REGCLASS (VPCMPEQDZrr
889 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
890 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
892 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass WMRC, RegisterClass KRC,
893 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
894 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
895 def rri : AVX512AIi8<opc, MRMSrcReg,
896 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
897 !strconcat("vpcmp${cc}", Suffix,
898 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
899 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
900 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
901 def rmi : AVX512AIi8<opc, MRMSrcMem,
902 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
903 !strconcat("vpcmp${cc}", Suffix,
904 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
905 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
906 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
907 // Accept explicit immediate argument form instead of comparison code.
908 let isAsmParserOnly = 1, hasSideEffects = 0 in {
909 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
910 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
911 !strconcat("vpcmp", Suffix,
912 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
913 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
914 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
915 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, RC:$src2, i8imm:$cc),
916 !strconcat("vpcmp", Suffix,
917 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
918 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
919 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
920 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
921 !strconcat("vpcmp", Suffix,
922 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
923 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
924 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
925 (outs KRC:$dst), (ins WMRC:$mask, RC:$src1, x86memop:$src2, i8imm:$cc),
926 !strconcat("vpcmp", Suffix,
927 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
928 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
932 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16WM, VK16, VR512, i512mem, memopv16i32,
933 X86cmpm, v16i32, AVXCC, "d">,
934 EVEX_V512, EVEX_CD8<32, CD8VF>;
935 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16WM, VK16, VR512, i512mem, memopv16i32,
936 X86cmpmu, v16i32, AVXCC, "ud">,
937 EVEX_V512, EVEX_CD8<32, CD8VF>;
939 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8WM, VK8, VR512, i512mem, memopv8i64,
940 X86cmpm, v8i64, AVXCC, "q">,
941 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
942 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8WM, VK8, VR512, i512mem, memopv8i64,
943 X86cmpmu, v8i64, AVXCC, "uq">,
944 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
946 // avx512_cmp_packed - compare packed instructions
947 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
948 X86MemOperand x86memop, ValueType vt,
949 string suffix, Domain d> {
950 def rri : AVX512PIi8<0xC2, MRMSrcReg,
951 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
952 !strconcat("vcmp${cc}", suffix,
953 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
954 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
955 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
956 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
957 !strconcat("vcmp${cc}", suffix,
958 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
960 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
961 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
962 !strconcat("vcmp${cc}", suffix,
963 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
965 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
967 // Accept explicit immediate argument form instead of comparison code.
968 let isAsmParserOnly = 1, hasSideEffects = 0 in {
969 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
970 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
971 !strconcat("vcmp", suffix,
972 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
973 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
974 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
975 !strconcat("vcmp", suffix,
976 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
980 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
981 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
983 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
984 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
987 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
988 (COPY_TO_REGCLASS (VCMPPSZrri
989 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
990 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
992 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
993 (COPY_TO_REGCLASS (VPCMPDZrri
994 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
995 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
997 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
998 (COPY_TO_REGCLASS (VPCMPUDZrri
999 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1000 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1003 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1004 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1006 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1007 (I8Imm imm:$cc)), GR16)>;
1009 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1010 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1012 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1013 (I8Imm imm:$cc)), GR8)>;
1015 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1016 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1018 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1019 (I8Imm imm:$cc)), GR16)>;
1021 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1022 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1024 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1025 (I8Imm imm:$cc)), GR8)>;
1027 // Mask register copy, including
1028 // - copy between mask registers
1029 // - load/store mask registers
1030 // - copy from GPR to mask register and vice versa
1032 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1033 string OpcodeStr, RegisterClass KRC,
1034 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1035 let hasSideEffects = 0 in {
1036 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1037 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1039 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1040 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1041 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1043 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1044 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1048 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1050 RegisterClass KRC, RegisterClass GRC> {
1051 let hasSideEffects = 0 in {
1052 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1053 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1054 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1055 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1059 let Predicates = [HasDQI] in
1060 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1062 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1065 let Predicates = [HasAVX512] in
1066 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1068 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1071 let Predicates = [HasBWI] in {
1072 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1073 i32mem>, VEX, PD, VEX_W;
1074 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1078 let Predicates = [HasBWI] in {
1079 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1080 i64mem>, VEX, PS, VEX_W;
1081 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1085 // GR from/to mask register
1086 let Predicates = [HasDQI] in {
1087 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1088 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1089 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1090 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1092 let Predicates = [HasAVX512] in {
1093 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1094 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1095 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1096 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1098 let Predicates = [HasBWI] in {
1099 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1100 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1102 let Predicates = [HasBWI] in {
1103 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1104 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1108 let Predicates = [HasDQI] in {
1109 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1110 (KMOVBmk addr:$dst, VK8:$src)>;
1112 let Predicates = [HasAVX512] in {
1113 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1114 (KMOVWmk addr:$dst, VK16:$src)>;
1115 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1116 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1117 def : Pat<(i1 (load addr:$src)),
1118 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1119 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1120 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1122 let Predicates = [HasBWI] in {
1123 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1124 (KMOVDmk addr:$dst, VK32:$src)>;
1126 let Predicates = [HasBWI] in {
1127 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1128 (KMOVQmk addr:$dst, VK64:$src)>;
1131 let Predicates = [HasAVX512] in {
1132 def : Pat<(i1 (trunc (i32 GR32:$src))),
1133 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1135 def : Pat<(i1 (trunc (i8 GR8:$src))),
1137 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1139 def : Pat<(i1 (trunc (i16 GR16:$src))),
1141 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1144 def : Pat<(i32 (zext VK1:$src)),
1145 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1146 def : Pat<(i8 (zext VK1:$src)),
1149 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1150 def : Pat<(i64 (zext VK1:$src)),
1151 (AND64ri8 (SUBREG_TO_REG (i64 0),
1152 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1153 def : Pat<(i16 (zext VK1:$src)),
1155 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1157 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1158 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1159 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1160 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1162 let Predicates = [HasBWI] in {
1163 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1164 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1165 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1166 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1170 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1171 let Predicates = [HasAVX512] in {
1172 // GR from/to 8-bit mask without native support
1173 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1175 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1177 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1179 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1182 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1183 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1184 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1185 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1187 let Predicates = [HasBWI] in {
1188 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1189 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1190 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1191 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1194 // Mask unary operation
1196 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1197 RegisterClass KRC, SDPatternOperator OpNode,
1199 let Predicates = [prd] in
1200 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1201 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1202 [(set KRC:$dst, (OpNode KRC:$src))]>;
1205 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1206 SDPatternOperator OpNode> {
1207 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1209 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1210 HasAVX512>, VEX, PS;
1211 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1212 HasBWI>, VEX, PD, VEX_W;
1213 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1214 HasBWI>, VEX, PS, VEX_W;
1217 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1219 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1220 let Predicates = [HasAVX512] in
1221 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1223 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1224 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1226 defm : avx512_mask_unop_int<"knot", "KNOT">;
1228 let Predicates = [HasDQI] in
1229 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1230 let Predicates = [HasAVX512] in
1231 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1232 let Predicates = [HasBWI] in
1233 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1234 let Predicates = [HasBWI] in
1235 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1237 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1238 let Predicates = [HasAVX512] in {
1239 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1240 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1242 def : Pat<(not VK8:$src),
1244 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1247 // Mask binary operation
1248 // - KAND, KANDN, KOR, KXNOR, KXOR
1249 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1250 RegisterClass KRC, SDPatternOperator OpNode,
1252 let Predicates = [prd] in
1253 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1254 !strconcat(OpcodeStr,
1255 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1256 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1259 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1260 SDPatternOperator OpNode> {
1261 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1262 HasDQI>, VEX_4V, VEX_L, PD;
1263 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1264 HasAVX512>, VEX_4V, VEX_L, PS;
1265 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1266 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1267 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1268 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1271 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1272 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1274 let isCommutable = 1 in {
1275 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1276 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1277 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1278 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1280 let isCommutable = 0 in
1281 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1283 def : Pat<(xor VK1:$src1, VK1:$src2),
1284 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1285 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1287 def : Pat<(or VK1:$src1, VK1:$src2),
1288 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1289 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1291 def : Pat<(and VK1:$src1, VK1:$src2),
1292 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1293 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1295 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1296 let Predicates = [HasAVX512] in
1297 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1298 (i16 GR16:$src1), (i16 GR16:$src2)),
1299 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1300 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1301 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1304 defm : avx512_mask_binop_int<"kand", "KAND">;
1305 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1306 defm : avx512_mask_binop_int<"kor", "KOR">;
1307 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1308 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1310 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1311 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1312 let Predicates = [HasAVX512] in
1313 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1315 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1316 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1319 defm : avx512_binop_pat<and, KANDWrr>;
1320 defm : avx512_binop_pat<andn, KANDNWrr>;
1321 defm : avx512_binop_pat<or, KORWrr>;
1322 defm : avx512_binop_pat<xnor, KXNORWrr>;
1323 defm : avx512_binop_pat<xor, KXORWrr>;
1326 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1327 RegisterClass KRC> {
1328 let Predicates = [HasAVX512] in
1329 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1330 !strconcat(OpcodeStr,
1331 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1334 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1335 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1339 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1340 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1341 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1342 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1345 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1346 let Predicates = [HasAVX512] in
1347 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1348 (i16 GR16:$src1), (i16 GR16:$src2)),
1349 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1350 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1351 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1353 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1356 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1358 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1359 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1360 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1361 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1364 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1365 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1369 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1371 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1372 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1373 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1376 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1378 let Predicates = [HasAVX512] in
1379 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1380 !strconcat(OpcodeStr,
1381 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1382 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1385 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1387 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1391 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1392 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1394 // Mask setting all 0s or 1s
1395 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1396 let Predicates = [HasAVX512] in
1397 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1398 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1399 [(set KRC:$dst, (VT Val))]>;
1402 multiclass avx512_mask_setop_w<PatFrag Val> {
1403 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1404 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1407 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1408 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1410 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1411 let Predicates = [HasAVX512] in {
1412 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1413 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1414 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1415 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1416 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1418 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1419 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1421 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1422 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1424 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1425 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1427 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1428 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1430 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1431 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1432 //===----------------------------------------------------------------------===//
1433 // AVX-512 - Aligned and unaligned load and store
1436 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1437 RegisterClass KRC, RegisterClass RC,
1438 ValueType vt, ValueType zvt, X86MemOperand memop,
1439 Domain d, bit IsReMaterializable = 1> {
1440 let hasSideEffects = 0 in {
1441 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1442 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1444 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1445 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1446 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1448 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1449 SchedRW = [WriteLoad] in
1450 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1451 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1452 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1455 let AddedComplexity = 20 in {
1456 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1457 let hasSideEffects = 0 in
1458 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1459 (ins RC:$src0, KRC:$mask, RC:$src1),
1460 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1461 "${dst} {${mask}}, $src1}"),
1462 [(set RC:$dst, (vt (vselect KRC:$mask,
1466 let mayLoad = 1, SchedRW = [WriteLoad] in
1467 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1468 (ins RC:$src0, KRC:$mask, memop:$src1),
1469 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1470 "${dst} {${mask}}, $src1}"),
1473 (vt (bitconvert (ld_frag addr:$src1))),
1477 let mayLoad = 1, SchedRW = [WriteLoad] in
1478 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1479 (ins KRC:$mask, memop:$src),
1480 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1481 "${dst} {${mask}} {z}, $src}"),
1484 (vt (bitconvert (ld_frag addr:$src))),
1485 (vt (bitconvert (zvt immAllZerosV))))))],
1490 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1491 string elty, string elsz, string vsz512,
1492 string vsz256, string vsz128, Domain d,
1493 Predicate prd, bit IsReMaterializable = 1> {
1494 let Predicates = [prd] in
1495 defm Z : avx512_load<opc, OpcodeStr,
1496 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1497 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1498 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1499 !cast<X86MemOperand>(elty##"512mem"), d,
1500 IsReMaterializable>, EVEX_V512;
1502 let Predicates = [prd, HasVLX] in {
1503 defm Z256 : avx512_load<opc, OpcodeStr,
1504 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1505 "v"##vsz256##elty##elsz, "v4i64")),
1506 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1507 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1508 !cast<X86MemOperand>(elty##"256mem"), d,
1509 IsReMaterializable>, EVEX_V256;
1511 defm Z128 : avx512_load<opc, OpcodeStr,
1512 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1513 "v"##vsz128##elty##elsz, "v2i64")),
1514 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1515 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1516 !cast<X86MemOperand>(elty##"128mem"), d,
1517 IsReMaterializable>, EVEX_V128;
1522 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1523 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1524 X86MemOperand memop, Domain d> {
1525 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1526 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1527 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
1529 let Constraints = "$src1 = $dst" in
1530 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1531 (ins RC:$src1, KRC:$mask, RC:$src2),
1532 !strconcat(OpcodeStr,
1533 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1535 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1536 (ins KRC:$mask, RC:$src),
1537 !strconcat(OpcodeStr,
1538 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1539 [], d>, EVEX, EVEX_KZ;
1541 let mayStore = 1 in {
1542 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1543 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1544 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
1545 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1546 (ins memop:$dst, KRC:$mask, RC:$src),
1547 !strconcat(OpcodeStr,
1548 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1549 [], d>, EVEX, EVEX_K;
1554 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1555 string st_suff_512, string st_suff_256,
1556 string st_suff_128, string elty, string elsz,
1557 string vsz512, string vsz256, string vsz128,
1558 Domain d, Predicate prd> {
1559 let Predicates = [prd] in
1560 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1561 !cast<ValueType>("v"##vsz512##elty##elsz),
1562 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1563 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1565 let Predicates = [prd, HasVLX] in {
1566 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1567 !cast<ValueType>("v"##vsz256##elty##elsz),
1568 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1569 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1571 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1572 !cast<ValueType>("v"##vsz128##elty##elsz),
1573 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1574 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1578 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1579 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1580 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1581 "512", "256", "", "f", "32", "16", "8", "4",
1582 SSEPackedSingle, HasAVX512>,
1583 PS, EVEX_CD8<32, CD8VF>;
1585 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1586 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1587 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1588 "512", "256", "", "f", "64", "8", "4", "2",
1589 SSEPackedDouble, HasAVX512>,
1590 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1592 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1593 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1594 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1595 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1596 PS, EVEX_CD8<32, CD8VF>;
1598 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1599 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1600 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1601 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1602 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1604 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1605 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1606 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1608 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1609 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1610 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1612 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1614 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1616 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1618 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1621 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1622 "16", "8", "4", SSEPackedInt, HasAVX512>,
1623 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1624 "512", "256", "", "i", "32", "16", "8", "4",
1625 SSEPackedInt, HasAVX512>,
1626 PD, EVEX_CD8<32, CD8VF>;
1628 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1629 "8", "4", "2", SSEPackedInt, HasAVX512>,
1630 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1631 "512", "256", "", "i", "64", "8", "4", "2",
1632 SSEPackedInt, HasAVX512>,
1633 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1635 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1636 "64", "32", "16", SSEPackedInt, HasBWI>,
1637 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1638 "i", "8", "64", "32", "16", SSEPackedInt,
1639 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1641 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1642 "32", "16", "8", SSEPackedInt, HasBWI>,
1643 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1644 "i", "16", "32", "16", "8", SSEPackedInt,
1645 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1647 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1648 "16", "8", "4", SSEPackedInt, HasAVX512>,
1649 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1650 "i", "32", "16", "8", "4", SSEPackedInt,
1651 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1653 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1654 "8", "4", "2", SSEPackedInt, HasAVX512>,
1655 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
1656 "i", "64", "8", "4", "2", SSEPackedInt,
1657 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
1659 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1660 (v16i32 immAllZerosV), GR16:$mask)),
1661 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1663 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1664 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1665 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1667 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1669 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1671 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1673 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1676 let AddedComplexity = 20 in {
1677 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1678 (bc_v8i64 (v16i32 immAllZerosV)))),
1679 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
1681 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1682 (v8i64 VR512:$src))),
1683 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1686 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1687 (v16i32 immAllZerosV))),
1688 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
1690 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1691 (v16i32 VR512:$src))),
1692 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1695 // Move Int Doubleword to Packed Double Int
1697 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1698 "vmovd\t{$src, $dst|$dst, $src}",
1700 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1702 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1703 "vmovd\t{$src, $dst|$dst, $src}",
1705 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1706 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1707 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1708 "vmovq\t{$src, $dst|$dst, $src}",
1710 (v2i64 (scalar_to_vector GR64:$src)))],
1711 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1712 let isCodeGenOnly = 1 in {
1713 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1714 "vmovq\t{$src, $dst|$dst, $src}",
1715 [(set FR64:$dst, (bitconvert GR64:$src))],
1716 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1717 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1718 "vmovq\t{$src, $dst|$dst, $src}",
1719 [(set GR64:$dst, (bitconvert FR64:$src))],
1720 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1722 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1723 "vmovq\t{$src, $dst|$dst, $src}",
1724 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1725 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1726 EVEX_CD8<64, CD8VT1>;
1728 // Move Int Doubleword to Single Scalar
1730 let isCodeGenOnly = 1 in {
1731 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1732 "vmovd\t{$src, $dst|$dst, $src}",
1733 [(set FR32X:$dst, (bitconvert GR32:$src))],
1734 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1736 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1737 "vmovd\t{$src, $dst|$dst, $src}",
1738 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1739 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1742 // Move doubleword from xmm register to r/m32
1744 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1745 "vmovd\t{$src, $dst|$dst, $src}",
1746 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1747 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1749 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1750 (ins i32mem:$dst, VR128X:$src),
1751 "vmovd\t{$src, $dst|$dst, $src}",
1752 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1753 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1754 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1756 // Move quadword from xmm1 register to r/m64
1758 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1759 "vmovq\t{$src, $dst|$dst, $src}",
1760 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1762 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1763 Requires<[HasAVX512, In64BitMode]>;
1765 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1766 (ins i64mem:$dst, VR128X:$src),
1767 "vmovq\t{$src, $dst|$dst, $src}",
1768 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1769 addr:$dst)], IIC_SSE_MOVDQ>,
1770 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1771 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1773 // Move Scalar Single to Double Int
1775 let isCodeGenOnly = 1 in {
1776 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1778 "vmovd\t{$src, $dst|$dst, $src}",
1779 [(set GR32:$dst, (bitconvert FR32X:$src))],
1780 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1781 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1782 (ins i32mem:$dst, FR32X:$src),
1783 "vmovd\t{$src, $dst|$dst, $src}",
1784 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1785 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1788 // Move Quadword Int to Packed Quadword Int
1790 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1792 "vmovq\t{$src, $dst|$dst, $src}",
1794 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1795 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1797 //===----------------------------------------------------------------------===//
1798 // AVX-512 MOVSS, MOVSD
1799 //===----------------------------------------------------------------------===//
1801 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1802 SDNode OpNode, ValueType vt,
1803 X86MemOperand x86memop, PatFrag mem_pat> {
1804 let hasSideEffects = 0 in {
1805 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1806 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1807 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1808 (scalar_to_vector RC:$src2))))],
1809 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1810 let Constraints = "$src1 = $dst" in
1811 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1812 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1814 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1815 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1816 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1817 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1818 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1820 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1821 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1822 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1824 } //hasSideEffects = 0
1827 let ExeDomain = SSEPackedSingle in
1828 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1829 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1831 let ExeDomain = SSEPackedDouble in
1832 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1833 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1835 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1836 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1837 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1839 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1840 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1841 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1843 // For the disassembler
1844 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1845 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1846 (ins VR128X:$src1, FR32X:$src2),
1847 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1849 XS, EVEX_4V, VEX_LIG;
1850 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1851 (ins VR128X:$src1, FR64X:$src2),
1852 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1854 XD, EVEX_4V, VEX_LIG, VEX_W;
1857 let Predicates = [HasAVX512] in {
1858 let AddedComplexity = 15 in {
1859 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1860 // MOVS{S,D} to the lower bits.
1861 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1862 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1863 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1864 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1865 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1866 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1867 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1868 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1870 // Move low f32 and clear high bits.
1871 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1872 (SUBREG_TO_REG (i32 0),
1873 (VMOVSSZrr (v4f32 (V_SET0)),
1874 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1875 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1876 (SUBREG_TO_REG (i32 0),
1877 (VMOVSSZrr (v4i32 (V_SET0)),
1878 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1881 let AddedComplexity = 20 in {
1882 // MOVSSrm zeros the high parts of the register; represent this
1883 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1884 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1885 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1886 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1887 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1888 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1889 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1891 // MOVSDrm zeros the high parts of the register; represent this
1892 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1893 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1894 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1895 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1896 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1897 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1898 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1899 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1900 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1901 def : Pat<(v2f64 (X86vzload addr:$src)),
1902 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1904 // Represent the same patterns above but in the form they appear for
1906 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1907 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1908 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1909 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1910 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1911 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1912 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1913 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1914 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1916 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1917 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1918 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1919 FR32X:$src)), sub_xmm)>;
1920 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1921 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1922 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1923 FR64X:$src)), sub_xmm)>;
1924 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1925 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1926 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1928 // Move low f64 and clear high bits.
1929 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1930 (SUBREG_TO_REG (i32 0),
1931 (VMOVSDZrr (v2f64 (V_SET0)),
1932 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1934 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1935 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1936 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1938 // Extract and store.
1939 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1941 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1942 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1944 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1946 // Shuffle with VMOVSS
1947 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1948 (VMOVSSZrr (v4i32 VR128X:$src1),
1949 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1950 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1951 (VMOVSSZrr (v4f32 VR128X:$src1),
1952 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1955 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1956 (SUBREG_TO_REG (i32 0),
1957 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1958 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1960 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1961 (SUBREG_TO_REG (i32 0),
1962 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1963 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1966 // Shuffle with VMOVSD
1967 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1968 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1969 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1970 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1971 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1972 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1973 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1974 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1977 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1978 (SUBREG_TO_REG (i32 0),
1979 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1980 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1982 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1983 (SUBREG_TO_REG (i32 0),
1984 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1985 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1988 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1989 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1990 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1991 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1992 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1993 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1994 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1995 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1998 let AddedComplexity = 15 in
1999 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2001 "vmovq\t{$src, $dst|$dst, $src}",
2002 [(set VR128X:$dst, (v2i64 (X86vzmovl
2003 (v2i64 VR128X:$src))))],
2004 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2006 let AddedComplexity = 20 in
2007 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2009 "vmovq\t{$src, $dst|$dst, $src}",
2010 [(set VR128X:$dst, (v2i64 (X86vzmovl
2011 (loadv2i64 addr:$src))))],
2012 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2013 EVEX_CD8<8, CD8VT8>;
2015 let Predicates = [HasAVX512] in {
2016 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2017 let AddedComplexity = 20 in {
2018 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2019 (VMOVDI2PDIZrm addr:$src)>;
2020 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2021 (VMOV64toPQIZrr GR64:$src)>;
2022 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2023 (VMOVDI2PDIZrr GR32:$src)>;
2025 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2026 (VMOVDI2PDIZrm addr:$src)>;
2027 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2028 (VMOVDI2PDIZrm addr:$src)>;
2029 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2030 (VMOVZPQILo2PQIZrm addr:$src)>;
2031 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2032 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2033 def : Pat<(v2i64 (X86vzload addr:$src)),
2034 (VMOVZPQILo2PQIZrm addr:$src)>;
2037 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2038 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2039 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2040 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2041 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2042 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2043 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2046 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2047 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2049 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2050 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2052 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2053 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2055 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2056 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2058 //===----------------------------------------------------------------------===//
2059 // AVX-512 - Non-temporals
2060 //===----------------------------------------------------------------------===//
2062 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
2064 "vmovntdqa\t{$src, $dst|$dst, $src}",
2066 (int_x86_avx512_movntdqa addr:$src))]>,
2067 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2069 // Prefer non-temporal over temporal versions
2070 let AddedComplexity = 400, SchedRW = [WriteStore] in {
2072 def VMOVNTPSZmr : AVX512PSI<0x2B, MRMDestMem, (outs),
2073 (ins f512mem:$dst, VR512:$src),
2074 "vmovntps\t{$src, $dst|$dst, $src}",
2075 [(alignednontemporalstore (v16f32 VR512:$src),
2078 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2080 def VMOVNTPDZmr : AVX512PDI<0x2B, MRMDestMem, (outs),
2081 (ins f512mem:$dst, VR512:$src),
2082 "vmovntpd\t{$src, $dst|$dst, $src}",
2083 [(alignednontemporalstore (v8f64 VR512:$src),
2086 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2089 def VMOVNTDQZmr : AVX512BI<0xE7, MRMDestMem, (outs),
2090 (ins i512mem:$dst, VR512:$src),
2091 "vmovntdq\t{$src, $dst|$dst, $src}",
2092 [(alignednontemporalstore (v8i64 VR512:$src),
2095 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2098 //===----------------------------------------------------------------------===//
2099 // AVX-512 - Integer arithmetic
2101 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2102 ValueType OpVT, RegisterClass KRC,
2103 RegisterClass RC, PatFrag memop_frag,
2104 X86MemOperand x86memop, PatFrag scalar_mfrag,
2105 X86MemOperand x86scalar_mop, string BrdcstStr,
2106 OpndItins itins, bit IsCommutable = 0> {
2107 let isCommutable = IsCommutable in
2108 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2109 (ins RC:$src1, RC:$src2),
2110 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2111 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2113 let AddedComplexity = 30 in {
2114 let Constraints = "$src0 = $dst" in
2115 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2116 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
2117 !strconcat(OpcodeStr,
2118 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2119 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2120 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2122 itins.rr>, EVEX_4V, EVEX_K;
2123 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2124 (ins KRC:$mask, RC:$src1, RC:$src2),
2125 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2126 "|$dst {${mask}} {z}, $src1, $src2}"),
2127 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2128 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2129 (OpVT immAllZerosV))))],
2130 itins.rr>, EVEX_4V, EVEX_KZ;
2133 let mayLoad = 1 in {
2134 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2135 (ins RC:$src1, x86memop:$src2),
2136 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2137 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
2139 let AddedComplexity = 30 in {
2140 let Constraints = "$src0 = $dst" in
2141 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2142 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
2143 !strconcat(OpcodeStr,
2144 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2145 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2146 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2148 itins.rm>, EVEX_4V, EVEX_K;
2149 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2150 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2151 !strconcat(OpcodeStr,
2152 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2153 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2154 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2155 (OpVT immAllZerosV))))],
2156 itins.rm>, EVEX_4V, EVEX_KZ;
2158 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2159 (ins RC:$src1, x86scalar_mop:$src2),
2160 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2161 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2162 [(set RC:$dst, (OpNode RC:$src1,
2163 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2164 itins.rm>, EVEX_4V, EVEX_B;
2165 let AddedComplexity = 30 in {
2166 let Constraints = "$src0 = $dst" in
2167 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2168 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2169 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2170 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2172 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2173 (OpNode (OpVT RC:$src1),
2174 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2176 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2177 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2178 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2179 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2180 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2182 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2183 (OpNode (OpVT RC:$src1),
2184 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2185 (OpVT immAllZerosV))))],
2186 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2191 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2192 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2193 PatFrag memop_frag, X86MemOperand x86memop,
2194 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2195 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2196 let isCommutable = IsCommutable in
2198 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2199 (ins RC:$src1, RC:$src2),
2200 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2202 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2203 (ins KRC:$mask, RC:$src1, RC:$src2),
2204 !strconcat(OpcodeStr,
2205 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2206 [], itins.rr>, EVEX_4V, EVEX_K;
2207 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2208 (ins KRC:$mask, RC:$src1, RC:$src2),
2209 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2210 "|$dst {${mask}} {z}, $src1, $src2}"),
2211 [], itins.rr>, EVEX_4V, EVEX_KZ;
2213 let mayLoad = 1 in {
2214 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2215 (ins RC:$src1, x86memop:$src2),
2216 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2218 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2219 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2220 !strconcat(OpcodeStr,
2221 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2222 [], itins.rm>, EVEX_4V, EVEX_K;
2223 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2224 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2225 !strconcat(OpcodeStr,
2226 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2227 [], itins.rm>, EVEX_4V, EVEX_KZ;
2228 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2229 (ins RC:$src1, x86scalar_mop:$src2),
2230 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2231 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2232 [], itins.rm>, EVEX_4V, EVEX_B;
2233 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2234 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2235 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2236 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2238 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2239 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2240 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2241 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2242 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2244 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2248 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2249 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2250 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2252 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2253 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2254 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2256 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2257 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2258 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2260 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2261 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2262 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2264 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2265 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2266 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2268 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2269 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2270 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2271 EVEX_CD8<64, CD8VF>, VEX_W;
2273 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2274 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2275 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2277 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2278 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2280 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2281 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2282 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2283 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2284 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2285 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2287 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2288 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2289 SSE_INTALU_ITINS_P, 1>,
2290 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2291 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2292 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2293 SSE_INTALU_ITINS_P, 0>,
2294 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2296 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2297 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2298 SSE_INTALU_ITINS_P, 1>,
2299 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2300 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2301 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2302 SSE_INTALU_ITINS_P, 0>,
2303 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2305 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2306 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2307 SSE_INTALU_ITINS_P, 1>,
2308 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2309 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2310 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2311 SSE_INTALU_ITINS_P, 0>,
2312 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2314 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2315 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2316 SSE_INTALU_ITINS_P, 1>,
2317 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2318 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2319 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2320 SSE_INTALU_ITINS_P, 0>,
2321 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2323 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2324 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2325 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2326 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2327 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2328 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2329 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2330 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2331 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2332 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2333 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2334 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2335 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2336 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2337 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2338 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2339 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2340 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2341 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2342 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2343 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2344 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2345 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2346 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2347 //===----------------------------------------------------------------------===//
2348 // AVX-512 - Unpack Instructions
2349 //===----------------------------------------------------------------------===//
2351 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2352 PatFrag mem_frag, RegisterClass RC,
2353 X86MemOperand x86memop, string asm,
2355 def rr : AVX512PI<opc, MRMSrcReg,
2356 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2358 (vt (OpNode RC:$src1, RC:$src2)))],
2360 def rm : AVX512PI<opc, MRMSrcMem,
2361 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2363 (vt (OpNode RC:$src1,
2364 (bitconvert (mem_frag addr:$src2)))))],
2368 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2369 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2370 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2371 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2372 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2373 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2374 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2375 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2376 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2377 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2378 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2379 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2381 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2382 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2383 X86MemOperand x86memop> {
2384 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2385 (ins RC:$src1, RC:$src2),
2386 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2387 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2388 IIC_SSE_UNPCK>, EVEX_4V;
2389 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2390 (ins RC:$src1, x86memop:$src2),
2391 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2392 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2393 (bitconvert (memop_frag addr:$src2)))))],
2394 IIC_SSE_UNPCK>, EVEX_4V;
2396 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2397 VR512, memopv16i32, i512mem>, EVEX_V512,
2398 EVEX_CD8<32, CD8VF>;
2399 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2400 VR512, memopv8i64, i512mem>, EVEX_V512,
2401 VEX_W, EVEX_CD8<64, CD8VF>;
2402 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2403 VR512, memopv16i32, i512mem>, EVEX_V512,
2404 EVEX_CD8<32, CD8VF>;
2405 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2406 VR512, memopv8i64, i512mem>, EVEX_V512,
2407 VEX_W, EVEX_CD8<64, CD8VF>;
2408 //===----------------------------------------------------------------------===//
2412 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2413 SDNode OpNode, PatFrag mem_frag,
2414 X86MemOperand x86memop, ValueType OpVT> {
2415 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2416 (ins RC:$src1, i8imm:$src2),
2417 !strconcat(OpcodeStr,
2418 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2420 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2422 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2423 (ins x86memop:$src1, i8imm:$src2),
2424 !strconcat(OpcodeStr,
2425 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2427 (OpVT (OpNode (mem_frag addr:$src1),
2428 (i8 imm:$src2))))]>, EVEX;
2431 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2432 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2434 let ExeDomain = SSEPackedSingle in
2435 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2436 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2437 EVEX_CD8<32, CD8VF>;
2438 let ExeDomain = SSEPackedDouble in
2439 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2440 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2441 VEX_W, EVEX_CD8<32, CD8VF>;
2443 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2444 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2445 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2446 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2448 //===----------------------------------------------------------------------===//
2449 // AVX-512 Logical Instructions
2450 //===----------------------------------------------------------------------===//
2452 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2453 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2454 EVEX_V512, EVEX_CD8<32, CD8VF>;
2455 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2456 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2457 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2458 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2459 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2460 EVEX_V512, EVEX_CD8<32, CD8VF>;
2461 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2462 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2463 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2464 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2465 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2466 EVEX_V512, EVEX_CD8<32, CD8VF>;
2467 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2468 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2469 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2470 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2471 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2472 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2473 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2474 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2475 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2477 //===----------------------------------------------------------------------===//
2478 // AVX-512 FP arithmetic
2479 //===----------------------------------------------------------------------===//
2481 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2483 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2484 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2485 EVEX_CD8<32, CD8VT1>;
2486 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2487 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2488 EVEX_CD8<64, CD8VT1>;
2491 let isCommutable = 1 in {
2492 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2493 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2494 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2495 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2497 let isCommutable = 0 in {
2498 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2499 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2502 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2504 RegisterClass RC, ValueType vt,
2505 X86MemOperand x86memop, PatFrag mem_frag,
2506 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2508 Domain d, OpndItins itins, bit commutable> {
2509 let isCommutable = commutable in {
2510 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2511 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2512 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2515 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2516 !strconcat(OpcodeStr,
2517 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2518 [], itins.rr, d>, EVEX_4V, EVEX_K;
2520 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2521 !strconcat(OpcodeStr,
2522 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2523 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2526 let mayLoad = 1 in {
2527 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2528 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2529 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2530 itins.rm, d>, EVEX_4V;
2532 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2533 (ins RC:$src1, x86scalar_mop:$src2),
2534 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2535 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2536 [(set RC:$dst, (OpNode RC:$src1,
2537 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2538 itins.rm, d>, EVEX_4V, EVEX_B;
2540 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2541 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2542 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2543 [], itins.rm, d>, EVEX_4V, EVEX_K;
2545 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2546 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2547 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2548 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2550 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2551 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2552 " \t{${src2}", BrdcstStr,
2553 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2554 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2556 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2557 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2558 " \t{${src2}", BrdcstStr,
2559 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2561 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2565 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2566 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2567 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2569 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2570 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2571 SSE_ALU_ITINS_P.d, 1>,
2572 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2574 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2575 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2576 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2577 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2578 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2579 SSE_ALU_ITINS_P.d, 1>,
2580 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2582 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2583 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2584 SSE_ALU_ITINS_P.s, 1>,
2585 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2586 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2587 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2588 SSE_ALU_ITINS_P.s, 1>,
2589 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2591 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2592 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2593 SSE_ALU_ITINS_P.d, 1>,
2594 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2595 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2596 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2597 SSE_ALU_ITINS_P.d, 1>,
2598 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2600 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2601 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2602 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2603 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2604 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2605 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2607 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2608 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2609 SSE_ALU_ITINS_P.d, 0>,
2610 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2611 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2612 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2613 SSE_ALU_ITINS_P.d, 0>,
2614 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2616 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2617 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2618 (i16 -1), FROUND_CURRENT)),
2619 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2621 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2622 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2623 (i8 -1), FROUND_CURRENT)),
2624 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2626 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2627 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2628 (i16 -1), FROUND_CURRENT)),
2629 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2631 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2632 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2633 (i8 -1), FROUND_CURRENT)),
2634 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2635 //===----------------------------------------------------------------------===//
2636 // AVX-512 VPTESTM instructions
2637 //===----------------------------------------------------------------------===//
2639 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2640 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2641 SDNode OpNode, ValueType vt> {
2642 def rr : AVX512PI<opc, MRMSrcReg,
2643 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2644 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2645 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2646 SSEPackedInt>, EVEX_4V;
2647 def rm : AVX512PI<opc, MRMSrcMem,
2648 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2649 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2650 [(set KRC:$dst, (OpNode (vt RC:$src1),
2651 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2654 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2655 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2656 EVEX_CD8<32, CD8VF>;
2657 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2658 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2659 EVEX_CD8<64, CD8VF>;
2661 let Predicates = [HasCDI] in {
2662 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2663 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2664 EVEX_CD8<32, CD8VF>;
2665 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2666 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2667 EVEX_CD8<64, CD8VF>;
2670 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2671 (v16i32 VR512:$src2), (i16 -1))),
2672 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2674 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2675 (v8i64 VR512:$src2), (i8 -1))),
2676 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2677 //===----------------------------------------------------------------------===//
2678 // AVX-512 Shift instructions
2679 //===----------------------------------------------------------------------===//
2680 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2681 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2682 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2683 RegisterClass KRC> {
2684 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2685 (ins RC:$src1, i8imm:$src2),
2686 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2687 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2688 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2689 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2690 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2691 !strconcat(OpcodeStr,
2692 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2693 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2694 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2695 (ins x86memop:$src1, i8imm:$src2),
2696 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2697 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2698 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2699 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2700 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2701 !strconcat(OpcodeStr,
2702 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2703 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2706 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2707 RegisterClass RC, ValueType vt, ValueType SrcVT,
2708 PatFrag bc_frag, RegisterClass KRC> {
2709 // src2 is always 128-bit
2710 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2711 (ins RC:$src1, VR128X:$src2),
2712 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2713 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2714 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2715 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2716 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2717 !strconcat(OpcodeStr,
2718 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2719 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2720 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2721 (ins RC:$src1, i128mem:$src2),
2722 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2723 [(set RC:$dst, (vt (OpNode RC:$src1,
2724 (bc_frag (memopv2i64 addr:$src2)))))],
2725 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2726 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2727 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2728 !strconcat(OpcodeStr,
2729 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2730 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2733 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2734 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2735 EVEX_V512, EVEX_CD8<32, CD8VF>;
2736 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2737 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2738 EVEX_CD8<32, CD8VQ>;
2740 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2741 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2742 EVEX_CD8<64, CD8VF>, VEX_W;
2743 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2744 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2745 EVEX_CD8<64, CD8VQ>, VEX_W;
2747 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2748 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2749 EVEX_CD8<32, CD8VF>;
2750 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2751 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2752 EVEX_CD8<32, CD8VQ>;
2754 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2755 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2756 EVEX_CD8<64, CD8VF>, VEX_W;
2757 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2758 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2759 EVEX_CD8<64, CD8VQ>, VEX_W;
2761 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2762 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2763 EVEX_V512, EVEX_CD8<32, CD8VF>;
2764 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2765 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2766 EVEX_CD8<32, CD8VQ>;
2768 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2769 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2770 EVEX_CD8<64, CD8VF>, VEX_W;
2771 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2772 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2773 EVEX_CD8<64, CD8VQ>, VEX_W;
2775 //===-------------------------------------------------------------------===//
2776 // Variable Bit Shifts
2777 //===-------------------------------------------------------------------===//
2778 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2779 RegisterClass RC, ValueType vt,
2780 X86MemOperand x86memop, PatFrag mem_frag> {
2781 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2782 (ins RC:$src1, RC:$src2),
2783 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2785 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2787 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2788 (ins RC:$src1, x86memop:$src2),
2789 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2791 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2795 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2796 i512mem, memopv16i32>, EVEX_V512,
2797 EVEX_CD8<32, CD8VF>;
2798 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2799 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2800 EVEX_CD8<64, CD8VF>;
2801 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2802 i512mem, memopv16i32>, EVEX_V512,
2803 EVEX_CD8<32, CD8VF>;
2804 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2805 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2806 EVEX_CD8<64, CD8VF>;
2807 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2808 i512mem, memopv16i32>, EVEX_V512,
2809 EVEX_CD8<32, CD8VF>;
2810 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2811 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2812 EVEX_CD8<64, CD8VF>;
2814 //===----------------------------------------------------------------------===//
2815 // AVX-512 - MOVDDUP
2816 //===----------------------------------------------------------------------===//
2818 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2819 X86MemOperand x86memop, PatFrag memop_frag> {
2820 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2821 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2822 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2823 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2824 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2826 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2829 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2830 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2831 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2832 (VMOVDDUPZrm addr:$src)>;
2834 //===---------------------------------------------------------------------===//
2835 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2836 //===---------------------------------------------------------------------===//
2837 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2838 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2839 X86MemOperand x86memop> {
2840 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2841 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2842 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2844 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2845 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2846 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2849 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2850 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2851 EVEX_CD8<32, CD8VF>;
2852 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2853 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2854 EVEX_CD8<32, CD8VF>;
2856 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2857 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2858 (VMOVSHDUPZrm addr:$src)>;
2859 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2860 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2861 (VMOVSLDUPZrm addr:$src)>;
2863 //===----------------------------------------------------------------------===//
2864 // Move Low to High and High to Low packed FP Instructions
2865 //===----------------------------------------------------------------------===//
2866 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2867 (ins VR128X:$src1, VR128X:$src2),
2868 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2869 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2870 IIC_SSE_MOV_LH>, EVEX_4V;
2871 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2872 (ins VR128X:$src1, VR128X:$src2),
2873 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2874 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2875 IIC_SSE_MOV_LH>, EVEX_4V;
2877 let Predicates = [HasAVX512] in {
2879 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2880 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2881 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2882 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2885 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2886 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2889 //===----------------------------------------------------------------------===//
2890 // FMA - Fused Multiply Operations
2892 let Constraints = "$src1 = $dst" in {
2893 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2894 RegisterClass RC, X86MemOperand x86memop,
2895 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2896 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2897 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2898 (ins RC:$src1, RC:$src2, RC:$src3),
2899 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2900 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2903 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2904 (ins RC:$src1, RC:$src2, x86memop:$src3),
2905 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2906 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2907 (mem_frag addr:$src3))))]>;
2908 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2909 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2910 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2911 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2912 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2913 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2915 } // Constraints = "$src1 = $dst"
2917 let ExeDomain = SSEPackedSingle in {
2918 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2919 memopv16f32, f32mem, loadf32, "{1to16}",
2920 X86Fmadd, v16f32>, EVEX_V512,
2921 EVEX_CD8<32, CD8VF>;
2922 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2923 memopv16f32, f32mem, loadf32, "{1to16}",
2924 X86Fmsub, v16f32>, EVEX_V512,
2925 EVEX_CD8<32, CD8VF>;
2926 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2927 memopv16f32, f32mem, loadf32, "{1to16}",
2928 X86Fmaddsub, v16f32>,
2929 EVEX_V512, EVEX_CD8<32, CD8VF>;
2930 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2931 memopv16f32, f32mem, loadf32, "{1to16}",
2932 X86Fmsubadd, v16f32>,
2933 EVEX_V512, EVEX_CD8<32, CD8VF>;
2934 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2935 memopv16f32, f32mem, loadf32, "{1to16}",
2936 X86Fnmadd, v16f32>, EVEX_V512,
2937 EVEX_CD8<32, CD8VF>;
2938 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2939 memopv16f32, f32mem, loadf32, "{1to16}",
2940 X86Fnmsub, v16f32>, EVEX_V512,
2941 EVEX_CD8<32, CD8VF>;
2943 let ExeDomain = SSEPackedDouble in {
2944 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2945 memopv8f64, f64mem, loadf64, "{1to8}",
2946 X86Fmadd, v8f64>, EVEX_V512,
2947 VEX_W, EVEX_CD8<64, CD8VF>;
2948 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2949 memopv8f64, f64mem, loadf64, "{1to8}",
2950 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2951 EVEX_CD8<64, CD8VF>;
2952 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2953 memopv8f64, f64mem, loadf64, "{1to8}",
2954 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2955 EVEX_CD8<64, CD8VF>;
2956 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2957 memopv8f64, f64mem, loadf64, "{1to8}",
2958 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2959 EVEX_CD8<64, CD8VF>;
2960 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2961 memopv8f64, f64mem, loadf64, "{1to8}",
2962 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2963 EVEX_CD8<64, CD8VF>;
2964 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2965 memopv8f64, f64mem, loadf64, "{1to8}",
2966 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2967 EVEX_CD8<64, CD8VF>;
2970 let Constraints = "$src1 = $dst" in {
2971 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2972 RegisterClass RC, X86MemOperand x86memop,
2973 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2974 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2976 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2977 (ins RC:$src1, RC:$src3, x86memop:$src2),
2978 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2979 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2980 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2981 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2982 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2983 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2984 [(set RC:$dst, (OpNode RC:$src1,
2985 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2987 } // Constraints = "$src1 = $dst"
2990 let ExeDomain = SSEPackedSingle in {
2991 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2992 memopv16f32, f32mem, loadf32, "{1to16}",
2993 X86Fmadd, v16f32>, EVEX_V512,
2994 EVEX_CD8<32, CD8VF>;
2995 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2996 memopv16f32, f32mem, loadf32, "{1to16}",
2997 X86Fmsub, v16f32>, EVEX_V512,
2998 EVEX_CD8<32, CD8VF>;
2999 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
3000 memopv16f32, f32mem, loadf32, "{1to16}",
3001 X86Fmaddsub, v16f32>,
3002 EVEX_V512, EVEX_CD8<32, CD8VF>;
3003 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
3004 memopv16f32, f32mem, loadf32, "{1to16}",
3005 X86Fmsubadd, v16f32>,
3006 EVEX_V512, EVEX_CD8<32, CD8VF>;
3007 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
3008 memopv16f32, f32mem, loadf32, "{1to16}",
3009 X86Fnmadd, v16f32>, EVEX_V512,
3010 EVEX_CD8<32, CD8VF>;
3011 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
3012 memopv16f32, f32mem, loadf32, "{1to16}",
3013 X86Fnmsub, v16f32>, EVEX_V512,
3014 EVEX_CD8<32, CD8VF>;
3016 let ExeDomain = SSEPackedDouble in {
3017 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
3018 memopv8f64, f64mem, loadf64, "{1to8}",
3019 X86Fmadd, v8f64>, EVEX_V512,
3020 VEX_W, EVEX_CD8<64, CD8VF>;
3021 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
3022 memopv8f64, f64mem, loadf64, "{1to8}",
3023 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
3024 EVEX_CD8<64, CD8VF>;
3025 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
3026 memopv8f64, f64mem, loadf64, "{1to8}",
3027 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
3028 EVEX_CD8<64, CD8VF>;
3029 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
3030 memopv8f64, f64mem, loadf64, "{1to8}",
3031 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
3032 EVEX_CD8<64, CD8VF>;
3033 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
3034 memopv8f64, f64mem, loadf64, "{1to8}",
3035 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
3036 EVEX_CD8<64, CD8VF>;
3037 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
3038 memopv8f64, f64mem, loadf64, "{1to8}",
3039 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
3040 EVEX_CD8<64, CD8VF>;
3044 let Constraints = "$src1 = $dst" in {
3045 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3046 RegisterClass RC, ValueType OpVT,
3047 X86MemOperand x86memop, Operand memop,
3049 let isCommutable = 1 in
3050 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3051 (ins RC:$src1, RC:$src2, RC:$src3),
3052 !strconcat(OpcodeStr,
3053 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3055 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3057 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3058 (ins RC:$src1, RC:$src2, f128mem:$src3),
3059 !strconcat(OpcodeStr,
3060 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3062 (OpVT (OpNode RC:$src2, RC:$src1,
3063 (mem_frag addr:$src3))))]>;
3066 } // Constraints = "$src1 = $dst"
3068 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3069 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3070 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3071 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3072 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3073 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3074 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3075 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3076 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3077 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3078 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3079 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3080 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3081 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3082 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3083 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3085 //===----------------------------------------------------------------------===//
3086 // AVX-512 Scalar convert from sign integer to float/double
3087 //===----------------------------------------------------------------------===//
3089 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3090 X86MemOperand x86memop, string asm> {
3091 let hasSideEffects = 0 in {
3092 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3093 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3096 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3097 (ins DstRC:$src1, x86memop:$src),
3098 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3100 } // hasSideEffects = 0
3102 let Predicates = [HasAVX512] in {
3103 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3104 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3105 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3106 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3107 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3108 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3109 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3110 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3112 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3113 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3114 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3115 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3116 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3117 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3118 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3119 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3121 def : Pat<(f32 (sint_to_fp GR32:$src)),
3122 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3123 def : Pat<(f32 (sint_to_fp GR64:$src)),
3124 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3125 def : Pat<(f64 (sint_to_fp GR32:$src)),
3126 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3127 def : Pat<(f64 (sint_to_fp GR64:$src)),
3128 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3130 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3131 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3132 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3133 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3134 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3135 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3136 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3137 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3139 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3140 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3141 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3142 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3143 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3144 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3145 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3146 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3148 def : Pat<(f32 (uint_to_fp GR32:$src)),
3149 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3150 def : Pat<(f32 (uint_to_fp GR64:$src)),
3151 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3152 def : Pat<(f64 (uint_to_fp GR32:$src)),
3153 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3154 def : Pat<(f64 (uint_to_fp GR64:$src)),
3155 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3158 //===----------------------------------------------------------------------===//
3159 // AVX-512 Scalar convert from float/double to integer
3160 //===----------------------------------------------------------------------===//
3161 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3162 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3164 let hasSideEffects = 0 in {
3165 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3166 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3167 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3168 Requires<[HasAVX512]>;
3170 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3171 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3172 Requires<[HasAVX512]>;
3173 } // hasSideEffects = 0
3175 let Predicates = [HasAVX512] in {
3176 // Convert float/double to signed/unsigned int 32/64
3177 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3178 ssmem, sse_load_f32, "cvtss2si">,
3179 XS, EVEX_CD8<32, CD8VT1>;
3180 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3181 ssmem, sse_load_f32, "cvtss2si">,
3182 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3183 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3184 ssmem, sse_load_f32, "cvtss2usi">,
3185 XS, EVEX_CD8<32, CD8VT1>;
3186 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3187 int_x86_avx512_cvtss2usi64, ssmem,
3188 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3189 EVEX_CD8<32, CD8VT1>;
3190 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3191 sdmem, sse_load_f64, "cvtsd2si">,
3192 XD, EVEX_CD8<64, CD8VT1>;
3193 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3194 sdmem, sse_load_f64, "cvtsd2si">,
3195 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3196 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3197 sdmem, sse_load_f64, "cvtsd2usi">,
3198 XD, EVEX_CD8<64, CD8VT1>;
3199 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3200 int_x86_avx512_cvtsd2usi64, sdmem,
3201 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3202 EVEX_CD8<64, CD8VT1>;
3204 let isCodeGenOnly = 1 in {
3205 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3206 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3207 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3208 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3209 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3210 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3211 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3212 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3213 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3214 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3215 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3216 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3218 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3219 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3220 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3221 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3222 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3223 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3224 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3225 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3226 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3227 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3228 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3229 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3230 } // isCodeGenOnly = 1
3232 // Convert float/double to signed/unsigned int 32/64 with truncation
3233 let isCodeGenOnly = 1 in {
3234 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3235 ssmem, sse_load_f32, "cvttss2si">,
3236 XS, EVEX_CD8<32, CD8VT1>;
3237 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3238 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3239 "cvttss2si">, XS, VEX_W,
3240 EVEX_CD8<32, CD8VT1>;
3241 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3242 sdmem, sse_load_f64, "cvttsd2si">, XD,
3243 EVEX_CD8<64, CD8VT1>;
3244 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3245 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3246 "cvttsd2si">, XD, VEX_W,
3247 EVEX_CD8<64, CD8VT1>;
3248 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3249 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3250 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3251 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3252 int_x86_avx512_cvttss2usi64, ssmem,
3253 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3254 EVEX_CD8<32, CD8VT1>;
3255 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3256 int_x86_avx512_cvttsd2usi,
3257 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3258 EVEX_CD8<64, CD8VT1>;
3259 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3260 int_x86_avx512_cvttsd2usi64, sdmem,
3261 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3262 EVEX_CD8<64, CD8VT1>;
3263 } // isCodeGenOnly = 1
3265 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3266 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3268 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3269 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3270 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3271 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3272 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3273 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3276 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3277 loadf32, "cvttss2si">, XS,
3278 EVEX_CD8<32, CD8VT1>;
3279 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3280 loadf32, "cvttss2usi">, XS,
3281 EVEX_CD8<32, CD8VT1>;
3282 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3283 loadf32, "cvttss2si">, XS, VEX_W,
3284 EVEX_CD8<32, CD8VT1>;
3285 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3286 loadf32, "cvttss2usi">, XS, VEX_W,
3287 EVEX_CD8<32, CD8VT1>;
3288 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3289 loadf64, "cvttsd2si">, XD,
3290 EVEX_CD8<64, CD8VT1>;
3291 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3292 loadf64, "cvttsd2usi">, XD,
3293 EVEX_CD8<64, CD8VT1>;
3294 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3295 loadf64, "cvttsd2si">, XD, VEX_W,
3296 EVEX_CD8<64, CD8VT1>;
3297 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3298 loadf64, "cvttsd2usi">, XD, VEX_W,
3299 EVEX_CD8<64, CD8VT1>;
3301 //===----------------------------------------------------------------------===//
3302 // AVX-512 Convert form float to double and back
3303 //===----------------------------------------------------------------------===//
3304 let hasSideEffects = 0 in {
3305 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3306 (ins FR32X:$src1, FR32X:$src2),
3307 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3308 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3310 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3311 (ins FR32X:$src1, f32mem:$src2),
3312 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3313 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3314 EVEX_CD8<32, CD8VT1>;
3316 // Convert scalar double to scalar single
3317 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3318 (ins FR64X:$src1, FR64X:$src2),
3319 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3320 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3322 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3323 (ins FR64X:$src1, f64mem:$src2),
3324 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3325 []>, EVEX_4V, VEX_LIG, VEX_W,
3326 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3329 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3330 Requires<[HasAVX512]>;
3331 def : Pat<(fextend (loadf32 addr:$src)),
3332 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3334 def : Pat<(extloadf32 addr:$src),
3335 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3336 Requires<[HasAVX512, OptForSize]>;
3338 def : Pat<(extloadf32 addr:$src),
3339 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3340 Requires<[HasAVX512, OptForSpeed]>;
3342 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3343 Requires<[HasAVX512]>;
3345 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3346 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3347 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3349 let hasSideEffects = 0 in {
3350 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3351 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3353 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3354 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3355 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3356 [], d>, EVEX, EVEX_B, EVEX_RC;
3358 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3359 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3361 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3362 } // hasSideEffects = 0
3365 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3366 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3367 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3369 let hasSideEffects = 0 in {
3370 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3371 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3373 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3375 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3376 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3378 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3379 } // hasSideEffects = 0
3382 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3383 memopv8f64, f512mem, v8f32, v8f64,
3384 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3385 EVEX_CD8<64, CD8VF>;
3387 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3388 memopv4f64, f256mem, v8f64, v8f32,
3389 SSEPackedDouble>, EVEX_V512, PS,
3390 EVEX_CD8<32, CD8VH>;
3391 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3392 (VCVTPS2PDZrm addr:$src)>;
3394 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3395 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3396 (VCVTPD2PSZrr VR512:$src)>;
3398 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3399 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3400 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3402 //===----------------------------------------------------------------------===//
3403 // AVX-512 Vector convert from sign integer to float/double
3404 //===----------------------------------------------------------------------===//
3406 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3407 memopv8i64, i512mem, v16f32, v16i32,
3408 SSEPackedSingle>, EVEX_V512, PS,
3409 EVEX_CD8<32, CD8VF>;
3411 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3412 memopv4i64, i256mem, v8f64, v8i32,
3413 SSEPackedDouble>, EVEX_V512, XS,
3414 EVEX_CD8<32, CD8VH>;
3416 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3417 memopv16f32, f512mem, v16i32, v16f32,
3418 SSEPackedSingle>, EVEX_V512, XS,
3419 EVEX_CD8<32, CD8VF>;
3421 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3422 memopv8f64, f512mem, v8i32, v8f64,
3423 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3424 EVEX_CD8<64, CD8VF>;
3426 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3427 memopv16f32, f512mem, v16i32, v16f32,
3428 SSEPackedSingle>, EVEX_V512, PS,
3429 EVEX_CD8<32, CD8VF>;
3431 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3432 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3433 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3434 (VCVTTPS2UDQZrr VR512:$src)>;
3436 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3437 memopv8f64, f512mem, v8i32, v8f64,
3438 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3439 EVEX_CD8<64, CD8VF>;
3441 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3442 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3443 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3444 (VCVTTPD2UDQZrr VR512:$src)>;
3446 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3447 memopv4i64, f256mem, v8f64, v8i32,
3448 SSEPackedDouble>, EVEX_V512, XS,
3449 EVEX_CD8<32, CD8VH>;
3451 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3452 memopv16i32, f512mem, v16f32, v16i32,
3453 SSEPackedSingle>, EVEX_V512, XD,
3454 EVEX_CD8<32, CD8VF>;
3456 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3457 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3458 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3460 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3461 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3462 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3464 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3465 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3466 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3468 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3469 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3470 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3472 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3473 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3474 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3476 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3477 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3478 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3479 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3480 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3481 (VCVTDQ2PDZrr VR256X:$src)>;
3482 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3483 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3484 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3485 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3486 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3487 (VCVTUDQ2PDZrr VR256X:$src)>;
3489 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3490 RegisterClass DstRC, PatFrag mem_frag,
3491 X86MemOperand x86memop, Domain d> {
3492 let hasSideEffects = 0 in {
3493 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3494 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3496 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3497 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3498 [], d>, EVEX, EVEX_B, EVEX_RC;
3500 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3501 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3503 } // hasSideEffects = 0
3506 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3507 memopv16f32, f512mem, SSEPackedSingle>, PD,
3508 EVEX_V512, EVEX_CD8<32, CD8VF>;
3509 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3510 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3511 EVEX_V512, EVEX_CD8<64, CD8VF>;
3513 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3514 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3515 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3517 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3518 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3519 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3521 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3522 memopv16f32, f512mem, SSEPackedSingle>,
3523 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3524 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3525 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3526 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3528 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3529 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3530 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3532 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3533 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3534 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3536 let Predicates = [HasAVX512] in {
3537 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3538 (VCVTPD2PSZrm addr:$src)>;
3539 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3540 (VCVTPS2PDZrm addr:$src)>;
3543 //===----------------------------------------------------------------------===//
3544 // Half precision conversion instructions
3545 //===----------------------------------------------------------------------===//
3546 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3547 X86MemOperand x86memop> {
3548 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3549 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3551 let hasSideEffects = 0, mayLoad = 1 in
3552 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3553 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3556 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3557 X86MemOperand x86memop> {
3558 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3559 (ins srcRC:$src1, i32i8imm:$src2),
3560 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3562 let hasSideEffects = 0, mayStore = 1 in
3563 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3564 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3565 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3568 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3569 EVEX_CD8<32, CD8VH>;
3570 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3571 EVEX_CD8<32, CD8VH>;
3573 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3574 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3575 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3577 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3578 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3579 (VCVTPH2PSZrr VR256X:$src)>;
3581 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3582 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3583 "ucomiss">, PS, EVEX, VEX_LIG,
3584 EVEX_CD8<32, CD8VT1>;
3585 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3586 "ucomisd">, PD, EVEX,
3587 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3588 let Pattern = []<dag> in {
3589 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3590 "comiss">, PS, EVEX, VEX_LIG,
3591 EVEX_CD8<32, CD8VT1>;
3592 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3593 "comisd">, PD, EVEX,
3594 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3596 let isCodeGenOnly = 1 in {
3597 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3598 load, "ucomiss">, PS, EVEX, VEX_LIG,
3599 EVEX_CD8<32, CD8VT1>;
3600 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3601 load, "ucomisd">, PD, EVEX,
3602 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3604 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3605 load, "comiss">, PS, EVEX, VEX_LIG,
3606 EVEX_CD8<32, CD8VT1>;
3607 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3608 load, "comisd">, PD, EVEX,
3609 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3613 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3614 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3615 X86MemOperand x86memop> {
3616 let hasSideEffects = 0 in {
3617 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3618 (ins RC:$src1, RC:$src2),
3619 !strconcat(OpcodeStr,
3620 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3621 let mayLoad = 1 in {
3622 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3623 (ins RC:$src1, x86memop:$src2),
3624 !strconcat(OpcodeStr,
3625 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3630 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3631 EVEX_CD8<32, CD8VT1>;
3632 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3633 VEX_W, EVEX_CD8<64, CD8VT1>;
3634 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3635 EVEX_CD8<32, CD8VT1>;
3636 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3637 VEX_W, EVEX_CD8<64, CD8VT1>;
3639 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3640 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3641 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3642 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3644 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3645 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3646 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3647 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3649 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3650 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3651 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3652 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3654 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3655 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3656 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3657 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3659 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3660 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3661 RegisterClass RC, X86MemOperand x86memop,
3662 PatFrag mem_frag, ValueType OpVt> {
3663 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3664 !strconcat(OpcodeStr,
3665 " \t{$src, $dst|$dst, $src}"),
3666 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3668 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3669 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3670 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3673 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3674 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3675 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3676 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3677 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3678 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3679 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3680 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3682 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3683 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3684 (VRSQRT14PSZr VR512:$src)>;
3685 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3686 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3687 (VRSQRT14PDZr VR512:$src)>;
3689 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3690 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3691 (VRCP14PSZr VR512:$src)>;
3692 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3693 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3694 (VRCP14PDZr VR512:$src)>;
3696 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3697 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3698 X86MemOperand x86memop> {
3699 let hasSideEffects = 0, Predicates = [HasERI] in {
3700 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3701 (ins RC:$src1, RC:$src2),
3702 !strconcat(OpcodeStr,
3703 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3704 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3705 (ins RC:$src1, RC:$src2),
3706 !strconcat(OpcodeStr,
3707 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3708 []>, EVEX_4V, EVEX_B;
3709 let mayLoad = 1 in {
3710 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3711 (ins RC:$src1, x86memop:$src2),
3712 !strconcat(OpcodeStr,
3713 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3718 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3719 EVEX_CD8<32, CD8VT1>;
3720 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3721 VEX_W, EVEX_CD8<64, CD8VT1>;
3722 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3723 EVEX_CD8<32, CD8VT1>;
3724 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3725 VEX_W, EVEX_CD8<64, CD8VT1>;
3727 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3728 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3730 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3731 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3733 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3734 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3736 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3737 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3739 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3740 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3742 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3743 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3745 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3746 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3748 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3749 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3751 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3752 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3753 RegisterClass RC, X86MemOperand x86memop> {
3754 let hasSideEffects = 0, Predicates = [HasERI] in {
3755 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3756 !strconcat(OpcodeStr,
3757 " \t{$src, $dst|$dst, $src}"),
3759 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3760 !strconcat(OpcodeStr,
3761 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3763 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3764 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3768 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3769 EVEX_V512, EVEX_CD8<32, CD8VF>;
3770 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3771 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3772 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3773 EVEX_V512, EVEX_CD8<32, CD8VF>;
3774 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3775 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3777 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3778 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3779 (VRSQRT28PSZrb VR512:$src)>;
3780 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3781 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3782 (VRSQRT28PDZrb VR512:$src)>;
3784 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3785 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3786 (VRCP28PSZrb VR512:$src)>;
3787 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3788 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3789 (VRCP28PDZrb VR512:$src)>;
3791 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3792 OpndItins itins_s, OpndItins itins_d> {
3793 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3794 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3795 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3799 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3800 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3802 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3803 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3805 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3806 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3807 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3811 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3812 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3813 [(set VR512:$dst, (OpNode
3814 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3815 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3819 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3820 Intrinsic F32Int, Intrinsic F64Int,
3821 OpndItins itins_s, OpndItins itins_d> {
3822 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3823 (ins FR32X:$src1, FR32X:$src2),
3824 !strconcat(OpcodeStr,
3825 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3826 [], itins_s.rr>, XS, EVEX_4V;
3827 let isCodeGenOnly = 1 in
3828 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3829 (ins VR128X:$src1, VR128X:$src2),
3830 !strconcat(OpcodeStr,
3831 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3833 (F32Int VR128X:$src1, VR128X:$src2))],
3834 itins_s.rr>, XS, EVEX_4V;
3835 let mayLoad = 1 in {
3836 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3837 (ins FR32X:$src1, f32mem:$src2),
3838 !strconcat(OpcodeStr,
3839 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3840 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3841 let isCodeGenOnly = 1 in
3842 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3843 (ins VR128X:$src1, ssmem:$src2),
3844 !strconcat(OpcodeStr,
3845 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3847 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3848 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3850 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3851 (ins FR64X:$src1, FR64X:$src2),
3852 !strconcat(OpcodeStr,
3853 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3855 let isCodeGenOnly = 1 in
3856 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3857 (ins VR128X:$src1, VR128X:$src2),
3858 !strconcat(OpcodeStr,
3859 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3861 (F64Int VR128X:$src1, VR128X:$src2))],
3862 itins_s.rr>, XD, EVEX_4V, VEX_W;
3863 let mayLoad = 1 in {
3864 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3865 (ins FR64X:$src1, f64mem:$src2),
3866 !strconcat(OpcodeStr,
3867 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3868 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3869 let isCodeGenOnly = 1 in
3870 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3871 (ins VR128X:$src1, sdmem:$src2),
3872 !strconcat(OpcodeStr,
3873 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3875 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3876 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3881 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3882 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3883 SSE_SQRTSS, SSE_SQRTSD>,
3884 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3885 SSE_SQRTPS, SSE_SQRTPD>;
3887 let Predicates = [HasAVX512] in {
3888 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
3889 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
3890 (VSQRTPSZrr VR512:$src1)>;
3891 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
3892 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
3893 (VSQRTPDZrr VR512:$src1)>;
3895 def : Pat<(f32 (fsqrt FR32X:$src)),
3896 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3897 def : Pat<(f32 (fsqrt (load addr:$src))),
3898 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3899 Requires<[OptForSize]>;
3900 def : Pat<(f64 (fsqrt FR64X:$src)),
3901 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3902 def : Pat<(f64 (fsqrt (load addr:$src))),
3903 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3904 Requires<[OptForSize]>;
3906 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3907 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3908 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3909 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3910 Requires<[OptForSize]>;
3912 def : Pat<(f32 (X86frcp FR32X:$src)),
3913 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3914 def : Pat<(f32 (X86frcp (load addr:$src))),
3915 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3916 Requires<[OptForSize]>;
3918 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3919 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3920 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3922 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3923 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3925 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3926 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3927 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3929 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3930 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3934 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3935 X86MemOperand x86memop, RegisterClass RC,
3936 PatFrag mem_frag32, PatFrag mem_frag64,
3937 Intrinsic V4F32Int, Intrinsic V2F64Int,
3939 let ExeDomain = SSEPackedSingle in {
3940 // Intrinsic operation, reg.
3941 // Vector intrinsic operation, reg
3942 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3943 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3944 !strconcat(OpcodeStr,
3945 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3946 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3948 // Vector intrinsic operation, mem
3949 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3950 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3951 !strconcat(OpcodeStr,
3952 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3954 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3955 EVEX_CD8<32, VForm>;
3956 } // ExeDomain = SSEPackedSingle
3958 let ExeDomain = SSEPackedDouble in {
3959 // Vector intrinsic operation, reg
3960 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3961 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3962 !strconcat(OpcodeStr,
3963 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3964 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3966 // Vector intrinsic operation, mem
3967 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3968 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3969 !strconcat(OpcodeStr,
3970 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3972 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3973 EVEX_CD8<64, VForm>;
3974 } // ExeDomain = SSEPackedDouble
3977 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3981 let ExeDomain = GenericDomain in {
3983 let hasSideEffects = 0 in
3984 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3985 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3986 !strconcat(OpcodeStr,
3987 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3990 // Intrinsic operation, reg.
3991 let isCodeGenOnly = 1 in
3992 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3993 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3994 !strconcat(OpcodeStr,
3995 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3996 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3998 // Intrinsic operation, mem.
3999 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4000 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4001 !strconcat(OpcodeStr,
4002 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4003 [(set VR128X:$dst, (F32Int VR128X:$src1,
4004 sse_load_f32:$src2, imm:$src3))]>,
4005 EVEX_CD8<32, CD8VT1>;
4008 let hasSideEffects = 0 in
4009 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4010 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4011 !strconcat(OpcodeStr,
4012 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4015 // Intrinsic operation, reg.
4016 let isCodeGenOnly = 1 in
4017 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4018 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4019 !strconcat(OpcodeStr,
4020 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4021 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4024 // Intrinsic operation, mem.
4025 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4026 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4027 !strconcat(OpcodeStr,
4028 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4030 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4031 VEX_W, EVEX_CD8<64, CD8VT1>;
4032 } // ExeDomain = GenericDomain
4035 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4036 X86MemOperand x86memop, RegisterClass RC,
4037 PatFrag mem_frag, Domain d> {
4038 let ExeDomain = d in {
4039 // Intrinsic operation, reg.
4040 // Vector intrinsic operation, reg
4041 def r : AVX512AIi8<opc, MRMSrcReg,
4042 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4043 !strconcat(OpcodeStr,
4044 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4047 // Vector intrinsic operation, mem
4048 def m : AVX512AIi8<opc, MRMSrcMem,
4049 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4050 !strconcat(OpcodeStr,
4051 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4057 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4058 memopv16f32, SSEPackedSingle>, EVEX_V512,
4059 EVEX_CD8<32, CD8VF>;
4061 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4062 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4064 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4067 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4068 memopv8f64, SSEPackedDouble>, EVEX_V512,
4069 VEX_W, EVEX_CD8<64, CD8VF>;
4071 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4072 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4074 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4076 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4077 Operand x86memop, RegisterClass RC, Domain d> {
4078 let ExeDomain = d in {
4079 def r : AVX512AIi8<opc, MRMSrcReg,
4080 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4081 !strconcat(OpcodeStr,
4082 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4085 def m : AVX512AIi8<opc, MRMSrcMem,
4086 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4087 !strconcat(OpcodeStr,
4088 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4093 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4094 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4096 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4097 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4099 def : Pat<(ffloor FR32X:$src),
4100 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4101 def : Pat<(f64 (ffloor FR64X:$src)),
4102 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4103 def : Pat<(f32 (fnearbyint FR32X:$src)),
4104 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4105 def : Pat<(f64 (fnearbyint FR64X:$src)),
4106 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4107 def : Pat<(f32 (fceil FR32X:$src)),
4108 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4109 def : Pat<(f64 (fceil FR64X:$src)),
4110 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4111 def : Pat<(f32 (frint FR32X:$src)),
4112 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4113 def : Pat<(f64 (frint FR64X:$src)),
4114 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4115 def : Pat<(f32 (ftrunc FR32X:$src)),
4116 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4117 def : Pat<(f64 (ftrunc FR64X:$src)),
4118 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4120 def : Pat<(v16f32 (ffloor VR512:$src)),
4121 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4122 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4123 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4124 def : Pat<(v16f32 (fceil VR512:$src)),
4125 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4126 def : Pat<(v16f32 (frint VR512:$src)),
4127 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4128 def : Pat<(v16f32 (ftrunc VR512:$src)),
4129 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4131 def : Pat<(v8f64 (ffloor VR512:$src)),
4132 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4133 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4134 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4135 def : Pat<(v8f64 (fceil VR512:$src)),
4136 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4137 def : Pat<(v8f64 (frint VR512:$src)),
4138 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4139 def : Pat<(v8f64 (ftrunc VR512:$src)),
4140 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4142 //-------------------------------------------------
4143 // Integer truncate and extend operations
4144 //-------------------------------------------------
4146 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4147 RegisterClass dstRC, RegisterClass srcRC,
4148 RegisterClass KRC, X86MemOperand x86memop> {
4149 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4151 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4154 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4155 (ins KRC:$mask, srcRC:$src),
4156 !strconcat(OpcodeStr,
4157 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4160 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4161 (ins KRC:$mask, srcRC:$src),
4162 !strconcat(OpcodeStr,
4163 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4166 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4167 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4170 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4171 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4172 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4176 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4177 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4178 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4179 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4180 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4181 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4182 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4183 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4184 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4185 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4186 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4187 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4188 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4189 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4190 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4191 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4192 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4193 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4194 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4195 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4196 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4197 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4198 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4199 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4200 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4201 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4202 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4203 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4204 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4205 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4207 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4208 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4209 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4210 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4211 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4213 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4214 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4215 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4216 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4217 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4218 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4219 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4220 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4223 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4224 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4225 PatFrag mem_frag, X86MemOperand x86memop,
4226 ValueType OpVT, ValueType InVT> {
4228 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4230 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4231 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4233 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4234 (ins KRC:$mask, SrcRC:$src),
4235 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4238 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4239 (ins KRC:$mask, SrcRC:$src),
4240 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4243 let mayLoad = 1 in {
4244 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4245 (ins x86memop:$src),
4246 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4248 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4251 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4252 (ins KRC:$mask, x86memop:$src),
4253 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4257 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4258 (ins KRC:$mask, x86memop:$src),
4259 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4265 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4266 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4268 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4269 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4271 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4272 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4273 EVEX_CD8<16, CD8VH>;
4274 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4275 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4276 EVEX_CD8<16, CD8VQ>;
4277 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4278 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4279 EVEX_CD8<32, CD8VH>;
4281 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4282 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4284 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4285 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4287 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4288 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4289 EVEX_CD8<16, CD8VH>;
4290 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4291 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4292 EVEX_CD8<16, CD8VQ>;
4293 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4294 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4295 EVEX_CD8<32, CD8VH>;
4297 //===----------------------------------------------------------------------===//
4298 // GATHER - SCATTER Operations
4300 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4301 RegisterClass RC, X86MemOperand memop> {
4303 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4304 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4305 (ins RC:$src1, KRC:$mask, memop:$src2),
4306 !strconcat(OpcodeStr,
4307 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4311 let ExeDomain = SSEPackedDouble in {
4312 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4313 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4314 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4315 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4318 let ExeDomain = SSEPackedSingle in {
4319 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4320 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4321 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4322 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4325 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4326 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4327 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4328 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4330 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4331 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4332 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4333 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4335 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4336 RegisterClass RC, X86MemOperand memop> {
4337 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4338 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4339 (ins memop:$dst, KRC:$mask, RC:$src2),
4340 !strconcat(OpcodeStr,
4341 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4345 let ExeDomain = SSEPackedDouble in {
4346 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4347 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4348 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4349 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4352 let ExeDomain = SSEPackedSingle in {
4353 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4354 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4355 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4356 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4359 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4360 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4361 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4362 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4364 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4365 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4366 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4367 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4370 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4371 RegisterClass KRC, X86MemOperand memop> {
4372 let Predicates = [HasPFI], hasSideEffects = 1 in
4373 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4374 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4378 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4379 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4381 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4382 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4384 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4385 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4387 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4388 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4390 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4391 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4393 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4394 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4396 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4397 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4399 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4400 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4402 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4403 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4405 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4406 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4408 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4409 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4411 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4412 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4414 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4415 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4417 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4418 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4420 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4421 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4423 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4424 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4425 //===----------------------------------------------------------------------===//
4426 // VSHUFPS - VSHUFPD Operations
4428 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4429 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4431 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4432 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4433 !strconcat(OpcodeStr,
4434 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4435 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4436 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4437 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4438 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4439 (ins RC:$src1, RC:$src2, i8imm:$src3),
4440 !strconcat(OpcodeStr,
4441 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4442 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4443 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4444 EVEX_4V, Sched<[WriteShuffle]>;
4447 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4448 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4449 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4450 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4452 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4453 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4454 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4455 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4456 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4458 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4459 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4460 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4461 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4462 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4464 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4465 X86MemOperand x86memop, ValueType IntVT,
4466 ValueType FloatVT> {
4467 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4468 (ins RC:$src1, RC:$src2, i8imm:$src3),
4469 !strconcat(OpcodeStr,
4470 " \t{$src3, $src2, $src1, $dst|"
4471 "$dst, $src1, $src2, $src3}"),
4473 (IntVT (X86PAlignr RC:$src2, RC:$src1,
4474 (i8 imm:$src3))))]>, EVEX_4V;
4476 // Also match valign of packed floats.
4477 def : Pat<(FloatVT (X86PAlignr RC:$src1, RC:$src2, (i8 imm:$imm))),
4478 (!cast<Instruction>(NAME##rri) RC:$src2, RC:$src1, imm:$imm)>;
4481 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4482 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4483 !strconcat(OpcodeStr,
4484 " \t{$src3, $src2, $src1, $dst|"
4485 "$dst, $src1, $src2, $src3}"),
4488 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem, v16i32, v16f32>,
4489 EVEX_V512, EVEX_CD8<32, CD8VF>;
4490 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem, v8i64, v8f64>,
4491 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4493 // Helper fragments to match sext vXi1 to vXiY.
4494 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4495 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4497 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4498 RegisterClass KRC, RegisterClass RC,
4499 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4501 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4502 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4504 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4505 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4507 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4508 !strconcat(OpcodeStr,
4509 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4511 let mayLoad = 1 in {
4512 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4513 (ins x86memop:$src),
4514 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4516 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4517 (ins KRC:$mask, x86memop:$src),
4518 !strconcat(OpcodeStr,
4519 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4521 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4522 (ins KRC:$mask, x86memop:$src),
4523 !strconcat(OpcodeStr,
4524 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4526 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4527 (ins x86scalar_mop:$src),
4528 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4529 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4531 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4532 (ins KRC:$mask, x86scalar_mop:$src),
4533 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4534 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4535 []>, EVEX, EVEX_B, EVEX_K;
4536 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4537 (ins KRC:$mask, x86scalar_mop:$src),
4538 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4539 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4541 []>, EVEX, EVEX_B, EVEX_KZ;
4545 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4546 i512mem, i32mem, "{1to16}">, EVEX_V512,
4547 EVEX_CD8<32, CD8VF>;
4548 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4549 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4550 EVEX_CD8<64, CD8VF>;
4553 (bc_v16i32 (v16i1sextv16i32)),
4554 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4555 (VPABSDZrr VR512:$src)>;
4557 (bc_v8i64 (v8i1sextv8i64)),
4558 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4559 (VPABSQZrr VR512:$src)>;
4561 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4562 (v16i32 immAllZerosV), (i16 -1))),
4563 (VPABSDZrr VR512:$src)>;
4564 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4565 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4566 (VPABSQZrr VR512:$src)>;
4568 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4569 RegisterClass RC, RegisterClass KRC,
4570 X86MemOperand x86memop,
4571 X86MemOperand x86scalar_mop, string BrdcstStr> {
4572 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4574 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4576 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4577 (ins x86memop:$src),
4578 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4580 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4581 (ins x86scalar_mop:$src),
4582 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4583 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4585 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4586 (ins KRC:$mask, RC:$src),
4587 !strconcat(OpcodeStr,
4588 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4590 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4591 (ins KRC:$mask, x86memop:$src),
4592 !strconcat(OpcodeStr,
4593 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4595 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4596 (ins KRC:$mask, x86scalar_mop:$src),
4597 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4598 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4600 []>, EVEX, EVEX_KZ, EVEX_B;
4602 let Constraints = "$src1 = $dst" in {
4603 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4604 (ins RC:$src1, KRC:$mask, RC:$src2),
4605 !strconcat(OpcodeStr,
4606 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4608 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4609 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4610 !strconcat(OpcodeStr,
4611 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4613 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4614 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4615 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4616 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4617 []>, EVEX, EVEX_K, EVEX_B;
4621 let Predicates = [HasCDI] in {
4622 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4623 i512mem, i32mem, "{1to16}">,
4624 EVEX_V512, EVEX_CD8<32, CD8VF>;
4627 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4628 i512mem, i64mem, "{1to8}">,
4629 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4633 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4635 (VPCONFLICTDrrk VR512:$src1,
4636 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4638 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4640 (VPCONFLICTQrrk VR512:$src1,
4641 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4643 let Predicates = [HasCDI] in {
4644 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4645 i512mem, i32mem, "{1to16}">,
4646 EVEX_V512, EVEX_CD8<32, CD8VF>;
4649 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4650 i512mem, i64mem, "{1to8}">,
4651 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4655 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4657 (VPLZCNTDrrk VR512:$src1,
4658 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4660 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4662 (VPLZCNTQrrk VR512:$src1,
4663 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4665 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4666 (VPLZCNTDrm addr:$src)>;
4667 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4668 (VPLZCNTDrr VR512:$src)>;
4669 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4670 (VPLZCNTQrm addr:$src)>;
4671 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4672 (VPLZCNTQrr VR512:$src)>;
4674 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4675 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4676 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4678 def : Pat<(store VK1:$src, addr:$dst),
4679 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4681 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4682 (truncstore node:$val, node:$ptr), [{
4683 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4686 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4687 (MOV8mr addr:$dst, GR8:$src)>;