1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
11 // Corresponding mask register class.
12 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
14 // Corresponding write-mask register class.
15 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
17 // The GPR register class that can hold the write mask. Use GR8 for fewer
18 // than 8 elements. Use shift-right and equal to work around the lack of
21 !cast<RegisterClass>("GR" #
22 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
24 // Suffix used in the instruction mnemonic.
25 string Suffix = suffix;
27 // VTName is a string name for vector VT. For vector types it will be
28 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
29 // It is a little bit complex for scalar types, where NumElts = 1.
30 // In this case we build v4f32 or v2f64
31 string VTName = "v" # !if (!eq (NumElts, 1),
32 !if (!eq (EltVT.Size, 32), 4,
33 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
36 ValueType VT = !cast<ValueType>(VTName);
38 string EltTypeName = !cast<string>(EltVT);
39 // Size of the element type in bits, e.g. 32 for v16i32.
40 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
41 int EltSize = EltVT.Size;
43 // "i" for integer types and "f" for floating-point types
44 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
46 // Size of RC in bits, e.g. 512 for VR512.
49 // The corresponding memory operand, e.g. i512mem for VR512.
50 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
51 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
54 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
55 // due to load promotion during legalization
56 PatFrag LdFrag = !cast<PatFrag>("load" #
57 !if (!eq (TypeVariantName, "i"),
58 !if (!eq (Size, 128), "v2i64",
59 !if (!eq (Size, 256), "v4i64",
61 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
63 // Load patterns used for memory operands. We only have this defined in
64 // case of i64 element types for sub-512 integer vectors. For now, keep
65 // MemOpFrag undefined in these cases.
67 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
68 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
69 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
70 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
71 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
73 // The corresponding float type, e.g. v16f32 for v16i32
74 // Note: For EltSize < 32, FloatVT is illegal and TableGen
75 // fails to compile, so we choose FloatVT = VT
76 ValueType FloatVT = !cast<ValueType>(
77 !if (!eq (!srl(EltSize,5),0),
79 !if (!eq(TypeVariantName, "i"),
80 "v" # NumElts # "f" # EltSize,
83 // The string to specify embedded broadcast in assembly.
84 string BroadcastStr = "{1to" # NumElts # "}";
86 // 8-bit compressed displacement tuple/subvector format. This is only
87 // defined for NumElts <= 8.
88 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
89 !cast<CD8VForm>("CD8VT" # NumElts), ?);
91 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
92 !if (!eq (Size, 256), sub_ymm, ?));
94 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
95 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
98 // A vector type of the same width with element type i32. This is used to
99 // create the canonical constant zero node ImmAllZerosV.
100 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
101 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
104 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
105 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
106 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
107 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
108 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
109 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
111 // "x" in v32i8x_info means RC = VR256X
112 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
113 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
114 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
115 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
116 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
117 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
119 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
120 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
121 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
122 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
123 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
124 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
126 // We map scalar types to the smallest (128-bit) vector type
127 // with the appropriate element type. This allows to use the same masking logic.
128 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
129 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
131 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
132 X86VectorVTInfo i128> {
133 X86VectorVTInfo info512 = i512;
134 X86VectorVTInfo info256 = i256;
135 X86VectorVTInfo info128 = i128;
138 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
140 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
142 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
144 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
146 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
148 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
151 // This multiclass generates the masking variants from the non-masking
152 // variant. It only provides the assembly pieces for the masking variants.
153 // It assumes custom ISel patterns for masking which can be provided as
154 // template arguments.
155 multiclass AVX512_maskable_custom<bits<8> O, Format F,
157 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
159 string AttSrcAsm, string IntelSrcAsm,
161 list<dag> MaskingPattern,
162 list<dag> ZeroMaskingPattern,
164 string MaskingConstraint = "",
165 InstrItinClass itin = NoItinerary,
166 bit IsCommutable = 0> {
167 let isCommutable = IsCommutable in
168 def NAME: AVX512<O, F, Outs, Ins,
169 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
170 "$dst "#Round#", "#IntelSrcAsm#"}",
173 // Prefer over VMOV*rrk Pat<>
174 let AddedComplexity = 20 in
175 def NAME#k: AVX512<O, F, Outs, MaskingIns,
176 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
177 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
178 MaskingPattern, itin>,
180 // In case of the 3src subclass this is overridden with a let.
181 string Constraints = MaskingConstraint;
183 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
184 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
185 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
186 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
193 // Common base class of AVX512_maskable and AVX512_maskable_3src.
194 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
196 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
198 string AttSrcAsm, string IntelSrcAsm,
199 dag RHS, dag MaskingRHS,
200 SDNode Select = vselect, string Round = "",
201 string MaskingConstraint = "",
202 InstrItinClass itin = NoItinerary,
203 bit IsCommutable = 0> :
204 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
205 AttSrcAsm, IntelSrcAsm,
206 [(set _.RC:$dst, RHS)],
207 [(set _.RC:$dst, MaskingRHS)],
209 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
210 Round, MaskingConstraint, NoItinerary, IsCommutable>;
212 // This multiclass generates the unconditional/non-masking, the masking and
213 // the zero-masking variant of the vector instruction. In the masking case, the
214 // perserved vector elements come from a new dummy input operand tied to $dst.
215 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
216 dag Outs, dag Ins, string OpcodeStr,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, string Round = "",
219 InstrItinClass itin = NoItinerary,
220 bit IsCommutable = 0> :
221 AVX512_maskable_common<O, F, _, Outs, Ins,
222 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
223 !con((ins _.KRCWM:$mask), Ins),
224 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
225 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
226 Round, "$src0 = $dst", itin, IsCommutable>;
228 // This multiclass generates the unconditional/non-masking, the masking and
229 // the zero-masking variant of the scalar instruction.
230 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
231 dag Outs, dag Ins, string OpcodeStr,
232 string AttSrcAsm, string IntelSrcAsm,
233 dag RHS, string Round = "",
234 InstrItinClass itin = NoItinerary,
235 bit IsCommutable = 0> :
236 AVX512_maskable_common<O, F, _, Outs, Ins,
237 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
238 !con((ins _.KRCWM:$mask), Ins),
239 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
240 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
241 Round, "$src0 = $dst", itin, IsCommutable>;
243 // Similar to AVX512_maskable but in this case one of the source operands
244 // ($src1) is already tied to $dst so we just use that for the preserved
245 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
247 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
248 dag Outs, dag NonTiedIns, string OpcodeStr,
249 string AttSrcAsm, string IntelSrcAsm,
251 AVX512_maskable_common<O, F, _, Outs,
252 !con((ins _.RC:$src1), NonTiedIns),
253 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
255 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
256 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
259 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
262 string AttSrcAsm, string IntelSrcAsm,
264 AVX512_maskable_custom<O, F, Outs, Ins,
265 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
266 !con((ins _.KRCWM:$mask), Ins),
267 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
270 // Bitcasts between 512-bit vector types. Return the original type since
271 // no instruction is needed for the conversion
272 let Predicates = [HasAVX512] in {
273 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
274 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
275 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
276 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
277 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
278 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
279 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
280 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
281 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
282 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
283 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
284 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
285 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
286 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
287 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
288 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
289 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
290 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
291 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
292 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
293 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
296 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
297 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
299 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
300 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
302 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
303 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
305 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
306 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
307 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
308 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
309 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
310 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
311 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
312 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
313 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
314 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
315 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
316 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
317 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
318 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
319 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
320 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
321 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
322 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
323 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
324 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
325 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
326 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
327 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
328 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
329 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
330 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
331 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
332 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
333 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
334 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
336 // Bitcasts between 256-bit vector types. Return the original type since
337 // no instruction is needed for the conversion
338 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
339 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
340 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
341 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
342 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
343 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
344 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
346 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
347 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
348 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
350 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
351 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
352 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
353 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
355 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
357 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
358 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
359 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
360 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
361 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
363 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
365 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
367 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
371 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
374 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
375 isPseudo = 1, Predicates = [HasAVX512] in {
376 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
377 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
380 let Predicates = [HasAVX512] in {
381 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
382 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
383 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
386 //===----------------------------------------------------------------------===//
387 // AVX-512 - VECTOR INSERT
390 multiclass vinsert_for_size_no_alt<int Opcode,
391 X86VectorVTInfo From, X86VectorVTInfo To,
392 PatFrag vinsert_insert,
393 SDNodeXForm INSERT_get_vinsert_imm> {
394 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
395 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
396 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
397 "vinsert" # From.EltTypeName # "x" # From.NumElts #
398 "\t{$src3, $src2, $src1, $dst|"
399 "$dst, $src1, $src2, $src3}",
400 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
401 (From.VT From.RC:$src2),
406 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
407 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
408 "vinsert" # From.EltTypeName # "x" # From.NumElts #
409 "\t{$src3, $src2, $src1, $dst|"
410 "$dst, $src1, $src2, $src3}",
412 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
416 multiclass vinsert_for_size<int Opcode,
417 X86VectorVTInfo From, X86VectorVTInfo To,
418 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
419 PatFrag vinsert_insert,
420 SDNodeXForm INSERT_get_vinsert_imm> :
421 vinsert_for_size_no_alt<Opcode, From, To,
422 vinsert_insert, INSERT_get_vinsert_imm> {
423 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
424 // vinserti32x4. Only add this if 64x2 and friends are not supported
425 // natively via AVX512DQ.
426 let Predicates = [NoDQI] in
427 def : Pat<(vinsert_insert:$ins
428 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
429 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
430 VR512:$src1, From.RC:$src2,
431 (INSERT_get_vinsert_imm VR512:$ins)))>;
434 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
435 ValueType EltVT64, int Opcode256> {
436 defm NAME # "32x4" : vinsert_for_size<Opcode128,
437 X86VectorVTInfo< 4, EltVT32, VR128X>,
438 X86VectorVTInfo<16, EltVT32, VR512>,
439 X86VectorVTInfo< 2, EltVT64, VR128X>,
440 X86VectorVTInfo< 8, EltVT64, VR512>,
442 INSERT_get_vinsert128_imm>;
443 let Predicates = [HasDQI] in
444 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
445 X86VectorVTInfo< 2, EltVT64, VR128X>,
446 X86VectorVTInfo< 8, EltVT64, VR512>,
448 INSERT_get_vinsert128_imm>, VEX_W;
449 defm NAME # "64x4" : vinsert_for_size<Opcode256,
450 X86VectorVTInfo< 4, EltVT64, VR256X>,
451 X86VectorVTInfo< 8, EltVT64, VR512>,
452 X86VectorVTInfo< 8, EltVT32, VR256>,
453 X86VectorVTInfo<16, EltVT32, VR512>,
455 INSERT_get_vinsert256_imm>, VEX_W;
456 let Predicates = [HasDQI] in
457 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
458 X86VectorVTInfo< 8, EltVT32, VR256X>,
459 X86VectorVTInfo<16, EltVT32, VR512>,
461 INSERT_get_vinsert256_imm>;
464 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
465 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
467 // vinsertps - insert f32 to XMM
468 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
469 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
470 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
471 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
473 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
474 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
475 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
476 [(set VR128X:$dst, (X86insertps VR128X:$src1,
477 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
478 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
480 //===----------------------------------------------------------------------===//
481 // AVX-512 VECTOR EXTRACT
484 multiclass vextract_for_size<int Opcode,
485 X86VectorVTInfo From, X86VectorVTInfo To,
486 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
487 PatFrag vextract_extract,
488 SDNodeXForm EXTRACT_get_vextract_imm> {
489 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
490 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
491 (ins VR512:$src1, i8imm:$idx),
492 "vextract" # To.EltTypeName # "x4",
493 "$idx, $src1", "$src1, $idx",
494 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
496 AVX512AIi8Base, EVEX, EVEX_V512;
498 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
499 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
500 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
501 "$dst, $src1, $src2}",
502 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
505 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
507 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
508 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
510 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
512 // A 128/256-bit subvector extract from the first 512-bit vector position is
513 // a subregister copy that needs no instruction.
514 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
516 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
518 // And for the alternative types.
519 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
521 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
523 // Intrinsic call with masking.
524 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
526 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
527 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
528 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
529 VR512:$src1, imm:$idx)>;
531 // Intrinsic call with zero-masking.
532 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
534 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
535 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
536 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
537 VR512:$src1, imm:$idx)>;
539 // Intrinsic call without masking.
540 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
542 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
543 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
544 VR512:$src1, imm:$idx)>;
547 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
548 ValueType EltVT64, int Opcode64> {
549 defm NAME # "32x4" : vextract_for_size<Opcode32,
550 X86VectorVTInfo<16, EltVT32, VR512>,
551 X86VectorVTInfo< 4, EltVT32, VR128X>,
552 X86VectorVTInfo< 8, EltVT64, VR512>,
553 X86VectorVTInfo< 2, EltVT64, VR128X>,
555 EXTRACT_get_vextract128_imm>;
556 defm NAME # "64x4" : vextract_for_size<Opcode64,
557 X86VectorVTInfo< 8, EltVT64, VR512>,
558 X86VectorVTInfo< 4, EltVT64, VR256X>,
559 X86VectorVTInfo<16, EltVT32, VR512>,
560 X86VectorVTInfo< 8, EltVT32, VR256>,
562 EXTRACT_get_vextract256_imm>, VEX_W;
565 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
566 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
568 // A 128-bit subvector insert to the first 512-bit vector position
569 // is a subregister copy that needs no instruction.
570 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
571 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
572 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
574 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
575 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
576 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
578 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
579 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
580 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
582 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
583 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
584 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
587 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
588 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
589 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
590 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
591 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
592 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
593 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
594 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
596 // vextractps - extract 32 bits from XMM
597 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
598 (ins VR128X:$src1, i32i8imm:$src2),
599 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
600 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
603 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
604 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
605 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
606 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
607 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
609 //===---------------------------------------------------------------------===//
612 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
613 ValueType svt, X86VectorVTInfo _> {
614 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
615 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
616 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
620 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
621 (ins _.ScalarMemOp:$src),
622 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
623 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
628 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
629 AVX512VLVectorVTInfo _> {
630 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
633 let Predicates = [HasVLX] in {
634 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
639 let ExeDomain = SSEPackedSingle in {
640 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
641 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
642 let Predicates = [HasVLX] in {
643 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
644 v4f32, v4f32x_info>, EVEX_V128,
645 EVEX_CD8<32, CD8VT1>;
649 let ExeDomain = SSEPackedDouble in {
650 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
651 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
654 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
655 (VBROADCASTSSZm addr:$src)>;
656 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
657 (VBROADCASTSDZm addr:$src)>;
659 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
660 (VBROADCASTSSZm addr:$src)>;
661 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
662 (VBROADCASTSDZm addr:$src)>;
664 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
665 RegisterClass SrcRC> {
666 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
667 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
668 "$src", "$src", []>, T8PD, EVEX;
671 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
672 RegisterClass SrcRC, Predicate prd> {
673 let Predicates = [prd] in
674 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
675 let Predicates = [prd, HasVLX] in {
676 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
677 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
681 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
683 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
685 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
687 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
690 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
691 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
693 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
694 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
696 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
697 (VPBROADCASTDrZr GR32:$src)>;
698 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
699 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
700 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
701 (VPBROADCASTQrZr GR64:$src)>;
702 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
703 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
705 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
706 (VPBROADCASTDrZr GR32:$src)>;
707 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
708 (VPBROADCASTQrZr GR64:$src)>;
710 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
711 (v16i32 immAllZerosV), (i16 GR16:$mask))),
712 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
713 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
714 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
715 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
717 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
718 X86MemOperand x86memop, PatFrag ld_frag,
719 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
721 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
722 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
724 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
725 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
727 !strconcat(OpcodeStr,
728 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
730 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
733 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
734 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
736 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
737 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
739 !strconcat(OpcodeStr,
740 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
741 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
742 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
746 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
747 loadi32, VR512, v16i32, v4i32, VK16WM>,
748 EVEX_V512, EVEX_CD8<32, CD8VT1>;
749 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
750 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
751 EVEX_CD8<64, CD8VT1>;
753 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
754 X86MemOperand x86memop, PatFrag ld_frag,
757 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
758 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
760 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
762 !strconcat(OpcodeStr,
763 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
768 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
769 i128mem, loadv2i64, VK16WM>,
770 EVEX_V512, EVEX_CD8<32, CD8VT4>;
771 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
772 i256mem, loadv4i64, VK16WM>, VEX_W,
773 EVEX_V512, EVEX_CD8<64, CD8VT4>;
775 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
776 (VPBROADCASTDZrr VR128X:$src)>;
777 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
778 (VPBROADCASTQZrr VR128X:$src)>;
780 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
781 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
782 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
783 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
785 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
786 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
787 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
788 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
790 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
791 (VBROADCASTSSZr VR128X:$src)>;
792 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
793 (VBROADCASTSDZr VR128X:$src)>;
795 // Provide fallback in case the load node that is used in the patterns above
796 // is used by additional users, which prevents the pattern selection.
797 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
798 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
799 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
800 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
803 let Predicates = [HasAVX512] in {
804 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
806 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
807 addr:$src)), sub_ymm)>;
809 //===----------------------------------------------------------------------===//
810 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
813 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
815 let Predicates = [HasCDI] in
816 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
817 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
818 []>, EVEX, EVEX_V512;
820 let Predicates = [HasCDI, HasVLX] in {
821 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
822 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
823 []>, EVEX, EVEX_V128;
824 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
825 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
826 []>, EVEX, EVEX_V256;
830 let Predicates = [HasCDI] in {
831 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
833 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
837 //===----------------------------------------------------------------------===//
840 // -- immediate form --
841 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
843 let ExeDomain = _.ExeDomain in {
844 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
845 (ins _.RC:$src1, i8imm:$src2),
846 !strconcat(OpcodeStr,
847 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
849 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
851 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
852 (ins _.MemOp:$src1, i8imm:$src2),
853 !strconcat(OpcodeStr,
854 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
856 (_.VT (OpNode (_.MemOpFrag addr:$src1),
858 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
862 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
863 X86VectorVTInfo Ctrl> :
864 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
865 let ExeDomain = _.ExeDomain in {
866 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
867 (ins _.RC:$src1, _.RC:$src2),
868 !strconcat("vpermil" # _.Suffix,
869 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
871 (_.VT (X86VPermilpv _.RC:$src1,
872 (Ctrl.VT Ctrl.RC:$src2))))]>,
874 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
875 (ins _.RC:$src1, Ctrl.MemOp:$src2),
876 !strconcat("vpermil" # _.Suffix,
877 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
879 (_.VT (X86VPermilpv _.RC:$src1,
880 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
885 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
887 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
890 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
892 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
895 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
896 (VPERMILPSZri VR512:$src1, imm:$imm)>;
897 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
898 (VPERMILPDZri VR512:$src1, imm:$imm)>;
900 // -- VPERM - register form --
901 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
902 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
904 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
905 (ins RC:$src1, RC:$src2),
906 !strconcat(OpcodeStr,
907 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
909 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
911 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
912 (ins RC:$src1, x86memop:$src2),
913 !strconcat(OpcodeStr,
914 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
916 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
920 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
921 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
922 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
923 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
924 let ExeDomain = SSEPackedSingle in
925 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
926 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
927 let ExeDomain = SSEPackedDouble in
928 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
929 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
931 // -- VPERM2I - 3 source operands form --
932 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
933 PatFrag mem_frag, X86MemOperand x86memop,
934 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
935 let Constraints = "$src1 = $dst" in {
936 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
937 (ins RC:$src1, RC:$src2, RC:$src3),
938 !strconcat(OpcodeStr,
939 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
941 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
944 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
945 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
946 !strconcat(OpcodeStr,
947 "\t{$src3, $src2, $dst {${mask}}|"
948 "$dst {${mask}}, $src2, $src3}"),
949 [(set RC:$dst, (OpVT (vselect KRC:$mask,
950 (OpNode RC:$src1, RC:$src2,
955 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
956 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
957 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
958 !strconcat(OpcodeStr,
959 "\t{$src3, $src2, $dst {${mask}} {z} |",
960 "$dst {${mask}} {z}, $src2, $src3}"),
961 [(set RC:$dst, (OpVT (vselect KRC:$mask,
962 (OpNode RC:$src1, RC:$src2,
965 (v16i32 immAllZerosV))))))]>,
968 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
969 (ins RC:$src1, RC:$src2, x86memop:$src3),
970 !strconcat(OpcodeStr,
971 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
973 (OpVT (OpNode RC:$src1, RC:$src2,
974 (mem_frag addr:$src3))))]>, EVEX_4V;
976 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
977 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
978 !strconcat(OpcodeStr,
979 "\t{$src3, $src2, $dst {${mask}}|"
980 "$dst {${mask}}, $src2, $src3}"),
982 (OpVT (vselect KRC:$mask,
983 (OpNode RC:$src1, RC:$src2,
984 (mem_frag addr:$src3)),
988 let AddedComplexity = 10 in // Prefer over the rrkz variant
989 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
990 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
991 !strconcat(OpcodeStr,
992 "\t{$src3, $src2, $dst {${mask}} {z}|"
993 "$dst {${mask}} {z}, $src2, $src3}"),
995 (OpVT (vselect KRC:$mask,
996 (OpNode RC:$src1, RC:$src2,
997 (mem_frag addr:$src3)),
999 (v16i32 immAllZerosV))))))]>,
1003 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
1004 i512mem, X86VPermiv3, v16i32, VK16WM>,
1005 EVEX_V512, EVEX_CD8<32, CD8VF>;
1006 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
1007 i512mem, X86VPermiv3, v8i64, VK8WM>,
1008 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1009 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
1010 i512mem, X86VPermiv3, v16f32, VK16WM>,
1011 EVEX_V512, EVEX_CD8<32, CD8VF>;
1012 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
1013 i512mem, X86VPermiv3, v8f64, VK8WM>,
1014 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1016 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1017 PatFrag mem_frag, X86MemOperand x86memop,
1018 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1019 ValueType MaskVT, RegisterClass MRC> :
1020 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1022 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1023 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1024 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1026 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1027 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1028 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1029 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1032 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1033 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1034 EVEX_V512, EVEX_CD8<32, CD8VF>;
1035 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1036 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1037 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1038 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1039 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1040 EVEX_V512, EVEX_CD8<32, CD8VF>;
1041 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1042 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1043 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1045 //===----------------------------------------------------------------------===//
1046 // AVX-512 - BLEND using mask
1048 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
1049 RegisterClass KRC, RegisterClass RC,
1050 X86MemOperand x86memop, PatFrag mem_frag,
1051 SDNode OpNode, ValueType vt> {
1052 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1053 (ins KRC:$mask, RC:$src1, RC:$src2),
1054 !strconcat(OpcodeStr,
1055 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1056 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
1057 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
1059 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1060 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1061 !strconcat(OpcodeStr,
1062 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1063 []>, EVEX_4V, EVEX_K;
1066 let ExeDomain = SSEPackedSingle in
1067 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
1068 VK16WM, VR512, f512mem,
1069 memopv16f32, vselect, v16f32>,
1070 EVEX_CD8<32, CD8VF>, EVEX_V512;
1071 let ExeDomain = SSEPackedDouble in
1072 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
1073 VK8WM, VR512, f512mem,
1074 memopv8f64, vselect, v8f64>,
1075 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1077 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1078 (v16f32 VR512:$src2), (i16 GR16:$mask))),
1079 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
1080 VR512:$src1, VR512:$src2)>;
1082 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1083 (v8f64 VR512:$src2), (i8 GR8:$mask))),
1084 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
1085 VR512:$src1, VR512:$src2)>;
1087 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
1088 VK16WM, VR512, f512mem,
1089 memopv16i32, vselect, v16i32>,
1090 EVEX_CD8<32, CD8VF>, EVEX_V512;
1092 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
1093 VK8WM, VR512, f512mem,
1094 memopv8i64, vselect, v8i64>,
1095 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1097 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1098 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1099 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1100 VR512:$src1, VR512:$src2)>;
1102 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1103 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1104 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1105 VR512:$src1, VR512:$src2)>;
1107 let Predicates = [HasAVX512] in {
1108 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1109 (v8f32 VR256X:$src2))),
1111 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1112 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1113 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1115 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1116 (v8i32 VR256X:$src2))),
1118 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1119 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1120 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1122 //===----------------------------------------------------------------------===//
1123 // Compare Instructions
1124 //===----------------------------------------------------------------------===//
1126 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1127 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1128 Operand CC, SDNode OpNode, ValueType VT,
1129 PatFrag ld_frag, string asm, string asm_alt> {
1130 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1131 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1132 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1133 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1134 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1135 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1136 [(set VK1:$dst, (OpNode (VT RC:$src1),
1137 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1138 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1139 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1140 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1141 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1142 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1143 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1144 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1148 let Predicates = [HasAVX512] in {
1149 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1150 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1151 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1153 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1154 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1155 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1159 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1160 X86VectorVTInfo _> {
1161 def rr : AVX512BI<opc, MRMSrcReg,
1162 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1163 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1164 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1165 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1167 def rm : AVX512BI<opc, MRMSrcMem,
1168 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1169 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1170 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1171 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1172 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1173 def rrk : AVX512BI<opc, MRMSrcReg,
1174 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1175 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1176 "$dst {${mask}}, $src1, $src2}"),
1177 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1178 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1179 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1181 def rmk : AVX512BI<opc, MRMSrcMem,
1182 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1183 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1184 "$dst {${mask}}, $src1, $src2}"),
1185 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1186 (OpNode (_.VT _.RC:$src1),
1188 (_.LdFrag addr:$src2))))))],
1189 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1192 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1193 X86VectorVTInfo _> :
1194 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1195 let mayLoad = 1 in {
1196 def rmb : AVX512BI<opc, MRMSrcMem,
1197 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1198 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1199 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1200 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1201 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1202 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1203 def rmbk : AVX512BI<opc, MRMSrcMem,
1204 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1205 _.ScalarMemOp:$src2),
1206 !strconcat(OpcodeStr,
1207 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1208 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1209 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1210 (OpNode (_.VT _.RC:$src1),
1212 (_.ScalarLdFrag addr:$src2)))))],
1213 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1217 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1218 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1219 let Predicates = [prd] in
1220 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1223 let Predicates = [prd, HasVLX] in {
1224 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1226 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1231 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1232 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1234 let Predicates = [prd] in
1235 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1238 let Predicates = [prd, HasVLX] in {
1239 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1241 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1246 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1247 avx512vl_i8_info, HasBWI>,
1250 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1251 avx512vl_i16_info, HasBWI>,
1252 EVEX_CD8<16, CD8VF>;
1254 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1255 avx512vl_i32_info, HasAVX512>,
1256 EVEX_CD8<32, CD8VF>;
1258 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1259 avx512vl_i64_info, HasAVX512>,
1260 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1262 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1263 avx512vl_i8_info, HasBWI>,
1266 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1267 avx512vl_i16_info, HasBWI>,
1268 EVEX_CD8<16, CD8VF>;
1270 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1271 avx512vl_i32_info, HasAVX512>,
1272 EVEX_CD8<32, CD8VF>;
1274 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1275 avx512vl_i64_info, HasAVX512>,
1276 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1278 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1279 (COPY_TO_REGCLASS (VPCMPGTDZrr
1280 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1281 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1283 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1284 (COPY_TO_REGCLASS (VPCMPEQDZrr
1285 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1286 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1288 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1289 X86VectorVTInfo _> {
1290 def rri : AVX512AIi8<opc, MRMSrcReg,
1291 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1292 !strconcat("vpcmp${cc}", Suffix,
1293 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1294 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1296 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1298 def rmi : AVX512AIi8<opc, MRMSrcMem,
1299 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1300 !strconcat("vpcmp${cc}", Suffix,
1301 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1302 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1303 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1305 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1306 def rrik : AVX512AIi8<opc, MRMSrcReg,
1307 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1309 !strconcat("vpcmp${cc}", Suffix,
1310 "\t{$src2, $src1, $dst {${mask}}|",
1311 "$dst {${mask}}, $src1, $src2}"),
1312 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1313 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1315 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1317 def rmik : AVX512AIi8<opc, MRMSrcMem,
1318 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1320 !strconcat("vpcmp${cc}", Suffix,
1321 "\t{$src2, $src1, $dst {${mask}}|",
1322 "$dst {${mask}}, $src1, $src2}"),
1323 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1324 (OpNode (_.VT _.RC:$src1),
1325 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1327 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1329 // Accept explicit immediate argument form instead of comparison code.
1330 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1331 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1332 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1333 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1334 "$dst, $src1, $src2, $cc}"),
1335 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1336 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1337 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1338 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1339 "$dst, $src1, $src2, $cc}"),
1340 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1341 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1342 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1344 !strconcat("vpcmp", Suffix,
1345 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1346 "$dst {${mask}}, $src1, $src2, $cc}"),
1347 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1348 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1349 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1351 !strconcat("vpcmp", Suffix,
1352 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1353 "$dst {${mask}}, $src1, $src2, $cc}"),
1354 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1358 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1359 X86VectorVTInfo _> :
1360 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1361 let mayLoad = 1 in {
1362 def rmib : AVX512AIi8<opc, MRMSrcMem,
1363 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1365 !strconcat("vpcmp${cc}", Suffix,
1366 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1367 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1368 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1369 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1371 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1372 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1373 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1374 _.ScalarMemOp:$src2, AVXCC:$cc),
1375 !strconcat("vpcmp${cc}", Suffix,
1376 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1377 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1378 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1379 (OpNode (_.VT _.RC:$src1),
1380 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1382 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1385 // Accept explicit immediate argument form instead of comparison code.
1386 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1387 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1388 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1390 !strconcat("vpcmp", Suffix,
1391 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1392 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1393 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1394 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1395 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1396 _.ScalarMemOp:$src2, i8imm:$cc),
1397 !strconcat("vpcmp", Suffix,
1398 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1399 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1400 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1404 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1405 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1406 let Predicates = [prd] in
1407 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1409 let Predicates = [prd, HasVLX] in {
1410 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1411 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1415 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1416 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1417 let Predicates = [prd] in
1418 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1421 let Predicates = [prd, HasVLX] in {
1422 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1424 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1429 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1430 HasBWI>, EVEX_CD8<8, CD8VF>;
1431 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1432 HasBWI>, EVEX_CD8<8, CD8VF>;
1434 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1435 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1436 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1437 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1439 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1440 HasAVX512>, EVEX_CD8<32, CD8VF>;
1441 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1442 HasAVX512>, EVEX_CD8<32, CD8VF>;
1444 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1445 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1446 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1447 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1449 // avx512_cmp_packed - compare packed instructions
1450 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1451 X86MemOperand x86memop, ValueType vt,
1452 string suffix, Domain d> {
1453 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1454 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1455 !strconcat("vcmp${cc}", suffix,
1456 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1457 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1458 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1459 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1460 !strconcat("vcmp${cc}", suffix,
1461 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1463 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1464 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1465 !strconcat("vcmp${cc}", suffix,
1466 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1468 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
1470 // Accept explicit immediate argument form instead of comparison code.
1471 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1472 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1473 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1474 !strconcat("vcmp", suffix,
1475 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1476 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1477 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1478 !strconcat("vcmp", suffix,
1479 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1483 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1484 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1485 EVEX_CD8<32, CD8VF>;
1486 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1487 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1488 EVEX_CD8<64, CD8VF>;
1490 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1491 (COPY_TO_REGCLASS (VCMPPSZrri
1492 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1493 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1495 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1496 (COPY_TO_REGCLASS (VPCMPDZrri
1497 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1498 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1500 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1501 (COPY_TO_REGCLASS (VPCMPUDZrri
1502 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1503 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1506 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1507 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1509 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1510 (I8Imm imm:$cc)), GR16)>;
1512 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1513 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1515 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1516 (I8Imm imm:$cc)), GR8)>;
1518 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1519 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1521 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1522 (I8Imm imm:$cc)), GR16)>;
1524 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1525 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1527 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1528 (I8Imm imm:$cc)), GR8)>;
1530 // Mask register copy, including
1531 // - copy between mask registers
1532 // - load/store mask registers
1533 // - copy from GPR to mask register and vice versa
1535 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1536 string OpcodeStr, RegisterClass KRC,
1537 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1538 let hasSideEffects = 0 in {
1539 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1540 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1542 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1543 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1544 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1546 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1547 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1551 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1553 RegisterClass KRC, RegisterClass GRC> {
1554 let hasSideEffects = 0 in {
1555 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1556 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1557 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1558 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1562 let Predicates = [HasDQI] in
1563 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1565 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1568 let Predicates = [HasAVX512] in
1569 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1571 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1574 let Predicates = [HasBWI] in {
1575 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1576 i32mem>, VEX, PD, VEX_W;
1577 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1581 let Predicates = [HasBWI] in {
1582 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1583 i64mem>, VEX, PS, VEX_W;
1584 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1588 // GR from/to mask register
1589 let Predicates = [HasDQI] in {
1590 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1591 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1592 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1593 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1595 let Predicates = [HasAVX512] in {
1596 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1597 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1598 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1599 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1601 let Predicates = [HasBWI] in {
1602 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1603 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1605 let Predicates = [HasBWI] in {
1606 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1607 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1611 let Predicates = [HasDQI] in {
1612 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1613 (KMOVBmk addr:$dst, VK8:$src)>;
1615 let Predicates = [HasAVX512] in {
1616 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1617 (KMOVWmk addr:$dst, VK16:$src)>;
1618 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1619 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1620 def : Pat<(i1 (load addr:$src)),
1621 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1622 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1623 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1625 let Predicates = [HasBWI] in {
1626 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1627 (KMOVDmk addr:$dst, VK32:$src)>;
1629 let Predicates = [HasBWI] in {
1630 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1631 (KMOVQmk addr:$dst, VK64:$src)>;
1634 let Predicates = [HasAVX512] in {
1635 def : Pat<(i1 (trunc (i64 GR64:$src))),
1636 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1639 def : Pat<(i1 (trunc (i32 GR32:$src))),
1640 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1642 def : Pat<(i1 (trunc (i8 GR8:$src))),
1644 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1646 def : Pat<(i1 (trunc (i16 GR16:$src))),
1648 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1651 def : Pat<(i32 (zext VK1:$src)),
1652 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1653 def : Pat<(i8 (zext VK1:$src)),
1656 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1657 def : Pat<(i64 (zext VK1:$src)),
1658 (AND64ri8 (SUBREG_TO_REG (i64 0),
1659 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1660 def : Pat<(i16 (zext VK1:$src)),
1662 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1664 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1665 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1666 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1667 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1669 let Predicates = [HasBWI] in {
1670 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1671 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1672 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1673 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1677 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1678 let Predicates = [HasAVX512] in {
1679 // GR from/to 8-bit mask without native support
1680 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1682 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1684 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1686 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1689 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1690 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1691 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1692 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1694 let Predicates = [HasBWI] in {
1695 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1696 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1697 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1698 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1701 // Mask unary operation
1703 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1704 RegisterClass KRC, SDPatternOperator OpNode,
1706 let Predicates = [prd] in
1707 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1708 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1709 [(set KRC:$dst, (OpNode KRC:$src))]>;
1712 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1713 SDPatternOperator OpNode> {
1714 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1716 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1717 HasAVX512>, VEX, PS;
1718 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1719 HasBWI>, VEX, PD, VEX_W;
1720 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1721 HasBWI>, VEX, PS, VEX_W;
1724 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1726 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1727 let Predicates = [HasAVX512] in
1728 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1730 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1731 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1733 defm : avx512_mask_unop_int<"knot", "KNOT">;
1735 let Predicates = [HasDQI] in
1736 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1737 let Predicates = [HasAVX512] in
1738 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1739 let Predicates = [HasBWI] in
1740 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1741 let Predicates = [HasBWI] in
1742 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1744 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1745 let Predicates = [HasAVX512] in {
1746 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1747 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1749 def : Pat<(not VK8:$src),
1751 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1754 // Mask binary operation
1755 // - KAND, KANDN, KOR, KXNOR, KXOR
1756 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1757 RegisterClass KRC, SDPatternOperator OpNode,
1759 let Predicates = [prd] in
1760 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1761 !strconcat(OpcodeStr,
1762 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1763 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1766 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1767 SDPatternOperator OpNode> {
1768 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1769 HasDQI>, VEX_4V, VEX_L, PD;
1770 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1771 HasAVX512>, VEX_4V, VEX_L, PS;
1772 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1773 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1774 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1775 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1778 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1779 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1781 let isCommutable = 1 in {
1782 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1783 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1784 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1785 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1787 let isCommutable = 0 in
1788 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1790 def : Pat<(xor VK1:$src1, VK1:$src2),
1791 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1792 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1794 def : Pat<(or VK1:$src1, VK1:$src2),
1795 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1796 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1798 def : Pat<(and VK1:$src1, VK1:$src2),
1799 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1800 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1802 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1803 let Predicates = [HasAVX512] in
1804 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1805 (i16 GR16:$src1), (i16 GR16:$src2)),
1806 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1807 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1808 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1811 defm : avx512_mask_binop_int<"kand", "KAND">;
1812 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1813 defm : avx512_mask_binop_int<"kor", "KOR">;
1814 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1815 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1817 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1818 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1819 let Predicates = [HasAVX512] in
1820 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1822 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1823 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1826 defm : avx512_binop_pat<and, KANDWrr>;
1827 defm : avx512_binop_pat<andn, KANDNWrr>;
1828 defm : avx512_binop_pat<or, KORWrr>;
1829 defm : avx512_binop_pat<xnor, KXNORWrr>;
1830 defm : avx512_binop_pat<xor, KXORWrr>;
1833 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1834 RegisterClass KRC> {
1835 let Predicates = [HasAVX512] in
1836 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1837 !strconcat(OpcodeStr,
1838 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1841 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1842 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1846 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1847 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1848 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1849 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1852 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1853 let Predicates = [HasAVX512] in
1854 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1855 (i16 GR16:$src1), (i16 GR16:$src2)),
1856 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1857 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1858 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1860 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1863 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1865 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1866 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1867 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1868 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1871 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1872 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1876 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1878 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1879 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1880 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1883 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1885 let Predicates = [HasAVX512] in
1886 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1887 !strconcat(OpcodeStr,
1888 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1889 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1892 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1894 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1898 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1899 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1901 // Mask setting all 0s or 1s
1902 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1903 let Predicates = [HasAVX512] in
1904 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1905 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1906 [(set KRC:$dst, (VT Val))]>;
1909 multiclass avx512_mask_setop_w<PatFrag Val> {
1910 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1911 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1914 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1915 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1917 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1918 let Predicates = [HasAVX512] in {
1919 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1920 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1921 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1922 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1923 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1925 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1926 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1928 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1929 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1931 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1932 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1934 let Predicates = [HasVLX] in {
1935 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1936 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1937 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1938 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1939 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1940 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1941 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1942 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1945 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1946 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1948 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1949 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1950 //===----------------------------------------------------------------------===//
1951 // AVX-512 - Aligned and unaligned load and store
1954 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1955 RegisterClass KRC, RegisterClass RC,
1956 ValueType vt, ValueType zvt, X86MemOperand memop,
1957 Domain d, bit IsReMaterializable = 1> {
1958 let hasSideEffects = 0 in {
1959 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1960 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1962 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1963 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1964 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
1966 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1967 SchedRW = [WriteLoad] in
1968 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1969 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1970 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1973 let AddedComplexity = 20 in {
1974 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1975 let hasSideEffects = 0 in
1976 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1977 (ins RC:$src0, KRC:$mask, RC:$src1),
1978 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1979 "${dst} {${mask}}, $src1}"),
1980 [(set RC:$dst, (vt (vselect KRC:$mask,
1984 let mayLoad = 1, SchedRW = [WriteLoad] in
1985 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1986 (ins RC:$src0, KRC:$mask, memop:$src1),
1987 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1988 "${dst} {${mask}}, $src1}"),
1991 (vt (bitconvert (ld_frag addr:$src1))),
1995 let mayLoad = 1, SchedRW = [WriteLoad] in
1996 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1997 (ins KRC:$mask, memop:$src),
1998 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1999 "${dst} {${mask}} {z}, $src}"),
2002 (vt (bitconvert (ld_frag addr:$src))),
2003 (vt (bitconvert (zvt immAllZerosV))))))],
2008 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2009 string elty, string elsz, string vsz512,
2010 string vsz256, string vsz128, Domain d,
2011 Predicate prd, bit IsReMaterializable = 1> {
2012 let Predicates = [prd] in
2013 defm Z : avx512_load<opc, OpcodeStr,
2014 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2015 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2016 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2017 !cast<X86MemOperand>(elty##"512mem"), d,
2018 IsReMaterializable>, EVEX_V512;
2020 let Predicates = [prd, HasVLX] in {
2021 defm Z256 : avx512_load<opc, OpcodeStr,
2022 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2023 "v"##vsz256##elty##elsz, "v4i64")),
2024 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2025 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2026 !cast<X86MemOperand>(elty##"256mem"), d,
2027 IsReMaterializable>, EVEX_V256;
2029 defm Z128 : avx512_load<opc, OpcodeStr,
2030 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2031 "v"##vsz128##elty##elsz, "v2i64")),
2032 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2033 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2034 !cast<X86MemOperand>(elty##"128mem"), d,
2035 IsReMaterializable>, EVEX_V128;
2040 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2041 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2042 X86MemOperand memop, Domain d> {
2043 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2044 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2045 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2047 let Constraints = "$src1 = $dst" in
2048 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2049 (ins RC:$src1, KRC:$mask, RC:$src2),
2050 !strconcat(OpcodeStr,
2051 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2053 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2054 (ins KRC:$mask, RC:$src),
2055 !strconcat(OpcodeStr,
2056 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2057 [], d>, EVEX, EVEX_KZ;
2059 let mayStore = 1 in {
2060 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2061 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2062 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2063 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2064 (ins memop:$dst, KRC:$mask, RC:$src),
2065 !strconcat(OpcodeStr,
2066 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2067 [], d>, EVEX, EVEX_K;
2072 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2073 string st_suff_512, string st_suff_256,
2074 string st_suff_128, string elty, string elsz,
2075 string vsz512, string vsz256, string vsz128,
2076 Domain d, Predicate prd> {
2077 let Predicates = [prd] in
2078 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2079 !cast<ValueType>("v"##vsz512##elty##elsz),
2080 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2081 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2083 let Predicates = [prd, HasVLX] in {
2084 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2085 !cast<ValueType>("v"##vsz256##elty##elsz),
2086 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2087 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2089 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2090 !cast<ValueType>("v"##vsz128##elty##elsz),
2091 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2092 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2096 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2097 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2098 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2099 "512", "256", "", "f", "32", "16", "8", "4",
2100 SSEPackedSingle, HasAVX512>,
2101 PS, EVEX_CD8<32, CD8VF>;
2103 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2104 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2105 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2106 "512", "256", "", "f", "64", "8", "4", "2",
2107 SSEPackedDouble, HasAVX512>,
2108 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2110 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2111 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2112 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2113 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2114 PS, EVEX_CD8<32, CD8VF>;
2116 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2117 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2118 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2119 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2120 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2122 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2123 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2124 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2126 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2127 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2128 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2130 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2132 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2134 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2136 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2139 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2140 (VMOVUPSZmrk addr:$ptr,
2141 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2142 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2144 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2145 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2146 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2148 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2149 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2151 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2152 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2154 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2155 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2157 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2158 (bc_v16f32 (v16i32 immAllZerosV)))),
2159 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2161 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2162 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2164 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2165 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2167 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2168 (bc_v8f64 (v16i32 immAllZerosV)))),
2169 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2171 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2172 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2174 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2175 "16", "8", "4", SSEPackedInt, HasAVX512>,
2176 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2177 "512", "256", "", "i", "32", "16", "8", "4",
2178 SSEPackedInt, HasAVX512>,
2179 PD, EVEX_CD8<32, CD8VF>;
2181 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2182 "8", "4", "2", SSEPackedInt, HasAVX512>,
2183 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2184 "512", "256", "", "i", "64", "8", "4", "2",
2185 SSEPackedInt, HasAVX512>,
2186 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2188 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2189 "64", "32", "16", SSEPackedInt, HasBWI>,
2190 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2191 "i", "8", "64", "32", "16", SSEPackedInt,
2192 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2194 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2195 "32", "16", "8", SSEPackedInt, HasBWI>,
2196 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2197 "i", "16", "32", "16", "8", SSEPackedInt,
2198 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2200 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2201 "16", "8", "4", SSEPackedInt, HasAVX512>,
2202 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2203 "i", "32", "16", "8", "4", SSEPackedInt,
2204 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2206 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2207 "8", "4", "2", SSEPackedInt, HasAVX512>,
2208 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2209 "i", "64", "8", "4", "2", SSEPackedInt,
2210 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2212 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2213 (v16i32 immAllZerosV), GR16:$mask)),
2214 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2216 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2217 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2218 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2220 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2222 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2224 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2226 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2229 let AddedComplexity = 20 in {
2230 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2231 (bc_v8i64 (v16i32 immAllZerosV)))),
2232 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2234 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2235 (v8i64 VR512:$src))),
2236 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2239 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2240 (v16i32 immAllZerosV))),
2241 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2243 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2244 (v16i32 VR512:$src))),
2245 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2248 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2249 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2251 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2252 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2254 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2255 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2257 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2258 (bc_v8i64 (v16i32 immAllZerosV)))),
2259 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2261 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2262 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2264 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2265 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2267 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2268 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2270 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2271 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2274 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2275 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2278 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2279 (VMOVDQU32Zmrk addr:$ptr,
2280 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2281 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2283 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2284 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2285 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2288 // Move Int Doubleword to Packed Double Int
2290 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2291 "vmovd\t{$src, $dst|$dst, $src}",
2293 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2295 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2296 "vmovd\t{$src, $dst|$dst, $src}",
2298 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2299 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2300 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2301 "vmovq\t{$src, $dst|$dst, $src}",
2303 (v2i64 (scalar_to_vector GR64:$src)))],
2304 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2305 let isCodeGenOnly = 1 in {
2306 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2307 "vmovq\t{$src, $dst|$dst, $src}",
2308 [(set FR64:$dst, (bitconvert GR64:$src))],
2309 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2310 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2311 "vmovq\t{$src, $dst|$dst, $src}",
2312 [(set GR64:$dst, (bitconvert FR64:$src))],
2313 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2315 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2316 "vmovq\t{$src, $dst|$dst, $src}",
2317 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2318 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2319 EVEX_CD8<64, CD8VT1>;
2321 // Move Int Doubleword to Single Scalar
2323 let isCodeGenOnly = 1 in {
2324 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2325 "vmovd\t{$src, $dst|$dst, $src}",
2326 [(set FR32X:$dst, (bitconvert GR32:$src))],
2327 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2329 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2330 "vmovd\t{$src, $dst|$dst, $src}",
2331 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2332 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2335 // Move doubleword from xmm register to r/m32
2337 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2338 "vmovd\t{$src, $dst|$dst, $src}",
2339 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2340 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2342 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2343 (ins i32mem:$dst, VR128X:$src),
2344 "vmovd\t{$src, $dst|$dst, $src}",
2345 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2346 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2347 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2349 // Move quadword from xmm1 register to r/m64
2351 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2352 "vmovq\t{$src, $dst|$dst, $src}",
2353 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2355 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2356 Requires<[HasAVX512, In64BitMode]>;
2358 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2359 (ins i64mem:$dst, VR128X:$src),
2360 "vmovq\t{$src, $dst|$dst, $src}",
2361 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2362 addr:$dst)], IIC_SSE_MOVDQ>,
2363 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2364 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2366 // Move Scalar Single to Double Int
2368 let isCodeGenOnly = 1 in {
2369 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2371 "vmovd\t{$src, $dst|$dst, $src}",
2372 [(set GR32:$dst, (bitconvert FR32X:$src))],
2373 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2374 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2375 (ins i32mem:$dst, FR32X:$src),
2376 "vmovd\t{$src, $dst|$dst, $src}",
2377 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2378 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2381 // Move Quadword Int to Packed Quadword Int
2383 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2385 "vmovq\t{$src, $dst|$dst, $src}",
2387 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2388 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2390 //===----------------------------------------------------------------------===//
2391 // AVX-512 MOVSS, MOVSD
2392 //===----------------------------------------------------------------------===//
2394 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2395 SDNode OpNode, ValueType vt,
2396 X86MemOperand x86memop, PatFrag mem_pat> {
2397 let hasSideEffects = 0 in {
2398 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2399 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2400 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2401 (scalar_to_vector RC:$src2))))],
2402 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2403 let Constraints = "$src1 = $dst" in
2404 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2405 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2407 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2408 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2409 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2410 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2411 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2413 let mayStore = 1 in {
2414 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2415 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2416 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2418 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2419 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2420 [], IIC_SSE_MOV_S_MR>,
2421 EVEX, VEX_LIG, EVEX_K;
2423 } //hasSideEffects = 0
2426 let ExeDomain = SSEPackedSingle in
2427 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2428 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2430 let ExeDomain = SSEPackedDouble in
2431 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2432 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2434 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2435 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2436 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2438 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2439 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2440 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2442 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2443 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2444 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2446 // For the disassembler
2447 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2448 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2449 (ins VR128X:$src1, FR32X:$src2),
2450 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2452 XS, EVEX_4V, VEX_LIG;
2453 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2454 (ins VR128X:$src1, FR64X:$src2),
2455 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2457 XD, EVEX_4V, VEX_LIG, VEX_W;
2460 let Predicates = [HasAVX512] in {
2461 let AddedComplexity = 15 in {
2462 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2463 // MOVS{S,D} to the lower bits.
2464 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2465 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2466 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2467 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2468 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2469 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2470 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2471 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2473 // Move low f32 and clear high bits.
2474 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2475 (SUBREG_TO_REG (i32 0),
2476 (VMOVSSZrr (v4f32 (V_SET0)),
2477 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2478 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2479 (SUBREG_TO_REG (i32 0),
2480 (VMOVSSZrr (v4i32 (V_SET0)),
2481 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2484 let AddedComplexity = 20 in {
2485 // MOVSSrm zeros the high parts of the register; represent this
2486 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2487 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2488 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2489 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2490 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2491 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2492 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2494 // MOVSDrm zeros the high parts of the register; represent this
2495 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2496 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2497 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2498 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2499 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2500 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2501 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2502 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2503 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2504 def : Pat<(v2f64 (X86vzload addr:$src)),
2505 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2507 // Represent the same patterns above but in the form they appear for
2509 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2510 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2511 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2512 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2513 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2514 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2515 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2516 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2517 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2519 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2520 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2521 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2522 FR32X:$src)), sub_xmm)>;
2523 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2524 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2525 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2526 FR64X:$src)), sub_xmm)>;
2527 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2528 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2529 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2531 // Move low f64 and clear high bits.
2532 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2533 (SUBREG_TO_REG (i32 0),
2534 (VMOVSDZrr (v2f64 (V_SET0)),
2535 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2537 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2538 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2539 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2541 // Extract and store.
2542 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2544 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2545 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2547 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2549 // Shuffle with VMOVSS
2550 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2551 (VMOVSSZrr (v4i32 VR128X:$src1),
2552 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2553 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2554 (VMOVSSZrr (v4f32 VR128X:$src1),
2555 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2558 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2559 (SUBREG_TO_REG (i32 0),
2560 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2561 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2563 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2564 (SUBREG_TO_REG (i32 0),
2565 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2566 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2569 // Shuffle with VMOVSD
2570 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2571 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2572 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2573 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2574 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2575 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2576 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2577 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2580 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2581 (SUBREG_TO_REG (i32 0),
2582 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2583 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2585 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2586 (SUBREG_TO_REG (i32 0),
2587 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2588 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2591 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2592 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2593 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2594 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2595 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2596 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2597 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2598 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2601 let AddedComplexity = 15 in
2602 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2604 "vmovq\t{$src, $dst|$dst, $src}",
2605 [(set VR128X:$dst, (v2i64 (X86vzmovl
2606 (v2i64 VR128X:$src))))],
2607 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2609 let AddedComplexity = 20 in
2610 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2612 "vmovq\t{$src, $dst|$dst, $src}",
2613 [(set VR128X:$dst, (v2i64 (X86vzmovl
2614 (loadv2i64 addr:$src))))],
2615 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2616 EVEX_CD8<8, CD8VT8>;
2618 let Predicates = [HasAVX512] in {
2619 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2620 let AddedComplexity = 20 in {
2621 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2622 (VMOVDI2PDIZrm addr:$src)>;
2623 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2624 (VMOV64toPQIZrr GR64:$src)>;
2625 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2626 (VMOVDI2PDIZrr GR32:$src)>;
2628 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2629 (VMOVDI2PDIZrm addr:$src)>;
2630 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2631 (VMOVDI2PDIZrm addr:$src)>;
2632 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2633 (VMOVZPQILo2PQIZrm addr:$src)>;
2634 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2635 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2636 def : Pat<(v2i64 (X86vzload addr:$src)),
2637 (VMOVZPQILo2PQIZrm addr:$src)>;
2640 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2641 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2642 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2643 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2644 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2645 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2646 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2649 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2650 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2652 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2653 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2655 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2656 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2658 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2659 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2661 //===----------------------------------------------------------------------===//
2662 // AVX-512 - Non-temporals
2663 //===----------------------------------------------------------------------===//
2664 let SchedRW = [WriteLoad] in {
2665 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2666 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2667 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2668 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2669 EVEX_CD8<64, CD8VF>;
2671 let Predicates = [HasAVX512, HasVLX] in {
2672 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2674 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2675 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2676 EVEX_CD8<64, CD8VF>;
2678 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2680 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2681 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2682 EVEX_CD8<64, CD8VF>;
2686 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2687 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2688 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2689 let SchedRW = [WriteStore], mayStore = 1,
2690 AddedComplexity = 400 in
2691 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2692 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2693 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2696 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2697 string elty, string elsz, string vsz512,
2698 string vsz256, string vsz128, Domain d,
2699 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2700 let Predicates = [prd] in
2701 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2702 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2703 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2706 let Predicates = [prd, HasVLX] in {
2707 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2708 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2709 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2712 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2713 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2714 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2719 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2720 "i", "64", "8", "4", "2", SSEPackedInt,
2721 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2723 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2724 "f", "64", "8", "4", "2", SSEPackedDouble,
2725 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2727 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2728 "f", "32", "16", "8", "4", SSEPackedSingle,
2729 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2731 //===----------------------------------------------------------------------===//
2732 // AVX-512 - Integer arithmetic
2734 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2735 X86VectorVTInfo _, OpndItins itins,
2736 bit IsCommutable = 0> {
2737 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2738 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2739 "$src2, $src1", "$src1, $src2",
2740 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2741 "", itins.rr, IsCommutable>,
2742 AVX512BIBase, EVEX_4V;
2745 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2746 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2747 "$src2, $src1", "$src1, $src2",
2748 (_.VT (OpNode _.RC:$src1,
2749 (bitconvert (_.LdFrag addr:$src2)))),
2751 AVX512BIBase, EVEX_4V;
2754 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2755 X86VectorVTInfo _, OpndItins itins,
2756 bit IsCommutable = 0> :
2757 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2759 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2760 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2761 "${src2}"##_.BroadcastStr##", $src1",
2762 "$src1, ${src2}"##_.BroadcastStr,
2763 (_.VT (OpNode _.RC:$src1,
2765 (_.ScalarLdFrag addr:$src2)))),
2767 AVX512BIBase, EVEX_4V, EVEX_B;
2770 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2771 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2772 Predicate prd, bit IsCommutable = 0> {
2773 let Predicates = [prd] in
2774 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2775 IsCommutable>, EVEX_V512;
2777 let Predicates = [prd, HasVLX] in {
2778 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2779 IsCommutable>, EVEX_V256;
2780 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2781 IsCommutable>, EVEX_V128;
2785 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2786 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2787 Predicate prd, bit IsCommutable = 0> {
2788 let Predicates = [prd] in
2789 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2790 IsCommutable>, EVEX_V512;
2792 let Predicates = [prd, HasVLX] in {
2793 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2794 IsCommutable>, EVEX_V256;
2795 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2796 IsCommutable>, EVEX_V128;
2800 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2801 OpndItins itins, Predicate prd,
2802 bit IsCommutable = 0> {
2803 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2804 itins, prd, IsCommutable>,
2805 VEX_W, EVEX_CD8<64, CD8VF>;
2808 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2809 OpndItins itins, Predicate prd,
2810 bit IsCommutable = 0> {
2811 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2812 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2815 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2816 OpndItins itins, Predicate prd,
2817 bit IsCommutable = 0> {
2818 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2819 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2822 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2823 OpndItins itins, Predicate prd,
2824 bit IsCommutable = 0> {
2825 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2826 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2829 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2830 SDNode OpNode, OpndItins itins, Predicate prd,
2831 bit IsCommutable = 0> {
2832 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2835 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2839 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2840 SDNode OpNode, OpndItins itins, Predicate prd,
2841 bit IsCommutable = 0> {
2842 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2845 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2849 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2850 bits<8> opc_d, bits<8> opc_q,
2851 string OpcodeStr, SDNode OpNode,
2852 OpndItins itins, bit IsCommutable = 0> {
2853 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2854 itins, HasAVX512, IsCommutable>,
2855 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2856 itins, HasBWI, IsCommutable>;
2859 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2860 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2861 PatFrag memop_frag, X86MemOperand x86memop,
2862 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2863 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2864 let isCommutable = IsCommutable in
2866 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2867 (ins RC:$src1, RC:$src2),
2868 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2870 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2871 (ins KRC:$mask, RC:$src1, RC:$src2),
2872 !strconcat(OpcodeStr,
2873 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2874 [], itins.rr>, EVEX_4V, EVEX_K;
2875 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2876 (ins KRC:$mask, RC:$src1, RC:$src2),
2877 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
2878 "|$dst {${mask}} {z}, $src1, $src2}"),
2879 [], itins.rr>, EVEX_4V, EVEX_KZ;
2881 let mayLoad = 1 in {
2882 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2883 (ins RC:$src1, x86memop:$src2),
2884 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2886 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2887 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2888 !strconcat(OpcodeStr,
2889 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2890 [], itins.rm>, EVEX_4V, EVEX_K;
2891 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2892 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2893 !strconcat(OpcodeStr,
2894 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2895 [], itins.rm>, EVEX_4V, EVEX_KZ;
2896 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2897 (ins RC:$src1, x86scalar_mop:$src2),
2898 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2899 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2900 [], itins.rm>, EVEX_4V, EVEX_B;
2901 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2902 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2903 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2904 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2906 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2907 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2908 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2909 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2910 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2912 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2916 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2917 SSE_INTALU_ITINS_P, 1>;
2918 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2919 SSE_INTALU_ITINS_P, 0>;
2920 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2921 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2922 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2923 SSE_INTALU_ITINS_P, HasBWI, 1>;
2924 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2925 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
2927 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2928 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2929 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2930 EVEX_CD8<64, CD8VF>, VEX_W;
2932 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2933 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2934 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2936 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2937 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2939 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2940 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2941 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2942 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2943 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2944 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2946 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2947 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2948 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2949 SSE_INTALU_ITINS_P, HasBWI, 1>;
2950 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2951 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2953 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2954 SSE_INTALU_ITINS_P, HasBWI, 1>;
2955 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2956 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2957 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2958 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2960 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2961 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2962 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2963 SSE_INTALU_ITINS_P, HasBWI, 1>;
2964 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2965 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2967 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2968 SSE_INTALU_ITINS_P, HasBWI, 1>;
2969 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2970 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2971 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2972 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2974 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2975 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2976 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2977 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2978 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2979 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2980 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2981 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2982 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2983 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2984 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2985 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2986 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2987 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2988 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2989 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2990 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2991 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2992 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2993 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2994 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2995 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2996 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2997 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2998 //===----------------------------------------------------------------------===//
2999 // AVX-512 - Unpack Instructions
3000 //===----------------------------------------------------------------------===//
3002 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3003 PatFrag mem_frag, RegisterClass RC,
3004 X86MemOperand x86memop, string asm,
3006 def rr : AVX512PI<opc, MRMSrcReg,
3007 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3009 (vt (OpNode RC:$src1, RC:$src2)))],
3011 def rm : AVX512PI<opc, MRMSrcMem,
3012 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3014 (vt (OpNode RC:$src1,
3015 (bitconvert (mem_frag addr:$src2)))))],
3019 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3020 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3021 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3022 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3023 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3024 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3025 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3026 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3027 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3028 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3029 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3030 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3032 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3033 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3034 X86MemOperand x86memop> {
3035 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3036 (ins RC:$src1, RC:$src2),
3037 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3038 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3039 IIC_SSE_UNPCK>, EVEX_4V;
3040 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3041 (ins RC:$src1, x86memop:$src2),
3042 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3043 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3044 (bitconvert (memop_frag addr:$src2)))))],
3045 IIC_SSE_UNPCK>, EVEX_4V;
3047 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3048 VR512, memopv16i32, i512mem>, EVEX_V512,
3049 EVEX_CD8<32, CD8VF>;
3050 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3051 VR512, memopv8i64, i512mem>, EVEX_V512,
3052 VEX_W, EVEX_CD8<64, CD8VF>;
3053 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3054 VR512, memopv16i32, i512mem>, EVEX_V512,
3055 EVEX_CD8<32, CD8VF>;
3056 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3057 VR512, memopv8i64, i512mem>, EVEX_V512,
3058 VEX_W, EVEX_CD8<64, CD8VF>;
3059 //===----------------------------------------------------------------------===//
3063 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3064 SDNode OpNode, PatFrag mem_frag,
3065 X86MemOperand x86memop, ValueType OpVT> {
3066 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3067 (ins RC:$src1, i8imm:$src2),
3068 !strconcat(OpcodeStr,
3069 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3071 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3073 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3074 (ins x86memop:$src1, i8imm:$src2),
3075 !strconcat(OpcodeStr,
3076 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3078 (OpVT (OpNode (mem_frag addr:$src1),
3079 (i8 imm:$src2))))]>, EVEX;
3082 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3083 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3085 //===----------------------------------------------------------------------===//
3086 // AVX-512 Logical Instructions
3087 //===----------------------------------------------------------------------===//
3089 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3090 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3091 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3092 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3093 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3094 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3095 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3096 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3098 //===----------------------------------------------------------------------===//
3099 // AVX-512 FP arithmetic
3100 //===----------------------------------------------------------------------===//
3102 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3104 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3105 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3106 EVEX_CD8<32, CD8VT1>;
3107 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3108 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3109 EVEX_CD8<64, CD8VT1>;
3112 let isCommutable = 1 in {
3113 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3114 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3115 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3116 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3118 let isCommutable = 0 in {
3119 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3120 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3123 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3124 X86VectorVTInfo _, bit IsCommutable> {
3125 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3126 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3127 "$src2, $src1", "$src1, $src2",
3128 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3129 let mayLoad = 1 in {
3130 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3131 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3132 "$src2, $src1", "$src1, $src2",
3133 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3134 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3135 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3136 "${src2}"##_.BroadcastStr##", $src1",
3137 "$src1, ${src2}"##_.BroadcastStr,
3138 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3139 (_.ScalarLdFrag addr:$src2))))>,
3144 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3145 bit IsCommutable = 0> {
3146 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3147 IsCommutable>, EVEX_V512, PS,
3148 EVEX_CD8<32, CD8VF>;
3149 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3150 IsCommutable>, EVEX_V512, PD, VEX_W,
3151 EVEX_CD8<64, CD8VF>;
3153 // Define only if AVX512VL feature is present.
3154 let Predicates = [HasVLX] in {
3155 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3156 IsCommutable>, EVEX_V128, PS,
3157 EVEX_CD8<32, CD8VF>;
3158 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3159 IsCommutable>, EVEX_V256, PS,
3160 EVEX_CD8<32, CD8VF>;
3161 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3162 IsCommutable>, EVEX_V128, PD, VEX_W,
3163 EVEX_CD8<64, CD8VF>;
3164 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3165 IsCommutable>, EVEX_V256, PD, VEX_W,
3166 EVEX_CD8<64, CD8VF>;
3170 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3171 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3172 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3173 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3174 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3175 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3177 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3178 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3179 (i16 -1), FROUND_CURRENT)),
3180 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3182 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3183 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3184 (i8 -1), FROUND_CURRENT)),
3185 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3187 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3188 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3189 (i16 -1), FROUND_CURRENT)),
3190 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3192 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3193 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3194 (i8 -1), FROUND_CURRENT)),
3195 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3196 //===----------------------------------------------------------------------===//
3197 // AVX-512 VPTESTM instructions
3198 //===----------------------------------------------------------------------===//
3200 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3201 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3202 SDNode OpNode, ValueType vt> {
3203 def rr : AVX512PI<opc, MRMSrcReg,
3204 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3205 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3206 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3207 SSEPackedInt>, EVEX_4V;
3208 def rm : AVX512PI<opc, MRMSrcMem,
3209 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3210 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3211 [(set KRC:$dst, (OpNode (vt RC:$src1),
3212 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3215 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3216 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3217 EVEX_CD8<32, CD8VF>;
3218 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3219 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3220 EVEX_CD8<64, CD8VF>;
3222 let Predicates = [HasCDI] in {
3223 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3224 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3225 EVEX_CD8<32, CD8VF>;
3226 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3227 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3228 EVEX_CD8<64, CD8VF>;
3231 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3232 (v16i32 VR512:$src2), (i16 -1))),
3233 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3235 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3236 (v8i64 VR512:$src2), (i8 -1))),
3237 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3239 //===----------------------------------------------------------------------===//
3240 // AVX-512 Shift instructions
3241 //===----------------------------------------------------------------------===//
3242 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3243 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3244 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3245 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3246 "$src2, $src1", "$src1, $src2",
3247 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3248 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3249 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3250 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3251 "$src2, $src1", "$src1, $src2",
3252 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3253 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3256 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3257 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3258 // src2 is always 128-bit
3259 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3260 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3261 "$src2, $src1", "$src1, $src2",
3262 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3263 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3264 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3265 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3266 "$src2, $src1", "$src1, $src2",
3267 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3268 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3271 multiclass avx512_varshift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3272 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3273 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3276 multiclass avx512_varshift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3278 defm D : avx512_varshift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3279 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3280 defm Q : avx512_varshift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3281 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3284 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3286 EVEX_V512, EVEX_CD8<32, CD8VF>;
3287 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3288 v8i64_info>, EVEX_V512,
3289 EVEX_CD8<64, CD8VF>, VEX_W;
3291 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3292 v16i32_info>, EVEX_V512,
3293 EVEX_CD8<32, CD8VF>;
3294 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3295 v8i64_info>, EVEX_V512,
3296 EVEX_CD8<64, CD8VF>, VEX_W;
3298 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3300 EVEX_V512, EVEX_CD8<32, CD8VF>;
3301 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3302 v8i64_info>, EVEX_V512,
3303 EVEX_CD8<64, CD8VF>, VEX_W;
3305 defm VPSRL : avx512_varshift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3306 defm VPSLL : avx512_varshift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3307 defm VPSRA : avx512_varshift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3309 //===-------------------------------------------------------------------===//
3310 // Variable Bit Shifts
3311 //===-------------------------------------------------------------------===//
3312 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3313 RegisterClass RC, ValueType vt,
3314 X86MemOperand x86memop, PatFrag mem_frag> {
3315 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3316 (ins RC:$src1, RC:$src2),
3317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3319 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3321 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3322 (ins RC:$src1, x86memop:$src2),
3323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3325 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3329 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3330 i512mem, memopv16i32>, EVEX_V512,
3331 EVEX_CD8<32, CD8VF>;
3332 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3333 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3334 EVEX_CD8<64, CD8VF>;
3335 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3336 i512mem, memopv16i32>, EVEX_V512,
3337 EVEX_CD8<32, CD8VF>;
3338 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3339 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3340 EVEX_CD8<64, CD8VF>;
3341 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3342 i512mem, memopv16i32>, EVEX_V512,
3343 EVEX_CD8<32, CD8VF>;
3344 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3345 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3346 EVEX_CD8<64, CD8VF>;
3348 //===----------------------------------------------------------------------===//
3349 // AVX-512 - MOVDDUP
3350 //===----------------------------------------------------------------------===//
3352 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3353 X86MemOperand x86memop, PatFrag memop_frag> {
3354 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3355 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3356 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3357 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3358 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3360 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3363 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3364 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3365 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3366 (VMOVDDUPZrm addr:$src)>;
3368 //===---------------------------------------------------------------------===//
3369 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3370 //===---------------------------------------------------------------------===//
3371 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3372 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3373 X86MemOperand x86memop> {
3374 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3376 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3378 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3379 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3380 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3383 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3384 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3385 EVEX_CD8<32, CD8VF>;
3386 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3387 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3388 EVEX_CD8<32, CD8VF>;
3390 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3391 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3392 (VMOVSHDUPZrm addr:$src)>;
3393 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3394 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3395 (VMOVSLDUPZrm addr:$src)>;
3397 //===----------------------------------------------------------------------===//
3398 // Move Low to High and High to Low packed FP Instructions
3399 //===----------------------------------------------------------------------===//
3400 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3401 (ins VR128X:$src1, VR128X:$src2),
3402 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3403 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3404 IIC_SSE_MOV_LH>, EVEX_4V;
3405 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3406 (ins VR128X:$src1, VR128X:$src2),
3407 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3408 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3409 IIC_SSE_MOV_LH>, EVEX_4V;
3411 let Predicates = [HasAVX512] in {
3413 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3414 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3415 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3416 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3419 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3420 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3423 //===----------------------------------------------------------------------===//
3424 // FMA - Fused Multiply Operations
3427 let Constraints = "$src1 = $dst" in {
3428 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3429 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3430 SDPatternOperator OpNode = null_frag> {
3431 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3432 (ins _.RC:$src2, _.RC:$src3),
3433 OpcodeStr, "$src3, $src2", "$src2, $src3",
3434 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3438 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3439 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
3440 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3441 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3442 (_.MemOpFrag addr:$src3))))]>;
3443 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3444 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3445 !strconcat(OpcodeStr, "\t{${src3}", _.BroadcastStr,
3446 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3447 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3448 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
3450 } // Constraints = "$src1 = $dst"
3452 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3453 string OpcodeStr, X86VectorVTInfo VTI,
3454 SDPatternOperator OpNode> {
3455 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3457 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3459 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3461 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
3464 let ExeDomain = SSEPackedSingle in {
3465 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3466 v16f32_info, X86Fmadd>;
3467 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3468 v16f32_info, X86Fmsub>;
3469 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3470 v16f32_info, X86Fmaddsub>;
3471 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3472 v16f32_info, X86Fmsubadd>;
3473 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3474 v16f32_info, X86Fnmadd>;
3475 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3476 v16f32_info, X86Fnmsub>;
3478 let ExeDomain = SSEPackedDouble in {
3479 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
3480 v8f64_info, X86Fmadd>, VEX_W;
3481 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
3482 v8f64_info, X86Fmsub>, VEX_W;
3483 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
3484 v8f64_info, X86Fmaddsub>, VEX_W;
3485 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
3486 v8f64_info, X86Fmsubadd>, VEX_W;
3487 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
3488 v8f64_info, X86Fnmadd>, VEX_W;
3489 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
3490 v8f64_info, X86Fnmsub>, VEX_W;
3493 let Constraints = "$src1 = $dst" in {
3494 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3495 X86VectorVTInfo _> {
3497 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3498 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3499 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3500 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3502 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3503 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3504 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3505 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3507 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3508 (_.ScalarLdFrag addr:$src2))),
3509 _.RC:$src3))]>, EVEX_B;
3511 } // Constraints = "$src1 = $dst"
3514 let ExeDomain = SSEPackedSingle in {
3515 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3517 EVEX_V512, EVEX_CD8<32, CD8VF>;
3518 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3520 EVEX_V512, EVEX_CD8<32, CD8VF>;
3521 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3523 EVEX_V512, EVEX_CD8<32, CD8VF>;
3524 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3526 EVEX_V512, EVEX_CD8<32, CD8VF>;
3527 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3529 EVEX_V512, EVEX_CD8<32, CD8VF>;
3530 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3532 EVEX_V512, EVEX_CD8<32, CD8VF>;
3534 let ExeDomain = SSEPackedDouble in {
3535 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3537 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3538 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3540 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3541 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3543 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3544 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3546 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3547 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3549 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3550 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3552 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3556 let Constraints = "$src1 = $dst" in {
3557 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3558 RegisterClass RC, ValueType OpVT,
3559 X86MemOperand x86memop, Operand memop,
3561 let isCommutable = 1 in
3562 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3563 (ins RC:$src1, RC:$src2, RC:$src3),
3564 !strconcat(OpcodeStr,
3565 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3567 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3569 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3570 (ins RC:$src1, RC:$src2, f128mem:$src3),
3571 !strconcat(OpcodeStr,
3572 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3574 (OpVT (OpNode RC:$src2, RC:$src1,
3575 (mem_frag addr:$src3))))]>;
3578 } // Constraints = "$src1 = $dst"
3580 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3581 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3582 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3583 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3584 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3585 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3586 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3587 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3588 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3589 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3590 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3591 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3592 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3593 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3594 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3595 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3597 //===----------------------------------------------------------------------===//
3598 // AVX-512 Scalar convert from sign integer to float/double
3599 //===----------------------------------------------------------------------===//
3601 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3602 X86MemOperand x86memop, string asm> {
3603 let hasSideEffects = 0 in {
3604 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3605 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3608 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3609 (ins DstRC:$src1, x86memop:$src),
3610 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3612 } // hasSideEffects = 0
3614 let Predicates = [HasAVX512] in {
3615 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3616 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3617 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3618 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3619 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3620 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3621 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3622 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3624 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3625 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3626 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3627 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3628 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3629 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3630 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3631 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3633 def : Pat<(f32 (sint_to_fp GR32:$src)),
3634 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3635 def : Pat<(f32 (sint_to_fp GR64:$src)),
3636 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3637 def : Pat<(f64 (sint_to_fp GR32:$src)),
3638 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3639 def : Pat<(f64 (sint_to_fp GR64:$src)),
3640 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3642 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3643 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3644 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3645 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3646 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3647 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3648 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3649 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3651 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3652 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3653 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3654 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3655 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3656 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3657 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3658 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3660 def : Pat<(f32 (uint_to_fp GR32:$src)),
3661 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3662 def : Pat<(f32 (uint_to_fp GR64:$src)),
3663 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3664 def : Pat<(f64 (uint_to_fp GR32:$src)),
3665 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3666 def : Pat<(f64 (uint_to_fp GR64:$src)),
3667 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3670 //===----------------------------------------------------------------------===//
3671 // AVX-512 Scalar convert from float/double to integer
3672 //===----------------------------------------------------------------------===//
3673 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3674 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3676 let hasSideEffects = 0 in {
3677 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3678 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3679 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3680 Requires<[HasAVX512]>;
3682 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3683 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3684 Requires<[HasAVX512]>;
3685 } // hasSideEffects = 0
3687 let Predicates = [HasAVX512] in {
3688 // Convert float/double to signed/unsigned int 32/64
3689 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3690 ssmem, sse_load_f32, "cvtss2si">,
3691 XS, EVEX_CD8<32, CD8VT1>;
3692 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3693 ssmem, sse_load_f32, "cvtss2si">,
3694 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3695 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3696 ssmem, sse_load_f32, "cvtss2usi">,
3697 XS, EVEX_CD8<32, CD8VT1>;
3698 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3699 int_x86_avx512_cvtss2usi64, ssmem,
3700 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3701 EVEX_CD8<32, CD8VT1>;
3702 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3703 sdmem, sse_load_f64, "cvtsd2si">,
3704 XD, EVEX_CD8<64, CD8VT1>;
3705 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3706 sdmem, sse_load_f64, "cvtsd2si">,
3707 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3708 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3709 sdmem, sse_load_f64, "cvtsd2usi">,
3710 XD, EVEX_CD8<64, CD8VT1>;
3711 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3712 int_x86_avx512_cvtsd2usi64, sdmem,
3713 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3714 EVEX_CD8<64, CD8VT1>;
3716 let isCodeGenOnly = 1 in {
3717 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3718 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3719 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3720 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3721 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3722 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3723 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3724 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3725 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3726 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3727 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3728 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3730 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3731 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3732 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3733 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3734 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3735 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3736 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3737 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3738 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3739 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3740 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3741 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3742 } // isCodeGenOnly = 1
3744 // Convert float/double to signed/unsigned int 32/64 with truncation
3745 let isCodeGenOnly = 1 in {
3746 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3747 ssmem, sse_load_f32, "cvttss2si">,
3748 XS, EVEX_CD8<32, CD8VT1>;
3749 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3750 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3751 "cvttss2si">, XS, VEX_W,
3752 EVEX_CD8<32, CD8VT1>;
3753 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3754 sdmem, sse_load_f64, "cvttsd2si">, XD,
3755 EVEX_CD8<64, CD8VT1>;
3756 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3757 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3758 "cvttsd2si">, XD, VEX_W,
3759 EVEX_CD8<64, CD8VT1>;
3760 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3761 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3762 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3763 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3764 int_x86_avx512_cvttss2usi64, ssmem,
3765 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3766 EVEX_CD8<32, CD8VT1>;
3767 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3768 int_x86_avx512_cvttsd2usi,
3769 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3770 EVEX_CD8<64, CD8VT1>;
3771 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3772 int_x86_avx512_cvttsd2usi64, sdmem,
3773 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3774 EVEX_CD8<64, CD8VT1>;
3775 } // isCodeGenOnly = 1
3777 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3778 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3780 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3781 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3782 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3783 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3784 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3785 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3788 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3789 loadf32, "cvttss2si">, XS,
3790 EVEX_CD8<32, CD8VT1>;
3791 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3792 loadf32, "cvttss2usi">, XS,
3793 EVEX_CD8<32, CD8VT1>;
3794 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3795 loadf32, "cvttss2si">, XS, VEX_W,
3796 EVEX_CD8<32, CD8VT1>;
3797 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3798 loadf32, "cvttss2usi">, XS, VEX_W,
3799 EVEX_CD8<32, CD8VT1>;
3800 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3801 loadf64, "cvttsd2si">, XD,
3802 EVEX_CD8<64, CD8VT1>;
3803 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3804 loadf64, "cvttsd2usi">, XD,
3805 EVEX_CD8<64, CD8VT1>;
3806 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3807 loadf64, "cvttsd2si">, XD, VEX_W,
3808 EVEX_CD8<64, CD8VT1>;
3809 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3810 loadf64, "cvttsd2usi">, XD, VEX_W,
3811 EVEX_CD8<64, CD8VT1>;
3813 //===----------------------------------------------------------------------===//
3814 // AVX-512 Convert form float to double and back
3815 //===----------------------------------------------------------------------===//
3816 let hasSideEffects = 0 in {
3817 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3818 (ins FR32X:$src1, FR32X:$src2),
3819 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3820 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3822 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3823 (ins FR32X:$src1, f32mem:$src2),
3824 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3825 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3826 EVEX_CD8<32, CD8VT1>;
3828 // Convert scalar double to scalar single
3829 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3830 (ins FR64X:$src1, FR64X:$src2),
3831 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3832 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3834 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3835 (ins FR64X:$src1, f64mem:$src2),
3836 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3837 []>, EVEX_4V, VEX_LIG, VEX_W,
3838 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3841 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3842 Requires<[HasAVX512]>;
3843 def : Pat<(fextend (loadf32 addr:$src)),
3844 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3846 def : Pat<(extloadf32 addr:$src),
3847 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3848 Requires<[HasAVX512, OptForSize]>;
3850 def : Pat<(extloadf32 addr:$src),
3851 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3852 Requires<[HasAVX512, OptForSpeed]>;
3854 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3855 Requires<[HasAVX512]>;
3857 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3858 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3859 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3861 let hasSideEffects = 0 in {
3862 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3863 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3865 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3866 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3867 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3868 [], d>, EVEX, EVEX_B, EVEX_RC;
3870 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3871 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3873 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3874 } // hasSideEffects = 0
3877 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3878 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3879 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3881 let hasSideEffects = 0 in {
3882 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3883 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3885 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3887 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3888 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3890 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3891 } // hasSideEffects = 0
3894 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3895 memopv8f64, f512mem, v8f32, v8f64,
3896 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3897 EVEX_CD8<64, CD8VF>;
3899 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3900 memopv4f64, f256mem, v8f64, v8f32,
3901 SSEPackedDouble>, EVEX_V512, PS,
3902 EVEX_CD8<32, CD8VH>;
3903 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3904 (VCVTPS2PDZrm addr:$src)>;
3906 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3907 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3908 (VCVTPD2PSZrr VR512:$src)>;
3910 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3911 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3912 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3914 //===----------------------------------------------------------------------===//
3915 // AVX-512 Vector convert from sign integer to float/double
3916 //===----------------------------------------------------------------------===//
3918 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3919 memopv8i64, i512mem, v16f32, v16i32,
3920 SSEPackedSingle>, EVEX_V512, PS,
3921 EVEX_CD8<32, CD8VF>;
3923 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3924 memopv4i64, i256mem, v8f64, v8i32,
3925 SSEPackedDouble>, EVEX_V512, XS,
3926 EVEX_CD8<32, CD8VH>;
3928 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3929 memopv16f32, f512mem, v16i32, v16f32,
3930 SSEPackedSingle>, EVEX_V512, XS,
3931 EVEX_CD8<32, CD8VF>;
3933 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3934 memopv8f64, f512mem, v8i32, v8f64,
3935 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3936 EVEX_CD8<64, CD8VF>;
3938 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3939 memopv16f32, f512mem, v16i32, v16f32,
3940 SSEPackedSingle>, EVEX_V512, PS,
3941 EVEX_CD8<32, CD8VF>;
3943 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3944 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3945 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3946 (VCVTTPS2UDQZrr VR512:$src)>;
3948 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3949 memopv8f64, f512mem, v8i32, v8f64,
3950 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3951 EVEX_CD8<64, CD8VF>;
3953 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3954 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3955 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3956 (VCVTTPD2UDQZrr VR512:$src)>;
3958 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3959 memopv4i64, f256mem, v8f64, v8i32,
3960 SSEPackedDouble>, EVEX_V512, XS,
3961 EVEX_CD8<32, CD8VH>;
3963 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3964 memopv16i32, f512mem, v16f32, v16i32,
3965 SSEPackedSingle>, EVEX_V512, XD,
3966 EVEX_CD8<32, CD8VF>;
3968 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3969 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3970 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3972 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3973 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3974 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3976 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3977 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3978 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3980 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3981 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3982 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3984 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3985 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3986 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3988 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3989 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3990 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3991 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3992 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3993 (VCVTDQ2PDZrr VR256X:$src)>;
3994 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3995 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3996 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3997 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3998 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3999 (VCVTUDQ2PDZrr VR256X:$src)>;
4001 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4002 RegisterClass DstRC, PatFrag mem_frag,
4003 X86MemOperand x86memop, Domain d> {
4004 let hasSideEffects = 0 in {
4005 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4006 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4008 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4009 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4010 [], d>, EVEX, EVEX_B, EVEX_RC;
4012 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4013 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4015 } // hasSideEffects = 0
4018 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4019 memopv16f32, f512mem, SSEPackedSingle>, PD,
4020 EVEX_V512, EVEX_CD8<32, CD8VF>;
4021 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4022 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4023 EVEX_V512, EVEX_CD8<64, CD8VF>;
4025 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4026 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4027 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4029 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4030 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4031 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4033 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4034 memopv16f32, f512mem, SSEPackedSingle>,
4035 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4036 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4037 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4038 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4040 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4041 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4042 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4044 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4045 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4046 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4048 let Predicates = [HasAVX512] in {
4049 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4050 (VCVTPD2PSZrm addr:$src)>;
4051 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4052 (VCVTPS2PDZrm addr:$src)>;
4055 //===----------------------------------------------------------------------===//
4056 // Half precision conversion instructions
4057 //===----------------------------------------------------------------------===//
4058 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4059 X86MemOperand x86memop> {
4060 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4061 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4063 let hasSideEffects = 0, mayLoad = 1 in
4064 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4065 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4068 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4069 X86MemOperand x86memop> {
4070 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4071 (ins srcRC:$src1, i32i8imm:$src2),
4072 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4074 let hasSideEffects = 0, mayStore = 1 in
4075 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4076 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
4077 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4080 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4081 EVEX_CD8<32, CD8VH>;
4082 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4083 EVEX_CD8<32, CD8VH>;
4085 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4086 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4087 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4089 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4090 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4091 (VCVTPH2PSZrr VR256X:$src)>;
4093 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4094 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4095 "ucomiss">, PS, EVEX, VEX_LIG,
4096 EVEX_CD8<32, CD8VT1>;
4097 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4098 "ucomisd">, PD, EVEX,
4099 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4100 let Pattern = []<dag> in {
4101 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4102 "comiss">, PS, EVEX, VEX_LIG,
4103 EVEX_CD8<32, CD8VT1>;
4104 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4105 "comisd">, PD, EVEX,
4106 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4108 let isCodeGenOnly = 1 in {
4109 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4110 load, "ucomiss">, PS, EVEX, VEX_LIG,
4111 EVEX_CD8<32, CD8VT1>;
4112 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4113 load, "ucomisd">, PD, EVEX,
4114 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4116 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4117 load, "comiss">, PS, EVEX, VEX_LIG,
4118 EVEX_CD8<32, CD8VT1>;
4119 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4120 load, "comisd">, PD, EVEX,
4121 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4125 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4126 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4127 X86MemOperand x86memop> {
4128 let hasSideEffects = 0 in {
4129 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4130 (ins RC:$src1, RC:$src2),
4131 !strconcat(OpcodeStr,
4132 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4133 let mayLoad = 1 in {
4134 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4135 (ins RC:$src1, x86memop:$src2),
4136 !strconcat(OpcodeStr,
4137 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4142 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4143 EVEX_CD8<32, CD8VT1>;
4144 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4145 VEX_W, EVEX_CD8<64, CD8VT1>;
4146 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4147 EVEX_CD8<32, CD8VT1>;
4148 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4149 VEX_W, EVEX_CD8<64, CD8VT1>;
4151 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4152 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4153 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4154 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4156 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4157 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4158 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4159 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4161 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4162 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4163 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4164 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4166 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4167 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4168 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4169 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4171 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4172 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4173 X86VectorVTInfo _> {
4174 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4175 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4176 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4177 let mayLoad = 1 in {
4178 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4179 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4181 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4182 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4183 (ins _.ScalarMemOp:$src), OpcodeStr,
4184 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4186 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4191 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4192 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4193 EVEX_V512, EVEX_CD8<32, CD8VF>;
4194 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4195 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4197 // Define only if AVX512VL feature is present.
4198 let Predicates = [HasVLX] in {
4199 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4200 OpNode, v4f32x_info>,
4201 EVEX_V128, EVEX_CD8<32, CD8VF>;
4202 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4203 OpNode, v8f32x_info>,
4204 EVEX_V256, EVEX_CD8<32, CD8VF>;
4205 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4206 OpNode, v2f64x_info>,
4207 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4208 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4209 OpNode, v4f64x_info>,
4210 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4214 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4215 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4217 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4218 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4219 (VRSQRT14PSZr VR512:$src)>;
4220 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4221 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4222 (VRSQRT14PDZr VR512:$src)>;
4224 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4225 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4226 (VRCP14PSZr VR512:$src)>;
4227 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4228 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4229 (VRCP14PDZr VR512:$src)>;
4231 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4232 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4235 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4236 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4237 "$src2, $src1", "$src1, $src2",
4238 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4239 (i32 FROUND_CURRENT))>;
4241 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4242 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4243 "$src2, $src1", "$src1, $src2",
4244 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4245 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4247 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4248 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4249 "$src2, $src1", "$src1, $src2",
4250 (OpNode (_.VT _.RC:$src1),
4251 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4252 (i32 FROUND_CURRENT))>;
4255 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4256 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4257 EVEX_CD8<32, CD8VT1>;
4258 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4259 EVEX_CD8<64, CD8VT1>, VEX_W;
4262 let hasSideEffects = 0, Predicates = [HasERI] in {
4263 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4264 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4266 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4268 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4271 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4272 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4273 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4275 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4276 (ins _.RC:$src), OpcodeStr,
4278 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4281 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4282 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4284 (bitconvert (_.LdFrag addr:$src))),
4285 (i32 FROUND_CURRENT))>;
4287 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4288 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4290 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4291 (i32 FROUND_CURRENT))>, EVEX_B;
4294 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4295 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4296 EVEX_CD8<32, CD8VF>;
4297 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4298 VEX_W, EVEX_CD8<32, CD8VF>;
4301 let Predicates = [HasERI], hasSideEffects = 0 in {
4303 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4304 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4305 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4308 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4309 SDNode OpNode, X86VectorVTInfo _>{
4310 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4311 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4312 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4313 let mayLoad = 1 in {
4314 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4315 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4317 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4319 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4320 (ins _.ScalarMemOp:$src), OpcodeStr,
4321 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4323 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4328 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4329 Intrinsic F32Int, Intrinsic F64Int,
4330 OpndItins itins_s, OpndItins itins_d> {
4331 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4332 (ins FR32X:$src1, FR32X:$src2),
4333 !strconcat(OpcodeStr,
4334 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4335 [], itins_s.rr>, XS, EVEX_4V;
4336 let isCodeGenOnly = 1 in
4337 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4338 (ins VR128X:$src1, VR128X:$src2),
4339 !strconcat(OpcodeStr,
4340 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4342 (F32Int VR128X:$src1, VR128X:$src2))],
4343 itins_s.rr>, XS, EVEX_4V;
4344 let mayLoad = 1 in {
4345 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4346 (ins FR32X:$src1, f32mem:$src2),
4347 !strconcat(OpcodeStr,
4348 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4349 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4350 let isCodeGenOnly = 1 in
4351 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4352 (ins VR128X:$src1, ssmem:$src2),
4353 !strconcat(OpcodeStr,
4354 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4356 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4357 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4359 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4360 (ins FR64X:$src1, FR64X:$src2),
4361 !strconcat(OpcodeStr,
4362 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4364 let isCodeGenOnly = 1 in
4365 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4366 (ins VR128X:$src1, VR128X:$src2),
4367 !strconcat(OpcodeStr,
4368 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4370 (F64Int VR128X:$src1, VR128X:$src2))],
4371 itins_s.rr>, XD, EVEX_4V, VEX_W;
4372 let mayLoad = 1 in {
4373 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4374 (ins FR64X:$src1, f64mem:$src2),
4375 !strconcat(OpcodeStr,
4376 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4377 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4378 let isCodeGenOnly = 1 in
4379 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4380 (ins VR128X:$src1, sdmem:$src2),
4381 !strconcat(OpcodeStr,
4382 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4384 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4385 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4389 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4391 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4393 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4394 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4396 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4397 // Define only if AVX512VL feature is present.
4398 let Predicates = [HasVLX] in {
4399 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4400 OpNode, v4f32x_info>,
4401 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4402 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4403 OpNode, v8f32x_info>,
4404 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4405 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4406 OpNode, v2f64x_info>,
4407 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4408 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4409 OpNode, v4f64x_info>,
4410 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4414 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4416 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4417 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4418 SSE_SQRTSS, SSE_SQRTSD>;
4420 let Predicates = [HasAVX512] in {
4421 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4422 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4423 (VSQRTPSZr VR512:$src1)>;
4424 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4425 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4426 (VSQRTPDZr VR512:$src1)>;
4428 def : Pat<(f32 (fsqrt FR32X:$src)),
4429 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4430 def : Pat<(f32 (fsqrt (load addr:$src))),
4431 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4432 Requires<[OptForSize]>;
4433 def : Pat<(f64 (fsqrt FR64X:$src)),
4434 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4435 def : Pat<(f64 (fsqrt (load addr:$src))),
4436 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4437 Requires<[OptForSize]>;
4439 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4440 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4441 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4442 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4443 Requires<[OptForSize]>;
4445 def : Pat<(f32 (X86frcp FR32X:$src)),
4446 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4447 def : Pat<(f32 (X86frcp (load addr:$src))),
4448 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4449 Requires<[OptForSize]>;
4451 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4452 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4453 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4455 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4456 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4458 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4459 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4460 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4462 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4463 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4467 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4468 X86MemOperand x86memop, RegisterClass RC,
4469 PatFrag mem_frag32, PatFrag mem_frag64,
4470 Intrinsic V4F32Int, Intrinsic V2F64Int,
4472 let ExeDomain = SSEPackedSingle in {
4473 // Intrinsic operation, reg.
4474 // Vector intrinsic operation, reg
4475 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4476 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4477 !strconcat(OpcodeStr,
4478 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4479 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4481 // Vector intrinsic operation, mem
4482 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4483 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4484 !strconcat(OpcodeStr,
4485 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4487 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4488 EVEX_CD8<32, VForm>;
4489 } // ExeDomain = SSEPackedSingle
4491 let ExeDomain = SSEPackedDouble in {
4492 // Vector intrinsic operation, reg
4493 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4494 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4495 !strconcat(OpcodeStr,
4496 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4497 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4499 // Vector intrinsic operation, mem
4500 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4501 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4502 !strconcat(OpcodeStr,
4503 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4505 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4506 EVEX_CD8<64, VForm>;
4507 } // ExeDomain = SSEPackedDouble
4510 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4514 let ExeDomain = GenericDomain in {
4516 let hasSideEffects = 0 in
4517 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4518 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4519 !strconcat(OpcodeStr,
4520 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4523 // Intrinsic operation, reg.
4524 let isCodeGenOnly = 1 in
4525 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4526 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4527 !strconcat(OpcodeStr,
4528 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4529 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4531 // Intrinsic operation, mem.
4532 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4533 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4534 !strconcat(OpcodeStr,
4535 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4536 [(set VR128X:$dst, (F32Int VR128X:$src1,
4537 sse_load_f32:$src2, imm:$src3))]>,
4538 EVEX_CD8<32, CD8VT1>;
4541 let hasSideEffects = 0 in
4542 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4543 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4544 !strconcat(OpcodeStr,
4545 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4548 // Intrinsic operation, reg.
4549 let isCodeGenOnly = 1 in
4550 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4551 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4552 !strconcat(OpcodeStr,
4553 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4554 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4557 // Intrinsic operation, mem.
4558 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4559 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4560 !strconcat(OpcodeStr,
4561 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4563 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4564 VEX_W, EVEX_CD8<64, CD8VT1>;
4565 } // ExeDomain = GenericDomain
4568 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4569 X86MemOperand x86memop, RegisterClass RC,
4570 PatFrag mem_frag, Domain d> {
4571 let ExeDomain = d in {
4572 // Intrinsic operation, reg.
4573 // Vector intrinsic operation, reg
4574 def r : AVX512AIi8<opc, MRMSrcReg,
4575 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4576 !strconcat(OpcodeStr,
4577 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4580 // Vector intrinsic operation, mem
4581 def m : AVX512AIi8<opc, MRMSrcMem,
4582 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4583 !strconcat(OpcodeStr,
4584 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4590 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4591 memopv16f32, SSEPackedSingle>, EVEX_V512,
4592 EVEX_CD8<32, CD8VF>;
4594 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4595 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4597 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4600 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4601 memopv8f64, SSEPackedDouble>, EVEX_V512,
4602 VEX_W, EVEX_CD8<64, CD8VF>;
4604 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4605 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4607 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4609 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4610 Operand x86memop, RegisterClass RC, Domain d> {
4611 let ExeDomain = d in {
4612 def r : AVX512AIi8<opc, MRMSrcReg,
4613 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4614 !strconcat(OpcodeStr,
4615 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4618 def m : AVX512AIi8<opc, MRMSrcMem,
4619 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4620 !strconcat(OpcodeStr,
4621 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4626 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4627 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4629 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4630 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4632 def : Pat<(ffloor FR32X:$src),
4633 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4634 def : Pat<(f64 (ffloor FR64X:$src)),
4635 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4636 def : Pat<(f32 (fnearbyint FR32X:$src)),
4637 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4638 def : Pat<(f64 (fnearbyint FR64X:$src)),
4639 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4640 def : Pat<(f32 (fceil FR32X:$src)),
4641 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4642 def : Pat<(f64 (fceil FR64X:$src)),
4643 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4644 def : Pat<(f32 (frint FR32X:$src)),
4645 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4646 def : Pat<(f64 (frint FR64X:$src)),
4647 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4648 def : Pat<(f32 (ftrunc FR32X:$src)),
4649 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4650 def : Pat<(f64 (ftrunc FR64X:$src)),
4651 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4653 def : Pat<(v16f32 (ffloor VR512:$src)),
4654 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4655 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4656 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4657 def : Pat<(v16f32 (fceil VR512:$src)),
4658 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4659 def : Pat<(v16f32 (frint VR512:$src)),
4660 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4661 def : Pat<(v16f32 (ftrunc VR512:$src)),
4662 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4664 def : Pat<(v8f64 (ffloor VR512:$src)),
4665 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4666 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4667 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4668 def : Pat<(v8f64 (fceil VR512:$src)),
4669 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4670 def : Pat<(v8f64 (frint VR512:$src)),
4671 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4672 def : Pat<(v8f64 (ftrunc VR512:$src)),
4673 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4675 //-------------------------------------------------
4676 // Integer truncate and extend operations
4677 //-------------------------------------------------
4679 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4680 RegisterClass dstRC, RegisterClass srcRC,
4681 RegisterClass KRC, X86MemOperand x86memop> {
4682 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4684 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4687 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4688 (ins KRC:$mask, srcRC:$src),
4689 !strconcat(OpcodeStr,
4690 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4693 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4694 (ins KRC:$mask, srcRC:$src),
4695 !strconcat(OpcodeStr,
4696 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4699 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4700 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4703 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4704 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4705 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4709 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4710 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4711 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4712 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4713 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4714 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4715 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4716 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4717 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4718 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4719 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4720 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4721 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4722 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4723 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4724 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4725 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4726 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4727 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4728 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4729 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4730 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4731 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4732 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4733 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4734 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4735 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4736 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4737 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4738 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4740 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4741 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4742 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4743 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4744 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4746 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4747 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4748 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4749 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4750 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4751 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4752 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4753 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4756 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4757 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4758 PatFrag mem_frag, X86MemOperand x86memop,
4759 ValueType OpVT, ValueType InVT> {
4761 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4763 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4764 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4766 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4767 (ins KRC:$mask, SrcRC:$src),
4768 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4771 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4772 (ins KRC:$mask, SrcRC:$src),
4773 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4776 let mayLoad = 1 in {
4777 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4778 (ins x86memop:$src),
4779 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4781 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4784 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4785 (ins KRC:$mask, x86memop:$src),
4786 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4790 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4791 (ins KRC:$mask, x86memop:$src),
4792 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4798 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4799 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4801 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4802 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4804 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4805 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4806 EVEX_CD8<16, CD8VH>;
4807 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4808 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4809 EVEX_CD8<16, CD8VQ>;
4810 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4811 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4812 EVEX_CD8<32, CD8VH>;
4814 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4815 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4817 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4818 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4820 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4821 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4822 EVEX_CD8<16, CD8VH>;
4823 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4824 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4825 EVEX_CD8<16, CD8VQ>;
4826 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4827 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4828 EVEX_CD8<32, CD8VH>;
4830 //===----------------------------------------------------------------------===//
4831 // GATHER - SCATTER Operations
4833 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4834 RegisterClass RC, X86MemOperand memop> {
4836 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4837 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4838 (ins RC:$src1, KRC:$mask, memop:$src2),
4839 !strconcat(OpcodeStr,
4840 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4844 let ExeDomain = SSEPackedDouble in {
4845 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4846 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4847 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4848 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4851 let ExeDomain = SSEPackedSingle in {
4852 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4853 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4854 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4855 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4858 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4859 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4860 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4861 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4863 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4864 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4865 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4866 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4868 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4869 RegisterClass RC, X86MemOperand memop> {
4870 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4871 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4872 (ins memop:$dst, KRC:$mask, RC:$src2),
4873 !strconcat(OpcodeStr,
4874 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4878 let ExeDomain = SSEPackedDouble in {
4879 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4880 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4881 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4882 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4885 let ExeDomain = SSEPackedSingle in {
4886 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4887 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4888 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4889 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4892 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4893 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4894 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4895 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4897 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4898 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4899 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4900 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4903 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4904 RegisterClass KRC, X86MemOperand memop> {
4905 let Predicates = [HasPFI], hasSideEffects = 1 in
4906 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4907 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4911 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4912 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4914 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4915 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4917 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4918 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4920 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4921 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4923 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4924 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4926 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4927 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4929 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4930 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4932 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4933 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4935 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4936 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4938 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4939 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4941 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4942 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4944 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4945 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4947 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4948 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4950 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4951 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4953 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4954 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4956 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4957 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4958 //===----------------------------------------------------------------------===//
4959 // VSHUFPS - VSHUFPD Operations
4961 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4962 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4964 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4965 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4966 !strconcat(OpcodeStr,
4967 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4968 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4969 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4970 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4971 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4972 (ins RC:$src1, RC:$src2, i8imm:$src3),
4973 !strconcat(OpcodeStr,
4974 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4975 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4976 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4977 EVEX_4V, Sched<[WriteShuffle]>;
4980 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4981 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4982 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4983 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4985 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4986 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4987 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4988 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4989 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4991 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4992 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4993 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4994 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4995 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4997 multiclass avx512_valign<X86VectorVTInfo _> {
4998 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
4999 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
5001 "$src3, $src2, $src1", "$src1, $src2, $src3",
5002 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5004 AVX512AIi8Base, EVEX_4V;
5006 // Also match valign of packed floats.
5007 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5008 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5011 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5012 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
5013 !strconcat("valign"##_.Suffix,
5014 "\t{$src3, $src2, $src1, $dst|"
5015 "$dst, $src1, $src2, $src3}"),
5018 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5019 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5021 // Helper fragments to match sext vXi1 to vXiY.
5022 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5023 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5025 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5026 RegisterClass KRC, RegisterClass RC,
5027 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5029 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5030 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5032 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5033 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5035 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5036 !strconcat(OpcodeStr,
5037 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5039 let mayLoad = 1 in {
5040 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5041 (ins x86memop:$src),
5042 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5044 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5045 (ins KRC:$mask, x86memop:$src),
5046 !strconcat(OpcodeStr,
5047 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5049 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5050 (ins KRC:$mask, x86memop:$src),
5051 !strconcat(OpcodeStr,
5052 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5054 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5055 (ins x86scalar_mop:$src),
5056 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5057 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5059 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5060 (ins KRC:$mask, x86scalar_mop:$src),
5061 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5062 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5063 []>, EVEX, EVEX_B, EVEX_K;
5064 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5065 (ins KRC:$mask, x86scalar_mop:$src),
5066 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5067 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5069 []>, EVEX, EVEX_B, EVEX_KZ;
5073 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5074 i512mem, i32mem, "{1to16}">, EVEX_V512,
5075 EVEX_CD8<32, CD8VF>;
5076 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5077 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5078 EVEX_CD8<64, CD8VF>;
5081 (bc_v16i32 (v16i1sextv16i32)),
5082 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5083 (VPABSDZrr VR512:$src)>;
5085 (bc_v8i64 (v8i1sextv8i64)),
5086 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5087 (VPABSQZrr VR512:$src)>;
5089 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5090 (v16i32 immAllZerosV), (i16 -1))),
5091 (VPABSDZrr VR512:$src)>;
5092 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5093 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5094 (VPABSQZrr VR512:$src)>;
5096 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5097 RegisterClass RC, RegisterClass KRC,
5098 X86MemOperand x86memop,
5099 X86MemOperand x86scalar_mop, string BrdcstStr> {
5100 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5102 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5104 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5105 (ins x86memop:$src),
5106 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5108 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5109 (ins x86scalar_mop:$src),
5110 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5111 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5113 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5114 (ins KRC:$mask, RC:$src),
5115 !strconcat(OpcodeStr,
5116 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5118 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5119 (ins KRC:$mask, x86memop:$src),
5120 !strconcat(OpcodeStr,
5121 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5123 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5124 (ins KRC:$mask, x86scalar_mop:$src),
5125 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5126 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5128 []>, EVEX, EVEX_KZ, EVEX_B;
5130 let Constraints = "$src1 = $dst" in {
5131 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5132 (ins RC:$src1, KRC:$mask, RC:$src2),
5133 !strconcat(OpcodeStr,
5134 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5136 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5137 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5138 !strconcat(OpcodeStr,
5139 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5141 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5142 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5143 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5144 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5145 []>, EVEX, EVEX_K, EVEX_B;
5149 let Predicates = [HasCDI] in {
5150 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5151 i512mem, i32mem, "{1to16}">,
5152 EVEX_V512, EVEX_CD8<32, CD8VF>;
5155 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5156 i512mem, i64mem, "{1to8}">,
5157 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5161 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5163 (VPCONFLICTDrrk VR512:$src1,
5164 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5166 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5168 (VPCONFLICTQrrk VR512:$src1,
5169 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5171 let Predicates = [HasCDI] in {
5172 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5173 i512mem, i32mem, "{1to16}">,
5174 EVEX_V512, EVEX_CD8<32, CD8VF>;
5177 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5178 i512mem, i64mem, "{1to8}">,
5179 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5183 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5185 (VPLZCNTDrrk VR512:$src1,
5186 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5188 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5190 (VPLZCNTQrrk VR512:$src1,
5191 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5193 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5194 (VPLZCNTDrm addr:$src)>;
5195 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5196 (VPLZCNTDrr VR512:$src)>;
5197 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5198 (VPLZCNTQrm addr:$src)>;
5199 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5200 (VPLZCNTQrr VR512:$src)>;
5202 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5203 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5204 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5206 def : Pat<(store VK1:$src, addr:$dst),
5207 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5209 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5210 (truncstore node:$val, node:$ptr), [{
5211 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5214 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5215 (MOV8mr addr:$dst, GR8:$src)>;
5217 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5218 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5219 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5220 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5223 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5224 string OpcodeStr, Predicate prd> {
5225 let Predicates = [prd] in
5226 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5228 let Predicates = [prd, HasVLX] in {
5229 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5230 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5234 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5235 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5237 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5239 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5241 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5245 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;