1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
621 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
622 (ins KRC:$mask, RC:$src1, RC:$src2),
623 !strconcat(OpcodeStr,
624 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
625 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
626 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
629 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
630 (ins KRC:$mask, RC:$src1, x86memop:$src2),
631 !strconcat(OpcodeStr,
632 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
636 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
637 (ins KRC:$mask, RC:$src1, x86memop:$src2),
638 !strconcat(OpcodeStr,
639 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
640 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
641 (mem_frag addr:$src2)))]>,
646 let ExeDomain = SSEPackedSingle in
647 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
648 int_x86_avx512_mask_blend_ps_512,
649 VK16WM, VR512, f512mem,
650 memopv16f32, vselect, v16f32>,
651 EVEX_CD8<32, CD8VF>, EVEX_V512;
652 let ExeDomain = SSEPackedDouble in
653 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
654 int_x86_avx512_mask_blend_pd_512,
655 VK8WM, VR512, f512mem,
656 memopv8f64, vselect, v8f64>,
657 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
659 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
660 int_x86_avx512_mask_blend_d_512,
661 VK16WM, VR512, f512mem,
662 memopv16i32, vselect, v16i32>,
663 EVEX_CD8<32, CD8VF>, EVEX_V512;
665 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
666 int_x86_avx512_mask_blend_q_512,
667 VK8WM, VR512, f512mem,
668 memopv8i64, vselect, v8i64>,
669 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
671 let Predicates = [HasAVX512] in {
672 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
673 (v8f32 VR256X:$src2))),
675 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
676 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
677 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
679 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
680 (v8i32 VR256X:$src2))),
682 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
686 //===----------------------------------------------------------------------===//
687 // Compare Instructions
688 //===----------------------------------------------------------------------===//
690 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
691 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
692 Operand CC, SDNode OpNode, ValueType VT,
693 PatFrag ld_frag, string asm, string asm_alt> {
694 def rr : AVX512Ii8<0xC2, MRMSrcReg,
695 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
696 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
697 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
698 def rm : AVX512Ii8<0xC2, MRMSrcMem,
699 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
700 [(set VK1:$dst, (OpNode (VT RC:$src1),
701 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
702 let neverHasSideEffects = 1 in {
703 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
704 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
705 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
706 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
707 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
708 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
712 let Predicates = [HasAVX512] in {
713 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
714 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
717 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
718 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
719 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
723 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
724 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
725 SDNode OpNode, ValueType vt> {
726 def rr : AVX512BI<opc, MRMSrcReg,
727 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
728 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
729 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
730 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
731 def rm : AVX512BI<opc, MRMSrcMem,
732 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
733 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
734 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
735 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
738 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
739 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
740 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
741 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
743 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
744 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
745 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
746 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
748 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
749 (COPY_TO_REGCLASS (VPCMPGTDZrr
750 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
751 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
753 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
754 (COPY_TO_REGCLASS (VPCMPEQDZrr
755 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
756 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
758 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
759 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
760 SDNode OpNode, ValueType vt, Operand CC, string asm,
762 def rri : AVX512AIi8<opc, MRMSrcReg,
763 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
764 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
765 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
766 def rmi : AVX512AIi8<opc, MRMSrcMem,
767 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
768 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
769 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
770 // Accept explicit immediate argument form instead of comparison code.
771 let neverHasSideEffects = 1 in {
772 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
773 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
774 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
775 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
776 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
777 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
781 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
782 X86cmpm, v16i32, AVXCC,
783 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
784 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
785 EVEX_V512, EVEX_CD8<32, CD8VF>;
786 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
787 X86cmpmu, v16i32, AVXCC,
788 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
789 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
790 EVEX_V512, EVEX_CD8<32, CD8VF>;
792 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
793 X86cmpm, v8i64, AVXCC,
794 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
795 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
796 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
797 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
798 X86cmpmu, v8i64, AVXCC,
799 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
800 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
801 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
803 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
804 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
805 X86MemOperand x86memop, Operand CC,
806 SDNode OpNode, ValueType vt, string asm,
807 string asm_alt, Domain d> {
808 def rri : AVX512PIi8<0xC2, MRMSrcReg,
809 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
810 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
811 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
812 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
814 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
816 // Accept explicit immediate argument form instead of comparison code.
817 let neverHasSideEffects = 1 in {
818 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
819 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
821 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
822 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
827 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
828 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
829 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
830 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
831 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
832 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
833 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
834 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
837 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
838 (COPY_TO_REGCLASS (VCMPPSZrri
839 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
840 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
842 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
843 (COPY_TO_REGCLASS (VPCMPDZrri
844 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
845 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
847 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
848 (COPY_TO_REGCLASS (VPCMPUDZrri
849 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
850 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
853 // Mask register copy, including
854 // - copy between mask registers
855 // - load/store mask registers
856 // - copy from GPR to mask register and vice versa
858 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
859 string OpcodeStr, RegisterClass KRC,
860 ValueType vt, X86MemOperand x86memop> {
861 let neverHasSideEffects = 1 in {
862 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
863 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
865 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
866 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
867 [(set KRC:$dst, (vt (load addr:$src)))]>;
869 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
870 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
874 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
876 RegisterClass KRC, RegisterClass GRC> {
877 let neverHasSideEffects = 1 in {
878 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
879 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
880 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
881 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
885 let Predicates = [HasAVX512] in {
886 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
888 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
892 let Predicates = [HasAVX512] in {
893 // GR16 from/to 16-bit mask
894 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
895 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
896 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
897 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
899 // Store kreg in memory
900 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
901 (KMOVWmk addr:$dst, VK16:$src)>;
903 def : Pat<(store VK8:$src, addr:$dst),
904 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
906 def : Pat<(i1 (load addr:$src)),
907 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
909 def : Pat<(v8i1 (load addr:$src)),
910 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
912 def : Pat<(i1 (X86trunc (i32 GR32:$src))),
913 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
915 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
917 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
918 let Predicates = [HasAVX512] in {
919 // GR from/to 8-bit mask without native support
920 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
922 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
924 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
926 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
929 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
930 (COPY_TO_REGCLASS VK16:$src, VK1)>;
931 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
932 (COPY_TO_REGCLASS VK8:$src, VK1)>;
936 // Mask unary operation
938 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
939 RegisterClass KRC, SDPatternOperator OpNode> {
940 let Predicates = [HasAVX512] in
941 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
942 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
943 [(set KRC:$dst, (OpNode KRC:$src))]>;
946 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
947 SDPatternOperator OpNode> {
948 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
952 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
954 multiclass avx512_mask_unop_int<string IntName, string InstName> {
955 let Predicates = [HasAVX512] in
956 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
958 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
959 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
961 defm : avx512_mask_unop_int<"knot", "KNOT">;
963 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
964 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
965 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
967 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
968 def : Pat<(not VK8:$src),
970 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
972 // Mask binary operation
973 // - KAND, KANDN, KOR, KXNOR, KXOR
974 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
975 RegisterClass KRC, SDPatternOperator OpNode> {
976 let Predicates = [HasAVX512] in
977 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
978 !strconcat(OpcodeStr,
979 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
980 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
983 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
984 SDPatternOperator OpNode> {
985 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
989 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
990 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
992 let isCommutable = 1 in {
993 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
994 let isCommutable = 0 in
995 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
996 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
997 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
998 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1001 def : Pat<(xor VK1:$src1, VK1:$src2),
1002 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1003 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1005 def : Pat<(or VK1:$src1, VK1:$src2),
1006 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1007 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1009 def : Pat<(not VK1:$src),
1010 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1011 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1012 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1014 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1015 let Predicates = [HasAVX512] in
1016 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1017 (i16 GR16:$src1), (i16 GR16:$src2)),
1018 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1019 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1020 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1023 defm : avx512_mask_binop_int<"kand", "KAND">;
1024 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1025 defm : avx512_mask_binop_int<"kor", "KOR">;
1026 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1027 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1029 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1030 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1031 let Predicates = [HasAVX512] in
1032 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1034 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1035 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1038 defm : avx512_binop_pat<and, KANDWrr>;
1039 defm : avx512_binop_pat<andn, KANDNWrr>;
1040 defm : avx512_binop_pat<or, KORWrr>;
1041 defm : avx512_binop_pat<xnor, KXNORWrr>;
1042 defm : avx512_binop_pat<xor, KXORWrr>;
1045 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1046 RegisterClass KRC> {
1047 let Predicates = [HasAVX512] in
1048 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1049 !strconcat(OpcodeStr,
1050 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1053 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1054 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1055 VEX_4V, VEX_L, OpSize, TB;
1058 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1059 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1060 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1061 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1064 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1065 let Predicates = [HasAVX512] in
1066 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1067 (i16 GR16:$src1), (i16 GR16:$src2)),
1068 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1069 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1070 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1072 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1075 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1077 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1078 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1079 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1080 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1083 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1084 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1088 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1090 def : Pat<(X86cmp VK1:$src1, VK1:$src2),
1091 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1092 (COPY_TO_REGCLASS VK1:$src2, VK16))>;
1095 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1097 let Predicates = [HasAVX512] in
1098 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1099 !strconcat(OpcodeStr,
1100 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1101 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1104 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1106 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1107 VEX, OpSize, TA, VEX_W;
1110 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1111 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1113 // Mask setting all 0s or 1s
1114 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1115 let Predicates = [HasAVX512] in
1116 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1117 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1118 [(set KRC:$dst, (VT Val))]>;
1121 multiclass avx512_mask_setop_w<PatFrag Val> {
1122 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1123 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1126 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1127 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1129 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1130 let Predicates = [HasAVX512] in {
1131 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1132 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1134 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1135 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1137 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1138 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1140 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1141 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1143 //===----------------------------------------------------------------------===//
1144 // AVX-512 - Aligned and unaligned load and store
1147 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1148 X86MemOperand x86memop, PatFrag ld_frag,
1149 string asm, Domain d> {
1150 let neverHasSideEffects = 1 in
1151 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1152 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1154 let canFoldAsLoad = 1 in
1155 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1156 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1157 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1158 let Constraints = "$src1 = $dst" in {
1159 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1160 (ins RC:$src1, KRC:$mask, RC:$src2),
1162 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1164 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1165 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1167 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1168 [], d>, EVEX, EVEX_K;
1172 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1173 "vmovaps", SSEPackedSingle>,
1174 EVEX_V512, EVEX_CD8<32, CD8VF>;
1175 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1176 "vmovapd", SSEPackedDouble>,
1177 OpSize, EVEX_V512, VEX_W,
1178 EVEX_CD8<64, CD8VF>;
1179 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1180 "vmovups", SSEPackedSingle>,
1181 EVEX_V512, EVEX_CD8<32, CD8VF>;
1182 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1183 "vmovupd", SSEPackedDouble>,
1184 OpSize, EVEX_V512, VEX_W,
1185 EVEX_CD8<64, CD8VF>;
1186 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1187 "vmovaps\t{$src, $dst|$dst, $src}",
1188 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1189 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1190 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1191 "vmovapd\t{$src, $dst|$dst, $src}",
1192 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1193 SSEPackedDouble>, EVEX, EVEX_V512,
1194 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1195 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1196 "vmovups\t{$src, $dst|$dst, $src}",
1197 [(store (v16f32 VR512:$src), addr:$dst)],
1198 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1199 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1200 "vmovupd\t{$src, $dst|$dst, $src}",
1201 [(store (v8f64 VR512:$src), addr:$dst)],
1202 SSEPackedDouble>, EVEX, EVEX_V512,
1203 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1205 let neverHasSideEffects = 1 in {
1206 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1208 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1210 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1212 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1213 EVEX, EVEX_V512, VEX_W;
1214 let mayStore = 1 in {
1215 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1216 (ins i512mem:$dst, VR512:$src),
1217 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1218 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1219 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1220 (ins i512mem:$dst, VR512:$src),
1221 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1222 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1224 let mayLoad = 1 in {
1225 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1227 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1228 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1229 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1231 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1232 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1236 // 512-bit aligned load/store
1237 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1238 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1240 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1241 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1242 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1243 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1245 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1246 RegisterClass RC, RegisterClass KRC,
1247 PatFrag ld_frag, X86MemOperand x86memop> {
1248 let neverHasSideEffects = 1 in
1249 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1250 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1251 let canFoldAsLoad = 1 in
1252 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1253 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1254 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1256 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1257 (ins x86memop:$dst, VR512:$src),
1258 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1259 let Constraints = "$src1 = $dst" in {
1260 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1261 (ins RC:$src1, KRC:$mask, RC:$src2),
1263 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1265 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1266 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1268 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1273 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1274 memopv16i32, i512mem>,
1275 EVEX_V512, EVEX_CD8<32, CD8VF>;
1276 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1277 memopv8i64, i512mem>,
1278 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1280 // 512-bit unaligned load/store
1281 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1282 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1284 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1285 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1286 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1287 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1289 let AddedComplexity = 20 in {
1290 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1291 (v16f32 VR512:$src2))),
1292 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1293 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1294 (v8f64 VR512:$src2))),
1295 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1296 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1297 (v16i32 VR512:$src2))),
1298 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1299 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1300 (v8i64 VR512:$src2))),
1301 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1303 // Move Int Doubleword to Packed Double Int
1305 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1306 "vmovd\t{$src, $dst|$dst, $src}",
1308 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1310 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1311 "vmovd\t{$src, $dst|$dst, $src}",
1313 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1314 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1315 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1316 "vmovq\t{$src, $dst|$dst, $src}",
1318 (v2i64 (scalar_to_vector GR64:$src)))],
1319 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1320 let isCodeGenOnly = 1 in {
1321 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1322 "vmovq\t{$src, $dst|$dst, $src}",
1323 [(set FR64:$dst, (bitconvert GR64:$src))],
1324 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1325 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1326 "vmovq\t{$src, $dst|$dst, $src}",
1327 [(set GR64:$dst, (bitconvert FR64:$src))],
1328 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1330 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1331 "vmovq\t{$src, $dst|$dst, $src}",
1332 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1333 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1334 EVEX_CD8<64, CD8VT1>;
1336 // Move Int Doubleword to Single Scalar
1338 let isCodeGenOnly = 1 in {
1339 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1340 "vmovd\t{$src, $dst|$dst, $src}",
1341 [(set FR32X:$dst, (bitconvert GR32:$src))],
1342 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1344 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1345 "vmovd\t{$src, $dst|$dst, $src}",
1346 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1347 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1350 // Move Packed Doubleword Int to Packed Double Int
1352 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1353 "vmovd\t{$src, $dst|$dst, $src}",
1354 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1355 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1357 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1358 (ins i32mem:$dst, VR128X:$src),
1359 "vmovd\t{$src, $dst|$dst, $src}",
1360 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1361 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1362 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1364 // Move Packed Doubleword Int first element to Doubleword Int
1366 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1367 "vmovq\t{$src, $dst|$dst, $src}",
1368 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1370 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1371 Requires<[HasAVX512, In64BitMode]>;
1373 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1374 (ins i64mem:$dst, VR128X:$src),
1375 "vmovq\t{$src, $dst|$dst, $src}",
1376 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1377 addr:$dst)], IIC_SSE_MOVDQ>,
1378 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1379 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1381 // Move Scalar Single to Double Int
1383 let isCodeGenOnly = 1 in {
1384 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1386 "vmovd\t{$src, $dst|$dst, $src}",
1387 [(set GR32:$dst, (bitconvert FR32X:$src))],
1388 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1389 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1390 (ins i32mem:$dst, FR32X:$src),
1391 "vmovd\t{$src, $dst|$dst, $src}",
1392 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1393 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1396 // Move Quadword Int to Packed Quadword Int
1398 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1400 "vmovq\t{$src, $dst|$dst, $src}",
1402 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1403 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1405 //===----------------------------------------------------------------------===//
1406 // AVX-512 MOVSS, MOVSD
1407 //===----------------------------------------------------------------------===//
1409 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1410 SDNode OpNode, ValueType vt,
1411 X86MemOperand x86memop, PatFrag mem_pat> {
1412 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1413 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1414 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1415 (scalar_to_vector RC:$src2))))],
1416 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1417 let Constraints = "$src1 = $dst" in
1418 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1419 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1421 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1422 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1423 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1424 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1425 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1427 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1428 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1429 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1433 let ExeDomain = SSEPackedSingle in
1434 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1435 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1437 let ExeDomain = SSEPackedDouble in
1438 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1439 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1441 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1442 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1443 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1445 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1446 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1447 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1449 // For the disassembler
1450 let isCodeGenOnly = 1 in {
1451 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1452 (ins VR128X:$src1, FR32X:$src2),
1453 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1455 XS, EVEX_4V, VEX_LIG;
1456 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1457 (ins VR128X:$src1, FR64X:$src2),
1458 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1460 XD, EVEX_4V, VEX_LIG, VEX_W;
1463 let Predicates = [HasAVX512] in {
1464 let AddedComplexity = 15 in {
1465 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1466 // MOVS{S,D} to the lower bits.
1467 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1468 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1469 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1470 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1471 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1472 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1473 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1474 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1476 // Move low f32 and clear high bits.
1477 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1478 (SUBREG_TO_REG (i32 0),
1479 (VMOVSSZrr (v4f32 (V_SET0)),
1480 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1481 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1482 (SUBREG_TO_REG (i32 0),
1483 (VMOVSSZrr (v4i32 (V_SET0)),
1484 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1487 let AddedComplexity = 20 in {
1488 // MOVSSrm zeros the high parts of the register; represent this
1489 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1490 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1491 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1492 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1493 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1494 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1495 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1497 // MOVSDrm zeros the high parts of the register; represent this
1498 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1499 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1500 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1501 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1502 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1503 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1504 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1505 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1506 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1507 def : Pat<(v2f64 (X86vzload addr:$src)),
1508 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1510 // Represent the same patterns above but in the form they appear for
1512 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1513 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1514 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1515 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1516 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1517 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1518 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1519 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1520 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1522 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1523 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1524 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1525 FR32X:$src)), sub_xmm)>;
1526 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1527 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1528 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1529 FR64X:$src)), sub_xmm)>;
1530 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1531 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1532 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1534 // Move low f64 and clear high bits.
1535 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1536 (SUBREG_TO_REG (i32 0),
1537 (VMOVSDZrr (v2f64 (V_SET0)),
1538 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1540 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1541 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1542 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1544 // Extract and store.
1545 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1547 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1548 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1550 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1552 // Shuffle with VMOVSS
1553 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1554 (VMOVSSZrr (v4i32 VR128X:$src1),
1555 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1556 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1557 (VMOVSSZrr (v4f32 VR128X:$src1),
1558 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1561 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1562 (SUBREG_TO_REG (i32 0),
1563 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1564 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1566 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1567 (SUBREG_TO_REG (i32 0),
1568 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1569 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1572 // Shuffle with VMOVSD
1573 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1574 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1575 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1576 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1577 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1578 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1579 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1580 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1583 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1584 (SUBREG_TO_REG (i32 0),
1585 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1586 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1588 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1589 (SUBREG_TO_REG (i32 0),
1590 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1591 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1594 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1595 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1596 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1597 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1598 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1599 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1600 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1601 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1604 let AddedComplexity = 15 in
1605 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1607 "vmovq\t{$src, $dst|$dst, $src}",
1608 [(set VR128X:$dst, (v2i64 (X86vzmovl
1609 (v2i64 VR128X:$src))))],
1610 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1612 let AddedComplexity = 20 in
1613 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1615 "vmovq\t{$src, $dst|$dst, $src}",
1616 [(set VR128X:$dst, (v2i64 (X86vzmovl
1617 (loadv2i64 addr:$src))))],
1618 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1619 EVEX_CD8<8, CD8VT8>;
1621 let Predicates = [HasAVX512] in {
1622 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1623 let AddedComplexity = 20 in {
1624 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1625 (VMOVDI2PDIZrm addr:$src)>;
1626 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1627 (VMOV64toPQIZrr GR64:$src)>;
1628 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1629 (VMOVDI2PDIZrr GR32:$src)>;
1631 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1632 (VMOVDI2PDIZrm addr:$src)>;
1633 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1634 (VMOVDI2PDIZrm addr:$src)>;
1635 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1636 (VMOVZPQILo2PQIZrm addr:$src)>;
1637 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1638 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1639 def : Pat<(v2i64 (X86vzload addr:$src)),
1640 (VMOVZPQILo2PQIZrm addr:$src)>;
1643 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1644 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1645 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1646 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1647 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1648 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1649 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1652 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1653 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1655 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1656 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1658 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1659 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1661 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1662 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1664 //===----------------------------------------------------------------------===//
1665 // AVX-512 - Integer arithmetic
1667 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1668 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1669 X86MemOperand x86memop, PatFrag scalar_mfrag,
1670 X86MemOperand x86scalar_mop, string BrdcstStr,
1671 OpndItins itins, bit IsCommutable = 0> {
1672 let isCommutable = IsCommutable in
1673 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1674 (ins RC:$src1, RC:$src2),
1675 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1676 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1678 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1679 (ins RC:$src1, x86memop:$src2),
1680 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1681 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1683 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1684 (ins RC:$src1, x86scalar_mop:$src2),
1685 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1686 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1687 [(set RC:$dst, (OpNode RC:$src1,
1688 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1689 itins.rm>, EVEX_4V, EVEX_B;
1691 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1692 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1693 PatFrag memop_frag, X86MemOperand x86memop,
1695 bit IsCommutable = 0> {
1696 let isCommutable = IsCommutable in
1697 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1698 (ins RC:$src1, RC:$src2),
1699 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1700 []>, EVEX_4V, VEX_W;
1701 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1702 (ins RC:$src1, x86memop:$src2),
1703 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1704 []>, EVEX_4V, VEX_W;
1707 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1708 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1709 EVEX_V512, EVEX_CD8<32, CD8VF>;
1711 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1712 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1713 EVEX_V512, EVEX_CD8<32, CD8VF>;
1715 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1716 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1717 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1719 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1720 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1721 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1723 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1724 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1725 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1727 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1728 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1729 EVEX_V512, EVEX_CD8<64, CD8VF>;
1731 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1732 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1733 EVEX_CD8<64, CD8VF>;
1735 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1736 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1738 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1739 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1740 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1741 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1742 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1743 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1745 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1746 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1747 EVEX_V512, EVEX_CD8<32, CD8VF>;
1748 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1749 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1750 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1752 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1753 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1754 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1755 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1756 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1757 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1759 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1760 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1761 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1762 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1763 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1764 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1766 //===----------------------------------------------------------------------===//
1767 // AVX-512 - Unpack Instructions
1768 //===----------------------------------------------------------------------===//
1770 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1771 PatFrag mem_frag, RegisterClass RC,
1772 X86MemOperand x86memop, string asm,
1774 def rr : AVX512PI<opc, MRMSrcReg,
1775 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1777 (vt (OpNode RC:$src1, RC:$src2)))],
1779 def rm : AVX512PI<opc, MRMSrcMem,
1780 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1782 (vt (OpNode RC:$src1,
1783 (bitconvert (mem_frag addr:$src2)))))],
1787 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1788 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1789 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1790 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1791 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1792 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1793 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1794 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1795 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1796 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1797 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1798 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1800 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1801 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1802 X86MemOperand x86memop> {
1803 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1804 (ins RC:$src1, RC:$src2),
1805 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1806 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1807 IIC_SSE_UNPCK>, EVEX_4V;
1808 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1809 (ins RC:$src1, x86memop:$src2),
1810 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1811 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1812 (bitconvert (memop_frag addr:$src2)))))],
1813 IIC_SSE_UNPCK>, EVEX_4V;
1815 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1816 VR512, memopv16i32, i512mem>, EVEX_V512,
1817 EVEX_CD8<32, CD8VF>;
1818 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1819 VR512, memopv8i64, i512mem>, EVEX_V512,
1820 VEX_W, EVEX_CD8<64, CD8VF>;
1821 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1822 VR512, memopv16i32, i512mem>, EVEX_V512,
1823 EVEX_CD8<32, CD8VF>;
1824 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1825 VR512, memopv8i64, i512mem>, EVEX_V512,
1826 VEX_W, EVEX_CD8<64, CD8VF>;
1827 //===----------------------------------------------------------------------===//
1831 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1832 SDNode OpNode, PatFrag mem_frag,
1833 X86MemOperand x86memop, ValueType OpVT> {
1834 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1835 (ins RC:$src1, i8imm:$src2),
1836 !strconcat(OpcodeStr,
1837 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1839 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1841 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1842 (ins x86memop:$src1, i8imm:$src2),
1843 !strconcat(OpcodeStr,
1844 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1846 (OpVT (OpNode (mem_frag addr:$src1),
1847 (i8 imm:$src2))))]>, EVEX;
1850 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1851 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1853 let ExeDomain = SSEPackedSingle in
1854 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1855 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1856 EVEX_CD8<32, CD8VF>;
1857 let ExeDomain = SSEPackedDouble in
1858 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1859 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1860 VEX_W, EVEX_CD8<32, CD8VF>;
1862 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1863 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1864 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1865 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1867 //===----------------------------------------------------------------------===//
1868 // AVX-512 Logical Instructions
1869 //===----------------------------------------------------------------------===//
1871 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1872 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1873 EVEX_V512, EVEX_CD8<32, CD8VF>;
1874 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1875 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1876 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1877 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1878 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1879 EVEX_V512, EVEX_CD8<32, CD8VF>;
1880 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1881 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1882 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1883 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1884 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1885 EVEX_V512, EVEX_CD8<32, CD8VF>;
1886 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1887 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1888 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1889 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1890 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1891 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1892 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1893 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1894 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1896 //===----------------------------------------------------------------------===//
1897 // AVX-512 FP arithmetic
1898 //===----------------------------------------------------------------------===//
1900 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1902 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1903 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1904 EVEX_CD8<32, CD8VT1>;
1905 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1906 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1907 EVEX_CD8<64, CD8VT1>;
1910 let isCommutable = 1 in {
1911 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1912 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1913 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1914 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1916 let isCommutable = 0 in {
1917 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1918 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1921 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1922 RegisterClass RC, ValueType vt,
1923 X86MemOperand x86memop, PatFrag mem_frag,
1924 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1926 Domain d, OpndItins itins, bit commutable> {
1927 let isCommutable = commutable in
1928 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1929 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1930 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1932 let mayLoad = 1 in {
1933 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1934 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1935 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1936 itins.rm, d>, EVEX_4V, TB;
1937 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1938 (ins RC:$src1, x86scalar_mop:$src2),
1939 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1940 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1941 [(set RC:$dst, (OpNode RC:$src1,
1942 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1943 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1947 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1948 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1949 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1951 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1952 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1953 SSE_ALU_ITINS_P.d, 1>,
1954 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1956 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1957 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1958 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1959 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1960 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1961 SSE_ALU_ITINS_P.d, 1>,
1962 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1964 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1965 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1966 SSE_ALU_ITINS_P.s, 1>,
1967 EVEX_V512, EVEX_CD8<32, CD8VF>;
1968 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1969 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1970 SSE_ALU_ITINS_P.s, 1>,
1971 EVEX_V512, EVEX_CD8<32, CD8VF>;
1973 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1974 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1975 SSE_ALU_ITINS_P.d, 1>,
1976 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1977 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1978 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1979 SSE_ALU_ITINS_P.d, 1>,
1980 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1982 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1983 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1984 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1985 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1986 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1987 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1989 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1990 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1991 SSE_ALU_ITINS_P.d, 0>,
1992 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1993 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1994 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1995 SSE_ALU_ITINS_P.d, 0>,
1996 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1998 //===----------------------------------------------------------------------===//
1999 // AVX-512 VPTESTM instructions
2000 //===----------------------------------------------------------------------===//
2002 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2003 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2004 SDNode OpNode, ValueType vt> {
2005 def rr : AVX5128I<opc, MRMSrcReg,
2006 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2007 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2008 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2009 def rm : AVX5128I<opc, MRMSrcMem,
2010 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2012 [(set KRC:$dst, (OpNode (vt RC:$src1),
2013 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2016 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2017 memopv16i32, X86testm, v16i32>, EVEX_V512,
2018 EVEX_CD8<32, CD8VF>;
2019 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2020 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2021 EVEX_CD8<64, CD8VF>;
2023 //===----------------------------------------------------------------------===//
2024 // AVX-512 Shift instructions
2025 //===----------------------------------------------------------------------===//
2026 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2027 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2028 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2029 RegisterClass KRC> {
2030 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2031 (ins RC:$src1, i8imm:$src2),
2032 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2033 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2034 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2035 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2036 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2037 !strconcat(OpcodeStr,
2038 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2039 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2040 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2041 (ins x86memop:$src1, i8imm:$src2),
2042 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2043 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2044 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2045 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2046 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2047 !strconcat(OpcodeStr,
2048 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2049 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2052 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2053 RegisterClass RC, ValueType vt, ValueType SrcVT,
2054 PatFrag bc_frag, RegisterClass KRC> {
2055 // src2 is always 128-bit
2056 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2057 (ins RC:$src1, VR128X:$src2),
2058 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2059 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2060 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2061 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2062 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2063 !strconcat(OpcodeStr,
2064 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2065 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2066 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2067 (ins RC:$src1, i128mem:$src2),
2068 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2069 [(set RC:$dst, (vt (OpNode RC:$src1,
2070 (bc_frag (memopv2i64 addr:$src2)))))],
2071 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2072 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2073 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2074 !strconcat(OpcodeStr,
2075 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2076 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2079 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2080 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2081 EVEX_V512, EVEX_CD8<32, CD8VF>;
2082 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2083 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2084 EVEX_CD8<32, CD8VQ>;
2086 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2087 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2088 EVEX_CD8<64, CD8VF>, VEX_W;
2089 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2090 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2091 EVEX_CD8<64, CD8VQ>, VEX_W;
2093 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2094 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2095 EVEX_CD8<32, CD8VF>;
2096 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2097 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2098 EVEX_CD8<32, CD8VQ>;
2100 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2101 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2102 EVEX_CD8<64, CD8VF>, VEX_W;
2103 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2104 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2105 EVEX_CD8<64, CD8VQ>, VEX_W;
2107 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2108 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2109 EVEX_V512, EVEX_CD8<32, CD8VF>;
2110 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2111 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2112 EVEX_CD8<32, CD8VQ>;
2114 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2115 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2116 EVEX_CD8<64, CD8VF>, VEX_W;
2117 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2118 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2119 EVEX_CD8<64, CD8VQ>, VEX_W;
2121 //===-------------------------------------------------------------------===//
2122 // Variable Bit Shifts
2123 //===-------------------------------------------------------------------===//
2124 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2125 RegisterClass RC, ValueType vt,
2126 X86MemOperand x86memop, PatFrag mem_frag> {
2127 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2128 (ins RC:$src1, RC:$src2),
2129 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2131 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2133 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2134 (ins RC:$src1, x86memop:$src2),
2135 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2137 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2141 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2142 i512mem, memopv16i32>, EVEX_V512,
2143 EVEX_CD8<32, CD8VF>;
2144 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2145 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2146 EVEX_CD8<64, CD8VF>;
2147 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2148 i512mem, memopv16i32>, EVEX_V512,
2149 EVEX_CD8<32, CD8VF>;
2150 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2151 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2152 EVEX_CD8<64, CD8VF>;
2153 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2154 i512mem, memopv16i32>, EVEX_V512,
2155 EVEX_CD8<32, CD8VF>;
2156 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2157 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2158 EVEX_CD8<64, CD8VF>;
2160 //===----------------------------------------------------------------------===//
2161 // AVX-512 - MOVDDUP
2162 //===----------------------------------------------------------------------===//
2164 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2165 X86MemOperand x86memop, PatFrag memop_frag> {
2166 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2167 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2168 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2169 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2170 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2172 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2175 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2176 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2177 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2178 (VMOVDDUPZrm addr:$src)>;
2180 //===---------------------------------------------------------------------===//
2181 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2182 //===---------------------------------------------------------------------===//
2183 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2184 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2185 X86MemOperand x86memop> {
2186 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2187 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2188 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2190 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2191 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2192 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2195 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2196 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2197 EVEX_CD8<32, CD8VF>;
2198 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2199 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2200 EVEX_CD8<32, CD8VF>;
2202 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2203 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2204 (VMOVSHDUPZrm addr:$src)>;
2205 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2206 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2207 (VMOVSLDUPZrm addr:$src)>;
2209 //===----------------------------------------------------------------------===//
2210 // Move Low to High and High to Low packed FP Instructions
2211 //===----------------------------------------------------------------------===//
2212 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2213 (ins VR128X:$src1, VR128X:$src2),
2214 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2215 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2216 IIC_SSE_MOV_LH>, EVEX_4V;
2217 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2218 (ins VR128X:$src1, VR128X:$src2),
2219 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2220 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2221 IIC_SSE_MOV_LH>, EVEX_4V;
2223 let Predicates = [HasAVX512] in {
2225 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2226 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2227 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2228 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2231 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2232 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2235 //===----------------------------------------------------------------------===//
2236 // FMA - Fused Multiply Operations
2238 let Constraints = "$src1 = $dst" in {
2239 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2240 RegisterClass RC, X86MemOperand x86memop,
2241 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2242 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2243 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2244 (ins RC:$src1, RC:$src2, RC:$src3),
2245 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2246 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2249 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2250 (ins RC:$src1, RC:$src2, x86memop:$src3),
2251 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2252 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2253 (mem_frag addr:$src3))))]>;
2254 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2255 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2256 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2257 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2258 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2259 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2261 } // Constraints = "$src1 = $dst"
2263 let ExeDomain = SSEPackedSingle in {
2264 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2265 memopv16f32, f32mem, loadf32, "{1to16}",
2266 X86Fmadd, v16f32>, EVEX_V512,
2267 EVEX_CD8<32, CD8VF>;
2268 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2269 memopv16f32, f32mem, loadf32, "{1to16}",
2270 X86Fmsub, v16f32>, EVEX_V512,
2271 EVEX_CD8<32, CD8VF>;
2272 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2273 memopv16f32, f32mem, loadf32, "{1to16}",
2274 X86Fmaddsub, v16f32>,
2275 EVEX_V512, EVEX_CD8<32, CD8VF>;
2276 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2277 memopv16f32, f32mem, loadf32, "{1to16}",
2278 X86Fmsubadd, v16f32>,
2279 EVEX_V512, EVEX_CD8<32, CD8VF>;
2280 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2281 memopv16f32, f32mem, loadf32, "{1to16}",
2282 X86Fnmadd, v16f32>, EVEX_V512,
2283 EVEX_CD8<32, CD8VF>;
2284 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2285 memopv16f32, f32mem, loadf32, "{1to16}",
2286 X86Fnmsub, v16f32>, EVEX_V512,
2287 EVEX_CD8<32, CD8VF>;
2289 let ExeDomain = SSEPackedDouble in {
2290 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2291 memopv8f64, f64mem, loadf64, "{1to8}",
2292 X86Fmadd, v8f64>, EVEX_V512,
2293 VEX_W, EVEX_CD8<64, CD8VF>;
2294 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2295 memopv8f64, f64mem, loadf64, "{1to8}",
2296 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2297 EVEX_CD8<64, CD8VF>;
2298 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2299 memopv8f64, f64mem, loadf64, "{1to8}",
2300 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2301 EVEX_CD8<64, CD8VF>;
2302 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2303 memopv8f64, f64mem, loadf64, "{1to8}",
2304 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2305 EVEX_CD8<64, CD8VF>;
2306 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2307 memopv8f64, f64mem, loadf64, "{1to8}",
2308 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2309 EVEX_CD8<64, CD8VF>;
2310 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2311 memopv8f64, f64mem, loadf64, "{1to8}",
2312 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2313 EVEX_CD8<64, CD8VF>;
2316 let Constraints = "$src1 = $dst" in {
2317 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2318 RegisterClass RC, X86MemOperand x86memop,
2319 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2320 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2322 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2323 (ins RC:$src1, RC:$src3, x86memop:$src2),
2324 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2325 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2326 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2327 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2328 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2329 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2330 [(set RC:$dst, (OpNode RC:$src1,
2331 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2333 } // Constraints = "$src1 = $dst"
2336 let ExeDomain = SSEPackedSingle in {
2337 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2338 memopv16f32, f32mem, loadf32, "{1to16}",
2339 X86Fmadd, v16f32>, EVEX_V512,
2340 EVEX_CD8<32, CD8VF>;
2341 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2342 memopv16f32, f32mem, loadf32, "{1to16}",
2343 X86Fmsub, v16f32>, EVEX_V512,
2344 EVEX_CD8<32, CD8VF>;
2345 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2346 memopv16f32, f32mem, loadf32, "{1to16}",
2347 X86Fmaddsub, v16f32>,
2348 EVEX_V512, EVEX_CD8<32, CD8VF>;
2349 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2350 memopv16f32, f32mem, loadf32, "{1to16}",
2351 X86Fmsubadd, v16f32>,
2352 EVEX_V512, EVEX_CD8<32, CD8VF>;
2353 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2354 memopv16f32, f32mem, loadf32, "{1to16}",
2355 X86Fnmadd, v16f32>, EVEX_V512,
2356 EVEX_CD8<32, CD8VF>;
2357 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2358 memopv16f32, f32mem, loadf32, "{1to16}",
2359 X86Fnmsub, v16f32>, EVEX_V512,
2360 EVEX_CD8<32, CD8VF>;
2362 let ExeDomain = SSEPackedDouble in {
2363 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2364 memopv8f64, f64mem, loadf64, "{1to8}",
2365 X86Fmadd, v8f64>, EVEX_V512,
2366 VEX_W, EVEX_CD8<64, CD8VF>;
2367 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2368 memopv8f64, f64mem, loadf64, "{1to8}",
2369 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2370 EVEX_CD8<64, CD8VF>;
2371 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2372 memopv8f64, f64mem, loadf64, "{1to8}",
2373 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2374 EVEX_CD8<64, CD8VF>;
2375 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2376 memopv8f64, f64mem, loadf64, "{1to8}",
2377 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2378 EVEX_CD8<64, CD8VF>;
2379 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2380 memopv8f64, f64mem, loadf64, "{1to8}",
2381 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2382 EVEX_CD8<64, CD8VF>;
2383 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2384 memopv8f64, f64mem, loadf64, "{1to8}",
2385 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2386 EVEX_CD8<64, CD8VF>;
2390 let Constraints = "$src1 = $dst" in {
2391 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2392 RegisterClass RC, ValueType OpVT,
2393 X86MemOperand x86memop, Operand memop,
2395 let isCommutable = 1 in
2396 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2397 (ins RC:$src1, RC:$src2, RC:$src3),
2398 !strconcat(OpcodeStr,
2399 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2401 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2403 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2404 (ins RC:$src1, RC:$src2, f128mem:$src3),
2405 !strconcat(OpcodeStr,
2406 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2408 (OpVT (OpNode RC:$src2, RC:$src1,
2409 (mem_frag addr:$src3))))]>;
2412 } // Constraints = "$src1 = $dst"
2414 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2415 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2416 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2417 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2418 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2419 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2420 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2421 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2422 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2423 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2424 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2425 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2426 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2427 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2428 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2429 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2431 //===----------------------------------------------------------------------===//
2432 // AVX-512 Scalar convert from sign integer to float/double
2433 //===----------------------------------------------------------------------===//
2435 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2436 X86MemOperand x86memop, string asm> {
2437 let neverHasSideEffects = 1 in {
2438 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2439 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2442 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2443 (ins DstRC:$src1, x86memop:$src),
2444 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2446 } // neverHasSideEffects = 1
2448 let Predicates = [HasAVX512] in {
2449 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2450 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2451 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2452 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2453 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2454 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2455 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2456 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2458 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2459 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2460 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2461 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2462 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2463 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2464 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2465 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2467 def : Pat<(f32 (sint_to_fp GR32:$src)),
2468 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2469 def : Pat<(f32 (sint_to_fp GR64:$src)),
2470 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2471 def : Pat<(f64 (sint_to_fp GR32:$src)),
2472 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2473 def : Pat<(f64 (sint_to_fp GR64:$src)),
2474 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2476 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2477 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2478 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2479 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2480 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2481 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2482 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2483 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2485 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2486 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2487 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2488 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2489 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2490 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2491 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2492 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2494 def : Pat<(f32 (uint_to_fp GR32:$src)),
2495 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2496 def : Pat<(f32 (uint_to_fp GR64:$src)),
2497 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2498 def : Pat<(f64 (uint_to_fp GR32:$src)),
2499 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2500 def : Pat<(f64 (uint_to_fp GR64:$src)),
2501 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2504 //===----------------------------------------------------------------------===//
2505 // AVX-512 Scalar convert from float/double to integer
2506 //===----------------------------------------------------------------------===//
2507 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2508 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2510 let neverHasSideEffects = 1 in {
2511 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2512 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2513 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2514 Requires<[HasAVX512]>;
2516 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2517 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2518 Requires<[HasAVX512]>;
2519 } // neverHasSideEffects = 1
2521 let Predicates = [HasAVX512] in {
2522 // Convert float/double to signed/unsigned int 32/64
2523 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2524 ssmem, sse_load_f32, "cvtss2si">,
2525 XS, EVEX_CD8<32, CD8VT1>;
2526 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2527 ssmem, sse_load_f32, "cvtss2si">,
2528 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2529 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2530 ssmem, sse_load_f32, "cvtss2usi">,
2531 XS, EVEX_CD8<32, CD8VT1>;
2532 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2533 int_x86_avx512_cvtss2usi64, ssmem,
2534 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2535 EVEX_CD8<32, CD8VT1>;
2536 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2537 sdmem, sse_load_f64, "cvtsd2si">,
2538 XD, EVEX_CD8<64, CD8VT1>;
2539 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2540 sdmem, sse_load_f64, "cvtsd2si">,
2541 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2542 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2543 sdmem, sse_load_f64, "cvtsd2usi">,
2544 XD, EVEX_CD8<64, CD8VT1>;
2545 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2546 int_x86_avx512_cvtsd2usi64, sdmem,
2547 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2548 EVEX_CD8<64, CD8VT1>;
2550 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2551 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2552 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2553 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2554 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2555 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2556 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2557 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2558 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2559 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2560 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2561 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2563 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2564 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2565 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2566 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2567 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2568 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2569 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2570 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2571 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2572 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2573 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2574 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2576 // Convert float/double to signed/unsigned int 32/64 with truncation
2577 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2578 ssmem, sse_load_f32, "cvttss2si">,
2579 XS, EVEX_CD8<32, CD8VT1>;
2580 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2581 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2582 "cvttss2si">, XS, VEX_W,
2583 EVEX_CD8<32, CD8VT1>;
2584 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2585 sdmem, sse_load_f64, "cvttsd2si">, XD,
2586 EVEX_CD8<64, CD8VT1>;
2587 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2588 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2589 "cvttsd2si">, XD, VEX_W,
2590 EVEX_CD8<64, CD8VT1>;
2591 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2592 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2593 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2594 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2595 int_x86_avx512_cvttss2usi64, ssmem,
2596 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2597 EVEX_CD8<32, CD8VT1>;
2598 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2599 int_x86_avx512_cvttsd2usi,
2600 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2601 EVEX_CD8<64, CD8VT1>;
2602 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2603 int_x86_avx512_cvttsd2usi64, sdmem,
2604 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2605 EVEX_CD8<64, CD8VT1>;
2607 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2608 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2610 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2611 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2612 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2613 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2614 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2615 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2618 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2619 loadf32, "cvttss2si">, XS,
2620 EVEX_CD8<32, CD8VT1>;
2621 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2622 loadf32, "cvttss2usi">, XS,
2623 EVEX_CD8<32, CD8VT1>;
2624 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2625 loadf32, "cvttss2si">, XS, VEX_W,
2626 EVEX_CD8<32, CD8VT1>;
2627 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2628 loadf32, "cvttss2usi">, XS, VEX_W,
2629 EVEX_CD8<32, CD8VT1>;
2630 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2631 loadf64, "cvttsd2si">, XD,
2632 EVEX_CD8<64, CD8VT1>;
2633 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2634 loadf64, "cvttsd2usi">, XD,
2635 EVEX_CD8<64, CD8VT1>;
2636 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2637 loadf64, "cvttsd2si">, XD, VEX_W,
2638 EVEX_CD8<64, CD8VT1>;
2639 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2640 loadf64, "cvttsd2usi">, XD, VEX_W,
2641 EVEX_CD8<64, CD8VT1>;
2643 //===----------------------------------------------------------------------===//
2644 // AVX-512 Convert form float to double and back
2645 //===----------------------------------------------------------------------===//
2646 let neverHasSideEffects = 1 in {
2647 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2648 (ins FR32X:$src1, FR32X:$src2),
2649 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2650 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2652 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2653 (ins FR32X:$src1, f32mem:$src2),
2654 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2655 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2656 EVEX_CD8<32, CD8VT1>;
2658 // Convert scalar double to scalar single
2659 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2660 (ins FR64X:$src1, FR64X:$src2),
2661 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2662 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2664 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2665 (ins FR64X:$src1, f64mem:$src2),
2666 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2667 []>, EVEX_4V, VEX_LIG, VEX_W,
2668 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2671 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2672 Requires<[HasAVX512]>;
2673 def : Pat<(fextend (loadf32 addr:$src)),
2674 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2676 def : Pat<(extloadf32 addr:$src),
2677 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2678 Requires<[HasAVX512, OptForSize]>;
2680 def : Pat<(extloadf32 addr:$src),
2681 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2682 Requires<[HasAVX512, OptForSpeed]>;
2684 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2685 Requires<[HasAVX512]>;
2687 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2688 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2689 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2691 let neverHasSideEffects = 1 in {
2692 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2693 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2695 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2697 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2698 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2700 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2701 } // neverHasSideEffects = 1
2704 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2705 memopv8f64, f512mem, v8f32, v8f64,
2706 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2707 EVEX_CD8<64, CD8VF>;
2709 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2710 memopv4f64, f256mem, v8f64, v8f32,
2711 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2712 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2713 (VCVTPS2PDZrm addr:$src)>;
2715 //===----------------------------------------------------------------------===//
2716 // AVX-512 Vector convert from sign integer to float/double
2717 //===----------------------------------------------------------------------===//
2719 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2720 memopv8i64, i512mem, v16f32, v16i32,
2721 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2723 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2724 memopv4i64, i256mem, v8f64, v8i32,
2725 SSEPackedDouble>, EVEX_V512, XS,
2726 EVEX_CD8<32, CD8VH>;
2728 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2729 memopv16f32, f512mem, v16i32, v16f32,
2730 SSEPackedSingle>, EVEX_V512, XS,
2731 EVEX_CD8<32, CD8VF>;
2733 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2734 memopv8f64, f512mem, v8i32, v8f64,
2735 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2736 EVEX_CD8<64, CD8VF>;
2738 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2739 memopv16f32, f512mem, v16i32, v16f32,
2740 SSEPackedSingle>, EVEX_V512,
2741 EVEX_CD8<32, CD8VF>;
2743 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2744 memopv8f64, f512mem, v8i32, v8f64,
2745 SSEPackedDouble>, EVEX_V512, VEX_W,
2746 EVEX_CD8<64, CD8VF>;
2748 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2749 memopv4i64, f256mem, v8f64, v8i32,
2750 SSEPackedDouble>, EVEX_V512, XS,
2751 EVEX_CD8<32, CD8VH>;
2753 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2754 memopv16i32, f512mem, v16f32, v16i32,
2755 SSEPackedSingle>, EVEX_V512, XD,
2756 EVEX_CD8<32, CD8VF>;
2758 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2759 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2760 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2763 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2764 (VCVTDQ2PSZrr VR512:$src)>;
2765 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2766 (VCVTDQ2PSZrm addr:$src)>;
2768 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2769 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2771 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2772 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2773 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2774 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2776 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2777 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2780 let Predicates = [HasAVX512] in {
2781 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2782 (VCVTPD2PSZrm addr:$src)>;
2783 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2784 (VCVTPS2PDZrm addr:$src)>;
2787 //===----------------------------------------------------------------------===//
2788 // Half precision conversion instructions
2789 //===----------------------------------------------------------------------===//
2790 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2791 X86MemOperand x86memop, Intrinsic Int> {
2792 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2793 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2794 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2795 let neverHasSideEffects = 1, mayLoad = 1 in
2796 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2797 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2800 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2801 X86MemOperand x86memop, Intrinsic Int> {
2802 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2803 (ins srcRC:$src1, i32i8imm:$src2),
2804 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2805 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2806 let neverHasSideEffects = 1, mayStore = 1 in
2807 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2808 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2809 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2812 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2813 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2814 EVEX_CD8<32, CD8VH>;
2815 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2816 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2817 EVEX_CD8<32, CD8VH>;
2819 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2820 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2821 "ucomiss">, TB, EVEX, VEX_LIG,
2822 EVEX_CD8<32, CD8VT1>;
2823 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2824 "ucomisd">, TB, OpSize, EVEX,
2825 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2826 let Pattern = []<dag> in {
2827 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2828 "comiss">, TB, EVEX, VEX_LIG,
2829 EVEX_CD8<32, CD8VT1>;
2830 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2831 "comisd">, TB, OpSize, EVEX,
2832 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2834 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2835 load, "ucomiss">, TB, EVEX, VEX_LIG,
2836 EVEX_CD8<32, CD8VT1>;
2837 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2838 load, "ucomisd">, TB, OpSize, EVEX,
2839 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2841 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2842 load, "comiss">, TB, EVEX, VEX_LIG,
2843 EVEX_CD8<32, CD8VT1>;
2844 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2845 load, "comisd">, TB, OpSize, EVEX,
2846 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2849 /// avx512_unop_p - AVX-512 unops in packed form.
2850 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2851 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2852 !strconcat(OpcodeStr,
2853 "ps\t{$src, $dst|$dst, $src}"),
2854 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2856 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2857 !strconcat(OpcodeStr,
2858 "ps\t{$src, $dst|$dst, $src}"),
2859 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2860 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2861 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2862 !strconcat(OpcodeStr,
2863 "pd\t{$src, $dst|$dst, $src}"),
2864 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2865 EVEX, EVEX_V512, VEX_W;
2866 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2867 !strconcat(OpcodeStr,
2868 "pd\t{$src, $dst|$dst, $src}"),
2869 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2870 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2873 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2874 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2875 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2876 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2877 !strconcat(OpcodeStr,
2878 "ps\t{$src, $dst|$dst, $src}"),
2879 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2881 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2882 !strconcat(OpcodeStr,
2883 "ps\t{$src, $dst|$dst, $src}"),
2885 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2886 EVEX_V512, EVEX_CD8<32, CD8VF>;
2887 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2888 !strconcat(OpcodeStr,
2889 "pd\t{$src, $dst|$dst, $src}"),
2890 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2891 EVEX, EVEX_V512, VEX_W;
2892 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2893 !strconcat(OpcodeStr,
2894 "pd\t{$src, $dst|$dst, $src}"),
2896 (V8F64Int (memopv8f64 addr:$src)))]>,
2897 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2900 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
2901 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
2902 let hasSideEffects = 0 in {
2903 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2904 (ins FR32X:$src1, FR32X:$src2),
2905 !strconcat(OpcodeStr,
2906 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2908 let mayLoad = 1 in {
2909 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2910 (ins FR32X:$src1, f32mem:$src2),
2911 !strconcat(OpcodeStr,
2912 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2913 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2914 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2915 (ins VR128X:$src1, ssmem:$src2),
2916 !strconcat(OpcodeStr,
2917 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2918 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2920 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2921 (ins FR64X:$src1, FR64X:$src2),
2922 !strconcat(OpcodeStr,
2923 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2925 let mayLoad = 1 in {
2926 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2927 (ins FR64X:$src1, f64mem:$src2),
2928 !strconcat(OpcodeStr,
2929 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2930 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2931 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2932 (ins VR128X:$src1, sdmem:$src2),
2933 !strconcat(OpcodeStr,
2934 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2935 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2940 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
2941 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2942 avx512_fp_unop_p_int<0x4C, "vrcp14",
2943 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2945 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
2946 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2947 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2948 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2950 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2951 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2952 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2954 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2955 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2957 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2958 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2959 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2961 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2962 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2964 let AddedComplexity = 20, Predicates = [HasERI] in {
2965 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2966 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2967 avx512_fp_unop_p_int<0xCA, "vrcp28",
2968 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2970 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2971 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2972 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2973 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2976 let Predicates = [HasERI] in {
2977 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2978 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2979 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2981 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2982 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2984 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2985 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2986 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2988 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2989 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2991 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2992 Intrinsic V16F32Int, Intrinsic V8F64Int,
2993 OpndItins itins_s, OpndItins itins_d> {
2994 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2995 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2996 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3000 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3001 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3003 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3004 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3006 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3007 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3008 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3012 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3013 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3014 [(set VR512:$dst, (OpNode
3015 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3016 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3018 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3019 !strconcat(OpcodeStr,
3020 "ps\t{$src, $dst|$dst, $src}"),
3021 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3023 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3024 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3026 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3027 EVEX_V512, EVEX_CD8<32, CD8VF>;
3028 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3029 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3030 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3031 EVEX, EVEX_V512, VEX_W;
3032 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3033 !strconcat(OpcodeStr,
3034 "pd\t{$src, $dst|$dst, $src}"),
3035 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3036 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3039 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3040 Intrinsic F32Int, Intrinsic F64Int,
3041 OpndItins itins_s, OpndItins itins_d> {
3042 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3043 (ins FR32X:$src1, FR32X:$src2),
3044 !strconcat(OpcodeStr,
3045 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3046 [], itins_s.rr>, XS, EVEX_4V;
3047 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3048 (ins VR128X:$src1, VR128X:$src2),
3049 !strconcat(OpcodeStr,
3050 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3052 (F32Int VR128X:$src1, VR128X:$src2))],
3053 itins_s.rr>, XS, EVEX_4V;
3054 let mayLoad = 1 in {
3055 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3056 (ins FR32X:$src1, f32mem:$src2),
3057 !strconcat(OpcodeStr,
3058 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3059 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3060 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3061 (ins VR128X:$src1, ssmem:$src2),
3062 !strconcat(OpcodeStr,
3063 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3065 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3066 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3068 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3069 (ins FR64X:$src1, FR64X:$src2),
3070 !strconcat(OpcodeStr,
3071 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3073 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3074 (ins VR128X:$src1, VR128X:$src2),
3075 !strconcat(OpcodeStr,
3076 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3078 (F64Int VR128X:$src1, VR128X:$src2))],
3079 itins_s.rr>, XD, EVEX_4V, VEX_W;
3080 let mayLoad = 1 in {
3081 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3082 (ins FR64X:$src1, f64mem:$src2),
3083 !strconcat(OpcodeStr,
3084 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3085 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3086 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3087 (ins VR128X:$src1, sdmem:$src2),
3088 !strconcat(OpcodeStr,
3089 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3091 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3092 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3097 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3098 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3099 SSE_SQRTSS, SSE_SQRTSD>,
3100 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3101 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3102 SSE_SQRTPS, SSE_SQRTPD>;
3104 let Predicates = [HasAVX512] in {
3105 def : Pat<(f32 (fsqrt FR32X:$src)),
3106 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3107 def : Pat<(f32 (fsqrt (load addr:$src))),
3108 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3109 Requires<[OptForSize]>;
3110 def : Pat<(f64 (fsqrt FR64X:$src)),
3111 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3112 def : Pat<(f64 (fsqrt (load addr:$src))),
3113 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3114 Requires<[OptForSize]>;
3116 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3117 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3118 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3119 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3120 Requires<[OptForSize]>;
3122 def : Pat<(f32 (X86frcp FR32X:$src)),
3123 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3124 def : Pat<(f32 (X86frcp (load addr:$src))),
3125 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3126 Requires<[OptForSize]>;
3128 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3129 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3130 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3132 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3133 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3135 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3136 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3137 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3139 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3140 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3144 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3145 X86MemOperand x86memop, RegisterClass RC,
3146 PatFrag mem_frag32, PatFrag mem_frag64,
3147 Intrinsic V4F32Int, Intrinsic V2F64Int,
3149 let ExeDomain = SSEPackedSingle in {
3150 // Intrinsic operation, reg.
3151 // Vector intrinsic operation, reg
3152 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3153 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3154 !strconcat(OpcodeStr,
3155 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3156 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3158 // Vector intrinsic operation, mem
3159 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3160 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3161 !strconcat(OpcodeStr,
3162 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3164 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3165 EVEX_CD8<32, VForm>;
3166 } // ExeDomain = SSEPackedSingle
3168 let ExeDomain = SSEPackedDouble in {
3169 // Vector intrinsic operation, reg
3170 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3171 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3172 !strconcat(OpcodeStr,
3173 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3174 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3176 // Vector intrinsic operation, mem
3177 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3178 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3179 !strconcat(OpcodeStr,
3180 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3182 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3183 EVEX_CD8<64, VForm>;
3184 } // ExeDomain = SSEPackedDouble
3187 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3191 let ExeDomain = GenericDomain in {
3193 let hasSideEffects = 0 in
3194 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3195 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3196 !strconcat(OpcodeStr,
3197 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3200 // Intrinsic operation, reg.
3201 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3202 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3203 !strconcat(OpcodeStr,
3204 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3205 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3207 // Intrinsic operation, mem.
3208 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3209 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3210 !strconcat(OpcodeStr,
3211 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3212 [(set VR128X:$dst, (F32Int VR128X:$src1,
3213 sse_load_f32:$src2, imm:$src3))]>,
3214 EVEX_CD8<32, CD8VT1>;
3217 let hasSideEffects = 0 in
3218 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3219 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3220 !strconcat(OpcodeStr,
3221 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3224 // Intrinsic operation, reg.
3225 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3226 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3227 !strconcat(OpcodeStr,
3228 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3229 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3232 // Intrinsic operation, mem.
3233 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3234 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3235 !strconcat(OpcodeStr,
3236 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3238 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3239 VEX_W, EVEX_CD8<64, CD8VT1>;
3240 } // ExeDomain = GenericDomain
3243 let Predicates = [HasAVX512] in {
3244 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3245 int_x86_avx512_rndscale_ss,
3246 int_x86_avx512_rndscale_sd>, EVEX_4V;
3248 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3249 memopv16f32, memopv8f64,
3250 int_x86_avx512_rndscale_ps_512,
3251 int_x86_avx512_rndscale_pd_512, CD8VF>,
3255 def : Pat<(ffloor FR32X:$src),
3256 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3257 def : Pat<(f64 (ffloor FR64X:$src)),
3258 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3259 def : Pat<(f32 (fnearbyint FR32X:$src)),
3260 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3261 def : Pat<(f64 (fnearbyint FR64X:$src)),
3262 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3263 def : Pat<(f32 (fceil FR32X:$src)),
3264 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3265 def : Pat<(f64 (fceil FR64X:$src)),
3266 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3267 def : Pat<(f32 (frint FR32X:$src)),
3268 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3269 def : Pat<(f64 (frint FR64X:$src)),
3270 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3271 def : Pat<(f32 (ftrunc FR32X:$src)),
3272 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3273 def : Pat<(f64 (ftrunc FR64X:$src)),
3274 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3276 def : Pat<(v16f32 (ffloor VR512:$src)),
3277 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3278 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3279 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3280 def : Pat<(v16f32 (fceil VR512:$src)),
3281 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3282 def : Pat<(v16f32 (frint VR512:$src)),
3283 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3284 def : Pat<(v16f32 (ftrunc VR512:$src)),
3285 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3287 def : Pat<(v8f64 (ffloor VR512:$src)),
3288 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3289 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3290 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3291 def : Pat<(v8f64 (fceil VR512:$src)),
3292 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3293 def : Pat<(v8f64 (frint VR512:$src)),
3294 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3295 def : Pat<(v8f64 (ftrunc VR512:$src)),
3296 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3298 //-------------------------------------------------
3299 // Integer truncate and extend operations
3300 //-------------------------------------------------
3302 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3303 RegisterClass dstRC, RegisterClass srcRC,
3304 RegisterClass KRC, X86MemOperand x86memop> {
3305 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3307 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3310 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3311 (ins KRC:$mask, srcRC:$src),
3312 !strconcat(OpcodeStr,
3313 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3316 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3317 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3320 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3321 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3322 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3323 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3324 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3325 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3326 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3327 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3328 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3329 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3330 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3331 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3332 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3333 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3334 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3335 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3336 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3337 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3338 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3339 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3340 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3341 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3342 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3343 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3344 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3345 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3346 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3347 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3348 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3349 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3351 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3352 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3353 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3354 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3355 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3357 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3358 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3359 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3360 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3361 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3362 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3363 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3364 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3367 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3368 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3369 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3371 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3373 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3374 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3375 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3376 (ins x86memop:$src),
3377 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3379 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3383 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3384 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3386 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3387 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3389 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3390 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3391 EVEX_CD8<16, CD8VH>;
3392 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3393 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3394 EVEX_CD8<16, CD8VQ>;
3395 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3396 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3397 EVEX_CD8<32, CD8VH>;
3399 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3400 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3402 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3403 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3405 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3406 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3407 EVEX_CD8<16, CD8VH>;
3408 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3409 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3410 EVEX_CD8<16, CD8VQ>;
3411 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3412 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3413 EVEX_CD8<32, CD8VH>;
3415 //===----------------------------------------------------------------------===//
3416 // GATHER - SCATTER Operations
3418 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3419 RegisterClass RC, X86MemOperand memop> {
3421 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3422 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3423 (ins RC:$src1, KRC:$mask, memop:$src2),
3424 !strconcat(OpcodeStr,
3425 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3428 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3429 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3430 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3431 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3433 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3434 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3435 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3436 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3438 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3439 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3440 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3441 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3443 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3444 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3445 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3446 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3448 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3449 RegisterClass RC, X86MemOperand memop> {
3450 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3451 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3452 (ins memop:$dst, KRC:$mask, RC:$src2),
3453 !strconcat(OpcodeStr,
3454 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3458 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3459 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3460 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3461 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3463 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3464 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3465 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3468 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3469 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3470 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3471 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3473 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3474 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3475 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3476 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3478 //===----------------------------------------------------------------------===//
3479 // VSHUFPS - VSHUFPD Operations
3481 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3482 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3484 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3485 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3486 !strconcat(OpcodeStr,
3487 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3488 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3489 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3490 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3491 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3492 (ins RC:$src1, RC:$src2, i8imm:$src3),
3493 !strconcat(OpcodeStr,
3494 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3495 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3496 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3497 EVEX_4V, Sched<[WriteShuffle]>;
3500 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3501 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3502 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3503 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3505 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3506 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3507 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3508 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3509 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3511 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3512 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3513 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3514 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3515 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3517 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3518 X86MemOperand x86memop> {
3519 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3520 (ins RC:$src1, RC:$src2, i8imm:$src3),
3521 !strconcat(OpcodeStr,
3522 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3525 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3526 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3527 !strconcat(OpcodeStr,
3528 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3531 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3532 EVEX_V512, EVEX_CD8<32, CD8VF>;
3533 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3534 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3536 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3537 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3538 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3539 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3540 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3541 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3542 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3543 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3545 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3546 X86MemOperand x86memop> {
3547 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3548 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3550 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3551 (ins x86memop:$src),
3552 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3556 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3557 EVEX_CD8<32, CD8VF>;
3558 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3559 EVEX_CD8<64, CD8VF>;
3561 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3562 RegisterClass RC, RegisterClass KRC,
3563 X86MemOperand x86memop,
3564 X86MemOperand x86scalar_mop, string BrdcstStr> {
3565 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3567 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3569 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3570 (ins x86memop:$src),
3571 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3573 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3574 (ins x86scalar_mop:$src),
3575 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3576 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3578 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3579 (ins KRC:$mask, RC:$src),
3580 !strconcat(OpcodeStr,
3581 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3583 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3584 (ins KRC:$mask, x86memop:$src),
3585 !strconcat(OpcodeStr,
3586 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3588 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3589 (ins KRC:$mask, x86scalar_mop:$src),
3590 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3591 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3593 []>, EVEX, EVEX_KZ, EVEX_B;
3595 let Constraints = "$src1 = $dst" in {
3596 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3597 (ins RC:$src1, KRC:$mask, RC:$src2),
3598 !strconcat(OpcodeStr,
3599 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3601 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3602 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3603 !strconcat(OpcodeStr,
3604 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3606 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3607 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3608 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3609 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3610 []>, EVEX, EVEX_K, EVEX_B;
3614 let Predicates = [HasCDI] in {
3615 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3616 i512mem, i32mem, "{1to16}">,
3617 EVEX_V512, EVEX_CD8<32, CD8VF>;
3620 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3621 i512mem, i64mem, "{1to8}">,
3622 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3626 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3628 (VPCONFLICTDrrk VR512:$src1,
3629 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3631 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3633 (VPCONFLICTQrrk VR512:$src1,
3634 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;