1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
183 string MaskingConstraint = "",
184 InstrItinClass itin = NoItinerary,
185 bit IsCommutable = 0> {
186 let isCommutable = IsCommutable in
187 def NAME: AVX512<O, F, Outs, Ins,
188 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
189 "$dst , "#IntelSrcAsm#"}",
192 // Prefer over VMOV*rrk Pat<>
193 let AddedComplexity = 20 in
194 def NAME#k: AVX512<O, F, Outs, MaskingIns,
195 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
196 "$dst {${mask}}, "#IntelSrcAsm#"}",
197 MaskingPattern, itin>,
199 // In case of the 3src subclass this is overridden with a let.
200 string Constraints = MaskingConstraint;
202 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
203 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
204 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
205 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
212 // Common base class of AVX512_maskable and AVX512_maskable_3src.
213 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
215 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, dag MaskingRHS,
219 SDNode Select = vselect,
220 string MaskingConstraint = "",
221 InstrItinClass itin = NoItinerary,
222 bit IsCommutable = 0> :
223 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
224 AttSrcAsm, IntelSrcAsm,
225 [(set _.RC:$dst, RHS)],
226 [(set _.RC:$dst, MaskingRHS)],
228 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
229 MaskingConstraint, NoItinerary, IsCommutable>;
231 // This multiclass generates the unconditional/non-masking, the masking and
232 // the zero-masking variant of the vector instruction. In the masking case, the
233 // perserved vector elements come from a new dummy input operand tied to $dst.
234 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
235 dag Outs, dag Ins, string OpcodeStr,
236 string AttSrcAsm, string IntelSrcAsm,
238 InstrItinClass itin = NoItinerary,
239 bit IsCommutable = 0> :
240 AVX512_maskable_common<O, F, _, Outs, Ins,
241 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
242 !con((ins _.KRCWM:$mask), Ins),
243 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
244 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
245 "$src0 = $dst", itin, IsCommutable>;
247 // This multiclass generates the unconditional/non-masking, the masking and
248 // the zero-masking variant of the scalar instruction.
249 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
250 dag Outs, dag Ins, string OpcodeStr,
251 string AttSrcAsm, string IntelSrcAsm,
253 InstrItinClass itin = NoItinerary,
254 bit IsCommutable = 0> :
255 AVX512_maskable_common<O, F, _, Outs, Ins,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
257 !con((ins _.KRCWM:$mask), Ins),
258 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
259 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
260 "$src0 = $dst", itin, IsCommutable>;
262 // Similar to AVX512_maskable but in this case one of the source operands
263 // ($src1) is already tied to $dst so we just use that for the preserved
264 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
266 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
267 dag Outs, dag NonTiedIns, string OpcodeStr,
268 string AttSrcAsm, string IntelSrcAsm,
270 AVX512_maskable_common<O, F, _, Outs,
271 !con((ins _.RC:$src1), NonTiedIns),
272 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
275 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
278 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_custom<O, F, Outs, Ins,
284 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
285 !con((ins _.KRCWM:$mask), Ins),
286 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
290 // Instruction with mask that puts result in mask register,
291 // like "compare" and "vptest"
292 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
294 dag Ins, dag MaskingIns,
296 string AttSrcAsm, string IntelSrcAsm,
298 list<dag> MaskingPattern,
300 InstrItinClass itin = NoItinerary> {
301 def NAME: AVX512<O, F, Outs, Ins,
302 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
303 "$dst "#Round#", "#IntelSrcAsm#"}",
306 def NAME#k: AVX512<O, F, Outs, MaskingIns,
307 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
308 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
309 MaskingPattern, itin>, EVEX_K;
312 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
314 dag Ins, dag MaskingIns,
316 string AttSrcAsm, string IntelSrcAsm,
317 dag RHS, dag MaskingRHS,
319 InstrItinClass itin = NoItinerary> :
320 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
321 AttSrcAsm, IntelSrcAsm,
322 [(set _.KRC:$dst, RHS)],
323 [(set _.KRC:$dst, MaskingRHS)],
326 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
327 dag Outs, dag Ins, string OpcodeStr,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, string Round = "",
330 InstrItinClass itin = NoItinerary> :
331 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
332 !con((ins _.KRCWM:$mask), Ins),
333 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
334 (and _.KRCWM:$mask, RHS),
337 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
338 dag Outs, dag Ins, string OpcodeStr,
339 string AttSrcAsm, string IntelSrcAsm> :
340 AVX512_maskable_custom_cmp<O, F, Outs,
341 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
342 AttSrcAsm, IntelSrcAsm,
343 [],[],"", NoItinerary>;
345 // Bitcasts between 512-bit vector types. Return the original type since
346 // no instruction is needed for the conversion
347 let Predicates = [HasAVX512] in {
348 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
349 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
350 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
351 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
352 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
353 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
354 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
355 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
356 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
357 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
358 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
359 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
360 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
361 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
362 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
363 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
364 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
365 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
366 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
367 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
368 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
369 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
370 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
371 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
372 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
373 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
374 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
375 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
376 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
377 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
378 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
380 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
381 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
382 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
383 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
384 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
385 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
386 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
387 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
388 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
389 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
390 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
391 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
392 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
393 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
394 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
395 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
396 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
397 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
398 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
399 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
400 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
401 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
402 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
403 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
404 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
405 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
406 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
407 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
408 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
409 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
411 // Bitcasts between 256-bit vector types. Return the original type since
412 // no instruction is needed for the conversion
413 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
414 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
415 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
416 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
417 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
418 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
419 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
420 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
421 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
422 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
423 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
424 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
425 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
426 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
427 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
428 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
429 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
430 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
431 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
432 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
433 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
434 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
435 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
436 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
437 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
438 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
439 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
440 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
441 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
442 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
446 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
449 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
450 isPseudo = 1, Predicates = [HasAVX512] in {
451 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
452 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
455 let Predicates = [HasAVX512] in {
456 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
457 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
458 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
461 //===----------------------------------------------------------------------===//
462 // AVX-512 - VECTOR INSERT
465 multiclass vinsert_for_size_no_alt<int Opcode,
466 X86VectorVTInfo From, X86VectorVTInfo To,
467 PatFrag vinsert_insert,
468 SDNodeXForm INSERT_get_vinsert_imm> {
469 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
470 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
471 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
472 "vinsert" # From.EltTypeName # "x" # From.NumElts #
473 "\t{$src3, $src2, $src1, $dst|"
474 "$dst, $src1, $src2, $src3}",
475 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
476 (From.VT From.RC:$src2),
481 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
482 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
483 "vinsert" # From.EltTypeName # "x" # From.NumElts #
484 "\t{$src3, $src2, $src1, $dst|"
485 "$dst, $src1, $src2, $src3}",
487 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
491 multiclass vinsert_for_size<int Opcode,
492 X86VectorVTInfo From, X86VectorVTInfo To,
493 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
494 PatFrag vinsert_insert,
495 SDNodeXForm INSERT_get_vinsert_imm> :
496 vinsert_for_size_no_alt<Opcode, From, To,
497 vinsert_insert, INSERT_get_vinsert_imm> {
498 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
499 // vinserti32x4. Only add this if 64x2 and friends are not supported
500 // natively via AVX512DQ.
501 let Predicates = [NoDQI] in
502 def : Pat<(vinsert_insert:$ins
503 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
504 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
505 VR512:$src1, From.RC:$src2,
506 (INSERT_get_vinsert_imm VR512:$ins)))>;
509 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
510 ValueType EltVT64, int Opcode256> {
511 defm NAME # "32x4" : vinsert_for_size<Opcode128,
512 X86VectorVTInfo< 4, EltVT32, VR128X>,
513 X86VectorVTInfo<16, EltVT32, VR512>,
514 X86VectorVTInfo< 2, EltVT64, VR128X>,
515 X86VectorVTInfo< 8, EltVT64, VR512>,
517 INSERT_get_vinsert128_imm>;
518 let Predicates = [HasDQI] in
519 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
520 X86VectorVTInfo< 2, EltVT64, VR128X>,
521 X86VectorVTInfo< 8, EltVT64, VR512>,
523 INSERT_get_vinsert128_imm>, VEX_W;
524 defm NAME # "64x4" : vinsert_for_size<Opcode256,
525 X86VectorVTInfo< 4, EltVT64, VR256X>,
526 X86VectorVTInfo< 8, EltVT64, VR512>,
527 X86VectorVTInfo< 8, EltVT32, VR256>,
528 X86VectorVTInfo<16, EltVT32, VR512>,
530 INSERT_get_vinsert256_imm>, VEX_W;
531 let Predicates = [HasDQI] in
532 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
533 X86VectorVTInfo< 8, EltVT32, VR256X>,
534 X86VectorVTInfo<16, EltVT32, VR512>,
536 INSERT_get_vinsert256_imm>;
539 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
540 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
542 // vinsertps - insert f32 to XMM
543 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
544 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
545 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
546 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
548 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
549 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
550 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
551 [(set VR128X:$dst, (X86insertps VR128X:$src1,
552 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
553 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
555 //===----------------------------------------------------------------------===//
556 // AVX-512 VECTOR EXTRACT
559 multiclass vextract_for_size<int Opcode,
560 X86VectorVTInfo From, X86VectorVTInfo To,
561 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
562 PatFrag vextract_extract,
563 SDNodeXForm EXTRACT_get_vextract_imm> {
564 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
565 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
566 (ins VR512:$src1, u8imm:$idx),
567 "vextract" # To.EltTypeName # "x4",
568 "$idx, $src1", "$src1, $idx",
569 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
571 AVX512AIi8Base, EVEX, EVEX_V512;
573 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
574 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
575 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
576 "$dst, $src1, $src2}",
577 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
580 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
582 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
583 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
585 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
587 // A 128/256-bit subvector extract from the first 512-bit vector position is
588 // a subregister copy that needs no instruction.
589 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
591 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
593 // And for the alternative types.
594 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
596 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
598 // Intrinsic call with masking.
599 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
601 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
602 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
603 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
604 VR512:$src1, imm:$idx)>;
606 // Intrinsic call with zero-masking.
607 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
609 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
610 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
611 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
612 VR512:$src1, imm:$idx)>;
614 // Intrinsic call without masking.
615 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
617 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
618 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
619 VR512:$src1, imm:$idx)>;
622 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
623 ValueType EltVT64, int Opcode64> {
624 defm NAME # "32x4" : vextract_for_size<Opcode32,
625 X86VectorVTInfo<16, EltVT32, VR512>,
626 X86VectorVTInfo< 4, EltVT32, VR128X>,
627 X86VectorVTInfo< 8, EltVT64, VR512>,
628 X86VectorVTInfo< 2, EltVT64, VR128X>,
630 EXTRACT_get_vextract128_imm>;
631 defm NAME # "64x4" : vextract_for_size<Opcode64,
632 X86VectorVTInfo< 8, EltVT64, VR512>,
633 X86VectorVTInfo< 4, EltVT64, VR256X>,
634 X86VectorVTInfo<16, EltVT32, VR512>,
635 X86VectorVTInfo< 8, EltVT32, VR256>,
637 EXTRACT_get_vextract256_imm>, VEX_W;
640 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
641 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
643 // A 128-bit subvector insert to the first 512-bit vector position
644 // is a subregister copy that needs no instruction.
645 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
646 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
647 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
649 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
650 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
651 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
653 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
654 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
655 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
657 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
658 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
659 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
662 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
663 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
664 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
665 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
666 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
667 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
668 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
669 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
671 // vextractps - extract 32 bits from XMM
672 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
673 (ins VR128X:$src1, u8imm:$src2),
674 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
675 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
678 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
679 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
680 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
681 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
682 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
684 //===---------------------------------------------------------------------===//
687 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
688 ValueType svt, X86VectorVTInfo _> {
689 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
690 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
691 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
695 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
696 (ins _.ScalarMemOp:$src),
697 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
698 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
703 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
704 AVX512VLVectorVTInfo _> {
705 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
708 let Predicates = [HasVLX] in {
709 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
714 let ExeDomain = SSEPackedSingle in {
715 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
716 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
717 let Predicates = [HasVLX] in {
718 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
719 v4f32, v4f32x_info>, EVEX_V128,
720 EVEX_CD8<32, CD8VT1>;
724 let ExeDomain = SSEPackedDouble in {
725 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
726 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
729 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
730 // Later, we can canonize broadcast instructions before ISel phase and
731 // eliminate additional patterns on ISel.
732 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
733 // representations of source
734 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
735 X86VectorVTInfo _, RegisterClass SrcRC_v,
736 RegisterClass SrcRC_s> {
737 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
738 (!cast<Instruction>(InstName##"r")
739 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
741 let AddedComplexity = 30 in {
742 def : Pat<(_.VT (vselect _.KRCWM:$mask,
743 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
744 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
745 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
747 def : Pat<(_.VT(vselect _.KRCWM:$mask,
748 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
749 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
750 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
754 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
756 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
759 let Predicates = [HasVLX] in {
760 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
761 v8f32x_info, VR128X, FR32X>;
762 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
763 v4f32x_info, VR128X, FR32X>;
764 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
765 v4f64x_info, VR128X, FR64X>;
768 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
769 (VBROADCASTSSZm addr:$src)>;
770 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
771 (VBROADCASTSDZm addr:$src)>;
773 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
774 (VBROADCASTSSZm addr:$src)>;
775 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
776 (VBROADCASTSDZm addr:$src)>;
778 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
779 RegisterClass SrcRC> {
780 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
781 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
782 "$src", "$src", []>, T8PD, EVEX;
785 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
786 RegisterClass SrcRC, Predicate prd> {
787 let Predicates = [prd] in
788 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
789 let Predicates = [prd, HasVLX] in {
790 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
791 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
795 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
797 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
799 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
801 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
804 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
805 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
807 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
808 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
810 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
811 (VPBROADCASTDrZr GR32:$src)>;
812 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
813 (VPBROADCASTQrZr GR64:$src)>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
816 (VPBROADCASTDrZr GR32:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
818 (VPBROADCASTQrZr GR64:$src)>;
820 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
821 (v16i32 immAllZerosV), (i16 GR16:$mask))),
822 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
823 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
824 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
825 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
827 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86MemOperand x86memop, PatFrag ld_frag,
829 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
831 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
832 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
834 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
835 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
837 !strconcat(OpcodeStr,
838 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
840 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
842 !strconcat(OpcodeStr,
843 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
846 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
849 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
850 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
852 !strconcat(OpcodeStr,
853 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
855 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
857 !strconcat(OpcodeStr,
858 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
859 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
860 (X86VBroadcast (ld_frag addr:$src)),
861 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
865 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
866 loadi32, VR512, v16i32, v4i32, VK16WM>,
867 EVEX_V512, EVEX_CD8<32, CD8VT1>;
868 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
869 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
870 EVEX_CD8<64, CD8VT1>;
872 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
873 X86MemOperand x86memop, PatFrag ld_frag,
876 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
877 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
879 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
881 !strconcat(OpcodeStr,
882 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
887 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
888 i128mem, loadv2i64, VK16WM>,
889 EVEX_V512, EVEX_CD8<32, CD8VT4>;
890 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
891 i256mem, loadv4i64, VK16WM>, VEX_W,
892 EVEX_V512, EVEX_CD8<64, CD8VT4>;
894 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
895 (VPBROADCASTDZrr VR128X:$src)>;
896 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
897 (VPBROADCASTQZrr VR128X:$src)>;
899 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
900 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
901 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
902 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
904 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
905 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
906 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
907 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
909 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
910 (VBROADCASTSSZr VR128X:$src)>;
911 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
912 (VBROADCASTSDZr VR128X:$src)>;
914 // Provide fallback in case the load node that is used in the patterns above
915 // is used by additional users, which prevents the pattern selection.
916 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
917 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
918 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
919 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
922 //===----------------------------------------------------------------------===//
923 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
926 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
928 let Predicates = [HasCDI] in
929 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
930 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
931 []>, EVEX, EVEX_V512;
933 let Predicates = [HasCDI, HasVLX] in {
934 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
935 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
936 []>, EVEX, EVEX_V128;
937 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
938 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
939 []>, EVEX, EVEX_V256;
943 let Predicates = [HasCDI] in {
944 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
946 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
950 //===----------------------------------------------------------------------===//
953 // -- immediate form --
954 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
956 let ExeDomain = _.ExeDomain in {
957 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
958 (ins _.RC:$src1, u8imm:$src2),
959 !strconcat(OpcodeStr,
960 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
962 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
964 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
965 (ins _.MemOp:$src1, u8imm:$src2),
966 !strconcat(OpcodeStr,
967 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
969 (_.VT (OpNode (_.LdFrag addr:$src1),
971 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
975 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
976 X86VectorVTInfo Ctrl> :
977 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
978 let ExeDomain = _.ExeDomain in {
979 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
980 (ins _.RC:$src1, _.RC:$src2),
981 !strconcat("vpermil" # _.Suffix,
982 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
984 (_.VT (X86VPermilpv _.RC:$src1,
985 (Ctrl.VT Ctrl.RC:$src2))))]>,
987 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
988 (ins _.RC:$src1, Ctrl.MemOp:$src2),
989 !strconcat("vpermil" # _.Suffix,
990 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
992 (_.VT (X86VPermilpv _.RC:$src1,
993 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
998 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
1000 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
1003 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
1005 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1008 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1009 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1010 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1011 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1013 // -- VPERM - register form --
1014 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1015 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
1017 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1018 (ins RC:$src1, RC:$src2),
1019 !strconcat(OpcodeStr,
1020 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1022 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
1024 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1025 (ins RC:$src1, x86memop:$src2),
1026 !strconcat(OpcodeStr,
1027 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1029 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
1033 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, loadv16i32, i512mem,
1034 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1035 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, loadv8i64, i512mem,
1036 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1037 let ExeDomain = SSEPackedSingle in
1038 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, loadv16f32, f512mem,
1039 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1040 let ExeDomain = SSEPackedDouble in
1041 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, loadv8f64, f512mem,
1042 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1044 // -- VPERM2I - 3 source operands form --
1045 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
1046 PatFrag mem_frag, X86MemOperand x86memop,
1047 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
1048 let Constraints = "$src1 = $dst" in {
1049 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1050 (ins RC:$src1, RC:$src2, RC:$src3),
1051 !strconcat(OpcodeStr,
1052 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1054 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
1057 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1058 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1059 !strconcat(OpcodeStr,
1060 "\t{$src3, $src2, $dst {${mask}}|"
1061 "$dst {${mask}}, $src2, $src3}"),
1062 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1063 (OpNode RC:$src1, RC:$src2,
1068 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
1069 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1070 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
1071 !strconcat(OpcodeStr,
1072 "\t{$src3, $src2, $dst {${mask}} {z} |",
1073 "$dst {${mask}} {z}, $src2, $src3}"),
1074 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1075 (OpNode RC:$src1, RC:$src2,
1078 (v16i32 immAllZerosV))))))]>,
1081 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1082 (ins RC:$src1, RC:$src2, x86memop:$src3),
1083 !strconcat(OpcodeStr,
1084 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1086 (OpVT (OpNode RC:$src1, RC:$src2,
1087 (mem_frag addr:$src3))))]>, EVEX_4V;
1089 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1090 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1091 !strconcat(OpcodeStr,
1092 "\t{$src3, $src2, $dst {${mask}}|"
1093 "$dst {${mask}}, $src2, $src3}"),
1095 (OpVT (vselect KRC:$mask,
1096 (OpNode RC:$src1, RC:$src2,
1097 (mem_frag addr:$src3)),
1101 let AddedComplexity = 10 in // Prefer over the rrkz variant
1102 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1103 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1104 !strconcat(OpcodeStr,
1105 "\t{$src3, $src2, $dst {${mask}} {z}|"
1106 "$dst {${mask}} {z}, $src2, $src3}"),
1108 (OpVT (vselect KRC:$mask,
1109 (OpNode RC:$src1, RC:$src2,
1110 (mem_frag addr:$src3)),
1112 (v16i32 immAllZerosV))))))]>,
1116 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, loadv16i32,
1117 i512mem, X86VPermiv3, v16i32, VK16WM>,
1118 EVEX_V512, EVEX_CD8<32, CD8VF>;
1119 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, loadv8i64,
1120 i512mem, X86VPermiv3, v8i64, VK8WM>,
1121 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1122 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, loadv16f32,
1123 i512mem, X86VPermiv3, v16f32, VK16WM>,
1124 EVEX_V512, EVEX_CD8<32, CD8VF>;
1125 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, loadv8f64,
1126 i512mem, X86VPermiv3, v8f64, VK8WM>,
1127 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1129 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1130 PatFrag mem_frag, X86MemOperand x86memop,
1131 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1132 ValueType MaskVT, RegisterClass MRC> :
1133 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1135 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1136 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1137 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1139 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1140 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1141 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1142 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1145 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, loadv16i32, i512mem,
1146 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1147 EVEX_V512, EVEX_CD8<32, CD8VF>;
1148 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, loadv8i64, i512mem,
1149 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1150 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1151 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, loadv16f32, i512mem,
1152 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1153 EVEX_V512, EVEX_CD8<32, CD8VF>;
1154 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, loadv8f64, i512mem,
1155 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1156 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1158 //===----------------------------------------------------------------------===//
1159 // AVX-512 - BLEND using mask
1161 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1162 let ExeDomain = _.ExeDomain in {
1163 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1164 (ins _.RC:$src1, _.RC:$src2),
1165 !strconcat(OpcodeStr,
1166 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1168 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1169 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1170 !strconcat(OpcodeStr,
1171 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1172 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1173 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1174 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1175 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1176 !strconcat(OpcodeStr,
1177 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1178 []>, EVEX_4V, EVEX_KZ;
1179 let mayLoad = 1 in {
1180 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1181 (ins _.RC:$src1, _.MemOp:$src2),
1182 !strconcat(OpcodeStr,
1183 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1184 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1185 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1186 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1187 !strconcat(OpcodeStr,
1188 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1189 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1190 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1191 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1192 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1193 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1194 !strconcat(OpcodeStr,
1195 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1196 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1200 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1202 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1203 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1204 !strconcat(OpcodeStr,
1205 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1206 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1207 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1208 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1209 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1211 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1212 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1213 !strconcat(OpcodeStr,
1214 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1215 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1216 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1220 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1221 AVX512VLVectorVTInfo VTInfo> {
1222 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1223 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1225 let Predicates = [HasVLX] in {
1226 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1227 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1228 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1229 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1233 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1234 AVX512VLVectorVTInfo VTInfo> {
1235 let Predicates = [HasBWI] in
1236 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1238 let Predicates = [HasBWI, HasVLX] in {
1239 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1240 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1245 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1246 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1247 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1248 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1249 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1250 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1253 let Predicates = [HasAVX512] in {
1254 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1255 (v8f32 VR256X:$src2))),
1257 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1258 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1259 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1261 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1262 (v8i32 VR256X:$src2))),
1264 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1265 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1266 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1268 //===----------------------------------------------------------------------===//
1269 // Compare Instructions
1270 //===----------------------------------------------------------------------===//
1272 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1273 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1274 SDNode OpNode, ValueType VT,
1275 PatFrag ld_frag, string Suffix> {
1276 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1277 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1278 !strconcat("vcmp${cc}", Suffix,
1279 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1280 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1281 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1282 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1283 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1284 !strconcat("vcmp${cc}", Suffix,
1285 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1286 [(set VK1:$dst, (OpNode (VT RC:$src1),
1287 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1288 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1289 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1290 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1291 !strconcat("vcmp", Suffix,
1292 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1293 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1295 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1296 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1297 !strconcat("vcmp", Suffix,
1298 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1299 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1303 let Predicates = [HasAVX512] in {
1304 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1306 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1310 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1311 X86VectorVTInfo _> {
1312 def rr : AVX512BI<opc, MRMSrcReg,
1313 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1314 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1315 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1316 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1318 def rm : AVX512BI<opc, MRMSrcMem,
1319 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1320 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1321 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1322 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1323 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1324 def rrk : AVX512BI<opc, MRMSrcReg,
1325 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1326 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1327 "$dst {${mask}}, $src1, $src2}"),
1328 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1329 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1330 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1332 def rmk : AVX512BI<opc, MRMSrcMem,
1333 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1334 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1335 "$dst {${mask}}, $src1, $src2}"),
1336 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1337 (OpNode (_.VT _.RC:$src1),
1339 (_.LdFrag addr:$src2))))))],
1340 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1343 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1344 X86VectorVTInfo _> :
1345 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1346 let mayLoad = 1 in {
1347 def rmb : AVX512BI<opc, MRMSrcMem,
1348 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1349 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1350 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1351 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1352 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1353 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1354 def rmbk : AVX512BI<opc, MRMSrcMem,
1355 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1356 _.ScalarMemOp:$src2),
1357 !strconcat(OpcodeStr,
1358 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1359 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1360 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1361 (OpNode (_.VT _.RC:$src1),
1363 (_.ScalarLdFrag addr:$src2)))))],
1364 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1368 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1369 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1370 let Predicates = [prd] in
1371 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1374 let Predicates = [prd, HasVLX] in {
1375 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1377 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1382 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1383 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1385 let Predicates = [prd] in
1386 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1389 let Predicates = [prd, HasVLX] in {
1390 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1392 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1397 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1398 avx512vl_i8_info, HasBWI>,
1401 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1402 avx512vl_i16_info, HasBWI>,
1403 EVEX_CD8<16, CD8VF>;
1405 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1406 avx512vl_i32_info, HasAVX512>,
1407 EVEX_CD8<32, CD8VF>;
1409 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1410 avx512vl_i64_info, HasAVX512>,
1411 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1413 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1414 avx512vl_i8_info, HasBWI>,
1417 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1418 avx512vl_i16_info, HasBWI>,
1419 EVEX_CD8<16, CD8VF>;
1421 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1422 avx512vl_i32_info, HasAVX512>,
1423 EVEX_CD8<32, CD8VF>;
1425 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1426 avx512vl_i64_info, HasAVX512>,
1427 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1429 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1430 (COPY_TO_REGCLASS (VPCMPGTDZrr
1431 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1432 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1434 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1435 (COPY_TO_REGCLASS (VPCMPEQDZrr
1436 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1437 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1439 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1440 X86VectorVTInfo _> {
1441 def rri : AVX512AIi8<opc, MRMSrcReg,
1442 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1443 !strconcat("vpcmp${cc}", Suffix,
1444 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1445 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1447 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1449 def rmi : AVX512AIi8<opc, MRMSrcMem,
1450 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1451 !strconcat("vpcmp${cc}", Suffix,
1452 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1453 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1454 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1456 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1457 def rrik : AVX512AIi8<opc, MRMSrcReg,
1458 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1460 !strconcat("vpcmp${cc}", Suffix,
1461 "\t{$src2, $src1, $dst {${mask}}|",
1462 "$dst {${mask}}, $src1, $src2}"),
1463 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1464 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1466 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1468 def rmik : AVX512AIi8<opc, MRMSrcMem,
1469 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1471 !strconcat("vpcmp${cc}", Suffix,
1472 "\t{$src2, $src1, $dst {${mask}}|",
1473 "$dst {${mask}}, $src1, $src2}"),
1474 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1475 (OpNode (_.VT _.RC:$src1),
1476 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1478 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1480 // Accept explicit immediate argument form instead of comparison code.
1481 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1482 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1483 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1484 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1485 "$dst, $src1, $src2, $cc}"),
1486 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1488 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1489 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1490 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1491 "$dst, $src1, $src2, $cc}"),
1492 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1493 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1494 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1496 !strconcat("vpcmp", Suffix,
1497 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1498 "$dst {${mask}}, $src1, $src2, $cc}"),
1499 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1501 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1502 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1504 !strconcat("vpcmp", Suffix,
1505 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1506 "$dst {${mask}}, $src1, $src2, $cc}"),
1507 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1511 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1512 X86VectorVTInfo _> :
1513 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1514 def rmib : AVX512AIi8<opc, MRMSrcMem,
1515 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1517 !strconcat("vpcmp${cc}", Suffix,
1518 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1519 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1520 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1521 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1523 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1524 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1525 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1526 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1527 !strconcat("vpcmp${cc}", Suffix,
1528 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1529 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1530 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1531 (OpNode (_.VT _.RC:$src1),
1532 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1534 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1536 // Accept explicit immediate argument form instead of comparison code.
1537 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1538 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1539 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1541 !strconcat("vpcmp", Suffix,
1542 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1543 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1544 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1545 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1546 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1547 _.ScalarMemOp:$src2, u8imm:$cc),
1548 !strconcat("vpcmp", Suffix,
1549 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1550 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1551 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1555 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1556 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1557 let Predicates = [prd] in
1558 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1560 let Predicates = [prd, HasVLX] in {
1561 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1562 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1566 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1567 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1568 let Predicates = [prd] in
1569 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1572 let Predicates = [prd, HasVLX] in {
1573 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1575 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1580 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1581 HasBWI>, EVEX_CD8<8, CD8VF>;
1582 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1583 HasBWI>, EVEX_CD8<8, CD8VF>;
1585 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1586 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1587 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1588 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1590 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1591 HasAVX512>, EVEX_CD8<32, CD8VF>;
1592 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1593 HasAVX512>, EVEX_CD8<32, CD8VF>;
1595 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1596 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1597 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1598 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1600 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1602 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1603 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1604 "vcmp${cc}"#_.Suffix,
1605 "$src2, $src1", "$src1, $src2",
1606 (X86cmpm (_.VT _.RC:$src1),
1610 let mayLoad = 1 in {
1611 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1612 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1613 "vcmp${cc}"#_.Suffix,
1614 "$src2, $src1", "$src1, $src2",
1615 (X86cmpm (_.VT _.RC:$src1),
1616 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1619 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1621 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1622 "vcmp${cc}"#_.Suffix,
1623 "${src2}"##_.BroadcastStr##", $src1",
1624 "$src1, ${src2}"##_.BroadcastStr,
1625 (X86cmpm (_.VT _.RC:$src1),
1626 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1629 // Accept explicit immediate argument form instead of comparison code.
1630 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1631 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1633 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1635 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1637 let mayLoad = 1 in {
1638 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1640 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1642 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1644 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1646 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1648 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1649 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1654 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1655 // comparison code form (VCMP[EQ/LT/LE/...]
1656 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1657 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1658 "vcmp${cc}"#_.Suffix,
1659 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1660 (X86cmpmRnd (_.VT _.RC:$src1),
1663 (i32 FROUND_NO_EXC))>, EVEX_B;
1665 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1666 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1668 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1670 "$cc,{sae}, $src2, $src1",
1671 "$src1, $src2,{sae}, $cc">, EVEX_B;
1675 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1676 let Predicates = [HasAVX512] in {
1677 defm Z : avx512_vcmp_common<_.info512>,
1678 avx512_vcmp_sae<_.info512>, EVEX_V512;
1681 let Predicates = [HasAVX512,HasVLX] in {
1682 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1683 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1687 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1688 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1689 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1690 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1692 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1693 (COPY_TO_REGCLASS (VCMPPSZrri
1694 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1695 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1697 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1698 (COPY_TO_REGCLASS (VPCMPDZrri
1699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1700 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1702 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1703 (COPY_TO_REGCLASS (VPCMPUDZrri
1704 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1705 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1708 //-----------------------------------------------------------------
1709 // Mask register copy, including
1710 // - copy between mask registers
1711 // - load/store mask registers
1712 // - copy from GPR to mask register and vice versa
1714 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1715 string OpcodeStr, RegisterClass KRC,
1716 ValueType vvt, X86MemOperand x86memop> {
1717 let hasSideEffects = 0 in {
1718 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1719 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1721 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1722 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1723 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1725 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1726 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1727 [(store KRC:$src, addr:$dst)]>;
1731 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1733 RegisterClass KRC, RegisterClass GRC> {
1734 let hasSideEffects = 0 in {
1735 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1736 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1737 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1738 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1742 let Predicates = [HasDQI] in
1743 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1744 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1747 let Predicates = [HasAVX512] in
1748 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1749 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1752 let Predicates = [HasBWI] in {
1753 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1755 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1759 let Predicates = [HasBWI] in {
1760 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1762 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1766 // GR from/to mask register
1767 let Predicates = [HasDQI] in {
1768 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1769 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1770 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1771 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1773 let Predicates = [HasAVX512] in {
1774 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1775 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1776 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1777 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1779 let Predicates = [HasBWI] in {
1780 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1781 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1783 let Predicates = [HasBWI] in {
1784 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1785 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1789 let Predicates = [HasDQI] in {
1790 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1791 (KMOVBmk addr:$dst, VK8:$src)>;
1792 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1793 (KMOVBkm addr:$src)>;
1795 let Predicates = [HasAVX512, NoDQI] in {
1796 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1797 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1798 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1799 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1801 let Predicates = [HasAVX512] in {
1802 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1803 (KMOVWmk addr:$dst, VK16:$src)>;
1804 def : Pat<(i1 (load addr:$src)),
1805 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1806 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1807 (KMOVWkm addr:$src)>;
1809 let Predicates = [HasBWI] in {
1810 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1811 (KMOVDmk addr:$dst, VK32:$src)>;
1812 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1813 (KMOVDkm addr:$src)>;
1815 let Predicates = [HasBWI] in {
1816 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1817 (KMOVQmk addr:$dst, VK64:$src)>;
1818 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1819 (KMOVQkm addr:$src)>;
1822 let Predicates = [HasAVX512] in {
1823 def : Pat<(i1 (trunc (i64 GR64:$src))),
1824 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1827 def : Pat<(i1 (trunc (i32 GR32:$src))),
1828 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1830 def : Pat<(i1 (trunc (i8 GR8:$src))),
1832 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1834 def : Pat<(i1 (trunc (i16 GR16:$src))),
1836 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1839 def : Pat<(i32 (zext VK1:$src)),
1840 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1841 def : Pat<(i8 (zext VK1:$src)),
1844 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1845 def : Pat<(i64 (zext VK1:$src)),
1846 (AND64ri8 (SUBREG_TO_REG (i64 0),
1847 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1848 def : Pat<(i16 (zext VK1:$src)),
1850 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1852 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1853 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1854 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1855 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1857 let Predicates = [HasBWI] in {
1858 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1859 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1860 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1861 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1865 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1866 let Predicates = [HasAVX512, NoDQI] in {
1867 // GR from/to 8-bit mask without native support
1868 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1870 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1872 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1874 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1877 let Predicates = [HasAVX512] in {
1878 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1879 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1880 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1881 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1883 let Predicates = [HasBWI] in {
1884 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1885 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1886 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1887 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1890 // Mask unary operation
1892 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1893 RegisterClass KRC, SDPatternOperator OpNode,
1895 let Predicates = [prd] in
1896 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1897 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1898 [(set KRC:$dst, (OpNode KRC:$src))]>;
1901 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1902 SDPatternOperator OpNode> {
1903 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1905 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1906 HasAVX512>, VEX, PS;
1907 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1908 HasBWI>, VEX, PD, VEX_W;
1909 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1910 HasBWI>, VEX, PS, VEX_W;
1913 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1915 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1916 let Predicates = [HasAVX512] in
1917 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1919 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1920 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1922 defm : avx512_mask_unop_int<"knot", "KNOT">;
1924 let Predicates = [HasDQI] in
1925 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1926 let Predicates = [HasAVX512] in
1927 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1928 let Predicates = [HasBWI] in
1929 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1930 let Predicates = [HasBWI] in
1931 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1933 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1934 let Predicates = [HasAVX512, NoDQI] in {
1935 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1936 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1937 def : Pat<(not VK8:$src),
1939 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1941 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
1942 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
1943 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
1944 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
1946 // Mask binary operation
1947 // - KAND, KANDN, KOR, KXNOR, KXOR
1948 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1949 RegisterClass KRC, SDPatternOperator OpNode,
1950 Predicate prd, bit IsCommutable> {
1951 let Predicates = [prd], isCommutable = IsCommutable in
1952 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1953 !strconcat(OpcodeStr,
1954 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1955 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1958 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1959 SDPatternOperator OpNode, bit IsCommutable> {
1960 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1961 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
1962 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1963 HasAVX512, IsCommutable>, VEX_4V, VEX_L, PS;
1964 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1965 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
1966 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1967 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
1970 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1971 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1973 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
1974 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
1975 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
1976 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
1977 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
1979 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1980 let Predicates = [HasAVX512] in
1981 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1982 (i16 GR16:$src1), (i16 GR16:$src2)),
1983 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1984 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1985 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1988 defm : avx512_mask_binop_int<"kand", "KAND">;
1989 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1990 defm : avx512_mask_binop_int<"kor", "KOR">;
1991 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1992 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1994 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1995 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
1996 // for the DQI set, this type is legal and KxxxB instruction is used
1997 let Predicates = [NoDQI] in
1998 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2000 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2001 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2003 // All types smaller than 8 bits require conversion anyway
2004 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2005 (COPY_TO_REGCLASS (Inst
2006 (COPY_TO_REGCLASS VK1:$src1, VK16),
2007 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2008 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2009 (COPY_TO_REGCLASS (Inst
2010 (COPY_TO_REGCLASS VK2:$src1, VK16),
2011 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2012 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2013 (COPY_TO_REGCLASS (Inst
2014 (COPY_TO_REGCLASS VK4:$src1, VK16),
2015 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2018 defm : avx512_binop_pat<and, KANDWrr>;
2019 defm : avx512_binop_pat<andn, KANDNWrr>;
2020 defm : avx512_binop_pat<or, KORWrr>;
2021 defm : avx512_binop_pat<xnor, KXNORWrr>;
2022 defm : avx512_binop_pat<xor, KXORWrr>;
2024 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2025 (KXNORWrr VK16:$src1, VK16:$src2)>;
2026 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2027 (KXNORBrr VK8:$src1, VK8:$src2)>;
2028 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2029 (KXNORDrr VK32:$src1, VK32:$src2)>;
2030 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2031 (KXNORQrr VK64:$src1, VK64:$src2)>;
2033 let Predicates = [NoDQI] in
2034 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2035 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2036 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2038 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2039 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2040 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2042 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2043 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2044 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2046 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2047 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2048 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2051 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
2052 RegisterClass KRC> {
2053 let Predicates = [HasAVX512] in
2054 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2055 !strconcat(OpcodeStr,
2056 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2059 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
2060 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
2064 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
2065 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
2066 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
2067 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
2070 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2071 let Predicates = [HasAVX512] in
2072 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2073 (i16 GR16:$src1), (i16 GR16:$src2)),
2074 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2075 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2076 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2078 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2081 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2083 let Predicates = [HasAVX512], Defs = [EFLAGS] in
2084 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2085 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2086 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2089 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2090 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2092 let Predicates = [HasDQI] in
2093 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2095 let Predicates = [HasBWI] in {
2096 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2098 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2103 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2106 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2108 let Predicates = [HasAVX512] in
2109 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2110 !strconcat(OpcodeStr,
2111 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2112 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2115 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2117 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2119 let Predicates = [HasDQI] in
2120 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2122 let Predicates = [HasBWI] in {
2123 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2125 let Predicates = [HasDQI] in
2126 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2131 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2132 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2134 // Mask setting all 0s or 1s
2135 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2136 let Predicates = [HasAVX512] in
2137 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2138 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2139 [(set KRC:$dst, (VT Val))]>;
2142 multiclass avx512_mask_setop_w<PatFrag Val> {
2143 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2144 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2145 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2146 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2149 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2150 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2152 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2153 let Predicates = [HasAVX512] in {
2154 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2155 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2156 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2157 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2158 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2159 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2160 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2162 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2163 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2165 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2166 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2168 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2169 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2171 let Predicates = [HasVLX] in {
2172 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2173 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2174 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2175 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2176 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2177 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2178 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2179 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2180 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2181 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2184 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2185 (v8i1 (COPY_TO_REGCLASS
2186 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2187 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2189 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2190 (v8i1 (COPY_TO_REGCLASS
2191 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2192 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2194 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2195 (v4i1 (COPY_TO_REGCLASS
2196 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2197 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2199 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2200 (v4i1 (COPY_TO_REGCLASS
2201 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2202 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2204 //===----------------------------------------------------------------------===//
2205 // AVX-512 - Aligned and unaligned load and store
2209 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2210 PatFrag ld_frag, PatFrag mload,
2211 bit IsReMaterializable = 1> {
2212 let hasSideEffects = 0 in {
2213 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2214 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2216 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2217 (ins _.KRCWM:$mask, _.RC:$src),
2218 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2219 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2222 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2223 SchedRW = [WriteLoad] in
2224 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2225 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2226 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2229 let Constraints = "$src0 = $dst" in {
2230 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2231 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2232 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2233 "${dst} {${mask}}, $src1}"),
2234 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2236 (_.VT _.RC:$src0))))], _.ExeDomain>,
2238 let mayLoad = 1, SchedRW = [WriteLoad] in
2239 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2240 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2241 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2242 "${dst} {${mask}}, $src1}"),
2243 [(set _.RC:$dst, (_.VT
2244 (vselect _.KRCWM:$mask,
2245 (_.VT (bitconvert (ld_frag addr:$src1))),
2246 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2248 let mayLoad = 1, SchedRW = [WriteLoad] in
2249 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2250 (ins _.KRCWM:$mask, _.MemOp:$src),
2251 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2252 "${dst} {${mask}} {z}, $src}",
2253 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2254 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2255 _.ExeDomain>, EVEX, EVEX_KZ;
2257 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2258 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2260 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2261 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2263 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2264 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2265 _.KRCWM:$mask, addr:$ptr)>;
2268 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2269 AVX512VLVectorVTInfo _,
2271 bit IsReMaterializable = 1> {
2272 let Predicates = [prd] in
2273 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2274 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2276 let Predicates = [prd, HasVLX] in {
2277 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2278 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2279 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2280 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2284 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2285 AVX512VLVectorVTInfo _,
2287 bit IsReMaterializable = 1> {
2288 let Predicates = [prd] in
2289 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2290 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2292 let Predicates = [prd, HasVLX] in {
2293 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2294 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2295 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2296 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2300 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2301 PatFrag st_frag, PatFrag mstore> {
2302 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2303 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2304 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2306 let Constraints = "$src1 = $dst" in
2307 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2308 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2310 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2311 [], _.ExeDomain>, EVEX, EVEX_K;
2312 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2313 (ins _.KRCWM:$mask, _.RC:$src),
2315 "\t{$src, ${dst} {${mask}} {z}|" #
2316 "${dst} {${mask}} {z}, $src}",
2317 [], _.ExeDomain>, EVEX, EVEX_KZ;
2319 let mayStore = 1 in {
2320 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2321 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2322 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2323 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2324 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2325 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2326 [], _.ExeDomain>, EVEX, EVEX_K;
2329 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2330 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2331 _.KRCWM:$mask, _.RC:$src)>;
2335 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2336 AVX512VLVectorVTInfo _, Predicate prd> {
2337 let Predicates = [prd] in
2338 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2339 masked_store_unaligned>, EVEX_V512;
2341 let Predicates = [prd, HasVLX] in {
2342 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2343 masked_store_unaligned>, EVEX_V256;
2344 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2345 masked_store_unaligned>, EVEX_V128;
2349 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2350 AVX512VLVectorVTInfo _, Predicate prd> {
2351 let Predicates = [prd] in
2352 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2353 masked_store_aligned512>, EVEX_V512;
2355 let Predicates = [prd, HasVLX] in {
2356 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2357 masked_store_aligned256>, EVEX_V256;
2358 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2359 masked_store_aligned128>, EVEX_V128;
2363 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2365 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2366 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2368 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2370 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2371 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2373 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2374 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2375 PS, EVEX_CD8<32, CD8VF>;
2377 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2378 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2379 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2381 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2382 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2383 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2385 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2386 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2387 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2389 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2390 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2391 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2393 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2394 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2395 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2397 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2398 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2399 (VMOVAPDZrm addr:$ptr)>;
2401 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2402 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2403 (VMOVAPSZrm addr:$ptr)>;
2405 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2407 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2409 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2411 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2414 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2416 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2418 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2420 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2423 let Predicates = [HasAVX512, NoVLX] in {
2424 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2425 (VMOVUPSZmrk addr:$ptr,
2426 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2427 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2429 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2430 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2431 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2433 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2434 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2435 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2436 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2439 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2441 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2442 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2444 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2446 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2447 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2449 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2450 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2451 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2453 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2454 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2455 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2457 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2458 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2459 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2461 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2462 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2463 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2465 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2466 (v16i32 immAllZerosV), GR16:$mask)),
2467 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2469 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2470 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2471 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2473 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2475 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2477 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2479 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2482 let AddedComplexity = 20 in {
2483 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2484 (bc_v8i64 (v16i32 immAllZerosV)))),
2485 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2487 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2488 (v8i64 VR512:$src))),
2489 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2492 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2493 (v16i32 immAllZerosV))),
2494 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2496 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2497 (v16i32 VR512:$src))),
2498 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2501 let Predicates = [HasAVX512, NoVLX] in {
2502 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2503 (VMOVDQU32Zmrk addr:$ptr,
2504 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2505 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2507 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2508 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2509 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2512 // Move Int Doubleword to Packed Double Int
2514 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2515 "vmovd\t{$src, $dst|$dst, $src}",
2517 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2519 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2520 "vmovd\t{$src, $dst|$dst, $src}",
2522 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2523 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2524 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2525 "vmovq\t{$src, $dst|$dst, $src}",
2527 (v2i64 (scalar_to_vector GR64:$src)))],
2528 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2529 let isCodeGenOnly = 1 in {
2530 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2531 "vmovq\t{$src, $dst|$dst, $src}",
2532 [(set FR64:$dst, (bitconvert GR64:$src))],
2533 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2534 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2535 "vmovq\t{$src, $dst|$dst, $src}",
2536 [(set GR64:$dst, (bitconvert FR64:$src))],
2537 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2539 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2540 "vmovq\t{$src, $dst|$dst, $src}",
2541 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2542 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2543 EVEX_CD8<64, CD8VT1>;
2545 // Move Int Doubleword to Single Scalar
2547 let isCodeGenOnly = 1 in {
2548 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2549 "vmovd\t{$src, $dst|$dst, $src}",
2550 [(set FR32X:$dst, (bitconvert GR32:$src))],
2551 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2553 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2554 "vmovd\t{$src, $dst|$dst, $src}",
2555 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2556 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2559 // Move doubleword from xmm register to r/m32
2561 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2562 "vmovd\t{$src, $dst|$dst, $src}",
2563 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2564 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2566 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2567 (ins i32mem:$dst, VR128X:$src),
2568 "vmovd\t{$src, $dst|$dst, $src}",
2569 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2570 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2571 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2573 // Move quadword from xmm1 register to r/m64
2575 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2576 "vmovq\t{$src, $dst|$dst, $src}",
2577 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2579 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2580 Requires<[HasAVX512, In64BitMode]>;
2582 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2583 (ins i64mem:$dst, VR128X:$src),
2584 "vmovq\t{$src, $dst|$dst, $src}",
2585 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2586 addr:$dst)], IIC_SSE_MOVDQ>,
2587 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2588 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2590 // Move Scalar Single to Double Int
2592 let isCodeGenOnly = 1 in {
2593 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2595 "vmovd\t{$src, $dst|$dst, $src}",
2596 [(set GR32:$dst, (bitconvert FR32X:$src))],
2597 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2598 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2599 (ins i32mem:$dst, FR32X:$src),
2600 "vmovd\t{$src, $dst|$dst, $src}",
2601 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2602 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2605 // Move Quadword Int to Packed Quadword Int
2607 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2609 "vmovq\t{$src, $dst|$dst, $src}",
2611 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2612 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2614 //===----------------------------------------------------------------------===//
2615 // AVX-512 MOVSS, MOVSD
2616 //===----------------------------------------------------------------------===//
2618 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2619 SDNode OpNode, ValueType vt,
2620 X86MemOperand x86memop, PatFrag mem_pat> {
2621 let hasSideEffects = 0 in {
2622 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2623 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2624 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2625 (scalar_to_vector RC:$src2))))],
2626 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2627 let Constraints = "$src1 = $dst" in
2628 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2629 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2631 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2632 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2633 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2634 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2635 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2637 let mayStore = 1 in {
2638 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2639 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2640 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2642 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2643 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2644 [], IIC_SSE_MOV_S_MR>,
2645 EVEX, VEX_LIG, EVEX_K;
2647 } //hasSideEffects = 0
2650 let ExeDomain = SSEPackedSingle in
2651 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2652 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2654 let ExeDomain = SSEPackedDouble in
2655 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2656 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2658 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2659 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2660 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2662 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2663 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2664 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2666 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2667 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2668 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2670 // For the disassembler
2671 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2672 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2673 (ins VR128X:$src1, FR32X:$src2),
2674 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2676 XS, EVEX_4V, VEX_LIG;
2677 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2678 (ins VR128X:$src1, FR64X:$src2),
2679 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2681 XD, EVEX_4V, VEX_LIG, VEX_W;
2684 let Predicates = [HasAVX512] in {
2685 let AddedComplexity = 15 in {
2686 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2687 // MOVS{S,D} to the lower bits.
2688 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2689 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2690 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2691 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2692 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2693 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2694 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2695 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2697 // Move low f32 and clear high bits.
2698 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2699 (SUBREG_TO_REG (i32 0),
2700 (VMOVSSZrr (v4f32 (V_SET0)),
2701 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2702 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2703 (SUBREG_TO_REG (i32 0),
2704 (VMOVSSZrr (v4i32 (V_SET0)),
2705 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2708 let AddedComplexity = 20 in {
2709 // MOVSSrm zeros the high parts of the register; represent this
2710 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2711 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2712 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2713 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2714 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2715 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2716 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2718 // MOVSDrm zeros the high parts of the register; represent this
2719 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2720 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2721 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2722 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2723 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2724 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2725 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2726 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2727 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2728 def : Pat<(v2f64 (X86vzload addr:$src)),
2729 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2731 // Represent the same patterns above but in the form they appear for
2733 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2734 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2735 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2736 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2737 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2738 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2739 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2740 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2741 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2743 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2744 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2745 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2746 FR32X:$src)), sub_xmm)>;
2747 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2748 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2749 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2750 FR64X:$src)), sub_xmm)>;
2751 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2752 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2753 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2755 // Move low f64 and clear high bits.
2756 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2757 (SUBREG_TO_REG (i32 0),
2758 (VMOVSDZrr (v2f64 (V_SET0)),
2759 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2761 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2762 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2763 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2765 // Extract and store.
2766 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2768 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2769 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2771 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2773 // Shuffle with VMOVSS
2774 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2775 (VMOVSSZrr (v4i32 VR128X:$src1),
2776 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2777 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2778 (VMOVSSZrr (v4f32 VR128X:$src1),
2779 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2782 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2783 (SUBREG_TO_REG (i32 0),
2784 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2785 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2787 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2788 (SUBREG_TO_REG (i32 0),
2789 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2790 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2793 // Shuffle with VMOVSD
2794 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2795 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2796 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2797 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2798 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2799 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2800 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2801 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2804 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2805 (SUBREG_TO_REG (i32 0),
2806 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2807 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2809 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2810 (SUBREG_TO_REG (i32 0),
2811 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2812 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2815 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2816 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2817 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2818 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2819 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2820 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2821 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2822 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2825 let AddedComplexity = 15 in
2826 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2828 "vmovq\t{$src, $dst|$dst, $src}",
2829 [(set VR128X:$dst, (v2i64 (X86vzmovl
2830 (v2i64 VR128X:$src))))],
2831 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2833 let AddedComplexity = 20 in
2834 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2836 "vmovq\t{$src, $dst|$dst, $src}",
2837 [(set VR128X:$dst, (v2i64 (X86vzmovl
2838 (loadv2i64 addr:$src))))],
2839 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2840 EVEX_CD8<8, CD8VT8>;
2842 let Predicates = [HasAVX512] in {
2843 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2844 let AddedComplexity = 20 in {
2845 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2846 (VMOVDI2PDIZrm addr:$src)>;
2847 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2848 (VMOV64toPQIZrr GR64:$src)>;
2849 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2850 (VMOVDI2PDIZrr GR32:$src)>;
2852 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2853 (VMOVDI2PDIZrm addr:$src)>;
2854 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2855 (VMOVDI2PDIZrm addr:$src)>;
2856 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2857 (VMOVZPQILo2PQIZrm addr:$src)>;
2858 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2859 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2860 def : Pat<(v2i64 (X86vzload addr:$src)),
2861 (VMOVZPQILo2PQIZrm addr:$src)>;
2864 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2865 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2866 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2867 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2868 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2869 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2870 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2873 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2874 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2876 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2877 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2879 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2880 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2882 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2883 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2885 //===----------------------------------------------------------------------===//
2886 // AVX-512 - Non-temporals
2887 //===----------------------------------------------------------------------===//
2888 let SchedRW = [WriteLoad] in {
2889 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2890 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2891 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2892 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2893 EVEX_CD8<64, CD8VF>;
2895 let Predicates = [HasAVX512, HasVLX] in {
2896 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2898 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2899 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2900 EVEX_CD8<64, CD8VF>;
2902 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2904 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2905 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2906 EVEX_CD8<64, CD8VF>;
2910 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2911 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2912 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2913 let SchedRW = [WriteStore], mayStore = 1,
2914 AddedComplexity = 400 in
2915 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2916 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2917 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2920 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2921 string elty, string elsz, string vsz512,
2922 string vsz256, string vsz128, Domain d,
2923 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2924 let Predicates = [prd] in
2925 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2926 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2927 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2930 let Predicates = [prd, HasVLX] in {
2931 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2932 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2933 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2936 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2937 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2938 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2943 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2944 "i", "64", "8", "4", "2", SSEPackedInt,
2945 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2947 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2948 "f", "64", "8", "4", "2", SSEPackedDouble,
2949 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2951 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2952 "f", "32", "16", "8", "4", SSEPackedSingle,
2953 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2955 //===----------------------------------------------------------------------===//
2956 // AVX-512 - Integer arithmetic
2958 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2959 X86VectorVTInfo _, OpndItins itins,
2960 bit IsCommutable = 0> {
2961 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2962 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2963 "$src2, $src1", "$src1, $src2",
2964 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2965 itins.rr, IsCommutable>,
2966 AVX512BIBase, EVEX_4V;
2969 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2970 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2971 "$src2, $src1", "$src1, $src2",
2972 (_.VT (OpNode _.RC:$src1,
2973 (bitconvert (_.LdFrag addr:$src2)))),
2975 AVX512BIBase, EVEX_4V;
2978 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2979 X86VectorVTInfo _, OpndItins itins,
2980 bit IsCommutable = 0> :
2981 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2983 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2984 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2985 "${src2}"##_.BroadcastStr##", $src1",
2986 "$src1, ${src2}"##_.BroadcastStr,
2987 (_.VT (OpNode _.RC:$src1,
2989 (_.ScalarLdFrag addr:$src2)))),
2991 AVX512BIBase, EVEX_4V, EVEX_B;
2994 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2995 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2996 Predicate prd, bit IsCommutable = 0> {
2997 let Predicates = [prd] in
2998 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2999 IsCommutable>, EVEX_V512;
3001 let Predicates = [prd, HasVLX] in {
3002 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3003 IsCommutable>, EVEX_V256;
3004 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3005 IsCommutable>, EVEX_V128;
3009 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3010 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3011 Predicate prd, bit IsCommutable = 0> {
3012 let Predicates = [prd] in
3013 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3014 IsCommutable>, EVEX_V512;
3016 let Predicates = [prd, HasVLX] in {
3017 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3018 IsCommutable>, EVEX_V256;
3019 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3020 IsCommutable>, EVEX_V128;
3024 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3025 OpndItins itins, Predicate prd,
3026 bit IsCommutable = 0> {
3027 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3028 itins, prd, IsCommutable>,
3029 VEX_W, EVEX_CD8<64, CD8VF>;
3032 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3033 OpndItins itins, Predicate prd,
3034 bit IsCommutable = 0> {
3035 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3036 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3039 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3040 OpndItins itins, Predicate prd,
3041 bit IsCommutable = 0> {
3042 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3043 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3046 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3047 OpndItins itins, Predicate prd,
3048 bit IsCommutable = 0> {
3049 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3050 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3053 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3054 SDNode OpNode, OpndItins itins, Predicate prd,
3055 bit IsCommutable = 0> {
3056 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
3059 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
3063 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3064 SDNode OpNode, OpndItins itins, Predicate prd,
3065 bit IsCommutable = 0> {
3066 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
3069 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
3073 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3074 bits<8> opc_d, bits<8> opc_q,
3075 string OpcodeStr, SDNode OpNode,
3076 OpndItins itins, bit IsCommutable = 0> {
3077 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3078 itins, HasAVX512, IsCommutable>,
3079 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3080 itins, HasBWI, IsCommutable>;
3083 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3084 SDNode OpNode,X86VectorVTInfo _Src,
3085 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3086 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3087 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3088 "$src2, $src1","$src1, $src2",
3090 (_Src.VT _Src.RC:$src1),
3091 (_Src.VT _Src.RC:$src2))),
3092 itins.rr, IsCommutable>,
3093 AVX512BIBase, EVEX_4V;
3094 let mayLoad = 1 in {
3095 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3096 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3097 "$src2, $src1", "$src1, $src2",
3098 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3099 (bitconvert (_Src.LdFrag addr:$src2)))),
3101 AVX512BIBase, EVEX_4V;
3103 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3104 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3106 "${src2}"##_Dst.BroadcastStr##", $src1",
3107 "$src1, ${src2}"##_Dst.BroadcastStr,
3108 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3109 (_Dst.VT (X86VBroadcast
3110 (_Dst.ScalarLdFrag addr:$src2)))))),
3112 AVX512BIBase, EVEX_4V, EVEX_B;
3116 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3117 SSE_INTALU_ITINS_P, 1>;
3118 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3119 SSE_INTALU_ITINS_P, 0>;
3120 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3121 SSE_INTALU_ITINS_P, HasBWI, 1>;
3122 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3123 SSE_INTALU_ITINS_P, HasBWI, 0>;
3124 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3125 SSE_INTALU_ITINS_P, HasBWI, 1>;
3126 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3127 SSE_INTALU_ITINS_P, HasBWI, 0>;
3128 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3129 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3130 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3131 SSE_INTALU_ITINS_P, HasBWI, 1>;
3132 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3133 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3136 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3137 SDNode OpNode, bit IsCommutable = 0> {
3139 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3140 v16i32_info, v8i64_info, IsCommutable>,
3141 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3142 let Predicates = [HasVLX] in {
3143 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3144 v8i32x_info, v4i64x_info, IsCommutable>,
3145 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3146 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3147 v4i32x_info, v2i64x_info, IsCommutable>,
3148 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3152 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3154 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3157 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3158 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3159 let mayLoad = 1 in {
3160 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3161 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3163 "${src2}"##_Src.BroadcastStr##", $src1",
3164 "$src1, ${src2}"##_Src.BroadcastStr,
3165 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3166 (_Src.VT (X86VBroadcast
3167 (_Src.ScalarLdFrag addr:$src2))))))>,
3168 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3172 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3173 SDNode OpNode,X86VectorVTInfo _Src,
3174 X86VectorVTInfo _Dst> {
3175 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3176 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3177 "$src2, $src1","$src1, $src2",
3179 (_Src.VT _Src.RC:$src1),
3180 (_Src.VT _Src.RC:$src2)))>,
3181 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3182 let mayLoad = 1 in {
3183 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3184 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3185 "$src2, $src1", "$src1, $src2",
3186 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3187 (bitconvert (_Src.LdFrag addr:$src2))))>,
3188 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3192 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3194 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3196 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3197 v32i16_info>, EVEX_V512;
3198 let Predicates = [HasVLX] in {
3199 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3201 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3202 v16i16x_info>, EVEX_V256;
3203 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3205 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3206 v8i16x_info>, EVEX_V128;
3209 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3211 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3212 v64i8_info>, EVEX_V512;
3213 let Predicates = [HasVLX] in {
3214 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3215 v32i8x_info>, EVEX_V256;
3216 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3217 v16i8x_info>, EVEX_V128;
3220 let Predicates = [HasBWI] in {
3221 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3222 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3223 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3224 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3227 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3228 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3229 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3230 SSE_INTALU_ITINS_P, HasBWI, 1>;
3231 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3232 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3234 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3235 SSE_INTALU_ITINS_P, HasBWI, 1>;
3236 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3237 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3238 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3239 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3241 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3242 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3243 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3244 SSE_INTALU_ITINS_P, HasBWI, 1>;
3245 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3246 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3248 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3249 SSE_INTALU_ITINS_P, HasBWI, 1>;
3250 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3251 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3252 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3253 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3255 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3256 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3257 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3258 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3259 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3260 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3261 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3262 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3263 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3264 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3265 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3266 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3267 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3268 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3269 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3270 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3271 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3272 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3273 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3274 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3275 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3276 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3277 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3278 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3279 //===----------------------------------------------------------------------===//
3280 // AVX-512 - Unpack Instructions
3281 //===----------------------------------------------------------------------===//
3283 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3284 PatFrag mem_frag, RegisterClass RC,
3285 X86MemOperand x86memop, string asm,
3287 def rr : AVX512PI<opc, MRMSrcReg,
3288 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3290 (vt (OpNode RC:$src1, RC:$src2)))],
3292 def rm : AVX512PI<opc, MRMSrcMem,
3293 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3295 (vt (OpNode RC:$src1,
3296 (bitconvert (mem_frag addr:$src2)))))],
3300 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3301 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3302 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3303 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3304 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3305 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3306 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3307 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3308 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3309 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3310 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3311 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3313 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3314 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3315 X86MemOperand x86memop> {
3316 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3317 (ins RC:$src1, RC:$src2),
3318 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3319 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3320 IIC_SSE_UNPCK>, EVEX_4V;
3321 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3322 (ins RC:$src1, x86memop:$src2),
3323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3324 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3325 (bitconvert (memop_frag addr:$src2)))))],
3326 IIC_SSE_UNPCK>, EVEX_4V;
3328 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3329 VR512, loadv16i32, i512mem>, EVEX_V512,
3330 EVEX_CD8<32, CD8VF>;
3331 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3332 VR512, loadv8i64, i512mem>, EVEX_V512,
3333 VEX_W, EVEX_CD8<64, CD8VF>;
3334 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3335 VR512, loadv16i32, i512mem>, EVEX_V512,
3336 EVEX_CD8<32, CD8VF>;
3337 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3338 VR512, loadv8i64, i512mem>, EVEX_V512,
3339 VEX_W, EVEX_CD8<64, CD8VF>;
3340 //===----------------------------------------------------------------------===//
3344 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3345 SDNode OpNode, PatFrag mem_frag,
3346 X86MemOperand x86memop, ValueType OpVT> {
3347 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3348 (ins RC:$src1, u8imm:$src2),
3349 !strconcat(OpcodeStr,
3350 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3352 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3354 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3355 (ins x86memop:$src1, u8imm:$src2),
3356 !strconcat(OpcodeStr,
3357 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3359 (OpVT (OpNode (mem_frag addr:$src1),
3360 (i8 imm:$src2))))]>, EVEX;
3363 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, loadv16i32,
3364 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3366 //===----------------------------------------------------------------------===//
3367 // AVX-512 Logical Instructions
3368 //===----------------------------------------------------------------------===//
3370 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3371 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3372 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3373 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3374 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3375 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3376 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3377 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3379 //===----------------------------------------------------------------------===//
3380 // AVX-512 FP arithmetic
3381 //===----------------------------------------------------------------------===//
3382 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3383 SDNode OpNode, SDNode VecNode, OpndItins itins,
3386 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3387 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3388 "$src2, $src1", "$src1, $src2",
3389 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3390 (i32 FROUND_CURRENT)),
3391 itins.rr, IsCommutable>;
3393 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3394 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3395 "$src2, $src1", "$src1, $src2",
3396 (VecNode (_.VT _.RC:$src1),
3397 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3398 (i32 FROUND_CURRENT)),
3399 itins.rm, IsCommutable>;
3400 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3401 Predicates = [HasAVX512] in {
3402 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3403 (ins _.FRC:$src1, _.FRC:$src2),
3404 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3405 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3407 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3408 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3409 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3410 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3411 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3415 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3416 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3418 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3419 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3420 "$rc, $src2, $src1", "$src1, $src2, $rc",
3421 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3422 (i32 imm:$rc)), itins.rr, IsCommutable>,
3425 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3426 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3428 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3429 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3430 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3431 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3432 (i32 FROUND_NO_EXC))>, EVEX_B;
3435 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3437 SizeItins itins, bit IsCommutable> {
3438 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3439 itins.s, IsCommutable>,
3440 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3441 itins.s, IsCommutable>,
3442 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3443 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3444 itins.d, IsCommutable>,
3445 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3446 itins.d, IsCommutable>,
3447 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3450 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3452 SizeItins itins, bit IsCommutable> {
3453 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3454 itins.s, IsCommutable>,
3455 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3456 itins.s, IsCommutable>,
3457 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3458 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3459 itins.d, IsCommutable>,
3460 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3461 itins.d, IsCommutable>,
3462 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3464 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3465 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3466 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3467 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3468 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3469 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3471 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3472 X86VectorVTInfo _, bit IsCommutable> {
3473 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3474 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3475 "$src2, $src1", "$src1, $src2",
3476 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3477 let mayLoad = 1 in {
3478 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3479 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3480 "$src2, $src1", "$src1, $src2",
3481 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3482 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3483 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3484 "${src2}"##_.BroadcastStr##", $src1",
3485 "$src1, ${src2}"##_.BroadcastStr,
3486 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3487 (_.ScalarLdFrag addr:$src2))))>,
3492 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3493 X86VectorVTInfo _, bit IsCommutable> {
3494 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3495 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3496 "$rc, $src2, $src1", "$src1, $src2, $rc",
3497 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3498 EVEX_4V, EVEX_B, EVEX_RC;
3502 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3503 X86VectorVTInfo _, bit IsCommutable> {
3504 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3505 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3506 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3507 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3511 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3512 bit IsCommutable = 0> {
3513 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3514 IsCommutable>, EVEX_V512, PS,
3515 EVEX_CD8<32, CD8VF>;
3516 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3517 IsCommutable>, EVEX_V512, PD, VEX_W,
3518 EVEX_CD8<64, CD8VF>;
3520 // Define only if AVX512VL feature is present.
3521 let Predicates = [HasVLX] in {
3522 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3523 IsCommutable>, EVEX_V128, PS,
3524 EVEX_CD8<32, CD8VF>;
3525 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3526 IsCommutable>, EVEX_V256, PS,
3527 EVEX_CD8<32, CD8VF>;
3528 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3529 IsCommutable>, EVEX_V128, PD, VEX_W,
3530 EVEX_CD8<64, CD8VF>;
3531 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3532 IsCommutable>, EVEX_V256, PD, VEX_W,
3533 EVEX_CD8<64, CD8VF>;
3537 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3538 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3539 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3540 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3541 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3544 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3545 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3546 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3547 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3548 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3551 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3552 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3553 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3554 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3555 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3556 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3557 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3558 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3559 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3560 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3561 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3562 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3563 let Predicates = [HasDQI] in {
3564 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3565 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3566 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3567 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3570 //===----------------------------------------------------------------------===//
3571 // AVX-512 VPTESTM instructions
3572 //===----------------------------------------------------------------------===//
3574 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3575 X86VectorVTInfo _> {
3576 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3577 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3578 "$src2, $src1", "$src1, $src2",
3579 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3582 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3583 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3584 "$src2, $src1", "$src1, $src2",
3585 (OpNode (_.VT _.RC:$src1),
3586 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3588 EVEX_CD8<_.EltSize, CD8VF>;
3591 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3592 X86VectorVTInfo _> {
3594 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3595 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3596 "${src2}"##_.BroadcastStr##", $src1",
3597 "$src1, ${src2}"##_.BroadcastStr,
3598 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3599 (_.ScalarLdFrag addr:$src2))))>,
3600 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3602 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3603 AVX512VLVectorVTInfo _> {
3604 let Predicates = [HasAVX512] in
3605 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3606 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3608 let Predicates = [HasAVX512, HasVLX] in {
3609 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3610 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3611 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3612 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3616 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3617 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3619 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3620 avx512vl_i64_info>, VEX_W;
3623 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3625 let Predicates = [HasBWI] in {
3626 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3628 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3631 let Predicates = [HasVLX, HasBWI] in {
3633 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3635 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3637 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3639 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3644 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3646 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3647 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3649 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3650 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3652 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3653 (v16i32 VR512:$src2), (i16 -1))),
3654 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3656 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3657 (v8i64 VR512:$src2), (i8 -1))),
3658 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3660 //===----------------------------------------------------------------------===//
3661 // AVX-512 Shift instructions
3662 //===----------------------------------------------------------------------===//
3663 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3664 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3665 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3666 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3667 "$src2, $src1", "$src1, $src2",
3668 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3669 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3671 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3672 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3673 "$src2, $src1", "$src1, $src2",
3674 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3676 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3679 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3680 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3682 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3683 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3684 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3685 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3686 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V, EVEX_B;
3689 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3690 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3691 // src2 is always 128-bit
3692 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3693 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3694 "$src2, $src1", "$src1, $src2",
3695 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3696 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3697 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3698 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3699 "$src2, $src1", "$src1, $src2",
3700 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3701 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3705 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3706 ValueType SrcVT, PatFrag bc_frag,
3707 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3708 let Predicates = [prd] in
3709 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3710 VTInfo.info512>, EVEX_V512,
3711 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3712 let Predicates = [prd, HasVLX] in {
3713 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3714 VTInfo.info256>, EVEX_V256,
3715 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3716 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3717 VTInfo.info128>, EVEX_V128,
3718 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3722 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3723 string OpcodeStr, SDNode OpNode> {
3724 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3725 avx512vl_i32_info, HasAVX512>;
3726 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3727 avx512vl_i64_info, HasAVX512>, VEX_W;
3728 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3729 avx512vl_i16_info, HasBWI>;
3732 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3733 string OpcodeStr, SDNode OpNode,
3734 AVX512VLVectorVTInfo VTInfo> {
3735 let Predicates = [HasAVX512] in
3736 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3738 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3739 VTInfo.info512>, EVEX_V512;
3740 let Predicates = [HasAVX512, HasVLX] in {
3741 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3743 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3744 VTInfo.info256>, EVEX_V256;
3745 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3747 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3748 VTInfo.info128>, EVEX_V128;
3752 multiclass avx512_shift_rmi_w<bits<8> opcw,
3753 Format ImmFormR, Format ImmFormM,
3754 string OpcodeStr, SDNode OpNode> {
3755 let Predicates = [HasBWI] in
3756 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3757 v32i16_info>, EVEX_V512;
3758 let Predicates = [HasVLX, HasBWI] in {
3759 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3760 v16i16x_info>, EVEX_V256;
3761 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3762 v8i16x_info>, EVEX_V128;
3766 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3767 Format ImmFormR, Format ImmFormM,
3768 string OpcodeStr, SDNode OpNode> {
3769 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3770 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3771 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3772 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3775 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3776 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>;
3778 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3779 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>;
3781 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3782 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>;
3784 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>;
3785 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>;
3787 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3788 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3789 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3791 //===-------------------------------------------------------------------===//
3792 // Variable Bit Shifts
3793 //===-------------------------------------------------------------------===//
3794 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3795 X86VectorVTInfo _> {
3796 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3797 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3798 "$src2, $src1", "$src1, $src2",
3799 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3800 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3802 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3803 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3804 "$src2, $src1", "$src1, $src2",
3805 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2))),
3806 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3807 EVEX_CD8<_.EltSize, CD8VF>;
3810 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3811 X86VectorVTInfo _> {
3813 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3814 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3815 "${src2}"##_.BroadcastStr##", $src1",
3816 "$src1, ${src2}"##_.BroadcastStr,
3817 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3818 (_.ScalarLdFrag addr:$src2))))),
3819 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3820 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3822 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3823 AVX512VLVectorVTInfo _> {
3824 let Predicates = [HasAVX512] in
3825 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3826 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3828 let Predicates = [HasAVX512, HasVLX] in {
3829 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3830 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3831 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3832 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3836 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3838 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3840 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3841 avx512vl_i64_info>, VEX_W;
3844 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3846 let Predicates = [HasBWI] in
3847 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3849 let Predicates = [HasVLX, HasBWI] in {
3851 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3853 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3858 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3859 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3860 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3861 avx512_var_shift_w<0x11, "vpsravw", sra>;
3862 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3863 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3864 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3865 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3867 //===----------------------------------------------------------------------===//
3868 // AVX-512 - MOVDDUP
3869 //===----------------------------------------------------------------------===//
3871 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3872 X86MemOperand x86memop, PatFrag memop_frag> {
3873 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3874 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3875 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3876 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3877 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3879 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3882 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3883 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3884 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3885 (VMOVDDUPZrm addr:$src)>;
3887 //===---------------------------------------------------------------------===//
3888 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3889 //===---------------------------------------------------------------------===//
3890 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3891 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3892 X86MemOperand x86memop> {
3893 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3894 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3895 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3897 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3898 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3899 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3902 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3903 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3904 EVEX_CD8<32, CD8VF>;
3905 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3906 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3907 EVEX_CD8<32, CD8VF>;
3909 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3910 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3911 (VMOVSHDUPZrm addr:$src)>;
3912 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3913 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3914 (VMOVSLDUPZrm addr:$src)>;
3916 //===----------------------------------------------------------------------===//
3917 // Move Low to High and High to Low packed FP Instructions
3918 //===----------------------------------------------------------------------===//
3919 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3920 (ins VR128X:$src1, VR128X:$src2),
3921 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3922 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3923 IIC_SSE_MOV_LH>, EVEX_4V;
3924 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3925 (ins VR128X:$src1, VR128X:$src2),
3926 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3927 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3928 IIC_SSE_MOV_LH>, EVEX_4V;
3930 let Predicates = [HasAVX512] in {
3932 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3933 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3934 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3935 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3938 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3939 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3942 //===----------------------------------------------------------------------===//
3943 // FMA - Fused Multiply Operations
3946 let Constraints = "$src1 = $dst" in {
3947 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3948 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3949 SDPatternOperator OpNode = null_frag> {
3950 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3951 (ins _.RC:$src2, _.RC:$src3),
3952 OpcodeStr, "$src3, $src2", "$src2, $src3",
3953 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3957 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3958 (ins _.RC:$src2, _.MemOp:$src3),
3959 OpcodeStr, "$src3, $src2", "$src2, $src3",
3960 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3963 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3964 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3965 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
3966 !strconcat("$src2, ${src3}", _.BroadcastStr ),
3968 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3969 AVX512FMA3Base, EVEX_B;
3971 } // Constraints = "$src1 = $dst"
3973 let Constraints = "$src1 = $dst" in {
3974 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3975 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr,
3977 SDPatternOperator OpNode> {
3978 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3979 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
3980 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
3981 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
3982 AVX512FMA3Base, EVEX_B, EVEX_RC;
3984 } // Constraints = "$src1 = $dst"
3986 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
3987 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
3988 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3989 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3992 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3993 string OpcodeStr, X86VectorVTInfo VTI,
3994 SDPatternOperator OpNode> {
3995 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3996 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3997 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3998 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
4001 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
4003 SDPatternOperator OpNode,
4004 SDPatternOperator OpNodeRnd> {
4005 let ExeDomain = SSEPackedSingle in {
4006 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4007 v16f32_info, OpNode>,
4008 avx512_fma3_round_forms<opc213, OpcodeStr,
4009 v16f32_info, OpNodeRnd>, EVEX_V512;
4010 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4011 v8f32x_info, OpNode>, EVEX_V256;
4012 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4013 v4f32x_info, OpNode>, EVEX_V128;
4015 let ExeDomain = SSEPackedDouble in {
4016 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4017 v8f64_info, OpNode>,
4018 avx512_fma3_round_forms<opc213, OpcodeStr, v8f64_info,
4019 OpNodeRnd>, EVEX_V512, VEX_W;
4020 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4021 v4f64x_info, OpNode>,
4023 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4024 v2f64x_info, OpNode>,
4029 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
4030 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
4031 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
4032 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
4033 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4034 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4036 let Constraints = "$src1 = $dst" in {
4037 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
4038 X86VectorVTInfo _> {
4040 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4041 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
4042 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
4043 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
4045 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4046 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
4047 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
4048 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
4050 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4051 (_.ScalarLdFrag addr:$src2))),
4052 _.RC:$src3))]>, EVEX_B;
4054 } // Constraints = "$src1 = $dst"
4056 multiclass avx512_fma3p_m132_f<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4058 let ExeDomain = SSEPackedSingle in {
4059 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
4060 OpNode,v16f32_info>, EVEX_V512,
4061 EVEX_CD8<32, CD8VF>;
4062 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4063 OpNode, v8f32x_info>, EVEX_V256,
4064 EVEX_CD8<32, CD8VF>;
4065 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4066 OpNode, v4f32x_info>, EVEX_V128,
4067 EVEX_CD8<32, CD8VF>;
4069 let ExeDomain = SSEPackedDouble in {
4070 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
4071 OpNode, v8f64_info>, EVEX_V512,
4072 VEX_W, EVEX_CD8<32, CD8VF>;
4073 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4074 OpNode, v4f64x_info>, EVEX_V256,
4075 VEX_W, EVEX_CD8<32, CD8VF>;
4076 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4077 OpNode, v2f64x_info>, EVEX_V128,
4078 VEX_W, EVEX_CD8<32, CD8VF>;
4082 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
4083 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
4084 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
4085 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
4086 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
4087 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
4090 let Constraints = "$src1 = $dst" in {
4091 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4092 RegisterClass RC, ValueType OpVT,
4093 X86MemOperand x86memop, Operand memop,
4095 let isCommutable = 1 in
4096 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
4097 (ins RC:$src1, RC:$src2, RC:$src3),
4098 !strconcat(OpcodeStr,
4099 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4101 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
4103 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
4104 (ins RC:$src1, RC:$src2, f128mem:$src3),
4105 !strconcat(OpcodeStr,
4106 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4108 (OpVT (OpNode RC:$src2, RC:$src1,
4109 (mem_frag addr:$src3))))]>;
4111 } // Constraints = "$src1 = $dst"
4113 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
4114 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4115 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
4116 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4117 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
4118 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4119 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
4120 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4121 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
4122 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4123 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
4124 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4125 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
4126 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4127 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
4128 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4130 //===----------------------------------------------------------------------===//
4131 // AVX-512 Scalar convert from sign integer to float/double
4132 //===----------------------------------------------------------------------===//
4134 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4135 X86MemOperand x86memop, string asm> {
4136 let hasSideEffects = 0 in {
4137 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
4138 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4141 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
4142 (ins DstRC:$src1, x86memop:$src),
4143 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4145 } // hasSideEffects = 0
4148 let Predicates = [HasAVX512] in {
4149 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
4150 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4151 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
4152 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4153 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
4154 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4155 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
4156 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4158 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4159 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4160 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4161 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4162 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4163 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4164 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4165 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4167 def : Pat<(f32 (sint_to_fp GR32:$src)),
4168 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4169 def : Pat<(f32 (sint_to_fp GR64:$src)),
4170 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4171 def : Pat<(f64 (sint_to_fp GR32:$src)),
4172 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4173 def : Pat<(f64 (sint_to_fp GR64:$src)),
4174 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4176 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
4177 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4178 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
4179 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4180 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
4181 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4182 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
4183 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
4185 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4186 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4187 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4188 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4189 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4190 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4191 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4192 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4194 def : Pat<(f32 (uint_to_fp GR32:$src)),
4195 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4196 def : Pat<(f32 (uint_to_fp GR64:$src)),
4197 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4198 def : Pat<(f64 (uint_to_fp GR32:$src)),
4199 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4200 def : Pat<(f64 (uint_to_fp GR64:$src)),
4201 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4204 //===----------------------------------------------------------------------===//
4205 // AVX-512 Scalar convert from float/double to integer
4206 //===----------------------------------------------------------------------===//
4207 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4208 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
4210 let hasSideEffects = 0 in {
4211 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4212 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4213 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
4214 Requires<[HasAVX512]>;
4216 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4217 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
4218 Requires<[HasAVX512]>;
4219 } // hasSideEffects = 0
4221 let Predicates = [HasAVX512] in {
4222 // Convert float/double to signed/unsigned int 32/64
4223 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4224 ssmem, sse_load_f32, "cvtss2si">,
4225 XS, EVEX_CD8<32, CD8VT1>;
4226 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
4227 ssmem, sse_load_f32, "cvtss2si">,
4228 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4229 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
4230 ssmem, sse_load_f32, "cvtss2usi">,
4231 XS, EVEX_CD8<32, CD8VT1>;
4232 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4233 int_x86_avx512_cvtss2usi64, ssmem,
4234 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4235 EVEX_CD8<32, CD8VT1>;
4236 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4237 sdmem, sse_load_f64, "cvtsd2si">,
4238 XD, EVEX_CD8<64, CD8VT1>;
4239 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4240 sdmem, sse_load_f64, "cvtsd2si">,
4241 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4242 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4243 sdmem, sse_load_f64, "cvtsd2usi">,
4244 XD, EVEX_CD8<64, CD8VT1>;
4245 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4246 int_x86_avx512_cvtsd2usi64, sdmem,
4247 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4248 EVEX_CD8<64, CD8VT1>;
4250 let isCodeGenOnly = 1 in {
4251 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4252 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4253 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4254 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4255 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4256 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4257 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4258 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4259 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4260 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4261 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4262 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4264 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4265 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
4266 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4267 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4268 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
4269 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4270 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4271 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4272 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4273 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4274 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
4275 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4276 } // isCodeGenOnly = 1
4278 // Convert float/double to signed/unsigned int 32/64 with truncation
4279 let isCodeGenOnly = 1 in {
4280 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4281 ssmem, sse_load_f32, "cvttss2si">,
4282 XS, EVEX_CD8<32, CD8VT1>;
4283 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4284 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4285 "cvttss2si">, XS, VEX_W,
4286 EVEX_CD8<32, CD8VT1>;
4287 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4288 sdmem, sse_load_f64, "cvttsd2si">, XD,
4289 EVEX_CD8<64, CD8VT1>;
4290 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4291 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4292 "cvttsd2si">, XD, VEX_W,
4293 EVEX_CD8<64, CD8VT1>;
4294 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4295 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4296 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4297 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4298 int_x86_avx512_cvttss2usi64, ssmem,
4299 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4300 EVEX_CD8<32, CD8VT1>;
4301 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4302 int_x86_avx512_cvttsd2usi,
4303 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4304 EVEX_CD8<64, CD8VT1>;
4305 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4306 int_x86_avx512_cvttsd2usi64, sdmem,
4307 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4308 EVEX_CD8<64, CD8VT1>;
4309 } // isCodeGenOnly = 1
4311 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4312 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4314 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4315 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4316 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4317 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4318 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4319 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4322 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4323 loadf32, "cvttss2si">, XS,
4324 EVEX_CD8<32, CD8VT1>;
4325 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4326 loadf32, "cvttss2usi">, XS,
4327 EVEX_CD8<32, CD8VT1>;
4328 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4329 loadf32, "cvttss2si">, XS, VEX_W,
4330 EVEX_CD8<32, CD8VT1>;
4331 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4332 loadf32, "cvttss2usi">, XS, VEX_W,
4333 EVEX_CD8<32, CD8VT1>;
4334 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4335 loadf64, "cvttsd2si">, XD,
4336 EVEX_CD8<64, CD8VT1>;
4337 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4338 loadf64, "cvttsd2usi">, XD,
4339 EVEX_CD8<64, CD8VT1>;
4340 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4341 loadf64, "cvttsd2si">, XD, VEX_W,
4342 EVEX_CD8<64, CD8VT1>;
4343 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4344 loadf64, "cvttsd2usi">, XD, VEX_W,
4345 EVEX_CD8<64, CD8VT1>;
4347 //===----------------------------------------------------------------------===//
4348 // AVX-512 Convert form float to double and back
4349 //===----------------------------------------------------------------------===//
4350 let hasSideEffects = 0 in {
4351 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4352 (ins FR32X:$src1, FR32X:$src2),
4353 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4354 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4356 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4357 (ins FR32X:$src1, f32mem:$src2),
4358 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4359 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4360 EVEX_CD8<32, CD8VT1>;
4362 // Convert scalar double to scalar single
4363 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4364 (ins FR64X:$src1, FR64X:$src2),
4365 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4366 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4368 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4369 (ins FR64X:$src1, f64mem:$src2),
4370 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4371 []>, EVEX_4V, VEX_LIG, VEX_W,
4372 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4375 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4376 Requires<[HasAVX512]>;
4377 def : Pat<(fextend (loadf32 addr:$src)),
4378 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4380 def : Pat<(extloadf32 addr:$src),
4381 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4382 Requires<[HasAVX512, OptForSize]>;
4384 def : Pat<(extloadf32 addr:$src),
4385 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4386 Requires<[HasAVX512, OptForSpeed]>;
4388 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4389 Requires<[HasAVX512]>;
4391 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4392 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4393 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4395 let hasSideEffects = 0 in {
4396 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4397 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4399 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4400 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4401 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4402 [], d>, EVEX, EVEX_B, EVEX_RC;
4404 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4405 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4407 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4408 } // hasSideEffects = 0
4411 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4412 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4413 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4415 let hasSideEffects = 0 in {
4416 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4417 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4419 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4421 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4422 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4424 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4425 } // hasSideEffects = 0
4428 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4429 loadv8f64, f512mem, v8f32, v8f64,
4430 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4431 EVEX_CD8<64, CD8VF>;
4433 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4434 loadv4f64, f256mem, v8f64, v8f32,
4435 SSEPackedDouble>, EVEX_V512, PS,
4436 EVEX_CD8<32, CD8VH>;
4437 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4438 (VCVTPS2PDZrm addr:$src)>;
4440 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4441 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4442 (VCVTPD2PSZrr VR512:$src)>;
4444 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4445 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4446 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4448 //===----------------------------------------------------------------------===//
4449 // AVX-512 Vector convert from sign integer to float/double
4450 //===----------------------------------------------------------------------===//
4452 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4453 loadv8i64, i512mem, v16f32, v16i32,
4454 SSEPackedSingle>, EVEX_V512, PS,
4455 EVEX_CD8<32, CD8VF>;
4457 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4458 loadv4i64, i256mem, v8f64, v8i32,
4459 SSEPackedDouble>, EVEX_V512, XS,
4460 EVEX_CD8<32, CD8VH>;
4462 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4463 loadv16f32, f512mem, v16i32, v16f32,
4464 SSEPackedSingle>, EVEX_V512, XS,
4465 EVEX_CD8<32, CD8VF>;
4467 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4468 loadv8f64, f512mem, v8i32, v8f64,
4469 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4470 EVEX_CD8<64, CD8VF>;
4472 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4473 loadv16f32, f512mem, v16i32, v16f32,
4474 SSEPackedSingle>, EVEX_V512, PS,
4475 EVEX_CD8<32, CD8VF>;
4477 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4478 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4479 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4480 (VCVTTPS2UDQZrr VR512:$src)>;
4482 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4483 loadv8f64, f512mem, v8i32, v8f64,
4484 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4485 EVEX_CD8<64, CD8VF>;
4487 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4488 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4489 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4490 (VCVTTPD2UDQZrr VR512:$src)>;
4492 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4493 loadv4i64, f256mem, v8f64, v8i32,
4494 SSEPackedDouble>, EVEX_V512, XS,
4495 EVEX_CD8<32, CD8VH>;
4497 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4498 loadv16i32, f512mem, v16f32, v16i32,
4499 SSEPackedSingle>, EVEX_V512, XD,
4500 EVEX_CD8<32, CD8VF>;
4502 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4503 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4504 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4506 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4507 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4508 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4510 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4511 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4512 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4514 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4515 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4516 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4518 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4519 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4520 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4522 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4523 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4524 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4525 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4526 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4527 (VCVTDQ2PDZrr VR256X:$src)>;
4528 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4529 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4530 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4531 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4532 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4533 (VCVTUDQ2PDZrr VR256X:$src)>;
4535 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4536 RegisterClass DstRC, PatFrag mem_frag,
4537 X86MemOperand x86memop, Domain d> {
4538 let hasSideEffects = 0 in {
4539 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4540 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4542 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4543 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4544 [], d>, EVEX, EVEX_B, EVEX_RC;
4546 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4547 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4549 } // hasSideEffects = 0
4552 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4553 loadv16f32, f512mem, SSEPackedSingle>, PD,
4554 EVEX_V512, EVEX_CD8<32, CD8VF>;
4555 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4556 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4557 EVEX_V512, EVEX_CD8<64, CD8VF>;
4559 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4560 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4561 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4563 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4564 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4565 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4567 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4568 loadv16f32, f512mem, SSEPackedSingle>,
4569 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4570 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4571 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4572 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4574 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4575 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4576 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4578 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4579 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4580 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4582 let Predicates = [HasAVX512] in {
4583 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4584 (VCVTPD2PSZrm addr:$src)>;
4585 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4586 (VCVTPS2PDZrm addr:$src)>;
4589 //===----------------------------------------------------------------------===//
4590 // Half precision conversion instructions
4591 //===----------------------------------------------------------------------===//
4592 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4593 X86MemOperand x86memop> {
4594 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4595 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4597 let hasSideEffects = 0, mayLoad = 1 in
4598 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4599 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4602 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4603 X86MemOperand x86memop> {
4604 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4605 (ins srcRC:$src1, i32u8imm:$src2),
4606 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4608 let hasSideEffects = 0, mayStore = 1 in
4609 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4610 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4611 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4614 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4615 EVEX_CD8<32, CD8VH>;
4616 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4617 EVEX_CD8<32, CD8VH>;
4619 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4620 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4621 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4623 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4624 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4625 (VCVTPH2PSZrr VR256X:$src)>;
4627 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4628 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4629 "ucomiss">, PS, EVEX, VEX_LIG,
4630 EVEX_CD8<32, CD8VT1>;
4631 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4632 "ucomisd">, PD, EVEX,
4633 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4634 let Pattern = []<dag> in {
4635 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4636 "comiss">, PS, EVEX, VEX_LIG,
4637 EVEX_CD8<32, CD8VT1>;
4638 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4639 "comisd">, PD, EVEX,
4640 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4642 let isCodeGenOnly = 1 in {
4643 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4644 load, "ucomiss">, PS, EVEX, VEX_LIG,
4645 EVEX_CD8<32, CD8VT1>;
4646 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4647 load, "ucomisd">, PD, EVEX,
4648 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4650 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4651 load, "comiss">, PS, EVEX, VEX_LIG,
4652 EVEX_CD8<32, CD8VT1>;
4653 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4654 load, "comisd">, PD, EVEX,
4655 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4659 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4660 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4661 X86MemOperand x86memop> {
4662 let hasSideEffects = 0 in {
4663 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4664 (ins RC:$src1, RC:$src2),
4665 !strconcat(OpcodeStr,
4666 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4667 let mayLoad = 1 in {
4668 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4669 (ins RC:$src1, x86memop:$src2),
4670 !strconcat(OpcodeStr,
4671 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4676 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4677 EVEX_CD8<32, CD8VT1>;
4678 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4679 VEX_W, EVEX_CD8<64, CD8VT1>;
4680 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4681 EVEX_CD8<32, CD8VT1>;
4682 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4683 VEX_W, EVEX_CD8<64, CD8VT1>;
4685 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4686 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4687 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4688 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4690 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4691 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4692 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4693 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4695 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4696 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4697 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4698 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4700 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4701 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4702 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4703 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4705 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4706 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4707 X86VectorVTInfo _> {
4708 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4709 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4710 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4711 let mayLoad = 1 in {
4712 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4713 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4715 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4716 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4717 (ins _.ScalarMemOp:$src), OpcodeStr,
4718 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4720 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4725 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4726 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4727 EVEX_V512, EVEX_CD8<32, CD8VF>;
4728 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4729 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4731 // Define only if AVX512VL feature is present.
4732 let Predicates = [HasVLX] in {
4733 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4734 OpNode, v4f32x_info>,
4735 EVEX_V128, EVEX_CD8<32, CD8VF>;
4736 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4737 OpNode, v8f32x_info>,
4738 EVEX_V256, EVEX_CD8<32, CD8VF>;
4739 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4740 OpNode, v2f64x_info>,
4741 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4742 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4743 OpNode, v4f64x_info>,
4744 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4748 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4749 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4751 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4752 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4753 (VRSQRT14PSZr VR512:$src)>;
4754 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4755 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4756 (VRSQRT14PDZr VR512:$src)>;
4758 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4759 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4760 (VRCP14PSZr VR512:$src)>;
4761 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4762 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4763 (VRCP14PDZr VR512:$src)>;
4765 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4766 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4769 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4770 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4771 "$src2, $src1", "$src1, $src2",
4772 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4773 (i32 FROUND_CURRENT))>;
4775 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4776 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4777 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4778 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4779 (i32 FROUND_NO_EXC))>, EVEX_B;
4781 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4782 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4783 "$src2, $src1", "$src1, $src2",
4784 (OpNode (_.VT _.RC:$src1),
4785 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4786 (i32 FROUND_CURRENT))>;
4789 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4790 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4791 EVEX_CD8<32, CD8VT1>;
4792 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4793 EVEX_CD8<64, CD8VT1>, VEX_W;
4796 let hasSideEffects = 0, Predicates = [HasERI] in {
4797 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4798 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4800 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4802 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4805 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4806 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4807 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4809 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4810 (ins _.RC:$src), OpcodeStr,
4811 "{sae}, $src", "$src, {sae}",
4812 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
4814 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4815 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4817 (bitconvert (_.LdFrag addr:$src))),
4818 (i32 FROUND_CURRENT))>;
4820 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4821 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4823 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4824 (i32 FROUND_CURRENT))>, EVEX_B;
4827 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4828 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4829 EVEX_CD8<32, CD8VF>;
4830 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4831 VEX_W, EVEX_CD8<32, CD8VF>;
4834 let Predicates = [HasERI], hasSideEffects = 0 in {
4836 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4837 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4838 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4841 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4842 SDNode OpNode, X86VectorVTInfo _>{
4843 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4844 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4845 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4846 let mayLoad = 1 in {
4847 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4848 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4850 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4852 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4853 (ins _.ScalarMemOp:$src), OpcodeStr,
4854 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4856 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4861 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4862 Intrinsic F32Int, Intrinsic F64Int,
4863 OpndItins itins_s, OpndItins itins_d> {
4864 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4865 (ins FR32X:$src1, FR32X:$src2),
4866 !strconcat(OpcodeStr,
4867 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4868 [], itins_s.rr>, XS, EVEX_4V;
4869 let isCodeGenOnly = 1 in
4870 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4871 (ins VR128X:$src1, VR128X:$src2),
4872 !strconcat(OpcodeStr,
4873 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4875 (F32Int VR128X:$src1, VR128X:$src2))],
4876 itins_s.rr>, XS, EVEX_4V;
4877 let mayLoad = 1 in {
4878 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4879 (ins FR32X:$src1, f32mem:$src2),
4880 !strconcat(OpcodeStr,
4881 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4882 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4883 let isCodeGenOnly = 1 in
4884 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4885 (ins VR128X:$src1, ssmem:$src2),
4886 !strconcat(OpcodeStr,
4887 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4889 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4890 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4892 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4893 (ins FR64X:$src1, FR64X:$src2),
4894 !strconcat(OpcodeStr,
4895 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4897 let isCodeGenOnly = 1 in
4898 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4899 (ins VR128X:$src1, VR128X:$src2),
4900 !strconcat(OpcodeStr,
4901 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4903 (F64Int VR128X:$src1, VR128X:$src2))],
4904 itins_s.rr>, XD, EVEX_4V, VEX_W;
4905 let mayLoad = 1 in {
4906 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4907 (ins FR64X:$src1, f64mem:$src2),
4908 !strconcat(OpcodeStr,
4909 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4910 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4911 let isCodeGenOnly = 1 in
4912 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4913 (ins VR128X:$src1, sdmem:$src2),
4914 !strconcat(OpcodeStr,
4915 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4917 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4918 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4922 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4924 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4926 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4927 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4929 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4930 // Define only if AVX512VL feature is present.
4931 let Predicates = [HasVLX] in {
4932 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4933 OpNode, v4f32x_info>,
4934 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4935 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4936 OpNode, v8f32x_info>,
4937 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4938 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4939 OpNode, v2f64x_info>,
4940 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4941 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4942 OpNode, v4f64x_info>,
4943 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4947 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4949 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4950 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4951 SSE_SQRTSS, SSE_SQRTSD>;
4953 let Predicates = [HasAVX512] in {
4954 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4955 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4956 (VSQRTPSZr VR512:$src1)>;
4957 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4958 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4959 (VSQRTPDZr VR512:$src1)>;
4961 def : Pat<(f32 (fsqrt FR32X:$src)),
4962 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4963 def : Pat<(f32 (fsqrt (load addr:$src))),
4964 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4965 Requires<[OptForSize]>;
4966 def : Pat<(f64 (fsqrt FR64X:$src)),
4967 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4968 def : Pat<(f64 (fsqrt (load addr:$src))),
4969 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4970 Requires<[OptForSize]>;
4972 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4973 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4974 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4975 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4976 Requires<[OptForSize]>;
4978 def : Pat<(f32 (X86frcp FR32X:$src)),
4979 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4980 def : Pat<(f32 (X86frcp (load addr:$src))),
4981 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4982 Requires<[OptForSize]>;
4984 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4985 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4986 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4988 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4989 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4991 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4992 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4993 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4995 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4996 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
5000 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
5001 X86MemOperand x86memop, RegisterClass RC,
5002 PatFrag mem_frag, Domain d> {
5003 let ExeDomain = d in {
5004 // Intrinsic operation, reg.
5005 // Vector intrinsic operation, reg
5006 def r : AVX512AIi8<opc, MRMSrcReg,
5007 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
5008 !strconcat(OpcodeStr,
5009 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5012 // Vector intrinsic operation, mem
5013 def m : AVX512AIi8<opc, MRMSrcMem,
5014 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
5015 !strconcat(OpcodeStr,
5016 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5021 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
5022 loadv16f32, SSEPackedSingle>, EVEX_V512,
5023 EVEX_CD8<32, CD8VF>;
5025 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
5026 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
5028 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
5031 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
5032 loadv8f64, SSEPackedDouble>, EVEX_V512,
5033 VEX_W, EVEX_CD8<64, CD8VF>;
5035 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
5036 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
5038 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
5041 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5043 let ExeDomain = _.ExeDomain in {
5044 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5045 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5046 "$src3, $src2, $src1", "$src1, $src2, $src3",
5047 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5048 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5050 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5051 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5052 "{sae}, $src3, $src2, $src1", "$src1, $src2, $src3, {sae}",
5053 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5054 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5057 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5058 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5059 "$src3, $src2, $src1", "$src1, $src2, $src3",
5060 (_.VT (X86RndScale (_.VT _.RC:$src1),
5061 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5062 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5064 let Predicates = [HasAVX512] in {
5065 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5066 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5067 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5068 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5069 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5070 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5071 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5072 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5073 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5074 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5075 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5076 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5077 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5078 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5079 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5081 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5082 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5083 addr:$src, (i32 0x1))), _.FRC)>;
5084 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5085 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5086 addr:$src, (i32 0x2))), _.FRC)>;
5087 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5088 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5089 addr:$src, (i32 0x3))), _.FRC)>;
5090 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5091 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5092 addr:$src, (i32 0x4))), _.FRC)>;
5093 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5094 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5095 addr:$src, (i32 0xc))), _.FRC)>;
5099 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5100 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5102 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5103 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5105 let Predicates = [HasAVX512] in {
5106 def : Pat<(v16f32 (ffloor VR512:$src)),
5107 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
5108 def : Pat<(v16f32 (fnearbyint VR512:$src)),
5109 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
5110 def : Pat<(v16f32 (fceil VR512:$src)),
5111 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
5112 def : Pat<(v16f32 (frint VR512:$src)),
5113 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
5114 def : Pat<(v16f32 (ftrunc VR512:$src)),
5115 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
5117 def : Pat<(v8f64 (ffloor VR512:$src)),
5118 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
5119 def : Pat<(v8f64 (fnearbyint VR512:$src)),
5120 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
5121 def : Pat<(v8f64 (fceil VR512:$src)),
5122 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
5123 def : Pat<(v8f64 (frint VR512:$src)),
5124 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
5125 def : Pat<(v8f64 (ftrunc VR512:$src)),
5126 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
5128 //-------------------------------------------------
5129 // Integer truncate and extend operations
5130 //-------------------------------------------------
5132 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
5133 RegisterClass dstRC, RegisterClass srcRC,
5134 RegisterClass KRC, X86MemOperand x86memop> {
5135 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5137 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5140 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5141 (ins KRC:$mask, srcRC:$src),
5142 !strconcat(OpcodeStr,
5143 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5146 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5147 (ins KRC:$mask, srcRC:$src),
5148 !strconcat(OpcodeStr,
5149 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5152 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
5153 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5156 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5157 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
5158 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
5162 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
5163 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5164 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
5165 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5166 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
5167 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5168 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
5169 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5170 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
5171 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5172 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
5173 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5174 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
5175 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5176 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
5177 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5178 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
5179 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5180 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
5181 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5182 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
5183 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5184 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
5185 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5186 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
5187 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5188 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
5189 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5190 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
5191 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5193 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
5194 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
5195 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
5196 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
5197 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
5199 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5200 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
5201 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5202 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
5203 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5204 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
5205 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5206 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
5209 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
5210 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
5211 PatFrag mem_frag, X86MemOperand x86memop,
5212 ValueType OpVT, ValueType InVT> {
5214 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
5216 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5217 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
5219 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
5220 (ins KRC:$mask, SrcRC:$src),
5221 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
5224 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
5225 (ins KRC:$mask, SrcRC:$src),
5226 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5229 let mayLoad = 1 in {
5230 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5231 (ins x86memop:$src),
5232 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5234 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
5237 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5238 (ins KRC:$mask, x86memop:$src),
5239 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
5243 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
5244 (ins KRC:$mask, x86memop:$src),
5245 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5251 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
5252 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
5254 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
5255 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
5257 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
5258 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
5259 EVEX_CD8<16, CD8VH>;
5260 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
5261 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
5262 EVEX_CD8<16, CD8VQ>;
5263 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
5264 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
5265 EVEX_CD8<32, CD8VH>;
5267 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
5268 loadv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
5270 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
5271 loadv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
5273 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
5274 loadv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
5275 EVEX_CD8<16, CD8VH>;
5276 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
5277 loadv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
5278 EVEX_CD8<16, CD8VQ>;
5279 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
5280 loadv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
5281 EVEX_CD8<32, CD8VH>;
5283 //===----------------------------------------------------------------------===//
5284 // GATHER - SCATTER Operations
5286 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5287 X86MemOperand memop, PatFrag GatherNode> {
5288 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
5289 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
5290 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
5291 !strconcat(OpcodeStr,
5292 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5293 [(set _.RC:$dst, _.KRCWM:$mask_wb,
5294 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
5295 vectoraddr:$src2))]>, EVEX, EVEX_K,
5296 EVEX_CD8<_.EltSize, CD8VT1>;
5299 let ExeDomain = SSEPackedDouble in {
5300 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", v8f64_info, vy64xmem,
5301 mgatherv8i32>, EVEX_V512, VEX_W;
5302 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", v8f64_info, vz64mem,
5303 mgatherv8i64>, EVEX_V512, VEX_W;
5306 let ExeDomain = SSEPackedSingle in {
5307 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", v16f32_info, vz32mem,
5308 mgatherv16i32>, EVEX_V512;
5309 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", v8f32x_info, vz64mem,
5310 mgatherv8i64>, EVEX_V512;
5313 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", v8i64_info, vy64xmem,
5314 mgatherv8i32>, EVEX_V512, VEX_W;
5315 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", v16i32_info, vz32mem,
5316 mgatherv16i32>, EVEX_V512;
5318 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", v8i64_info, vz64mem,
5319 mgatherv8i64>, EVEX_V512, VEX_W;
5320 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", v8i32x_info, vz64mem,
5321 mgatherv8i64>, EVEX_V512;
5323 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5324 X86MemOperand memop, PatFrag ScatterNode> {
5326 let mayStore = 1, Constraints = "$mask = $mask_wb" in
5328 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
5329 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
5330 !strconcat(OpcodeStr,
5331 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5332 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
5333 _.KRCWM:$mask, vectoraddr:$dst))]>,
5334 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5337 let ExeDomain = SSEPackedDouble in {
5338 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", v8f64_info, vy64xmem,
5339 mscatterv8i32>, EVEX_V512, VEX_W;
5340 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", v8f64_info, vz64mem,
5341 mscatterv8i64>, EVEX_V512, VEX_W;
5344 let ExeDomain = SSEPackedSingle in {
5345 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", v16f32_info, vz32mem,
5346 mscatterv16i32>, EVEX_V512;
5347 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", v8f32x_info, vz64mem,
5348 mscatterv8i64>, EVEX_V512;
5351 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", v8i64_info, vy64xmem,
5352 mscatterv8i32>, EVEX_V512, VEX_W;
5353 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", v16i32_info, vz32mem,
5354 mscatterv16i32>, EVEX_V512;
5356 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", v8i64_info, vz64mem,
5357 mscatterv8i64>, EVEX_V512, VEX_W;
5358 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", v8i32x_info, vz64mem,
5359 mscatterv8i64>, EVEX_V512;
5362 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
5363 RegisterClass KRC, X86MemOperand memop> {
5364 let Predicates = [HasPFI], hasSideEffects = 1 in
5365 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
5366 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
5370 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
5371 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5373 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5374 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5376 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5377 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5379 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
5380 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5382 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
5383 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5385 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
5386 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5388 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5389 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5391 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5392 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5394 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5395 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5397 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5398 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5400 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5401 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5403 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5404 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5406 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5407 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5409 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5410 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5412 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5413 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5415 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5416 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5417 //===----------------------------------------------------------------------===//
5418 // VSHUFPS - VSHUFPD Operations
5420 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5421 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5423 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5424 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5425 !strconcat(OpcodeStr,
5426 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5427 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5428 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5429 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5430 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5431 (ins RC:$src1, RC:$src2, u8imm:$src3),
5432 !strconcat(OpcodeStr,
5433 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5434 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5435 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5436 EVEX_4V, Sched<[WriteShuffle]>;
5439 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5440 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5441 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5442 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5444 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5445 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5446 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5447 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5448 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5450 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5451 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5452 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5453 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5454 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5456 multiclass avx512_valign<X86VectorVTInfo _> {
5457 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5458 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5460 "$src3, $src2, $src1", "$src1, $src2, $src3",
5461 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5463 AVX512AIi8Base, EVEX_4V;
5465 // Also match valign of packed floats.
5466 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5467 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5470 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5471 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5472 !strconcat("valign"##_.Suffix,
5473 "\t{$src3, $src2, $src1, $dst|"
5474 "$dst, $src1, $src2, $src3}"),
5477 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5478 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5480 // Helper fragments to match sext vXi1 to vXiY.
5481 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5482 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5484 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5485 RegisterClass KRC, RegisterClass RC,
5486 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5488 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5489 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5491 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5492 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5494 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5495 !strconcat(OpcodeStr,
5496 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5498 let mayLoad = 1 in {
5499 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5500 (ins x86memop:$src),
5501 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5503 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5504 (ins KRC:$mask, x86memop:$src),
5505 !strconcat(OpcodeStr,
5506 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5508 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5509 (ins KRC:$mask, x86memop:$src),
5510 !strconcat(OpcodeStr,
5511 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5513 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5514 (ins x86scalar_mop:$src),
5515 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5516 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5518 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5519 (ins KRC:$mask, x86scalar_mop:$src),
5520 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5521 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5522 []>, EVEX, EVEX_B, EVEX_K;
5523 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5524 (ins KRC:$mask, x86scalar_mop:$src),
5525 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5526 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5528 []>, EVEX, EVEX_B, EVEX_KZ;
5532 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5533 i512mem, i32mem, "{1to16}">, EVEX_V512,
5534 EVEX_CD8<32, CD8VF>;
5535 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5536 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5537 EVEX_CD8<64, CD8VF>;
5540 (bc_v16i32 (v16i1sextv16i32)),
5541 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5542 (VPABSDZrr VR512:$src)>;
5544 (bc_v8i64 (v8i1sextv8i64)),
5545 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5546 (VPABSQZrr VR512:$src)>;
5548 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5549 (v16i32 immAllZerosV), (i16 -1))),
5550 (VPABSDZrr VR512:$src)>;
5551 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5552 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5553 (VPABSQZrr VR512:$src)>;
5555 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5556 RegisterClass RC, RegisterClass KRC,
5557 X86MemOperand x86memop,
5558 X86MemOperand x86scalar_mop, string BrdcstStr> {
5559 let hasSideEffects = 0 in {
5560 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5562 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5566 (ins x86memop:$src),
5567 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5570 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5571 (ins x86scalar_mop:$src),
5572 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5573 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5575 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5576 (ins KRC:$mask, RC:$src),
5577 !strconcat(OpcodeStr,
5578 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5581 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5582 (ins KRC:$mask, x86memop:$src),
5583 !strconcat(OpcodeStr,
5584 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5587 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5588 (ins KRC:$mask, x86scalar_mop:$src),
5589 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5590 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5592 []>, EVEX, EVEX_KZ, EVEX_B;
5594 let Constraints = "$src1 = $dst" in {
5595 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5596 (ins RC:$src1, KRC:$mask, RC:$src2),
5597 !strconcat(OpcodeStr,
5598 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5601 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5602 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5603 !strconcat(OpcodeStr,
5604 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5607 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5608 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5609 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5610 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5611 []>, EVEX, EVEX_K, EVEX_B;
5616 let Predicates = [HasCDI] in {
5617 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5618 i512mem, i32mem, "{1to16}">,
5619 EVEX_V512, EVEX_CD8<32, CD8VF>;
5622 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5623 i512mem, i64mem, "{1to8}">,
5624 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5628 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5630 (VPCONFLICTDrrk VR512:$src1,
5631 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5633 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5635 (VPCONFLICTQrrk VR512:$src1,
5636 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5638 let Predicates = [HasCDI] in {
5639 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5640 i512mem, i32mem, "{1to16}">,
5641 EVEX_V512, EVEX_CD8<32, CD8VF>;
5644 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5645 i512mem, i64mem, "{1to8}">,
5646 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5650 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5652 (VPLZCNTDrrk VR512:$src1,
5653 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5655 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5657 (VPLZCNTQrrk VR512:$src1,
5658 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5660 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5661 (VPLZCNTDrm addr:$src)>;
5662 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5663 (VPLZCNTDrr VR512:$src)>;
5664 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5665 (VPLZCNTQrm addr:$src)>;
5666 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5667 (VPLZCNTQrr VR512:$src)>;
5669 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5670 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5671 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5673 def : Pat<(store VK1:$src, addr:$dst),
5675 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5676 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5678 def : Pat<(store VK8:$src, addr:$dst),
5680 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5681 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5683 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5684 (truncstore node:$val, node:$ptr), [{
5685 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5688 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5689 (MOV8mr addr:$dst, GR8:$src)>;
5691 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5692 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5693 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5694 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5697 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5698 string OpcodeStr, Predicate prd> {
5699 let Predicates = [prd] in
5700 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5702 let Predicates = [prd, HasVLX] in {
5703 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5704 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5708 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5709 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5711 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5713 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5715 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5719 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5721 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
5722 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
5723 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5724 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
5727 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
5728 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
5729 let Predicates = [prd] in
5730 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
5733 let Predicates = [prd, HasVLX] in {
5734 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
5736 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
5741 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
5742 avx512vl_i8_info, HasBWI>;
5743 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
5744 avx512vl_i16_info, HasBWI>, VEX_W;
5745 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
5746 avx512vl_i32_info, HasDQI>;
5747 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
5748 avx512vl_i64_info, HasDQI>, VEX_W;
5750 //===----------------------------------------------------------------------===//
5751 // AVX-512 - COMPRESS and EXPAND
5753 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5755 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5756 (ins _.KRCWM:$mask, _.RC:$src),
5757 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5758 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5759 _.ImmAllZerosV)))]>, EVEX_KZ;
5761 let Constraints = "$src0 = $dst" in
5762 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5763 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5764 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5765 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5766 _.RC:$src0)))]>, EVEX_K;
5768 let mayStore = 1 in {
5769 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5770 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5771 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5772 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5774 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5778 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5779 AVX512VLVectorVTInfo VTInfo> {
5780 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5782 let Predicates = [HasVLX] in {
5783 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5784 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5788 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5790 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5792 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5794 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5798 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5800 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5801 (ins _.KRCWM:$mask, _.RC:$src),
5802 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5803 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5804 _.ImmAllZerosV)))]>, EVEX_KZ;
5806 let Constraints = "$src0 = $dst" in
5807 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5808 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5809 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5810 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5811 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5813 let mayLoad = 1, Constraints = "$src0 = $dst" in
5814 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5815 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5816 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5817 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5819 (_.LdFrag addr:$src))),
5821 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5824 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5825 (ins _.KRCWM:$mask, _.MemOp:$src),
5826 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5827 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5828 (_.VT (bitconvert (_.LdFrag addr:$src))),
5829 _.ImmAllZerosV)))]>,
5830 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5834 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5835 AVX512VLVectorVTInfo VTInfo> {
5836 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5838 let Predicates = [HasVLX] in {
5839 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5840 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5844 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5846 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5848 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5850 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,