1 // Group template arguments that can be derived from the vector type (EltNum x
2 // EltVT). These are things like the register class for the writemask, etc.
3 // The idea is to pass one of these as the template argument rather than the
4 // individual arguments.
5 // The template is also used for scalar types, in this case numelts is 1.
6 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
9 ValueType EltVT = eltvt;
10 int NumElts = numelts;
12 // Corresponding mask register class.
13 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
15 // Corresponding write-mask register class.
16 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
18 // The GPR register class that can hold the write mask. Use GR8 for fewer
19 // than 8 elements. Use shift-right and equal to work around the lack of
22 !cast<RegisterClass>("GR" #
23 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
25 // Suffix used in the instruction mnemonic.
26 string Suffix = suffix;
28 // VTName is a string name for vector VT. For vector types it will be
29 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
30 // It is a little bit complex for scalar types, where NumElts = 1.
31 // In this case we build v4f32 or v2f64
32 string VTName = "v" # !if (!eq (NumElts, 1),
33 !if (!eq (EltVT.Size, 32), 4,
34 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
37 ValueType VT = !cast<ValueType>(VTName);
39 string EltTypeName = !cast<string>(EltVT);
40 // Size of the element type in bits, e.g. 32 for v16i32.
41 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
42 int EltSize = EltVT.Size;
44 // "i" for integer types and "f" for floating-point types
45 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
47 // Size of RC in bits, e.g. 512 for VR512.
50 // The corresponding memory operand, e.g. i512mem for VR512.
51 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
52 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
55 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
56 // due to load promotion during legalization
57 PatFrag LdFrag = !cast<PatFrag>("load" #
58 !if (!eq (TypeVariantName, "i"),
59 !if (!eq (Size, 128), "v2i64",
60 !if (!eq (Size, 256), "v4i64",
62 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
64 // Load patterns used for memory operands. We only have this defined in
65 // case of i64 element types for sub-512 integer vectors. For now, keep
66 // MemOpFrag undefined in these cases.
68 !if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
69 !if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
70 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
71 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
72 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
74 // The corresponding float type, e.g. v16f32 for v16i32
75 // Note: For EltSize < 32, FloatVT is illegal and TableGen
76 // fails to compile, so we choose FloatVT = VT
77 ValueType FloatVT = !cast<ValueType>(
78 !if (!eq (!srl(EltSize,5),0),
80 !if (!eq(TypeVariantName, "i"),
81 "v" # NumElts # "f" # EltSize,
84 // The string to specify embedded broadcast in assembly.
85 string BroadcastStr = "{1to" # NumElts # "}";
87 // 8-bit compressed displacement tuple/subvector format. This is only
88 // defined for NumElts <= 8.
89 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
90 !cast<CD8VForm>("CD8VT" # NumElts), ?);
92 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
93 !if (!eq (Size, 256), sub_ymm, ?));
95 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
96 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
99 // A vector type of the same width with element type i32. This is used to
100 // create the canonical constant zero node ImmAllZerosV.
101 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
102 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
105 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
106 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
107 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
108 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
109 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
110 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
112 // "x" in v32i8x_info means RC = VR256X
113 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
114 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
115 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
116 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
117 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
118 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
120 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
121 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
122 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
123 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
124 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
125 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
127 // We map scalar types to the smallest (128-bit) vector type
128 // with the appropriate element type. This allows to use the same masking logic.
129 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
130 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
132 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
133 X86VectorVTInfo i128> {
134 X86VectorVTInfo info512 = i512;
135 X86VectorVTInfo info256 = i256;
136 X86VectorVTInfo info128 = i128;
139 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
141 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
143 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
145 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
147 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
149 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
152 // This multiclass generates the masking variants from the non-masking
153 // variant. It only provides the assembly pieces for the masking variants.
154 // It assumes custom ISel patterns for masking which can be provided as
155 // template arguments.
156 multiclass AVX512_maskable_custom<bits<8> O, Format F,
158 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
160 string AttSrcAsm, string IntelSrcAsm,
162 list<dag> MaskingPattern,
163 list<dag> ZeroMaskingPattern,
165 string MaskingConstraint = "",
166 InstrItinClass itin = NoItinerary,
167 bit IsCommutable = 0> {
168 let isCommutable = IsCommutable in
169 def NAME: AVX512<O, F, Outs, Ins,
170 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
171 "$dst "#Round#", "#IntelSrcAsm#"}",
174 // Prefer over VMOV*rrk Pat<>
175 let AddedComplexity = 20 in
176 def NAME#k: AVX512<O, F, Outs, MaskingIns,
177 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}"#Round#"|"#
178 "$dst {${mask}}"#Round#", "#IntelSrcAsm#"}",
179 MaskingPattern, itin>,
181 // In case of the 3src subclass this is overridden with a let.
182 string Constraints = MaskingConstraint;
184 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
185 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
186 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}"#Round#"|"#
187 "$dst {${mask}} {z}"#Round#", "#IntelSrcAsm#"}",
194 // Common base class of AVX512_maskable and AVX512_maskable_3src.
195 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
197 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
199 string AttSrcAsm, string IntelSrcAsm,
200 dag RHS, dag MaskingRHS,
201 SDNode Select = vselect, string Round = "",
202 string MaskingConstraint = "",
203 InstrItinClass itin = NoItinerary,
204 bit IsCommutable = 0> :
205 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
206 AttSrcAsm, IntelSrcAsm,
207 [(set _.RC:$dst, RHS)],
208 [(set _.RC:$dst, MaskingRHS)],
210 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
211 Round, MaskingConstraint, NoItinerary, IsCommutable>;
213 // This multiclass generates the unconditional/non-masking, the masking and
214 // the zero-masking variant of the vector instruction. In the masking case, the
215 // perserved vector elements come from a new dummy input operand tied to $dst.
216 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Outs, dag Ins, string OpcodeStr,
218 string AttSrcAsm, string IntelSrcAsm,
219 dag RHS, string Round = "",
220 InstrItinClass itin = NoItinerary,
221 bit IsCommutable = 0> :
222 AVX512_maskable_common<O, F, _, Outs, Ins,
223 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
224 !con((ins _.KRCWM:$mask), Ins),
225 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
226 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
227 Round, "$src0 = $dst", itin, IsCommutable>;
229 // This multiclass generates the unconditional/non-masking, the masking and
230 // the zero-masking variant of the scalar instruction.
231 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
232 dag Outs, dag Ins, string OpcodeStr,
233 string AttSrcAsm, string IntelSrcAsm,
234 dag RHS, string Round = "",
235 InstrItinClass itin = NoItinerary,
236 bit IsCommutable = 0> :
237 AVX512_maskable_common<O, F, _, Outs, Ins,
238 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
239 !con((ins _.KRCWM:$mask), Ins),
240 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
241 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
242 Round, "$src0 = $dst", itin, IsCommutable>;
244 // Similar to AVX512_maskable but in this case one of the source operands
245 // ($src1) is already tied to $dst so we just use that for the preserved
246 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
248 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
249 dag Outs, dag NonTiedIns, string OpcodeStr,
250 string AttSrcAsm, string IntelSrcAsm,
252 AVX512_maskable_common<O, F, _, Outs,
253 !con((ins _.RC:$src1), NonTiedIns),
254 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
255 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
256 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
257 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
260 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
263 string AttSrcAsm, string IntelSrcAsm,
265 AVX512_maskable_custom<O, F, Outs, Ins,
266 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
267 !con((ins _.KRCWM:$mask), Ins),
268 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [], "",
271 // Bitcasts between 512-bit vector types. Return the original type since
272 // no instruction is needed for the conversion
273 let Predicates = [HasAVX512] in {
274 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
275 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
276 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
277 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
278 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
279 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
280 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
281 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
282 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
283 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
284 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
285 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
286 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
287 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
288 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
289 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
290 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
291 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
292 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
293 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
294 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
295 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
296 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
297 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
298 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
299 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
300 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
301 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
302 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
303 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
304 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
306 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
307 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
308 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
309 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
310 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
311 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
312 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
313 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
314 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
315 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
316 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
317 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
318 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
319 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
320 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
321 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
322 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
323 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
324 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
325 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
326 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
327 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
328 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
329 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
330 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
331 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
332 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
333 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
334 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
335 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
337 // Bitcasts between 256-bit vector types. Return the original type since
338 // no instruction is needed for the conversion
339 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
340 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
341 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
342 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
343 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
344 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
346 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
347 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
348 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
350 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
351 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
352 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
353 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
355 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
357 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
358 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
359 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
360 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
361 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
363 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
365 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
367 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
368 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
372 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
375 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
376 isPseudo = 1, Predicates = [HasAVX512] in {
377 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
378 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
381 let Predicates = [HasAVX512] in {
382 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
383 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
384 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
387 //===----------------------------------------------------------------------===//
388 // AVX-512 - VECTOR INSERT
391 multiclass vinsert_for_size_no_alt<int Opcode,
392 X86VectorVTInfo From, X86VectorVTInfo To,
393 PatFrag vinsert_insert,
394 SDNodeXForm INSERT_get_vinsert_imm> {
395 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
396 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
397 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
398 "vinsert" # From.EltTypeName # "x" # From.NumElts #
399 "\t{$src3, $src2, $src1, $dst|"
400 "$dst, $src1, $src2, $src3}",
401 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
402 (From.VT From.RC:$src2),
407 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
408 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
409 "vinsert" # From.EltTypeName # "x" # From.NumElts #
410 "\t{$src3, $src2, $src1, $dst|"
411 "$dst, $src1, $src2, $src3}",
413 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
417 multiclass vinsert_for_size<int Opcode,
418 X86VectorVTInfo From, X86VectorVTInfo To,
419 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
420 PatFrag vinsert_insert,
421 SDNodeXForm INSERT_get_vinsert_imm> :
422 vinsert_for_size_no_alt<Opcode, From, To,
423 vinsert_insert, INSERT_get_vinsert_imm> {
424 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
425 // vinserti32x4. Only add this if 64x2 and friends are not supported
426 // natively via AVX512DQ.
427 let Predicates = [NoDQI] in
428 def : Pat<(vinsert_insert:$ins
429 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
430 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
431 VR512:$src1, From.RC:$src2,
432 (INSERT_get_vinsert_imm VR512:$ins)))>;
435 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
436 ValueType EltVT64, int Opcode256> {
437 defm NAME # "32x4" : vinsert_for_size<Opcode128,
438 X86VectorVTInfo< 4, EltVT32, VR128X>,
439 X86VectorVTInfo<16, EltVT32, VR512>,
440 X86VectorVTInfo< 2, EltVT64, VR128X>,
441 X86VectorVTInfo< 8, EltVT64, VR512>,
443 INSERT_get_vinsert128_imm>;
444 let Predicates = [HasDQI] in
445 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
446 X86VectorVTInfo< 2, EltVT64, VR128X>,
447 X86VectorVTInfo< 8, EltVT64, VR512>,
449 INSERT_get_vinsert128_imm>, VEX_W;
450 defm NAME # "64x4" : vinsert_for_size<Opcode256,
451 X86VectorVTInfo< 4, EltVT64, VR256X>,
452 X86VectorVTInfo< 8, EltVT64, VR512>,
453 X86VectorVTInfo< 8, EltVT32, VR256>,
454 X86VectorVTInfo<16, EltVT32, VR512>,
456 INSERT_get_vinsert256_imm>, VEX_W;
457 let Predicates = [HasDQI] in
458 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
459 X86VectorVTInfo< 8, EltVT32, VR256X>,
460 X86VectorVTInfo<16, EltVT32, VR512>,
462 INSERT_get_vinsert256_imm>;
465 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
466 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
468 // vinsertps - insert f32 to XMM
469 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
470 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
471 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
472 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
474 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
475 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
476 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
477 [(set VR128X:$dst, (X86insertps VR128X:$src1,
478 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
479 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
481 //===----------------------------------------------------------------------===//
482 // AVX-512 VECTOR EXTRACT
485 multiclass vextract_for_size<int Opcode,
486 X86VectorVTInfo From, X86VectorVTInfo To,
487 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
488 PatFrag vextract_extract,
489 SDNodeXForm EXTRACT_get_vextract_imm> {
490 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
491 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
492 (ins VR512:$src1, i8imm:$idx),
493 "vextract" # To.EltTypeName # "x4",
494 "$idx, $src1", "$src1, $idx",
495 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
497 AVX512AIi8Base, EVEX, EVEX_V512;
499 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
500 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
501 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
502 "$dst, $src1, $src2}",
503 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
506 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
508 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
509 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
511 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
513 // A 128/256-bit subvector extract from the first 512-bit vector position is
514 // a subregister copy that needs no instruction.
515 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
517 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
519 // And for the alternative types.
520 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
522 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
524 // Intrinsic call with masking.
525 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
527 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
528 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
529 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
530 VR512:$src1, imm:$idx)>;
532 // Intrinsic call with zero-masking.
533 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
535 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
536 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
537 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
538 VR512:$src1, imm:$idx)>;
540 // Intrinsic call without masking.
541 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
543 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
544 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
545 VR512:$src1, imm:$idx)>;
548 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
549 ValueType EltVT64, int Opcode64> {
550 defm NAME # "32x4" : vextract_for_size<Opcode32,
551 X86VectorVTInfo<16, EltVT32, VR512>,
552 X86VectorVTInfo< 4, EltVT32, VR128X>,
553 X86VectorVTInfo< 8, EltVT64, VR512>,
554 X86VectorVTInfo< 2, EltVT64, VR128X>,
556 EXTRACT_get_vextract128_imm>;
557 defm NAME # "64x4" : vextract_for_size<Opcode64,
558 X86VectorVTInfo< 8, EltVT64, VR512>,
559 X86VectorVTInfo< 4, EltVT64, VR256X>,
560 X86VectorVTInfo<16, EltVT32, VR512>,
561 X86VectorVTInfo< 8, EltVT32, VR256>,
563 EXTRACT_get_vextract256_imm>, VEX_W;
566 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
567 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
569 // A 128-bit subvector insert to the first 512-bit vector position
570 // is a subregister copy that needs no instruction.
571 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
572 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
573 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
575 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
576 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
577 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
579 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
580 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
581 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
583 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
584 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
585 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
588 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
589 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
590 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
591 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
592 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
593 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
594 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
595 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
597 // vextractps - extract 32 bits from XMM
598 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
599 (ins VR128X:$src1, i32i8imm:$src2),
600 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
601 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
604 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
605 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
606 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
607 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
608 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
610 //===---------------------------------------------------------------------===//
613 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
614 ValueType svt, X86VectorVTInfo _> {
615 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
616 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
617 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
621 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
622 (ins _.ScalarMemOp:$src),
623 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
624 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
629 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
630 AVX512VLVectorVTInfo _> {
631 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
634 let Predicates = [HasVLX] in {
635 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
640 let ExeDomain = SSEPackedSingle in {
641 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
642 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
643 let Predicates = [HasVLX] in {
644 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
645 v4f32, v4f32x_info>, EVEX_V128,
646 EVEX_CD8<32, CD8VT1>;
650 let ExeDomain = SSEPackedDouble in {
651 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
652 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
655 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
656 // Later, we can canonize broadcast instructions before ISel phase and
657 // eliminate additional patterns on ISel.
658 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
659 // representations of source
660 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
661 X86VectorVTInfo _, RegisterClass SrcRC_v,
662 RegisterClass SrcRC_s> {
663 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
664 (!cast<Instruction>(InstName##"r")
665 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
667 let AddedComplexity = 30 in {
668 def : Pat<(_.VT (vselect _.KRCWM:$mask,
669 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
670 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
671 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
673 def : Pat<(_.VT(vselect _.KRCWM:$mask,
674 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
675 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
676 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
680 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
682 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
685 let Predicates = [HasVLX] in {
686 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
687 v8f32x_info, VR128X, FR32X>;
688 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
689 v4f32x_info, VR128X, FR32X>;
690 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
691 v4f64x_info, VR128X, FR64X>;
694 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
695 (VBROADCASTSSZm addr:$src)>;
696 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
697 (VBROADCASTSDZm addr:$src)>;
699 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
700 (VBROADCASTSSZm addr:$src)>;
701 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
702 (VBROADCASTSDZm addr:$src)>;
704 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
705 RegisterClass SrcRC> {
706 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
707 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
708 "$src", "$src", []>, T8PD, EVEX;
711 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
712 RegisterClass SrcRC, Predicate prd> {
713 let Predicates = [prd] in
714 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
715 let Predicates = [prd, HasVLX] in {
716 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
717 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
721 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
723 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
725 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
727 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
730 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
731 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
733 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
734 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
736 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
737 (VPBROADCASTDrZr GR32:$src)>;
738 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
739 (VPBROADCASTDrZrkz VK16WM:$mask, GR32:$src)>;
740 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
741 (VPBROADCASTQrZr GR64:$src)>;
742 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
743 (VPBROADCASTQrZrkz VK8WM:$mask, GR64:$src)>;
745 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
746 (VPBROADCASTDrZr GR32:$src)>;
747 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
748 (VPBROADCASTQrZr GR64:$src)>;
750 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
751 (v16i32 immAllZerosV), (i16 GR16:$mask))),
752 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
753 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
754 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
755 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
757 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
758 X86MemOperand x86memop, PatFrag ld_frag,
759 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
761 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
764 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
765 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
767 !strconcat(OpcodeStr,
768 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
770 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
773 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
774 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
776 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
777 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
779 !strconcat(OpcodeStr,
780 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
781 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
782 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
786 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
787 loadi32, VR512, v16i32, v4i32, VK16WM>,
788 EVEX_V512, EVEX_CD8<32, CD8VT1>;
789 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
790 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
791 EVEX_CD8<64, CD8VT1>;
793 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
794 X86MemOperand x86memop, PatFrag ld_frag,
797 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
800 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
802 !strconcat(OpcodeStr,
803 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
808 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
809 i128mem, loadv2i64, VK16WM>,
810 EVEX_V512, EVEX_CD8<32, CD8VT4>;
811 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
812 i256mem, loadv4i64, VK16WM>, VEX_W,
813 EVEX_V512, EVEX_CD8<64, CD8VT4>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
816 (VPBROADCASTDZrr VR128X:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
818 (VPBROADCASTQZrr VR128X:$src)>;
820 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
821 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
822 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
823 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
825 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
826 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
827 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
828 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
830 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
831 (VBROADCASTSSZr VR128X:$src)>;
832 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
833 (VBROADCASTSDZr VR128X:$src)>;
835 // Provide fallback in case the load node that is used in the patterns above
836 // is used by additional users, which prevents the pattern selection.
837 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
838 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
839 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
840 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
843 let Predicates = [HasAVX512] in {
844 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
846 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
847 addr:$src)), sub_ymm)>;
849 //===----------------------------------------------------------------------===//
850 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
853 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
855 let Predicates = [HasCDI] in
856 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
858 []>, EVEX, EVEX_V512;
860 let Predicates = [HasCDI, HasVLX] in {
861 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
862 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
863 []>, EVEX, EVEX_V128;
864 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
865 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
866 []>, EVEX, EVEX_V256;
870 let Predicates = [HasCDI] in {
871 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
873 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
877 //===----------------------------------------------------------------------===//
880 // -- immediate form --
881 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
883 let ExeDomain = _.ExeDomain in {
884 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
885 (ins _.RC:$src1, i8imm:$src2),
886 !strconcat(OpcodeStr,
887 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
889 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
891 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
892 (ins _.MemOp:$src1, i8imm:$src2),
893 !strconcat(OpcodeStr,
894 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
896 (_.VT (OpNode (_.MemOpFrag addr:$src1),
898 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
902 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
903 X86VectorVTInfo Ctrl> :
904 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
905 let ExeDomain = _.ExeDomain in {
906 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
907 (ins _.RC:$src1, _.RC:$src2),
908 !strconcat("vpermil" # _.Suffix,
909 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
911 (_.VT (X86VPermilpv _.RC:$src1,
912 (Ctrl.VT Ctrl.RC:$src2))))]>,
914 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
915 (ins _.RC:$src1, Ctrl.MemOp:$src2),
916 !strconcat("vpermil" # _.Suffix,
917 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
919 (_.VT (X86VPermilpv _.RC:$src1,
920 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
925 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
927 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
930 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
932 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
935 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
936 (VPERMILPSZri VR512:$src1, imm:$imm)>;
937 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
938 (VPERMILPDZri VR512:$src1, imm:$imm)>;
940 // -- VPERM - register form --
941 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
942 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
944 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
945 (ins RC:$src1, RC:$src2),
946 !strconcat(OpcodeStr,
947 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
949 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
951 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
952 (ins RC:$src1, x86memop:$src2),
953 !strconcat(OpcodeStr,
954 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
956 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
960 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
961 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
962 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
963 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
964 let ExeDomain = SSEPackedSingle in
965 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
966 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
967 let ExeDomain = SSEPackedDouble in
968 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
969 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
971 // -- VPERM2I - 3 source operands form --
972 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
973 PatFrag mem_frag, X86MemOperand x86memop,
974 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
975 let Constraints = "$src1 = $dst" in {
976 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
977 (ins RC:$src1, RC:$src2, RC:$src3),
978 !strconcat(OpcodeStr,
979 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
981 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
984 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
985 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
986 !strconcat(OpcodeStr,
987 "\t{$src3, $src2, $dst {${mask}}|"
988 "$dst {${mask}}, $src2, $src3}"),
989 [(set RC:$dst, (OpVT (vselect KRC:$mask,
990 (OpNode RC:$src1, RC:$src2,
995 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
996 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
997 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
998 !strconcat(OpcodeStr,
999 "\t{$src3, $src2, $dst {${mask}} {z} |",
1000 "$dst {${mask}} {z}, $src2, $src3}"),
1001 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1002 (OpNode RC:$src1, RC:$src2,
1005 (v16i32 immAllZerosV))))))]>,
1008 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1009 (ins RC:$src1, RC:$src2, x86memop:$src3),
1010 !strconcat(OpcodeStr,
1011 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
1013 (OpVT (OpNode RC:$src1, RC:$src2,
1014 (mem_frag addr:$src3))))]>, EVEX_4V;
1016 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1017 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1018 !strconcat(OpcodeStr,
1019 "\t{$src3, $src2, $dst {${mask}}|"
1020 "$dst {${mask}}, $src2, $src3}"),
1022 (OpVT (vselect KRC:$mask,
1023 (OpNode RC:$src1, RC:$src2,
1024 (mem_frag addr:$src3)),
1028 let AddedComplexity = 10 in // Prefer over the rrkz variant
1029 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1030 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
1031 !strconcat(OpcodeStr,
1032 "\t{$src3, $src2, $dst {${mask}} {z}|"
1033 "$dst {${mask}} {z}, $src2, $src3}"),
1035 (OpVT (vselect KRC:$mask,
1036 (OpNode RC:$src1, RC:$src2,
1037 (mem_frag addr:$src3)),
1039 (v16i32 immAllZerosV))))))]>,
1043 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
1044 i512mem, X86VPermiv3, v16i32, VK16WM>,
1045 EVEX_V512, EVEX_CD8<32, CD8VF>;
1046 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
1047 i512mem, X86VPermiv3, v8i64, VK8WM>,
1048 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1049 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
1050 i512mem, X86VPermiv3, v16f32, VK16WM>,
1051 EVEX_V512, EVEX_CD8<32, CD8VF>;
1052 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
1053 i512mem, X86VPermiv3, v8f64, VK8WM>,
1054 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1056 multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
1057 PatFrag mem_frag, X86MemOperand x86memop,
1058 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
1059 ValueType MaskVT, RegisterClass MRC> :
1060 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
1062 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1063 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
1064 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
1066 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
1067 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
1068 (!cast<Instruction>(NAME#rrk) VR512:$src1,
1069 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
1072 defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
1073 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
1074 EVEX_V512, EVEX_CD8<32, CD8VF>;
1075 defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
1076 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
1077 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1078 defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
1079 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
1080 EVEX_V512, EVEX_CD8<32, CD8VF>;
1081 defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
1082 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
1083 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1085 //===----------------------------------------------------------------------===//
1086 // AVX-512 - BLEND using mask
1088 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1089 let ExeDomain = _.ExeDomain in {
1090 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1091 (ins _.RC:$src1, _.RC:$src2),
1092 !strconcat(OpcodeStr,
1093 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1095 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1096 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1097 !strconcat(OpcodeStr,
1098 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1099 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1100 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1101 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1102 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1103 !strconcat(OpcodeStr,
1104 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1105 []>, EVEX_4V, EVEX_KZ;
1106 let mayLoad = 1 in {
1107 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1108 (ins _.RC:$src1, _.MemOp:$src2),
1109 !strconcat(OpcodeStr,
1110 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1111 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1112 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1113 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1114 !strconcat(OpcodeStr,
1115 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1116 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1117 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1118 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1119 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1120 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1121 !strconcat(OpcodeStr,
1122 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1123 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1127 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1129 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1130 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1131 !strconcat(OpcodeStr,
1132 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1133 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1134 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1135 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1136 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1138 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1139 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1140 !strconcat(OpcodeStr,
1141 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1142 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1143 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1147 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1148 AVX512VLVectorVTInfo VTInfo> {
1149 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1150 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1152 let Predicates = [HasVLX] in {
1153 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1154 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1155 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1156 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1160 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1161 AVX512VLVectorVTInfo VTInfo> {
1162 let Predicates = [HasBWI] in
1163 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1165 let Predicates = [HasBWI, HasVLX] in {
1166 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1167 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1172 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1173 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1174 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1175 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1176 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1177 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1180 let Predicates = [HasAVX512] in {
1181 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1182 (v8f32 VR256X:$src2))),
1184 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1185 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1186 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1188 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1189 (v8i32 VR256X:$src2))),
1191 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1192 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1193 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1195 //===----------------------------------------------------------------------===//
1196 // Compare Instructions
1197 //===----------------------------------------------------------------------===//
1199 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1200 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1202 PatFrag ld_frag, string asm, string asm_alt> {
1203 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1204 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc), asm,
1205 [(set VK1:$dst, (X86cmpms (VT RC:$src1),
1206 RC:$src2, i8immZExt5:$cc))],
1207 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1208 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1209 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc), asm,
1210 [(set VK1:$dst, (X86cmpms (VT RC:$src1),
1211 (ld_frag addr:$src2), i8immZExt5:$cc))], IIC_SSE_ALU_F32P_RM>,
1213 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1214 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1215 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1216 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1217 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1218 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1219 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1223 let Predicates = [HasAVX512] in {
1224 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, f32, loadf32,
1225 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1226 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1228 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, f64, loadf64,
1229 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1230 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1234 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1235 X86VectorVTInfo _> {
1236 def rr : AVX512BI<opc, MRMSrcReg,
1237 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1238 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1239 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1240 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1242 def rm : AVX512BI<opc, MRMSrcMem,
1243 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1244 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1245 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1246 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1247 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1248 def rrk : AVX512BI<opc, MRMSrcReg,
1249 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1251 "$dst {${mask}}, $src1, $src2}"),
1252 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1253 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1254 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1256 def rmk : AVX512BI<opc, MRMSrcMem,
1257 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1258 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1259 "$dst {${mask}}, $src1, $src2}"),
1260 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1261 (OpNode (_.VT _.RC:$src1),
1263 (_.LdFrag addr:$src2))))))],
1264 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1267 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1268 X86VectorVTInfo _> :
1269 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1270 let mayLoad = 1 in {
1271 def rmb : AVX512BI<opc, MRMSrcMem,
1272 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1273 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1274 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1275 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1276 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1277 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1278 def rmbk : AVX512BI<opc, MRMSrcMem,
1279 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1280 _.ScalarMemOp:$src2),
1281 !strconcat(OpcodeStr,
1282 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1283 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1284 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1285 (OpNode (_.VT _.RC:$src1),
1287 (_.ScalarLdFrag addr:$src2)))))],
1288 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1292 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1293 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1294 let Predicates = [prd] in
1295 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1298 let Predicates = [prd, HasVLX] in {
1299 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1301 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1306 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1307 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1309 let Predicates = [prd] in
1310 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1313 let Predicates = [prd, HasVLX] in {
1314 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1316 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1321 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1322 avx512vl_i8_info, HasBWI>,
1325 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1326 avx512vl_i16_info, HasBWI>,
1327 EVEX_CD8<16, CD8VF>;
1329 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1330 avx512vl_i32_info, HasAVX512>,
1331 EVEX_CD8<32, CD8VF>;
1333 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1334 avx512vl_i64_info, HasAVX512>,
1335 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1337 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1338 avx512vl_i8_info, HasBWI>,
1341 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1342 avx512vl_i16_info, HasBWI>,
1343 EVEX_CD8<16, CD8VF>;
1345 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1346 avx512vl_i32_info, HasAVX512>,
1347 EVEX_CD8<32, CD8VF>;
1349 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1350 avx512vl_i64_info, HasAVX512>,
1351 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1353 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1354 (COPY_TO_REGCLASS (VPCMPGTDZrr
1355 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1356 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1358 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1359 (COPY_TO_REGCLASS (VPCMPEQDZrr
1360 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1361 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1363 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1364 X86VectorVTInfo _> {
1365 def rri : AVX512AIi8<opc, MRMSrcReg,
1366 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1367 !strconcat("vpcmp${cc}", Suffix,
1368 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1369 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1371 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1373 def rmi : AVX512AIi8<opc, MRMSrcMem,
1374 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1375 !strconcat("vpcmp${cc}", Suffix,
1376 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1377 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1378 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1380 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1381 def rrik : AVX512AIi8<opc, MRMSrcReg,
1382 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1384 !strconcat("vpcmp${cc}", Suffix,
1385 "\t{$src2, $src1, $dst {${mask}}|",
1386 "$dst {${mask}}, $src1, $src2}"),
1387 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1388 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1390 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1392 def rmik : AVX512AIi8<opc, MRMSrcMem,
1393 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1395 !strconcat("vpcmp${cc}", Suffix,
1396 "\t{$src2, $src1, $dst {${mask}}|",
1397 "$dst {${mask}}, $src1, $src2}"),
1398 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1399 (OpNode (_.VT _.RC:$src1),
1400 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1402 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1404 // Accept explicit immediate argument form instead of comparison code.
1405 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1406 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1407 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1408 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1409 "$dst, $src1, $src2, $cc}"),
1410 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1411 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1412 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1413 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1414 "$dst, $src1, $src2, $cc}"),
1415 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1416 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1417 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1419 !strconcat("vpcmp", Suffix,
1420 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1421 "$dst {${mask}}, $src1, $src2, $cc}"),
1422 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1423 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1424 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1426 !strconcat("vpcmp", Suffix,
1427 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1428 "$dst {${mask}}, $src1, $src2, $cc}"),
1429 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1433 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1434 X86VectorVTInfo _> :
1435 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1436 let mayLoad = 1 in {
1437 def rmib : AVX512AIi8<opc, MRMSrcMem,
1438 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1440 !strconcat("vpcmp${cc}", Suffix,
1441 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1442 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1443 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1444 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1446 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1447 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1448 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1449 _.ScalarMemOp:$src2, AVXCC:$cc),
1450 !strconcat("vpcmp${cc}", Suffix,
1451 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1452 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1453 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1454 (OpNode (_.VT _.RC:$src1),
1455 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1457 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1460 // Accept explicit immediate argument form instead of comparison code.
1461 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1462 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1463 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1465 !strconcat("vpcmp", Suffix,
1466 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1467 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1468 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1469 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1470 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1471 _.ScalarMemOp:$src2, i8imm:$cc),
1472 !strconcat("vpcmp", Suffix,
1473 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1474 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1475 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1479 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1480 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1481 let Predicates = [prd] in
1482 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1484 let Predicates = [prd, HasVLX] in {
1485 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1486 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1490 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1491 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1492 let Predicates = [prd] in
1493 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1496 let Predicates = [prd, HasVLX] in {
1497 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1499 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1504 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1505 HasBWI>, EVEX_CD8<8, CD8VF>;
1506 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1507 HasBWI>, EVEX_CD8<8, CD8VF>;
1509 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1510 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1511 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1512 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1514 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1515 HasAVX512>, EVEX_CD8<32, CD8VF>;
1516 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1517 HasAVX512>, EVEX_CD8<32, CD8VF>;
1519 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1520 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1521 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1522 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1524 // avx512_cmp_packed - compare packed instructions
1525 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
1526 X86MemOperand x86memop, ValueType vt,
1527 string suffix, Domain d> {
1528 def rri : AVX512PIi8<0xC2, MRMSrcReg,
1529 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1530 !strconcat("vcmp${cc}", suffix,
1531 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1532 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2),
1533 i8immZExt5:$cc))], d>;
1534 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
1535 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1536 !strconcat("vcmp${cc}", suffix,
1537 "\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
1539 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
1540 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1541 !strconcat("vcmp${cc}", suffix,
1542 "\t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1544 (X86cmpm (vt RC:$src1), (memop addr:$src2), i8immZExt5:$cc))], d>;
1546 // Accept explicit immediate argument form instead of comparison code.
1547 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1548 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
1549 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1550 !strconcat("vcmp", suffix,
1551 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1552 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
1553 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1554 !strconcat("vcmp", suffix,
1555 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
1559 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
1560 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
1561 EVEX_CD8<32, CD8VF>;
1562 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
1563 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
1564 EVEX_CD8<64, CD8VF>;
1566 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1567 (COPY_TO_REGCLASS (VCMPPSZrri
1568 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1569 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1571 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1572 (COPY_TO_REGCLASS (VPCMPDZrri
1573 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1574 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1576 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1577 (COPY_TO_REGCLASS (VPCMPUDZrri
1578 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1579 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1582 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1583 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1585 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
1586 (I8Imm imm:$cc)), GR16)>;
1588 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1589 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1591 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
1592 (I8Imm imm:$cc)), GR8)>;
1594 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1595 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1597 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1598 (I8Imm imm:$cc)), GR16)>;
1600 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1601 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1603 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1604 (I8Imm imm:$cc)), GR8)>;
1606 // Mask register copy, including
1607 // - copy between mask registers
1608 // - load/store mask registers
1609 // - copy from GPR to mask register and vice versa
1611 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1612 string OpcodeStr, RegisterClass KRC,
1613 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
1614 let hasSideEffects = 0 in {
1615 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1618 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1619 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1620 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
1622 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1623 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1627 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1629 RegisterClass KRC, RegisterClass GRC> {
1630 let hasSideEffects = 0 in {
1631 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1632 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1633 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1634 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1638 let Predicates = [HasDQI] in
1639 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1641 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1644 let Predicates = [HasAVX512] in
1645 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1647 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1650 let Predicates = [HasBWI] in {
1651 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1652 i32mem>, VEX, PD, VEX_W;
1653 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1657 let Predicates = [HasBWI] in {
1658 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1659 i64mem>, VEX, PS, VEX_W;
1660 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1664 // GR from/to mask register
1665 let Predicates = [HasDQI] in {
1666 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1667 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1668 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1669 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1671 let Predicates = [HasAVX512] in {
1672 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1673 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1674 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1675 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1677 let Predicates = [HasBWI] in {
1678 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1679 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1681 let Predicates = [HasBWI] in {
1682 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1683 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1687 let Predicates = [HasDQI] in {
1688 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1689 (KMOVBmk addr:$dst, VK8:$src)>;
1691 let Predicates = [HasAVX512] in {
1692 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1693 (KMOVWmk addr:$dst, VK16:$src)>;
1694 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1695 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1696 def : Pat<(i1 (load addr:$src)),
1697 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1698 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1699 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1701 let Predicates = [HasBWI] in {
1702 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1703 (KMOVDmk addr:$dst, VK32:$src)>;
1705 let Predicates = [HasBWI] in {
1706 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1707 (KMOVQmk addr:$dst, VK64:$src)>;
1710 let Predicates = [HasAVX512] in {
1711 def : Pat<(i1 (trunc (i64 GR64:$src))),
1712 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1715 def : Pat<(i1 (trunc (i32 GR32:$src))),
1716 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1718 def : Pat<(i1 (trunc (i8 GR8:$src))),
1720 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1722 def : Pat<(i1 (trunc (i16 GR16:$src))),
1724 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1727 def : Pat<(i32 (zext VK1:$src)),
1728 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1729 def : Pat<(i8 (zext VK1:$src)),
1732 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1733 def : Pat<(i64 (zext VK1:$src)),
1734 (AND64ri8 (SUBREG_TO_REG (i64 0),
1735 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1736 def : Pat<(i16 (zext VK1:$src)),
1738 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1740 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1741 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1742 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1743 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1745 let Predicates = [HasBWI] in {
1746 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1747 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1748 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1749 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1753 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1754 let Predicates = [HasAVX512] in {
1755 // GR from/to 8-bit mask without native support
1756 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1758 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1760 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1762 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1765 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1766 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1767 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1768 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1770 let Predicates = [HasBWI] in {
1771 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1772 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1773 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1774 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1777 // Mask unary operation
1779 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1780 RegisterClass KRC, SDPatternOperator OpNode,
1782 let Predicates = [prd] in
1783 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1784 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1785 [(set KRC:$dst, (OpNode KRC:$src))]>;
1788 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1789 SDPatternOperator OpNode> {
1790 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1792 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1793 HasAVX512>, VEX, PS;
1794 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1795 HasBWI>, VEX, PD, VEX_W;
1796 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1797 HasBWI>, VEX, PS, VEX_W;
1800 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1802 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1803 let Predicates = [HasAVX512] in
1804 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1806 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1807 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1809 defm : avx512_mask_unop_int<"knot", "KNOT">;
1811 let Predicates = [HasDQI] in
1812 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1813 let Predicates = [HasAVX512] in
1814 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1815 let Predicates = [HasBWI] in
1816 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1817 let Predicates = [HasBWI] in
1818 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1820 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1821 let Predicates = [HasAVX512] in {
1822 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1823 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1825 def : Pat<(not VK8:$src),
1827 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1830 // Mask binary operation
1831 // - KAND, KANDN, KOR, KXNOR, KXOR
1832 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1833 RegisterClass KRC, SDPatternOperator OpNode,
1835 let Predicates = [prd] in
1836 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1837 !strconcat(OpcodeStr,
1838 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1839 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1842 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1843 SDPatternOperator OpNode> {
1844 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1845 HasDQI>, VEX_4V, VEX_L, PD;
1846 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1847 HasAVX512>, VEX_4V, VEX_L, PS;
1848 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1849 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1850 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1851 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
1854 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1855 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1857 let isCommutable = 1 in {
1858 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1859 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1860 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1861 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
1863 let isCommutable = 0 in
1864 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
1866 def : Pat<(xor VK1:$src1, VK1:$src2),
1867 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1868 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1870 def : Pat<(or VK1:$src1, VK1:$src2),
1871 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1872 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1874 def : Pat<(and VK1:$src1, VK1:$src2),
1875 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1876 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1878 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1879 let Predicates = [HasAVX512] in
1880 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1881 (i16 GR16:$src1), (i16 GR16:$src2)),
1882 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1883 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1884 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1887 defm : avx512_mask_binop_int<"kand", "KAND">;
1888 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1889 defm : avx512_mask_binop_int<"kor", "KOR">;
1890 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1891 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1893 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1894 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1895 let Predicates = [HasAVX512] in
1896 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1898 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1899 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1902 defm : avx512_binop_pat<and, KANDWrr>;
1903 defm : avx512_binop_pat<andn, KANDNWrr>;
1904 defm : avx512_binop_pat<or, KORWrr>;
1905 defm : avx512_binop_pat<xnor, KXNORWrr>;
1906 defm : avx512_binop_pat<xor, KXORWrr>;
1909 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1910 RegisterClass KRC> {
1911 let Predicates = [HasAVX512] in
1912 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1913 !strconcat(OpcodeStr,
1914 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1917 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1918 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1922 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1923 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1924 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1925 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1928 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1929 let Predicates = [HasAVX512] in
1930 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1931 (i16 GR16:$src1), (i16 GR16:$src2)),
1932 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1933 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1934 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1936 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1939 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1941 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1942 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1943 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1944 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1947 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1948 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1952 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1954 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1955 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1956 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1959 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1961 let Predicates = [HasAVX512] in
1962 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1963 !strconcat(OpcodeStr,
1964 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1965 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1968 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1970 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1974 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1975 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1977 // Mask setting all 0s or 1s
1978 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1979 let Predicates = [HasAVX512] in
1980 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1981 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1982 [(set KRC:$dst, (VT Val))]>;
1985 multiclass avx512_mask_setop_w<PatFrag Val> {
1986 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1987 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1990 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1991 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1993 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1994 let Predicates = [HasAVX512] in {
1995 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1996 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1997 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1998 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1999 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
2001 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2002 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2004 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2005 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2007 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2008 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2010 let Predicates = [HasVLX] in {
2011 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2012 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2013 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2014 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2015 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2016 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2017 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2018 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2021 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2022 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
2024 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2025 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
2026 //===----------------------------------------------------------------------===//
2027 // AVX-512 - Aligned and unaligned load and store
2030 multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
2031 RegisterClass KRC, RegisterClass RC,
2032 ValueType vt, ValueType zvt, X86MemOperand memop,
2033 Domain d, bit IsReMaterializable = 1> {
2034 let hasSideEffects = 0 in {
2035 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2036 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2038 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
2039 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2040 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
2042 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2043 SchedRW = [WriteLoad] in
2044 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
2045 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2046 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
2049 let AddedComplexity = 20 in {
2050 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
2051 let hasSideEffects = 0 in
2052 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
2053 (ins RC:$src0, KRC:$mask, RC:$src1),
2054 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2055 "${dst} {${mask}}, $src1}"),
2056 [(set RC:$dst, (vt (vselect KRC:$mask,
2060 let mayLoad = 1, SchedRW = [WriteLoad] in
2061 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2062 (ins RC:$src0, KRC:$mask, memop:$src1),
2063 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2064 "${dst} {${mask}}, $src1}"),
2067 (vt (bitconvert (ld_frag addr:$src1))),
2071 let mayLoad = 1, SchedRW = [WriteLoad] in
2072 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
2073 (ins KRC:$mask, memop:$src),
2074 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2075 "${dst} {${mask}} {z}, $src}"),
2078 (vt (bitconvert (ld_frag addr:$src))),
2079 (vt (bitconvert (zvt immAllZerosV))))))],
2084 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
2085 string elty, string elsz, string vsz512,
2086 string vsz256, string vsz128, Domain d,
2087 Predicate prd, bit IsReMaterializable = 1> {
2088 let Predicates = [prd] in
2089 defm Z : avx512_load<opc, OpcodeStr,
2090 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
2091 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2092 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
2093 !cast<X86MemOperand>(elty##"512mem"), d,
2094 IsReMaterializable>, EVEX_V512;
2096 let Predicates = [prd, HasVLX] in {
2097 defm Z256 : avx512_load<opc, OpcodeStr,
2098 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2099 "v"##vsz256##elty##elsz, "v4i64")),
2100 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2101 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
2102 !cast<X86MemOperand>(elty##"256mem"), d,
2103 IsReMaterializable>, EVEX_V256;
2105 defm Z128 : avx512_load<opc, OpcodeStr,
2106 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
2107 "v"##vsz128##elty##elsz, "v2i64")),
2108 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2109 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
2110 !cast<X86MemOperand>(elty##"128mem"), d,
2111 IsReMaterializable>, EVEX_V128;
2116 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2117 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
2118 X86MemOperand memop, Domain d> {
2119 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2120 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
2121 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
2123 let Constraints = "$src1 = $dst" in
2124 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2125 (ins RC:$src1, KRC:$mask, RC:$src2),
2126 !strconcat(OpcodeStr,
2127 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
2129 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
2130 (ins KRC:$mask, RC:$src),
2131 !strconcat(OpcodeStr,
2132 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
2133 [], d>, EVEX, EVEX_KZ;
2135 let mayStore = 1 in {
2136 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2137 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2138 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
2139 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2140 (ins memop:$dst, KRC:$mask, RC:$src),
2141 !strconcat(OpcodeStr,
2142 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
2143 [], d>, EVEX, EVEX_K;
2148 multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2149 string st_suff_512, string st_suff_256,
2150 string st_suff_128, string elty, string elsz,
2151 string vsz512, string vsz256, string vsz128,
2152 Domain d, Predicate prd> {
2153 let Predicates = [prd] in
2154 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2155 !cast<ValueType>("v"##vsz512##elty##elsz),
2156 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2157 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2159 let Predicates = [prd, HasVLX] in {
2160 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2161 !cast<ValueType>("v"##vsz256##elty##elsz),
2162 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2163 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2165 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2166 !cast<ValueType>("v"##vsz128##elty##elsz),
2167 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2168 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2172 defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2173 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2174 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2175 "512", "256", "", "f", "32", "16", "8", "4",
2176 SSEPackedSingle, HasAVX512>,
2177 PS, EVEX_CD8<32, CD8VF>;
2179 defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2180 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2181 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2182 "512", "256", "", "f", "64", "8", "4", "2",
2183 SSEPackedDouble, HasAVX512>,
2184 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2186 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2187 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2188 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2189 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2190 PS, EVEX_CD8<32, CD8VF>;
2192 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2193 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2194 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2195 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2196 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2198 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2199 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2200 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2202 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2203 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2204 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2206 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2208 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2210 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2212 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2215 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2216 (VMOVUPSZmrk addr:$ptr,
2217 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2218 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2220 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2221 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2222 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2224 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src)),
2225 (VMOVUPSZmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2227 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src)),
2228 (VMOVUPDZmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2230 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2231 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2233 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask,
2234 (bc_v16f32 (v16i32 immAllZerosV)))),
2235 (VMOVUPSZrmkz VK16WM:$mask, addr:$ptr)>;
2237 def: Pat<(v16f32 (masked_load addr:$ptr, VK16WM:$mask, (v16f32 VR512:$src0))),
2238 (VMOVUPSZrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2240 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2241 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2243 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask,
2244 (bc_v8f64 (v16i32 immAllZerosV)))),
2245 (VMOVUPDZrmkz VK8WM:$mask, addr:$ptr)>;
2247 def: Pat<(v8f64 (masked_load addr:$ptr, VK8WM:$mask, (v8f64 VR512:$src0))),
2248 (VMOVUPDZrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2250 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2251 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2252 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2253 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2255 defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2256 "16", "8", "4", SSEPackedInt, HasAVX512>,
2257 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2258 "512", "256", "", "i", "32", "16", "8", "4",
2259 SSEPackedInt, HasAVX512>,
2260 PD, EVEX_CD8<32, CD8VF>;
2262 defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2263 "8", "4", "2", SSEPackedInt, HasAVX512>,
2264 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2265 "512", "256", "", "i", "64", "8", "4", "2",
2266 SSEPackedInt, HasAVX512>,
2267 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2269 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2270 "64", "32", "16", SSEPackedInt, HasBWI>,
2271 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2272 "i", "8", "64", "32", "16", SSEPackedInt,
2273 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2275 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2276 "32", "16", "8", SSEPackedInt, HasBWI>,
2277 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2278 "i", "16", "32", "16", "8", SSEPackedInt,
2279 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2281 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2282 "16", "8", "4", SSEPackedInt, HasAVX512>,
2283 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2284 "i", "32", "16", "8", "4", SSEPackedInt,
2285 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2287 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2288 "8", "4", "2", SSEPackedInt, HasAVX512>,
2289 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2290 "i", "64", "8", "4", "2", SSEPackedInt,
2291 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2293 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2294 (v16i32 immAllZerosV), GR16:$mask)),
2295 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2297 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2298 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2299 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2301 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2303 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2305 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2307 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2310 let AddedComplexity = 20 in {
2311 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2312 (bc_v8i64 (v16i32 immAllZerosV)))),
2313 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2315 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2316 (v8i64 VR512:$src))),
2317 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2320 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2321 (v16i32 immAllZerosV))),
2322 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2324 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2325 (v16i32 VR512:$src))),
2326 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2329 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 immAllZerosV))),
2330 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2332 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, undef)),
2333 (VMOVDQU32Zrmkz VK16WM:$mask, addr:$ptr)>;
2335 def: Pat<(v16i32 (masked_load addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src0))),
2336 (VMOVDQU32Zrmk VR512:$src0, VK16WM:$mask, addr:$ptr)>;
2338 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask,
2339 (bc_v8i64 (v16i32 immAllZerosV)))),
2340 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2342 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2343 (VMOVDQU64Zrmkz VK8WM:$mask, addr:$ptr)>;
2345 def: Pat<(v8i64 (masked_load addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src0))),
2346 (VMOVDQU64Zrmk VR512:$src0, VK8WM:$mask, addr:$ptr)>;
2348 def: Pat<(masked_store addr:$ptr, VK16WM:$mask, (v16i32 VR512:$src)),
2349 (VMOVDQU32Zmrk addr:$ptr, VK16WM:$mask, VR512:$src)>;
2351 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i64 VR512:$src)),
2352 (VMOVDQU64Zmrk addr:$ptr, VK8WM:$mask, VR512:$src)>;
2355 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2356 (VMOVDQU32Z256mrk addr:$ptr, VK8WM:$mask, VR256:$src)>;
2359 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2360 (VMOVDQU32Zmrk addr:$ptr,
2361 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2362 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2364 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2365 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2366 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2369 // Move Int Doubleword to Packed Double Int
2371 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2372 "vmovd\t{$src, $dst|$dst, $src}",
2374 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2376 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2377 "vmovd\t{$src, $dst|$dst, $src}",
2379 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2380 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2381 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2382 "vmovq\t{$src, $dst|$dst, $src}",
2384 (v2i64 (scalar_to_vector GR64:$src)))],
2385 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2386 let isCodeGenOnly = 1 in {
2387 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2388 "vmovq\t{$src, $dst|$dst, $src}",
2389 [(set FR64:$dst, (bitconvert GR64:$src))],
2390 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2391 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2392 "vmovq\t{$src, $dst|$dst, $src}",
2393 [(set GR64:$dst, (bitconvert FR64:$src))],
2394 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2396 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2397 "vmovq\t{$src, $dst|$dst, $src}",
2398 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2399 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2400 EVEX_CD8<64, CD8VT1>;
2402 // Move Int Doubleword to Single Scalar
2404 let isCodeGenOnly = 1 in {
2405 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2406 "vmovd\t{$src, $dst|$dst, $src}",
2407 [(set FR32X:$dst, (bitconvert GR32:$src))],
2408 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2410 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2411 "vmovd\t{$src, $dst|$dst, $src}",
2412 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2413 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2416 // Move doubleword from xmm register to r/m32
2418 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2419 "vmovd\t{$src, $dst|$dst, $src}",
2420 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2421 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2423 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2424 (ins i32mem:$dst, VR128X:$src),
2425 "vmovd\t{$src, $dst|$dst, $src}",
2426 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2427 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2428 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2430 // Move quadword from xmm1 register to r/m64
2432 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2433 "vmovq\t{$src, $dst|$dst, $src}",
2434 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2436 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2437 Requires<[HasAVX512, In64BitMode]>;
2439 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2440 (ins i64mem:$dst, VR128X:$src),
2441 "vmovq\t{$src, $dst|$dst, $src}",
2442 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2443 addr:$dst)], IIC_SSE_MOVDQ>,
2444 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2445 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2447 // Move Scalar Single to Double Int
2449 let isCodeGenOnly = 1 in {
2450 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2452 "vmovd\t{$src, $dst|$dst, $src}",
2453 [(set GR32:$dst, (bitconvert FR32X:$src))],
2454 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2455 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2456 (ins i32mem:$dst, FR32X:$src),
2457 "vmovd\t{$src, $dst|$dst, $src}",
2458 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2459 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2462 // Move Quadword Int to Packed Quadword Int
2464 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2466 "vmovq\t{$src, $dst|$dst, $src}",
2468 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2469 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2471 //===----------------------------------------------------------------------===//
2472 // AVX-512 MOVSS, MOVSD
2473 //===----------------------------------------------------------------------===//
2475 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2476 SDNode OpNode, ValueType vt,
2477 X86MemOperand x86memop, PatFrag mem_pat> {
2478 let hasSideEffects = 0 in {
2479 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2480 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2481 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2482 (scalar_to_vector RC:$src2))))],
2483 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2484 let Constraints = "$src1 = $dst" in
2485 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2486 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2488 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2489 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2490 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2491 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2492 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2494 let mayStore = 1 in {
2495 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2496 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2497 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2499 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2500 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2501 [], IIC_SSE_MOV_S_MR>,
2502 EVEX, VEX_LIG, EVEX_K;
2504 } //hasSideEffects = 0
2507 let ExeDomain = SSEPackedSingle in
2508 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2509 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2511 let ExeDomain = SSEPackedDouble in
2512 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2513 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2515 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2516 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2517 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2519 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2520 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2521 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2523 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2524 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2525 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2527 // For the disassembler
2528 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2529 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2530 (ins VR128X:$src1, FR32X:$src2),
2531 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2533 XS, EVEX_4V, VEX_LIG;
2534 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2535 (ins VR128X:$src1, FR64X:$src2),
2536 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2538 XD, EVEX_4V, VEX_LIG, VEX_W;
2541 let Predicates = [HasAVX512] in {
2542 let AddedComplexity = 15 in {
2543 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2544 // MOVS{S,D} to the lower bits.
2545 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2546 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2547 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2548 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2549 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2550 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2551 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2552 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2554 // Move low f32 and clear high bits.
2555 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2556 (SUBREG_TO_REG (i32 0),
2557 (VMOVSSZrr (v4f32 (V_SET0)),
2558 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2559 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2560 (SUBREG_TO_REG (i32 0),
2561 (VMOVSSZrr (v4i32 (V_SET0)),
2562 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2565 let AddedComplexity = 20 in {
2566 // MOVSSrm zeros the high parts of the register; represent this
2567 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2568 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2569 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2570 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2571 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2572 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2573 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2575 // MOVSDrm zeros the high parts of the register; represent this
2576 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2577 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2578 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2579 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2580 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2581 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2582 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2583 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2584 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2585 def : Pat<(v2f64 (X86vzload addr:$src)),
2586 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2588 // Represent the same patterns above but in the form they appear for
2590 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2591 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2592 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2593 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2594 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2595 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2596 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2597 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2598 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2600 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2601 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2602 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2603 FR32X:$src)), sub_xmm)>;
2604 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2605 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2606 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2607 FR64X:$src)), sub_xmm)>;
2608 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2609 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2610 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2612 // Move low f64 and clear high bits.
2613 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2614 (SUBREG_TO_REG (i32 0),
2615 (VMOVSDZrr (v2f64 (V_SET0)),
2616 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2618 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2619 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2620 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2622 // Extract and store.
2623 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2625 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2626 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2628 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2630 // Shuffle with VMOVSS
2631 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2632 (VMOVSSZrr (v4i32 VR128X:$src1),
2633 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2634 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2635 (VMOVSSZrr (v4f32 VR128X:$src1),
2636 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2639 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2640 (SUBREG_TO_REG (i32 0),
2641 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2642 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2644 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2645 (SUBREG_TO_REG (i32 0),
2646 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2647 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2650 // Shuffle with VMOVSD
2651 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2652 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2653 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2654 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2655 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2656 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2657 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2658 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2661 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2662 (SUBREG_TO_REG (i32 0),
2663 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2664 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2666 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2667 (SUBREG_TO_REG (i32 0),
2668 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2669 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2672 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2673 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2674 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2675 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2676 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2677 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2678 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2679 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2682 let AddedComplexity = 15 in
2683 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2685 "vmovq\t{$src, $dst|$dst, $src}",
2686 [(set VR128X:$dst, (v2i64 (X86vzmovl
2687 (v2i64 VR128X:$src))))],
2688 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2690 let AddedComplexity = 20 in
2691 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2693 "vmovq\t{$src, $dst|$dst, $src}",
2694 [(set VR128X:$dst, (v2i64 (X86vzmovl
2695 (loadv2i64 addr:$src))))],
2696 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2697 EVEX_CD8<8, CD8VT8>;
2699 let Predicates = [HasAVX512] in {
2700 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2701 let AddedComplexity = 20 in {
2702 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2703 (VMOVDI2PDIZrm addr:$src)>;
2704 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2705 (VMOV64toPQIZrr GR64:$src)>;
2706 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2707 (VMOVDI2PDIZrr GR32:$src)>;
2709 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2710 (VMOVDI2PDIZrm addr:$src)>;
2711 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2712 (VMOVDI2PDIZrm addr:$src)>;
2713 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2714 (VMOVZPQILo2PQIZrm addr:$src)>;
2715 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2716 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2717 def : Pat<(v2i64 (X86vzload addr:$src)),
2718 (VMOVZPQILo2PQIZrm addr:$src)>;
2721 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2722 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2723 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2724 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2725 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2726 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2727 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2730 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2731 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2733 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2734 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2736 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2737 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2739 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2740 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2742 //===----------------------------------------------------------------------===//
2743 // AVX-512 - Non-temporals
2744 //===----------------------------------------------------------------------===//
2745 let SchedRW = [WriteLoad] in {
2746 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2747 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2748 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2749 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2750 EVEX_CD8<64, CD8VF>;
2752 let Predicates = [HasAVX512, HasVLX] in {
2753 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2755 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2756 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2757 EVEX_CD8<64, CD8VF>;
2759 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2761 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2762 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2763 EVEX_CD8<64, CD8VF>;
2767 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2768 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2769 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2770 let SchedRW = [WriteStore], mayStore = 1,
2771 AddedComplexity = 400 in
2772 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2773 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2774 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2777 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2778 string elty, string elsz, string vsz512,
2779 string vsz256, string vsz128, Domain d,
2780 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2781 let Predicates = [prd] in
2782 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2783 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2784 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2787 let Predicates = [prd, HasVLX] in {
2788 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2789 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2790 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2793 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2794 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2795 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2800 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2801 "i", "64", "8", "4", "2", SSEPackedInt,
2802 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2804 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2805 "f", "64", "8", "4", "2", SSEPackedDouble,
2806 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2808 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2809 "f", "32", "16", "8", "4", SSEPackedSingle,
2810 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2812 //===----------------------------------------------------------------------===//
2813 // AVX-512 - Integer arithmetic
2815 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2816 X86VectorVTInfo _, OpndItins itins,
2817 bit IsCommutable = 0> {
2818 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2819 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2820 "$src2, $src1", "$src1, $src2",
2821 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2822 "", itins.rr, IsCommutable>,
2823 AVX512BIBase, EVEX_4V;
2826 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2827 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2828 "$src2, $src1", "$src1, $src2",
2829 (_.VT (OpNode _.RC:$src1,
2830 (bitconvert (_.LdFrag addr:$src2)))),
2832 AVX512BIBase, EVEX_4V;
2835 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2836 X86VectorVTInfo _, OpndItins itins,
2837 bit IsCommutable = 0> :
2838 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2840 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2841 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2842 "${src2}"##_.BroadcastStr##", $src1",
2843 "$src1, ${src2}"##_.BroadcastStr,
2844 (_.VT (OpNode _.RC:$src1,
2846 (_.ScalarLdFrag addr:$src2)))),
2848 AVX512BIBase, EVEX_4V, EVEX_B;
2851 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2852 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2853 Predicate prd, bit IsCommutable = 0> {
2854 let Predicates = [prd] in
2855 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2856 IsCommutable>, EVEX_V512;
2858 let Predicates = [prd, HasVLX] in {
2859 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2860 IsCommutable>, EVEX_V256;
2861 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2862 IsCommutable>, EVEX_V128;
2866 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2867 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2868 Predicate prd, bit IsCommutable = 0> {
2869 let Predicates = [prd] in
2870 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2871 IsCommutable>, EVEX_V512;
2873 let Predicates = [prd, HasVLX] in {
2874 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2875 IsCommutable>, EVEX_V256;
2876 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2877 IsCommutable>, EVEX_V128;
2881 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2882 OpndItins itins, Predicate prd,
2883 bit IsCommutable = 0> {
2884 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2885 itins, prd, IsCommutable>,
2886 VEX_W, EVEX_CD8<64, CD8VF>;
2889 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2890 OpndItins itins, Predicate prd,
2891 bit IsCommutable = 0> {
2892 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2893 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2896 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2897 OpndItins itins, Predicate prd,
2898 bit IsCommutable = 0> {
2899 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2900 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2903 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2904 OpndItins itins, Predicate prd,
2905 bit IsCommutable = 0> {
2906 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2907 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2910 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2911 SDNode OpNode, OpndItins itins, Predicate prd,
2912 bit IsCommutable = 0> {
2913 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2916 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2920 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2921 SDNode OpNode, OpndItins itins, Predicate prd,
2922 bit IsCommutable = 0> {
2923 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2926 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2930 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2931 bits<8> opc_d, bits<8> opc_q,
2932 string OpcodeStr, SDNode OpNode,
2933 OpndItins itins, bit IsCommutable = 0> {
2934 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2935 itins, HasAVX512, IsCommutable>,
2936 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2937 itins, HasBWI, IsCommutable>;
2940 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2941 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2942 PatFrag memop_frag, X86MemOperand x86memop,
2943 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2944 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2945 let isCommutable = IsCommutable in
2947 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2948 (ins RC:$src1, RC:$src2),
2949 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2951 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2952 (ins KRC:$mask, RC:$src1, RC:$src2),
2953 !strconcat(OpcodeStr,
2954 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2955 [], itins.rr>, EVEX_4V, EVEX_K;
2956 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2957 (ins KRC:$mask, RC:$src1, RC:$src2),
2958 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}} {z}" ,
2959 "|$dst {${mask}} {z}, $src1, $src2}"),
2960 [], itins.rr>, EVEX_4V, EVEX_KZ;
2962 let mayLoad = 1 in {
2963 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2964 (ins RC:$src1, x86memop:$src2),
2965 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2967 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2968 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2969 !strconcat(OpcodeStr,
2970 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2971 [], itins.rm>, EVEX_4V, EVEX_K;
2972 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2973 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2974 !strconcat(OpcodeStr,
2975 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2976 [], itins.rm>, EVEX_4V, EVEX_KZ;
2977 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2978 (ins RC:$src1, x86scalar_mop:$src2),
2979 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2980 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2981 [], itins.rm>, EVEX_4V, EVEX_B;
2982 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2983 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2984 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2985 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2987 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2988 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2989 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2990 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2991 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2993 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2997 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2998 SSE_INTALU_ITINS_P, 1>;
2999 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3000 SSE_INTALU_ITINS_P, 0>;
3001 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3002 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3003 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3004 SSE_INTALU_ITINS_P, HasBWI, 1>;
3005 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3006 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3008 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
3009 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3010 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
3011 EVEX_CD8<64, CD8VF>, VEX_W;
3013 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
3014 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3015 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3017 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
3018 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3020 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
3021 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3022 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
3023 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
3024 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3025 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
3027 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3028 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3029 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3030 SSE_INTALU_ITINS_P, HasBWI, 1>;
3031 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3032 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3034 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3035 SSE_INTALU_ITINS_P, HasBWI, 1>;
3036 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3037 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3038 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3039 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3041 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3042 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3043 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3044 SSE_INTALU_ITINS_P, HasBWI, 1>;
3045 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3046 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3048 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3049 SSE_INTALU_ITINS_P, HasBWI, 1>;
3050 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3051 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3052 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3053 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3055 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
3056 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3057 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
3058 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
3059 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3060 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
3061 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
3062 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3063 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
3064 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
3065 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3066 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
3067 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
3068 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3069 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
3070 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
3071 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
3072 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
3073 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
3074 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3075 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
3076 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
3077 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3078 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
3079 //===----------------------------------------------------------------------===//
3080 // AVX-512 - Unpack Instructions
3081 //===----------------------------------------------------------------------===//
3083 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3084 PatFrag mem_frag, RegisterClass RC,
3085 X86MemOperand x86memop, string asm,
3087 def rr : AVX512PI<opc, MRMSrcReg,
3088 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3090 (vt (OpNode RC:$src1, RC:$src2)))],
3092 def rm : AVX512PI<opc, MRMSrcMem,
3093 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3095 (vt (OpNode RC:$src1,
3096 (bitconvert (mem_frag addr:$src2)))))],
3100 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
3101 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3102 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3103 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
3104 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3105 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3106 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
3107 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3108 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3109 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
3110 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3111 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3113 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3114 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3115 X86MemOperand x86memop> {
3116 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3117 (ins RC:$src1, RC:$src2),
3118 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3119 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3120 IIC_SSE_UNPCK>, EVEX_4V;
3121 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3122 (ins RC:$src1, x86memop:$src2),
3123 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3124 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3125 (bitconvert (memop_frag addr:$src2)))))],
3126 IIC_SSE_UNPCK>, EVEX_4V;
3128 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3129 VR512, memopv16i32, i512mem>, EVEX_V512,
3130 EVEX_CD8<32, CD8VF>;
3131 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3132 VR512, memopv8i64, i512mem>, EVEX_V512,
3133 VEX_W, EVEX_CD8<64, CD8VF>;
3134 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3135 VR512, memopv16i32, i512mem>, EVEX_V512,
3136 EVEX_CD8<32, CD8VF>;
3137 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3138 VR512, memopv8i64, i512mem>, EVEX_V512,
3139 VEX_W, EVEX_CD8<64, CD8VF>;
3140 //===----------------------------------------------------------------------===//
3144 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
3145 SDNode OpNode, PatFrag mem_frag,
3146 X86MemOperand x86memop, ValueType OpVT> {
3147 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
3148 (ins RC:$src1, i8imm:$src2),
3149 !strconcat(OpcodeStr,
3150 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3152 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
3154 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
3155 (ins x86memop:$src1, i8imm:$src2),
3156 !strconcat(OpcodeStr,
3157 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3159 (OpVT (OpNode (mem_frag addr:$src1),
3160 (i8 imm:$src2))))]>, EVEX;
3163 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
3164 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
3166 //===----------------------------------------------------------------------===//
3167 // AVX-512 Logical Instructions
3168 //===----------------------------------------------------------------------===//
3170 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3171 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3172 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3173 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3174 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3175 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3176 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3177 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3179 //===----------------------------------------------------------------------===//
3180 // AVX-512 FP arithmetic
3181 //===----------------------------------------------------------------------===//
3183 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3185 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
3186 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
3187 EVEX_CD8<32, CD8VT1>;
3188 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
3189 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
3190 EVEX_CD8<64, CD8VT1>;
3193 let isCommutable = 1 in {
3194 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
3195 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
3196 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
3197 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
3199 let isCommutable = 0 in {
3200 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
3201 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
3204 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3205 X86VectorVTInfo _, bit IsCommutable> {
3206 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3207 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3208 "$src2, $src1", "$src1, $src2",
3209 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3210 let mayLoad = 1 in {
3211 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3212 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3213 "$src2, $src1", "$src1, $src2",
3214 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3215 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3216 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3217 "${src2}"##_.BroadcastStr##", $src1",
3218 "$src1, ${src2}"##_.BroadcastStr,
3219 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3220 (_.ScalarLdFrag addr:$src2))))>,
3225 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3226 bit IsCommutable = 0> {
3227 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3228 IsCommutable>, EVEX_V512, PS,
3229 EVEX_CD8<32, CD8VF>;
3230 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3231 IsCommutable>, EVEX_V512, PD, VEX_W,
3232 EVEX_CD8<64, CD8VF>;
3234 // Define only if AVX512VL feature is present.
3235 let Predicates = [HasVLX] in {
3236 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3237 IsCommutable>, EVEX_V128, PS,
3238 EVEX_CD8<32, CD8VF>;
3239 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3240 IsCommutable>, EVEX_V256, PS,
3241 EVEX_CD8<32, CD8VF>;
3242 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3243 IsCommutable>, EVEX_V128, PD, VEX_W,
3244 EVEX_CD8<64, CD8VF>;
3245 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3246 IsCommutable>, EVEX_V256, PD, VEX_W,
3247 EVEX_CD8<64, CD8VF>;
3251 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3252 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3253 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3254 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3255 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3256 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
3258 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3259 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3260 (i16 -1), FROUND_CURRENT)),
3261 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3263 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3264 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3265 (i8 -1), FROUND_CURRENT)),
3266 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3268 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3269 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3270 (i16 -1), FROUND_CURRENT)),
3271 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3273 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3274 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3275 (i8 -1), FROUND_CURRENT)),
3276 (VMINPDZrr VR512:$src1, VR512:$src2)>;
3277 //===----------------------------------------------------------------------===//
3278 // AVX-512 VPTESTM instructions
3279 //===----------------------------------------------------------------------===//
3281 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3282 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3283 SDNode OpNode, ValueType vt> {
3284 def rr : AVX512PI<opc, MRMSrcReg,
3285 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
3286 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3287 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3288 SSEPackedInt>, EVEX_4V;
3289 def rm : AVX512PI<opc, MRMSrcMem,
3290 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
3291 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3292 [(set KRC:$dst, (OpNode (vt RC:$src1),
3293 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
3296 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
3297 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
3298 EVEX_CD8<32, CD8VF>;
3299 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
3300 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
3301 EVEX_CD8<64, CD8VF>;
3303 let Predicates = [HasCDI] in {
3304 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3305 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3306 EVEX_CD8<32, CD8VF>;
3307 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
3308 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
3309 EVEX_CD8<64, CD8VF>;
3312 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3313 (v16i32 VR512:$src2), (i16 -1))),
3314 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3316 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3317 (v8i64 VR512:$src2), (i8 -1))),
3318 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3320 //===----------------------------------------------------------------------===//
3321 // AVX-512 Shift instructions
3322 //===----------------------------------------------------------------------===//
3323 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3324 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3325 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3326 (ins _.RC:$src1, i8imm:$src2), OpcodeStr,
3327 "$src2, $src1", "$src1, $src2",
3328 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3329 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIi8Base, EVEX_4V;
3330 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3331 (ins _.MemOp:$src1, i8imm:$src2), OpcodeStr,
3332 "$src2, $src1", "$src1, $src2",
3333 (_.VT (OpNode (_.MemOpFrag addr:$src1), (i8 imm:$src2))),
3334 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIi8Base, EVEX_4V;
3337 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3338 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3339 // src2 is always 128-bit
3340 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3341 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3342 "$src2, $src1", "$src1, $src2",
3343 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3344 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3345 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3346 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3347 "$src2, $src1", "$src1, $src2",
3348 (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),
3349 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;
3352 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3353 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3354 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;
3357 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,
3359 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3360 v16i32_info>, EVEX_CD8<32, CD8VQ>;
3361 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3362 v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3365 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3367 EVEX_V512, EVEX_CD8<32, CD8VF>;
3368 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3369 v8i64_info>, EVEX_V512,
3370 EVEX_CD8<64, CD8VF>, VEX_W;
3372 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3373 v16i32_info>, EVEX_V512,
3374 EVEX_CD8<32, CD8VF>;
3375 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3376 v8i64_info>, EVEX_V512,
3377 EVEX_CD8<64, CD8VF>, VEX_W;
3379 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3381 EVEX_V512, EVEX_CD8<32, CD8VF>;
3382 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3383 v8i64_info>, EVEX_V512,
3384 EVEX_CD8<64, CD8VF>, VEX_W;
3386 defm VPSLL : avx512_shift_types<0xF2, 0xF3, "vpsll", X86vshl>;
3387 defm VPSRA : avx512_shift_types<0xE2, 0xE2, "vpsra", X86vsra>;
3388 defm VPSRL : avx512_shift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;
3390 //===-------------------------------------------------------------------===//
3391 // Variable Bit Shifts
3392 //===-------------------------------------------------------------------===//
3393 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3394 X86VectorVTInfo _> {
3395 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3396 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3397 "$src2, $src1", "$src1, $src2",
3398 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3399 " ", SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3400 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3401 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3402 "$src2, $src1", "$src1, $src2",
3403 (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2))),
3404 " ", SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V;
3407 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3408 AVX512VLVectorVTInfo _> {
3409 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3412 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3414 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3415 avx512vl_i32_info>, EVEX_CD8<32, CD8VQ>;
3416 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3417 avx512vl_i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;
3420 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>;
3421 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>;
3422 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>;
3424 //===----------------------------------------------------------------------===//
3425 // AVX-512 - MOVDDUP
3426 //===----------------------------------------------------------------------===//
3428 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3429 X86MemOperand x86memop, PatFrag memop_frag> {
3430 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3431 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3432 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3433 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3434 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3436 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3439 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3440 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3441 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3442 (VMOVDDUPZrm addr:$src)>;
3444 //===---------------------------------------------------------------------===//
3445 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3446 //===---------------------------------------------------------------------===//
3447 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3448 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3449 X86MemOperand x86memop> {
3450 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3451 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3452 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3454 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3455 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3456 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3459 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3460 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3461 EVEX_CD8<32, CD8VF>;
3462 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3463 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3464 EVEX_CD8<32, CD8VF>;
3466 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3467 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3468 (VMOVSHDUPZrm addr:$src)>;
3469 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3470 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3471 (VMOVSLDUPZrm addr:$src)>;
3473 //===----------------------------------------------------------------------===//
3474 // Move Low to High and High to Low packed FP Instructions
3475 //===----------------------------------------------------------------------===//
3476 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3477 (ins VR128X:$src1, VR128X:$src2),
3478 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3479 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3480 IIC_SSE_MOV_LH>, EVEX_4V;
3481 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3482 (ins VR128X:$src1, VR128X:$src2),
3483 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3484 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3485 IIC_SSE_MOV_LH>, EVEX_4V;
3487 let Predicates = [HasAVX512] in {
3489 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3490 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3491 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3492 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3495 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3496 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3499 //===----------------------------------------------------------------------===//
3500 // FMA - Fused Multiply Operations
3503 let Constraints = "$src1 = $dst" in {
3504 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3505 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3506 SDPatternOperator OpNode = null_frag> {
3507 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3508 (ins _.RC:$src2, _.RC:$src3),
3509 OpcodeStr, "$src3, $src2", "$src2, $src3",
3510 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3514 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3515 (ins _.RC:$src2, _.MemOp:$src3),
3516 OpcodeStr, "$src3, $src2", "$src2, $src3",
3517 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3520 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3521 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3522 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ),
3523 (OpNode _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3524 AVX512FMA3Base, EVEX_B;
3526 } // Constraints = "$src1 = $dst"
3528 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3529 string OpcodeStr, X86VectorVTInfo VTI,
3530 SDPatternOperator OpNode> {
3531 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3532 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3534 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3535 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
3538 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
3540 SDPatternOperator OpNode> {
3541 let ExeDomain = SSEPackedSingle in {
3542 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3543 v16f32_info, OpNode>, EVEX_V512;
3544 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3545 v8f32x_info, OpNode>, EVEX_V256;
3546 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3547 v4f32x_info, OpNode>, EVEX_V128;
3549 let ExeDomain = SSEPackedDouble in {
3550 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3551 v8f64_info, OpNode>, EVEX_V512, VEX_W;
3552 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3553 v4f64x_info, OpNode>, EVEX_V256, VEX_W;
3554 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
3555 v2f64x_info, OpNode>, EVEX_V128, VEX_W;
3559 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd>;
3560 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub>;
3561 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub>;
3562 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd>;
3563 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd>;
3564 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub>;
3566 let Constraints = "$src1 = $dst" in {
3567 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3568 X86VectorVTInfo _> {
3570 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3571 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
3572 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
3573 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3575 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3576 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3577 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
3578 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3580 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3581 (_.ScalarLdFrag addr:$src2))),
3582 _.RC:$src3))]>, EVEX_B;
3584 } // Constraints = "$src1 = $dst"
3587 multiclass avx512_fma3p_m132_f<bits<8> opc,
3591 let ExeDomain = SSEPackedSingle in {
3592 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
3593 OpNode,v16f32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3594 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3595 OpNode, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>;
3596 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
3597 OpNode, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>;
3599 let ExeDomain = SSEPackedDouble in {
3600 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
3601 OpNode, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VF>;
3602 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3603 OpNode, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<32, CD8VF>;
3604 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
3605 OpNode, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<32, CD8VF>;
3609 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
3610 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
3611 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
3612 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
3613 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
3614 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
3618 let Constraints = "$src1 = $dst" in {
3619 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3620 RegisterClass RC, ValueType OpVT,
3621 X86MemOperand x86memop, Operand memop,
3623 let isCommutable = 1 in
3624 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3625 (ins RC:$src1, RC:$src2, RC:$src3),
3626 !strconcat(OpcodeStr,
3627 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3629 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3631 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3632 (ins RC:$src1, RC:$src2, f128mem:$src3),
3633 !strconcat(OpcodeStr,
3634 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3636 (OpVT (OpNode RC:$src2, RC:$src1,
3637 (mem_frag addr:$src3))))]>;
3640 } // Constraints = "$src1 = $dst"
3642 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
3643 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3644 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
3645 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3646 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
3647 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3648 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
3649 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3650 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
3651 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3652 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
3653 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3654 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
3655 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
3656 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
3657 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3659 //===----------------------------------------------------------------------===//
3660 // AVX-512 Scalar convert from sign integer to float/double
3661 //===----------------------------------------------------------------------===//
3663 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3664 X86MemOperand x86memop, string asm> {
3665 let hasSideEffects = 0 in {
3666 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
3667 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3670 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3671 (ins DstRC:$src1, x86memop:$src),
3672 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
3674 } // hasSideEffects = 0
3676 let Predicates = [HasAVX512] in {
3677 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
3678 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3679 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
3680 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3681 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
3682 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3683 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
3684 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3686 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3687 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3688 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
3689 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3690 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3691 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3692 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
3693 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3695 def : Pat<(f32 (sint_to_fp GR32:$src)),
3696 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3697 def : Pat<(f32 (sint_to_fp GR64:$src)),
3698 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3699 def : Pat<(f64 (sint_to_fp GR32:$src)),
3700 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3701 def : Pat<(f64 (sint_to_fp GR64:$src)),
3702 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3704 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
3705 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3706 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
3707 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3708 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
3709 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3710 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
3711 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3713 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3714 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3715 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3716 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3717 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3718 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3719 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3720 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3722 def : Pat<(f32 (uint_to_fp GR32:$src)),
3723 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3724 def : Pat<(f32 (uint_to_fp GR64:$src)),
3725 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3726 def : Pat<(f64 (uint_to_fp GR32:$src)),
3727 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3728 def : Pat<(f64 (uint_to_fp GR64:$src)),
3729 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3732 //===----------------------------------------------------------------------===//
3733 // AVX-512 Scalar convert from float/double to integer
3734 //===----------------------------------------------------------------------===//
3735 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3736 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3738 let hasSideEffects = 0 in {
3739 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3740 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3741 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3742 Requires<[HasAVX512]>;
3744 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
3745 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
3746 Requires<[HasAVX512]>;
3747 } // hasSideEffects = 0
3749 let Predicates = [HasAVX512] in {
3750 // Convert float/double to signed/unsigned int 32/64
3751 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
3752 ssmem, sse_load_f32, "cvtss2si">,
3753 XS, EVEX_CD8<32, CD8VT1>;
3754 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3755 ssmem, sse_load_f32, "cvtss2si">,
3756 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3757 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3758 ssmem, sse_load_f32, "cvtss2usi">,
3759 XS, EVEX_CD8<32, CD8VT1>;
3760 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3761 int_x86_avx512_cvtss2usi64, ssmem,
3762 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3763 EVEX_CD8<32, CD8VT1>;
3764 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3765 sdmem, sse_load_f64, "cvtsd2si">,
3766 XD, EVEX_CD8<64, CD8VT1>;
3767 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3768 sdmem, sse_load_f64, "cvtsd2si">,
3769 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3770 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3771 sdmem, sse_load_f64, "cvtsd2usi">,
3772 XD, EVEX_CD8<64, CD8VT1>;
3773 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3774 int_x86_avx512_cvtsd2usi64, sdmem,
3775 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3776 EVEX_CD8<64, CD8VT1>;
3778 let isCodeGenOnly = 1 in {
3779 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3780 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3781 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3782 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3783 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3784 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3785 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3786 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3787 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3788 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3789 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3790 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3792 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3793 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3794 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3795 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3796 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3797 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3798 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3799 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3800 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3801 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3802 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3803 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3804 } // isCodeGenOnly = 1
3806 // Convert float/double to signed/unsigned int 32/64 with truncation
3807 let isCodeGenOnly = 1 in {
3808 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3809 ssmem, sse_load_f32, "cvttss2si">,
3810 XS, EVEX_CD8<32, CD8VT1>;
3811 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3812 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3813 "cvttss2si">, XS, VEX_W,
3814 EVEX_CD8<32, CD8VT1>;
3815 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3816 sdmem, sse_load_f64, "cvttsd2si">, XD,
3817 EVEX_CD8<64, CD8VT1>;
3818 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3819 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3820 "cvttsd2si">, XD, VEX_W,
3821 EVEX_CD8<64, CD8VT1>;
3822 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3823 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3824 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3825 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3826 int_x86_avx512_cvttss2usi64, ssmem,
3827 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3828 EVEX_CD8<32, CD8VT1>;
3829 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3830 int_x86_avx512_cvttsd2usi,
3831 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3832 EVEX_CD8<64, CD8VT1>;
3833 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3834 int_x86_avx512_cvttsd2usi64, sdmem,
3835 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3836 EVEX_CD8<64, CD8VT1>;
3837 } // isCodeGenOnly = 1
3839 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3840 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3842 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3843 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3844 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3845 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3846 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3847 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3850 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3851 loadf32, "cvttss2si">, XS,
3852 EVEX_CD8<32, CD8VT1>;
3853 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3854 loadf32, "cvttss2usi">, XS,
3855 EVEX_CD8<32, CD8VT1>;
3856 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3857 loadf32, "cvttss2si">, XS, VEX_W,
3858 EVEX_CD8<32, CD8VT1>;
3859 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3860 loadf32, "cvttss2usi">, XS, VEX_W,
3861 EVEX_CD8<32, CD8VT1>;
3862 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3863 loadf64, "cvttsd2si">, XD,
3864 EVEX_CD8<64, CD8VT1>;
3865 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3866 loadf64, "cvttsd2usi">, XD,
3867 EVEX_CD8<64, CD8VT1>;
3868 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3869 loadf64, "cvttsd2si">, XD, VEX_W,
3870 EVEX_CD8<64, CD8VT1>;
3871 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3872 loadf64, "cvttsd2usi">, XD, VEX_W,
3873 EVEX_CD8<64, CD8VT1>;
3875 //===----------------------------------------------------------------------===//
3876 // AVX-512 Convert form float to double and back
3877 //===----------------------------------------------------------------------===//
3878 let hasSideEffects = 0 in {
3879 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3880 (ins FR32X:$src1, FR32X:$src2),
3881 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3882 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3884 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3885 (ins FR32X:$src1, f32mem:$src2),
3886 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3887 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3888 EVEX_CD8<32, CD8VT1>;
3890 // Convert scalar double to scalar single
3891 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3892 (ins FR64X:$src1, FR64X:$src2),
3893 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3894 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3896 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3897 (ins FR64X:$src1, f64mem:$src2),
3898 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3899 []>, EVEX_4V, VEX_LIG, VEX_W,
3900 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3903 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3904 Requires<[HasAVX512]>;
3905 def : Pat<(fextend (loadf32 addr:$src)),
3906 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3908 def : Pat<(extloadf32 addr:$src),
3909 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3910 Requires<[HasAVX512, OptForSize]>;
3912 def : Pat<(extloadf32 addr:$src),
3913 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3914 Requires<[HasAVX512, OptForSpeed]>;
3916 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3917 Requires<[HasAVX512]>;
3919 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3920 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3921 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3923 let hasSideEffects = 0 in {
3924 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3925 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3927 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3928 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3929 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
3930 [], d>, EVEX, EVEX_B, EVEX_RC;
3932 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3933 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3935 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3936 } // hasSideEffects = 0
3939 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3940 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3941 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3943 let hasSideEffects = 0 in {
3944 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3945 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3947 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3949 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3950 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
3952 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3953 } // hasSideEffects = 0
3956 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3957 memopv8f64, f512mem, v8f32, v8f64,
3958 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3959 EVEX_CD8<64, CD8VF>;
3961 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3962 memopv4f64, f256mem, v8f64, v8f32,
3963 SSEPackedDouble>, EVEX_V512, PS,
3964 EVEX_CD8<32, CD8VH>;
3965 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3966 (VCVTPS2PDZrm addr:$src)>;
3968 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3969 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3970 (VCVTPD2PSZrr VR512:$src)>;
3972 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3973 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3974 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3976 //===----------------------------------------------------------------------===//
3977 // AVX-512 Vector convert from sign integer to float/double
3978 //===----------------------------------------------------------------------===//
3980 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3981 memopv8i64, i512mem, v16f32, v16i32,
3982 SSEPackedSingle>, EVEX_V512, PS,
3983 EVEX_CD8<32, CD8VF>;
3985 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3986 memopv4i64, i256mem, v8f64, v8i32,
3987 SSEPackedDouble>, EVEX_V512, XS,
3988 EVEX_CD8<32, CD8VH>;
3990 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3991 memopv16f32, f512mem, v16i32, v16f32,
3992 SSEPackedSingle>, EVEX_V512, XS,
3993 EVEX_CD8<32, CD8VF>;
3995 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3996 memopv8f64, f512mem, v8i32, v8f64,
3997 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3998 EVEX_CD8<64, CD8VF>;
4000 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4001 memopv16f32, f512mem, v16i32, v16f32,
4002 SSEPackedSingle>, EVEX_V512, PS,
4003 EVEX_CD8<32, CD8VF>;
4005 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4006 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4007 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4008 (VCVTTPS2UDQZrr VR512:$src)>;
4010 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4011 memopv8f64, f512mem, v8i32, v8f64,
4012 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4013 EVEX_CD8<64, CD8VF>;
4015 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4016 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4017 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4018 (VCVTTPD2UDQZrr VR512:$src)>;
4020 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4021 memopv4i64, f256mem, v8f64, v8i32,
4022 SSEPackedDouble>, EVEX_V512, XS,
4023 EVEX_CD8<32, CD8VH>;
4025 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4026 memopv16i32, f512mem, v16f32, v16i32,
4027 SSEPackedSingle>, EVEX_V512, XD,
4028 EVEX_CD8<32, CD8VF>;
4030 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4031 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4032 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4034 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4035 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4036 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4038 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4039 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4040 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4042 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4043 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4044 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4046 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4047 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4048 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4050 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4051 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4052 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4053 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4054 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4055 (VCVTDQ2PDZrr VR256X:$src)>;
4056 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4057 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4058 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4059 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4060 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4061 (VCVTUDQ2PDZrr VR256X:$src)>;
4063 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4064 RegisterClass DstRC, PatFrag mem_frag,
4065 X86MemOperand x86memop, Domain d> {
4066 let hasSideEffects = 0 in {
4067 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4068 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4070 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4071 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4072 [], d>, EVEX, EVEX_B, EVEX_RC;
4074 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4075 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4077 } // hasSideEffects = 0
4080 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4081 memopv16f32, f512mem, SSEPackedSingle>, PD,
4082 EVEX_V512, EVEX_CD8<32, CD8VF>;
4083 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4084 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4085 EVEX_V512, EVEX_CD8<64, CD8VF>;
4087 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4088 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4089 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4091 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4092 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4093 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4095 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4096 memopv16f32, f512mem, SSEPackedSingle>,
4097 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4098 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4099 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
4100 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4102 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4103 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4104 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4106 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4107 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4108 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4110 let Predicates = [HasAVX512] in {
4111 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4112 (VCVTPD2PSZrm addr:$src)>;
4113 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4114 (VCVTPS2PDZrm addr:$src)>;
4117 //===----------------------------------------------------------------------===//
4118 // Half precision conversion instructions
4119 //===----------------------------------------------------------------------===//
4120 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4121 X86MemOperand x86memop> {
4122 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4123 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4125 let hasSideEffects = 0, mayLoad = 1 in
4126 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4127 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4130 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4131 X86MemOperand x86memop> {
4132 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4133 (ins srcRC:$src1, i32i8imm:$src2),
4134 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4136 let hasSideEffects = 0, mayStore = 1 in
4137 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4138 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
4139 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4142 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4143 EVEX_CD8<32, CD8VH>;
4144 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4145 EVEX_CD8<32, CD8VH>;
4147 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4148 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4149 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4151 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4152 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4153 (VCVTPH2PSZrr VR256X:$src)>;
4155 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4156 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4157 "ucomiss">, PS, EVEX, VEX_LIG,
4158 EVEX_CD8<32, CD8VT1>;
4159 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4160 "ucomisd">, PD, EVEX,
4161 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4162 let Pattern = []<dag> in {
4163 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4164 "comiss">, PS, EVEX, VEX_LIG,
4165 EVEX_CD8<32, CD8VT1>;
4166 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4167 "comisd">, PD, EVEX,
4168 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4170 let isCodeGenOnly = 1 in {
4171 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4172 load, "ucomiss">, PS, EVEX, VEX_LIG,
4173 EVEX_CD8<32, CD8VT1>;
4174 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4175 load, "ucomisd">, PD, EVEX,
4176 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4178 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4179 load, "comiss">, PS, EVEX, VEX_LIG,
4180 EVEX_CD8<32, CD8VT1>;
4181 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4182 load, "comisd">, PD, EVEX,
4183 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4187 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4188 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4189 X86MemOperand x86memop> {
4190 let hasSideEffects = 0 in {
4191 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4192 (ins RC:$src1, RC:$src2),
4193 !strconcat(OpcodeStr,
4194 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4195 let mayLoad = 1 in {
4196 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4197 (ins RC:$src1, x86memop:$src2),
4198 !strconcat(OpcodeStr,
4199 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4204 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4205 EVEX_CD8<32, CD8VT1>;
4206 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4207 VEX_W, EVEX_CD8<64, CD8VT1>;
4208 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4209 EVEX_CD8<32, CD8VT1>;
4210 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4211 VEX_W, EVEX_CD8<64, CD8VT1>;
4213 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4214 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4215 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4216 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4218 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4219 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4220 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4221 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4223 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4224 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4225 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4226 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4228 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4229 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4230 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4231 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4233 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4234 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4235 X86VectorVTInfo _> {
4236 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4237 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4238 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4239 let mayLoad = 1 in {
4240 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4241 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4243 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4244 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4245 (ins _.ScalarMemOp:$src), OpcodeStr,
4246 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4248 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4253 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4254 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4255 EVEX_V512, EVEX_CD8<32, CD8VF>;
4256 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4257 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4259 // Define only if AVX512VL feature is present.
4260 let Predicates = [HasVLX] in {
4261 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4262 OpNode, v4f32x_info>,
4263 EVEX_V128, EVEX_CD8<32, CD8VF>;
4264 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4265 OpNode, v8f32x_info>,
4266 EVEX_V256, EVEX_CD8<32, CD8VF>;
4267 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4268 OpNode, v2f64x_info>,
4269 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4270 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4271 OpNode, v4f64x_info>,
4272 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4276 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4277 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4279 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4280 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4281 (VRSQRT14PSZr VR512:$src)>;
4282 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4283 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4284 (VRSQRT14PDZr VR512:$src)>;
4286 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4287 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4288 (VRCP14PSZr VR512:$src)>;
4289 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4290 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4291 (VRCP14PDZr VR512:$src)>;
4293 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4294 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4297 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4298 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4299 "$src2, $src1", "$src1, $src2",
4300 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4301 (i32 FROUND_CURRENT))>;
4303 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4304 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4305 "$src2, $src1", "$src1, $src2",
4306 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4307 (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
4309 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4310 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4311 "$src2, $src1", "$src1, $src2",
4312 (OpNode (_.VT _.RC:$src1),
4313 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4314 (i32 FROUND_CURRENT))>;
4317 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4318 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4319 EVEX_CD8<32, CD8VT1>;
4320 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4321 EVEX_CD8<64, CD8VT1>, VEX_W;
4324 let hasSideEffects = 0, Predicates = [HasERI] in {
4325 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4326 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4328 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4330 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4333 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4334 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4335 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4337 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4338 (ins _.RC:$src), OpcodeStr,
4340 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
4343 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4344 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4346 (bitconvert (_.LdFrag addr:$src))),
4347 (i32 FROUND_CURRENT))>;
4349 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4350 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4352 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4353 (i32 FROUND_CURRENT))>, EVEX_B;
4356 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4357 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4358 EVEX_CD8<32, CD8VF>;
4359 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4360 VEX_W, EVEX_CD8<32, CD8VF>;
4363 let Predicates = [HasERI], hasSideEffects = 0 in {
4365 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX, EVEX_V512, T8PD;
4366 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX, EVEX_V512, T8PD;
4367 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX, EVEX_V512, T8PD;
4370 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4371 SDNode OpNode, X86VectorVTInfo _>{
4372 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4373 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4374 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4375 let mayLoad = 1 in {
4376 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4377 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4379 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4381 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4382 (ins _.ScalarMemOp:$src), OpcodeStr,
4383 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4385 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4390 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4391 Intrinsic F32Int, Intrinsic F64Int,
4392 OpndItins itins_s, OpndItins itins_d> {
4393 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4394 (ins FR32X:$src1, FR32X:$src2),
4395 !strconcat(OpcodeStr,
4396 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4397 [], itins_s.rr>, XS, EVEX_4V;
4398 let isCodeGenOnly = 1 in
4399 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4400 (ins VR128X:$src1, VR128X:$src2),
4401 !strconcat(OpcodeStr,
4402 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4404 (F32Int VR128X:$src1, VR128X:$src2))],
4405 itins_s.rr>, XS, EVEX_4V;
4406 let mayLoad = 1 in {
4407 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4408 (ins FR32X:$src1, f32mem:$src2),
4409 !strconcat(OpcodeStr,
4410 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4411 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4412 let isCodeGenOnly = 1 in
4413 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4414 (ins VR128X:$src1, ssmem:$src2),
4415 !strconcat(OpcodeStr,
4416 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4418 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4419 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4421 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4422 (ins FR64X:$src1, FR64X:$src2),
4423 !strconcat(OpcodeStr,
4424 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4426 let isCodeGenOnly = 1 in
4427 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4428 (ins VR128X:$src1, VR128X:$src2),
4429 !strconcat(OpcodeStr,
4430 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4432 (F64Int VR128X:$src1, VR128X:$src2))],
4433 itins_s.rr>, XD, EVEX_4V, VEX_W;
4434 let mayLoad = 1 in {
4435 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4436 (ins FR64X:$src1, f64mem:$src2),
4437 !strconcat(OpcodeStr,
4438 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4439 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4440 let isCodeGenOnly = 1 in
4441 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4442 (ins VR128X:$src1, sdmem:$src2),
4443 !strconcat(OpcodeStr,
4444 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4446 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4447 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4451 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4453 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4455 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4456 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4458 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4459 // Define only if AVX512VL feature is present.
4460 let Predicates = [HasVLX] in {
4461 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4462 OpNode, v4f32x_info>,
4463 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4464 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4465 OpNode, v8f32x_info>,
4466 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4467 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4468 OpNode, v2f64x_info>,
4469 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4470 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4471 OpNode, v4f64x_info>,
4472 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4476 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
4478 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4479 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4480 SSE_SQRTSS, SSE_SQRTSD>;
4482 let Predicates = [HasAVX512] in {
4483 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4484 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4485 (VSQRTPSZr VR512:$src1)>;
4486 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4487 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4488 (VSQRTPDZr VR512:$src1)>;
4490 def : Pat<(f32 (fsqrt FR32X:$src)),
4491 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4492 def : Pat<(f32 (fsqrt (load addr:$src))),
4493 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4494 Requires<[OptForSize]>;
4495 def : Pat<(f64 (fsqrt FR64X:$src)),
4496 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4497 def : Pat<(f64 (fsqrt (load addr:$src))),
4498 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4499 Requires<[OptForSize]>;
4501 def : Pat<(f32 (X86frsqrt FR32X:$src)),
4502 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4503 def : Pat<(f32 (X86frsqrt (load addr:$src))),
4504 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4505 Requires<[OptForSize]>;
4507 def : Pat<(f32 (X86frcp FR32X:$src)),
4508 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4509 def : Pat<(f32 (X86frcp (load addr:$src))),
4510 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4511 Requires<[OptForSize]>;
4513 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4514 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4515 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4517 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4518 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4520 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4521 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4522 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4524 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4525 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4529 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4530 X86MemOperand x86memop, RegisterClass RC,
4531 PatFrag mem_frag32, PatFrag mem_frag64,
4532 Intrinsic V4F32Int, Intrinsic V2F64Int,
4534 let ExeDomain = SSEPackedSingle in {
4535 // Intrinsic operation, reg.
4536 // Vector intrinsic operation, reg
4537 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4538 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4539 !strconcat(OpcodeStr,
4540 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4541 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4543 // Vector intrinsic operation, mem
4544 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4545 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4546 !strconcat(OpcodeStr,
4547 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4549 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4550 EVEX_CD8<32, VForm>;
4551 } // ExeDomain = SSEPackedSingle
4553 let ExeDomain = SSEPackedDouble in {
4554 // Vector intrinsic operation, reg
4555 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4556 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4557 !strconcat(OpcodeStr,
4558 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4559 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4561 // Vector intrinsic operation, mem
4562 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4563 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4564 !strconcat(OpcodeStr,
4565 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4567 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4568 EVEX_CD8<64, VForm>;
4569 } // ExeDomain = SSEPackedDouble
4572 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4576 let ExeDomain = GenericDomain in {
4578 let hasSideEffects = 0 in
4579 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4580 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4581 !strconcat(OpcodeStr,
4582 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4585 // Intrinsic operation, reg.
4586 let isCodeGenOnly = 1 in
4587 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4588 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4589 !strconcat(OpcodeStr,
4590 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4591 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4593 // Intrinsic operation, mem.
4594 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4595 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4596 !strconcat(OpcodeStr,
4597 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4598 [(set VR128X:$dst, (F32Int VR128X:$src1,
4599 sse_load_f32:$src2, imm:$src3))]>,
4600 EVEX_CD8<32, CD8VT1>;
4603 let hasSideEffects = 0 in
4604 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4605 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4606 !strconcat(OpcodeStr,
4607 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4610 // Intrinsic operation, reg.
4611 let isCodeGenOnly = 1 in
4612 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4613 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4614 !strconcat(OpcodeStr,
4615 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4616 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4619 // Intrinsic operation, mem.
4620 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4621 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4622 !strconcat(OpcodeStr,
4623 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4625 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4626 VEX_W, EVEX_CD8<64, CD8VT1>;
4627 } // ExeDomain = GenericDomain
4630 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4631 X86MemOperand x86memop, RegisterClass RC,
4632 PatFrag mem_frag, Domain d> {
4633 let ExeDomain = d in {
4634 // Intrinsic operation, reg.
4635 // Vector intrinsic operation, reg
4636 def r : AVX512AIi8<opc, MRMSrcReg,
4637 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4638 !strconcat(OpcodeStr,
4639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4642 // Vector intrinsic operation, mem
4643 def m : AVX512AIi8<opc, MRMSrcMem,
4644 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4645 !strconcat(OpcodeStr,
4646 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4652 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4653 memopv16f32, SSEPackedSingle>, EVEX_V512,
4654 EVEX_CD8<32, CD8VF>;
4656 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
4657 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
4659 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4662 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4663 memopv8f64, SSEPackedDouble>, EVEX_V512,
4664 VEX_W, EVEX_CD8<64, CD8VF>;
4666 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
4667 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
4669 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4671 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4672 Operand x86memop, RegisterClass RC, Domain d> {
4673 let ExeDomain = d in {
4674 def r : AVX512AIi8<opc, MRMSrcReg,
4675 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4676 !strconcat(OpcodeStr,
4677 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4680 def m : AVX512AIi8<opc, MRMSrcMem,
4681 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4682 !strconcat(OpcodeStr,
4683 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4688 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4689 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4691 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4692 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4694 def : Pat<(ffloor FR32X:$src),
4695 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4696 def : Pat<(f64 (ffloor FR64X:$src)),
4697 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4698 def : Pat<(f32 (fnearbyint FR32X:$src)),
4699 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4700 def : Pat<(f64 (fnearbyint FR64X:$src)),
4701 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4702 def : Pat<(f32 (fceil FR32X:$src)),
4703 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4704 def : Pat<(f64 (fceil FR64X:$src)),
4705 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4706 def : Pat<(f32 (frint FR32X:$src)),
4707 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4708 def : Pat<(f64 (frint FR64X:$src)),
4709 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4710 def : Pat<(f32 (ftrunc FR32X:$src)),
4711 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4712 def : Pat<(f64 (ftrunc FR64X:$src)),
4713 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4715 def : Pat<(v16f32 (ffloor VR512:$src)),
4716 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
4717 def : Pat<(v16f32 (fnearbyint VR512:$src)),
4718 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
4719 def : Pat<(v16f32 (fceil VR512:$src)),
4720 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
4721 def : Pat<(v16f32 (frint VR512:$src)),
4722 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
4723 def : Pat<(v16f32 (ftrunc VR512:$src)),
4724 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
4726 def : Pat<(v8f64 (ffloor VR512:$src)),
4727 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
4728 def : Pat<(v8f64 (fnearbyint VR512:$src)),
4729 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
4730 def : Pat<(v8f64 (fceil VR512:$src)),
4731 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
4732 def : Pat<(v8f64 (frint VR512:$src)),
4733 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
4734 def : Pat<(v8f64 (ftrunc VR512:$src)),
4735 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
4737 //-------------------------------------------------
4738 // Integer truncate and extend operations
4739 //-------------------------------------------------
4741 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4742 RegisterClass dstRC, RegisterClass srcRC,
4743 RegisterClass KRC, X86MemOperand x86memop> {
4744 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4746 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4749 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4750 (ins KRC:$mask, srcRC:$src),
4751 !strconcat(OpcodeStr,
4752 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4755 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4756 (ins KRC:$mask, srcRC:$src),
4757 !strconcat(OpcodeStr,
4758 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4761 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4762 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4765 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4766 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4767 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4771 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4772 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4773 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4774 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4775 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4776 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4777 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4778 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4779 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4780 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4781 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4782 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4783 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4784 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4785 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4786 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4787 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4788 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4789 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4790 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4791 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4792 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4793 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4794 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4795 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4796 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4797 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4798 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4799 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4800 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4802 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4803 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4804 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4805 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4806 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4808 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4809 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4810 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4811 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4812 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4813 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4814 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4815 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4818 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4819 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4820 PatFrag mem_frag, X86MemOperand x86memop,
4821 ValueType OpVT, ValueType InVT> {
4823 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4825 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4826 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4828 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4829 (ins KRC:$mask, SrcRC:$src),
4830 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4833 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4834 (ins KRC:$mask, SrcRC:$src),
4835 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4838 let mayLoad = 1 in {
4839 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4840 (ins x86memop:$src),
4841 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
4843 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4846 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4847 (ins KRC:$mask, x86memop:$src),
4848 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4852 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4853 (ins KRC:$mask, x86memop:$src),
4854 !strconcat(OpcodeStr,"\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4860 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4861 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4863 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4864 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4866 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4867 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4868 EVEX_CD8<16, CD8VH>;
4869 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4870 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4871 EVEX_CD8<16, CD8VQ>;
4872 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4873 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4874 EVEX_CD8<32, CD8VH>;
4876 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4877 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4879 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4880 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4882 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4883 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4884 EVEX_CD8<16, CD8VH>;
4885 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4886 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4887 EVEX_CD8<16, CD8VQ>;
4888 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4889 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4890 EVEX_CD8<32, CD8VH>;
4892 //===----------------------------------------------------------------------===//
4893 // GATHER - SCATTER Operations
4895 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4896 RegisterClass RC, X86MemOperand memop> {
4898 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4899 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4900 (ins RC:$src1, KRC:$mask, memop:$src2),
4901 !strconcat(OpcodeStr,
4902 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4906 let ExeDomain = SSEPackedDouble in {
4907 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4908 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4909 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4910 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4913 let ExeDomain = SSEPackedSingle in {
4914 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4915 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4916 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4917 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4920 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4921 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4922 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4923 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4925 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4926 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4927 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4928 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4930 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4931 RegisterClass RC, X86MemOperand memop> {
4932 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4933 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4934 (ins memop:$dst, KRC:$mask, RC:$src2),
4935 !strconcat(OpcodeStr,
4936 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4940 let ExeDomain = SSEPackedDouble in {
4941 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4942 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4943 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4944 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4947 let ExeDomain = SSEPackedSingle in {
4948 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4949 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4950 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4951 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4954 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4955 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4956 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4957 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4959 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4960 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4961 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4962 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4965 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4966 RegisterClass KRC, X86MemOperand memop> {
4967 let Predicates = [HasPFI], hasSideEffects = 1 in
4968 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4969 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
4973 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4974 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4976 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4977 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4979 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4980 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4982 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4983 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4985 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4986 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4988 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4989 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4991 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4992 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4994 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4995 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4997 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4998 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5000 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5001 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5003 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5004 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5006 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5007 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5009 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5010 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5012 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5013 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5015 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5016 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5018 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5019 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5020 //===----------------------------------------------------------------------===//
5021 // VSHUFPS - VSHUFPD Operations
5023 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5024 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5026 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5027 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
5028 !strconcat(OpcodeStr,
5029 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5030 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5031 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5032 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5033 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5034 (ins RC:$src1, RC:$src2, i8imm:$src3),
5035 !strconcat(OpcodeStr,
5036 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5037 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5038 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5039 EVEX_4V, Sched<[WriteShuffle]>;
5042 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
5043 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5044 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
5045 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5047 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5048 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5049 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5050 (memopv16i32 addr:$src2), (i8 imm:$imm))),
5051 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5053 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5054 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5055 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5056 (memopv8i64 addr:$src2), (i8 imm:$imm))),
5057 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5059 multiclass avx512_valign<X86VectorVTInfo _> {
5060 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
5061 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
5063 "$src3, $src2, $src1", "$src1, $src2, $src3",
5064 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
5066 AVX512AIi8Base, EVEX_4V;
5068 // Also match valign of packed floats.
5069 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
5070 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
5073 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
5074 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
5075 !strconcat("valign"##_.Suffix,
5076 "\t{$src3, $src2, $src1, $dst|"
5077 "$dst, $src1, $src2, $src3}"),
5080 defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
5081 defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5083 // Helper fragments to match sext vXi1 to vXiY.
5084 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5085 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5087 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5088 RegisterClass KRC, RegisterClass RC,
5089 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5091 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5092 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5094 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5095 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5097 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5098 !strconcat(OpcodeStr,
5099 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5101 let mayLoad = 1 in {
5102 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5103 (ins x86memop:$src),
5104 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5106 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5107 (ins KRC:$mask, x86memop:$src),
5108 !strconcat(OpcodeStr,
5109 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5111 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5112 (ins KRC:$mask, x86memop:$src),
5113 !strconcat(OpcodeStr,
5114 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5116 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5117 (ins x86scalar_mop:$src),
5118 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5119 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5121 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5122 (ins KRC:$mask, x86scalar_mop:$src),
5123 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5124 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5125 []>, EVEX, EVEX_B, EVEX_K;
5126 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5127 (ins KRC:$mask, x86scalar_mop:$src),
5128 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5129 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5131 []>, EVEX, EVEX_B, EVEX_KZ;
5135 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5136 i512mem, i32mem, "{1to16}">, EVEX_V512,
5137 EVEX_CD8<32, CD8VF>;
5138 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5139 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5140 EVEX_CD8<64, CD8VF>;
5143 (bc_v16i32 (v16i1sextv16i32)),
5144 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5145 (VPABSDZrr VR512:$src)>;
5147 (bc_v8i64 (v8i1sextv8i64)),
5148 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5149 (VPABSQZrr VR512:$src)>;
5151 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5152 (v16i32 immAllZerosV), (i16 -1))),
5153 (VPABSDZrr VR512:$src)>;
5154 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5155 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5156 (VPABSQZrr VR512:$src)>;
5158 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5159 RegisterClass RC, RegisterClass KRC,
5160 X86MemOperand x86memop,
5161 X86MemOperand x86scalar_mop, string BrdcstStr> {
5162 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5164 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5166 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5167 (ins x86memop:$src),
5168 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5170 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5171 (ins x86scalar_mop:$src),
5172 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5173 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5175 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5176 (ins KRC:$mask, RC:$src),
5177 !strconcat(OpcodeStr,
5178 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5180 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5181 (ins KRC:$mask, x86memop:$src),
5182 !strconcat(OpcodeStr,
5183 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5185 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5186 (ins KRC:$mask, x86scalar_mop:$src),
5187 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5188 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5190 []>, EVEX, EVEX_KZ, EVEX_B;
5192 let Constraints = "$src1 = $dst" in {
5193 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5194 (ins RC:$src1, KRC:$mask, RC:$src2),
5195 !strconcat(OpcodeStr,
5196 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5198 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5199 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5200 !strconcat(OpcodeStr,
5201 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5203 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5204 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5205 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5206 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5207 []>, EVEX, EVEX_K, EVEX_B;
5211 let Predicates = [HasCDI] in {
5212 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5213 i512mem, i32mem, "{1to16}">,
5214 EVEX_V512, EVEX_CD8<32, CD8VF>;
5217 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5218 i512mem, i64mem, "{1to8}">,
5219 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5223 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5225 (VPCONFLICTDrrk VR512:$src1,
5226 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5228 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5230 (VPCONFLICTQrrk VR512:$src1,
5231 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5233 let Predicates = [HasCDI] in {
5234 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5235 i512mem, i32mem, "{1to16}">,
5236 EVEX_V512, EVEX_CD8<32, CD8VF>;
5239 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5240 i512mem, i64mem, "{1to8}">,
5241 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5245 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5247 (VPLZCNTDrrk VR512:$src1,
5248 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5250 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5252 (VPLZCNTQrrk VR512:$src1,
5253 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5255 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5256 (VPLZCNTDrm addr:$src)>;
5257 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5258 (VPLZCNTDrr VR512:$src)>;
5259 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5260 (VPLZCNTQrm addr:$src)>;
5261 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5262 (VPLZCNTQrr VR512:$src)>;
5264 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5265 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5266 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5268 def : Pat<(store VK1:$src, addr:$dst),
5269 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5271 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5272 (truncstore node:$val, node:$ptr), [{
5273 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5276 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5277 (MOV8mr addr:$dst, GR8:$src)>;
5279 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5280 def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5281 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5282 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5285 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5286 string OpcodeStr, Predicate prd> {
5287 let Predicates = [prd] in
5288 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5290 let Predicates = [prd, HasVLX] in {
5291 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5292 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5296 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5297 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5299 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5301 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5303 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5307 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5309 //===----------------------------------------------------------------------===//
5310 // AVX-512 - COMPRESS and EXPAND
5312 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5314 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5315 (ins _.KRCWM:$mask, _.RC:$src),
5316 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5317 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5318 _.ImmAllZerosV)))]>, EVEX_KZ;
5320 let Constraints = "$src0 = $dst" in
5321 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5322 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5323 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5324 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5325 _.RC:$src0)))]>, EVEX_K;
5327 let mayStore = 1 in {
5328 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5329 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5330 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5331 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5333 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5337 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5338 AVX512VLVectorVTInfo VTInfo> {
5339 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5341 let Predicates = [HasVLX] in {
5342 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5343 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5347 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5349 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5351 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5353 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5357 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5359 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5360 (ins _.KRCWM:$mask, _.RC:$src),
5361 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5362 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5363 _.ImmAllZerosV)))]>, EVEX_KZ;
5365 let Constraints = "$src0 = $dst" in
5366 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5367 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5368 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5369 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5370 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5372 let mayLoad = 1, Constraints = "$src0 = $dst" in
5373 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5374 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5375 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5376 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5378 (_.LdFrag addr:$src))),
5380 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5383 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5384 (ins _.KRCWM:$mask, _.MemOp:$src),
5385 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5386 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5387 (_.VT (bitconvert (_.LdFrag addr:$src))),
5388 _.ImmAllZerosV)))]>,
5389 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5393 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5394 AVX512VLVectorVTInfo VTInfo> {
5395 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5397 let Predicates = [HasVLX] in {
5398 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5399 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5403 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5405 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5407 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5409 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,