1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
183 string MaskingConstraint = "",
184 InstrItinClass itin = NoItinerary,
185 bit IsCommutable = 0> {
186 let isCommutable = IsCommutable in
187 def NAME: AVX512<O, F, Outs, Ins,
188 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
189 "$dst , "#IntelSrcAsm#"}",
192 // Prefer over VMOV*rrk Pat<>
193 let AddedComplexity = 20 in
194 def NAME#k: AVX512<O, F, Outs, MaskingIns,
195 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
196 "$dst {${mask}}, "#IntelSrcAsm#"}",
197 MaskingPattern, itin>,
199 // In case of the 3src subclass this is overridden with a let.
200 string Constraints = MaskingConstraint;
202 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
203 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
204 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
205 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
212 // Common base class of AVX512_maskable and AVX512_maskable_3src.
213 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
215 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, dag MaskingRHS,
219 SDNode Select = vselect,
220 string MaskingConstraint = "",
221 InstrItinClass itin = NoItinerary,
222 bit IsCommutable = 0> :
223 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
224 AttSrcAsm, IntelSrcAsm,
225 [(set _.RC:$dst, RHS)],
226 [(set _.RC:$dst, MaskingRHS)],
228 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
229 MaskingConstraint, NoItinerary, IsCommutable>;
231 // This multiclass generates the unconditional/non-masking, the masking and
232 // the zero-masking variant of the vector instruction. In the masking case, the
233 // perserved vector elements come from a new dummy input operand tied to $dst.
234 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
235 dag Outs, dag Ins, string OpcodeStr,
236 string AttSrcAsm, string IntelSrcAsm,
238 InstrItinClass itin = NoItinerary,
239 bit IsCommutable = 0> :
240 AVX512_maskable_common<O, F, _, Outs, Ins,
241 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
242 !con((ins _.KRCWM:$mask), Ins),
243 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
244 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
245 "$src0 = $dst", itin, IsCommutable>;
247 // This multiclass generates the unconditional/non-masking, the masking and
248 // the zero-masking variant of the scalar instruction.
249 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
250 dag Outs, dag Ins, string OpcodeStr,
251 string AttSrcAsm, string IntelSrcAsm,
253 InstrItinClass itin = NoItinerary,
254 bit IsCommutable = 0> :
255 AVX512_maskable_common<O, F, _, Outs, Ins,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
257 !con((ins _.KRCWM:$mask), Ins),
258 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
259 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
260 "$src0 = $dst", itin, IsCommutable>;
262 // Similar to AVX512_maskable but in this case one of the source operands
263 // ($src1) is already tied to $dst so we just use that for the preserved
264 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
266 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
267 dag Outs, dag NonTiedIns, string OpcodeStr,
268 string AttSrcAsm, string IntelSrcAsm,
270 AVX512_maskable_common<O, F, _, Outs,
271 !con((ins _.RC:$src1), NonTiedIns),
272 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
275 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
278 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_custom<O, F, Outs, Ins,
284 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
285 !con((ins _.KRCWM:$mask), Ins),
286 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
290 // Instruction with mask that puts result in mask register,
291 // like "compare" and "vptest"
292 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
294 dag Ins, dag MaskingIns,
296 string AttSrcAsm, string IntelSrcAsm,
298 list<dag> MaskingPattern,
300 InstrItinClass itin = NoItinerary> {
301 def NAME: AVX512<O, F, Outs, Ins,
302 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
303 "$dst "#Round#", "#IntelSrcAsm#"}",
306 def NAME#k: AVX512<O, F, Outs, MaskingIns,
307 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
308 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
309 MaskingPattern, itin>, EVEX_K;
312 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
314 dag Ins, dag MaskingIns,
316 string AttSrcAsm, string IntelSrcAsm,
317 dag RHS, dag MaskingRHS,
319 InstrItinClass itin = NoItinerary> :
320 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
321 AttSrcAsm, IntelSrcAsm,
322 [(set _.KRC:$dst, RHS)],
323 [(set _.KRC:$dst, MaskingRHS)],
326 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
327 dag Outs, dag Ins, string OpcodeStr,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, string Round = "",
330 InstrItinClass itin = NoItinerary> :
331 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
332 !con((ins _.KRCWM:$mask), Ins),
333 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
334 (and _.KRCWM:$mask, RHS),
337 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
338 dag Outs, dag Ins, string OpcodeStr,
339 string AttSrcAsm, string IntelSrcAsm> :
340 AVX512_maskable_custom_cmp<O, F, Outs,
341 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
342 AttSrcAsm, IntelSrcAsm,
343 [],[],"", NoItinerary>;
345 // Bitcasts between 512-bit vector types. Return the original type since
346 // no instruction is needed for the conversion
347 let Predicates = [HasAVX512] in {
348 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
349 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
350 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
351 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
352 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
353 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
354 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
355 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
356 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
357 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
358 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
359 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
360 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
361 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
362 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
363 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
364 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
365 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
366 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
367 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
368 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
369 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
370 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
371 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
372 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
373 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
374 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
375 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
376 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
377 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
378 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
380 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
381 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
382 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
383 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
384 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
385 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
386 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
387 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
388 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
389 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
390 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
391 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
392 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
393 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
394 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
395 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
396 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
397 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
398 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
399 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
400 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
401 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
402 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
403 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
404 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
405 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
406 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
407 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
408 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
409 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
411 // Bitcasts between 256-bit vector types. Return the original type since
412 // no instruction is needed for the conversion
413 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
414 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
415 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
416 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
417 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
418 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
419 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
420 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
421 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
422 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
423 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
424 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
425 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
426 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
427 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
428 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
429 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
430 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
431 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
432 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
433 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
434 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
435 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
436 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
437 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
438 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
439 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
440 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
441 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
442 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
446 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
449 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
450 isPseudo = 1, Predicates = [HasAVX512] in {
451 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
452 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
455 let Predicates = [HasAVX512] in {
456 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
457 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
458 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
461 //===----------------------------------------------------------------------===//
462 // AVX-512 - VECTOR INSERT
465 multiclass vinsert_for_size_no_alt<int Opcode,
466 X86VectorVTInfo From, X86VectorVTInfo To,
467 PatFrag vinsert_insert,
468 SDNodeXForm INSERT_get_vinsert_imm> {
469 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
470 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
471 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
472 "vinsert" # From.EltTypeName # "x" # From.NumElts #
473 "\t{$src3, $src2, $src1, $dst|"
474 "$dst, $src1, $src2, $src3}",
475 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
476 (From.VT From.RC:$src2),
481 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
482 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
483 "vinsert" # From.EltTypeName # "x" # From.NumElts #
484 "\t{$src3, $src2, $src1, $dst|"
485 "$dst, $src1, $src2, $src3}",
487 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
491 multiclass vinsert_for_size<int Opcode,
492 X86VectorVTInfo From, X86VectorVTInfo To,
493 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
494 PatFrag vinsert_insert,
495 SDNodeXForm INSERT_get_vinsert_imm> :
496 vinsert_for_size_no_alt<Opcode, From, To,
497 vinsert_insert, INSERT_get_vinsert_imm> {
498 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
499 // vinserti32x4. Only add this if 64x2 and friends are not supported
500 // natively via AVX512DQ.
501 let Predicates = [NoDQI] in
502 def : Pat<(vinsert_insert:$ins
503 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
504 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
505 VR512:$src1, From.RC:$src2,
506 (INSERT_get_vinsert_imm VR512:$ins)))>;
509 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
510 ValueType EltVT64, int Opcode256> {
511 defm NAME # "32x4" : vinsert_for_size<Opcode128,
512 X86VectorVTInfo< 4, EltVT32, VR128X>,
513 X86VectorVTInfo<16, EltVT32, VR512>,
514 X86VectorVTInfo< 2, EltVT64, VR128X>,
515 X86VectorVTInfo< 8, EltVT64, VR512>,
517 INSERT_get_vinsert128_imm>;
518 let Predicates = [HasDQI] in
519 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
520 X86VectorVTInfo< 2, EltVT64, VR128X>,
521 X86VectorVTInfo< 8, EltVT64, VR512>,
523 INSERT_get_vinsert128_imm>, VEX_W;
524 defm NAME # "64x4" : vinsert_for_size<Opcode256,
525 X86VectorVTInfo< 4, EltVT64, VR256X>,
526 X86VectorVTInfo< 8, EltVT64, VR512>,
527 X86VectorVTInfo< 8, EltVT32, VR256>,
528 X86VectorVTInfo<16, EltVT32, VR512>,
530 INSERT_get_vinsert256_imm>, VEX_W;
531 let Predicates = [HasDQI] in
532 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
533 X86VectorVTInfo< 8, EltVT32, VR256X>,
534 X86VectorVTInfo<16, EltVT32, VR512>,
536 INSERT_get_vinsert256_imm>;
539 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
540 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
542 // vinsertps - insert f32 to XMM
543 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
544 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
545 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
546 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
548 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
549 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
550 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
551 [(set VR128X:$dst, (X86insertps VR128X:$src1,
552 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
553 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
555 //===----------------------------------------------------------------------===//
556 // AVX-512 VECTOR EXTRACT
559 multiclass vextract_for_size<int Opcode,
560 X86VectorVTInfo From, X86VectorVTInfo To,
561 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
562 PatFrag vextract_extract,
563 SDNodeXForm EXTRACT_get_vextract_imm> {
564 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
565 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
566 (ins VR512:$src1, u8imm:$idx),
567 "vextract" # To.EltTypeName # "x4",
568 "$idx, $src1", "$src1, $idx",
569 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
571 AVX512AIi8Base, EVEX, EVEX_V512;
573 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
574 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
575 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
576 "$dst, $src1, $src2}",
577 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
580 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
582 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
583 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
585 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
587 // A 128/256-bit subvector extract from the first 512-bit vector position is
588 // a subregister copy that needs no instruction.
589 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
591 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
593 // And for the alternative types.
594 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
596 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
598 // Intrinsic call with masking.
599 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
601 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
602 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
603 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
604 VR512:$src1, imm:$idx)>;
606 // Intrinsic call with zero-masking.
607 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
609 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
610 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
611 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
612 VR512:$src1, imm:$idx)>;
614 // Intrinsic call without masking.
615 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
617 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
618 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
619 VR512:$src1, imm:$idx)>;
622 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
623 ValueType EltVT64, int Opcode64> {
624 defm NAME # "32x4" : vextract_for_size<Opcode32,
625 X86VectorVTInfo<16, EltVT32, VR512>,
626 X86VectorVTInfo< 4, EltVT32, VR128X>,
627 X86VectorVTInfo< 8, EltVT64, VR512>,
628 X86VectorVTInfo< 2, EltVT64, VR128X>,
630 EXTRACT_get_vextract128_imm>;
631 defm NAME # "64x4" : vextract_for_size<Opcode64,
632 X86VectorVTInfo< 8, EltVT64, VR512>,
633 X86VectorVTInfo< 4, EltVT64, VR256X>,
634 X86VectorVTInfo<16, EltVT32, VR512>,
635 X86VectorVTInfo< 8, EltVT32, VR256>,
637 EXTRACT_get_vextract256_imm>, VEX_W;
640 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
641 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
643 // A 128-bit subvector insert to the first 512-bit vector position
644 // is a subregister copy that needs no instruction.
645 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
646 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
647 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
649 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
650 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
651 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
653 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
654 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
655 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
657 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
658 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
659 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
662 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
663 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
664 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
665 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
666 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
667 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
668 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
669 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
671 // vextractps - extract 32 bits from XMM
672 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
673 (ins VR128X:$src1, u8imm:$src2),
674 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
675 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
678 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
679 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
680 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
681 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
682 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
684 //===---------------------------------------------------------------------===//
687 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
688 ValueType svt, X86VectorVTInfo _> {
689 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
690 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
691 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
695 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
696 (ins _.ScalarMemOp:$src),
697 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
698 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
703 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
704 AVX512VLVectorVTInfo _> {
705 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
708 let Predicates = [HasVLX] in {
709 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
714 let ExeDomain = SSEPackedSingle in {
715 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
716 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
717 let Predicates = [HasVLX] in {
718 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
719 v4f32, v4f32x_info>, EVEX_V128,
720 EVEX_CD8<32, CD8VT1>;
724 let ExeDomain = SSEPackedDouble in {
725 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
726 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
729 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
730 // Later, we can canonize broadcast instructions before ISel phase and
731 // eliminate additional patterns on ISel.
732 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
733 // representations of source
734 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
735 X86VectorVTInfo _, RegisterClass SrcRC_v,
736 RegisterClass SrcRC_s> {
737 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
738 (!cast<Instruction>(InstName##"r")
739 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
741 let AddedComplexity = 30 in {
742 def : Pat<(_.VT (vselect _.KRCWM:$mask,
743 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
744 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
745 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
747 def : Pat<(_.VT(vselect _.KRCWM:$mask,
748 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
749 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
750 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
754 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
756 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
759 let Predicates = [HasVLX] in {
760 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
761 v8f32x_info, VR128X, FR32X>;
762 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
763 v4f32x_info, VR128X, FR32X>;
764 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
765 v4f64x_info, VR128X, FR64X>;
768 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
769 (VBROADCASTSSZm addr:$src)>;
770 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
771 (VBROADCASTSDZm addr:$src)>;
773 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
774 (VBROADCASTSSZm addr:$src)>;
775 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
776 (VBROADCASTSDZm addr:$src)>;
778 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
779 RegisterClass SrcRC> {
780 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
781 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
782 "$src", "$src", []>, T8PD, EVEX;
785 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
786 RegisterClass SrcRC, Predicate prd> {
787 let Predicates = [prd] in
788 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
789 let Predicates = [prd, HasVLX] in {
790 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
791 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
795 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
797 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
799 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
801 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
804 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
805 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
807 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
808 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
810 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
811 (VPBROADCASTDrZr GR32:$src)>;
812 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
813 (VPBROADCASTQrZr GR64:$src)>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
816 (VPBROADCASTDrZr GR32:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
818 (VPBROADCASTQrZr GR64:$src)>;
820 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
821 (v16i32 immAllZerosV), (i16 GR16:$mask))),
822 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
823 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
824 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
825 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
827 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86MemOperand x86memop, PatFrag ld_frag,
829 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
831 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
832 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
834 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
835 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
837 !strconcat(OpcodeStr,
838 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
840 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
842 !strconcat(OpcodeStr,
843 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
846 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
849 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
850 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
852 !strconcat(OpcodeStr,
853 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
855 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
857 !strconcat(OpcodeStr,
858 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
859 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
860 (X86VBroadcast (ld_frag addr:$src)),
861 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
865 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
866 loadi32, VR512, v16i32, v4i32, VK16WM>,
867 EVEX_V512, EVEX_CD8<32, CD8VT1>;
868 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
869 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
870 EVEX_CD8<64, CD8VT1>;
872 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
873 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
875 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
876 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
878 (_Dst.VT (X86SubVBroadcast
879 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
880 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
882 !strconcat(OpcodeStr,
883 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
885 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
887 !strconcat(OpcodeStr,
888 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
893 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
894 v16i32_info, v4i32x_info>,
895 EVEX_V512, EVEX_CD8<32, CD8VT4>;
896 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
897 v16f32_info, v4f32x_info>,
898 EVEX_V512, EVEX_CD8<32, CD8VT4>;
899 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
900 v8i64_info, v4i64x_info>, VEX_W,
901 EVEX_V512, EVEX_CD8<64, CD8VT4>;
902 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
903 v8f64_info, v4f64x_info>, VEX_W,
904 EVEX_V512, EVEX_CD8<64, CD8VT4>;
906 let Predicates = [HasVLX] in {
907 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
908 v8i32x_info, v4i32x_info>,
909 EVEX_V256, EVEX_CD8<32, CD8VT4>;
910 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
911 v8f32x_info, v4f32x_info>,
912 EVEX_V256, EVEX_CD8<32, CD8VT4>;
914 let Predicates = [HasVLX, HasDQI] in {
915 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
916 v4i64x_info, v2i64x_info>, VEX_W,
917 EVEX_V256, EVEX_CD8<64, CD8VT2>;
918 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
919 v4f64x_info, v2f64x_info>, VEX_W,
920 EVEX_V256, EVEX_CD8<64, CD8VT2>;
922 let Predicates = [HasDQI] in {
923 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
924 v8i64_info, v2i64x_info>, VEX_W,
925 EVEX_V512, EVEX_CD8<64, CD8VT2>;
926 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
927 v16i32_info, v8i32x_info>,
928 EVEX_V512, EVEX_CD8<32, CD8VT8>;
929 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
930 v8f64_info, v2f64x_info>, VEX_W,
931 EVEX_V512, EVEX_CD8<64, CD8VT2>;
932 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
933 v16f32_info, v8f32x_info>,
934 EVEX_V512, EVEX_CD8<32, CD8VT8>;
937 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
938 (VPBROADCASTDZrr VR128X:$src)>;
939 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
940 (VPBROADCASTQZrr VR128X:$src)>;
942 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
943 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
944 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
945 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
947 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
948 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
949 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
950 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
952 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
953 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
954 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
955 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
957 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
958 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
959 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
960 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
962 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
963 (VBROADCASTSSZr VR128X:$src)>;
964 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
965 (VBROADCASTSDZr VR128X:$src)>;
967 // Provide fallback in case the load node that is used in the patterns above
968 // is used by additional users, which prevents the pattern selection.
969 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
970 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
971 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
972 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
975 //===----------------------------------------------------------------------===//
976 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
979 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
981 let Predicates = [HasCDI] in
982 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
983 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
984 []>, EVEX, EVEX_V512;
986 let Predicates = [HasCDI, HasVLX] in {
987 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
988 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
989 []>, EVEX, EVEX_V128;
990 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
991 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
992 []>, EVEX, EVEX_V256;
996 let Predicates = [HasCDI] in {
997 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
999 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1003 //===----------------------------------------------------------------------===//
1006 // -- immediate form --
1007 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1008 X86VectorVTInfo _> {
1009 let ExeDomain = _.ExeDomain in {
1010 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
1011 (ins _.RC:$src1, u8imm:$src2),
1012 !strconcat(OpcodeStr,
1013 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1015 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
1017 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
1018 (ins _.MemOp:$src1, u8imm:$src2),
1019 !strconcat(OpcodeStr,
1020 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1022 (_.VT (OpNode (_.LdFrag addr:$src1),
1023 (i8 imm:$src2))))]>,
1024 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
1028 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
1029 X86VectorVTInfo Ctrl> :
1030 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
1031 let ExeDomain = _.ExeDomain in {
1032 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
1033 (ins _.RC:$src1, _.RC:$src2),
1034 !strconcat("vpermil" # _.Suffix,
1035 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1037 (_.VT (X86VPermilpv _.RC:$src1,
1038 (Ctrl.VT Ctrl.RC:$src2))))]>,
1040 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
1041 (ins _.RC:$src1, Ctrl.MemOp:$src2),
1042 !strconcat("vpermil" # _.Suffix,
1043 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1045 (_.VT (X86VPermilpv _.RC:$src1,
1046 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
1050 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
1052 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1055 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1056 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1057 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1058 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1060 // -- VPERM2I - 3 source operands form --
1061 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1062 SDNode OpNode, X86VectorVTInfo _> {
1063 let Constraints = "$src1 = $dst" in {
1064 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1065 (ins _.RC:$src2, _.RC:$src3),
1066 OpcodeStr, "$src3, $src2", "$src2, $src3",
1067 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1071 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1072 (ins _.RC:$src2, _.MemOp:$src3),
1073 OpcodeStr, "$src3, $src2", "$src2, $src3",
1074 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1075 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1076 EVEX_4V, AVX5128IBase;
1079 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1080 SDNode OpNode, X86VectorVTInfo _> {
1081 let mayLoad = 1, Constraints = "$src1 = $dst" in
1082 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1083 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1084 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1085 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1086 (_.VT (OpNode _.RC:$src1,
1087 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1088 AVX5128IBase, EVEX_4V, EVEX_B;
1091 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1092 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1093 let Predicates = [HasAVX512] in
1094 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1095 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1096 let Predicates = [HasVLX] in {
1097 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1098 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1100 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1101 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1105 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1106 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1107 let Predicates = [HasBWI] in
1108 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1109 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1111 let Predicates = [HasBWI, HasVLX] in {
1112 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1113 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1115 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1116 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1120 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1121 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1122 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1123 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1124 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1125 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1126 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1127 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1129 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1130 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1131 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1132 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1133 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1134 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1135 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1136 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1138 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1139 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1140 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1141 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1143 //===----------------------------------------------------------------------===//
1144 // AVX-512 - BLEND using mask
1146 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1147 let ExeDomain = _.ExeDomain in {
1148 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1149 (ins _.RC:$src1, _.RC:$src2),
1150 !strconcat(OpcodeStr,
1151 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1153 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1154 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1155 !strconcat(OpcodeStr,
1156 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1157 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1158 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1159 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1160 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1161 !strconcat(OpcodeStr,
1162 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1163 []>, EVEX_4V, EVEX_KZ;
1164 let mayLoad = 1 in {
1165 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1166 (ins _.RC:$src1, _.MemOp:$src2),
1167 !strconcat(OpcodeStr,
1168 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1169 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1170 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1171 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1172 !strconcat(OpcodeStr,
1173 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1174 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1175 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1176 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1177 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1178 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1179 !strconcat(OpcodeStr,
1180 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1181 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1185 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1187 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1188 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1189 !strconcat(OpcodeStr,
1190 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1191 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1192 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1193 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1194 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1196 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1197 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1198 !strconcat(OpcodeStr,
1199 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1200 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1201 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1205 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1206 AVX512VLVectorVTInfo VTInfo> {
1207 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1208 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1210 let Predicates = [HasVLX] in {
1211 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1212 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1213 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1214 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1218 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1219 AVX512VLVectorVTInfo VTInfo> {
1220 let Predicates = [HasBWI] in
1221 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1223 let Predicates = [HasBWI, HasVLX] in {
1224 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1225 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1230 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1231 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1232 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1233 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1234 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1235 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1238 let Predicates = [HasAVX512] in {
1239 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1240 (v8f32 VR256X:$src2))),
1242 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1243 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1244 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1246 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1247 (v8i32 VR256X:$src2))),
1249 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1250 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1251 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1253 //===----------------------------------------------------------------------===//
1254 // Compare Instructions
1255 //===----------------------------------------------------------------------===//
1257 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1258 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1259 SDNode OpNode, ValueType VT,
1260 PatFrag ld_frag, string Suffix> {
1261 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1262 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1263 !strconcat("vcmp${cc}", Suffix,
1264 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1265 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1266 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1267 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1268 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1269 !strconcat("vcmp${cc}", Suffix,
1270 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1271 [(set VK1:$dst, (OpNode (VT RC:$src1),
1272 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1273 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1274 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1275 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1276 !strconcat("vcmp", Suffix,
1277 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1278 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1280 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1281 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1282 !strconcat("vcmp", Suffix,
1283 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1284 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1288 let Predicates = [HasAVX512] in {
1289 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1291 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1295 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1296 X86VectorVTInfo _> {
1297 def rr : AVX512BI<opc, MRMSrcReg,
1298 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1299 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1300 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1301 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1303 def rm : AVX512BI<opc, MRMSrcMem,
1304 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1305 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1306 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1307 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1308 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1309 def rrk : AVX512BI<opc, MRMSrcReg,
1310 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1311 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1312 "$dst {${mask}}, $src1, $src2}"),
1313 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1314 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1315 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1317 def rmk : AVX512BI<opc, MRMSrcMem,
1318 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1320 "$dst {${mask}}, $src1, $src2}"),
1321 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1322 (OpNode (_.VT _.RC:$src1),
1324 (_.LdFrag addr:$src2))))))],
1325 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1328 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1329 X86VectorVTInfo _> :
1330 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1331 let mayLoad = 1 in {
1332 def rmb : AVX512BI<opc, MRMSrcMem,
1333 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1334 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1335 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1336 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1337 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1338 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1339 def rmbk : AVX512BI<opc, MRMSrcMem,
1340 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1341 _.ScalarMemOp:$src2),
1342 !strconcat(OpcodeStr,
1343 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1344 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1345 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1346 (OpNode (_.VT _.RC:$src1),
1348 (_.ScalarLdFrag addr:$src2)))))],
1349 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1353 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1354 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1355 let Predicates = [prd] in
1356 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1359 let Predicates = [prd, HasVLX] in {
1360 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1362 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1367 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1368 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1370 let Predicates = [prd] in
1371 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1374 let Predicates = [prd, HasVLX] in {
1375 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1377 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1382 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1383 avx512vl_i8_info, HasBWI>,
1386 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1387 avx512vl_i16_info, HasBWI>,
1388 EVEX_CD8<16, CD8VF>;
1390 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1391 avx512vl_i32_info, HasAVX512>,
1392 EVEX_CD8<32, CD8VF>;
1394 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1395 avx512vl_i64_info, HasAVX512>,
1396 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1398 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1399 avx512vl_i8_info, HasBWI>,
1402 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1403 avx512vl_i16_info, HasBWI>,
1404 EVEX_CD8<16, CD8VF>;
1406 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1407 avx512vl_i32_info, HasAVX512>,
1408 EVEX_CD8<32, CD8VF>;
1410 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1411 avx512vl_i64_info, HasAVX512>,
1412 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1414 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1415 (COPY_TO_REGCLASS (VPCMPGTDZrr
1416 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1417 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1419 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1420 (COPY_TO_REGCLASS (VPCMPEQDZrr
1421 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1422 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1424 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1425 X86VectorVTInfo _> {
1426 def rri : AVX512AIi8<opc, MRMSrcReg,
1427 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1428 !strconcat("vpcmp${cc}", Suffix,
1429 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1430 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1432 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1434 def rmi : AVX512AIi8<opc, MRMSrcMem,
1435 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1436 !strconcat("vpcmp${cc}", Suffix,
1437 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1438 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1439 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1441 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1442 def rrik : AVX512AIi8<opc, MRMSrcReg,
1443 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1445 !strconcat("vpcmp${cc}", Suffix,
1446 "\t{$src2, $src1, $dst {${mask}}|",
1447 "$dst {${mask}}, $src1, $src2}"),
1448 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1449 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1451 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1453 def rmik : AVX512AIi8<opc, MRMSrcMem,
1454 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1456 !strconcat("vpcmp${cc}", Suffix,
1457 "\t{$src2, $src1, $dst {${mask}}|",
1458 "$dst {${mask}}, $src1, $src2}"),
1459 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1460 (OpNode (_.VT _.RC:$src1),
1461 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1463 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1465 // Accept explicit immediate argument form instead of comparison code.
1466 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1467 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1468 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1469 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1470 "$dst, $src1, $src2, $cc}"),
1471 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1473 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1474 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1475 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1476 "$dst, $src1, $src2, $cc}"),
1477 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1478 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1479 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1481 !strconcat("vpcmp", Suffix,
1482 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1483 "$dst {${mask}}, $src1, $src2, $cc}"),
1484 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1486 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1487 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1489 !strconcat("vpcmp", Suffix,
1490 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1491 "$dst {${mask}}, $src1, $src2, $cc}"),
1492 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1496 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1497 X86VectorVTInfo _> :
1498 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1499 def rmib : AVX512AIi8<opc, MRMSrcMem,
1500 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1502 !strconcat("vpcmp${cc}", Suffix,
1503 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1504 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1505 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1506 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1508 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1509 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1510 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1511 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1512 !strconcat("vpcmp${cc}", Suffix,
1513 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1514 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1515 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1516 (OpNode (_.VT _.RC:$src1),
1517 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1519 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1521 // Accept explicit immediate argument form instead of comparison code.
1522 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1523 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1524 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1526 !strconcat("vpcmp", Suffix,
1527 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1528 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1529 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1530 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1531 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1532 _.ScalarMemOp:$src2, u8imm:$cc),
1533 !strconcat("vpcmp", Suffix,
1534 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1535 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1536 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1540 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1541 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1542 let Predicates = [prd] in
1543 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1545 let Predicates = [prd, HasVLX] in {
1546 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1547 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1551 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1552 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1553 let Predicates = [prd] in
1554 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1557 let Predicates = [prd, HasVLX] in {
1558 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1560 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1565 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1566 HasBWI>, EVEX_CD8<8, CD8VF>;
1567 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1568 HasBWI>, EVEX_CD8<8, CD8VF>;
1570 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1571 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1572 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1573 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1575 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1576 HasAVX512>, EVEX_CD8<32, CD8VF>;
1577 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1578 HasAVX512>, EVEX_CD8<32, CD8VF>;
1580 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1581 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1582 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1583 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1585 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1587 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1588 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1589 "vcmp${cc}"#_.Suffix,
1590 "$src2, $src1", "$src1, $src2",
1591 (X86cmpm (_.VT _.RC:$src1),
1595 let mayLoad = 1 in {
1596 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1597 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1598 "vcmp${cc}"#_.Suffix,
1599 "$src2, $src1", "$src1, $src2",
1600 (X86cmpm (_.VT _.RC:$src1),
1601 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1604 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1606 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1607 "vcmp${cc}"#_.Suffix,
1608 "${src2}"##_.BroadcastStr##", $src1",
1609 "$src1, ${src2}"##_.BroadcastStr,
1610 (X86cmpm (_.VT _.RC:$src1),
1611 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1614 // Accept explicit immediate argument form instead of comparison code.
1615 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1616 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1618 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1620 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1622 let mayLoad = 1 in {
1623 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1625 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1627 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1629 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1631 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1633 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1634 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1639 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1640 // comparison code form (VCMP[EQ/LT/LE/...]
1641 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1642 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1643 "vcmp${cc}"#_.Suffix,
1644 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1645 (X86cmpmRnd (_.VT _.RC:$src1),
1648 (i32 FROUND_NO_EXC))>, EVEX_B;
1650 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1651 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1653 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1655 "$cc,{sae}, $src2, $src1",
1656 "$src1, $src2,{sae}, $cc">, EVEX_B;
1660 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1661 let Predicates = [HasAVX512] in {
1662 defm Z : avx512_vcmp_common<_.info512>,
1663 avx512_vcmp_sae<_.info512>, EVEX_V512;
1666 let Predicates = [HasAVX512,HasVLX] in {
1667 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1668 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1672 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1673 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1674 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1675 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1677 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1678 (COPY_TO_REGCLASS (VCMPPSZrri
1679 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1680 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1682 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1683 (COPY_TO_REGCLASS (VPCMPDZrri
1684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1685 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1687 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1688 (COPY_TO_REGCLASS (VPCMPUDZrri
1689 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1690 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1693 //-----------------------------------------------------------------
1694 // Mask register copy, including
1695 // - copy between mask registers
1696 // - load/store mask registers
1697 // - copy from GPR to mask register and vice versa
1699 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1700 string OpcodeStr, RegisterClass KRC,
1701 ValueType vvt, X86MemOperand x86memop> {
1702 let hasSideEffects = 0 in {
1703 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1704 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1706 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1707 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1708 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1710 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1711 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1712 [(store KRC:$src, addr:$dst)]>;
1716 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1718 RegisterClass KRC, RegisterClass GRC> {
1719 let hasSideEffects = 0 in {
1720 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1721 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1722 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1723 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1727 let Predicates = [HasDQI] in
1728 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1729 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1732 let Predicates = [HasAVX512] in
1733 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1734 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1737 let Predicates = [HasBWI] in {
1738 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1740 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1744 let Predicates = [HasBWI] in {
1745 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1747 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1751 // GR from/to mask register
1752 let Predicates = [HasDQI] in {
1753 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1754 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1755 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1756 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1758 let Predicates = [HasAVX512] in {
1759 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1760 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1761 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1762 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1764 let Predicates = [HasBWI] in {
1765 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1766 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1768 let Predicates = [HasBWI] in {
1769 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1770 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1774 let Predicates = [HasDQI] in {
1775 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1776 (KMOVBmk addr:$dst, VK8:$src)>;
1777 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1778 (KMOVBkm addr:$src)>;
1780 let Predicates = [HasAVX512, NoDQI] in {
1781 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1782 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1783 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1784 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1786 let Predicates = [HasAVX512] in {
1787 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1788 (KMOVWmk addr:$dst, VK16:$src)>;
1789 def : Pat<(i1 (load addr:$src)),
1790 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
1791 (MOV8rm addr:$src), sub_8bit)),
1793 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1794 (KMOVWkm addr:$src)>;
1796 let Predicates = [HasBWI] in {
1797 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1798 (KMOVDmk addr:$dst, VK32:$src)>;
1799 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1800 (KMOVDkm addr:$src)>;
1802 let Predicates = [HasBWI] in {
1803 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1804 (KMOVQmk addr:$dst, VK64:$src)>;
1805 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1806 (KMOVQkm addr:$src)>;
1809 let Predicates = [HasAVX512] in {
1810 def : Pat<(i1 (trunc (i64 GR64:$src))),
1811 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1814 def : Pat<(i1 (trunc (i32 GR32:$src))),
1815 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1817 def : Pat<(i1 (trunc (i8 GR8:$src))),
1819 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1821 def : Pat<(i1 (trunc (i16 GR16:$src))),
1823 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1826 def : Pat<(i32 (zext VK1:$src)),
1827 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1828 def : Pat<(i32 (anyext VK1:$src)),
1829 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
1830 def : Pat<(i8 (zext VK1:$src)),
1833 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1834 def : Pat<(i64 (zext VK1:$src)),
1835 (AND64ri8 (SUBREG_TO_REG (i64 0),
1836 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1837 def : Pat<(i16 (zext VK1:$src)),
1839 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1841 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1842 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1843 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1844 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1846 let Predicates = [HasBWI] in {
1847 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1848 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1849 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1850 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1854 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1855 let Predicates = [HasAVX512, NoDQI] in {
1856 // GR from/to 8-bit mask without native support
1857 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1859 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
1860 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1862 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1866 let Predicates = [HasAVX512] in {
1867 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1868 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1869 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1870 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1872 let Predicates = [HasBWI] in {
1873 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1874 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1875 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1876 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1879 // Mask unary operation
1881 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1882 RegisterClass KRC, SDPatternOperator OpNode,
1884 let Predicates = [prd] in
1885 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1886 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1887 [(set KRC:$dst, (OpNode KRC:$src))]>;
1890 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1891 SDPatternOperator OpNode> {
1892 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1894 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1895 HasAVX512>, VEX, PS;
1896 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1897 HasBWI>, VEX, PD, VEX_W;
1898 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1899 HasBWI>, VEX, PS, VEX_W;
1902 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1904 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1905 let Predicates = [HasAVX512] in
1906 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1908 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1909 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1911 defm : avx512_mask_unop_int<"knot", "KNOT">;
1913 let Predicates = [HasDQI] in
1914 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1915 let Predicates = [HasAVX512] in
1916 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1917 let Predicates = [HasBWI] in
1918 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1919 let Predicates = [HasBWI] in
1920 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1922 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1923 let Predicates = [HasAVX512, NoDQI] in {
1924 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1925 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1926 def : Pat<(not VK8:$src),
1928 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1930 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
1931 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
1932 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
1933 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
1935 // Mask binary operation
1936 // - KAND, KANDN, KOR, KXNOR, KXOR
1937 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1938 RegisterClass KRC, SDPatternOperator OpNode,
1939 Predicate prd, bit IsCommutable> {
1940 let Predicates = [prd], isCommutable = IsCommutable in
1941 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1942 !strconcat(OpcodeStr,
1943 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1944 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1947 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1948 SDPatternOperator OpNode, bit IsCommutable> {
1949 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1950 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
1951 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1952 HasAVX512, IsCommutable>, VEX_4V, VEX_L, PS;
1953 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1954 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
1955 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1956 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
1959 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1960 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1962 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
1963 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
1964 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
1965 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
1966 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
1968 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1969 let Predicates = [HasAVX512] in
1970 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1971 (i16 GR16:$src1), (i16 GR16:$src2)),
1972 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1973 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1974 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1977 defm : avx512_mask_binop_int<"kand", "KAND">;
1978 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1979 defm : avx512_mask_binop_int<"kor", "KOR">;
1980 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1981 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1983 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1984 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
1985 // for the DQI set, this type is legal and KxxxB instruction is used
1986 let Predicates = [NoDQI] in
1987 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1989 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1990 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1992 // All types smaller than 8 bits require conversion anyway
1993 def : Pat<(OpNode VK1:$src1, VK1:$src2),
1994 (COPY_TO_REGCLASS (Inst
1995 (COPY_TO_REGCLASS VK1:$src1, VK16),
1996 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1997 def : Pat<(OpNode VK2:$src1, VK2:$src2),
1998 (COPY_TO_REGCLASS (Inst
1999 (COPY_TO_REGCLASS VK2:$src1, VK16),
2000 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2001 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2002 (COPY_TO_REGCLASS (Inst
2003 (COPY_TO_REGCLASS VK4:$src1, VK16),
2004 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2007 defm : avx512_binop_pat<and, KANDWrr>;
2008 defm : avx512_binop_pat<andn, KANDNWrr>;
2009 defm : avx512_binop_pat<or, KORWrr>;
2010 defm : avx512_binop_pat<xnor, KXNORWrr>;
2011 defm : avx512_binop_pat<xor, KXORWrr>;
2013 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2014 (KXNORWrr VK16:$src1, VK16:$src2)>;
2015 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2016 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2017 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2018 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2019 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2020 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2022 let Predicates = [NoDQI] in
2023 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2024 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2025 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2027 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2028 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2029 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2031 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2032 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2033 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2035 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2036 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2037 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2040 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
2041 RegisterClass KRC> {
2042 let Predicates = [HasAVX512] in
2043 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2044 !strconcat(OpcodeStr,
2045 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2048 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
2049 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
2053 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
2054 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
2055 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
2056 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
2059 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2060 let Predicates = [HasAVX512] in
2061 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2062 (i16 GR16:$src1), (i16 GR16:$src2)),
2063 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2064 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2065 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2067 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2070 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2072 let Predicates = [HasAVX512], Defs = [EFLAGS] in
2073 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2074 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2075 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2078 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2079 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2081 let Predicates = [HasDQI] in
2082 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2084 let Predicates = [HasBWI] in {
2085 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2087 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2092 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2095 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2097 let Predicates = [HasAVX512] in
2098 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2099 !strconcat(OpcodeStr,
2100 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2101 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2104 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2106 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2108 let Predicates = [HasDQI] in
2109 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2111 let Predicates = [HasBWI] in {
2112 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2114 let Predicates = [HasDQI] in
2115 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2120 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2121 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2123 // Mask setting all 0s or 1s
2124 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2125 let Predicates = [HasAVX512] in
2126 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2127 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2128 [(set KRC:$dst, (VT Val))]>;
2131 multiclass avx512_mask_setop_w<PatFrag Val> {
2132 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2133 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2134 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2135 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2138 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2139 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2141 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2142 let Predicates = [HasAVX512] in {
2143 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2144 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2145 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2146 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2147 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2148 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2149 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2151 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2152 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2154 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2155 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2157 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2158 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2160 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2161 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2163 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2164 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2166 let Predicates = [HasVLX] in {
2167 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2168 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2169 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2170 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2171 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2172 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2173 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2174 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2175 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2176 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2179 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2180 (v8i1 (COPY_TO_REGCLASS
2181 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2182 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2184 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2185 (v8i1 (COPY_TO_REGCLASS
2186 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2187 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2189 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2190 (v4i1 (COPY_TO_REGCLASS
2191 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2192 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2194 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2195 (v4i1 (COPY_TO_REGCLASS
2196 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2197 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2199 //===----------------------------------------------------------------------===//
2200 // AVX-512 - Aligned and unaligned load and store
2204 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2205 PatFrag ld_frag, PatFrag mload,
2206 bit IsReMaterializable = 1> {
2207 let hasSideEffects = 0 in {
2208 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2209 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2211 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2212 (ins _.KRCWM:$mask, _.RC:$src),
2213 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2214 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2217 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2218 SchedRW = [WriteLoad] in
2219 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2220 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2221 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2224 let Constraints = "$src0 = $dst" in {
2225 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2226 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2227 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2228 "${dst} {${mask}}, $src1}"),
2229 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2231 (_.VT _.RC:$src0))))], _.ExeDomain>,
2233 let mayLoad = 1, SchedRW = [WriteLoad] in
2234 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2235 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2236 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2237 "${dst} {${mask}}, $src1}"),
2238 [(set _.RC:$dst, (_.VT
2239 (vselect _.KRCWM:$mask,
2240 (_.VT (bitconvert (ld_frag addr:$src1))),
2241 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2243 let mayLoad = 1, SchedRW = [WriteLoad] in
2244 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2245 (ins _.KRCWM:$mask, _.MemOp:$src),
2246 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2247 "${dst} {${mask}} {z}, $src}",
2248 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2249 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2250 _.ExeDomain>, EVEX, EVEX_KZ;
2252 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2253 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2255 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2256 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2258 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2259 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2260 _.KRCWM:$mask, addr:$ptr)>;
2263 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2264 AVX512VLVectorVTInfo _,
2266 bit IsReMaterializable = 1> {
2267 let Predicates = [prd] in
2268 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2269 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2271 let Predicates = [prd, HasVLX] in {
2272 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2273 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2274 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2275 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2279 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2280 AVX512VLVectorVTInfo _,
2282 bit IsReMaterializable = 1> {
2283 let Predicates = [prd] in
2284 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2285 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2287 let Predicates = [prd, HasVLX] in {
2288 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2289 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2290 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2291 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2295 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2296 PatFrag st_frag, PatFrag mstore> {
2297 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2298 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2299 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2301 let Constraints = "$src1 = $dst" in
2302 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2303 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2305 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2306 [], _.ExeDomain>, EVEX, EVEX_K;
2307 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2308 (ins _.KRCWM:$mask, _.RC:$src),
2310 "\t{$src, ${dst} {${mask}} {z}|" #
2311 "${dst} {${mask}} {z}, $src}",
2312 [], _.ExeDomain>, EVEX, EVEX_KZ;
2314 let mayStore = 1 in {
2315 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2316 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2317 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2318 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2319 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2320 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2321 [], _.ExeDomain>, EVEX, EVEX_K;
2324 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2325 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2326 _.KRCWM:$mask, _.RC:$src)>;
2330 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2331 AVX512VLVectorVTInfo _, Predicate prd> {
2332 let Predicates = [prd] in
2333 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2334 masked_store_unaligned>, EVEX_V512;
2336 let Predicates = [prd, HasVLX] in {
2337 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2338 masked_store_unaligned>, EVEX_V256;
2339 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2340 masked_store_unaligned>, EVEX_V128;
2344 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2345 AVX512VLVectorVTInfo _, Predicate prd> {
2346 let Predicates = [prd] in
2347 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2348 masked_store_aligned512>, EVEX_V512;
2350 let Predicates = [prd, HasVLX] in {
2351 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2352 masked_store_aligned256>, EVEX_V256;
2353 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2354 masked_store_aligned128>, EVEX_V128;
2358 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2360 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2361 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2363 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2365 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2366 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2368 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2369 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2370 PS, EVEX_CD8<32, CD8VF>;
2372 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2373 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2374 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2376 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2377 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2378 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2380 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2381 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2382 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2384 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2385 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2386 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2388 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2389 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2390 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2392 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2393 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2394 (VMOVAPDZrm addr:$ptr)>;
2396 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2397 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2398 (VMOVAPSZrm addr:$ptr)>;
2400 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2402 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2404 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2406 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2409 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2411 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2413 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2415 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2418 let Predicates = [HasAVX512, NoVLX] in {
2419 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2420 (VMOVUPSZmrk addr:$ptr,
2421 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2422 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2424 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2425 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2426 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2428 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2429 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2430 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2431 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2434 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2436 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2437 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2439 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2441 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2442 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2444 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2445 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2446 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2448 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2449 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2450 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2452 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2453 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2454 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2456 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2457 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2458 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2460 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2461 (v16i32 immAllZerosV), GR16:$mask)),
2462 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2464 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2465 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2466 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2468 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2470 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2472 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2474 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2477 let AddedComplexity = 20 in {
2478 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2479 (bc_v8i64 (v16i32 immAllZerosV)))),
2480 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2482 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2483 (v8i64 VR512:$src))),
2484 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2487 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2488 (v16i32 immAllZerosV))),
2489 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2491 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2492 (v16i32 VR512:$src))),
2493 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2496 let Predicates = [HasAVX512, NoVLX] in {
2497 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2498 (VMOVDQU32Zmrk addr:$ptr,
2499 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2500 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2502 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2503 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2504 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2507 // Move Int Doubleword to Packed Double Int
2509 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2510 "vmovd\t{$src, $dst|$dst, $src}",
2512 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2514 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2515 "vmovd\t{$src, $dst|$dst, $src}",
2517 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2518 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2519 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2520 "vmovq\t{$src, $dst|$dst, $src}",
2522 (v2i64 (scalar_to_vector GR64:$src)))],
2523 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2524 let isCodeGenOnly = 1 in {
2525 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2526 "vmovq\t{$src, $dst|$dst, $src}",
2527 [(set FR64:$dst, (bitconvert GR64:$src))],
2528 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2529 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2530 "vmovq\t{$src, $dst|$dst, $src}",
2531 [(set GR64:$dst, (bitconvert FR64:$src))],
2532 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2534 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2535 "vmovq\t{$src, $dst|$dst, $src}",
2536 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2537 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2538 EVEX_CD8<64, CD8VT1>;
2540 // Move Int Doubleword to Single Scalar
2542 let isCodeGenOnly = 1 in {
2543 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2544 "vmovd\t{$src, $dst|$dst, $src}",
2545 [(set FR32X:$dst, (bitconvert GR32:$src))],
2546 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2548 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2549 "vmovd\t{$src, $dst|$dst, $src}",
2550 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2551 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2554 // Move doubleword from xmm register to r/m32
2556 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2557 "vmovd\t{$src, $dst|$dst, $src}",
2558 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2559 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2561 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2562 (ins i32mem:$dst, VR128X:$src),
2563 "vmovd\t{$src, $dst|$dst, $src}",
2564 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2565 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2566 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2568 // Move quadword from xmm1 register to r/m64
2570 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2571 "vmovq\t{$src, $dst|$dst, $src}",
2572 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2574 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2575 Requires<[HasAVX512, In64BitMode]>;
2577 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2578 (ins i64mem:$dst, VR128X:$src),
2579 "vmovq\t{$src, $dst|$dst, $src}",
2580 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2581 addr:$dst)], IIC_SSE_MOVDQ>,
2582 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2583 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2585 // Move Scalar Single to Double Int
2587 let isCodeGenOnly = 1 in {
2588 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2590 "vmovd\t{$src, $dst|$dst, $src}",
2591 [(set GR32:$dst, (bitconvert FR32X:$src))],
2592 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2593 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2594 (ins i32mem:$dst, FR32X:$src),
2595 "vmovd\t{$src, $dst|$dst, $src}",
2596 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2597 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2600 // Move Quadword Int to Packed Quadword Int
2602 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2604 "vmovq\t{$src, $dst|$dst, $src}",
2606 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2607 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2609 //===----------------------------------------------------------------------===//
2610 // AVX-512 MOVSS, MOVSD
2611 //===----------------------------------------------------------------------===//
2613 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2614 SDNode OpNode, ValueType vt,
2615 X86MemOperand x86memop, PatFrag mem_pat> {
2616 let hasSideEffects = 0 in {
2617 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2618 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2619 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2620 (scalar_to_vector RC:$src2))))],
2621 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2622 let Constraints = "$src1 = $dst" in
2623 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2624 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2626 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2627 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2628 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2629 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2630 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2632 let mayStore = 1 in {
2633 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2634 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2635 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2637 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2638 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2639 [], IIC_SSE_MOV_S_MR>,
2640 EVEX, VEX_LIG, EVEX_K;
2642 } //hasSideEffects = 0
2645 let ExeDomain = SSEPackedSingle in
2646 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2647 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2649 let ExeDomain = SSEPackedDouble in
2650 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2651 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2653 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2654 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2655 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2657 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2658 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2659 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2661 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2662 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2663 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2665 // For the disassembler
2666 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2667 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2668 (ins VR128X:$src1, FR32X:$src2),
2669 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2671 XS, EVEX_4V, VEX_LIG;
2672 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2673 (ins VR128X:$src1, FR64X:$src2),
2674 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2676 XD, EVEX_4V, VEX_LIG, VEX_W;
2679 let Predicates = [HasAVX512] in {
2680 let AddedComplexity = 15 in {
2681 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2682 // MOVS{S,D} to the lower bits.
2683 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2684 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2685 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2686 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2687 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2688 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2689 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2690 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2692 // Move low f32 and clear high bits.
2693 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2694 (SUBREG_TO_REG (i32 0),
2695 (VMOVSSZrr (v4f32 (V_SET0)),
2696 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2697 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2698 (SUBREG_TO_REG (i32 0),
2699 (VMOVSSZrr (v4i32 (V_SET0)),
2700 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2703 let AddedComplexity = 20 in {
2704 // MOVSSrm zeros the high parts of the register; represent this
2705 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2706 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2707 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2708 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2709 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2710 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2711 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2713 // MOVSDrm zeros the high parts of the register; represent this
2714 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2715 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2716 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2717 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2718 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2719 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2720 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2721 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2722 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2723 def : Pat<(v2f64 (X86vzload addr:$src)),
2724 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2726 // Represent the same patterns above but in the form they appear for
2728 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2729 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2730 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2731 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2732 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2733 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2734 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2735 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2736 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2738 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2739 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2740 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2741 FR32X:$src)), sub_xmm)>;
2742 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2743 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2744 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2745 FR64X:$src)), sub_xmm)>;
2746 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2747 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2748 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2750 // Move low f64 and clear high bits.
2751 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2752 (SUBREG_TO_REG (i32 0),
2753 (VMOVSDZrr (v2f64 (V_SET0)),
2754 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2756 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2757 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2758 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2760 // Extract and store.
2761 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2763 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2764 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2766 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2768 // Shuffle with VMOVSS
2769 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2770 (VMOVSSZrr (v4i32 VR128X:$src1),
2771 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2772 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2773 (VMOVSSZrr (v4f32 VR128X:$src1),
2774 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2777 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2778 (SUBREG_TO_REG (i32 0),
2779 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2780 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2782 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2783 (SUBREG_TO_REG (i32 0),
2784 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2785 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2788 // Shuffle with VMOVSD
2789 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2790 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2791 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2792 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2793 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2794 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2795 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2796 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2799 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2800 (SUBREG_TO_REG (i32 0),
2801 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2802 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2804 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2805 (SUBREG_TO_REG (i32 0),
2806 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2807 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2810 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2811 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2812 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2813 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2814 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2815 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2816 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2817 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2820 let AddedComplexity = 15 in
2821 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2823 "vmovq\t{$src, $dst|$dst, $src}",
2824 [(set VR128X:$dst, (v2i64 (X86vzmovl
2825 (v2i64 VR128X:$src))))],
2826 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2828 let AddedComplexity = 20 in
2829 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2831 "vmovq\t{$src, $dst|$dst, $src}",
2832 [(set VR128X:$dst, (v2i64 (X86vzmovl
2833 (loadv2i64 addr:$src))))],
2834 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2835 EVEX_CD8<8, CD8VT8>;
2837 let Predicates = [HasAVX512] in {
2838 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2839 let AddedComplexity = 20 in {
2840 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2841 (VMOVDI2PDIZrm addr:$src)>;
2842 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2843 (VMOV64toPQIZrr GR64:$src)>;
2844 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2845 (VMOVDI2PDIZrr GR32:$src)>;
2847 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2848 (VMOVDI2PDIZrm addr:$src)>;
2849 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2850 (VMOVDI2PDIZrm addr:$src)>;
2851 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2852 (VMOVZPQILo2PQIZrm addr:$src)>;
2853 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2854 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2855 def : Pat<(v2i64 (X86vzload addr:$src)),
2856 (VMOVZPQILo2PQIZrm addr:$src)>;
2859 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2860 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2861 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2862 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2863 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2864 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2865 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2868 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2869 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2871 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2872 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2874 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2875 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2877 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2878 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2880 //===----------------------------------------------------------------------===//
2881 // AVX-512 - Non-temporals
2882 //===----------------------------------------------------------------------===//
2883 let SchedRW = [WriteLoad] in {
2884 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2885 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2886 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2887 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2888 EVEX_CD8<64, CD8VF>;
2890 let Predicates = [HasAVX512, HasVLX] in {
2891 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2893 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2894 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2895 EVEX_CD8<64, CD8VF>;
2897 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2899 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2900 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2901 EVEX_CD8<64, CD8VF>;
2905 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2906 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2907 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2908 let SchedRW = [WriteStore], mayStore = 1,
2909 AddedComplexity = 400 in
2910 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2911 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2912 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2915 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2916 string elty, string elsz, string vsz512,
2917 string vsz256, string vsz128, Domain d,
2918 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2919 let Predicates = [prd] in
2920 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2921 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2922 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2925 let Predicates = [prd, HasVLX] in {
2926 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2927 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2928 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2931 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2932 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2933 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2938 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2939 "i", "64", "8", "4", "2", SSEPackedInt,
2940 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2942 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2943 "f", "64", "8", "4", "2", SSEPackedDouble,
2944 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2946 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2947 "f", "32", "16", "8", "4", SSEPackedSingle,
2948 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2950 //===----------------------------------------------------------------------===//
2951 // AVX-512 - Integer arithmetic
2953 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2954 X86VectorVTInfo _, OpndItins itins,
2955 bit IsCommutable = 0> {
2956 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2957 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2958 "$src2, $src1", "$src1, $src2",
2959 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2960 itins.rr, IsCommutable>,
2961 AVX512BIBase, EVEX_4V;
2964 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2965 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2966 "$src2, $src1", "$src1, $src2",
2967 (_.VT (OpNode _.RC:$src1,
2968 (bitconvert (_.LdFrag addr:$src2)))),
2970 AVX512BIBase, EVEX_4V;
2973 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2974 X86VectorVTInfo _, OpndItins itins,
2975 bit IsCommutable = 0> :
2976 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2978 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2979 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2980 "${src2}"##_.BroadcastStr##", $src1",
2981 "$src1, ${src2}"##_.BroadcastStr,
2982 (_.VT (OpNode _.RC:$src1,
2984 (_.ScalarLdFrag addr:$src2)))),
2986 AVX512BIBase, EVEX_4V, EVEX_B;
2989 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2990 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2991 Predicate prd, bit IsCommutable = 0> {
2992 let Predicates = [prd] in
2993 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2994 IsCommutable>, EVEX_V512;
2996 let Predicates = [prd, HasVLX] in {
2997 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2998 IsCommutable>, EVEX_V256;
2999 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3000 IsCommutable>, EVEX_V128;
3004 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3005 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3006 Predicate prd, bit IsCommutable = 0> {
3007 let Predicates = [prd] in
3008 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3009 IsCommutable>, EVEX_V512;
3011 let Predicates = [prd, HasVLX] in {
3012 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3013 IsCommutable>, EVEX_V256;
3014 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3015 IsCommutable>, EVEX_V128;
3019 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3020 OpndItins itins, Predicate prd,
3021 bit IsCommutable = 0> {
3022 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3023 itins, prd, IsCommutable>,
3024 VEX_W, EVEX_CD8<64, CD8VF>;
3027 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3028 OpndItins itins, Predicate prd,
3029 bit IsCommutable = 0> {
3030 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3031 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3034 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3035 OpndItins itins, Predicate prd,
3036 bit IsCommutable = 0> {
3037 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3038 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3041 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3042 OpndItins itins, Predicate prd,
3043 bit IsCommutable = 0> {
3044 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3045 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3048 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3049 SDNode OpNode, OpndItins itins, Predicate prd,
3050 bit IsCommutable = 0> {
3051 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
3054 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
3058 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3059 SDNode OpNode, OpndItins itins, Predicate prd,
3060 bit IsCommutable = 0> {
3061 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
3064 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
3068 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3069 bits<8> opc_d, bits<8> opc_q,
3070 string OpcodeStr, SDNode OpNode,
3071 OpndItins itins, bit IsCommutable = 0> {
3072 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3073 itins, HasAVX512, IsCommutable>,
3074 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3075 itins, HasBWI, IsCommutable>;
3078 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3079 SDNode OpNode,X86VectorVTInfo _Src,
3080 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3081 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3082 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3083 "$src2, $src1","$src1, $src2",
3085 (_Src.VT _Src.RC:$src1),
3086 (_Src.VT _Src.RC:$src2))),
3087 itins.rr, IsCommutable>,
3088 AVX512BIBase, EVEX_4V;
3089 let mayLoad = 1 in {
3090 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3091 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3092 "$src2, $src1", "$src1, $src2",
3093 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3094 (bitconvert (_Src.LdFrag addr:$src2)))),
3096 AVX512BIBase, EVEX_4V;
3098 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3099 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3101 "${src2}"##_Dst.BroadcastStr##", $src1",
3102 "$src1, ${src2}"##_Dst.BroadcastStr,
3103 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3104 (_Dst.VT (X86VBroadcast
3105 (_Dst.ScalarLdFrag addr:$src2)))))),
3107 AVX512BIBase, EVEX_4V, EVEX_B;
3111 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3112 SSE_INTALU_ITINS_P, 1>;
3113 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3114 SSE_INTALU_ITINS_P, 0>;
3115 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3116 SSE_INTALU_ITINS_P, HasBWI, 1>;
3117 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3118 SSE_INTALU_ITINS_P, HasBWI, 0>;
3119 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3120 SSE_INTALU_ITINS_P, HasBWI, 1>;
3121 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3122 SSE_INTALU_ITINS_P, HasBWI, 0>;
3123 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3124 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3125 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3126 SSE_INTALU_ITINS_P, HasBWI, 1>;
3127 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3128 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3129 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3130 SSE_INTALU_ITINS_P, HasBWI, 1>;
3132 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3133 SDNode OpNode, bit IsCommutable = 0> {
3135 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3136 v16i32_info, v8i64_info, IsCommutable>,
3137 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3138 let Predicates = [HasVLX] in {
3139 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3140 v8i32x_info, v4i64x_info, IsCommutable>,
3141 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3142 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3143 v4i32x_info, v2i64x_info, IsCommutable>,
3144 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3148 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3150 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3153 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3154 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3155 let mayLoad = 1 in {
3156 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3157 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3159 "${src2}"##_Src.BroadcastStr##", $src1",
3160 "$src1, ${src2}"##_Src.BroadcastStr,
3161 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3162 (_Src.VT (X86VBroadcast
3163 (_Src.ScalarLdFrag addr:$src2))))))>,
3164 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3168 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3169 SDNode OpNode,X86VectorVTInfo _Src,
3170 X86VectorVTInfo _Dst> {
3171 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3172 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3173 "$src2, $src1","$src1, $src2",
3175 (_Src.VT _Src.RC:$src1),
3176 (_Src.VT _Src.RC:$src2)))>,
3177 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3178 let mayLoad = 1 in {
3179 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3180 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3181 "$src2, $src1", "$src1, $src2",
3182 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3183 (bitconvert (_Src.LdFrag addr:$src2))))>,
3184 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3188 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3190 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3192 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3193 v32i16_info>, EVEX_V512;
3194 let Predicates = [HasVLX] in {
3195 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3197 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3198 v16i16x_info>, EVEX_V256;
3199 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3201 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3202 v8i16x_info>, EVEX_V128;
3205 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3207 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3208 v64i8_info>, EVEX_V512;
3209 let Predicates = [HasVLX] in {
3210 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3211 v32i8x_info>, EVEX_V256;
3212 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3213 v16i8x_info>, EVEX_V128;
3216 let Predicates = [HasBWI] in {
3217 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3218 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3219 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3220 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3223 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3224 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3225 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3226 SSE_INTALU_ITINS_P, HasBWI, 1>;
3227 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3228 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3230 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3231 SSE_INTALU_ITINS_P, HasBWI, 1>;
3232 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3233 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3234 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3235 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3237 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3238 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3239 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3240 SSE_INTALU_ITINS_P, HasBWI, 1>;
3241 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3242 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3244 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3245 SSE_INTALU_ITINS_P, HasBWI, 1>;
3246 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3247 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3248 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3249 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3251 //===----------------------------------------------------------------------===//
3252 // AVX-512 - Unpack Instructions
3253 //===----------------------------------------------------------------------===//
3255 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3256 PatFrag mem_frag, RegisterClass RC,
3257 X86MemOperand x86memop, string asm,
3259 def rr : AVX512PI<opc, MRMSrcReg,
3260 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3262 (vt (OpNode RC:$src1, RC:$src2)))],
3264 def rm : AVX512PI<opc, MRMSrcMem,
3265 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3267 (vt (OpNode RC:$src1,
3268 (bitconvert (mem_frag addr:$src2)))))],
3272 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3273 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3274 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3275 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3276 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3277 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3278 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3279 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3280 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3281 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3282 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3283 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3285 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3286 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3287 X86MemOperand x86memop> {
3288 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3289 (ins RC:$src1, RC:$src2),
3290 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3291 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3292 IIC_SSE_UNPCK>, EVEX_4V;
3293 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3294 (ins RC:$src1, x86memop:$src2),
3295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3296 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3297 (bitconvert (memop_frag addr:$src2)))))],
3298 IIC_SSE_UNPCK>, EVEX_4V;
3300 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3301 VR512, loadv16i32, i512mem>, EVEX_V512,
3302 EVEX_CD8<32, CD8VF>;
3303 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3304 VR512, loadv8i64, i512mem>, EVEX_V512,
3305 VEX_W, EVEX_CD8<64, CD8VF>;
3306 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3307 VR512, loadv16i32, i512mem>, EVEX_V512,
3308 EVEX_CD8<32, CD8VF>;
3309 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3310 VR512, loadv8i64, i512mem>, EVEX_V512,
3311 VEX_W, EVEX_CD8<64, CD8VF>;
3312 //===----------------------------------------------------------------------===//
3313 // AVX-512 Logical Instructions
3314 //===----------------------------------------------------------------------===//
3316 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3317 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3318 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3319 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3320 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3321 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3322 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3323 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3325 //===----------------------------------------------------------------------===//
3326 // AVX-512 FP arithmetic
3327 //===----------------------------------------------------------------------===//
3328 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3329 SDNode OpNode, SDNode VecNode, OpndItins itins,
3332 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3333 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3334 "$src2, $src1", "$src1, $src2",
3335 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3336 (i32 FROUND_CURRENT)),
3337 itins.rr, IsCommutable>;
3339 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3340 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3341 "$src2, $src1", "$src1, $src2",
3342 (VecNode (_.VT _.RC:$src1),
3343 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3344 (i32 FROUND_CURRENT)),
3345 itins.rm, IsCommutable>;
3346 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3347 Predicates = [HasAVX512] in {
3348 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3349 (ins _.FRC:$src1, _.FRC:$src2),
3350 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3351 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3353 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3354 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3355 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3356 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3357 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3361 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3362 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3364 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3365 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3366 "$rc, $src2, $src1", "$src1, $src2, $rc",
3367 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3368 (i32 imm:$rc)), itins.rr, IsCommutable>,
3371 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3372 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3374 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3375 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3376 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3377 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3378 (i32 FROUND_NO_EXC))>, EVEX_B;
3381 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3383 SizeItins itins, bit IsCommutable> {
3384 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3385 itins.s, IsCommutable>,
3386 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3387 itins.s, IsCommutable>,
3388 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3389 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3390 itins.d, IsCommutable>,
3391 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3392 itins.d, IsCommutable>,
3393 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3396 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3398 SizeItins itins, bit IsCommutable> {
3399 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3400 itins.s, IsCommutable>,
3401 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3402 itins.s, IsCommutable>,
3403 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3404 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3405 itins.d, IsCommutable>,
3406 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3407 itins.d, IsCommutable>,
3408 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3410 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3411 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3412 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3413 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3414 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3415 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3417 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3418 X86VectorVTInfo _, bit IsCommutable> {
3419 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3420 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3421 "$src2, $src1", "$src1, $src2",
3422 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3423 let mayLoad = 1 in {
3424 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3425 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3426 "$src2, $src1", "$src1, $src2",
3427 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3428 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3429 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3430 "${src2}"##_.BroadcastStr##", $src1",
3431 "$src1, ${src2}"##_.BroadcastStr,
3432 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3433 (_.ScalarLdFrag addr:$src2))))>,
3438 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3439 X86VectorVTInfo _, bit IsCommutable> {
3440 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3441 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3442 "$rc, $src2, $src1", "$src1, $src2, $rc",
3443 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3444 EVEX_4V, EVEX_B, EVEX_RC;
3448 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3449 X86VectorVTInfo _, bit IsCommutable> {
3450 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3451 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3452 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3453 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3457 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3458 bit IsCommutable = 0> {
3459 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3460 IsCommutable>, EVEX_V512, PS,
3461 EVEX_CD8<32, CD8VF>;
3462 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3463 IsCommutable>, EVEX_V512, PD, VEX_W,
3464 EVEX_CD8<64, CD8VF>;
3466 // Define only if AVX512VL feature is present.
3467 let Predicates = [HasVLX] in {
3468 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3469 IsCommutable>, EVEX_V128, PS,
3470 EVEX_CD8<32, CD8VF>;
3471 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3472 IsCommutable>, EVEX_V256, PS,
3473 EVEX_CD8<32, CD8VF>;
3474 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3475 IsCommutable>, EVEX_V128, PD, VEX_W,
3476 EVEX_CD8<64, CD8VF>;
3477 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3478 IsCommutable>, EVEX_V256, PD, VEX_W,
3479 EVEX_CD8<64, CD8VF>;
3483 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3484 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3485 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3486 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3487 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3490 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3491 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3492 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3493 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3494 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3497 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3498 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3499 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3500 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3501 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3502 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3503 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3504 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3505 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3506 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3507 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3508 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3509 let Predicates = [HasDQI] in {
3510 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3511 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3512 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3513 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3516 //===----------------------------------------------------------------------===//
3517 // AVX-512 VPTESTM instructions
3518 //===----------------------------------------------------------------------===//
3520 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3521 X86VectorVTInfo _> {
3522 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3523 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3524 "$src2, $src1", "$src1, $src2",
3525 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3528 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3529 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3530 "$src2, $src1", "$src1, $src2",
3531 (OpNode (_.VT _.RC:$src1),
3532 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3534 EVEX_CD8<_.EltSize, CD8VF>;
3537 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3538 X86VectorVTInfo _> {
3540 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3541 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3542 "${src2}"##_.BroadcastStr##", $src1",
3543 "$src1, ${src2}"##_.BroadcastStr,
3544 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3545 (_.ScalarLdFrag addr:$src2))))>,
3546 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3548 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3549 AVX512VLVectorVTInfo _> {
3550 let Predicates = [HasAVX512] in
3551 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3552 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3554 let Predicates = [HasAVX512, HasVLX] in {
3555 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3556 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3557 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3558 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3562 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3563 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3565 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3566 avx512vl_i64_info>, VEX_W;
3569 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3571 let Predicates = [HasBWI] in {
3572 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3574 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3577 let Predicates = [HasVLX, HasBWI] in {
3579 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3581 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3583 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3585 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3590 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3592 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3593 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3595 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3596 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3598 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3599 (v16i32 VR512:$src2), (i16 -1))),
3600 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3602 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3603 (v8i64 VR512:$src2), (i8 -1))),
3604 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3606 //===----------------------------------------------------------------------===//
3607 // AVX-512 Shift instructions
3608 //===----------------------------------------------------------------------===//
3609 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3610 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3611 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3612 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3613 "$src2, $src1", "$src1, $src2",
3614 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3615 SSE_INTSHIFT_ITINS_P.rr>;
3617 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3618 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3619 "$src2, $src1", "$src1, $src2",
3620 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3622 SSE_INTSHIFT_ITINS_P.rm>;
3625 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3626 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3628 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3629 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3630 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3631 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3632 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3635 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3636 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3637 // src2 is always 128-bit
3638 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3639 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3640 "$src2, $src1", "$src1, $src2",
3641 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3642 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3643 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3644 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3645 "$src2, $src1", "$src1, $src2",
3646 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3647 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3651 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3652 ValueType SrcVT, PatFrag bc_frag,
3653 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3654 let Predicates = [prd] in
3655 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3656 VTInfo.info512>, EVEX_V512,
3657 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3658 let Predicates = [prd, HasVLX] in {
3659 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3660 VTInfo.info256>, EVEX_V256,
3661 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3662 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3663 VTInfo.info128>, EVEX_V128,
3664 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3668 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3669 string OpcodeStr, SDNode OpNode> {
3670 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3671 avx512vl_i32_info, HasAVX512>;
3672 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3673 avx512vl_i64_info, HasAVX512>, VEX_W;
3674 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3675 avx512vl_i16_info, HasBWI>;
3678 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3679 string OpcodeStr, SDNode OpNode,
3680 AVX512VLVectorVTInfo VTInfo> {
3681 let Predicates = [HasAVX512] in
3682 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3684 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3685 VTInfo.info512>, EVEX_V512;
3686 let Predicates = [HasAVX512, HasVLX] in {
3687 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3689 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3690 VTInfo.info256>, EVEX_V256;
3691 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3693 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3694 VTInfo.info128>, EVEX_V128;
3698 multiclass avx512_shift_rmi_w<bits<8> opcw,
3699 Format ImmFormR, Format ImmFormM,
3700 string OpcodeStr, SDNode OpNode> {
3701 let Predicates = [HasBWI] in
3702 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3703 v32i16_info>, EVEX_V512;
3704 let Predicates = [HasVLX, HasBWI] in {
3705 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3706 v16i16x_info>, EVEX_V256;
3707 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3708 v8i16x_info>, EVEX_V128;
3712 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3713 Format ImmFormR, Format ImmFormM,
3714 string OpcodeStr, SDNode OpNode> {
3715 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3716 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3717 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3718 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3721 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3722 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3724 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3725 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3727 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3728 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
3730 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
3731 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
3733 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3734 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3735 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3737 //===-------------------------------------------------------------------===//
3738 // Variable Bit Shifts
3739 //===-------------------------------------------------------------------===//
3740 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3741 X86VectorVTInfo _> {
3742 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3743 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3744 "$src2, $src1", "$src1, $src2",
3745 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3746 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3748 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3749 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3750 "$src2, $src1", "$src1, $src2",
3751 (_.VT (OpNode _.RC:$src1,
3752 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
3753 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3754 EVEX_CD8<_.EltSize, CD8VF>;
3757 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3758 X86VectorVTInfo _> {
3760 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3761 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3762 "${src2}"##_.BroadcastStr##", $src1",
3763 "$src1, ${src2}"##_.BroadcastStr,
3764 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3765 (_.ScalarLdFrag addr:$src2))))),
3766 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3767 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3769 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3770 AVX512VLVectorVTInfo _> {
3771 let Predicates = [HasAVX512] in
3772 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3773 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3775 let Predicates = [HasAVX512, HasVLX] in {
3776 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3777 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3778 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3779 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3783 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3785 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3787 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3788 avx512vl_i64_info>, VEX_W;
3791 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3793 let Predicates = [HasBWI] in
3794 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3796 let Predicates = [HasVLX, HasBWI] in {
3798 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3800 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3805 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3806 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3807 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3808 avx512_var_shift_w<0x11, "vpsravw", sra>;
3809 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3810 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3811 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3812 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3814 //===-------------------------------------------------------------------===//
3815 // 1-src variable permutation VPERMW/D/Q
3816 //===-------------------------------------------------------------------===//
3817 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3818 AVX512VLVectorVTInfo _> {
3819 let Predicates = [HasAVX512] in
3820 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3821 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3823 let Predicates = [HasAVX512, HasVLX] in
3824 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3825 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3828 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3829 string OpcodeStr, SDNode OpNode,
3830 AVX512VLVectorVTInfo VTInfo> {
3831 let Predicates = [HasAVX512] in
3832 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3834 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3835 VTInfo.info512>, EVEX_V512;
3836 let Predicates = [HasAVX512, HasVLX] in
3837 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3839 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3840 VTInfo.info256>, EVEX_V256;
3844 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
3846 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
3848 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
3849 avx512vl_i64_info>, VEX_W;
3850 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
3852 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
3853 avx512vl_f64_info>, VEX_W;
3855 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
3856 X86VPermi, avx512vl_i64_info>,
3857 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3858 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
3859 X86VPermi, avx512vl_f64_info>,
3860 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3862 //===----------------------------------------------------------------------===//
3863 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
3864 //===----------------------------------------------------------------------===//
3866 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
3867 X86PShufd, avx512vl_i32_info>,
3868 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
3869 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
3870 X86PShufhw>, EVEX, AVX512XSIi8Base, VEX_W;
3871 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
3872 X86PShuflw>, EVEX, AVX512XDIi8Base, VEX_W;
3874 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3875 let Predicates = [HasBWI] in
3876 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
3878 let Predicates = [HasVLX, HasBWI] in {
3879 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
3880 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
3884 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
3886 //===----------------------------------------------------------------------===//
3887 // AVX-512 - MOVDDUP
3888 //===----------------------------------------------------------------------===//
3890 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3891 X86MemOperand x86memop, PatFrag memop_frag> {
3892 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3893 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3894 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3895 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3896 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3898 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3901 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3902 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3903 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3904 (VMOVDDUPZrm addr:$src)>;
3906 //===---------------------------------------------------------------------===//
3907 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3908 //===---------------------------------------------------------------------===//
3909 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3910 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3911 X86MemOperand x86memop> {
3912 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3913 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3914 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3916 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3917 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3918 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3921 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3922 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3923 EVEX_CD8<32, CD8VF>;
3924 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3925 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3926 EVEX_CD8<32, CD8VF>;
3928 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3929 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3930 (VMOVSHDUPZrm addr:$src)>;
3931 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3932 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3933 (VMOVSLDUPZrm addr:$src)>;
3935 //===----------------------------------------------------------------------===//
3936 // Move Low to High and High to Low packed FP Instructions
3937 //===----------------------------------------------------------------------===//
3938 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3939 (ins VR128X:$src1, VR128X:$src2),
3940 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3941 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3942 IIC_SSE_MOV_LH>, EVEX_4V;
3943 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3944 (ins VR128X:$src1, VR128X:$src2),
3945 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3946 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3947 IIC_SSE_MOV_LH>, EVEX_4V;
3949 let Predicates = [HasAVX512] in {
3951 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3952 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3953 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3954 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3957 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3958 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3961 //===----------------------------------------------------------------------===//
3962 // FMA - Fused Multiply Operations
3965 let Constraints = "$src1 = $dst" in {
3966 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3967 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3968 SDPatternOperator OpNode = null_frag> {
3969 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3970 (ins _.RC:$src2, _.RC:$src3),
3971 OpcodeStr, "$src3, $src2", "$src2, $src3",
3972 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3976 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3977 (ins _.RC:$src2, _.MemOp:$src3),
3978 OpcodeStr, "$src3, $src2", "$src2, $src3",
3979 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3982 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3983 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3984 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
3985 !strconcat("$src2, ${src3}", _.BroadcastStr ),
3987 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3988 AVX512FMA3Base, EVEX_B;
3990 } // Constraints = "$src1 = $dst"
3992 let Constraints = "$src1 = $dst" in {
3993 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3994 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr,
3996 SDPatternOperator OpNode> {
3997 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3998 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
3999 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4000 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4001 AVX512FMA3Base, EVEX_B, EVEX_RC;
4003 } // Constraints = "$src1 = $dst"
4005 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
4006 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
4007 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
4008 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
4011 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
4012 string OpcodeStr, X86VectorVTInfo VTI,
4013 SDPatternOperator OpNode> {
4014 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
4015 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
4016 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
4017 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
4020 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
4022 SDPatternOperator OpNode,
4023 SDPatternOperator OpNodeRnd> {
4024 let ExeDomain = SSEPackedSingle in {
4025 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4026 v16f32_info, OpNode>,
4027 avx512_fma3_round_forms<opc213, OpcodeStr,
4028 v16f32_info, OpNodeRnd>, EVEX_V512;
4029 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4030 v8f32x_info, OpNode>, EVEX_V256;
4031 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4032 v4f32x_info, OpNode>, EVEX_V128;
4034 let ExeDomain = SSEPackedDouble in {
4035 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4036 v8f64_info, OpNode>,
4037 avx512_fma3_round_forms<opc213, OpcodeStr, v8f64_info,
4038 OpNodeRnd>, EVEX_V512, VEX_W;
4039 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4040 v4f64x_info, OpNode>,
4042 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4043 v2f64x_info, OpNode>,
4048 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
4049 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
4050 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
4051 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
4052 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4053 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4055 let Constraints = "$src1 = $dst" in {
4056 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
4057 X86VectorVTInfo _> {
4059 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4060 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
4061 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
4062 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
4064 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4065 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
4066 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
4067 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
4069 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4070 (_.ScalarLdFrag addr:$src2))),
4071 _.RC:$src3))]>, EVEX_B;
4073 } // Constraints = "$src1 = $dst"
4075 multiclass avx512_fma3p_m132_f<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4077 let ExeDomain = SSEPackedSingle in {
4078 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
4079 OpNode,v16f32_info>, EVEX_V512,
4080 EVEX_CD8<32, CD8VF>;
4081 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4082 OpNode, v8f32x_info>, EVEX_V256,
4083 EVEX_CD8<32, CD8VF>;
4084 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4085 OpNode, v4f32x_info>, EVEX_V128,
4086 EVEX_CD8<32, CD8VF>;
4088 let ExeDomain = SSEPackedDouble in {
4089 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
4090 OpNode, v8f64_info>, EVEX_V512,
4091 VEX_W, EVEX_CD8<32, CD8VF>;
4092 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4093 OpNode, v4f64x_info>, EVEX_V256,
4094 VEX_W, EVEX_CD8<32, CD8VF>;
4095 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4096 OpNode, v2f64x_info>, EVEX_V128,
4097 VEX_W, EVEX_CD8<32, CD8VF>;
4101 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
4102 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
4103 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
4104 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
4105 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
4106 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
4109 let Constraints = "$src1 = $dst" in {
4110 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4111 RegisterClass RC, ValueType OpVT,
4112 X86MemOperand x86memop, Operand memop,
4114 let isCommutable = 1 in
4115 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
4116 (ins RC:$src1, RC:$src2, RC:$src3),
4117 !strconcat(OpcodeStr,
4118 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4120 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
4122 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
4123 (ins RC:$src1, RC:$src2, f128mem:$src3),
4124 !strconcat(OpcodeStr,
4125 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4127 (OpVT (OpNode RC:$src2, RC:$src1,
4128 (mem_frag addr:$src3))))]>;
4130 } // Constraints = "$src1 = $dst"
4132 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
4133 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4134 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
4135 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4136 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
4137 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4138 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
4139 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4140 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
4141 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4142 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
4143 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4144 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
4145 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4146 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
4147 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4149 //===----------------------------------------------------------------------===//
4150 // AVX-512 Scalar convert from sign integer to float/double
4151 //===----------------------------------------------------------------------===//
4153 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4154 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4155 PatFrag ld_frag, string asm> {
4156 let hasSideEffects = 0 in {
4157 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4158 (ins DstVT.FRC:$src1, SrcRC:$src),
4159 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4162 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4163 (ins DstVT.FRC:$src1, x86memop:$src),
4164 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4166 } // hasSideEffects = 0
4167 let isCodeGenOnly = 1 in {
4168 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4169 (ins DstVT.RC:$src1, SrcRC:$src2),
4170 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4171 [(set DstVT.RC:$dst,
4172 (OpNode (DstVT.VT DstVT.RC:$src1),
4174 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4176 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4177 (ins DstVT.RC:$src1, x86memop:$src2),
4178 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4179 [(set DstVT.RC:$dst,
4180 (OpNode (DstVT.VT DstVT.RC:$src1),
4181 (ld_frag addr:$src2),
4182 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4183 }//isCodeGenOnly = 1
4186 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4187 X86VectorVTInfo DstVT, string asm> {
4188 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4189 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4191 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4192 [(set DstVT.RC:$dst,
4193 (OpNode (DstVT.VT DstVT.RC:$src1),
4195 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4198 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4199 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4200 PatFrag ld_frag, string asm> {
4201 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4202 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4206 let Predicates = [HasAVX512] in {
4207 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4208 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4209 XS, EVEX_CD8<32, CD8VT1>;
4210 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4211 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4212 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4213 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4214 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4215 XD, EVEX_CD8<32, CD8VT1>;
4216 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4217 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4218 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4220 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4221 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4222 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4223 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4224 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4225 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4226 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4227 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4229 def : Pat<(f32 (sint_to_fp GR32:$src)),
4230 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4231 def : Pat<(f32 (sint_to_fp GR64:$src)),
4232 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4233 def : Pat<(f64 (sint_to_fp GR32:$src)),
4234 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4235 def : Pat<(f64 (sint_to_fp GR64:$src)),
4236 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4238 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR32,
4239 v4f32x_info, i32mem, loadi32,
4240 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4241 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
4242 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4243 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4244 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86SuintToFpRnd, GR32, v2f64x_info,
4245 i32mem, loadi32, "cvtusi2sd{l}">,
4246 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4247 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
4248 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4249 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4251 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4252 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4253 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4254 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4255 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4256 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4257 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4258 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4260 def : Pat<(f32 (uint_to_fp GR32:$src)),
4261 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4262 def : Pat<(f32 (uint_to_fp GR64:$src)),
4263 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4264 def : Pat<(f64 (uint_to_fp GR32:$src)),
4265 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4266 def : Pat<(f64 (uint_to_fp GR64:$src)),
4267 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4270 //===----------------------------------------------------------------------===//
4271 // AVX-512 Scalar convert from float/double to integer
4272 //===----------------------------------------------------------------------===//
4273 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4274 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
4276 let hasSideEffects = 0 in {
4277 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4278 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4279 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
4280 Requires<[HasAVX512]>;
4282 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4283 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
4284 Requires<[HasAVX512]>;
4285 } // hasSideEffects = 0
4287 let Predicates = [HasAVX512] in {
4288 // Convert float/double to signed/unsigned int 32/64
4289 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4290 ssmem, sse_load_f32, "cvtss2si">,
4291 XS, EVEX_CD8<32, CD8VT1>;
4292 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
4293 ssmem, sse_load_f32, "cvtss2si">,
4294 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4295 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
4296 ssmem, sse_load_f32, "cvtss2usi">,
4297 XS, EVEX_CD8<32, CD8VT1>;
4298 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4299 int_x86_avx512_cvtss2usi64, ssmem,
4300 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4301 EVEX_CD8<32, CD8VT1>;
4302 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4303 sdmem, sse_load_f64, "cvtsd2si">,
4304 XD, EVEX_CD8<64, CD8VT1>;
4305 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4306 sdmem, sse_load_f64, "cvtsd2si">,
4307 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4308 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4309 sdmem, sse_load_f64, "cvtsd2usi">,
4310 XD, EVEX_CD8<64, CD8VT1>;
4311 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4312 int_x86_avx512_cvtsd2usi64, sdmem,
4313 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4314 EVEX_CD8<64, CD8VT1>;
4316 let isCodeGenOnly = 1 in {
4317 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4318 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4319 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4320 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4321 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4322 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4323 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4324 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4325 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4326 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4327 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4328 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4330 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4331 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4332 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4333 } // isCodeGenOnly = 1
4335 // Convert float/double to signed/unsigned int 32/64 with truncation
4336 let isCodeGenOnly = 1 in {
4337 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4338 ssmem, sse_load_f32, "cvttss2si">,
4339 XS, EVEX_CD8<32, CD8VT1>;
4340 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4341 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4342 "cvttss2si">, XS, VEX_W,
4343 EVEX_CD8<32, CD8VT1>;
4344 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4345 sdmem, sse_load_f64, "cvttsd2si">, XD,
4346 EVEX_CD8<64, CD8VT1>;
4347 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4348 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4349 "cvttsd2si">, XD, VEX_W,
4350 EVEX_CD8<64, CD8VT1>;
4351 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4352 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4353 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4354 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4355 int_x86_avx512_cvttss2usi64, ssmem,
4356 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4357 EVEX_CD8<32, CD8VT1>;
4358 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4359 int_x86_avx512_cvttsd2usi,
4360 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4361 EVEX_CD8<64, CD8VT1>;
4362 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4363 int_x86_avx512_cvttsd2usi64, sdmem,
4364 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4365 EVEX_CD8<64, CD8VT1>;
4366 } // isCodeGenOnly = 1
4368 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4369 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4371 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4372 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4373 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4374 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4375 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4376 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4379 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4380 loadf32, "cvttss2si">, XS,
4381 EVEX_CD8<32, CD8VT1>;
4382 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4383 loadf32, "cvttss2usi">, XS,
4384 EVEX_CD8<32, CD8VT1>;
4385 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4386 loadf32, "cvttss2si">, XS, VEX_W,
4387 EVEX_CD8<32, CD8VT1>;
4388 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4389 loadf32, "cvttss2usi">, XS, VEX_W,
4390 EVEX_CD8<32, CD8VT1>;
4391 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4392 loadf64, "cvttsd2si">, XD,
4393 EVEX_CD8<64, CD8VT1>;
4394 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4395 loadf64, "cvttsd2usi">, XD,
4396 EVEX_CD8<64, CD8VT1>;
4397 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4398 loadf64, "cvttsd2si">, XD, VEX_W,
4399 EVEX_CD8<64, CD8VT1>;
4400 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4401 loadf64, "cvttsd2usi">, XD, VEX_W,
4402 EVEX_CD8<64, CD8VT1>;
4404 //===----------------------------------------------------------------------===//
4405 // AVX-512 Convert form float to double and back
4406 //===----------------------------------------------------------------------===//
4407 let hasSideEffects = 0 in {
4408 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4409 (ins FR32X:$src1, FR32X:$src2),
4410 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4411 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4413 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4414 (ins FR32X:$src1, f32mem:$src2),
4415 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4416 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4417 EVEX_CD8<32, CD8VT1>;
4419 // Convert scalar double to scalar single
4420 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4421 (ins FR64X:$src1, FR64X:$src2),
4422 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4423 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4425 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4426 (ins FR64X:$src1, f64mem:$src2),
4427 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4428 []>, EVEX_4V, VEX_LIG, VEX_W,
4429 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4432 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4433 Requires<[HasAVX512]>;
4434 def : Pat<(fextend (loadf32 addr:$src)),
4435 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4437 def : Pat<(extloadf32 addr:$src),
4438 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4439 Requires<[HasAVX512, OptForSize]>;
4441 def : Pat<(extloadf32 addr:$src),
4442 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4443 Requires<[HasAVX512, OptForSpeed]>;
4445 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4446 Requires<[HasAVX512]>;
4448 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4449 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4450 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4452 let hasSideEffects = 0 in {
4453 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4454 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4456 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4457 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4458 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4459 [], d>, EVEX, EVEX_B, EVEX_RC;
4461 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4462 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4464 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4465 } // hasSideEffects = 0
4468 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4469 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4470 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4472 let hasSideEffects = 0 in {
4473 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4474 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4476 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4478 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4479 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4481 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4482 } // hasSideEffects = 0
4485 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4486 loadv8f64, f512mem, v8f32, v8f64,
4487 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4488 EVEX_CD8<64, CD8VF>;
4490 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4491 loadv4f64, f256mem, v8f64, v8f32,
4492 SSEPackedDouble>, EVEX_V512, PS,
4493 EVEX_CD8<32, CD8VH>;
4494 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4495 (VCVTPS2PDZrm addr:$src)>;
4497 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4498 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4499 (VCVTPD2PSZrr VR512:$src)>;
4501 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4502 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4503 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4505 //===----------------------------------------------------------------------===//
4506 // AVX-512 Vector convert from sign integer to float/double
4507 //===----------------------------------------------------------------------===//
4509 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4510 loadv8i64, i512mem, v16f32, v16i32,
4511 SSEPackedSingle>, EVEX_V512, PS,
4512 EVEX_CD8<32, CD8VF>;
4514 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4515 loadv4i64, i256mem, v8f64, v8i32,
4516 SSEPackedDouble>, EVEX_V512, XS,
4517 EVEX_CD8<32, CD8VH>;
4519 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4520 loadv16f32, f512mem, v16i32, v16f32,
4521 SSEPackedSingle>, EVEX_V512, XS,
4522 EVEX_CD8<32, CD8VF>;
4524 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4525 loadv8f64, f512mem, v8i32, v8f64,
4526 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4527 EVEX_CD8<64, CD8VF>;
4529 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4530 loadv16f32, f512mem, v16i32, v16f32,
4531 SSEPackedSingle>, EVEX_V512, PS,
4532 EVEX_CD8<32, CD8VF>;
4534 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4535 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4536 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4537 (VCVTTPS2UDQZrr VR512:$src)>;
4539 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4540 loadv8f64, f512mem, v8i32, v8f64,
4541 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4542 EVEX_CD8<64, CD8VF>;
4544 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4545 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4546 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4547 (VCVTTPD2UDQZrr VR512:$src)>;
4549 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4550 loadv4i64, f256mem, v8f64, v8i32,
4551 SSEPackedDouble>, EVEX_V512, XS,
4552 EVEX_CD8<32, CD8VH>;
4554 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4555 loadv16i32, f512mem, v16f32, v16i32,
4556 SSEPackedSingle>, EVEX_V512, XD,
4557 EVEX_CD8<32, CD8VF>;
4559 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4560 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4561 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4563 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4564 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4565 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4567 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4568 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4569 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4571 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4572 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4573 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4575 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4576 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4577 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4579 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4580 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4581 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4582 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4583 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4584 (VCVTDQ2PDZrr VR256X:$src)>;
4585 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4586 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4587 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4588 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4589 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4590 (VCVTUDQ2PDZrr VR256X:$src)>;
4592 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4593 RegisterClass DstRC, PatFrag mem_frag,
4594 X86MemOperand x86memop, Domain d> {
4595 let hasSideEffects = 0 in {
4596 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4597 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4599 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4600 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4601 [], d>, EVEX, EVEX_B, EVEX_RC;
4603 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4604 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4606 } // hasSideEffects = 0
4609 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4610 loadv16f32, f512mem, SSEPackedSingle>, PD,
4611 EVEX_V512, EVEX_CD8<32, CD8VF>;
4612 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4613 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4614 EVEX_V512, EVEX_CD8<64, CD8VF>;
4616 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4617 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4618 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4620 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4621 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4622 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4624 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4625 loadv16f32, f512mem, SSEPackedSingle>,
4626 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4627 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4628 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4629 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4631 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4632 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4633 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4635 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4636 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4637 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4639 let Predicates = [HasAVX512] in {
4640 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4641 (VCVTPD2PSZrm addr:$src)>;
4642 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4643 (VCVTPS2PDZrm addr:$src)>;
4646 //===----------------------------------------------------------------------===//
4647 // Half precision conversion instructions
4648 //===----------------------------------------------------------------------===//
4649 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4650 X86MemOperand x86memop> {
4651 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4652 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4654 let hasSideEffects = 0, mayLoad = 1 in
4655 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4656 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4659 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4660 X86MemOperand x86memop> {
4661 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4662 (ins srcRC:$src1, i32u8imm:$src2),
4663 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4665 let hasSideEffects = 0, mayStore = 1 in
4666 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4667 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4668 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4671 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4672 EVEX_CD8<32, CD8VH>;
4673 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4674 EVEX_CD8<32, CD8VH>;
4676 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4677 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4678 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4680 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4681 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4682 (VCVTPH2PSZrr VR256X:$src)>;
4684 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4685 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4686 "ucomiss">, PS, EVEX, VEX_LIG,
4687 EVEX_CD8<32, CD8VT1>;
4688 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4689 "ucomisd">, PD, EVEX,
4690 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4691 let Pattern = []<dag> in {
4692 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4693 "comiss">, PS, EVEX, VEX_LIG,
4694 EVEX_CD8<32, CD8VT1>;
4695 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4696 "comisd">, PD, EVEX,
4697 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4699 let isCodeGenOnly = 1 in {
4700 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4701 load, "ucomiss">, PS, EVEX, VEX_LIG,
4702 EVEX_CD8<32, CD8VT1>;
4703 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4704 load, "ucomisd">, PD, EVEX,
4705 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4707 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4708 load, "comiss">, PS, EVEX, VEX_LIG,
4709 EVEX_CD8<32, CD8VT1>;
4710 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4711 load, "comisd">, PD, EVEX,
4712 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4716 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4717 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4718 X86MemOperand x86memop> {
4719 let hasSideEffects = 0 in {
4720 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4721 (ins RC:$src1, RC:$src2),
4722 !strconcat(OpcodeStr,
4723 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4724 let mayLoad = 1 in {
4725 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4726 (ins RC:$src1, x86memop:$src2),
4727 !strconcat(OpcodeStr,
4728 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4733 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4734 EVEX_CD8<32, CD8VT1>;
4735 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4736 VEX_W, EVEX_CD8<64, CD8VT1>;
4737 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4738 EVEX_CD8<32, CD8VT1>;
4739 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4740 VEX_W, EVEX_CD8<64, CD8VT1>;
4742 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4743 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4744 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4745 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4747 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4748 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4749 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4750 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4752 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4753 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4754 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4755 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4757 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4758 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4759 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4760 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4762 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4763 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4764 X86VectorVTInfo _> {
4765 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4766 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4767 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4768 let mayLoad = 1 in {
4769 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4770 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4772 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4773 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4774 (ins _.ScalarMemOp:$src), OpcodeStr,
4775 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4777 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4782 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4783 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4784 EVEX_V512, EVEX_CD8<32, CD8VF>;
4785 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4786 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4788 // Define only if AVX512VL feature is present.
4789 let Predicates = [HasVLX] in {
4790 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4791 OpNode, v4f32x_info>,
4792 EVEX_V128, EVEX_CD8<32, CD8VF>;
4793 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4794 OpNode, v8f32x_info>,
4795 EVEX_V256, EVEX_CD8<32, CD8VF>;
4796 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4797 OpNode, v2f64x_info>,
4798 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4799 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4800 OpNode, v4f64x_info>,
4801 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4805 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4806 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4808 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4809 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4810 (VRSQRT14PSZr VR512:$src)>;
4811 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4812 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4813 (VRSQRT14PDZr VR512:$src)>;
4815 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4816 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4817 (VRCP14PSZr VR512:$src)>;
4818 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4819 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4820 (VRCP14PDZr VR512:$src)>;
4822 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4823 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4826 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4827 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4828 "$src2, $src1", "$src1, $src2",
4829 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4830 (i32 FROUND_CURRENT))>;
4832 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4833 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4834 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4835 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4836 (i32 FROUND_NO_EXC))>, EVEX_B;
4838 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4839 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4840 "$src2, $src1", "$src1, $src2",
4841 (OpNode (_.VT _.RC:$src1),
4842 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4843 (i32 FROUND_CURRENT))>;
4846 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4847 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4848 EVEX_CD8<32, CD8VT1>;
4849 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4850 EVEX_CD8<64, CD8VT1>, VEX_W;
4853 let hasSideEffects = 0, Predicates = [HasERI] in {
4854 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4855 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4857 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4859 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4862 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4863 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4864 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4866 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4867 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4869 (bitconvert (_.LdFrag addr:$src))),
4870 (i32 FROUND_CURRENT))>;
4872 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4873 (ins _.MemOp:$src), OpcodeStr,
4874 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4876 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4877 (i32 FROUND_CURRENT))>, EVEX_B;
4879 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4881 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4882 (ins _.RC:$src), OpcodeStr,
4883 "{sae}, $src", "$src, {sae}",
4884 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
4887 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4888 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4889 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4890 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
4891 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4892 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4893 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4896 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
4898 // Define only if AVX512VL feature is present.
4899 let Predicates = [HasVLX] in {
4900 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
4901 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
4902 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
4903 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
4904 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
4905 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
4906 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
4907 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
4910 let Predicates = [HasERI], hasSideEffects = 0 in {
4912 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
4913 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
4914 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
4916 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
4917 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
4919 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
4920 SDNode OpNodeRnd, X86VectorVTInfo _>{
4921 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4922 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
4923 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
4924 EVEX, EVEX_B, EVEX_RC;
4927 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4928 SDNode OpNode, X86VectorVTInfo _>{
4929 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4930 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4931 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4932 let mayLoad = 1 in {
4933 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4934 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4936 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4938 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4939 (ins _.ScalarMemOp:$src), OpcodeStr,
4940 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4942 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4947 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4948 Intrinsic F32Int, Intrinsic F64Int,
4949 OpndItins itins_s, OpndItins itins_d> {
4950 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4951 (ins FR32X:$src1, FR32X:$src2),
4952 !strconcat(OpcodeStr,
4953 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4954 [], itins_s.rr>, XS, EVEX_4V;
4955 let isCodeGenOnly = 1 in
4956 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4957 (ins VR128X:$src1, VR128X:$src2),
4958 !strconcat(OpcodeStr,
4959 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4961 (F32Int VR128X:$src1, VR128X:$src2))],
4962 itins_s.rr>, XS, EVEX_4V;
4963 let mayLoad = 1 in {
4964 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4965 (ins FR32X:$src1, f32mem:$src2),
4966 !strconcat(OpcodeStr,
4967 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4968 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4969 let isCodeGenOnly = 1 in
4970 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4971 (ins VR128X:$src1, ssmem:$src2),
4972 !strconcat(OpcodeStr,
4973 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4975 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4976 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4978 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4979 (ins FR64X:$src1, FR64X:$src2),
4980 !strconcat(OpcodeStr,
4981 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4983 let isCodeGenOnly = 1 in
4984 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4985 (ins VR128X:$src1, VR128X:$src2),
4986 !strconcat(OpcodeStr,
4987 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4989 (F64Int VR128X:$src1, VR128X:$src2))],
4990 itins_s.rr>, XD, EVEX_4V, VEX_W;
4991 let mayLoad = 1 in {
4992 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4993 (ins FR64X:$src1, f64mem:$src2),
4994 !strconcat(OpcodeStr,
4995 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4996 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4997 let isCodeGenOnly = 1 in
4998 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4999 (ins VR128X:$src1, sdmem:$src2),
5000 !strconcat(OpcodeStr,
5001 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5003 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
5004 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
5008 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5010 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5012 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5013 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5015 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5016 // Define only if AVX512VL feature is present.
5017 let Predicates = [HasVLX] in {
5018 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5019 OpNode, v4f32x_info>,
5020 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5021 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5022 OpNode, v8f32x_info>,
5023 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5024 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5025 OpNode, v2f64x_info>,
5026 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5027 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5028 OpNode, v4f64x_info>,
5029 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5033 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5035 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5036 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5037 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5038 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5041 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5042 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5044 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
5045 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
5046 SSE_SQRTSS, SSE_SQRTSD>;
5048 let Predicates = [HasAVX512] in {
5049 def : Pat<(f32 (fsqrt FR32X:$src)),
5050 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5051 def : Pat<(f32 (fsqrt (load addr:$src))),
5052 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
5053 Requires<[OptForSize]>;
5054 def : Pat<(f64 (fsqrt FR64X:$src)),
5055 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
5056 def : Pat<(f64 (fsqrt (load addr:$src))),
5057 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
5058 Requires<[OptForSize]>;
5060 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5061 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5062 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5063 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5064 Requires<[OptForSize]>;
5066 def : Pat<(f32 (X86frcp FR32X:$src)),
5067 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5068 def : Pat<(f32 (X86frcp (load addr:$src))),
5069 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5070 Requires<[OptForSize]>;
5072 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
5073 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
5074 (COPY_TO_REGCLASS VR128X:$src, FR32)),
5076 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
5077 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
5079 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
5080 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
5081 (COPY_TO_REGCLASS VR128X:$src, FR64)),
5083 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
5084 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
5088 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
5089 X86MemOperand x86memop, RegisterClass RC,
5090 PatFrag mem_frag, Domain d> {
5091 let ExeDomain = d in {
5092 // Intrinsic operation, reg.
5093 // Vector intrinsic operation, reg
5094 def r : AVX512AIi8<opc, MRMSrcReg,
5095 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
5096 !strconcat(OpcodeStr,
5097 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5100 // Vector intrinsic operation, mem
5101 def m : AVX512AIi8<opc, MRMSrcMem,
5102 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
5103 !strconcat(OpcodeStr,
5104 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5109 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
5110 loadv16f32, SSEPackedSingle>, EVEX_V512,
5111 EVEX_CD8<32, CD8VF>;
5113 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
5114 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
5116 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
5119 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
5120 loadv8f64, SSEPackedDouble>, EVEX_V512,
5121 VEX_W, EVEX_CD8<64, CD8VF>;
5123 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
5124 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
5126 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
5129 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5131 let ExeDomain = _.ExeDomain in {
5132 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5133 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5134 "$src3, $src2, $src1", "$src1, $src2, $src3",
5135 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5136 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5138 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5139 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5140 "{sae}, $src3, $src2, $src1", "$src1, $src2, $src3, {sae}",
5141 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5142 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5145 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5146 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5147 "$src3, $src2, $src1", "$src1, $src2, $src3",
5148 (_.VT (X86RndScale (_.VT _.RC:$src1),
5149 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5150 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5152 let Predicates = [HasAVX512] in {
5153 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5154 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5155 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5156 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5157 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5158 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5159 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5160 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5161 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5162 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5163 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5164 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5165 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5166 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5167 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5169 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5170 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5171 addr:$src, (i32 0x1))), _.FRC)>;
5172 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5173 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5174 addr:$src, (i32 0x2))), _.FRC)>;
5175 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5176 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5177 addr:$src, (i32 0x3))), _.FRC)>;
5178 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5179 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5180 addr:$src, (i32 0x4))), _.FRC)>;
5181 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5182 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5183 addr:$src, (i32 0xc))), _.FRC)>;
5187 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5188 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5190 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5191 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5193 let Predicates = [HasAVX512] in {
5194 def : Pat<(v16f32 (ffloor VR512:$src)),
5195 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
5196 def : Pat<(v16f32 (fnearbyint VR512:$src)),
5197 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
5198 def : Pat<(v16f32 (fceil VR512:$src)),
5199 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
5200 def : Pat<(v16f32 (frint VR512:$src)),
5201 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
5202 def : Pat<(v16f32 (ftrunc VR512:$src)),
5203 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
5205 def : Pat<(v8f64 (ffloor VR512:$src)),
5206 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
5207 def : Pat<(v8f64 (fnearbyint VR512:$src)),
5208 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
5209 def : Pat<(v8f64 (fceil VR512:$src)),
5210 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
5211 def : Pat<(v8f64 (frint VR512:$src)),
5212 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
5213 def : Pat<(v8f64 (ftrunc VR512:$src)),
5214 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
5216 //-------------------------------------------------
5217 // Integer truncate and extend operations
5218 //-------------------------------------------------
5220 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
5221 RegisterClass dstRC, RegisterClass srcRC,
5222 RegisterClass KRC, X86MemOperand x86memop> {
5223 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5225 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5228 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5229 (ins KRC:$mask, srcRC:$src),
5230 !strconcat(OpcodeStr,
5231 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5234 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5235 (ins KRC:$mask, srcRC:$src),
5236 !strconcat(OpcodeStr,
5237 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5240 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
5241 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5244 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5245 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
5246 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
5250 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
5251 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5252 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
5253 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5254 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
5255 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5256 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
5257 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5258 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
5259 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5260 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
5261 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5262 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
5263 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5264 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
5265 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5266 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
5267 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5268 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
5269 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5270 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
5271 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5272 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
5273 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5274 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
5275 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5276 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
5277 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5278 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
5279 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5281 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
5282 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
5283 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
5284 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
5285 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
5287 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5288 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
5289 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5290 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
5291 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5292 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
5293 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5294 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
5297 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
5298 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
5299 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
5301 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
5302 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
5303 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
5306 let mayLoad = 1 in {
5307 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
5308 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
5309 (DestInfo.VT (LdFrag addr:$src))>,
5314 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
5315 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5316 let Predicates = [HasVLX, HasBWI] in {
5317 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
5318 v16i8x_info, i64mem, LdFrag, OpNode>,
5319 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
5321 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
5322 v16i8x_info, i128mem, LdFrag, OpNode>,
5323 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
5325 let Predicates = [HasBWI] in {
5326 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
5327 v32i8x_info, i256mem, LdFrag, OpNode>,
5328 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
5332 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5333 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5334 let Predicates = [HasVLX, HasAVX512] in {
5335 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5336 v16i8x_info, i32mem, LdFrag, OpNode>,
5337 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
5339 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5340 v16i8x_info, i64mem, LdFrag, OpNode>,
5341 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
5343 let Predicates = [HasAVX512] in {
5344 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5345 v16i8x_info, i128mem, LdFrag, OpNode>,
5346 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
5350 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5351 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5352 let Predicates = [HasVLX, HasAVX512] in {
5353 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5354 v16i8x_info, i16mem, LdFrag, OpNode>,
5355 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
5357 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5358 v16i8x_info, i32mem, LdFrag, OpNode>,
5359 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
5361 let Predicates = [HasAVX512] in {
5362 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5363 v16i8x_info, i64mem, LdFrag, OpNode>,
5364 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
5368 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5369 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5370 let Predicates = [HasVLX, HasAVX512] in {
5371 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5372 v8i16x_info, i64mem, LdFrag, OpNode>,
5373 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
5375 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5376 v8i16x_info, i128mem, LdFrag, OpNode>,
5377 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
5379 let Predicates = [HasAVX512] in {
5380 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5381 v16i16x_info, i256mem, LdFrag, OpNode>,
5382 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
5386 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5387 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5388 let Predicates = [HasVLX, HasAVX512] in {
5389 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5390 v8i16x_info, i32mem, LdFrag, OpNode>,
5391 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
5393 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5394 v8i16x_info, i64mem, LdFrag, OpNode>,
5395 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
5397 let Predicates = [HasAVX512] in {
5398 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5399 v8i16x_info, i128mem, LdFrag, OpNode>,
5400 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
5404 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5405 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
5407 let Predicates = [HasVLX, HasAVX512] in {
5408 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5409 v4i32x_info, i64mem, LdFrag, OpNode>,
5410 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
5412 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5413 v4i32x_info, i128mem, LdFrag, OpNode>,
5414 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
5416 let Predicates = [HasAVX512] in {
5417 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5418 v8i32x_info, i256mem, LdFrag, OpNode>,
5419 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
5423 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
5424 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
5425 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
5426 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
5427 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
5428 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
5431 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
5432 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
5433 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
5434 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
5435 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
5436 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
5438 //===----------------------------------------------------------------------===//
5439 // GATHER - SCATTER Operations
5441 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5442 X86MemOperand memop, PatFrag GatherNode> {
5443 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
5444 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
5445 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
5446 !strconcat(OpcodeStr,
5447 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5448 [(set _.RC:$dst, _.KRCWM:$mask_wb,
5449 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
5450 vectoraddr:$src2))]>, EVEX, EVEX_K,
5451 EVEX_CD8<_.EltSize, CD8VT1>;
5454 let ExeDomain = SSEPackedDouble in {
5455 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", v8f64_info, vy64xmem,
5456 mgatherv8i32>, EVEX_V512, VEX_W;
5457 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", v8f64_info, vz64mem,
5458 mgatherv8i64>, EVEX_V512, VEX_W;
5461 let ExeDomain = SSEPackedSingle in {
5462 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", v16f32_info, vz32mem,
5463 mgatherv16i32>, EVEX_V512;
5464 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", v8f32x_info, vz64mem,
5465 mgatherv8i64>, EVEX_V512;
5468 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", v8i64_info, vy64xmem,
5469 mgatherv8i32>, EVEX_V512, VEX_W;
5470 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", v16i32_info, vz32mem,
5471 mgatherv16i32>, EVEX_V512;
5473 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", v8i64_info, vz64mem,
5474 mgatherv8i64>, EVEX_V512, VEX_W;
5475 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", v8i32x_info, vz64mem,
5476 mgatherv8i64>, EVEX_V512;
5478 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5479 X86MemOperand memop, PatFrag ScatterNode> {
5481 let mayStore = 1, Constraints = "$mask = $mask_wb" in
5483 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
5484 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
5485 !strconcat(OpcodeStr,
5486 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5487 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
5488 _.KRCWM:$mask, vectoraddr:$dst))]>,
5489 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5492 let ExeDomain = SSEPackedDouble in {
5493 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", v8f64_info, vy64xmem,
5494 mscatterv8i32>, EVEX_V512, VEX_W;
5495 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", v8f64_info, vz64mem,
5496 mscatterv8i64>, EVEX_V512, VEX_W;
5499 let ExeDomain = SSEPackedSingle in {
5500 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", v16f32_info, vz32mem,
5501 mscatterv16i32>, EVEX_V512;
5502 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", v8f32x_info, vz64mem,
5503 mscatterv8i64>, EVEX_V512;
5506 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", v8i64_info, vy64xmem,
5507 mscatterv8i32>, EVEX_V512, VEX_W;
5508 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", v16i32_info, vz32mem,
5509 mscatterv16i32>, EVEX_V512;
5511 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", v8i64_info, vz64mem,
5512 mscatterv8i64>, EVEX_V512, VEX_W;
5513 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", v8i32x_info, vz64mem,
5514 mscatterv8i64>, EVEX_V512;
5517 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
5518 RegisterClass KRC, X86MemOperand memop> {
5519 let Predicates = [HasPFI], hasSideEffects = 1 in
5520 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
5521 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
5525 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
5526 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5528 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5529 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5531 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5532 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5534 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
5535 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5537 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
5538 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5540 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
5541 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5543 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5544 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5546 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5547 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5549 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5550 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5552 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5553 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5555 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5556 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5558 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5559 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5561 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5562 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5564 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5565 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5567 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5568 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5570 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5571 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5572 //===----------------------------------------------------------------------===//
5573 // VSHUFPS - VSHUFPD Operations
5575 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5576 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5578 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5579 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5580 !strconcat(OpcodeStr,
5581 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5582 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5583 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5584 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5585 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5586 (ins RC:$src1, RC:$src2, u8imm:$src3),
5587 !strconcat(OpcodeStr,
5588 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5589 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5590 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5591 EVEX_4V, Sched<[WriteShuffle]>;
5594 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5595 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5596 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5597 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5599 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5600 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5601 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5602 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5603 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5605 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5606 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5607 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5608 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5609 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5611 // Helper fragments to match sext vXi1 to vXiY.
5612 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5613 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5615 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5616 RegisterClass RC, RegisterClass KRC,
5617 X86MemOperand x86memop,
5618 X86MemOperand x86scalar_mop, string BrdcstStr> {
5619 let hasSideEffects = 0 in {
5620 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5622 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5625 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5626 (ins x86memop:$src),
5627 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5630 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5631 (ins x86scalar_mop:$src),
5632 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5633 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5635 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5636 (ins KRC:$mask, RC:$src),
5637 !strconcat(OpcodeStr,
5638 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5641 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5642 (ins KRC:$mask, x86memop:$src),
5643 !strconcat(OpcodeStr,
5644 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5647 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5648 (ins KRC:$mask, x86scalar_mop:$src),
5649 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5650 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5652 []>, EVEX, EVEX_KZ, EVEX_B;
5654 let Constraints = "$src1 = $dst" in {
5655 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5656 (ins RC:$src1, KRC:$mask, RC:$src2),
5657 !strconcat(OpcodeStr,
5658 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5661 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5662 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5663 !strconcat(OpcodeStr,
5664 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5667 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5668 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5669 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5670 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5671 []>, EVEX, EVEX_K, EVEX_B;
5676 let Predicates = [HasCDI] in {
5677 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5678 i512mem, i32mem, "{1to16}">,
5679 EVEX_V512, EVEX_CD8<32, CD8VF>;
5682 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5683 i512mem, i64mem, "{1to8}">,
5684 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5688 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5690 (VPCONFLICTDrrk VR512:$src1,
5691 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5693 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5695 (VPCONFLICTQrrk VR512:$src1,
5696 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5698 let Predicates = [HasCDI] in {
5699 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5700 i512mem, i32mem, "{1to16}">,
5701 EVEX_V512, EVEX_CD8<32, CD8VF>;
5704 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5705 i512mem, i64mem, "{1to8}">,
5706 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5710 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5712 (VPLZCNTDrrk VR512:$src1,
5713 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5715 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5717 (VPLZCNTQrrk VR512:$src1,
5718 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5720 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5721 (VPLZCNTDrm addr:$src)>;
5722 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5723 (VPLZCNTDrr VR512:$src)>;
5724 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5725 (VPLZCNTQrm addr:$src)>;
5726 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5727 (VPLZCNTQrr VR512:$src)>;
5729 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5730 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5731 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5733 def : Pat<(store VK1:$src, addr:$dst),
5735 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5736 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5738 def : Pat<(store VK8:$src, addr:$dst),
5740 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5741 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5743 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5744 (truncstore node:$val, node:$ptr), [{
5745 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5748 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5749 (MOV8mr addr:$dst, GR8:$src)>;
5751 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5752 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5753 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5754 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5757 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5758 string OpcodeStr, Predicate prd> {
5759 let Predicates = [prd] in
5760 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5762 let Predicates = [prd, HasVLX] in {
5763 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5764 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5768 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5769 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5771 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5773 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5775 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5779 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5781 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
5782 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
5783 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5784 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
5787 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
5788 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
5789 let Predicates = [prd] in
5790 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
5793 let Predicates = [prd, HasVLX] in {
5794 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
5796 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
5801 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
5802 avx512vl_i8_info, HasBWI>;
5803 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
5804 avx512vl_i16_info, HasBWI>, VEX_W;
5805 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
5806 avx512vl_i32_info, HasDQI>;
5807 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
5808 avx512vl_i64_info, HasDQI>, VEX_W;
5810 //===----------------------------------------------------------------------===//
5811 // AVX-512 - COMPRESS and EXPAND
5814 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5816 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
5817 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
5818 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
5820 let mayStore = 1 in {
5821 def mr : AVX5128I<opc, MRMDestMem, (outs),
5822 (ins _.MemOp:$dst, _.RC:$src),
5823 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5824 []>, EVEX_CD8<_.EltSize, CD8VT1>;
5826 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5827 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5828 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5829 [(store (_.VT (vselect _.KRCWM:$mask,
5830 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
5832 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5836 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5837 AVX512VLVectorVTInfo VTInfo> {
5838 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5840 let Predicates = [HasVLX] in {
5841 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5842 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5846 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5848 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5850 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5852 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5856 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5858 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5859 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
5860 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
5863 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5864 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
5865 (_.VT (X86expand (_.VT (bitconvert
5866 (_.LdFrag addr:$src1)))))>,
5867 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
5870 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5871 AVX512VLVectorVTInfo VTInfo> {
5872 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5874 let Predicates = [HasVLX] in {
5875 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5876 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5880 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5882 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5884 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5886 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
5889 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
5890 // op(reg_vec2,mem_vec,imm)
5891 // op(reg_vec2,broadcast(eltVt),imm)
5892 //all instruction created with FROUND_CURRENT
5893 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5895 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5896 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5897 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5898 (OpNode (_.VT _.RC:$src1),
5901 (i32 FROUND_CURRENT))>;
5902 let mayLoad = 1 in {
5903 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5904 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5905 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5906 (OpNode (_.VT _.RC:$src1),
5907 (_.VT (bitconvert (_.LdFrag addr:$src2))),
5909 (i32 FROUND_CURRENT))>;
5910 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5911 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
5912 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
5913 "$src1, ${src2}"##_.BroadcastStr##", $src3",
5914 (OpNode (_.VT _.RC:$src1),
5915 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
5917 (i32 FROUND_CURRENT))>, EVEX_B;
5921 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
5922 // op(reg_vec2,mem_vec,imm)
5923 // op(reg_vec2,broadcast(eltVt),imm)
5924 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
5926 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5927 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5928 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5929 (OpNode (_.VT _.RC:$src1),
5932 let mayLoad = 1 in {
5933 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5934 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5935 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5936 (OpNode (_.VT _.RC:$src1),
5937 (_.VT (bitconvert (_.LdFrag addr:$src2))),
5939 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5940 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
5941 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
5942 "$src1, ${src2}"##_.BroadcastStr##", $src3",
5943 (OpNode (_.VT _.RC:$src1),
5944 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
5945 (i8 imm:$src3))>, EVEX_B;
5949 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
5950 // op(reg_vec2,mem_scalar,imm)
5951 //all instruction created with FROUND_CURRENT
5952 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5953 X86VectorVTInfo _> {
5955 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5956 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5957 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5958 (OpNode (_.VT _.RC:$src1),
5961 (i32 FROUND_CURRENT))>;
5962 let mayLoad = 1 in {
5963 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5964 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5965 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5966 (OpNode (_.VT _.RC:$src1),
5967 (_.VT (scalar_to_vector
5968 (_.ScalarLdFrag addr:$src2))),
5970 (i32 FROUND_CURRENT))>;
5972 let isAsmParserOnly = 1 in {
5973 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
5974 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
5975 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5981 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
5982 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
5983 SDNode OpNode, X86VectorVTInfo _>{
5984 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5985 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5986 OpcodeStr, "$src3,{sae}, $src2, $src1",
5987 "$src1, $src2,{sae}, $src3",
5988 (OpNode (_.VT _.RC:$src1),
5991 (i32 FROUND_NO_EXC))>, EVEX_B;
5993 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
5994 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
5995 SDNode OpNode, X86VectorVTInfo _> {
5996 defm NAME: avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _>;
5999 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6000 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6001 let Predicates = [prd] in {
6002 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6003 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6007 let Predicates = [prd, HasVLX] in {
6008 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6010 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6015 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6016 bits<8> opc, SDNode OpNode>{
6017 let Predicates = [HasAVX512] in {
6018 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6020 let Predicates = [HasAVX512, HasVLX] in {
6021 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6022 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6026 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6027 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6028 let Predicates = [prd] in {
6029 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6030 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6034 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6035 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6036 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6037 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6038 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6039 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6041 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6042 0x55, X86VFixupimm, HasAVX512>,
6043 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6044 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6045 0x55, X86VFixupimm, HasAVX512>,
6046 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6048 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6049 0x50, X86VRange, HasDQI>,
6050 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6051 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6052 0x50, X86VRange, HasDQI>,
6053 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6055 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6056 0x51, X86VRange, HasDQI>,
6057 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6058 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6059 0x51, X86VRange, HasDQI>,
6060 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6063 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6064 bits<8> opc, SDNode OpNode = X86Shuf128>{
6065 let Predicates = [HasAVX512] in {
6066 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6069 let Predicates = [HasAVX512, HasVLX] in {
6070 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6074 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6075 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6076 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6077 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6078 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6079 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6080 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6081 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6083 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6084 AVX512VLVectorVTInfo VTInfo_FP>{
6085 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6086 AVX512AIi8Base, EVEX_4V;
6087 let isCodeGenOnly = 1 in {
6088 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6089 AVX512AIi8Base, EVEX_4V;
6093 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6094 EVEX_CD8<32, CD8VF>;
6095 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6096 EVEX_CD8<64, CD8VF>, VEX_W;
6098 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6099 X86VectorVTInfo _> {
6100 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6101 (ins _.RC:$src1), OpcodeStr##_.Suffix,
6103 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
6106 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6107 (ins _.MemOp:$src1), OpcodeStr##_.Suffix,
6109 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
6110 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
6113 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
6114 X86VectorVTInfo _> :
6115 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
6117 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6118 (ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
6119 "${src1}"##_.BroadcastStr,
6120 "${src1}"##_.BroadcastStr,
6121 (_.VT (OpNode (X86VBroadcast
6122 (_.ScalarLdFrag addr:$src1))))>,
6123 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
6126 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6127 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6128 let Predicates = [prd] in
6129 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
6131 let Predicates = [prd, HasVLX] in {
6132 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
6134 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
6139 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6140 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6141 let Predicates = [prd] in
6142 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
6145 let Predicates = [prd, HasVLX] in {
6146 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
6148 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
6153 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
6154 SDNode OpNode, Predicate prd> {
6155 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
6157 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
6160 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
6161 SDNode OpNode, Predicate prd> {
6162 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
6163 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
6166 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
6167 bits<8> opc_d, bits<8> opc_q,
6168 string OpcodeStr, SDNode OpNode> {
6169 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
6171 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
6175 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
6178 (bc_v16i32 (v16i1sextv16i32)),
6179 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
6180 (VPABSDZrr VR512:$src)>;
6182 (bc_v8i64 (v8i1sextv8i64)),
6183 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
6184 (VPABSQZrr VR512:$src)>;