1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insertps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
480 X86MemOperand x86memop, PatFrag ld_frag,
483 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
484 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
486 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
488 !strconcat(OpcodeStr,
489 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
494 defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
495 i128mem, loadv2i64, VK16WM>,
496 EVEX_V512, EVEX_CD8<32, CD8VT4>;
497 defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
498 i256mem, loadv4i64, VK16WM>, VEX_W,
499 EVEX_V512, EVEX_CD8<64, CD8VT4>;
501 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
502 (VPBROADCASTDZrr VR128X:$src)>;
503 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
504 (VPBROADCASTQZrr VR128X:$src)>;
506 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
507 (VBROADCASTSSZrr VR128X:$src)>;
508 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
509 (VBROADCASTSDZrr VR128X:$src)>;
511 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
512 (VBROADCASTSSZrr VR128X:$src)>;
513 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
514 (VBROADCASTSDZrr VR128X:$src)>;
516 // Provide fallback in case the load node that is used in the patterns above
517 // is used by additional users, which prevents the pattern selection.
518 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
519 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
520 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
521 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
524 let Predicates = [HasAVX512] in {
525 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
527 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
528 addr:$src)), sub_ymm)>;
530 //===----------------------------------------------------------------------===//
531 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
534 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
535 RegisterClass DstRC, RegisterClass KRC,
536 ValueType OpVT, ValueType SrcVT> {
537 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
538 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
542 let Predicates = [HasCDI] in {
543 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
544 VK16, v16i32, v16i1>, EVEX_V512;
545 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
546 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
549 //===----------------------------------------------------------------------===//
552 // -- immediate form --
553 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
554 SDNode OpNode, PatFrag mem_frag,
555 X86MemOperand x86memop, ValueType OpVT> {
556 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
557 (ins RC:$src1, i8imm:$src2),
558 !strconcat(OpcodeStr,
559 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
561 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
563 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
564 (ins x86memop:$src1, i8imm:$src2),
565 !strconcat(OpcodeStr,
566 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
568 (OpVT (OpNode (mem_frag addr:$src1),
569 (i8 imm:$src2))))]>, EVEX;
572 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
573 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
574 let ExeDomain = SSEPackedDouble in
575 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
576 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 // -- VPERM - register form --
579 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
580 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2),
584 !strconcat(OpcodeStr,
585 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
587 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
589 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
590 (ins RC:$src1, x86memop:$src2),
591 !strconcat(OpcodeStr,
592 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
594 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
598 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
599 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
600 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
601 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
602 let ExeDomain = SSEPackedSingle in
603 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 let ExeDomain = SSEPackedDouble in
606 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
607 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
609 // -- VPERM2I - 3 source operands form --
610 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
611 PatFrag mem_frag, X86MemOperand x86memop,
612 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
613 let Constraints = "$src1 = $dst" in {
614 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
615 (ins RC:$src1, RC:$src2, RC:$src3),
616 !strconcat(OpcodeStr,
617 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
619 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
622 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
623 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
624 !strconcat(OpcodeStr,
625 " \t{$src3, $src2, $dst {${mask}}|"
626 "$dst {${mask}}, $src2, $src3}"),
627 [(set RC:$dst, (OpVT (vselect KRC:$mask,
628 (OpNode RC:$src1, RC:$src2,
633 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
634 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
635 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
636 !strconcat(OpcodeStr,
637 " \t{$src3, $src2, $dst {${mask}} {z} |",
638 "$dst {${mask}} {z}, $src2, $src3}"),
639 [(set RC:$dst, (OpVT (vselect KRC:$mask,
640 (OpNode RC:$src1, RC:$src2,
643 (v16i32 immAllZerosV))))))]>,
646 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
647 (ins RC:$src1, RC:$src2, x86memop:$src3),
648 !strconcat(OpcodeStr,
649 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
651 (OpVT (OpNode RC:$src1, RC:$src2,
652 (mem_frag addr:$src3))))]>, EVEX_4V;
654 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
655 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
656 !strconcat(OpcodeStr,
657 " \t{$src3, $src2, $dst {${mask}}|"
658 "$dst {${mask}}, $src2, $src3}"),
660 (OpVT (vselect KRC:$mask,
661 (OpNode RC:$src1, RC:$src2,
662 (mem_frag addr:$src3)),
666 let AddedComplexity = 10 in // Prefer over the rrkz variant
667 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
668 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
669 !strconcat(OpcodeStr,
670 " \t{$src3, $src2, $dst {${mask}} {z}|"
671 "$dst {${mask}} {z}, $src2, $src3}"),
673 (OpVT (vselect KRC:$mask,
674 (OpNode RC:$src1, RC:$src2,
675 (mem_frag addr:$src3)),
677 (v16i32 immAllZerosV))))))]>,
681 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
682 i512mem, X86VPermiv3, v16i32, VK16WM>,
683 EVEX_V512, EVEX_CD8<32, CD8VF>;
684 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
685 i512mem, X86VPermiv3, v8i64, VK8WM>,
686 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
687 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
688 i512mem, X86VPermiv3, v16f32, VK16WM>,
689 EVEX_V512, EVEX_CD8<32, CD8VF>;
690 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
691 i512mem, X86VPermiv3, v8f64, VK8WM>,
692 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
694 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
695 X86VPermv3, v16i32, VK16WM>, EVEX_V512, EVEX_CD8<32, CD8VF>;
696 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
697 X86VPermv3, v8i64, VK8WM>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
698 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
699 X86VPermv3, v16f32, VK16WM>, EVEX_V512, EVEX_CD8<32, CD8VF>;
700 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
701 X86VPermv3, v8f64, VK8WM>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
703 def : Pat<(v16f32 (int_x86_avx512_mask_vpermt_ps_512 (v16i32 VR512:$idx),
704 (v16f32 VR512:$src1), (v16f32 VR512:$src2), (i16 -1))),
705 (VPERMT2PSrr VR512:$src1, VR512:$idx, VR512:$src2)>;
707 def : Pat<(v16i32 (int_x86_avx512_mask_vpermt_d_512 (v16i32 VR512:$idx),
708 (v16i32 VR512:$src1), (v16i32 VR512:$src2), (i16 -1))),
709 (VPERMT2Drr VR512:$src1, VR512:$idx, VR512:$src2)>;
711 def : Pat<(v8f64 (int_x86_avx512_mask_vpermt_pd_512 (v8i64 VR512:$idx),
712 (v8f64 VR512:$src1), (v8f64 VR512:$src2), (i8 -1))),
713 (VPERMT2PDrr VR512:$src1, VR512:$idx, VR512:$src2)>;
715 def : Pat<(v8i64 (int_x86_avx512_mask_vpermt_q_512 (v8i64 VR512:$idx),
716 (v8i64 VR512:$src1), (v8i64 VR512:$src2), (i8 -1))),
717 (VPERMT2Qrr VR512:$src1, VR512:$idx, VR512:$src2)>;
718 //===----------------------------------------------------------------------===//
719 // AVX-512 - BLEND using mask
721 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
722 RegisterClass KRC, RegisterClass RC,
723 X86MemOperand x86memop, PatFrag mem_frag,
724 SDNode OpNode, ValueType vt> {
725 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
726 (ins KRC:$mask, RC:$src1, RC:$src2),
727 !strconcat(OpcodeStr,
728 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
729 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
730 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
732 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
733 (ins KRC:$mask, RC:$src1, x86memop:$src2),
734 !strconcat(OpcodeStr,
735 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
736 []>, EVEX_4V, EVEX_K;
739 let ExeDomain = SSEPackedSingle in
740 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
741 VK16WM, VR512, f512mem,
742 memopv16f32, vselect, v16f32>,
743 EVEX_CD8<32, CD8VF>, EVEX_V512;
744 let ExeDomain = SSEPackedDouble in
745 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
746 VK8WM, VR512, f512mem,
747 memopv8f64, vselect, v8f64>,
748 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
750 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
751 (v16f32 VR512:$src2), (i16 GR16:$mask))),
752 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
753 VR512:$src1, VR512:$src2)>;
755 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
756 (v8f64 VR512:$src2), (i8 GR8:$mask))),
757 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
758 VR512:$src1, VR512:$src2)>;
760 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
761 VK16WM, VR512, f512mem,
762 memopv16i32, vselect, v16i32>,
763 EVEX_CD8<32, CD8VF>, EVEX_V512;
765 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
766 VK8WM, VR512, f512mem,
767 memopv8i64, vselect, v8i64>,
768 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
770 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
771 (v16i32 VR512:$src2), (i16 GR16:$mask))),
772 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
773 VR512:$src1, VR512:$src2)>;
775 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
776 (v8i64 VR512:$src2), (i8 GR8:$mask))),
777 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
778 VR512:$src1, VR512:$src2)>;
780 let Predicates = [HasAVX512] in {
781 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
782 (v8f32 VR256X:$src2))),
784 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
785 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
786 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
788 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
789 (v8i32 VR256X:$src2))),
791 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
792 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
793 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
795 //===----------------------------------------------------------------------===//
796 // Compare Instructions
797 //===----------------------------------------------------------------------===//
799 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
800 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
801 Operand CC, SDNode OpNode, ValueType VT,
802 PatFrag ld_frag, string asm, string asm_alt> {
803 def rr : AVX512Ii8<0xC2, MRMSrcReg,
804 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
805 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
806 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
807 def rm : AVX512Ii8<0xC2, MRMSrcMem,
808 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
809 [(set VK1:$dst, (OpNode (VT RC:$src1),
810 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
811 let isAsmParserOnly = 1, hasSideEffects = 0 in {
812 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
813 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
814 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
815 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
816 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
817 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
821 let Predicates = [HasAVX512] in {
822 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
823 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
824 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
826 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
827 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
828 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
832 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
833 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
834 SDNode OpNode, ValueType vt> {
835 def rr : AVX512BI<opc, MRMSrcReg,
836 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
837 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
838 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
839 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
840 def rm : AVX512BI<opc, MRMSrcMem,
841 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
842 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
843 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
844 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
847 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
848 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
850 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
851 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
852 VEX_W, EVEX_CD8<64, CD8VF>;
854 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
855 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
857 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
858 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
859 VEX_W, EVEX_CD8<64, CD8VF>;
861 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
862 (COPY_TO_REGCLASS (VPCMPGTDZrr
863 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
864 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
866 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
867 (COPY_TO_REGCLASS (VPCMPEQDZrr
868 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
869 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
871 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
872 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
873 SDNode OpNode, ValueType vt, Operand CC, string Suffix> {
874 def rri : AVX512AIi8<opc, MRMSrcReg,
875 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc),
876 !strconcat("vpcmp${cc}", Suffix,
877 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
878 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
879 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
880 def rmi : AVX512AIi8<opc, MRMSrcMem,
881 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc),
882 !strconcat("vpcmp${cc}", Suffix,
883 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
884 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
885 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
886 // Accept explicit immediate argument form instead of comparison code.
887 let isAsmParserOnly = 1, hasSideEffects = 0 in {
888 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
889 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
890 !strconcat("vpcmp", Suffix,
891 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
892 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
893 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
894 (outs KRC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2, i8imm:$cc),
895 !strconcat("vpcmp", Suffix,
896 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
897 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
898 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
899 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
900 !strconcat("vpcmp", Suffix,
901 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
902 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
903 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
904 (outs KRC:$dst), (ins KRC:$mask, RC:$src1, x86memop:$src2, i8imm:$cc),
905 !strconcat("vpcmp", Suffix,
906 "\t{$cc, $src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2, $cc}"),
907 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
911 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
912 X86cmpm, v16i32, AVXCC, "d">,
913 EVEX_V512, EVEX_CD8<32, CD8VF>;
914 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
915 X86cmpmu, v16i32, AVXCC, "ud">,
916 EVEX_V512, EVEX_CD8<32, CD8VF>;
918 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
919 X86cmpm, v8i64, AVXCC, "q">,
920 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
921 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
922 X86cmpmu, v8i64, AVXCC, "uq">,
923 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
925 // avx512_cmp_packed - compare packed instructions
926 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
927 X86MemOperand x86memop, ValueType vt,
928 string suffix, Domain d> {
929 def rri : AVX512PIi8<0xC2, MRMSrcReg,
930 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
931 !strconcat("vcmp${cc}", suffix,
932 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
933 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
934 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
935 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
936 !strconcat("vcmp${cc}", suffix,
937 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
939 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
940 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
941 !strconcat("vcmp${cc}", suffix,
942 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
944 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
946 // Accept explicit immediate argument form instead of comparison code.
947 let isAsmParserOnly = 1, hasSideEffects = 0 in {
948 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
949 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
950 !strconcat("vcmp", suffix,
951 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
952 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
953 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
954 !strconcat("vcmp", suffix,
955 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
959 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
960 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
962 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
963 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
966 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
967 (COPY_TO_REGCLASS (VCMPPSZrri
968 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
969 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
971 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
972 (COPY_TO_REGCLASS (VPCMPDZrri
973 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
974 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
976 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
977 (COPY_TO_REGCLASS (VPCMPUDZrri
978 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
979 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
982 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
983 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
985 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
986 (I8Imm imm:$cc)), GR16)>;
988 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
989 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
991 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
992 (I8Imm imm:$cc)), GR8)>;
994 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
995 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
997 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
998 (I8Imm imm:$cc)), GR16)>;
1000 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1001 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1003 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1004 (I8Imm imm:$cc)), GR8)>;
1006 // Mask register copy, including
1007 // - copy between mask registers
1008 // - load/store mask registers
1009 // - copy from GPR to mask register and vice versa
1011 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1012 string OpcodeStr, RegisterClass KRC,
1013 ValueType vt, X86MemOperand x86memop> {
1014 let hasSideEffects = 0 in {
1015 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1016 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1018 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1019 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1020 [(set KRC:$dst, (vt (load addr:$src)))]>;
1022 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1023 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1027 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1029 RegisterClass KRC, RegisterClass GRC> {
1030 let hasSideEffects = 0 in {
1031 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1032 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1033 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1034 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
1038 let Predicates = [HasAVX512] in {
1039 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1041 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1045 let Predicates = [HasAVX512] in {
1046 // GR16 from/to 16-bit mask
1047 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1048 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1049 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1050 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1052 // Store kreg in memory
1053 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
1054 (KMOVWmk addr:$dst, VK16:$src)>;
1056 def : Pat<(store VK8:$src, addr:$dst),
1057 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1059 def : Pat<(i1 (load addr:$src)),
1060 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
1062 def : Pat<(v8i1 (load addr:$src)),
1063 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1065 def : Pat<(i1 (trunc (i32 GR32:$src))),
1066 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1068 def : Pat<(i1 (trunc (i8 GR8:$src))),
1070 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1072 def : Pat<(i1 (trunc (i16 GR16:$src))),
1074 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1077 def : Pat<(i32 (zext VK1:$src)),
1078 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1079 def : Pat<(i8 (zext VK1:$src)),
1082 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1083 def : Pat<(i64 (zext VK1:$src)),
1084 (AND64ri8 (SUBREG_TO_REG (i64 0),
1085 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1086 def : Pat<(i16 (zext VK1:$src)),
1088 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1090 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1091 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1092 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1093 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1095 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1096 let Predicates = [HasAVX512] in {
1097 // GR from/to 8-bit mask without native support
1098 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1100 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1102 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1104 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1107 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1108 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1109 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1110 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1114 // Mask unary operation
1116 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1117 RegisterClass KRC, SDPatternOperator OpNode> {
1118 let Predicates = [HasAVX512] in
1119 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1120 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1121 [(set KRC:$dst, (OpNode KRC:$src))]>;
1124 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1125 SDPatternOperator OpNode> {
1126 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1130 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1132 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1133 let Predicates = [HasAVX512] in
1134 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1136 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1137 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1139 defm : avx512_mask_unop_int<"knot", "KNOT">;
1141 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1142 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1143 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1145 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1146 def : Pat<(not VK8:$src),
1148 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1150 // Mask binary operation
1151 // - KAND, KANDN, KOR, KXNOR, KXOR
1152 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1153 RegisterClass KRC, SDPatternOperator OpNode> {
1154 let Predicates = [HasAVX512] in
1155 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1156 !strconcat(OpcodeStr,
1157 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1158 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1161 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1162 SDPatternOperator OpNode> {
1163 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1167 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1168 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1170 let isCommutable = 1 in {
1171 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1172 let isCommutable = 0 in
1173 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1174 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1175 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1176 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1179 def : Pat<(xor VK1:$src1, VK1:$src2),
1180 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1181 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1183 def : Pat<(or VK1:$src1, VK1:$src2),
1184 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1185 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1187 def : Pat<(and VK1:$src1, VK1:$src2),
1188 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1189 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1191 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1192 let Predicates = [HasAVX512] in
1193 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1194 (i16 GR16:$src1), (i16 GR16:$src2)),
1195 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1196 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1197 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1200 defm : avx512_mask_binop_int<"kand", "KAND">;
1201 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1202 defm : avx512_mask_binop_int<"kor", "KOR">;
1203 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1204 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1206 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1207 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1208 let Predicates = [HasAVX512] in
1209 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1211 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1212 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1215 defm : avx512_binop_pat<and, KANDWrr>;
1216 defm : avx512_binop_pat<andn, KANDNWrr>;
1217 defm : avx512_binop_pat<or, KORWrr>;
1218 defm : avx512_binop_pat<xnor, KXNORWrr>;
1219 defm : avx512_binop_pat<xor, KXORWrr>;
1222 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1223 RegisterClass KRC> {
1224 let Predicates = [HasAVX512] in
1225 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1226 !strconcat(OpcodeStr,
1227 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1230 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1231 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1235 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1236 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1237 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1238 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1241 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1242 let Predicates = [HasAVX512] in
1243 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1244 (i16 GR16:$src1), (i16 GR16:$src2)),
1245 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1246 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1247 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1249 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1252 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1254 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1255 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1256 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1257 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1260 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1261 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1265 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1267 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1268 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1269 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1272 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1274 let Predicates = [HasAVX512] in
1275 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1276 !strconcat(OpcodeStr,
1277 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1278 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1281 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1283 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1287 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1288 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1290 // Mask setting all 0s or 1s
1291 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1292 let Predicates = [HasAVX512] in
1293 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1294 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1295 [(set KRC:$dst, (VT Val))]>;
1298 multiclass avx512_mask_setop_w<PatFrag Val> {
1299 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1300 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1303 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1304 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1306 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1307 let Predicates = [HasAVX512] in {
1308 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1309 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1310 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1311 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1312 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1314 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1315 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1317 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1318 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1320 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1321 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1323 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1324 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1326 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1327 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1328 //===----------------------------------------------------------------------===//
1329 // AVX-512 - Aligned and unaligned load and store
1332 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1333 X86MemOperand x86memop, PatFrag ld_frag,
1334 string asm, Domain d,
1335 ValueType vt, bit IsReMaterializable = 1> {
1336 let hasSideEffects = 0 in {
1337 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1338 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1340 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1342 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1343 [], d>, EVEX, EVEX_KZ;
1345 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1346 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1347 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1348 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1349 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1350 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1351 (ins RC:$src1, KRC:$mask, RC:$src2),
1353 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1356 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1357 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1359 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1360 [], d>, EVEX, EVEX_K;
1363 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1364 (ins KRC:$mask, x86memop:$src2),
1366 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1367 [], d>, EVEX, EVEX_KZ;
1370 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1371 X86MemOperand x86memop, PatFrag store_frag,
1372 string asm, Domain d, ValueType vt> {
1373 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1374 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1375 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1377 let Constraints = "$src1 = $dst" in
1378 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1379 (ins RC:$src1, KRC:$mask, RC:$src2),
1381 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1383 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1384 (ins KRC:$mask, RC:$src),
1386 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1387 [], d>, EVEX, EVEX_KZ;
1389 let mayStore = 1 in {
1390 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1391 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1392 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1393 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1394 (ins x86memop:$dst, KRC:$mask, RC:$src),
1396 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1397 [], d>, EVEX, EVEX_K;
1398 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1399 (ins x86memop:$dst, KRC:$mask, RC:$src),
1401 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1402 [], d>, EVEX, EVEX_KZ;
1406 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1407 "vmovaps", SSEPackedSingle, v16f32>,
1408 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1409 "vmovaps", SSEPackedSingle, v16f32>,
1410 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1411 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1412 "vmovapd", SSEPackedDouble, v8f64>,
1413 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1414 "vmovapd", SSEPackedDouble, v8f64>,
1415 PD, EVEX_V512, VEX_W,
1416 EVEX_CD8<64, CD8VF>;
1417 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1418 "vmovups", SSEPackedSingle, v16f32>,
1419 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1420 "vmovups", SSEPackedSingle, v16f32>,
1421 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1422 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1423 "vmovupd", SSEPackedDouble, v8f64, 0>,
1424 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1425 "vmovupd", SSEPackedDouble, v8f64>,
1426 PD, EVEX_V512, VEX_W,
1427 EVEX_CD8<64, CD8VF>;
1428 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1429 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1430 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1432 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1433 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1434 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1436 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1438 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1440 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1442 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1445 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1446 "vmovdqa32", SSEPackedInt, v16i32>,
1447 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1448 "vmovdqa32", SSEPackedInt, v16i32>,
1449 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1450 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1451 "vmovdqa64", SSEPackedInt, v8i64>,
1452 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1453 "vmovdqa64", SSEPackedInt, v8i64>,
1454 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1455 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1456 "vmovdqu32", SSEPackedInt, v16i32>,
1457 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1458 "vmovdqu32", SSEPackedInt, v16i32>,
1459 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1460 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1461 "vmovdqu64", SSEPackedInt, v8i64>,
1462 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1463 "vmovdqu64", SSEPackedInt, v8i64>,
1464 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1466 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1467 (v16i32 immAllZerosV), GR16:$mask)),
1468 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1470 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1471 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1472 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1474 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
1476 (VMOVDQU32mrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1478 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
1480 (VMOVDQU64mrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1483 let AddedComplexity = 20 in {
1484 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1485 (bc_v8i64 (v16i32 immAllZerosV)))),
1486 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1488 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1489 (v8i64 VR512:$src))),
1490 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1493 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1494 (v16i32 immAllZerosV))),
1495 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1497 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1498 (v16i32 VR512:$src))),
1499 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1501 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1502 (v16f32 VR512:$src2))),
1503 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1504 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1505 (v8f64 VR512:$src2))),
1506 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1507 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1508 (v16i32 VR512:$src2))),
1509 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1510 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1511 (v8i64 VR512:$src2))),
1512 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1514 // Move Int Doubleword to Packed Double Int
1516 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1517 "vmovd\t{$src, $dst|$dst, $src}",
1519 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1521 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1522 "vmovd\t{$src, $dst|$dst, $src}",
1524 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1525 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1526 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1527 "vmovq\t{$src, $dst|$dst, $src}",
1529 (v2i64 (scalar_to_vector GR64:$src)))],
1530 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1531 let isCodeGenOnly = 1 in {
1532 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1533 "vmovq\t{$src, $dst|$dst, $src}",
1534 [(set FR64:$dst, (bitconvert GR64:$src))],
1535 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1536 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1537 "vmovq\t{$src, $dst|$dst, $src}",
1538 [(set GR64:$dst, (bitconvert FR64:$src))],
1539 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1541 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1542 "vmovq\t{$src, $dst|$dst, $src}",
1543 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1544 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1545 EVEX_CD8<64, CD8VT1>;
1547 // Move Int Doubleword to Single Scalar
1549 let isCodeGenOnly = 1 in {
1550 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1551 "vmovd\t{$src, $dst|$dst, $src}",
1552 [(set FR32X:$dst, (bitconvert GR32:$src))],
1553 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1555 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1556 "vmovd\t{$src, $dst|$dst, $src}",
1557 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1558 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1561 // Move doubleword from xmm register to r/m32
1563 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1564 "vmovd\t{$src, $dst|$dst, $src}",
1565 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1566 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1568 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1569 (ins i32mem:$dst, VR128X:$src),
1570 "vmovd\t{$src, $dst|$dst, $src}",
1571 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1572 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1573 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1575 // Move quadword from xmm1 register to r/m64
1577 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1578 "vmovq\t{$src, $dst|$dst, $src}",
1579 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1581 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1582 Requires<[HasAVX512, In64BitMode]>;
1584 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1585 (ins i64mem:$dst, VR128X:$src),
1586 "vmovq\t{$src, $dst|$dst, $src}",
1587 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1588 addr:$dst)], IIC_SSE_MOVDQ>,
1589 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1590 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1592 // Move Scalar Single to Double Int
1594 let isCodeGenOnly = 1 in {
1595 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1597 "vmovd\t{$src, $dst|$dst, $src}",
1598 [(set GR32:$dst, (bitconvert FR32X:$src))],
1599 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1600 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1601 (ins i32mem:$dst, FR32X:$src),
1602 "vmovd\t{$src, $dst|$dst, $src}",
1603 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1604 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1607 // Move Quadword Int to Packed Quadword Int
1609 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1611 "vmovq\t{$src, $dst|$dst, $src}",
1613 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1614 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1616 //===----------------------------------------------------------------------===//
1617 // AVX-512 MOVSS, MOVSD
1618 //===----------------------------------------------------------------------===//
1620 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1621 SDNode OpNode, ValueType vt,
1622 X86MemOperand x86memop, PatFrag mem_pat> {
1623 let hasSideEffects = 0 in {
1624 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1625 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1626 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1627 (scalar_to_vector RC:$src2))))],
1628 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1629 let Constraints = "$src1 = $dst" in
1630 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1631 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1633 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1634 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1635 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1636 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1637 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1639 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1640 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1641 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1643 } //hasSideEffects = 0
1646 let ExeDomain = SSEPackedSingle in
1647 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1648 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1650 let ExeDomain = SSEPackedDouble in
1651 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1652 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1654 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1655 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1656 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1658 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1659 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1660 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1662 // For the disassembler
1663 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1664 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1665 (ins VR128X:$src1, FR32X:$src2),
1666 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1668 XS, EVEX_4V, VEX_LIG;
1669 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1670 (ins VR128X:$src1, FR64X:$src2),
1671 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1673 XD, EVEX_4V, VEX_LIG, VEX_W;
1676 let Predicates = [HasAVX512] in {
1677 let AddedComplexity = 15 in {
1678 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1679 // MOVS{S,D} to the lower bits.
1680 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1681 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1682 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1683 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1684 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1685 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1686 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1687 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1689 // Move low f32 and clear high bits.
1690 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1691 (SUBREG_TO_REG (i32 0),
1692 (VMOVSSZrr (v4f32 (V_SET0)),
1693 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1694 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1695 (SUBREG_TO_REG (i32 0),
1696 (VMOVSSZrr (v4i32 (V_SET0)),
1697 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1700 let AddedComplexity = 20 in {
1701 // MOVSSrm zeros the high parts of the register; represent this
1702 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1703 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1704 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1705 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1706 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1707 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1708 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1710 // MOVSDrm zeros the high parts of the register; represent this
1711 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1712 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1713 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1714 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1715 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1716 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1717 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1718 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1719 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1720 def : Pat<(v2f64 (X86vzload addr:$src)),
1721 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1723 // Represent the same patterns above but in the form they appear for
1725 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1726 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1727 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1728 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1729 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1730 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1731 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1732 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1733 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1735 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1736 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1737 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1738 FR32X:$src)), sub_xmm)>;
1739 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1740 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1741 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1742 FR64X:$src)), sub_xmm)>;
1743 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1744 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1745 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1747 // Move low f64 and clear high bits.
1748 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1749 (SUBREG_TO_REG (i32 0),
1750 (VMOVSDZrr (v2f64 (V_SET0)),
1751 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1753 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1754 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1755 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1757 // Extract and store.
1758 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1760 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1761 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1763 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1765 // Shuffle with VMOVSS
1766 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1767 (VMOVSSZrr (v4i32 VR128X:$src1),
1768 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1769 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1770 (VMOVSSZrr (v4f32 VR128X:$src1),
1771 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1774 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1775 (SUBREG_TO_REG (i32 0),
1776 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1777 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1779 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1780 (SUBREG_TO_REG (i32 0),
1781 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1782 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1785 // Shuffle with VMOVSD
1786 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1787 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1788 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1789 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1790 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1791 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1792 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1793 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1796 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1797 (SUBREG_TO_REG (i32 0),
1798 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1799 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1801 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1802 (SUBREG_TO_REG (i32 0),
1803 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1804 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1807 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1808 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1809 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1810 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1811 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1812 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1813 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1814 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1817 let AddedComplexity = 15 in
1818 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1820 "vmovq\t{$src, $dst|$dst, $src}",
1821 [(set VR128X:$dst, (v2i64 (X86vzmovl
1822 (v2i64 VR128X:$src))))],
1823 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1825 let AddedComplexity = 20 in
1826 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1828 "vmovq\t{$src, $dst|$dst, $src}",
1829 [(set VR128X:$dst, (v2i64 (X86vzmovl
1830 (loadv2i64 addr:$src))))],
1831 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1832 EVEX_CD8<8, CD8VT8>;
1834 let Predicates = [HasAVX512] in {
1835 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1836 let AddedComplexity = 20 in {
1837 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1838 (VMOVDI2PDIZrm addr:$src)>;
1839 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1840 (VMOV64toPQIZrr GR64:$src)>;
1841 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1842 (VMOVDI2PDIZrr GR32:$src)>;
1844 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1845 (VMOVDI2PDIZrm addr:$src)>;
1846 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1847 (VMOVDI2PDIZrm addr:$src)>;
1848 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1849 (VMOVZPQILo2PQIZrm addr:$src)>;
1850 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1851 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1852 def : Pat<(v2i64 (X86vzload addr:$src)),
1853 (VMOVZPQILo2PQIZrm addr:$src)>;
1856 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1857 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1858 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1859 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1860 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1861 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1862 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1865 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1866 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1868 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1869 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1871 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1872 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1874 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1875 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1877 //===----------------------------------------------------------------------===//
1878 // AVX-512 - Non-temporals
1879 //===----------------------------------------------------------------------===//
1881 def VMOVNTDQAZrm : AVX5128I<0x2A, MRMSrcMem, (outs VR512:$dst),
1883 "vmovntdqa\t{$src, $dst|$dst, $src}",
1885 (int_x86_avx512_movntdqa addr:$src))]>,
1886 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1888 // Prefer non-temporal over temporal versions
1889 let AddedComplexity = 400, SchedRW = [WriteStore] in {
1891 def VMOVNTPSZmr : AVX512PSI<0x2B, MRMDestMem, (outs),
1892 (ins f512mem:$dst, VR512:$src),
1893 "vmovntps\t{$src, $dst|$dst, $src}",
1894 [(alignednontemporalstore (v16f32 VR512:$src),
1897 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1899 def VMOVNTPDZmr : AVX512PDI<0x2B, MRMDestMem, (outs),
1900 (ins f512mem:$dst, VR512:$src),
1901 "vmovntpd\t{$src, $dst|$dst, $src}",
1902 [(alignednontemporalstore (v8f64 VR512:$src),
1905 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1908 def VMOVNTDQZmr : AVX512BI<0xE7, MRMDestMem, (outs),
1909 (ins i512mem:$dst, VR512:$src),
1910 "vmovntdq\t{$src, $dst|$dst, $src}",
1911 [(alignednontemporalstore (v8i64 VR512:$src),
1914 EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
1917 //===----------------------------------------------------------------------===//
1918 // AVX-512 - Integer arithmetic
1920 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1921 ValueType OpVT, RegisterClass KRC,
1922 RegisterClass RC, PatFrag memop_frag,
1923 X86MemOperand x86memop, PatFrag scalar_mfrag,
1924 X86MemOperand x86scalar_mop, string BrdcstStr,
1925 OpndItins itins, bit IsCommutable = 0> {
1926 let isCommutable = IsCommutable in
1927 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1928 (ins RC:$src1, RC:$src2),
1929 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1930 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1932 let AddedComplexity = 30 in {
1933 let Constraints = "$src0 = $dst" in
1934 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1935 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
1936 !strconcat(OpcodeStr,
1937 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1938 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1939 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1941 itins.rr>, EVEX_4V, EVEX_K;
1942 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1943 (ins KRC:$mask, RC:$src1, RC:$src2),
1944 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1945 "|$dst {${mask}} {z}, $src1, $src2}"),
1946 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1947 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1948 (OpVT immAllZerosV))))],
1949 itins.rr>, EVEX_4V, EVEX_KZ;
1952 let mayLoad = 1 in {
1953 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1954 (ins RC:$src1, x86memop:$src2),
1955 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1956 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1958 let AddedComplexity = 30 in {
1959 let Constraints = "$src0 = $dst" in
1960 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1961 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
1962 !strconcat(OpcodeStr,
1963 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1964 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1965 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1967 itins.rm>, EVEX_4V, EVEX_K;
1968 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1969 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1970 !strconcat(OpcodeStr,
1971 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1972 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1973 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1974 (OpVT immAllZerosV))))],
1975 itins.rm>, EVEX_4V, EVEX_KZ;
1977 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1978 (ins RC:$src1, x86scalar_mop:$src2),
1979 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1980 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1981 [(set RC:$dst, (OpNode RC:$src1,
1982 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1983 itins.rm>, EVEX_4V, EVEX_B;
1984 let AddedComplexity = 30 in {
1985 let Constraints = "$src0 = $dst" in
1986 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1987 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1988 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1989 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1991 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1992 (OpNode (OpVT RC:$src1),
1993 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1995 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1996 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1997 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1998 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1999 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2001 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2002 (OpNode (OpVT RC:$src1),
2003 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2004 (OpVT immAllZerosV))))],
2005 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2010 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2011 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2012 PatFrag memop_frag, X86MemOperand x86memop,
2013 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2014 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
2015 let isCommutable = IsCommutable in
2017 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2018 (ins RC:$src1, RC:$src2),
2019 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2021 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2022 (ins KRC:$mask, RC:$src1, RC:$src2),
2023 !strconcat(OpcodeStr,
2024 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2025 [], itins.rr>, EVEX_4V, EVEX_K;
2026 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2027 (ins KRC:$mask, RC:$src1, RC:$src2),
2028 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2029 "|$dst {${mask}} {z}, $src1, $src2}"),
2030 [], itins.rr>, EVEX_4V, EVEX_KZ;
2032 let mayLoad = 1 in {
2033 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2034 (ins RC:$src1, x86memop:$src2),
2035 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2037 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2038 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2039 !strconcat(OpcodeStr,
2040 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2041 [], itins.rm>, EVEX_4V, EVEX_K;
2042 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2043 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2044 !strconcat(OpcodeStr,
2045 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2046 [], itins.rm>, EVEX_4V, EVEX_KZ;
2047 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2048 (ins RC:$src1, x86scalar_mop:$src2),
2049 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2050 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2051 [], itins.rm>, EVEX_4V, EVEX_B;
2052 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2053 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2054 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2055 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2057 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2058 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2059 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2060 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2061 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2063 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2067 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2068 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2069 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2071 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2072 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2073 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2075 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2076 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2077 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2079 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2080 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2081 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
2083 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2084 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2085 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2087 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2088 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2089 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2090 EVEX_CD8<64, CD8VF>, VEX_W;
2092 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2093 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2094 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
2096 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2097 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2099 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2100 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2101 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2102 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2103 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2104 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2106 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2107 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2108 SSE_INTALU_ITINS_P, 1>,
2109 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2110 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2111 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2112 SSE_INTALU_ITINS_P, 0>,
2113 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2115 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2116 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2117 SSE_INTALU_ITINS_P, 1>,
2118 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2119 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2120 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2121 SSE_INTALU_ITINS_P, 0>,
2122 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2124 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2125 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2126 SSE_INTALU_ITINS_P, 1>,
2127 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2128 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2129 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2130 SSE_INTALU_ITINS_P, 0>,
2131 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2133 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2134 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2135 SSE_INTALU_ITINS_P, 1>,
2136 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2137 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2138 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2139 SSE_INTALU_ITINS_P, 0>,
2140 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2142 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2143 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2144 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2145 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2146 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2147 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2148 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2149 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2150 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2151 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2152 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2153 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2154 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2155 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2156 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2157 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2158 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2159 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2160 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2161 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2162 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2163 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2164 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2165 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2166 //===----------------------------------------------------------------------===//
2167 // AVX-512 - Unpack Instructions
2168 //===----------------------------------------------------------------------===//
2170 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2171 PatFrag mem_frag, RegisterClass RC,
2172 X86MemOperand x86memop, string asm,
2174 def rr : AVX512PI<opc, MRMSrcReg,
2175 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2177 (vt (OpNode RC:$src1, RC:$src2)))],
2179 def rm : AVX512PI<opc, MRMSrcMem,
2180 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2182 (vt (OpNode RC:$src1,
2183 (bitconvert (mem_frag addr:$src2)))))],
2187 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2188 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2189 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2190 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2191 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2192 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2193 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2194 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2195 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2196 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2197 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2198 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2200 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2201 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2202 X86MemOperand x86memop> {
2203 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2204 (ins RC:$src1, RC:$src2),
2205 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2206 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2207 IIC_SSE_UNPCK>, EVEX_4V;
2208 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2209 (ins RC:$src1, x86memop:$src2),
2210 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2211 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2212 (bitconvert (memop_frag addr:$src2)))))],
2213 IIC_SSE_UNPCK>, EVEX_4V;
2215 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2216 VR512, memopv16i32, i512mem>, EVEX_V512,
2217 EVEX_CD8<32, CD8VF>;
2218 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2219 VR512, memopv8i64, i512mem>, EVEX_V512,
2220 VEX_W, EVEX_CD8<64, CD8VF>;
2221 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2222 VR512, memopv16i32, i512mem>, EVEX_V512,
2223 EVEX_CD8<32, CD8VF>;
2224 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2225 VR512, memopv8i64, i512mem>, EVEX_V512,
2226 VEX_W, EVEX_CD8<64, CD8VF>;
2227 //===----------------------------------------------------------------------===//
2231 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2232 SDNode OpNode, PatFrag mem_frag,
2233 X86MemOperand x86memop, ValueType OpVT> {
2234 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2235 (ins RC:$src1, i8imm:$src2),
2236 !strconcat(OpcodeStr,
2237 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2239 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2241 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2242 (ins x86memop:$src1, i8imm:$src2),
2243 !strconcat(OpcodeStr,
2244 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2246 (OpVT (OpNode (mem_frag addr:$src1),
2247 (i8 imm:$src2))))]>, EVEX;
2250 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2251 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2253 let ExeDomain = SSEPackedSingle in
2254 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2255 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2256 EVEX_CD8<32, CD8VF>;
2257 let ExeDomain = SSEPackedDouble in
2258 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2259 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2260 VEX_W, EVEX_CD8<32, CD8VF>;
2262 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2263 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2264 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2265 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2267 //===----------------------------------------------------------------------===//
2268 // AVX-512 Logical Instructions
2269 //===----------------------------------------------------------------------===//
2271 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2272 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2273 EVEX_V512, EVEX_CD8<32, CD8VF>;
2274 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2275 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2276 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2277 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2278 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2279 EVEX_V512, EVEX_CD8<32, CD8VF>;
2280 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2281 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2282 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2283 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2284 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2285 EVEX_V512, EVEX_CD8<32, CD8VF>;
2286 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2287 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2288 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2289 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2290 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2291 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2292 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2293 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2294 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2296 //===----------------------------------------------------------------------===//
2297 // AVX-512 FP arithmetic
2298 //===----------------------------------------------------------------------===//
2300 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2302 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2303 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2304 EVEX_CD8<32, CD8VT1>;
2305 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2306 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2307 EVEX_CD8<64, CD8VT1>;
2310 let isCommutable = 1 in {
2311 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2312 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2313 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2314 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2316 let isCommutable = 0 in {
2317 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2318 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2321 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2323 RegisterClass RC, ValueType vt,
2324 X86MemOperand x86memop, PatFrag mem_frag,
2325 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2327 Domain d, OpndItins itins, bit commutable> {
2328 let isCommutable = commutable in {
2329 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2330 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2331 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2334 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2335 !strconcat(OpcodeStr,
2336 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2337 [], itins.rr, d>, EVEX_4V, EVEX_K;
2339 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2340 !strconcat(OpcodeStr,
2341 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2342 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2345 let mayLoad = 1 in {
2346 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2347 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2348 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2349 itins.rm, d>, EVEX_4V;
2351 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2352 (ins RC:$src1, x86scalar_mop:$src2),
2353 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2354 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2355 [(set RC:$dst, (OpNode RC:$src1,
2356 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2357 itins.rm, d>, EVEX_4V, EVEX_B;
2359 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2360 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2361 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2362 [], itins.rm, d>, EVEX_4V, EVEX_K;
2364 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2365 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2366 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2367 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2369 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2370 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2371 " \t{${src2}", BrdcstStr,
2372 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2373 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2375 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2376 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2377 " \t{${src2}", BrdcstStr,
2378 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2380 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2384 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2385 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2386 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2388 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2389 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2390 SSE_ALU_ITINS_P.d, 1>,
2391 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2393 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2394 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2395 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2396 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2397 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2398 SSE_ALU_ITINS_P.d, 1>,
2399 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2401 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2402 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2403 SSE_ALU_ITINS_P.s, 1>,
2404 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2405 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2406 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2407 SSE_ALU_ITINS_P.s, 1>,
2408 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2410 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2411 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2412 SSE_ALU_ITINS_P.d, 1>,
2413 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2414 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2415 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2416 SSE_ALU_ITINS_P.d, 1>,
2417 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2419 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2420 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2421 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2422 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2423 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2424 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2426 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2427 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2428 SSE_ALU_ITINS_P.d, 0>,
2429 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2430 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2431 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2432 SSE_ALU_ITINS_P.d, 0>,
2433 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2435 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2436 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2437 (i16 -1), FROUND_CURRENT)),
2438 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2440 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2441 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2442 (i8 -1), FROUND_CURRENT)),
2443 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2445 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2446 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2447 (i16 -1), FROUND_CURRENT)),
2448 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2450 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2451 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2452 (i8 -1), FROUND_CURRENT)),
2453 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2454 //===----------------------------------------------------------------------===//
2455 // AVX-512 VPTESTM instructions
2456 //===----------------------------------------------------------------------===//
2458 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2459 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2460 SDNode OpNode, ValueType vt> {
2461 def rr : AVX512PI<opc, MRMSrcReg,
2462 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2463 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2464 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2465 SSEPackedInt>, EVEX_4V;
2466 def rm : AVX512PI<opc, MRMSrcMem,
2467 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2468 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2469 [(set KRC:$dst, (OpNode (vt RC:$src1),
2470 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2473 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2474 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2475 EVEX_CD8<32, CD8VF>;
2476 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2477 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2478 EVEX_CD8<64, CD8VF>;
2480 let Predicates = [HasCDI] in {
2481 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2482 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2483 EVEX_CD8<32, CD8VF>;
2484 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2485 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2486 EVEX_CD8<64, CD8VF>;
2489 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2490 (v16i32 VR512:$src2), (i16 -1))),
2491 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2493 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2494 (v8i64 VR512:$src2), (i8 -1))),
2495 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2496 //===----------------------------------------------------------------------===//
2497 // AVX-512 Shift instructions
2498 //===----------------------------------------------------------------------===//
2499 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2500 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2501 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2502 RegisterClass KRC> {
2503 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2504 (ins RC:$src1, i8imm:$src2),
2505 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2506 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2507 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2508 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2509 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2510 !strconcat(OpcodeStr,
2511 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2512 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2513 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2514 (ins x86memop:$src1, i8imm:$src2),
2515 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2516 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2517 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2518 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2519 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2520 !strconcat(OpcodeStr,
2521 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2522 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2525 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2526 RegisterClass RC, ValueType vt, ValueType SrcVT,
2527 PatFrag bc_frag, RegisterClass KRC> {
2528 // src2 is always 128-bit
2529 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2530 (ins RC:$src1, VR128X:$src2),
2531 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2532 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2533 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2534 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2535 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2536 !strconcat(OpcodeStr,
2537 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2538 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2539 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2540 (ins RC:$src1, i128mem:$src2),
2541 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2542 [(set RC:$dst, (vt (OpNode RC:$src1,
2543 (bc_frag (memopv2i64 addr:$src2)))))],
2544 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2545 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2546 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2547 !strconcat(OpcodeStr,
2548 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2549 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2552 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2553 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2554 EVEX_V512, EVEX_CD8<32, CD8VF>;
2555 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2556 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2557 EVEX_CD8<32, CD8VQ>;
2559 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2560 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2561 EVEX_CD8<64, CD8VF>, VEX_W;
2562 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2563 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2564 EVEX_CD8<64, CD8VQ>, VEX_W;
2566 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2567 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2568 EVEX_CD8<32, CD8VF>;
2569 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2570 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2571 EVEX_CD8<32, CD8VQ>;
2573 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2574 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2575 EVEX_CD8<64, CD8VF>, VEX_W;
2576 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2577 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2578 EVEX_CD8<64, CD8VQ>, VEX_W;
2580 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2581 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2582 EVEX_V512, EVEX_CD8<32, CD8VF>;
2583 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2584 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2585 EVEX_CD8<32, CD8VQ>;
2587 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2588 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2589 EVEX_CD8<64, CD8VF>, VEX_W;
2590 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2591 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2592 EVEX_CD8<64, CD8VQ>, VEX_W;
2594 //===-------------------------------------------------------------------===//
2595 // Variable Bit Shifts
2596 //===-------------------------------------------------------------------===//
2597 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2598 RegisterClass RC, ValueType vt,
2599 X86MemOperand x86memop, PatFrag mem_frag> {
2600 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2601 (ins RC:$src1, RC:$src2),
2602 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2604 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2606 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2607 (ins RC:$src1, x86memop:$src2),
2608 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2610 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2614 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2615 i512mem, memopv16i32>, EVEX_V512,
2616 EVEX_CD8<32, CD8VF>;
2617 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2618 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2619 EVEX_CD8<64, CD8VF>;
2620 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2621 i512mem, memopv16i32>, EVEX_V512,
2622 EVEX_CD8<32, CD8VF>;
2623 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2624 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2625 EVEX_CD8<64, CD8VF>;
2626 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2627 i512mem, memopv16i32>, EVEX_V512,
2628 EVEX_CD8<32, CD8VF>;
2629 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2630 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2631 EVEX_CD8<64, CD8VF>;
2633 //===----------------------------------------------------------------------===//
2634 // AVX-512 - MOVDDUP
2635 //===----------------------------------------------------------------------===//
2637 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2638 X86MemOperand x86memop, PatFrag memop_frag> {
2639 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2640 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2641 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2642 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2643 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2645 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2648 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2649 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2650 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2651 (VMOVDDUPZrm addr:$src)>;
2653 //===---------------------------------------------------------------------===//
2654 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2655 //===---------------------------------------------------------------------===//
2656 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2657 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2658 X86MemOperand x86memop> {
2659 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2660 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2661 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2663 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2664 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2665 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2668 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2669 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2670 EVEX_CD8<32, CD8VF>;
2671 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2672 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2673 EVEX_CD8<32, CD8VF>;
2675 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2676 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2677 (VMOVSHDUPZrm addr:$src)>;
2678 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2679 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2680 (VMOVSLDUPZrm addr:$src)>;
2682 //===----------------------------------------------------------------------===//
2683 // Move Low to High and High to Low packed FP Instructions
2684 //===----------------------------------------------------------------------===//
2685 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2686 (ins VR128X:$src1, VR128X:$src2),
2687 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2688 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2689 IIC_SSE_MOV_LH>, EVEX_4V;
2690 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2691 (ins VR128X:$src1, VR128X:$src2),
2692 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2693 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2694 IIC_SSE_MOV_LH>, EVEX_4V;
2696 let Predicates = [HasAVX512] in {
2698 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2699 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2700 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2701 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2704 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2705 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2708 //===----------------------------------------------------------------------===//
2709 // FMA - Fused Multiply Operations
2711 let Constraints = "$src1 = $dst" in {
2712 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2713 RegisterClass RC, X86MemOperand x86memop,
2714 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2715 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2716 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2717 (ins RC:$src1, RC:$src2, RC:$src3),
2718 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2719 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2722 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2723 (ins RC:$src1, RC:$src2, x86memop:$src3),
2724 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2725 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2726 (mem_frag addr:$src3))))]>;
2727 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2728 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2729 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2730 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2731 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2732 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2734 } // Constraints = "$src1 = $dst"
2736 let ExeDomain = SSEPackedSingle in {
2737 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2738 memopv16f32, f32mem, loadf32, "{1to16}",
2739 X86Fmadd, v16f32>, EVEX_V512,
2740 EVEX_CD8<32, CD8VF>;
2741 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2742 memopv16f32, f32mem, loadf32, "{1to16}",
2743 X86Fmsub, v16f32>, EVEX_V512,
2744 EVEX_CD8<32, CD8VF>;
2745 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2746 memopv16f32, f32mem, loadf32, "{1to16}",
2747 X86Fmaddsub, v16f32>,
2748 EVEX_V512, EVEX_CD8<32, CD8VF>;
2749 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2750 memopv16f32, f32mem, loadf32, "{1to16}",
2751 X86Fmsubadd, v16f32>,
2752 EVEX_V512, EVEX_CD8<32, CD8VF>;
2753 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2754 memopv16f32, f32mem, loadf32, "{1to16}",
2755 X86Fnmadd, v16f32>, EVEX_V512,
2756 EVEX_CD8<32, CD8VF>;
2757 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2758 memopv16f32, f32mem, loadf32, "{1to16}",
2759 X86Fnmsub, v16f32>, EVEX_V512,
2760 EVEX_CD8<32, CD8VF>;
2762 let ExeDomain = SSEPackedDouble in {
2763 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2764 memopv8f64, f64mem, loadf64, "{1to8}",
2765 X86Fmadd, v8f64>, EVEX_V512,
2766 VEX_W, EVEX_CD8<64, CD8VF>;
2767 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2768 memopv8f64, f64mem, loadf64, "{1to8}",
2769 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2770 EVEX_CD8<64, CD8VF>;
2771 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2772 memopv8f64, f64mem, loadf64, "{1to8}",
2773 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2774 EVEX_CD8<64, CD8VF>;
2775 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2776 memopv8f64, f64mem, loadf64, "{1to8}",
2777 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2778 EVEX_CD8<64, CD8VF>;
2779 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2780 memopv8f64, f64mem, loadf64, "{1to8}",
2781 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2782 EVEX_CD8<64, CD8VF>;
2783 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2784 memopv8f64, f64mem, loadf64, "{1to8}",
2785 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2786 EVEX_CD8<64, CD8VF>;
2789 let Constraints = "$src1 = $dst" in {
2790 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2791 RegisterClass RC, X86MemOperand x86memop,
2792 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2793 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2795 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2796 (ins RC:$src1, RC:$src3, x86memop:$src2),
2797 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2798 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2799 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2800 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2801 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2802 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2803 [(set RC:$dst, (OpNode RC:$src1,
2804 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2806 } // Constraints = "$src1 = $dst"
2809 let ExeDomain = SSEPackedSingle in {
2810 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2811 memopv16f32, f32mem, loadf32, "{1to16}",
2812 X86Fmadd, v16f32>, EVEX_V512,
2813 EVEX_CD8<32, CD8VF>;
2814 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2815 memopv16f32, f32mem, loadf32, "{1to16}",
2816 X86Fmsub, v16f32>, EVEX_V512,
2817 EVEX_CD8<32, CD8VF>;
2818 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2819 memopv16f32, f32mem, loadf32, "{1to16}",
2820 X86Fmaddsub, v16f32>,
2821 EVEX_V512, EVEX_CD8<32, CD8VF>;
2822 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2823 memopv16f32, f32mem, loadf32, "{1to16}",
2824 X86Fmsubadd, v16f32>,
2825 EVEX_V512, EVEX_CD8<32, CD8VF>;
2826 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2827 memopv16f32, f32mem, loadf32, "{1to16}",
2828 X86Fnmadd, v16f32>, EVEX_V512,
2829 EVEX_CD8<32, CD8VF>;
2830 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2831 memopv16f32, f32mem, loadf32, "{1to16}",
2832 X86Fnmsub, v16f32>, EVEX_V512,
2833 EVEX_CD8<32, CD8VF>;
2835 let ExeDomain = SSEPackedDouble in {
2836 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2837 memopv8f64, f64mem, loadf64, "{1to8}",
2838 X86Fmadd, v8f64>, EVEX_V512,
2839 VEX_W, EVEX_CD8<64, CD8VF>;
2840 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2841 memopv8f64, f64mem, loadf64, "{1to8}",
2842 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2843 EVEX_CD8<64, CD8VF>;
2844 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2845 memopv8f64, f64mem, loadf64, "{1to8}",
2846 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2847 EVEX_CD8<64, CD8VF>;
2848 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2849 memopv8f64, f64mem, loadf64, "{1to8}",
2850 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2851 EVEX_CD8<64, CD8VF>;
2852 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2853 memopv8f64, f64mem, loadf64, "{1to8}",
2854 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2855 EVEX_CD8<64, CD8VF>;
2856 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2857 memopv8f64, f64mem, loadf64, "{1to8}",
2858 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2859 EVEX_CD8<64, CD8VF>;
2863 let Constraints = "$src1 = $dst" in {
2864 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2865 RegisterClass RC, ValueType OpVT,
2866 X86MemOperand x86memop, Operand memop,
2868 let isCommutable = 1 in
2869 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2870 (ins RC:$src1, RC:$src2, RC:$src3),
2871 !strconcat(OpcodeStr,
2872 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2874 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2876 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2877 (ins RC:$src1, RC:$src2, f128mem:$src3),
2878 !strconcat(OpcodeStr,
2879 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2881 (OpVT (OpNode RC:$src2, RC:$src1,
2882 (mem_frag addr:$src3))))]>;
2885 } // Constraints = "$src1 = $dst"
2887 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2888 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2889 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2890 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2891 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2892 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2893 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2894 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2895 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2896 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2897 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2898 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2899 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2900 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2901 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2902 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2904 //===----------------------------------------------------------------------===//
2905 // AVX-512 Scalar convert from sign integer to float/double
2906 //===----------------------------------------------------------------------===//
2908 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2909 X86MemOperand x86memop, string asm> {
2910 let hasSideEffects = 0 in {
2911 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2912 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2915 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2916 (ins DstRC:$src1, x86memop:$src),
2917 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2919 } // hasSideEffects = 0
2921 let Predicates = [HasAVX512] in {
2922 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2923 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2924 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2925 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2926 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2927 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2928 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2929 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2931 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2932 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2933 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2934 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2935 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2936 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2937 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2938 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2940 def : Pat<(f32 (sint_to_fp GR32:$src)),
2941 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2942 def : Pat<(f32 (sint_to_fp GR64:$src)),
2943 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2944 def : Pat<(f64 (sint_to_fp GR32:$src)),
2945 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2946 def : Pat<(f64 (sint_to_fp GR64:$src)),
2947 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2949 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2950 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2951 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2952 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2953 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2954 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2955 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2956 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2958 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2959 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2960 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2961 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2962 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2963 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2964 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2965 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2967 def : Pat<(f32 (uint_to_fp GR32:$src)),
2968 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2969 def : Pat<(f32 (uint_to_fp GR64:$src)),
2970 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2971 def : Pat<(f64 (uint_to_fp GR32:$src)),
2972 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2973 def : Pat<(f64 (uint_to_fp GR64:$src)),
2974 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2977 //===----------------------------------------------------------------------===//
2978 // AVX-512 Scalar convert from float/double to integer
2979 //===----------------------------------------------------------------------===//
2980 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2981 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2983 let hasSideEffects = 0 in {
2984 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2985 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2986 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2987 Requires<[HasAVX512]>;
2989 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2990 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2991 Requires<[HasAVX512]>;
2992 } // hasSideEffects = 0
2994 let Predicates = [HasAVX512] in {
2995 // Convert float/double to signed/unsigned int 32/64
2996 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2997 ssmem, sse_load_f32, "cvtss2si">,
2998 XS, EVEX_CD8<32, CD8VT1>;
2999 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
3000 ssmem, sse_load_f32, "cvtss2si">,
3001 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3002 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
3003 ssmem, sse_load_f32, "cvtss2usi">,
3004 XS, EVEX_CD8<32, CD8VT1>;
3005 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3006 int_x86_avx512_cvtss2usi64, ssmem,
3007 sse_load_f32, "cvtss2usi">, XS, VEX_W,
3008 EVEX_CD8<32, CD8VT1>;
3009 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
3010 sdmem, sse_load_f64, "cvtsd2si">,
3011 XD, EVEX_CD8<64, CD8VT1>;
3012 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
3013 sdmem, sse_load_f64, "cvtsd2si">,
3014 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3015 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
3016 sdmem, sse_load_f64, "cvtsd2usi">,
3017 XD, EVEX_CD8<64, CD8VT1>;
3018 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3019 int_x86_avx512_cvtsd2usi64, sdmem,
3020 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
3021 EVEX_CD8<64, CD8VT1>;
3023 let isCodeGenOnly = 1 in {
3024 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3025 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3026 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3027 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3028 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3029 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3030 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3031 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3032 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3033 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3034 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3035 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3037 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3038 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3039 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3040 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3041 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3042 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3043 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3044 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3045 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3046 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3047 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3048 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3049 } // isCodeGenOnly = 1
3051 // Convert float/double to signed/unsigned int 32/64 with truncation
3052 let isCodeGenOnly = 1 in {
3053 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3054 ssmem, sse_load_f32, "cvttss2si">,
3055 XS, EVEX_CD8<32, CD8VT1>;
3056 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3057 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3058 "cvttss2si">, XS, VEX_W,
3059 EVEX_CD8<32, CD8VT1>;
3060 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3061 sdmem, sse_load_f64, "cvttsd2si">, XD,
3062 EVEX_CD8<64, CD8VT1>;
3063 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3064 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3065 "cvttsd2si">, XD, VEX_W,
3066 EVEX_CD8<64, CD8VT1>;
3067 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3068 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3069 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3070 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3071 int_x86_avx512_cvttss2usi64, ssmem,
3072 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3073 EVEX_CD8<32, CD8VT1>;
3074 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3075 int_x86_avx512_cvttsd2usi,
3076 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3077 EVEX_CD8<64, CD8VT1>;
3078 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3079 int_x86_avx512_cvttsd2usi64, sdmem,
3080 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3081 EVEX_CD8<64, CD8VT1>;
3082 } // isCodeGenOnly = 1
3084 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3085 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3087 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3088 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3089 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3090 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3091 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3092 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3095 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
3096 loadf32, "cvttss2si">, XS,
3097 EVEX_CD8<32, CD8VT1>;
3098 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
3099 loadf32, "cvttss2usi">, XS,
3100 EVEX_CD8<32, CD8VT1>;
3101 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
3102 loadf32, "cvttss2si">, XS, VEX_W,
3103 EVEX_CD8<32, CD8VT1>;
3104 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
3105 loadf32, "cvttss2usi">, XS, VEX_W,
3106 EVEX_CD8<32, CD8VT1>;
3107 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
3108 loadf64, "cvttsd2si">, XD,
3109 EVEX_CD8<64, CD8VT1>;
3110 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
3111 loadf64, "cvttsd2usi">, XD,
3112 EVEX_CD8<64, CD8VT1>;
3113 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
3114 loadf64, "cvttsd2si">, XD, VEX_W,
3115 EVEX_CD8<64, CD8VT1>;
3116 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
3117 loadf64, "cvttsd2usi">, XD, VEX_W,
3118 EVEX_CD8<64, CD8VT1>;
3120 //===----------------------------------------------------------------------===//
3121 // AVX-512 Convert form float to double and back
3122 //===----------------------------------------------------------------------===//
3123 let hasSideEffects = 0 in {
3124 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3125 (ins FR32X:$src1, FR32X:$src2),
3126 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3127 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3129 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3130 (ins FR32X:$src1, f32mem:$src2),
3131 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3132 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3133 EVEX_CD8<32, CD8VT1>;
3135 // Convert scalar double to scalar single
3136 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3137 (ins FR64X:$src1, FR64X:$src2),
3138 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3139 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3141 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3142 (ins FR64X:$src1, f64mem:$src2),
3143 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3144 []>, EVEX_4V, VEX_LIG, VEX_W,
3145 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3148 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3149 Requires<[HasAVX512]>;
3150 def : Pat<(fextend (loadf32 addr:$src)),
3151 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3153 def : Pat<(extloadf32 addr:$src),
3154 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3155 Requires<[HasAVX512, OptForSize]>;
3157 def : Pat<(extloadf32 addr:$src),
3158 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3159 Requires<[HasAVX512, OptForSpeed]>;
3161 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3162 Requires<[HasAVX512]>;
3164 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3165 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3166 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3168 let hasSideEffects = 0 in {
3169 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3170 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3172 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3173 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3174 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3175 [], d>, EVEX, EVEX_B, EVEX_RC;
3177 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3178 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3180 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3181 } // hasSideEffects = 0
3184 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3185 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3186 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3188 let hasSideEffects = 0 in {
3189 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3190 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3192 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3194 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3195 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3197 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3198 } // hasSideEffects = 0
3201 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3202 memopv8f64, f512mem, v8f32, v8f64,
3203 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3204 EVEX_CD8<64, CD8VF>;
3206 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3207 memopv4f64, f256mem, v8f64, v8f32,
3208 SSEPackedDouble>, EVEX_V512, PS,
3209 EVEX_CD8<32, CD8VH>;
3210 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3211 (VCVTPS2PDZrm addr:$src)>;
3213 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3214 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3215 (VCVTPD2PSZrr VR512:$src)>;
3217 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3218 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3219 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3221 //===----------------------------------------------------------------------===//
3222 // AVX-512 Vector convert from sign integer to float/double
3223 //===----------------------------------------------------------------------===//
3225 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3226 memopv8i64, i512mem, v16f32, v16i32,
3227 SSEPackedSingle>, EVEX_V512, PS,
3228 EVEX_CD8<32, CD8VF>;
3230 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3231 memopv4i64, i256mem, v8f64, v8i32,
3232 SSEPackedDouble>, EVEX_V512, XS,
3233 EVEX_CD8<32, CD8VH>;
3235 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3236 memopv16f32, f512mem, v16i32, v16f32,
3237 SSEPackedSingle>, EVEX_V512, XS,
3238 EVEX_CD8<32, CD8VF>;
3240 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3241 memopv8f64, f512mem, v8i32, v8f64,
3242 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3243 EVEX_CD8<64, CD8VF>;
3245 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3246 memopv16f32, f512mem, v16i32, v16f32,
3247 SSEPackedSingle>, EVEX_V512, PS,
3248 EVEX_CD8<32, CD8VF>;
3250 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3251 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3252 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3253 (VCVTTPS2UDQZrr VR512:$src)>;
3255 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3256 memopv8f64, f512mem, v8i32, v8f64,
3257 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3258 EVEX_CD8<64, CD8VF>;
3260 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3261 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3262 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3263 (VCVTTPD2UDQZrr VR512:$src)>;
3265 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3266 memopv4i64, f256mem, v8f64, v8i32,
3267 SSEPackedDouble>, EVEX_V512, XS,
3268 EVEX_CD8<32, CD8VH>;
3270 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3271 memopv16i32, f512mem, v16f32, v16i32,
3272 SSEPackedSingle>, EVEX_V512, XD,
3273 EVEX_CD8<32, CD8VF>;
3275 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3276 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3277 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3279 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3280 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3281 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3283 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3284 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3285 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3287 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3288 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3289 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3291 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3292 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3293 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3295 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3296 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3297 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3298 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3299 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3300 (VCVTDQ2PDZrr VR256X:$src)>;
3301 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3302 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3303 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3304 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3305 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3306 (VCVTUDQ2PDZrr VR256X:$src)>;
3308 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3309 RegisterClass DstRC, PatFrag mem_frag,
3310 X86MemOperand x86memop, Domain d> {
3311 let hasSideEffects = 0 in {
3312 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3313 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3315 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3316 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3317 [], d>, EVEX, EVEX_B, EVEX_RC;
3319 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3320 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3322 } // hasSideEffects = 0
3325 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3326 memopv16f32, f512mem, SSEPackedSingle>, PD,
3327 EVEX_V512, EVEX_CD8<32, CD8VF>;
3328 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3329 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3330 EVEX_V512, EVEX_CD8<64, CD8VF>;
3332 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3333 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3334 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3336 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3337 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3338 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3340 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3341 memopv16f32, f512mem, SSEPackedSingle>,
3342 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3343 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3344 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3345 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3347 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3348 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3349 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3351 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3352 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3353 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3355 let Predicates = [HasAVX512] in {
3356 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3357 (VCVTPD2PSZrm addr:$src)>;
3358 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3359 (VCVTPS2PDZrm addr:$src)>;
3362 //===----------------------------------------------------------------------===//
3363 // Half precision conversion instructions
3364 //===----------------------------------------------------------------------===//
3365 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3366 X86MemOperand x86memop> {
3367 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3368 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3370 let hasSideEffects = 0, mayLoad = 1 in
3371 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3372 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3375 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3376 X86MemOperand x86memop> {
3377 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3378 (ins srcRC:$src1, i32i8imm:$src2),
3379 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3381 let hasSideEffects = 0, mayStore = 1 in
3382 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3383 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3384 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3387 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3388 EVEX_CD8<32, CD8VH>;
3389 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3390 EVEX_CD8<32, CD8VH>;
3392 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3393 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3394 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3396 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3397 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3398 (VCVTPH2PSZrr VR256X:$src)>;
3400 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3401 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3402 "ucomiss">, PS, EVEX, VEX_LIG,
3403 EVEX_CD8<32, CD8VT1>;
3404 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3405 "ucomisd">, PD, EVEX,
3406 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3407 let Pattern = []<dag> in {
3408 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3409 "comiss">, PS, EVEX, VEX_LIG,
3410 EVEX_CD8<32, CD8VT1>;
3411 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3412 "comisd">, PD, EVEX,
3413 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3415 let isCodeGenOnly = 1 in {
3416 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3417 load, "ucomiss">, PS, EVEX, VEX_LIG,
3418 EVEX_CD8<32, CD8VT1>;
3419 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3420 load, "ucomisd">, PD, EVEX,
3421 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3423 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3424 load, "comiss">, PS, EVEX, VEX_LIG,
3425 EVEX_CD8<32, CD8VT1>;
3426 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3427 load, "comisd">, PD, EVEX,
3428 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3432 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3433 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3434 X86MemOperand x86memop> {
3435 let hasSideEffects = 0 in {
3436 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3437 (ins RC:$src1, RC:$src2),
3438 !strconcat(OpcodeStr,
3439 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3440 let mayLoad = 1 in {
3441 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3442 (ins RC:$src1, x86memop:$src2),
3443 !strconcat(OpcodeStr,
3444 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3449 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3450 EVEX_CD8<32, CD8VT1>;
3451 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3452 VEX_W, EVEX_CD8<64, CD8VT1>;
3453 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3454 EVEX_CD8<32, CD8VT1>;
3455 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3456 VEX_W, EVEX_CD8<64, CD8VT1>;
3458 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3459 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3460 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3461 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3463 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3464 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3465 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3466 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3468 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3469 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3470 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3471 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3473 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3474 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3475 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3476 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3478 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3479 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3480 RegisterClass RC, X86MemOperand x86memop,
3481 PatFrag mem_frag, ValueType OpVt> {
3482 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3483 !strconcat(OpcodeStr,
3484 " \t{$src, $dst|$dst, $src}"),
3485 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3487 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3488 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3489 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3492 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3493 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3494 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3495 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3496 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3497 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3498 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3499 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3501 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3502 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3503 (VRSQRT14PSZr VR512:$src)>;
3504 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3505 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3506 (VRSQRT14PDZr VR512:$src)>;
3508 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3509 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3510 (VRCP14PSZr VR512:$src)>;
3511 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3512 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3513 (VRCP14PDZr VR512:$src)>;
3515 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3516 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3517 X86MemOperand x86memop> {
3518 let hasSideEffects = 0, Predicates = [HasERI] in {
3519 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3520 (ins RC:$src1, RC:$src2),
3521 !strconcat(OpcodeStr,
3522 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3523 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3524 (ins RC:$src1, RC:$src2),
3525 !strconcat(OpcodeStr,
3526 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3527 []>, EVEX_4V, EVEX_B;
3528 let mayLoad = 1 in {
3529 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3530 (ins RC:$src1, x86memop:$src2),
3531 !strconcat(OpcodeStr,
3532 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3537 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3538 EVEX_CD8<32, CD8VT1>;
3539 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3540 VEX_W, EVEX_CD8<64, CD8VT1>;
3541 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3542 EVEX_CD8<32, CD8VT1>;
3543 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3544 VEX_W, EVEX_CD8<64, CD8VT1>;
3546 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3547 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3549 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3550 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3552 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3553 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3555 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3556 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3558 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3559 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3561 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3562 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3564 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3565 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3567 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3568 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3570 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3571 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3572 RegisterClass RC, X86MemOperand x86memop> {
3573 let hasSideEffects = 0, Predicates = [HasERI] in {
3574 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3575 !strconcat(OpcodeStr,
3576 " \t{$src, $dst|$dst, $src}"),
3578 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3579 !strconcat(OpcodeStr,
3580 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3582 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3583 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3587 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3588 EVEX_V512, EVEX_CD8<32, CD8VF>;
3589 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3590 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3591 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3592 EVEX_V512, EVEX_CD8<32, CD8VF>;
3593 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3594 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3596 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3597 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3598 (VRSQRT28PSZrb VR512:$src)>;
3599 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3600 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3601 (VRSQRT28PDZrb VR512:$src)>;
3603 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3604 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3605 (VRCP28PSZrb VR512:$src)>;
3606 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3607 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3608 (VRCP28PDZrb VR512:$src)>;
3610 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3611 Intrinsic V16F32Int, Intrinsic V8F64Int,
3612 OpndItins itins_s, OpndItins itins_d> {
3613 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3614 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3615 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3619 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3620 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3622 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3623 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3625 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3626 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3627 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3631 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3632 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3633 [(set VR512:$dst, (OpNode
3634 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3635 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3637 let isCodeGenOnly = 1 in {
3638 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3639 !strconcat(OpcodeStr,
3640 "ps\t{$src, $dst|$dst, $src}"),
3641 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3643 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3644 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3646 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3647 EVEX_V512, EVEX_CD8<32, CD8VF>;
3648 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3649 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3650 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3651 EVEX, EVEX_V512, VEX_W;
3652 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3653 !strconcat(OpcodeStr,
3654 "pd\t{$src, $dst|$dst, $src}"),
3655 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3656 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3657 } // isCodeGenOnly = 1
3660 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3661 Intrinsic F32Int, Intrinsic F64Int,
3662 OpndItins itins_s, OpndItins itins_d> {
3663 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3664 (ins FR32X:$src1, FR32X:$src2),
3665 !strconcat(OpcodeStr,
3666 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3667 [], itins_s.rr>, XS, EVEX_4V;
3668 let isCodeGenOnly = 1 in
3669 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3670 (ins VR128X:$src1, VR128X:$src2),
3671 !strconcat(OpcodeStr,
3672 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3674 (F32Int VR128X:$src1, VR128X:$src2))],
3675 itins_s.rr>, XS, EVEX_4V;
3676 let mayLoad = 1 in {
3677 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3678 (ins FR32X:$src1, f32mem:$src2),
3679 !strconcat(OpcodeStr,
3680 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3681 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3682 let isCodeGenOnly = 1 in
3683 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3684 (ins VR128X:$src1, ssmem:$src2),
3685 !strconcat(OpcodeStr,
3686 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3688 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3689 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3691 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3692 (ins FR64X:$src1, FR64X:$src2),
3693 !strconcat(OpcodeStr,
3694 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3696 let isCodeGenOnly = 1 in
3697 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3698 (ins VR128X:$src1, VR128X:$src2),
3699 !strconcat(OpcodeStr,
3700 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3702 (F64Int VR128X:$src1, VR128X:$src2))],
3703 itins_s.rr>, XD, EVEX_4V, VEX_W;
3704 let mayLoad = 1 in {
3705 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3706 (ins FR64X:$src1, f64mem:$src2),
3707 !strconcat(OpcodeStr,
3708 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3709 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3710 let isCodeGenOnly = 1 in
3711 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3712 (ins VR128X:$src1, sdmem:$src2),
3713 !strconcat(OpcodeStr,
3714 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3716 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3717 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3722 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3723 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3724 SSE_SQRTSS, SSE_SQRTSD>,
3725 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3726 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3727 SSE_SQRTPS, SSE_SQRTPD>;
3729 let Predicates = [HasAVX512] in {
3730 def : Pat<(f32 (fsqrt FR32X:$src)),
3731 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3732 def : Pat<(f32 (fsqrt (load addr:$src))),
3733 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3734 Requires<[OptForSize]>;
3735 def : Pat<(f64 (fsqrt FR64X:$src)),
3736 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3737 def : Pat<(f64 (fsqrt (load addr:$src))),
3738 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3739 Requires<[OptForSize]>;
3741 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3742 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3743 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3744 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3745 Requires<[OptForSize]>;
3747 def : Pat<(f32 (X86frcp FR32X:$src)),
3748 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3749 def : Pat<(f32 (X86frcp (load addr:$src))),
3750 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3751 Requires<[OptForSize]>;
3753 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3754 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3755 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3757 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3758 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3760 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3761 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3762 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3764 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3765 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3769 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3770 X86MemOperand x86memop, RegisterClass RC,
3771 PatFrag mem_frag32, PatFrag mem_frag64,
3772 Intrinsic V4F32Int, Intrinsic V2F64Int,
3774 let ExeDomain = SSEPackedSingle in {
3775 // Intrinsic operation, reg.
3776 // Vector intrinsic operation, reg
3777 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3778 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3779 !strconcat(OpcodeStr,
3780 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3781 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3783 // Vector intrinsic operation, mem
3784 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3785 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3786 !strconcat(OpcodeStr,
3787 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3789 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3790 EVEX_CD8<32, VForm>;
3791 } // ExeDomain = SSEPackedSingle
3793 let ExeDomain = SSEPackedDouble in {
3794 // Vector intrinsic operation, reg
3795 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3796 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3797 !strconcat(OpcodeStr,
3798 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3799 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3801 // Vector intrinsic operation, mem
3802 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3803 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3804 !strconcat(OpcodeStr,
3805 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3807 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3808 EVEX_CD8<64, VForm>;
3809 } // ExeDomain = SSEPackedDouble
3812 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3816 let ExeDomain = GenericDomain in {
3818 let hasSideEffects = 0 in
3819 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3820 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3821 !strconcat(OpcodeStr,
3822 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3825 // Intrinsic operation, reg.
3826 let isCodeGenOnly = 1 in
3827 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3828 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3829 !strconcat(OpcodeStr,
3830 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3831 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3833 // Intrinsic operation, mem.
3834 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3835 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3836 !strconcat(OpcodeStr,
3837 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3838 [(set VR128X:$dst, (F32Int VR128X:$src1,
3839 sse_load_f32:$src2, imm:$src3))]>,
3840 EVEX_CD8<32, CD8VT1>;
3843 let hasSideEffects = 0 in
3844 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3845 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3846 !strconcat(OpcodeStr,
3847 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3850 // Intrinsic operation, reg.
3851 let isCodeGenOnly = 1 in
3852 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3853 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3854 !strconcat(OpcodeStr,
3855 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3856 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3859 // Intrinsic operation, mem.
3860 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3861 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3862 !strconcat(OpcodeStr,
3863 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3865 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3866 VEX_W, EVEX_CD8<64, CD8VT1>;
3867 } // ExeDomain = GenericDomain
3870 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3871 X86MemOperand x86memop, RegisterClass RC,
3872 PatFrag mem_frag, Domain d> {
3873 let ExeDomain = d in {
3874 // Intrinsic operation, reg.
3875 // Vector intrinsic operation, reg
3876 def r : AVX512AIi8<opc, MRMSrcReg,
3877 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3878 !strconcat(OpcodeStr,
3879 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3882 // Vector intrinsic operation, mem
3883 def m : AVX512AIi8<opc, MRMSrcMem,
3884 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3885 !strconcat(OpcodeStr,
3886 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3892 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3893 memopv16f32, SSEPackedSingle>, EVEX_V512,
3894 EVEX_CD8<32, CD8VF>;
3896 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3897 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
3899 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3902 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3903 memopv8f64, SSEPackedDouble>, EVEX_V512,
3904 VEX_W, EVEX_CD8<64, CD8VF>;
3906 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3907 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
3909 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3911 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3912 Operand x86memop, RegisterClass RC, Domain d> {
3913 let ExeDomain = d in {
3914 def r : AVX512AIi8<opc, MRMSrcReg,
3915 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3916 !strconcat(OpcodeStr,
3917 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3920 def m : AVX512AIi8<opc, MRMSrcMem,
3921 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3922 !strconcat(OpcodeStr,
3923 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3928 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3929 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3931 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3932 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3934 def : Pat<(ffloor FR32X:$src),
3935 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3936 def : Pat<(f64 (ffloor FR64X:$src)),
3937 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3938 def : Pat<(f32 (fnearbyint FR32X:$src)),
3939 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3940 def : Pat<(f64 (fnearbyint FR64X:$src)),
3941 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3942 def : Pat<(f32 (fceil FR32X:$src)),
3943 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3944 def : Pat<(f64 (fceil FR64X:$src)),
3945 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3946 def : Pat<(f32 (frint FR32X:$src)),
3947 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3948 def : Pat<(f64 (frint FR64X:$src)),
3949 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3950 def : Pat<(f32 (ftrunc FR32X:$src)),
3951 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3952 def : Pat<(f64 (ftrunc FR64X:$src)),
3953 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3955 def : Pat<(v16f32 (ffloor VR512:$src)),
3956 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3957 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3958 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3959 def : Pat<(v16f32 (fceil VR512:$src)),
3960 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3961 def : Pat<(v16f32 (frint VR512:$src)),
3962 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3963 def : Pat<(v16f32 (ftrunc VR512:$src)),
3964 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3966 def : Pat<(v8f64 (ffloor VR512:$src)),
3967 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3968 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3969 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3970 def : Pat<(v8f64 (fceil VR512:$src)),
3971 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3972 def : Pat<(v8f64 (frint VR512:$src)),
3973 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3974 def : Pat<(v8f64 (ftrunc VR512:$src)),
3975 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3977 //-------------------------------------------------
3978 // Integer truncate and extend operations
3979 //-------------------------------------------------
3981 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3982 RegisterClass dstRC, RegisterClass srcRC,
3983 RegisterClass KRC, X86MemOperand x86memop> {
3984 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3986 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3989 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3990 (ins KRC:$mask, srcRC:$src),
3991 !strconcat(OpcodeStr,
3992 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
3995 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3996 (ins KRC:$mask, srcRC:$src),
3997 !strconcat(OpcodeStr,
3998 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4001 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
4002 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4005 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4006 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4007 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4011 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4012 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4013 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4014 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4015 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4016 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4017 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4018 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4019 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4020 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4021 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4022 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4023 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4024 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4025 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4026 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4027 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4028 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4029 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4030 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4031 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4032 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4033 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4034 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4035 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4036 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4037 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4038 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4039 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4040 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4042 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4043 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4044 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4045 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4046 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4048 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4049 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
4050 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
4051 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
4052 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4053 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
4054 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
4055 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
4058 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4059 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4060 PatFrag mem_frag, X86MemOperand x86memop,
4061 ValueType OpVT, ValueType InVT> {
4063 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4065 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4066 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
4068 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4069 (ins KRC:$mask, SrcRC:$src),
4070 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4073 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4074 (ins KRC:$mask, SrcRC:$src),
4075 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4078 let mayLoad = 1 in {
4079 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4080 (ins x86memop:$src),
4081 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
4083 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4086 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4087 (ins KRC:$mask, x86memop:$src),
4088 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4092 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4093 (ins KRC:$mask, x86memop:$src),
4094 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4100 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
4101 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4103 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
4104 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4106 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
4107 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4108 EVEX_CD8<16, CD8VH>;
4109 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
4110 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4111 EVEX_CD8<16, CD8VQ>;
4112 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
4113 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4114 EVEX_CD8<32, CD8VH>;
4116 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
4117 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4119 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
4120 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4122 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
4123 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4124 EVEX_CD8<16, CD8VH>;
4125 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
4126 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4127 EVEX_CD8<16, CD8VQ>;
4128 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
4129 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4130 EVEX_CD8<32, CD8VH>;
4132 //===----------------------------------------------------------------------===//
4133 // GATHER - SCATTER Operations
4135 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4136 RegisterClass RC, X86MemOperand memop> {
4138 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4139 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4140 (ins RC:$src1, KRC:$mask, memop:$src2),
4141 !strconcat(OpcodeStr,
4142 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4146 let ExeDomain = SSEPackedDouble in {
4147 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4148 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4149 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4150 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4153 let ExeDomain = SSEPackedSingle in {
4154 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4155 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4156 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4157 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4160 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4161 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4162 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4163 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4165 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4166 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4167 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4168 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4170 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4171 RegisterClass RC, X86MemOperand memop> {
4172 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4173 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4174 (ins memop:$dst, KRC:$mask, RC:$src2),
4175 !strconcat(OpcodeStr,
4176 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4180 let ExeDomain = SSEPackedDouble in {
4181 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4182 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4183 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4184 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4187 let ExeDomain = SSEPackedSingle in {
4188 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4189 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4190 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4191 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4194 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4195 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4196 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4197 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4199 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4200 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4201 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4202 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4205 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4206 RegisterClass KRC, X86MemOperand memop> {
4207 let Predicates = [HasPFI], hasSideEffects = 1 in
4208 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4209 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4213 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4214 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4216 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4217 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4219 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4220 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4222 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4223 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4225 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4226 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4228 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4229 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4231 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4232 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4234 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4235 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4237 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4238 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4240 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4241 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4243 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4244 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4246 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4247 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4249 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4250 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4252 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4253 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4255 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4256 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4258 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4259 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4260 //===----------------------------------------------------------------------===//
4261 // VSHUFPS - VSHUFPD Operations
4263 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4264 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4266 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4267 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4268 !strconcat(OpcodeStr,
4269 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4270 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4271 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4272 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4273 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4274 (ins RC:$src1, RC:$src2, i8imm:$src3),
4275 !strconcat(OpcodeStr,
4276 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4277 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4278 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4279 EVEX_4V, Sched<[WriteShuffle]>;
4282 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4283 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4284 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4285 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4287 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4288 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4289 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4290 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4291 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4293 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4294 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4295 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4296 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4297 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4299 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4300 X86MemOperand x86memop> {
4301 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4302 (ins RC:$src1, RC:$src2, i8imm:$src3),
4303 !strconcat(OpcodeStr,
4304 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4307 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4308 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4309 !strconcat(OpcodeStr,
4310 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4313 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4314 EVEX_V512, EVEX_CD8<32, CD8VF>;
4315 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4316 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4318 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4319 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4320 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4321 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4322 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4323 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4324 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4325 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4327 // Helper fragments to match sext vXi1 to vXiY.
4328 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4329 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4331 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4332 RegisterClass KRC, RegisterClass RC,
4333 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4335 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4336 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4338 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4339 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4341 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4342 !strconcat(OpcodeStr,
4343 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4345 let mayLoad = 1 in {
4346 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4347 (ins x86memop:$src),
4348 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4350 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4351 (ins KRC:$mask, x86memop:$src),
4352 !strconcat(OpcodeStr,
4353 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4355 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4356 (ins KRC:$mask, x86memop:$src),
4357 !strconcat(OpcodeStr,
4358 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4360 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4361 (ins x86scalar_mop:$src),
4362 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4363 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4365 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4366 (ins KRC:$mask, x86scalar_mop:$src),
4367 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4368 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4369 []>, EVEX, EVEX_B, EVEX_K;
4370 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4371 (ins KRC:$mask, x86scalar_mop:$src),
4372 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4373 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4375 []>, EVEX, EVEX_B, EVEX_KZ;
4379 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4380 i512mem, i32mem, "{1to16}">, EVEX_V512,
4381 EVEX_CD8<32, CD8VF>;
4382 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4383 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4384 EVEX_CD8<64, CD8VF>;
4387 (bc_v16i32 (v16i1sextv16i32)),
4388 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4389 (VPABSDZrr VR512:$src)>;
4391 (bc_v8i64 (v8i1sextv8i64)),
4392 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4393 (VPABSQZrr VR512:$src)>;
4395 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4396 (v16i32 immAllZerosV), (i16 -1))),
4397 (VPABSDZrr VR512:$src)>;
4398 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4399 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4400 (VPABSQZrr VR512:$src)>;
4402 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4403 RegisterClass RC, RegisterClass KRC,
4404 X86MemOperand x86memop,
4405 X86MemOperand x86scalar_mop, string BrdcstStr> {
4406 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4408 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4410 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4411 (ins x86memop:$src),
4412 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4414 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4415 (ins x86scalar_mop:$src),
4416 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4417 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4419 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4420 (ins KRC:$mask, RC:$src),
4421 !strconcat(OpcodeStr,
4422 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4424 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4425 (ins KRC:$mask, x86memop:$src),
4426 !strconcat(OpcodeStr,
4427 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4429 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4430 (ins KRC:$mask, x86scalar_mop:$src),
4431 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4432 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4434 []>, EVEX, EVEX_KZ, EVEX_B;
4436 let Constraints = "$src1 = $dst" in {
4437 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4438 (ins RC:$src1, KRC:$mask, RC:$src2),
4439 !strconcat(OpcodeStr,
4440 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4442 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4443 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4444 !strconcat(OpcodeStr,
4445 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4447 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4448 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4449 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4450 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4451 []>, EVEX, EVEX_K, EVEX_B;
4455 let Predicates = [HasCDI] in {
4456 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4457 i512mem, i32mem, "{1to16}">,
4458 EVEX_V512, EVEX_CD8<32, CD8VF>;
4461 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4462 i512mem, i64mem, "{1to8}">,
4463 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4467 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4469 (VPCONFLICTDrrk VR512:$src1,
4470 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4472 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4474 (VPCONFLICTQrrk VR512:$src1,
4475 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4477 let Predicates = [HasCDI] in {
4478 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4479 i512mem, i32mem, "{1to16}">,
4480 EVEX_V512, EVEX_CD8<32, CD8VF>;
4483 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4484 i512mem, i64mem, "{1to8}">,
4485 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4489 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4491 (VPLZCNTDrrk VR512:$src1,
4492 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4494 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4496 (VPLZCNTQrrk VR512:$src1,
4497 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4499 def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4500 (VPLZCNTDrm addr:$src)>;
4501 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4502 (VPLZCNTDrr VR512:$src)>;
4503 def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4504 (VPLZCNTQrm addr:$src)>;
4505 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4506 (VPLZCNTQrr VR512:$src)>;
4508 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4509 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4510 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4512 def : Pat<(store VK1:$src, addr:$dst),
4513 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4515 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4516 (truncstore node:$val, node:$ptr), [{
4517 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4520 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4521 (MOV8mr addr:$dst, GR8:$src)>;