1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insertps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
625 def : Pat<(v16f32 (int_x86_avx512_mask_vpermt_ps_512 (v16i32 VR512:$idx),
626 (v16f32 VR512:$src1), (v16f32 VR512:$src2), (i16 -1))),
627 (VPERMT2PSrr VR512:$src1, VR512:$idx, VR512:$src2)>;
629 def : Pat<(v16i32 (int_x86_avx512_mask_vpermt_d_512 (v16i32 VR512:$idx),
630 (v16i32 VR512:$src1), (v16i32 VR512:$src2), (i16 -1))),
631 (VPERMT2Drr VR512:$src1, VR512:$idx, VR512:$src2)>;
633 def : Pat<(v8f64 (int_x86_avx512_mask_vpermt_pd_512 (v8i64 VR512:$idx),
634 (v8f64 VR512:$src1), (v8f64 VR512:$src2), (i8 -1))),
635 (VPERMT2PDrr VR512:$src1, VR512:$idx, VR512:$src2)>;
637 def : Pat<(v8i64 (int_x86_avx512_mask_vpermt_q_512 (v8i64 VR512:$idx),
638 (v8i64 VR512:$src1), (v8i64 VR512:$src2), (i8 -1))),
639 (VPERMT2Qrr VR512:$src1, VR512:$idx, VR512:$src2)>;
640 //===----------------------------------------------------------------------===//
641 // AVX-512 - BLEND using mask
643 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
644 RegisterClass KRC, RegisterClass RC,
645 X86MemOperand x86memop, PatFrag mem_frag,
646 SDNode OpNode, ValueType vt> {
647 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
648 (ins KRC:$mask, RC:$src1, RC:$src2),
649 !strconcat(OpcodeStr,
650 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
651 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
652 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
654 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
655 (ins KRC:$mask, RC:$src1, x86memop:$src2),
656 !strconcat(OpcodeStr,
657 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
658 []>, EVEX_4V, EVEX_K;
661 let ExeDomain = SSEPackedSingle in
662 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
663 VK16WM, VR512, f512mem,
664 memopv16f32, vselect, v16f32>,
665 EVEX_CD8<32, CD8VF>, EVEX_V512;
666 let ExeDomain = SSEPackedDouble in
667 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
668 VK8WM, VR512, f512mem,
669 memopv8f64, vselect, v8f64>,
670 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
672 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
673 (v16f32 VR512:$src2), (i16 GR16:$mask))),
674 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
675 VR512:$src1, VR512:$src2)>;
677 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
678 (v8f64 VR512:$src2), (i8 GR8:$mask))),
679 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
680 VR512:$src1, VR512:$src2)>;
682 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
683 VK16WM, VR512, f512mem,
684 memopv16i32, vselect, v16i32>,
685 EVEX_CD8<32, CD8VF>, EVEX_V512;
687 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
688 VK8WM, VR512, f512mem,
689 memopv8i64, vselect, v8i64>,
690 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
692 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
693 (v16i32 VR512:$src2), (i16 GR16:$mask))),
694 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
695 VR512:$src1, VR512:$src2)>;
697 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
698 (v8i64 VR512:$src2), (i8 GR8:$mask))),
699 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
700 VR512:$src1, VR512:$src2)>;
702 let Predicates = [HasAVX512] in {
703 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
704 (v8f32 VR256X:$src2))),
706 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
707 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
708 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
710 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
711 (v8i32 VR256X:$src2))),
713 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
714 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
715 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
717 //===----------------------------------------------------------------------===//
718 // Compare Instructions
719 //===----------------------------------------------------------------------===//
721 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
722 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
723 Operand CC, SDNode OpNode, ValueType VT,
724 PatFrag ld_frag, string asm, string asm_alt> {
725 def rr : AVX512Ii8<0xC2, MRMSrcReg,
726 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
727 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
728 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
729 def rm : AVX512Ii8<0xC2, MRMSrcMem,
730 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
731 [(set VK1:$dst, (OpNode (VT RC:$src1),
732 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
733 let isAsmParserOnly = 1, hasSideEffects = 0 in {
734 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
735 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
736 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
737 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
738 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
739 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
743 let Predicates = [HasAVX512] in {
744 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
745 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
746 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
748 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
749 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
750 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
754 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
755 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
756 SDNode OpNode, ValueType vt> {
757 def rr : AVX512BI<opc, MRMSrcReg,
758 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
759 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
760 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
761 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
762 def rm : AVX512BI<opc, MRMSrcMem,
763 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
764 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
765 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
766 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
769 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
770 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
772 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
773 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
774 VEX_W, EVEX_CD8<64, CD8VF>;
776 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
777 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
779 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
780 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
781 VEX_W, EVEX_CD8<64, CD8VF>;
783 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
784 (COPY_TO_REGCLASS (VPCMPGTDZrr
785 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
786 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
788 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
789 (COPY_TO_REGCLASS (VPCMPEQDZrr
790 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
791 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
793 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
794 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
795 SDNode OpNode, ValueType vt, Operand CC, string asm,
797 def rri : AVX512AIi8<opc, MRMSrcReg,
798 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
799 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
800 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
801 def rmi : AVX512AIi8<opc, MRMSrcMem,
802 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
803 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
804 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
805 // Accept explicit immediate argument form instead of comparison code.
806 let isAsmParserOnly = 1, hasSideEffects = 0 in {
807 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
808 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
809 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
810 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
811 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
812 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
816 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
817 X86cmpm, v16i32, AVXCC,
818 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
819 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
820 EVEX_V512, EVEX_CD8<32, CD8VF>;
821 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
822 X86cmpmu, v16i32, AVXCC,
823 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
824 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
825 EVEX_V512, EVEX_CD8<32, CD8VF>;
827 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
828 X86cmpm, v8i64, AVXCC,
829 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
830 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
831 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
832 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
833 X86cmpmu, v8i64, AVXCC,
834 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
835 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
836 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
838 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
839 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
840 X86MemOperand x86memop, ValueType vt,
841 string suffix, Domain d> {
842 def rri : AVX512PIi8<0xC2, MRMSrcReg,
843 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
844 !strconcat("vcmp${cc}", suffix,
845 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
846 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
847 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
848 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
849 !strconcat("vcmp${cc}", suffix,
850 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
852 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
853 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
854 !strconcat("vcmp${cc}", suffix,
855 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
857 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
859 // Accept explicit immediate argument form instead of comparison code.
860 let isAsmParserOnly = 1, hasSideEffects = 0 in {
861 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
862 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
863 !strconcat("vcmp", suffix,
864 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
865 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
866 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
867 !strconcat("vcmp", suffix,
868 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
872 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
873 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
875 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
876 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
879 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
880 (COPY_TO_REGCLASS (VCMPPSZrri
881 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
882 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
884 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
885 (COPY_TO_REGCLASS (VPCMPDZrri
886 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
887 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
889 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
890 (COPY_TO_REGCLASS (VPCMPUDZrri
891 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
892 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
895 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
896 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
898 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
899 (I8Imm imm:$cc)), GR16)>;
901 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
902 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
904 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
905 (I8Imm imm:$cc)), GR8)>;
907 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
908 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
910 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
911 (I8Imm imm:$cc)), GR16)>;
913 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
914 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
916 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
917 (I8Imm imm:$cc)), GR8)>;
919 // Mask register copy, including
920 // - copy between mask registers
921 // - load/store mask registers
922 // - copy from GPR to mask register and vice versa
924 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
925 string OpcodeStr, RegisterClass KRC,
926 ValueType vt, X86MemOperand x86memop> {
927 let hasSideEffects = 0 in {
928 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
929 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
931 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
932 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
933 [(set KRC:$dst, (vt (load addr:$src)))]>;
935 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
936 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
940 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
942 RegisterClass KRC, RegisterClass GRC> {
943 let hasSideEffects = 0 in {
944 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
945 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
946 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
947 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
951 let Predicates = [HasAVX512] in {
952 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
954 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
958 let Predicates = [HasAVX512] in {
959 // GR16 from/to 16-bit mask
960 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
961 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
962 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
963 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
965 // Store kreg in memory
966 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
967 (KMOVWmk addr:$dst, VK16:$src)>;
969 def : Pat<(store VK8:$src, addr:$dst),
970 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
972 def : Pat<(i1 (load addr:$src)),
973 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
975 def : Pat<(v8i1 (load addr:$src)),
976 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
978 def : Pat<(i1 (trunc (i32 GR32:$src))),
979 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
981 def : Pat<(i1 (trunc (i8 GR8:$src))),
983 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
985 def : Pat<(i1 (trunc (i16 GR16:$src))),
987 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
990 def : Pat<(i32 (zext VK1:$src)),
991 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
992 def : Pat<(i8 (zext VK1:$src)),
995 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
996 def : Pat<(i64 (zext VK1:$src)),
997 (AND64ri8 (SUBREG_TO_REG (i64 0),
998 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
999 def : Pat<(i16 (zext VK1:$src)),
1001 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1003 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1004 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1005 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1006 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1008 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1009 let Predicates = [HasAVX512] in {
1010 // GR from/to 8-bit mask without native support
1011 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1013 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1015 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1017 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1020 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1021 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1022 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1023 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1027 // Mask unary operation
1029 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1030 RegisterClass KRC, SDPatternOperator OpNode> {
1031 let Predicates = [HasAVX512] in
1032 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1033 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1034 [(set KRC:$dst, (OpNode KRC:$src))]>;
1037 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1038 SDPatternOperator OpNode> {
1039 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1043 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1045 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1046 let Predicates = [HasAVX512] in
1047 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1049 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1050 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1052 defm : avx512_mask_unop_int<"knot", "KNOT">;
1054 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1055 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1056 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1058 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1059 def : Pat<(not VK8:$src),
1061 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1063 // Mask binary operation
1064 // - KAND, KANDN, KOR, KXNOR, KXOR
1065 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1066 RegisterClass KRC, SDPatternOperator OpNode> {
1067 let Predicates = [HasAVX512] in
1068 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1069 !strconcat(OpcodeStr,
1070 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1071 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1074 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1075 SDPatternOperator OpNode> {
1076 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1080 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1081 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1083 let isCommutable = 1 in {
1084 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1085 let isCommutable = 0 in
1086 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1087 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1088 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1089 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1092 def : Pat<(xor VK1:$src1, VK1:$src2),
1093 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1094 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1096 def : Pat<(or VK1:$src1, VK1:$src2),
1097 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1098 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1100 def : Pat<(and VK1:$src1, VK1:$src2),
1101 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1102 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1104 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1105 let Predicates = [HasAVX512] in
1106 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1107 (i16 GR16:$src1), (i16 GR16:$src2)),
1108 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1109 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1110 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1113 defm : avx512_mask_binop_int<"kand", "KAND">;
1114 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1115 defm : avx512_mask_binop_int<"kor", "KOR">;
1116 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1117 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1119 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1120 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1121 let Predicates = [HasAVX512] in
1122 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1124 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1125 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1128 defm : avx512_binop_pat<and, KANDWrr>;
1129 defm : avx512_binop_pat<andn, KANDNWrr>;
1130 defm : avx512_binop_pat<or, KORWrr>;
1131 defm : avx512_binop_pat<xnor, KXNORWrr>;
1132 defm : avx512_binop_pat<xor, KXORWrr>;
1135 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1136 RegisterClass KRC> {
1137 let Predicates = [HasAVX512] in
1138 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1139 !strconcat(OpcodeStr,
1140 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1143 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1144 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1148 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1149 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1150 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1151 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1154 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1155 let Predicates = [HasAVX512] in
1156 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1157 (i16 GR16:$src1), (i16 GR16:$src2)),
1158 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1159 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1160 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1162 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1165 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1167 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1168 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1169 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1170 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1173 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1174 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1178 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1180 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1181 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1182 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1185 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1187 let Predicates = [HasAVX512] in
1188 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1189 !strconcat(OpcodeStr,
1190 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1191 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1194 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1196 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1200 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1201 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1203 // Mask setting all 0s or 1s
1204 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1205 let Predicates = [HasAVX512] in
1206 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1207 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1208 [(set KRC:$dst, (VT Val))]>;
1211 multiclass avx512_mask_setop_w<PatFrag Val> {
1212 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1213 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1216 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1217 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1219 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1220 let Predicates = [HasAVX512] in {
1221 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1222 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1223 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1224 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1225 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1227 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1228 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1230 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1231 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1233 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1234 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1236 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1237 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1239 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1240 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1241 //===----------------------------------------------------------------------===//
1242 // AVX-512 - Aligned and unaligned load and store
1245 multiclass avx512_load<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1246 X86MemOperand x86memop, PatFrag ld_frag,
1247 string asm, Domain d,
1248 ValueType vt, bit IsReMaterializable = 1> {
1249 let hasSideEffects = 0 in {
1250 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1251 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1253 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
1255 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1256 [], d>, EVEX, EVEX_KZ;
1258 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1259 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1260 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1261 [(set (vt RC:$dst), (ld_frag addr:$src))], d>, EVEX;
1262 let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
1263 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1264 (ins RC:$src1, KRC:$mask, RC:$src2),
1266 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1269 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1270 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1272 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1273 [], d>, EVEX, EVEX_K;
1276 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1277 (ins KRC:$mask, x86memop:$src2),
1279 " \t{$src2, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src2}"),
1280 [], d>, EVEX, EVEX_KZ;
1283 multiclass avx512_store<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1284 X86MemOperand x86memop, PatFrag store_frag,
1285 string asm, Domain d, ValueType vt> {
1286 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1287 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
1288 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1290 let Constraints = "$src1 = $dst" in
1291 def alt_rrk : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1292 (ins RC:$src1, KRC:$mask, RC:$src2),
1294 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1296 def alt_rrkz : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1297 (ins KRC:$mask, RC:$src),
1299 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1300 [], d>, EVEX, EVEX_KZ;
1302 let mayStore = 1 in {
1303 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1304 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1305 [(store_frag (vt RC:$src), addr:$dst)], d>, EVEX;
1306 def mrk : AVX512PI<opc, MRMDestMem, (outs),
1307 (ins x86memop:$dst, KRC:$mask, RC:$src),
1309 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1310 [], d>, EVEX, EVEX_K;
1311 def mrkz : AVX512PI<opc, MRMDestMem, (outs),
1312 (ins x86memop:$dst, KRC:$mask, RC:$src),
1314 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1315 [], d>, EVEX, EVEX_KZ;
1319 defm VMOVAPSZ : avx512_load<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1320 "vmovaps", SSEPackedSingle, v16f32>,
1321 avx512_store<0x29, VR512, VK16WM, f512mem, alignedstore512,
1322 "vmovaps", SSEPackedSingle, v16f32>,
1323 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1324 defm VMOVAPDZ : avx512_load<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1325 "vmovapd", SSEPackedDouble, v8f64>,
1326 avx512_store<0x29, VR512, VK8WM, f512mem, alignedstore512,
1327 "vmovapd", SSEPackedDouble, v8f64>,
1328 PD, EVEX_V512, VEX_W,
1329 EVEX_CD8<64, CD8VF>;
1330 defm VMOVUPSZ : avx512_load<0x10, VR512, VK16WM, f512mem, loadv16f32,
1331 "vmovups", SSEPackedSingle, v16f32>,
1332 avx512_store<0x11, VR512, VK16WM, f512mem, store,
1333 "vmovups", SSEPackedSingle, v16f32>,
1334 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1335 defm VMOVUPDZ : avx512_load<0x10, VR512, VK8WM, f512mem, loadv8f64,
1336 "vmovupd", SSEPackedDouble, v8f64, 0>,
1337 avx512_store<0x11, VR512, VK8WM, f512mem, store,
1338 "vmovupd", SSEPackedDouble, v8f64>,
1339 PD, EVEX_V512, VEX_W,
1340 EVEX_CD8<64, CD8VF>;
1341 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
1342 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
1343 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1345 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1346 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1347 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1349 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1351 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1353 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1355 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1358 defm VMOVDQA32: avx512_load<0x6F, VR512, VK16WM, i512mem, alignedloadv16i32,
1359 "vmovdqa32", SSEPackedInt, v16i32>,
1360 avx512_store<0x7F, VR512, VK16WM, i512mem, alignedstore512,
1361 "vmovdqa32", SSEPackedInt, v16i32>,
1362 PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1363 defm VMOVDQA64: avx512_load<0x6F, VR512, VK8WM, i512mem, alignedloadv8i64,
1364 "vmovdqa64", SSEPackedInt, v8i64>,
1365 avx512_store<0x7F, VR512, VK8WM, i512mem, alignedstore512,
1366 "vmovdqa64", SSEPackedInt, v8i64>,
1367 PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1368 defm VMOVDQU32: avx512_load<0x6F, VR512, VK16WM, i512mem, load,
1369 "vmovdqu32", SSEPackedInt, v16i32>,
1370 avx512_store<0x7F, VR512, VK16WM, i512mem, store,
1371 "vmovdqu32", SSEPackedInt, v16i32>,
1372 XS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1373 defm VMOVDQU64: avx512_load<0x6F, VR512, VK8WM, i512mem, load,
1374 "vmovdqu64", SSEPackedInt, v8i64>,
1375 avx512_store<0x7F, VR512, VK8WM, i512mem, store,
1376 "vmovdqu64", SSEPackedInt, v8i64>,
1377 XS, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1379 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
1380 (v16i32 immAllZerosV), GR16:$mask)),
1381 (VMOVDQU32rmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
1383 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
1384 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
1385 (VMOVDQU64rmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
1387 let AddedComplexity = 20 in {
1388 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1389 (bc_v8i64 (v16i32 immAllZerosV)))),
1390 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1392 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1393 (v8i64 VR512:$src))),
1394 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1397 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1398 (v16i32 immAllZerosV))),
1399 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1401 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1402 (v16i32 VR512:$src))),
1403 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1405 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1406 (v16f32 VR512:$src2))),
1407 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1408 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1409 (v8f64 VR512:$src2))),
1410 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1411 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1412 (v16i32 VR512:$src2))),
1413 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1414 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1415 (v8i64 VR512:$src2))),
1416 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1418 // Move Int Doubleword to Packed Double Int
1420 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1421 "vmovd\t{$src, $dst|$dst, $src}",
1423 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1425 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1426 "vmovd\t{$src, $dst|$dst, $src}",
1428 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1429 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1430 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1431 "vmovq\t{$src, $dst|$dst, $src}",
1433 (v2i64 (scalar_to_vector GR64:$src)))],
1434 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1435 let isCodeGenOnly = 1 in {
1436 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1437 "vmovq\t{$src, $dst|$dst, $src}",
1438 [(set FR64:$dst, (bitconvert GR64:$src))],
1439 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1440 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1441 "vmovq\t{$src, $dst|$dst, $src}",
1442 [(set GR64:$dst, (bitconvert FR64:$src))],
1443 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1445 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1446 "vmovq\t{$src, $dst|$dst, $src}",
1447 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1448 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1449 EVEX_CD8<64, CD8VT1>;
1451 // Move Int Doubleword to Single Scalar
1453 let isCodeGenOnly = 1 in {
1454 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1455 "vmovd\t{$src, $dst|$dst, $src}",
1456 [(set FR32X:$dst, (bitconvert GR32:$src))],
1457 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1459 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1460 "vmovd\t{$src, $dst|$dst, $src}",
1461 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1462 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1465 // Move doubleword from xmm register to r/m32
1467 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1468 "vmovd\t{$src, $dst|$dst, $src}",
1469 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1470 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1472 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1473 (ins i32mem:$dst, VR128X:$src),
1474 "vmovd\t{$src, $dst|$dst, $src}",
1475 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1476 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1477 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1479 // Move quadword from xmm1 register to r/m64
1481 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1482 "vmovq\t{$src, $dst|$dst, $src}",
1483 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1485 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1486 Requires<[HasAVX512, In64BitMode]>;
1488 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1489 (ins i64mem:$dst, VR128X:$src),
1490 "vmovq\t{$src, $dst|$dst, $src}",
1491 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1492 addr:$dst)], IIC_SSE_MOVDQ>,
1493 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1494 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1496 // Move Scalar Single to Double Int
1498 let isCodeGenOnly = 1 in {
1499 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1501 "vmovd\t{$src, $dst|$dst, $src}",
1502 [(set GR32:$dst, (bitconvert FR32X:$src))],
1503 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1504 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1505 (ins i32mem:$dst, FR32X:$src),
1506 "vmovd\t{$src, $dst|$dst, $src}",
1507 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1508 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1511 // Move Quadword Int to Packed Quadword Int
1513 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1515 "vmovq\t{$src, $dst|$dst, $src}",
1517 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1518 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1520 //===----------------------------------------------------------------------===//
1521 // AVX-512 MOVSS, MOVSD
1522 //===----------------------------------------------------------------------===//
1524 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1525 SDNode OpNode, ValueType vt,
1526 X86MemOperand x86memop, PatFrag mem_pat> {
1527 let hasSideEffects = 0 in {
1528 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1529 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1530 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1531 (scalar_to_vector RC:$src2))))],
1532 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1533 let Constraints = "$src1 = $dst" in
1534 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1535 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1537 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1538 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1539 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1540 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1541 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1543 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1544 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1545 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1547 } //hasSideEffects = 0
1550 let ExeDomain = SSEPackedSingle in
1551 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1552 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1554 let ExeDomain = SSEPackedDouble in
1555 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1556 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1558 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1559 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1560 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1562 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1563 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1564 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1566 // For the disassembler
1567 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1568 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1569 (ins VR128X:$src1, FR32X:$src2),
1570 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1572 XS, EVEX_4V, VEX_LIG;
1573 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1574 (ins VR128X:$src1, FR64X:$src2),
1575 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1577 XD, EVEX_4V, VEX_LIG, VEX_W;
1580 let Predicates = [HasAVX512] in {
1581 let AddedComplexity = 15 in {
1582 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1583 // MOVS{S,D} to the lower bits.
1584 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1585 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1586 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1587 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1588 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1589 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1590 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1591 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1593 // Move low f32 and clear high bits.
1594 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1595 (SUBREG_TO_REG (i32 0),
1596 (VMOVSSZrr (v4f32 (V_SET0)),
1597 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1598 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1599 (SUBREG_TO_REG (i32 0),
1600 (VMOVSSZrr (v4i32 (V_SET0)),
1601 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1604 let AddedComplexity = 20 in {
1605 // MOVSSrm zeros the high parts of the register; represent this
1606 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1607 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1608 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1609 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1610 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1611 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1612 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1614 // MOVSDrm zeros the high parts of the register; represent this
1615 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1616 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1617 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1618 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1619 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1620 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1621 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1622 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1623 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1624 def : Pat<(v2f64 (X86vzload addr:$src)),
1625 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1627 // Represent the same patterns above but in the form they appear for
1629 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1630 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1631 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1632 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1633 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1634 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1635 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1636 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1637 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1639 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1640 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1641 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1642 FR32X:$src)), sub_xmm)>;
1643 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1644 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1645 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1646 FR64X:$src)), sub_xmm)>;
1647 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1648 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1649 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1651 // Move low f64 and clear high bits.
1652 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1653 (SUBREG_TO_REG (i32 0),
1654 (VMOVSDZrr (v2f64 (V_SET0)),
1655 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1657 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1658 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1659 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1661 // Extract and store.
1662 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1664 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1665 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1667 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1669 // Shuffle with VMOVSS
1670 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1671 (VMOVSSZrr (v4i32 VR128X:$src1),
1672 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1673 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1674 (VMOVSSZrr (v4f32 VR128X:$src1),
1675 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1678 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1679 (SUBREG_TO_REG (i32 0),
1680 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1681 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1683 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1684 (SUBREG_TO_REG (i32 0),
1685 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1686 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1689 // Shuffle with VMOVSD
1690 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1691 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1692 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1693 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1694 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1695 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1696 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1697 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1700 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1701 (SUBREG_TO_REG (i32 0),
1702 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1703 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1705 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1706 (SUBREG_TO_REG (i32 0),
1707 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1708 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1711 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1712 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1713 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1714 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1715 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1716 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1717 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1718 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1721 let AddedComplexity = 15 in
1722 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1724 "vmovq\t{$src, $dst|$dst, $src}",
1725 [(set VR128X:$dst, (v2i64 (X86vzmovl
1726 (v2i64 VR128X:$src))))],
1727 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1729 let AddedComplexity = 20 in
1730 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1732 "vmovq\t{$src, $dst|$dst, $src}",
1733 [(set VR128X:$dst, (v2i64 (X86vzmovl
1734 (loadv2i64 addr:$src))))],
1735 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1736 EVEX_CD8<8, CD8VT8>;
1738 let Predicates = [HasAVX512] in {
1739 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1740 let AddedComplexity = 20 in {
1741 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1742 (VMOVDI2PDIZrm addr:$src)>;
1743 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1744 (VMOV64toPQIZrr GR64:$src)>;
1745 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1746 (VMOVDI2PDIZrr GR32:$src)>;
1748 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1749 (VMOVDI2PDIZrm addr:$src)>;
1750 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1751 (VMOVDI2PDIZrm addr:$src)>;
1752 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1753 (VMOVZPQILo2PQIZrm addr:$src)>;
1754 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1755 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1756 def : Pat<(v2i64 (X86vzload addr:$src)),
1757 (VMOVZPQILo2PQIZrm addr:$src)>;
1760 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1761 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1762 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1763 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1764 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1765 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1766 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1769 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1770 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1772 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1773 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1775 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1776 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1778 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1779 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1781 //===----------------------------------------------------------------------===//
1782 // AVX-512 - Integer arithmetic
1784 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1785 ValueType OpVT, RegisterClass KRC,
1786 RegisterClass RC, PatFrag memop_frag,
1787 X86MemOperand x86memop, PatFrag scalar_mfrag,
1788 X86MemOperand x86scalar_mop, string BrdcstStr,
1789 OpndItins itins, bit IsCommutable = 0> {
1790 let isCommutable = IsCommutable in
1791 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1792 (ins RC:$src1, RC:$src2),
1793 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1794 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1796 let AddedComplexity = 30 in {
1797 let Constraints = "$src0 = $dst" in
1798 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1799 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
1800 !strconcat(OpcodeStr,
1801 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1802 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1803 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1805 itins.rr>, EVEX_4V, EVEX_K;
1806 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1807 (ins KRC:$mask, RC:$src1, RC:$src2),
1808 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1809 "|$dst {${mask}} {z}, $src1, $src2}"),
1810 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1811 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
1812 (OpVT immAllZerosV))))],
1813 itins.rr>, EVEX_4V, EVEX_KZ;
1816 let mayLoad = 1 in {
1817 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1818 (ins RC:$src1, x86memop:$src2),
1819 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1820 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1822 let AddedComplexity = 30 in {
1823 let Constraints = "$src0 = $dst" in
1824 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1825 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
1826 !strconcat(OpcodeStr,
1827 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1828 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1829 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1831 itins.rm>, EVEX_4V, EVEX_K;
1832 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1833 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1834 !strconcat(OpcodeStr,
1835 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1836 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1837 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
1838 (OpVT immAllZerosV))))],
1839 itins.rm>, EVEX_4V, EVEX_KZ;
1841 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1842 (ins RC:$src1, x86scalar_mop:$src2),
1843 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1844 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1845 [(set RC:$dst, (OpNode RC:$src1,
1846 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1847 itins.rm>, EVEX_4V, EVEX_B;
1848 let AddedComplexity = 30 in {
1849 let Constraints = "$src0 = $dst" in
1850 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1851 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1852 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1853 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1855 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1856 (OpNode (OpVT RC:$src1),
1857 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1859 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1860 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1861 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1862 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1863 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1865 [(set RC:$dst, (OpVT (vselect KRC:$mask,
1866 (OpNode (OpVT RC:$src1),
1867 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
1868 (OpVT immAllZerosV))))],
1869 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1874 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
1875 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
1876 PatFrag memop_frag, X86MemOperand x86memop,
1877 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
1878 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
1879 let isCommutable = IsCommutable in
1881 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1882 (ins RC:$src1, RC:$src2),
1883 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1885 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1886 (ins KRC:$mask, RC:$src1, RC:$src2),
1887 !strconcat(OpcodeStr,
1888 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1889 [], itins.rr>, EVEX_4V, EVEX_K;
1890 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1891 (ins KRC:$mask, RC:$src1, RC:$src2),
1892 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
1893 "|$dst {${mask}} {z}, $src1, $src2}"),
1894 [], itins.rr>, EVEX_4V, EVEX_KZ;
1896 let mayLoad = 1 in {
1897 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1898 (ins RC:$src1, x86memop:$src2),
1899 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1901 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1902 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1903 !strconcat(OpcodeStr,
1904 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1905 [], itins.rm>, EVEX_4V, EVEX_K;
1906 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1907 (ins KRC:$mask, RC:$src1, x86memop:$src2),
1908 !strconcat(OpcodeStr,
1909 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
1910 [], itins.rm>, EVEX_4V, EVEX_KZ;
1911 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1912 (ins RC:$src1, x86scalar_mop:$src2),
1913 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1914 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1915 [], itins.rm>, EVEX_4V, EVEX_B;
1916 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1917 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1918 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1919 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
1921 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
1922 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1923 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
1924 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1925 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
1927 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
1931 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
1932 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1933 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1935 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
1936 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1937 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1939 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
1940 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1941 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1943 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
1944 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1945 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1947 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
1948 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1949 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1951 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
1952 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1953 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
1954 EVEX_CD8<64, CD8VF>, VEX_W;
1956 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
1957 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1958 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
1960 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1961 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1963 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1964 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1965 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1966 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1967 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1968 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1970 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
1971 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1972 SSE_INTALU_ITINS_P, 1>,
1973 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1974 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
1975 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1976 SSE_INTALU_ITINS_P, 0>,
1977 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1979 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
1980 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1981 SSE_INTALU_ITINS_P, 1>,
1982 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1983 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
1984 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1985 SSE_INTALU_ITINS_P, 0>,
1986 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1988 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
1989 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1990 SSE_INTALU_ITINS_P, 1>,
1991 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1992 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
1993 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
1994 SSE_INTALU_ITINS_P, 0>,
1995 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1997 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
1998 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1999 SSE_INTALU_ITINS_P, 1>,
2000 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2001 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2002 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2003 SSE_INTALU_ITINS_P, 0>,
2004 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2006 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2007 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2008 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2009 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2010 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2011 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2012 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2013 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2014 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2015 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2016 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2017 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2018 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2019 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2020 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2021 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2022 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2023 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2024 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2025 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2026 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2027 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2028 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2029 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
2030 //===----------------------------------------------------------------------===//
2031 // AVX-512 - Unpack Instructions
2032 //===----------------------------------------------------------------------===//
2034 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2035 PatFrag mem_frag, RegisterClass RC,
2036 X86MemOperand x86memop, string asm,
2038 def rr : AVX512PI<opc, MRMSrcReg,
2039 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2041 (vt (OpNode RC:$src1, RC:$src2)))],
2043 def rm : AVX512PI<opc, MRMSrcMem,
2044 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2046 (vt (OpNode RC:$src1,
2047 (bitconvert (mem_frag addr:$src2)))))],
2051 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2052 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2053 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2054 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2055 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2056 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2057 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2058 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2059 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
2060 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2061 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2062 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2064 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2065 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2066 X86MemOperand x86memop> {
2067 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2068 (ins RC:$src1, RC:$src2),
2069 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2070 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2071 IIC_SSE_UNPCK>, EVEX_4V;
2072 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2073 (ins RC:$src1, x86memop:$src2),
2074 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2075 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2076 (bitconvert (memop_frag addr:$src2)))))],
2077 IIC_SSE_UNPCK>, EVEX_4V;
2079 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2080 VR512, memopv16i32, i512mem>, EVEX_V512,
2081 EVEX_CD8<32, CD8VF>;
2082 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2083 VR512, memopv8i64, i512mem>, EVEX_V512,
2084 VEX_W, EVEX_CD8<64, CD8VF>;
2085 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2086 VR512, memopv16i32, i512mem>, EVEX_V512,
2087 EVEX_CD8<32, CD8VF>;
2088 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2089 VR512, memopv8i64, i512mem>, EVEX_V512,
2090 VEX_W, EVEX_CD8<64, CD8VF>;
2091 //===----------------------------------------------------------------------===//
2095 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2096 SDNode OpNode, PatFrag mem_frag,
2097 X86MemOperand x86memop, ValueType OpVT> {
2098 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2099 (ins RC:$src1, i8imm:$src2),
2100 !strconcat(OpcodeStr,
2101 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2103 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2105 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2106 (ins x86memop:$src1, i8imm:$src2),
2107 !strconcat(OpcodeStr,
2108 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2110 (OpVT (OpNode (mem_frag addr:$src1),
2111 (i8 imm:$src2))))]>, EVEX;
2114 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
2115 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
2117 let ExeDomain = SSEPackedSingle in
2118 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
2119 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
2120 EVEX_CD8<32, CD8VF>;
2121 let ExeDomain = SSEPackedDouble in
2122 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
2123 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
2124 VEX_W, EVEX_CD8<32, CD8VF>;
2126 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2127 (VPERMILPSZri VR512:$src1, imm:$imm)>;
2128 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
2129 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2131 //===----------------------------------------------------------------------===//
2132 // AVX-512 Logical Instructions
2133 //===----------------------------------------------------------------------===//
2135 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
2136 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2137 EVEX_V512, EVEX_CD8<32, CD8VF>;
2138 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
2139 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2140 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2141 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
2142 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2143 EVEX_V512, EVEX_CD8<32, CD8VF>;
2144 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
2145 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2146 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2147 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
2148 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2149 EVEX_V512, EVEX_CD8<32, CD8VF>;
2150 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
2151 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2152 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2153 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
2154 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2155 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2156 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2157 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2158 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2160 //===----------------------------------------------------------------------===//
2161 // AVX-512 FP arithmetic
2162 //===----------------------------------------------------------------------===//
2164 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2166 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2167 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2168 EVEX_CD8<32, CD8VT1>;
2169 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2170 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2171 EVEX_CD8<64, CD8VT1>;
2174 let isCommutable = 1 in {
2175 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2176 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2177 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2178 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2180 let isCommutable = 0 in {
2181 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2182 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2185 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2187 RegisterClass RC, ValueType vt,
2188 X86MemOperand x86memop, PatFrag mem_frag,
2189 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2191 Domain d, OpndItins itins, bit commutable> {
2192 let isCommutable = commutable in {
2193 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2194 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2195 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2198 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2199 !strconcat(OpcodeStr,
2200 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2201 [], itins.rr, d>, EVEX_4V, EVEX_K;
2203 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2204 !strconcat(OpcodeStr,
2205 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2206 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2209 let mayLoad = 1 in {
2210 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2211 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2212 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2213 itins.rm, d>, EVEX_4V;
2215 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2216 (ins RC:$src1, x86scalar_mop:$src2),
2217 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2218 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2219 [(set RC:$dst, (OpNode RC:$src1,
2220 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2221 itins.rm, d>, EVEX_4V, EVEX_B;
2223 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2224 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2225 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2226 [], itins.rm, d>, EVEX_4V, EVEX_K;
2228 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2229 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2230 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2231 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2233 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2234 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2235 " \t{${src2}", BrdcstStr,
2236 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2237 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2239 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2240 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2241 " \t{${src2}", BrdcstStr,
2242 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2244 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2248 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
2249 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2250 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2252 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
2253 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2254 SSE_ALU_ITINS_P.d, 1>,
2255 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2257 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
2258 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2259 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2260 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
2261 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2262 SSE_ALU_ITINS_P.d, 1>,
2263 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2265 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
2266 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2267 SSE_ALU_ITINS_P.s, 1>,
2268 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2269 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
2270 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2271 SSE_ALU_ITINS_P.s, 1>,
2272 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2274 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
2275 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2276 SSE_ALU_ITINS_P.d, 1>,
2277 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2278 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
2279 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2280 SSE_ALU_ITINS_P.d, 1>,
2281 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2283 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
2284 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2285 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2286 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
2287 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2288 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2290 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
2291 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2292 SSE_ALU_ITINS_P.d, 0>,
2293 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2294 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
2295 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2296 SSE_ALU_ITINS_P.d, 0>,
2297 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2299 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2300 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2301 (i16 -1), FROUND_CURRENT)),
2302 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2304 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2305 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2306 (i8 -1), FROUND_CURRENT)),
2307 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2309 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2310 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2311 (i16 -1), FROUND_CURRENT)),
2312 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2314 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2315 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2316 (i8 -1), FROUND_CURRENT)),
2317 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2318 //===----------------------------------------------------------------------===//
2319 // AVX-512 VPTESTM instructions
2320 //===----------------------------------------------------------------------===//
2322 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2323 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2324 SDNode OpNode, ValueType vt> {
2325 def rr : AVX512PI<opc, MRMSrcReg,
2326 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2327 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2328 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2329 SSEPackedInt>, EVEX_4V;
2330 def rm : AVX512PI<opc, MRMSrcMem,
2331 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2332 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2333 [(set KRC:$dst, (OpNode (vt RC:$src1),
2334 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2337 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2338 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2339 EVEX_CD8<32, CD8VF>;
2340 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2341 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2342 EVEX_CD8<64, CD8VF>;
2344 let Predicates = [HasCDI] in {
2345 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2346 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2347 EVEX_CD8<32, CD8VF>;
2348 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2349 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2350 EVEX_CD8<64, CD8VF>;
2353 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2354 (v16i32 VR512:$src2), (i16 -1))),
2355 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2357 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2358 (v8i64 VR512:$src2), (i8 -1))),
2359 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2360 //===----------------------------------------------------------------------===//
2361 // AVX-512 Shift instructions
2362 //===----------------------------------------------------------------------===//
2363 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2364 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2365 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2366 RegisterClass KRC> {
2367 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2368 (ins RC:$src1, i8imm:$src2),
2369 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2370 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2371 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2372 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2373 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2374 !strconcat(OpcodeStr,
2375 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2376 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2377 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2378 (ins x86memop:$src1, i8imm:$src2),
2379 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2380 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2381 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2382 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2383 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2384 !strconcat(OpcodeStr,
2385 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2386 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2389 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2390 RegisterClass RC, ValueType vt, ValueType SrcVT,
2391 PatFrag bc_frag, RegisterClass KRC> {
2392 // src2 is always 128-bit
2393 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2394 (ins RC:$src1, VR128X:$src2),
2395 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2396 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2397 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2398 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2399 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2400 !strconcat(OpcodeStr,
2401 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2402 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2403 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2404 (ins RC:$src1, i128mem:$src2),
2405 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2406 [(set RC:$dst, (vt (OpNode RC:$src1,
2407 (bc_frag (memopv2i64 addr:$src2)))))],
2408 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2409 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2410 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2411 !strconcat(OpcodeStr,
2412 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2413 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2416 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2417 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2418 EVEX_V512, EVEX_CD8<32, CD8VF>;
2419 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2420 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2421 EVEX_CD8<32, CD8VQ>;
2423 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2424 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2425 EVEX_CD8<64, CD8VF>, VEX_W;
2426 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2427 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2428 EVEX_CD8<64, CD8VQ>, VEX_W;
2430 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2431 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2432 EVEX_CD8<32, CD8VF>;
2433 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2434 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2435 EVEX_CD8<32, CD8VQ>;
2437 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2438 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2439 EVEX_CD8<64, CD8VF>, VEX_W;
2440 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2441 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2442 EVEX_CD8<64, CD8VQ>, VEX_W;
2444 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2445 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2446 EVEX_V512, EVEX_CD8<32, CD8VF>;
2447 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2448 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2449 EVEX_CD8<32, CD8VQ>;
2451 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2452 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2453 EVEX_CD8<64, CD8VF>, VEX_W;
2454 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2455 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2456 EVEX_CD8<64, CD8VQ>, VEX_W;
2458 //===-------------------------------------------------------------------===//
2459 // Variable Bit Shifts
2460 //===-------------------------------------------------------------------===//
2461 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2462 RegisterClass RC, ValueType vt,
2463 X86MemOperand x86memop, PatFrag mem_frag> {
2464 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2465 (ins RC:$src1, RC:$src2),
2466 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2468 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2470 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2471 (ins RC:$src1, x86memop:$src2),
2472 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2474 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2478 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2479 i512mem, memopv16i32>, EVEX_V512,
2480 EVEX_CD8<32, CD8VF>;
2481 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2482 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2483 EVEX_CD8<64, CD8VF>;
2484 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2485 i512mem, memopv16i32>, EVEX_V512,
2486 EVEX_CD8<32, CD8VF>;
2487 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2488 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2489 EVEX_CD8<64, CD8VF>;
2490 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2491 i512mem, memopv16i32>, EVEX_V512,
2492 EVEX_CD8<32, CD8VF>;
2493 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2494 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2495 EVEX_CD8<64, CD8VF>;
2497 //===----------------------------------------------------------------------===//
2498 // AVX-512 - MOVDDUP
2499 //===----------------------------------------------------------------------===//
2501 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2502 X86MemOperand x86memop, PatFrag memop_frag> {
2503 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2504 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2505 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2506 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2507 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2509 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2512 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2513 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2514 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2515 (VMOVDDUPZrm addr:$src)>;
2517 //===---------------------------------------------------------------------===//
2518 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2519 //===---------------------------------------------------------------------===//
2520 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2521 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2522 X86MemOperand x86memop> {
2523 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2524 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2525 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2527 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2528 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2529 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2532 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2533 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2534 EVEX_CD8<32, CD8VF>;
2535 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2536 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2537 EVEX_CD8<32, CD8VF>;
2539 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2540 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2541 (VMOVSHDUPZrm addr:$src)>;
2542 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2543 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2544 (VMOVSLDUPZrm addr:$src)>;
2546 //===----------------------------------------------------------------------===//
2547 // Move Low to High and High to Low packed FP Instructions
2548 //===----------------------------------------------------------------------===//
2549 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2550 (ins VR128X:$src1, VR128X:$src2),
2551 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2552 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2553 IIC_SSE_MOV_LH>, EVEX_4V;
2554 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2555 (ins VR128X:$src1, VR128X:$src2),
2556 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2557 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2558 IIC_SSE_MOV_LH>, EVEX_4V;
2560 let Predicates = [HasAVX512] in {
2562 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2563 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2564 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2565 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2568 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2569 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2572 //===----------------------------------------------------------------------===//
2573 // FMA - Fused Multiply Operations
2575 let Constraints = "$src1 = $dst" in {
2576 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2577 RegisterClass RC, X86MemOperand x86memop,
2578 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2579 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2580 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2581 (ins RC:$src1, RC:$src2, RC:$src3),
2582 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2583 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2586 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2587 (ins RC:$src1, RC:$src2, x86memop:$src3),
2588 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2589 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2590 (mem_frag addr:$src3))))]>;
2591 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2592 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2593 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2594 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2595 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2596 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2598 } // Constraints = "$src1 = $dst"
2600 let ExeDomain = SSEPackedSingle in {
2601 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2602 memopv16f32, f32mem, loadf32, "{1to16}",
2603 X86Fmadd, v16f32>, EVEX_V512,
2604 EVEX_CD8<32, CD8VF>;
2605 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2606 memopv16f32, f32mem, loadf32, "{1to16}",
2607 X86Fmsub, v16f32>, EVEX_V512,
2608 EVEX_CD8<32, CD8VF>;
2609 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2610 memopv16f32, f32mem, loadf32, "{1to16}",
2611 X86Fmaddsub, v16f32>,
2612 EVEX_V512, EVEX_CD8<32, CD8VF>;
2613 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2614 memopv16f32, f32mem, loadf32, "{1to16}",
2615 X86Fmsubadd, v16f32>,
2616 EVEX_V512, EVEX_CD8<32, CD8VF>;
2617 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2618 memopv16f32, f32mem, loadf32, "{1to16}",
2619 X86Fnmadd, v16f32>, EVEX_V512,
2620 EVEX_CD8<32, CD8VF>;
2621 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2622 memopv16f32, f32mem, loadf32, "{1to16}",
2623 X86Fnmsub, v16f32>, EVEX_V512,
2624 EVEX_CD8<32, CD8VF>;
2626 let ExeDomain = SSEPackedDouble in {
2627 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2628 memopv8f64, f64mem, loadf64, "{1to8}",
2629 X86Fmadd, v8f64>, EVEX_V512,
2630 VEX_W, EVEX_CD8<64, CD8VF>;
2631 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2632 memopv8f64, f64mem, loadf64, "{1to8}",
2633 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2634 EVEX_CD8<64, CD8VF>;
2635 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2636 memopv8f64, f64mem, loadf64, "{1to8}",
2637 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2638 EVEX_CD8<64, CD8VF>;
2639 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2640 memopv8f64, f64mem, loadf64, "{1to8}",
2641 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2642 EVEX_CD8<64, CD8VF>;
2643 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2644 memopv8f64, f64mem, loadf64, "{1to8}",
2645 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2646 EVEX_CD8<64, CD8VF>;
2647 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2648 memopv8f64, f64mem, loadf64, "{1to8}",
2649 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2650 EVEX_CD8<64, CD8VF>;
2653 let Constraints = "$src1 = $dst" in {
2654 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2655 RegisterClass RC, X86MemOperand x86memop,
2656 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2657 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2659 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2660 (ins RC:$src1, RC:$src3, x86memop:$src2),
2661 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2662 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2663 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2664 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2665 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2666 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2667 [(set RC:$dst, (OpNode RC:$src1,
2668 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2670 } // Constraints = "$src1 = $dst"
2673 let ExeDomain = SSEPackedSingle in {
2674 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2675 memopv16f32, f32mem, loadf32, "{1to16}",
2676 X86Fmadd, v16f32>, EVEX_V512,
2677 EVEX_CD8<32, CD8VF>;
2678 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2679 memopv16f32, f32mem, loadf32, "{1to16}",
2680 X86Fmsub, v16f32>, EVEX_V512,
2681 EVEX_CD8<32, CD8VF>;
2682 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2683 memopv16f32, f32mem, loadf32, "{1to16}",
2684 X86Fmaddsub, v16f32>,
2685 EVEX_V512, EVEX_CD8<32, CD8VF>;
2686 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2687 memopv16f32, f32mem, loadf32, "{1to16}",
2688 X86Fmsubadd, v16f32>,
2689 EVEX_V512, EVEX_CD8<32, CD8VF>;
2690 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2691 memopv16f32, f32mem, loadf32, "{1to16}",
2692 X86Fnmadd, v16f32>, EVEX_V512,
2693 EVEX_CD8<32, CD8VF>;
2694 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2695 memopv16f32, f32mem, loadf32, "{1to16}",
2696 X86Fnmsub, v16f32>, EVEX_V512,
2697 EVEX_CD8<32, CD8VF>;
2699 let ExeDomain = SSEPackedDouble in {
2700 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2701 memopv8f64, f64mem, loadf64, "{1to8}",
2702 X86Fmadd, v8f64>, EVEX_V512,
2703 VEX_W, EVEX_CD8<64, CD8VF>;
2704 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2705 memopv8f64, f64mem, loadf64, "{1to8}",
2706 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2707 EVEX_CD8<64, CD8VF>;
2708 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2709 memopv8f64, f64mem, loadf64, "{1to8}",
2710 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2711 EVEX_CD8<64, CD8VF>;
2712 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2713 memopv8f64, f64mem, loadf64, "{1to8}",
2714 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2715 EVEX_CD8<64, CD8VF>;
2716 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2717 memopv8f64, f64mem, loadf64, "{1to8}",
2718 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2719 EVEX_CD8<64, CD8VF>;
2720 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2721 memopv8f64, f64mem, loadf64, "{1to8}",
2722 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2723 EVEX_CD8<64, CD8VF>;
2727 let Constraints = "$src1 = $dst" in {
2728 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2729 RegisterClass RC, ValueType OpVT,
2730 X86MemOperand x86memop, Operand memop,
2732 let isCommutable = 1 in
2733 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2734 (ins RC:$src1, RC:$src2, RC:$src3),
2735 !strconcat(OpcodeStr,
2736 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2738 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2740 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2741 (ins RC:$src1, RC:$src2, f128mem:$src3),
2742 !strconcat(OpcodeStr,
2743 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2745 (OpVT (OpNode RC:$src2, RC:$src1,
2746 (mem_frag addr:$src3))))]>;
2749 } // Constraints = "$src1 = $dst"
2751 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2752 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2753 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2754 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2755 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2756 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2757 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2758 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2759 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2760 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2761 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2762 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2763 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2764 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2765 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2766 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2768 //===----------------------------------------------------------------------===//
2769 // AVX-512 Scalar convert from sign integer to float/double
2770 //===----------------------------------------------------------------------===//
2772 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2773 X86MemOperand x86memop, string asm> {
2774 let hasSideEffects = 0 in {
2775 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2776 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2779 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2780 (ins DstRC:$src1, x86memop:$src),
2781 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2783 } // hasSideEffects = 0
2785 let Predicates = [HasAVX512] in {
2786 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2787 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2788 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2789 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2790 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2791 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2792 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2793 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2795 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2796 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2797 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2798 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2799 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2800 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2801 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2802 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2804 def : Pat<(f32 (sint_to_fp GR32:$src)),
2805 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2806 def : Pat<(f32 (sint_to_fp GR64:$src)),
2807 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2808 def : Pat<(f64 (sint_to_fp GR32:$src)),
2809 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2810 def : Pat<(f64 (sint_to_fp GR64:$src)),
2811 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2813 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2814 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2815 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2816 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2817 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2818 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2819 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2820 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2822 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2823 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2824 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2825 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2826 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2827 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2828 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2829 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2831 def : Pat<(f32 (uint_to_fp GR32:$src)),
2832 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2833 def : Pat<(f32 (uint_to_fp GR64:$src)),
2834 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2835 def : Pat<(f64 (uint_to_fp GR32:$src)),
2836 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2837 def : Pat<(f64 (uint_to_fp GR64:$src)),
2838 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2841 //===----------------------------------------------------------------------===//
2842 // AVX-512 Scalar convert from float/double to integer
2843 //===----------------------------------------------------------------------===//
2844 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2845 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2847 let hasSideEffects = 0 in {
2848 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2849 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2850 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2851 Requires<[HasAVX512]>;
2853 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2854 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2855 Requires<[HasAVX512]>;
2856 } // hasSideEffects = 0
2858 let Predicates = [HasAVX512] in {
2859 // Convert float/double to signed/unsigned int 32/64
2860 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2861 ssmem, sse_load_f32, "cvtss2si">,
2862 XS, EVEX_CD8<32, CD8VT1>;
2863 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2864 ssmem, sse_load_f32, "cvtss2si">,
2865 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2866 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2867 ssmem, sse_load_f32, "cvtss2usi">,
2868 XS, EVEX_CD8<32, CD8VT1>;
2869 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2870 int_x86_avx512_cvtss2usi64, ssmem,
2871 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2872 EVEX_CD8<32, CD8VT1>;
2873 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2874 sdmem, sse_load_f64, "cvtsd2si">,
2875 XD, EVEX_CD8<64, CD8VT1>;
2876 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2877 sdmem, sse_load_f64, "cvtsd2si">,
2878 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2879 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2880 sdmem, sse_load_f64, "cvtsd2usi">,
2881 XD, EVEX_CD8<64, CD8VT1>;
2882 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2883 int_x86_avx512_cvtsd2usi64, sdmem,
2884 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2885 EVEX_CD8<64, CD8VT1>;
2887 let isCodeGenOnly = 1 in {
2888 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2889 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2890 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2891 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2892 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2893 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2894 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2895 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2896 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2897 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2898 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2899 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2901 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2902 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2903 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2904 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2905 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2906 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2907 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2908 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2909 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2910 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2911 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2912 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2913 } // isCodeGenOnly = 1
2915 // Convert float/double to signed/unsigned int 32/64 with truncation
2916 let isCodeGenOnly = 1 in {
2917 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2918 ssmem, sse_load_f32, "cvttss2si">,
2919 XS, EVEX_CD8<32, CD8VT1>;
2920 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2921 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2922 "cvttss2si">, XS, VEX_W,
2923 EVEX_CD8<32, CD8VT1>;
2924 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2925 sdmem, sse_load_f64, "cvttsd2si">, XD,
2926 EVEX_CD8<64, CD8VT1>;
2927 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2928 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2929 "cvttsd2si">, XD, VEX_W,
2930 EVEX_CD8<64, CD8VT1>;
2931 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2932 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2933 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2934 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2935 int_x86_avx512_cvttss2usi64, ssmem,
2936 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2937 EVEX_CD8<32, CD8VT1>;
2938 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2939 int_x86_avx512_cvttsd2usi,
2940 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2941 EVEX_CD8<64, CD8VT1>;
2942 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2943 int_x86_avx512_cvttsd2usi64, sdmem,
2944 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2945 EVEX_CD8<64, CD8VT1>;
2946 } // isCodeGenOnly = 1
2948 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2949 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2951 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2952 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2953 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2954 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2955 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2956 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2959 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2960 loadf32, "cvttss2si">, XS,
2961 EVEX_CD8<32, CD8VT1>;
2962 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2963 loadf32, "cvttss2usi">, XS,
2964 EVEX_CD8<32, CD8VT1>;
2965 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2966 loadf32, "cvttss2si">, XS, VEX_W,
2967 EVEX_CD8<32, CD8VT1>;
2968 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2969 loadf32, "cvttss2usi">, XS, VEX_W,
2970 EVEX_CD8<32, CD8VT1>;
2971 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2972 loadf64, "cvttsd2si">, XD,
2973 EVEX_CD8<64, CD8VT1>;
2974 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2975 loadf64, "cvttsd2usi">, XD,
2976 EVEX_CD8<64, CD8VT1>;
2977 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2978 loadf64, "cvttsd2si">, XD, VEX_W,
2979 EVEX_CD8<64, CD8VT1>;
2980 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2981 loadf64, "cvttsd2usi">, XD, VEX_W,
2982 EVEX_CD8<64, CD8VT1>;
2984 //===----------------------------------------------------------------------===//
2985 // AVX-512 Convert form float to double and back
2986 //===----------------------------------------------------------------------===//
2987 let hasSideEffects = 0 in {
2988 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2989 (ins FR32X:$src1, FR32X:$src2),
2990 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2991 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2993 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2994 (ins FR32X:$src1, f32mem:$src2),
2995 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2996 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2997 EVEX_CD8<32, CD8VT1>;
2999 // Convert scalar double to scalar single
3000 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3001 (ins FR64X:$src1, FR64X:$src2),
3002 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3003 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3005 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3006 (ins FR64X:$src1, f64mem:$src2),
3007 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3008 []>, EVEX_4V, VEX_LIG, VEX_W,
3009 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3012 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3013 Requires<[HasAVX512]>;
3014 def : Pat<(fextend (loadf32 addr:$src)),
3015 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3017 def : Pat<(extloadf32 addr:$src),
3018 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3019 Requires<[HasAVX512, OptForSize]>;
3021 def : Pat<(extloadf32 addr:$src),
3022 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3023 Requires<[HasAVX512, OptForSpeed]>;
3025 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3026 Requires<[HasAVX512]>;
3028 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
3029 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3030 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3032 let hasSideEffects = 0 in {
3033 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3034 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3036 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3037 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3038 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3039 [], d>, EVEX, EVEX_B, EVEX_RC;
3041 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3042 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3044 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3045 } // hasSideEffects = 0
3048 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
3049 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3050 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3052 let hasSideEffects = 0 in {
3053 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3054 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3056 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3058 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3059 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3061 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
3062 } // hasSideEffects = 0
3065 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
3066 memopv8f64, f512mem, v8f32, v8f64,
3067 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
3068 EVEX_CD8<64, CD8VF>;
3070 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3071 memopv4f64, f256mem, v8f64, v8f32,
3072 SSEPackedDouble>, EVEX_V512, PS,
3073 EVEX_CD8<32, CD8VH>;
3074 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3075 (VCVTPS2PDZrm addr:$src)>;
3077 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3078 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3079 (VCVTPD2PSZrr VR512:$src)>;
3081 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3082 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3083 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
3085 //===----------------------------------------------------------------------===//
3086 // AVX-512 Vector convert from sign integer to float/double
3087 //===----------------------------------------------------------------------===//
3089 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
3090 memopv8i64, i512mem, v16f32, v16i32,
3091 SSEPackedSingle>, EVEX_V512, PS,
3092 EVEX_CD8<32, CD8VF>;
3094 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3095 memopv4i64, i256mem, v8f64, v8i32,
3096 SSEPackedDouble>, EVEX_V512, XS,
3097 EVEX_CD8<32, CD8VH>;
3099 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
3100 memopv16f32, f512mem, v16i32, v16f32,
3101 SSEPackedSingle>, EVEX_V512, XS,
3102 EVEX_CD8<32, CD8VF>;
3104 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
3105 memopv8f64, f512mem, v8i32, v8f64,
3106 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
3107 EVEX_CD8<64, CD8VF>;
3109 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
3110 memopv16f32, f512mem, v16i32, v16f32,
3111 SSEPackedSingle>, EVEX_V512, PS,
3112 EVEX_CD8<32, CD8VF>;
3114 // cvttps2udq (src, 0, mask-all-ones, sae-current)
3115 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3116 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3117 (VCVTTPS2UDQZrr VR512:$src)>;
3119 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
3120 memopv8f64, f512mem, v8i32, v8f64,
3121 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
3122 EVEX_CD8<64, CD8VF>;
3124 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
3125 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3126 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3127 (VCVTTPD2UDQZrr VR512:$src)>;
3129 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3130 memopv4i64, f256mem, v8f64, v8i32,
3131 SSEPackedDouble>, EVEX_V512, XS,
3132 EVEX_CD8<32, CD8VH>;
3134 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
3135 memopv16i32, f512mem, v16f32, v16i32,
3136 SSEPackedSingle>, EVEX_V512, XD,
3137 EVEX_CD8<32, CD8VF>;
3139 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3140 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3141 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3143 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3144 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3145 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3147 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3148 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3149 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3151 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3152 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3153 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3155 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
3156 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3157 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
3158 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3159 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3160 (VCVTDQ2PDZrr VR256X:$src)>;
3161 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3162 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3163 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3164 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3165 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3166 (VCVTUDQ2PDZrr VR256X:$src)>;
3168 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3169 RegisterClass DstRC, PatFrag mem_frag,
3170 X86MemOperand x86memop, Domain d> {
3171 let hasSideEffects = 0 in {
3172 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
3173 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3175 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
3176 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
3177 [], d>, EVEX, EVEX_B, EVEX_RC;
3179 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3180 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3182 } // hasSideEffects = 0
3185 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3186 memopv16f32, f512mem, SSEPackedSingle>, PD,
3187 EVEX_V512, EVEX_CD8<32, CD8VF>;
3188 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3189 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3190 EVEX_V512, EVEX_CD8<64, CD8VF>;
3192 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3193 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3194 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3196 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3197 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3198 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3200 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3201 memopv16f32, f512mem, SSEPackedSingle>,
3202 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3203 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3204 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3205 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3207 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3208 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3209 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3211 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3212 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3213 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3215 let Predicates = [HasAVX512] in {
3216 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3217 (VCVTPD2PSZrm addr:$src)>;
3218 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3219 (VCVTPS2PDZrm addr:$src)>;
3222 //===----------------------------------------------------------------------===//
3223 // Half precision conversion instructions
3224 //===----------------------------------------------------------------------===//
3225 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3226 X86MemOperand x86memop> {
3227 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3228 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3230 let hasSideEffects = 0, mayLoad = 1 in
3231 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3232 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3235 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3236 X86MemOperand x86memop> {
3237 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3238 (ins srcRC:$src1, i32i8imm:$src2),
3239 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3241 let hasSideEffects = 0, mayStore = 1 in
3242 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3243 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3244 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3247 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3248 EVEX_CD8<32, CD8VH>;
3249 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3250 EVEX_CD8<32, CD8VH>;
3252 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3253 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3254 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3256 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3257 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3258 (VCVTPH2PSZrr VR256X:$src)>;
3260 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3261 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3262 "ucomiss">, PS, EVEX, VEX_LIG,
3263 EVEX_CD8<32, CD8VT1>;
3264 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3265 "ucomisd">, PD, EVEX,
3266 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3267 let Pattern = []<dag> in {
3268 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3269 "comiss">, PS, EVEX, VEX_LIG,
3270 EVEX_CD8<32, CD8VT1>;
3271 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3272 "comisd">, PD, EVEX,
3273 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3275 let isCodeGenOnly = 1 in {
3276 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3277 load, "ucomiss">, PS, EVEX, VEX_LIG,
3278 EVEX_CD8<32, CD8VT1>;
3279 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3280 load, "ucomisd">, PD, EVEX,
3281 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3283 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3284 load, "comiss">, PS, EVEX, VEX_LIG,
3285 EVEX_CD8<32, CD8VT1>;
3286 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3287 load, "comisd">, PD, EVEX,
3288 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3292 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3293 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3294 X86MemOperand x86memop> {
3295 let hasSideEffects = 0 in {
3296 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3297 (ins RC:$src1, RC:$src2),
3298 !strconcat(OpcodeStr,
3299 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3300 let mayLoad = 1 in {
3301 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3302 (ins RC:$src1, x86memop:$src2),
3303 !strconcat(OpcodeStr,
3304 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3309 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3310 EVEX_CD8<32, CD8VT1>;
3311 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3312 VEX_W, EVEX_CD8<64, CD8VT1>;
3313 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3314 EVEX_CD8<32, CD8VT1>;
3315 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3316 VEX_W, EVEX_CD8<64, CD8VT1>;
3318 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3319 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3320 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3321 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3323 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3324 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3325 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3326 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3328 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3329 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3330 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3331 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3333 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3334 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3335 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3336 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3338 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3339 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3340 RegisterClass RC, X86MemOperand x86memop,
3341 PatFrag mem_frag, ValueType OpVt> {
3342 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3343 !strconcat(OpcodeStr,
3344 " \t{$src, $dst|$dst, $src}"),
3345 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3347 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3348 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3349 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3352 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3353 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3354 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3355 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3356 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3357 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3358 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3359 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3361 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3362 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3363 (VRSQRT14PSZr VR512:$src)>;
3364 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3365 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3366 (VRSQRT14PDZr VR512:$src)>;
3368 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3369 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3370 (VRCP14PSZr VR512:$src)>;
3371 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3372 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3373 (VRCP14PDZr VR512:$src)>;
3375 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3376 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3377 X86MemOperand x86memop> {
3378 let hasSideEffects = 0, Predicates = [HasERI] in {
3379 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3380 (ins RC:$src1, RC:$src2),
3381 !strconcat(OpcodeStr,
3382 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3383 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3384 (ins RC:$src1, RC:$src2),
3385 !strconcat(OpcodeStr,
3386 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3387 []>, EVEX_4V, EVEX_B;
3388 let mayLoad = 1 in {
3389 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3390 (ins RC:$src1, x86memop:$src2),
3391 !strconcat(OpcodeStr,
3392 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3397 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3398 EVEX_CD8<32, CD8VT1>;
3399 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3400 VEX_W, EVEX_CD8<64, CD8VT1>;
3401 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3402 EVEX_CD8<32, CD8VT1>;
3403 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3404 VEX_W, EVEX_CD8<64, CD8VT1>;
3406 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3407 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3409 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3410 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3412 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3413 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3415 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3416 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3418 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3419 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3421 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3422 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3424 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3425 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3427 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3428 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3430 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3431 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3432 RegisterClass RC, X86MemOperand x86memop> {
3433 let hasSideEffects = 0, Predicates = [HasERI] in {
3434 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3435 !strconcat(OpcodeStr,
3436 " \t{$src, $dst|$dst, $src}"),
3438 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3439 !strconcat(OpcodeStr,
3440 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3442 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3443 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3447 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3448 EVEX_V512, EVEX_CD8<32, CD8VF>;
3449 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3450 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3451 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3452 EVEX_V512, EVEX_CD8<32, CD8VF>;
3453 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3454 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3456 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3457 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3458 (VRSQRT28PSZrb VR512:$src)>;
3459 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3460 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3461 (VRSQRT28PDZrb VR512:$src)>;
3463 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3464 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3465 (VRCP28PSZrb VR512:$src)>;
3466 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3467 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3468 (VRCP28PDZrb VR512:$src)>;
3470 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3471 Intrinsic V16F32Int, Intrinsic V8F64Int,
3472 OpndItins itins_s, OpndItins itins_d> {
3473 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3474 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3475 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3479 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3480 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3482 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3483 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3485 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3486 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3487 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3491 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3492 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3493 [(set VR512:$dst, (OpNode
3494 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3495 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3497 let isCodeGenOnly = 1 in {
3498 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3499 !strconcat(OpcodeStr,
3500 "ps\t{$src, $dst|$dst, $src}"),
3501 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3503 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3504 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3506 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3507 EVEX_V512, EVEX_CD8<32, CD8VF>;
3508 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3509 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3510 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3511 EVEX, EVEX_V512, VEX_W;
3512 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3513 !strconcat(OpcodeStr,
3514 "pd\t{$src, $dst|$dst, $src}"),
3515 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3516 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3517 } // isCodeGenOnly = 1
3520 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3521 Intrinsic F32Int, Intrinsic F64Int,
3522 OpndItins itins_s, OpndItins itins_d> {
3523 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3524 (ins FR32X:$src1, FR32X:$src2),
3525 !strconcat(OpcodeStr,
3526 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3527 [], itins_s.rr>, XS, EVEX_4V;
3528 let isCodeGenOnly = 1 in
3529 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3530 (ins VR128X:$src1, VR128X:$src2),
3531 !strconcat(OpcodeStr,
3532 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3534 (F32Int VR128X:$src1, VR128X:$src2))],
3535 itins_s.rr>, XS, EVEX_4V;
3536 let mayLoad = 1 in {
3537 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3538 (ins FR32X:$src1, f32mem:$src2),
3539 !strconcat(OpcodeStr,
3540 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3541 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3542 let isCodeGenOnly = 1 in
3543 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3544 (ins VR128X:$src1, ssmem:$src2),
3545 !strconcat(OpcodeStr,
3546 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3548 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3549 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3551 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3552 (ins FR64X:$src1, FR64X:$src2),
3553 !strconcat(OpcodeStr,
3554 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3556 let isCodeGenOnly = 1 in
3557 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3558 (ins VR128X:$src1, VR128X:$src2),
3559 !strconcat(OpcodeStr,
3560 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3562 (F64Int VR128X:$src1, VR128X:$src2))],
3563 itins_s.rr>, XD, EVEX_4V, VEX_W;
3564 let mayLoad = 1 in {
3565 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3566 (ins FR64X:$src1, f64mem:$src2),
3567 !strconcat(OpcodeStr,
3568 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3569 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3570 let isCodeGenOnly = 1 in
3571 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3572 (ins VR128X:$src1, sdmem:$src2),
3573 !strconcat(OpcodeStr,
3574 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3576 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3577 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3582 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3583 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3584 SSE_SQRTSS, SSE_SQRTSD>,
3585 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3586 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3587 SSE_SQRTPS, SSE_SQRTPD>;
3589 let Predicates = [HasAVX512] in {
3590 def : Pat<(f32 (fsqrt FR32X:$src)),
3591 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3592 def : Pat<(f32 (fsqrt (load addr:$src))),
3593 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3594 Requires<[OptForSize]>;
3595 def : Pat<(f64 (fsqrt FR64X:$src)),
3596 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3597 def : Pat<(f64 (fsqrt (load addr:$src))),
3598 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3599 Requires<[OptForSize]>;
3601 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3602 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3603 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3604 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3605 Requires<[OptForSize]>;
3607 def : Pat<(f32 (X86frcp FR32X:$src)),
3608 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3609 def : Pat<(f32 (X86frcp (load addr:$src))),
3610 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3611 Requires<[OptForSize]>;
3613 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3614 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3615 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3617 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3618 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3620 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3621 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3622 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3624 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3625 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3629 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3630 X86MemOperand x86memop, RegisterClass RC,
3631 PatFrag mem_frag32, PatFrag mem_frag64,
3632 Intrinsic V4F32Int, Intrinsic V2F64Int,
3634 let ExeDomain = SSEPackedSingle in {
3635 // Intrinsic operation, reg.
3636 // Vector intrinsic operation, reg
3637 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3638 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3639 !strconcat(OpcodeStr,
3640 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3641 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3643 // Vector intrinsic operation, mem
3644 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3645 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3646 !strconcat(OpcodeStr,
3647 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3649 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3650 EVEX_CD8<32, VForm>;
3651 } // ExeDomain = SSEPackedSingle
3653 let ExeDomain = SSEPackedDouble in {
3654 // Vector intrinsic operation, reg
3655 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3656 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3657 !strconcat(OpcodeStr,
3658 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3659 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3661 // Vector intrinsic operation, mem
3662 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3663 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3664 !strconcat(OpcodeStr,
3665 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3667 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3668 EVEX_CD8<64, VForm>;
3669 } // ExeDomain = SSEPackedDouble
3672 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3676 let ExeDomain = GenericDomain in {
3678 let hasSideEffects = 0 in
3679 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3680 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3681 !strconcat(OpcodeStr,
3682 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3685 // Intrinsic operation, reg.
3686 let isCodeGenOnly = 1 in
3687 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3688 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3689 !strconcat(OpcodeStr,
3690 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3691 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3693 // Intrinsic operation, mem.
3694 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3695 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3696 !strconcat(OpcodeStr,
3697 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3698 [(set VR128X:$dst, (F32Int VR128X:$src1,
3699 sse_load_f32:$src2, imm:$src3))]>,
3700 EVEX_CD8<32, CD8VT1>;
3703 let hasSideEffects = 0 in
3704 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3705 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3706 !strconcat(OpcodeStr,
3707 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3710 // Intrinsic operation, reg.
3711 let isCodeGenOnly = 1 in
3712 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3713 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3714 !strconcat(OpcodeStr,
3715 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3716 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3719 // Intrinsic operation, mem.
3720 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3721 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3722 !strconcat(OpcodeStr,
3723 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3725 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3726 VEX_W, EVEX_CD8<64, CD8VT1>;
3727 } // ExeDomain = GenericDomain
3730 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3731 X86MemOperand x86memop, RegisterClass RC,
3732 PatFrag mem_frag, Domain d> {
3733 let ExeDomain = d in {
3734 // Intrinsic operation, reg.
3735 // Vector intrinsic operation, reg
3736 def r : AVX512AIi8<opc, MRMSrcReg,
3737 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3738 !strconcat(OpcodeStr,
3739 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3742 // Vector intrinsic operation, mem
3743 def m : AVX512AIi8<opc, MRMSrcMem,
3744 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3745 !strconcat(OpcodeStr,
3746 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3752 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3753 memopv16f32, SSEPackedSingle>, EVEX_V512,
3754 EVEX_CD8<32, CD8VF>;
3756 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3757 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3759 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3762 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3763 memopv8f64, SSEPackedDouble>, EVEX_V512,
3764 VEX_W, EVEX_CD8<64, CD8VF>;
3766 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3767 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3769 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3771 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3772 Operand x86memop, RegisterClass RC, Domain d> {
3773 let ExeDomain = d in {
3774 def r : AVX512AIi8<opc, MRMSrcReg,
3775 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3776 !strconcat(OpcodeStr,
3777 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3780 def m : AVX512AIi8<opc, MRMSrcMem,
3781 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3782 !strconcat(OpcodeStr,
3783 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3788 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3789 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3791 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3792 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3794 def : Pat<(ffloor FR32X:$src),
3795 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3796 def : Pat<(f64 (ffloor FR64X:$src)),
3797 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3798 def : Pat<(f32 (fnearbyint FR32X:$src)),
3799 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3800 def : Pat<(f64 (fnearbyint FR64X:$src)),
3801 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3802 def : Pat<(f32 (fceil FR32X:$src)),
3803 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3804 def : Pat<(f64 (fceil FR64X:$src)),
3805 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3806 def : Pat<(f32 (frint FR32X:$src)),
3807 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3808 def : Pat<(f64 (frint FR64X:$src)),
3809 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3810 def : Pat<(f32 (ftrunc FR32X:$src)),
3811 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3812 def : Pat<(f64 (ftrunc FR64X:$src)),
3813 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3815 def : Pat<(v16f32 (ffloor VR512:$src)),
3816 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3817 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3818 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3819 def : Pat<(v16f32 (fceil VR512:$src)),
3820 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3821 def : Pat<(v16f32 (frint VR512:$src)),
3822 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3823 def : Pat<(v16f32 (ftrunc VR512:$src)),
3824 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3826 def : Pat<(v8f64 (ffloor VR512:$src)),
3827 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3828 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3829 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3830 def : Pat<(v8f64 (fceil VR512:$src)),
3831 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3832 def : Pat<(v8f64 (frint VR512:$src)),
3833 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3834 def : Pat<(v8f64 (ftrunc VR512:$src)),
3835 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3837 //-------------------------------------------------
3838 // Integer truncate and extend operations
3839 //-------------------------------------------------
3841 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3842 RegisterClass dstRC, RegisterClass srcRC,
3843 RegisterClass KRC, X86MemOperand x86memop> {
3844 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3846 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3849 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3850 (ins KRC:$mask, srcRC:$src),
3851 !strconcat(OpcodeStr,
3852 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
3855 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3856 (ins KRC:$mask, srcRC:$src),
3857 !strconcat(OpcodeStr,
3858 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3861 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3862 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3865 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
3866 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
3867 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
3871 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3872 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3873 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3874 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3875 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3876 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3877 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3878 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3879 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3880 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3881 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3882 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3883 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3884 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3885 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3886 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3887 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3888 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3889 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3890 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3891 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3892 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3893 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3894 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3895 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3896 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3897 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3898 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3899 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3900 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3902 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3903 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3904 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3905 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3906 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3908 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3909 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
3910 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3911 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
3912 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3913 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
3914 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3915 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
3918 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3919 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
3920 PatFrag mem_frag, X86MemOperand x86memop,
3921 ValueType OpVT, ValueType InVT> {
3923 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3925 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3926 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3928 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3929 (ins KRC:$mask, SrcRC:$src),
3930 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
3933 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3934 (ins KRC:$mask, SrcRC:$src),
3935 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
3938 let mayLoad = 1 in {
3939 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3940 (ins x86memop:$src),
3941 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3943 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3946 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3947 (ins KRC:$mask, x86memop:$src),
3948 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
3952 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3953 (ins KRC:$mask, x86memop:$src),
3954 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
3960 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
3961 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3963 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
3964 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3966 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
3967 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3968 EVEX_CD8<16, CD8VH>;
3969 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
3970 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3971 EVEX_CD8<16, CD8VQ>;
3972 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
3973 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3974 EVEX_CD8<32, CD8VH>;
3976 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
3977 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3979 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
3980 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3982 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
3983 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3984 EVEX_CD8<16, CD8VH>;
3985 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
3986 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3987 EVEX_CD8<16, CD8VQ>;
3988 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
3989 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3990 EVEX_CD8<32, CD8VH>;
3992 //===----------------------------------------------------------------------===//
3993 // GATHER - SCATTER Operations
3995 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3996 RegisterClass RC, X86MemOperand memop> {
3998 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3999 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4000 (ins RC:$src1, KRC:$mask, memop:$src2),
4001 !strconcat(OpcodeStr,
4002 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4006 let ExeDomain = SSEPackedDouble in {
4007 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4008 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4009 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4010 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4013 let ExeDomain = SSEPackedSingle in {
4014 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4015 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4016 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4017 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4020 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4021 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4022 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4023 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4025 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4026 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4027 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4028 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4030 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4031 RegisterClass RC, X86MemOperand memop> {
4032 let mayStore = 1, Constraints = "$mask = $mask_wb" in
4033 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4034 (ins memop:$dst, KRC:$mask, RC:$src2),
4035 !strconcat(OpcodeStr,
4036 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4040 let ExeDomain = SSEPackedDouble in {
4041 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4042 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4043 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4044 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4047 let ExeDomain = SSEPackedSingle in {
4048 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4049 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4050 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4051 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4054 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4055 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4056 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4057 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4059 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4060 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4061 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4062 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4064 //===----------------------------------------------------------------------===//
4065 // VSHUFPS - VSHUFPD Operations
4067 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4068 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4070 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4071 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4072 !strconcat(OpcodeStr,
4073 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4074 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4075 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4076 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
4077 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4078 (ins RC:$src1, RC:$src2, i8imm:$src3),
4079 !strconcat(OpcodeStr,
4080 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4081 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4082 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
4083 EVEX_4V, Sched<[WriteShuffle]>;
4086 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
4087 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4088 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
4089 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4091 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4092 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4093 def : Pat<(v16i32 (X86Shufp VR512:$src1,
4094 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4095 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4097 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4098 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4099 def : Pat<(v8i64 (X86Shufp VR512:$src1,
4100 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4101 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4103 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
4104 X86MemOperand x86memop> {
4105 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
4106 (ins RC:$src1, RC:$src2, i8imm:$src3),
4107 !strconcat(OpcodeStr,
4108 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4111 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
4112 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4113 !strconcat(OpcodeStr,
4114 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4117 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
4118 EVEX_V512, EVEX_CD8<32, CD8VF>;
4119 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
4120 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4122 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4123 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4124 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4125 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4126 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4127 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
4128 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4129 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
4131 // Helper fragments to match sext vXi1 to vXiY.
4132 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4133 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4135 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4136 RegisterClass KRC, RegisterClass RC,
4137 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4139 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4140 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4142 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4143 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4145 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4146 !strconcat(OpcodeStr,
4147 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4149 let mayLoad = 1 in {
4150 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4151 (ins x86memop:$src),
4152 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4154 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4155 (ins KRC:$mask, x86memop:$src),
4156 !strconcat(OpcodeStr,
4157 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4159 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4160 (ins KRC:$mask, x86memop:$src),
4161 !strconcat(OpcodeStr,
4162 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4164 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4165 (ins x86scalar_mop:$src),
4166 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4167 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4169 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4170 (ins KRC:$mask, x86scalar_mop:$src),
4171 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4172 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4173 []>, EVEX, EVEX_B, EVEX_K;
4174 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4175 (ins KRC:$mask, x86scalar_mop:$src),
4176 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4177 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4179 []>, EVEX, EVEX_B, EVEX_KZ;
4183 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4184 i512mem, i32mem, "{1to16}">, EVEX_V512,
4185 EVEX_CD8<32, CD8VF>;
4186 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4187 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4188 EVEX_CD8<64, CD8VF>;
4191 (bc_v16i32 (v16i1sextv16i32)),
4192 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4193 (VPABSDZrr VR512:$src)>;
4195 (bc_v8i64 (v8i1sextv8i64)),
4196 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4197 (VPABSQZrr VR512:$src)>;
4199 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4200 (v16i32 immAllZerosV), (i16 -1))),
4201 (VPABSDZrr VR512:$src)>;
4202 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4203 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
4204 (VPABSQZrr VR512:$src)>;
4206 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
4207 RegisterClass RC, RegisterClass KRC,
4208 X86MemOperand x86memop,
4209 X86MemOperand x86scalar_mop, string BrdcstStr> {
4210 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4212 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
4214 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4215 (ins x86memop:$src),
4216 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
4218 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4219 (ins x86scalar_mop:$src),
4220 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4221 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4223 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4224 (ins KRC:$mask, RC:$src),
4225 !strconcat(OpcodeStr,
4226 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4228 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4229 (ins KRC:$mask, x86memop:$src),
4230 !strconcat(OpcodeStr,
4231 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
4233 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4234 (ins KRC:$mask, x86scalar_mop:$src),
4235 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4236 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4238 []>, EVEX, EVEX_KZ, EVEX_B;
4240 let Constraints = "$src1 = $dst" in {
4241 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4242 (ins RC:$src1, KRC:$mask, RC:$src2),
4243 !strconcat(OpcodeStr,
4244 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4246 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4247 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4248 !strconcat(OpcodeStr,
4249 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
4251 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4252 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
4253 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
4254 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4255 []>, EVEX, EVEX_K, EVEX_B;
4259 let Predicates = [HasCDI] in {
4260 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
4261 i512mem, i32mem, "{1to16}">,
4262 EVEX_V512, EVEX_CD8<32, CD8VF>;
4265 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
4266 i512mem, i64mem, "{1to8}">,
4267 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4271 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4273 (VPCONFLICTDrrk VR512:$src1,
4274 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4276 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4278 (VPCONFLICTQrrk VR512:$src1,
4279 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4281 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4282 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4283 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
4285 def : Pat<(store VK1:$src, addr:$dst),
4286 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
4288 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
4289 (truncstore node:$val, node:$ptr), [{
4290 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
4293 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
4294 (MOV8mr addr:$dst, GR8:$src)>;