1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
621 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
622 (ins KRC:$mask, RC:$src1, RC:$src2),
623 !strconcat(OpcodeStr,
624 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
625 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
626 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
629 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
630 (ins KRC:$mask, RC:$src1, x86memop:$src2),
631 !strconcat(OpcodeStr,
632 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
636 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
637 (ins KRC:$mask, RC:$src1, x86memop:$src2),
638 !strconcat(OpcodeStr,
639 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
640 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
641 (mem_frag addr:$src2)))]>,
646 let ExeDomain = SSEPackedSingle in
647 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
648 int_x86_avx512_mask_blend_ps_512,
649 VK16WM, VR512, f512mem,
650 memopv16f32, vselect, v16f32>,
651 EVEX_CD8<32, CD8VF>, EVEX_V512;
652 let ExeDomain = SSEPackedDouble in
653 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
654 int_x86_avx512_mask_blend_pd_512,
655 VK8WM, VR512, f512mem,
656 memopv8f64, vselect, v8f64>,
657 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
659 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
660 int_x86_avx512_mask_blend_d_512,
661 VK16WM, VR512, f512mem,
662 memopv16i32, vselect, v16i32>,
663 EVEX_CD8<32, CD8VF>, EVEX_V512;
665 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
666 int_x86_avx512_mask_blend_q_512,
667 VK8WM, VR512, f512mem,
668 memopv8i64, vselect, v8i64>,
669 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
671 let Predicates = [HasAVX512] in {
672 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
673 (v8f32 VR256X:$src2))),
675 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
676 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
677 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
679 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
680 (v8i32 VR256X:$src2))),
682 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
686 //===----------------------------------------------------------------------===//
687 // Compare Instructions
688 //===----------------------------------------------------------------------===//
690 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
691 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
692 Operand CC, SDNode OpNode, ValueType VT,
693 PatFrag ld_frag, string asm, string asm_alt> {
694 def rr : AVX512Ii8<0xC2, MRMSrcReg,
695 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
696 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
697 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
698 def rm : AVX512Ii8<0xC2, MRMSrcMem,
699 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
700 [(set VK1:$dst, (OpNode (VT RC:$src1),
701 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
702 let neverHasSideEffects = 1 in {
703 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
704 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
705 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
706 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
707 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
708 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
712 let Predicates = [HasAVX512] in {
713 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
714 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
717 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
718 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
719 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
723 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
724 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
725 SDNode OpNode, ValueType vt> {
726 def rr : AVX512BI<opc, MRMSrcReg,
727 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
728 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
729 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
730 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
731 def rm : AVX512BI<opc, MRMSrcMem,
732 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
733 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
734 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
735 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
738 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
739 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
740 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
741 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
743 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
744 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
745 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
746 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
748 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
749 (COPY_TO_REGCLASS (VPCMPGTDZrr
750 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
751 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
753 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
754 (COPY_TO_REGCLASS (VPCMPEQDZrr
755 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
756 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
758 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
759 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
760 SDNode OpNode, ValueType vt, Operand CC, string asm,
762 def rri : AVX512AIi8<opc, MRMSrcReg,
763 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
764 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
765 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
766 def rmi : AVX512AIi8<opc, MRMSrcMem,
767 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
768 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
769 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
770 // Accept explicit immediate argument form instead of comparison code.
771 let neverHasSideEffects = 1 in {
772 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
773 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
774 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
775 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
776 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
777 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
781 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
782 X86cmpm, v16i32, AVXCC,
783 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
784 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
785 EVEX_V512, EVEX_CD8<32, CD8VF>;
786 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
787 X86cmpmu, v16i32, AVXCC,
788 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
789 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
790 EVEX_V512, EVEX_CD8<32, CD8VF>;
792 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
793 X86cmpm, v8i64, AVXCC,
794 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
795 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
796 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
797 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
798 X86cmpmu, v8i64, AVXCC,
799 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
800 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
801 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
803 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
804 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
805 X86MemOperand x86memop, Operand CC,
806 SDNode OpNode, ValueType vt, string asm,
807 string asm_alt, Domain d> {
808 def rri : AVX512PIi8<0xC2, MRMSrcReg,
809 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
810 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
811 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
812 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
814 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
816 // Accept explicit immediate argument form instead of comparison code.
817 let neverHasSideEffects = 1 in {
818 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
819 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
821 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
822 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
827 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
828 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
829 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
830 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
831 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
832 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
833 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
834 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
837 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
838 (COPY_TO_REGCLASS (VCMPPSZrri
839 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
840 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
842 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
843 (COPY_TO_REGCLASS (VPCMPDZrri
844 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
845 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
847 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
848 (COPY_TO_REGCLASS (VPCMPUDZrri
849 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
850 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
853 // Mask register copy, including
854 // - copy between mask registers
855 // - load/store mask registers
856 // - copy from GPR to mask register and vice versa
858 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
859 string OpcodeStr, RegisterClass KRC,
860 ValueType vt, X86MemOperand x86memop> {
861 let neverHasSideEffects = 1 in {
862 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
863 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
865 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
866 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
867 [(set KRC:$dst, (vt (load addr:$src)))]>;
869 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
870 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
874 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
876 RegisterClass KRC, RegisterClass GRC> {
877 let neverHasSideEffects = 1 in {
878 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
879 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
880 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
881 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
885 let Predicates = [HasAVX512] in {
886 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
888 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
892 let Predicates = [HasAVX512] in {
893 // GR16 from/to 16-bit mask
894 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
895 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
896 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
897 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
899 // Store kreg in memory
900 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
901 (KMOVWmk addr:$dst, VK16:$src)>;
903 def : Pat<(store VK8:$src, addr:$dst),
904 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
906 def : Pat<(i1 (load addr:$src)),
907 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
909 def : Pat<(v8i1 (load addr:$src)),
910 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
912 def : Pat<(i1 (trunc (i32 GR32:$src))),
913 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
915 def : Pat<(i1 (trunc (i8 GR8:$src))),
917 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)), VK1)>;
919 def : Pat<(i32 (zext VK1:$src)), (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
920 def : Pat<(i8 (zext VK1:$src)),
922 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
924 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
925 let Predicates = [HasAVX512] in {
926 // GR from/to 8-bit mask without native support
927 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
929 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
931 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
933 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
936 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
937 (COPY_TO_REGCLASS VK16:$src, VK1)>;
938 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
939 (COPY_TO_REGCLASS VK8:$src, VK1)>;
943 // Mask unary operation
945 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
946 RegisterClass KRC, SDPatternOperator OpNode> {
947 let Predicates = [HasAVX512] in
948 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
949 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
950 [(set KRC:$dst, (OpNode KRC:$src))]>;
953 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
954 SDPatternOperator OpNode> {
955 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
959 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
961 multiclass avx512_mask_unop_int<string IntName, string InstName> {
962 let Predicates = [HasAVX512] in
963 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
965 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
966 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
968 defm : avx512_mask_unop_int<"knot", "KNOT">;
970 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
971 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
972 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
974 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
975 def : Pat<(not VK8:$src),
977 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
979 // Mask binary operation
980 // - KAND, KANDN, KOR, KXNOR, KXOR
981 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
982 RegisterClass KRC, SDPatternOperator OpNode> {
983 let Predicates = [HasAVX512] in
984 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
985 !strconcat(OpcodeStr,
986 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
987 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
990 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
991 SDPatternOperator OpNode> {
992 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
996 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
997 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
999 let isCommutable = 1 in {
1000 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1001 let isCommutable = 0 in
1002 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1003 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1004 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1005 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1008 def : Pat<(xor VK1:$src1, VK1:$src2),
1009 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1010 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1012 def : Pat<(or VK1:$src1, VK1:$src2),
1013 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1014 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1016 def : Pat<(not VK1:$src),
1017 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1018 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1019 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1021 def : Pat<(and VK1:$src1, VK1:$src2),
1022 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1023 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1025 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1026 let Predicates = [HasAVX512] in
1027 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1028 (i16 GR16:$src1), (i16 GR16:$src2)),
1029 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1030 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1031 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1034 defm : avx512_mask_binop_int<"kand", "KAND">;
1035 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1036 defm : avx512_mask_binop_int<"kor", "KOR">;
1037 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1038 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1040 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1041 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1042 let Predicates = [HasAVX512] in
1043 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1045 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1046 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1049 defm : avx512_binop_pat<and, KANDWrr>;
1050 defm : avx512_binop_pat<andn, KANDNWrr>;
1051 defm : avx512_binop_pat<or, KORWrr>;
1052 defm : avx512_binop_pat<xnor, KXNORWrr>;
1053 defm : avx512_binop_pat<xor, KXORWrr>;
1056 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1057 RegisterClass KRC> {
1058 let Predicates = [HasAVX512] in
1059 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1060 !strconcat(OpcodeStr,
1061 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1064 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1065 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1066 VEX_4V, VEX_L, OpSize, TB;
1069 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1070 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1071 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1072 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1075 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1076 let Predicates = [HasAVX512] in
1077 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1078 (i16 GR16:$src1), (i16 GR16:$src2)),
1079 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1080 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1081 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1083 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1086 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1088 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1089 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1090 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1091 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1094 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1095 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1099 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1101 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1102 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1103 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1106 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1108 let Predicates = [HasAVX512] in
1109 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1110 !strconcat(OpcodeStr,
1111 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1112 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1115 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1117 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1118 VEX, OpSize, TA, VEX_W;
1121 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1122 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1124 // Mask setting all 0s or 1s
1125 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1126 let Predicates = [HasAVX512] in
1127 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1128 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1129 [(set KRC:$dst, (VT Val))]>;
1132 multiclass avx512_mask_setop_w<PatFrag Val> {
1133 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1134 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1137 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1138 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1140 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1141 let Predicates = [HasAVX512] in {
1142 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1143 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1145 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1146 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1148 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1149 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1151 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1152 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1154 //===----------------------------------------------------------------------===//
1155 // AVX-512 - Aligned and unaligned load and store
1158 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1159 X86MemOperand x86memop, PatFrag ld_frag,
1160 string asm, Domain d> {
1161 let neverHasSideEffects = 1 in
1162 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1163 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1165 let canFoldAsLoad = 1 in
1166 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1167 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1168 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1169 let Constraints = "$src1 = $dst" in {
1170 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1171 (ins RC:$src1, KRC:$mask, RC:$src2),
1173 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1175 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1176 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1178 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1179 [], d>, EVEX, EVEX_K;
1183 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1184 "vmovaps", SSEPackedSingle>,
1185 EVEX_V512, EVEX_CD8<32, CD8VF>;
1186 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1187 "vmovapd", SSEPackedDouble>,
1188 OpSize, EVEX_V512, VEX_W,
1189 EVEX_CD8<64, CD8VF>;
1190 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1191 "vmovups", SSEPackedSingle>,
1192 EVEX_V512, EVEX_CD8<32, CD8VF>;
1193 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1194 "vmovupd", SSEPackedDouble>,
1195 OpSize, EVEX_V512, VEX_W,
1196 EVEX_CD8<64, CD8VF>;
1197 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1198 "vmovaps\t{$src, $dst|$dst, $src}",
1199 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1200 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1201 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1202 "vmovapd\t{$src, $dst|$dst, $src}",
1203 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1204 SSEPackedDouble>, EVEX, EVEX_V512,
1205 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1206 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1207 "vmovups\t{$src, $dst|$dst, $src}",
1208 [(store (v16f32 VR512:$src), addr:$dst)],
1209 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1210 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1211 "vmovupd\t{$src, $dst|$dst, $src}",
1212 [(store (v8f64 VR512:$src), addr:$dst)],
1213 SSEPackedDouble>, EVEX, EVEX_V512,
1214 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1216 let neverHasSideEffects = 1 in {
1217 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1219 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1221 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1223 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1224 EVEX, EVEX_V512, VEX_W;
1225 let mayStore = 1 in {
1226 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1227 (ins i512mem:$dst, VR512:$src),
1228 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1229 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1230 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1231 (ins i512mem:$dst, VR512:$src),
1232 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1233 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1235 let mayLoad = 1 in {
1236 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1238 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1239 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1240 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1242 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1243 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1247 // 512-bit aligned load/store
1248 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1249 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1251 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1252 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1253 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1254 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1256 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1257 RegisterClass RC, RegisterClass KRC,
1258 PatFrag ld_frag, X86MemOperand x86memop> {
1259 let neverHasSideEffects = 1 in
1260 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1261 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1262 let canFoldAsLoad = 1 in
1263 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1264 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1265 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1267 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1268 (ins x86memop:$dst, VR512:$src),
1269 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1270 let Constraints = "$src1 = $dst" in {
1271 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1272 (ins RC:$src1, KRC:$mask, RC:$src2),
1274 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1276 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1277 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1279 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1284 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1285 memopv16i32, i512mem>,
1286 EVEX_V512, EVEX_CD8<32, CD8VF>;
1287 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1288 memopv8i64, i512mem>,
1289 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1291 // 512-bit unaligned load/store
1292 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1293 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1295 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1296 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1297 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1298 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1300 let AddedComplexity = 20 in {
1301 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1302 (v16f32 VR512:$src2))),
1303 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1304 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1305 (v8f64 VR512:$src2))),
1306 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1307 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1308 (v16i32 VR512:$src2))),
1309 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1310 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1311 (v8i64 VR512:$src2))),
1312 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1314 // Move Int Doubleword to Packed Double Int
1316 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1317 "vmovd\t{$src, $dst|$dst, $src}",
1319 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1321 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1322 "vmovd\t{$src, $dst|$dst, $src}",
1324 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1325 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1326 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1327 "vmovq\t{$src, $dst|$dst, $src}",
1329 (v2i64 (scalar_to_vector GR64:$src)))],
1330 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1331 let isCodeGenOnly = 1 in {
1332 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1333 "vmovq\t{$src, $dst|$dst, $src}",
1334 [(set FR64:$dst, (bitconvert GR64:$src))],
1335 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1336 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1337 "vmovq\t{$src, $dst|$dst, $src}",
1338 [(set GR64:$dst, (bitconvert FR64:$src))],
1339 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1341 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1342 "vmovq\t{$src, $dst|$dst, $src}",
1343 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1344 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1345 EVEX_CD8<64, CD8VT1>;
1347 // Move Int Doubleword to Single Scalar
1349 let isCodeGenOnly = 1 in {
1350 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1351 "vmovd\t{$src, $dst|$dst, $src}",
1352 [(set FR32X:$dst, (bitconvert GR32:$src))],
1353 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1355 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1356 "vmovd\t{$src, $dst|$dst, $src}",
1357 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1358 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1361 // Move Packed Doubleword Int to Packed Double Int
1363 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1364 "vmovd\t{$src, $dst|$dst, $src}",
1365 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1366 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1368 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1369 (ins i32mem:$dst, VR128X:$src),
1370 "vmovd\t{$src, $dst|$dst, $src}",
1371 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1372 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1373 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1375 // Move Packed Doubleword Int first element to Doubleword Int
1377 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1378 "vmovq\t{$src, $dst|$dst, $src}",
1379 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1381 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1382 Requires<[HasAVX512, In64BitMode]>;
1384 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1385 (ins i64mem:$dst, VR128X:$src),
1386 "vmovq\t{$src, $dst|$dst, $src}",
1387 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1388 addr:$dst)], IIC_SSE_MOVDQ>,
1389 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1390 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1392 // Move Scalar Single to Double Int
1394 let isCodeGenOnly = 1 in {
1395 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1397 "vmovd\t{$src, $dst|$dst, $src}",
1398 [(set GR32:$dst, (bitconvert FR32X:$src))],
1399 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1400 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1401 (ins i32mem:$dst, FR32X:$src),
1402 "vmovd\t{$src, $dst|$dst, $src}",
1403 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1404 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1407 // Move Quadword Int to Packed Quadword Int
1409 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1411 "vmovq\t{$src, $dst|$dst, $src}",
1413 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1414 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1416 //===----------------------------------------------------------------------===//
1417 // AVX-512 MOVSS, MOVSD
1418 //===----------------------------------------------------------------------===//
1420 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1421 SDNode OpNode, ValueType vt,
1422 X86MemOperand x86memop, PatFrag mem_pat> {
1423 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1424 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1425 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1426 (scalar_to_vector RC:$src2))))],
1427 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1428 let Constraints = "$src1 = $dst" in
1429 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1430 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1432 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1433 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1434 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1435 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1436 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1438 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1439 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1440 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1444 let ExeDomain = SSEPackedSingle in
1445 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1446 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1448 let ExeDomain = SSEPackedDouble in
1449 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1450 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1452 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1453 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1454 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1456 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1457 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1458 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1460 // For the disassembler
1461 let isCodeGenOnly = 1 in {
1462 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1463 (ins VR128X:$src1, FR32X:$src2),
1464 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1466 XS, EVEX_4V, VEX_LIG;
1467 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1468 (ins VR128X:$src1, FR64X:$src2),
1469 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1471 XD, EVEX_4V, VEX_LIG, VEX_W;
1474 let Predicates = [HasAVX512] in {
1475 let AddedComplexity = 15 in {
1476 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1477 // MOVS{S,D} to the lower bits.
1478 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1479 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1480 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1481 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1482 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1483 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1484 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1485 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1487 // Move low f32 and clear high bits.
1488 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1489 (SUBREG_TO_REG (i32 0),
1490 (VMOVSSZrr (v4f32 (V_SET0)),
1491 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1492 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1493 (SUBREG_TO_REG (i32 0),
1494 (VMOVSSZrr (v4i32 (V_SET0)),
1495 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1498 let AddedComplexity = 20 in {
1499 // MOVSSrm zeros the high parts of the register; represent this
1500 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1501 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1502 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1503 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1504 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1505 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1506 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1508 // MOVSDrm zeros the high parts of the register; represent this
1509 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1510 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1511 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1512 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1513 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1514 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1515 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1516 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1517 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1518 def : Pat<(v2f64 (X86vzload addr:$src)),
1519 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1521 // Represent the same patterns above but in the form they appear for
1523 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1524 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1525 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1526 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1527 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1528 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1529 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1530 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1531 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1533 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1534 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1535 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1536 FR32X:$src)), sub_xmm)>;
1537 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1538 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1539 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1540 FR64X:$src)), sub_xmm)>;
1541 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1542 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1543 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1545 // Move low f64 and clear high bits.
1546 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1547 (SUBREG_TO_REG (i32 0),
1548 (VMOVSDZrr (v2f64 (V_SET0)),
1549 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1551 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1552 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1553 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1555 // Extract and store.
1556 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1558 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1559 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1561 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1563 // Shuffle with VMOVSS
1564 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1565 (VMOVSSZrr (v4i32 VR128X:$src1),
1566 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1567 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1568 (VMOVSSZrr (v4f32 VR128X:$src1),
1569 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1572 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1573 (SUBREG_TO_REG (i32 0),
1574 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1575 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1577 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1578 (SUBREG_TO_REG (i32 0),
1579 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1580 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1583 // Shuffle with VMOVSD
1584 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1585 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1586 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1587 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1588 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1589 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1590 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1591 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1594 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1595 (SUBREG_TO_REG (i32 0),
1596 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1597 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1599 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1600 (SUBREG_TO_REG (i32 0),
1601 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1602 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1605 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1606 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1607 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1608 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1609 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1610 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1611 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1612 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1615 let AddedComplexity = 15 in
1616 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1618 "vmovq\t{$src, $dst|$dst, $src}",
1619 [(set VR128X:$dst, (v2i64 (X86vzmovl
1620 (v2i64 VR128X:$src))))],
1621 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1623 let AddedComplexity = 20 in
1624 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1626 "vmovq\t{$src, $dst|$dst, $src}",
1627 [(set VR128X:$dst, (v2i64 (X86vzmovl
1628 (loadv2i64 addr:$src))))],
1629 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1630 EVEX_CD8<8, CD8VT8>;
1632 let Predicates = [HasAVX512] in {
1633 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1634 let AddedComplexity = 20 in {
1635 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1636 (VMOVDI2PDIZrm addr:$src)>;
1637 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1638 (VMOV64toPQIZrr GR64:$src)>;
1639 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1640 (VMOVDI2PDIZrr GR32:$src)>;
1642 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1643 (VMOVDI2PDIZrm addr:$src)>;
1644 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1645 (VMOVDI2PDIZrm addr:$src)>;
1646 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1647 (VMOVZPQILo2PQIZrm addr:$src)>;
1648 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1649 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1650 def : Pat<(v2i64 (X86vzload addr:$src)),
1651 (VMOVZPQILo2PQIZrm addr:$src)>;
1654 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1655 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1656 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1657 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1658 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1659 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1660 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1663 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1664 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1666 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1667 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1669 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1670 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1672 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1673 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1675 //===----------------------------------------------------------------------===//
1676 // AVX-512 - Integer arithmetic
1678 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1679 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1680 X86MemOperand x86memop, PatFrag scalar_mfrag,
1681 X86MemOperand x86scalar_mop, string BrdcstStr,
1682 OpndItins itins, bit IsCommutable = 0> {
1683 let isCommutable = IsCommutable in
1684 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1685 (ins RC:$src1, RC:$src2),
1686 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1687 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1689 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1690 (ins RC:$src1, x86memop:$src2),
1691 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1692 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1694 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1695 (ins RC:$src1, x86scalar_mop:$src2),
1696 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1697 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1698 [(set RC:$dst, (OpNode RC:$src1,
1699 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1700 itins.rm>, EVEX_4V, EVEX_B;
1702 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1703 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1704 PatFrag memop_frag, X86MemOperand x86memop,
1706 bit IsCommutable = 0> {
1707 let isCommutable = IsCommutable in
1708 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1709 (ins RC:$src1, RC:$src2),
1710 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1711 []>, EVEX_4V, VEX_W;
1712 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1713 (ins RC:$src1, x86memop:$src2),
1714 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1715 []>, EVEX_4V, VEX_W;
1718 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1719 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1720 EVEX_V512, EVEX_CD8<32, CD8VF>;
1722 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1723 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1724 EVEX_V512, EVEX_CD8<32, CD8VF>;
1726 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1727 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1728 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1730 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1731 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1732 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1734 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1735 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1736 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1738 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1739 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1740 EVEX_V512, EVEX_CD8<64, CD8VF>;
1742 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1743 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1744 EVEX_CD8<64, CD8VF>;
1746 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1747 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1749 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1750 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1751 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1752 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1753 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1754 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1756 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1757 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1758 EVEX_V512, EVEX_CD8<32, CD8VF>;
1759 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1760 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1761 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1763 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1764 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1765 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1766 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1767 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1768 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1770 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1771 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1772 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1773 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1774 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1775 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1777 //===----------------------------------------------------------------------===//
1778 // AVX-512 - Unpack Instructions
1779 //===----------------------------------------------------------------------===//
1781 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1782 PatFrag mem_frag, RegisterClass RC,
1783 X86MemOperand x86memop, string asm,
1785 def rr : AVX512PI<opc, MRMSrcReg,
1786 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1788 (vt (OpNode RC:$src1, RC:$src2)))],
1790 def rm : AVX512PI<opc, MRMSrcMem,
1791 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1793 (vt (OpNode RC:$src1,
1794 (bitconvert (mem_frag addr:$src2)))))],
1798 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1799 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1800 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1801 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1802 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1803 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1804 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1805 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1806 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1807 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1808 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1809 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1811 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1812 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1813 X86MemOperand x86memop> {
1814 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1815 (ins RC:$src1, RC:$src2),
1816 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1817 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1818 IIC_SSE_UNPCK>, EVEX_4V;
1819 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1820 (ins RC:$src1, x86memop:$src2),
1821 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1822 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1823 (bitconvert (memop_frag addr:$src2)))))],
1824 IIC_SSE_UNPCK>, EVEX_4V;
1826 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1827 VR512, memopv16i32, i512mem>, EVEX_V512,
1828 EVEX_CD8<32, CD8VF>;
1829 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1830 VR512, memopv8i64, i512mem>, EVEX_V512,
1831 VEX_W, EVEX_CD8<64, CD8VF>;
1832 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1833 VR512, memopv16i32, i512mem>, EVEX_V512,
1834 EVEX_CD8<32, CD8VF>;
1835 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1836 VR512, memopv8i64, i512mem>, EVEX_V512,
1837 VEX_W, EVEX_CD8<64, CD8VF>;
1838 //===----------------------------------------------------------------------===//
1842 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1843 SDNode OpNode, PatFrag mem_frag,
1844 X86MemOperand x86memop, ValueType OpVT> {
1845 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1846 (ins RC:$src1, i8imm:$src2),
1847 !strconcat(OpcodeStr,
1848 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1850 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1852 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1853 (ins x86memop:$src1, i8imm:$src2),
1854 !strconcat(OpcodeStr,
1855 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1857 (OpVT (OpNode (mem_frag addr:$src1),
1858 (i8 imm:$src2))))]>, EVEX;
1861 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1862 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1864 let ExeDomain = SSEPackedSingle in
1865 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1866 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1867 EVEX_CD8<32, CD8VF>;
1868 let ExeDomain = SSEPackedDouble in
1869 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1870 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1871 VEX_W, EVEX_CD8<32, CD8VF>;
1873 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1874 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1875 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1876 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1878 //===----------------------------------------------------------------------===//
1879 // AVX-512 Logical Instructions
1880 //===----------------------------------------------------------------------===//
1882 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1883 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1884 EVEX_V512, EVEX_CD8<32, CD8VF>;
1885 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1886 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1887 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1888 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1889 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1890 EVEX_V512, EVEX_CD8<32, CD8VF>;
1891 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1892 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1893 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1894 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1895 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1896 EVEX_V512, EVEX_CD8<32, CD8VF>;
1897 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1898 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1899 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1900 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1901 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1902 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1903 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1904 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1905 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1907 //===----------------------------------------------------------------------===//
1908 // AVX-512 FP arithmetic
1909 //===----------------------------------------------------------------------===//
1911 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1913 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1914 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1915 EVEX_CD8<32, CD8VT1>;
1916 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1917 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1918 EVEX_CD8<64, CD8VT1>;
1921 let isCommutable = 1 in {
1922 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1923 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1924 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1925 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1927 let isCommutable = 0 in {
1928 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1929 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1932 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1933 RegisterClass RC, ValueType vt,
1934 X86MemOperand x86memop, PatFrag mem_frag,
1935 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1937 Domain d, OpndItins itins, bit commutable> {
1938 let isCommutable = commutable in
1939 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1940 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1941 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1943 let mayLoad = 1 in {
1944 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1945 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1946 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1947 itins.rm, d>, EVEX_4V, TB;
1948 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1949 (ins RC:$src1, x86scalar_mop:$src2),
1950 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1951 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1952 [(set RC:$dst, (OpNode RC:$src1,
1953 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1954 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1958 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1959 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1960 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1962 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1963 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1964 SSE_ALU_ITINS_P.d, 1>,
1965 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1967 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1968 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1969 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1970 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1971 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1972 SSE_ALU_ITINS_P.d, 1>,
1973 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1975 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1976 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1977 SSE_ALU_ITINS_P.s, 1>,
1978 EVEX_V512, EVEX_CD8<32, CD8VF>;
1979 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1980 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1981 SSE_ALU_ITINS_P.s, 1>,
1982 EVEX_V512, EVEX_CD8<32, CD8VF>;
1984 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1985 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1986 SSE_ALU_ITINS_P.d, 1>,
1987 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1988 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1989 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1990 SSE_ALU_ITINS_P.d, 1>,
1991 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1993 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1994 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1995 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1996 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1997 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1998 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2000 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2001 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2002 SSE_ALU_ITINS_P.d, 0>,
2003 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2004 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2005 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2006 SSE_ALU_ITINS_P.d, 0>,
2007 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
2009 //===----------------------------------------------------------------------===//
2010 // AVX-512 VPTESTM instructions
2011 //===----------------------------------------------------------------------===//
2013 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2014 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2015 SDNode OpNode, ValueType vt> {
2016 def rr : AVX5128I<opc, MRMSrcReg,
2017 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2018 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2019 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2020 def rm : AVX5128I<opc, MRMSrcMem,
2021 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2022 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2023 [(set KRC:$dst, (OpNode (vt RC:$src1),
2024 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2027 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2028 memopv16i32, X86testm, v16i32>, EVEX_V512,
2029 EVEX_CD8<32, CD8VF>;
2030 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2031 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2032 EVEX_CD8<64, CD8VF>;
2034 //===----------------------------------------------------------------------===//
2035 // AVX-512 Shift instructions
2036 //===----------------------------------------------------------------------===//
2037 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2038 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2039 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2040 RegisterClass KRC> {
2041 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2042 (ins RC:$src1, i8imm:$src2),
2043 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2044 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2045 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2046 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2047 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2048 !strconcat(OpcodeStr,
2049 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2050 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2051 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2052 (ins x86memop:$src1, i8imm:$src2),
2053 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2054 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2055 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2056 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2057 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2058 !strconcat(OpcodeStr,
2059 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2060 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2063 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2064 RegisterClass RC, ValueType vt, ValueType SrcVT,
2065 PatFrag bc_frag, RegisterClass KRC> {
2066 // src2 is always 128-bit
2067 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2068 (ins RC:$src1, VR128X:$src2),
2069 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2070 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2071 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2072 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2073 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2074 !strconcat(OpcodeStr,
2075 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2076 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2077 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2078 (ins RC:$src1, i128mem:$src2),
2079 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2080 [(set RC:$dst, (vt (OpNode RC:$src1,
2081 (bc_frag (memopv2i64 addr:$src2)))))],
2082 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2083 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2084 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2085 !strconcat(OpcodeStr,
2086 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2087 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2090 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2091 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2092 EVEX_V512, EVEX_CD8<32, CD8VF>;
2093 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2094 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2095 EVEX_CD8<32, CD8VQ>;
2097 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2098 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2099 EVEX_CD8<64, CD8VF>, VEX_W;
2100 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2101 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2102 EVEX_CD8<64, CD8VQ>, VEX_W;
2104 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2105 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2106 EVEX_CD8<32, CD8VF>;
2107 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2108 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2109 EVEX_CD8<32, CD8VQ>;
2111 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2112 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2113 EVEX_CD8<64, CD8VF>, VEX_W;
2114 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2115 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2116 EVEX_CD8<64, CD8VQ>, VEX_W;
2118 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2119 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2120 EVEX_V512, EVEX_CD8<32, CD8VF>;
2121 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2122 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2123 EVEX_CD8<32, CD8VQ>;
2125 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2126 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2127 EVEX_CD8<64, CD8VF>, VEX_W;
2128 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2129 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2130 EVEX_CD8<64, CD8VQ>, VEX_W;
2132 //===-------------------------------------------------------------------===//
2133 // Variable Bit Shifts
2134 //===-------------------------------------------------------------------===//
2135 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2136 RegisterClass RC, ValueType vt,
2137 X86MemOperand x86memop, PatFrag mem_frag> {
2138 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2139 (ins RC:$src1, RC:$src2),
2140 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2142 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2144 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2145 (ins RC:$src1, x86memop:$src2),
2146 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2148 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2152 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2153 i512mem, memopv16i32>, EVEX_V512,
2154 EVEX_CD8<32, CD8VF>;
2155 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2156 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2157 EVEX_CD8<64, CD8VF>;
2158 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2159 i512mem, memopv16i32>, EVEX_V512,
2160 EVEX_CD8<32, CD8VF>;
2161 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2162 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2163 EVEX_CD8<64, CD8VF>;
2164 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2165 i512mem, memopv16i32>, EVEX_V512,
2166 EVEX_CD8<32, CD8VF>;
2167 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2168 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2169 EVEX_CD8<64, CD8VF>;
2171 //===----------------------------------------------------------------------===//
2172 // AVX-512 - MOVDDUP
2173 //===----------------------------------------------------------------------===//
2175 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2176 X86MemOperand x86memop, PatFrag memop_frag> {
2177 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2178 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2179 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2180 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2181 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2183 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2186 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2187 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2188 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2189 (VMOVDDUPZrm addr:$src)>;
2191 //===---------------------------------------------------------------------===//
2192 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2193 //===---------------------------------------------------------------------===//
2194 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2195 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2196 X86MemOperand x86memop> {
2197 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2198 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2199 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2201 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2202 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2203 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2206 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2207 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2208 EVEX_CD8<32, CD8VF>;
2209 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2210 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2211 EVEX_CD8<32, CD8VF>;
2213 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2214 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2215 (VMOVSHDUPZrm addr:$src)>;
2216 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2217 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2218 (VMOVSLDUPZrm addr:$src)>;
2220 //===----------------------------------------------------------------------===//
2221 // Move Low to High and High to Low packed FP Instructions
2222 //===----------------------------------------------------------------------===//
2223 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2224 (ins VR128X:$src1, VR128X:$src2),
2225 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2226 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2227 IIC_SSE_MOV_LH>, EVEX_4V;
2228 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2229 (ins VR128X:$src1, VR128X:$src2),
2230 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2231 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2232 IIC_SSE_MOV_LH>, EVEX_4V;
2234 let Predicates = [HasAVX512] in {
2236 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2237 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2238 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2239 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2242 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2243 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2246 //===----------------------------------------------------------------------===//
2247 // FMA - Fused Multiply Operations
2249 let Constraints = "$src1 = $dst" in {
2250 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2251 RegisterClass RC, X86MemOperand x86memop,
2252 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2253 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2254 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2255 (ins RC:$src1, RC:$src2, RC:$src3),
2256 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2257 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2260 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2261 (ins RC:$src1, RC:$src2, x86memop:$src3),
2262 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2263 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2264 (mem_frag addr:$src3))))]>;
2265 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2266 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2267 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2268 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2269 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2270 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2272 } // Constraints = "$src1 = $dst"
2274 let ExeDomain = SSEPackedSingle in {
2275 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2276 memopv16f32, f32mem, loadf32, "{1to16}",
2277 X86Fmadd, v16f32>, EVEX_V512,
2278 EVEX_CD8<32, CD8VF>;
2279 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2280 memopv16f32, f32mem, loadf32, "{1to16}",
2281 X86Fmsub, v16f32>, EVEX_V512,
2282 EVEX_CD8<32, CD8VF>;
2283 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2284 memopv16f32, f32mem, loadf32, "{1to16}",
2285 X86Fmaddsub, v16f32>,
2286 EVEX_V512, EVEX_CD8<32, CD8VF>;
2287 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2288 memopv16f32, f32mem, loadf32, "{1to16}",
2289 X86Fmsubadd, v16f32>,
2290 EVEX_V512, EVEX_CD8<32, CD8VF>;
2291 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2292 memopv16f32, f32mem, loadf32, "{1to16}",
2293 X86Fnmadd, v16f32>, EVEX_V512,
2294 EVEX_CD8<32, CD8VF>;
2295 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2296 memopv16f32, f32mem, loadf32, "{1to16}",
2297 X86Fnmsub, v16f32>, EVEX_V512,
2298 EVEX_CD8<32, CD8VF>;
2300 let ExeDomain = SSEPackedDouble in {
2301 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2302 memopv8f64, f64mem, loadf64, "{1to8}",
2303 X86Fmadd, v8f64>, EVEX_V512,
2304 VEX_W, EVEX_CD8<64, CD8VF>;
2305 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2306 memopv8f64, f64mem, loadf64, "{1to8}",
2307 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2308 EVEX_CD8<64, CD8VF>;
2309 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2310 memopv8f64, f64mem, loadf64, "{1to8}",
2311 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2312 EVEX_CD8<64, CD8VF>;
2313 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2314 memopv8f64, f64mem, loadf64, "{1to8}",
2315 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2316 EVEX_CD8<64, CD8VF>;
2317 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2318 memopv8f64, f64mem, loadf64, "{1to8}",
2319 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2320 EVEX_CD8<64, CD8VF>;
2321 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2322 memopv8f64, f64mem, loadf64, "{1to8}",
2323 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2324 EVEX_CD8<64, CD8VF>;
2327 let Constraints = "$src1 = $dst" in {
2328 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2329 RegisterClass RC, X86MemOperand x86memop,
2330 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2331 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2333 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2334 (ins RC:$src1, RC:$src3, x86memop:$src2),
2335 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2336 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2337 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2338 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2339 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2340 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2341 [(set RC:$dst, (OpNode RC:$src1,
2342 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2344 } // Constraints = "$src1 = $dst"
2347 let ExeDomain = SSEPackedSingle in {
2348 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2349 memopv16f32, f32mem, loadf32, "{1to16}",
2350 X86Fmadd, v16f32>, EVEX_V512,
2351 EVEX_CD8<32, CD8VF>;
2352 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2353 memopv16f32, f32mem, loadf32, "{1to16}",
2354 X86Fmsub, v16f32>, EVEX_V512,
2355 EVEX_CD8<32, CD8VF>;
2356 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2357 memopv16f32, f32mem, loadf32, "{1to16}",
2358 X86Fmaddsub, v16f32>,
2359 EVEX_V512, EVEX_CD8<32, CD8VF>;
2360 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2361 memopv16f32, f32mem, loadf32, "{1to16}",
2362 X86Fmsubadd, v16f32>,
2363 EVEX_V512, EVEX_CD8<32, CD8VF>;
2364 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2365 memopv16f32, f32mem, loadf32, "{1to16}",
2366 X86Fnmadd, v16f32>, EVEX_V512,
2367 EVEX_CD8<32, CD8VF>;
2368 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2369 memopv16f32, f32mem, loadf32, "{1to16}",
2370 X86Fnmsub, v16f32>, EVEX_V512,
2371 EVEX_CD8<32, CD8VF>;
2373 let ExeDomain = SSEPackedDouble in {
2374 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2375 memopv8f64, f64mem, loadf64, "{1to8}",
2376 X86Fmadd, v8f64>, EVEX_V512,
2377 VEX_W, EVEX_CD8<64, CD8VF>;
2378 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2379 memopv8f64, f64mem, loadf64, "{1to8}",
2380 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2381 EVEX_CD8<64, CD8VF>;
2382 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2383 memopv8f64, f64mem, loadf64, "{1to8}",
2384 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2385 EVEX_CD8<64, CD8VF>;
2386 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2387 memopv8f64, f64mem, loadf64, "{1to8}",
2388 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2389 EVEX_CD8<64, CD8VF>;
2390 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2391 memopv8f64, f64mem, loadf64, "{1to8}",
2392 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2393 EVEX_CD8<64, CD8VF>;
2394 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2395 memopv8f64, f64mem, loadf64, "{1to8}",
2396 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2397 EVEX_CD8<64, CD8VF>;
2401 let Constraints = "$src1 = $dst" in {
2402 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2403 RegisterClass RC, ValueType OpVT,
2404 X86MemOperand x86memop, Operand memop,
2406 let isCommutable = 1 in
2407 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2408 (ins RC:$src1, RC:$src2, RC:$src3),
2409 !strconcat(OpcodeStr,
2410 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2412 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2414 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2415 (ins RC:$src1, RC:$src2, f128mem:$src3),
2416 !strconcat(OpcodeStr,
2417 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2419 (OpVT (OpNode RC:$src2, RC:$src1,
2420 (mem_frag addr:$src3))))]>;
2423 } // Constraints = "$src1 = $dst"
2425 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2426 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2427 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2428 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2429 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2430 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2431 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2432 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2433 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2434 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2435 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2436 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2437 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2438 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2439 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2440 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2442 //===----------------------------------------------------------------------===//
2443 // AVX-512 Scalar convert from sign integer to float/double
2444 //===----------------------------------------------------------------------===//
2446 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2447 X86MemOperand x86memop, string asm> {
2448 let neverHasSideEffects = 1 in {
2449 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2450 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2453 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2454 (ins DstRC:$src1, x86memop:$src),
2455 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2457 } // neverHasSideEffects = 1
2459 let Predicates = [HasAVX512] in {
2460 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2461 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2462 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2463 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2464 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2465 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2466 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2467 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2469 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2470 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2471 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2472 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2473 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2474 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2475 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2476 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2478 def : Pat<(f32 (sint_to_fp GR32:$src)),
2479 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2480 def : Pat<(f32 (sint_to_fp GR64:$src)),
2481 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2482 def : Pat<(f64 (sint_to_fp GR32:$src)),
2483 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2484 def : Pat<(f64 (sint_to_fp GR64:$src)),
2485 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2487 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2488 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2489 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2490 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2491 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2492 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2493 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2494 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2496 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2497 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2498 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2499 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2500 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2501 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2502 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2503 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2505 def : Pat<(f32 (uint_to_fp GR32:$src)),
2506 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2507 def : Pat<(f32 (uint_to_fp GR64:$src)),
2508 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2509 def : Pat<(f64 (uint_to_fp GR32:$src)),
2510 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2511 def : Pat<(f64 (uint_to_fp GR64:$src)),
2512 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2515 //===----------------------------------------------------------------------===//
2516 // AVX-512 Scalar convert from float/double to integer
2517 //===----------------------------------------------------------------------===//
2518 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2519 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2521 let neverHasSideEffects = 1 in {
2522 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2523 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2524 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2525 Requires<[HasAVX512]>;
2527 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2528 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2529 Requires<[HasAVX512]>;
2530 } // neverHasSideEffects = 1
2532 let Predicates = [HasAVX512] in {
2533 // Convert float/double to signed/unsigned int 32/64
2534 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2535 ssmem, sse_load_f32, "cvtss2si">,
2536 XS, EVEX_CD8<32, CD8VT1>;
2537 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2538 ssmem, sse_load_f32, "cvtss2si">,
2539 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2540 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2541 ssmem, sse_load_f32, "cvtss2usi">,
2542 XS, EVEX_CD8<32, CD8VT1>;
2543 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2544 int_x86_avx512_cvtss2usi64, ssmem,
2545 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2546 EVEX_CD8<32, CD8VT1>;
2547 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2548 sdmem, sse_load_f64, "cvtsd2si">,
2549 XD, EVEX_CD8<64, CD8VT1>;
2550 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2551 sdmem, sse_load_f64, "cvtsd2si">,
2552 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2553 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2554 sdmem, sse_load_f64, "cvtsd2usi">,
2555 XD, EVEX_CD8<64, CD8VT1>;
2556 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2557 int_x86_avx512_cvtsd2usi64, sdmem,
2558 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2559 EVEX_CD8<64, CD8VT1>;
2561 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2562 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2563 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2564 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2565 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2566 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2567 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2568 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2569 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2570 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2571 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2572 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2574 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2575 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2576 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2577 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2578 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2579 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2580 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2581 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2582 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2583 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2584 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2585 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2587 // Convert float/double to signed/unsigned int 32/64 with truncation
2588 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2589 ssmem, sse_load_f32, "cvttss2si">,
2590 XS, EVEX_CD8<32, CD8VT1>;
2591 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2592 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2593 "cvttss2si">, XS, VEX_W,
2594 EVEX_CD8<32, CD8VT1>;
2595 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2596 sdmem, sse_load_f64, "cvttsd2si">, XD,
2597 EVEX_CD8<64, CD8VT1>;
2598 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2599 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2600 "cvttsd2si">, XD, VEX_W,
2601 EVEX_CD8<64, CD8VT1>;
2602 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2603 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2604 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2605 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2606 int_x86_avx512_cvttss2usi64, ssmem,
2607 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2608 EVEX_CD8<32, CD8VT1>;
2609 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2610 int_x86_avx512_cvttsd2usi,
2611 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2612 EVEX_CD8<64, CD8VT1>;
2613 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2614 int_x86_avx512_cvttsd2usi64, sdmem,
2615 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2616 EVEX_CD8<64, CD8VT1>;
2618 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2619 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2621 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2622 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2623 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2624 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2625 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2626 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2629 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2630 loadf32, "cvttss2si">, XS,
2631 EVEX_CD8<32, CD8VT1>;
2632 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2633 loadf32, "cvttss2usi">, XS,
2634 EVEX_CD8<32, CD8VT1>;
2635 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2636 loadf32, "cvttss2si">, XS, VEX_W,
2637 EVEX_CD8<32, CD8VT1>;
2638 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2639 loadf32, "cvttss2usi">, XS, VEX_W,
2640 EVEX_CD8<32, CD8VT1>;
2641 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2642 loadf64, "cvttsd2si">, XD,
2643 EVEX_CD8<64, CD8VT1>;
2644 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2645 loadf64, "cvttsd2usi">, XD,
2646 EVEX_CD8<64, CD8VT1>;
2647 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2648 loadf64, "cvttsd2si">, XD, VEX_W,
2649 EVEX_CD8<64, CD8VT1>;
2650 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2651 loadf64, "cvttsd2usi">, XD, VEX_W,
2652 EVEX_CD8<64, CD8VT1>;
2654 //===----------------------------------------------------------------------===//
2655 // AVX-512 Convert form float to double and back
2656 //===----------------------------------------------------------------------===//
2657 let neverHasSideEffects = 1 in {
2658 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2659 (ins FR32X:$src1, FR32X:$src2),
2660 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2661 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2663 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2664 (ins FR32X:$src1, f32mem:$src2),
2665 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2666 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2667 EVEX_CD8<32, CD8VT1>;
2669 // Convert scalar double to scalar single
2670 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2671 (ins FR64X:$src1, FR64X:$src2),
2672 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2673 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2675 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2676 (ins FR64X:$src1, f64mem:$src2),
2677 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2678 []>, EVEX_4V, VEX_LIG, VEX_W,
2679 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2682 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2683 Requires<[HasAVX512]>;
2684 def : Pat<(fextend (loadf32 addr:$src)),
2685 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2687 def : Pat<(extloadf32 addr:$src),
2688 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2689 Requires<[HasAVX512, OptForSize]>;
2691 def : Pat<(extloadf32 addr:$src),
2692 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2693 Requires<[HasAVX512, OptForSpeed]>;
2695 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2696 Requires<[HasAVX512]>;
2698 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2699 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2700 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2702 let neverHasSideEffects = 1 in {
2703 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2704 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2706 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2708 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2709 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2711 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2712 } // neverHasSideEffects = 1
2715 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2716 memopv8f64, f512mem, v8f32, v8f64,
2717 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2718 EVEX_CD8<64, CD8VF>;
2720 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2721 memopv4f64, f256mem, v8f64, v8f32,
2722 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2723 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2724 (VCVTPS2PDZrm addr:$src)>;
2726 //===----------------------------------------------------------------------===//
2727 // AVX-512 Vector convert from sign integer to float/double
2728 //===----------------------------------------------------------------------===//
2730 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2731 memopv8i64, i512mem, v16f32, v16i32,
2732 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2734 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2735 memopv4i64, i256mem, v8f64, v8i32,
2736 SSEPackedDouble>, EVEX_V512, XS,
2737 EVEX_CD8<32, CD8VH>;
2739 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2740 memopv16f32, f512mem, v16i32, v16f32,
2741 SSEPackedSingle>, EVEX_V512, XS,
2742 EVEX_CD8<32, CD8VF>;
2744 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2745 memopv8f64, f512mem, v8i32, v8f64,
2746 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2747 EVEX_CD8<64, CD8VF>;
2749 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2750 memopv16f32, f512mem, v16i32, v16f32,
2751 SSEPackedSingle>, EVEX_V512,
2752 EVEX_CD8<32, CD8VF>;
2754 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2755 memopv8f64, f512mem, v8i32, v8f64,
2756 SSEPackedDouble>, EVEX_V512, VEX_W,
2757 EVEX_CD8<64, CD8VF>;
2759 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2760 memopv4i64, f256mem, v8f64, v8i32,
2761 SSEPackedDouble>, EVEX_V512, XS,
2762 EVEX_CD8<32, CD8VH>;
2764 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2765 memopv16i32, f512mem, v16f32, v16i32,
2766 SSEPackedSingle>, EVEX_V512, XD,
2767 EVEX_CD8<32, CD8VF>;
2769 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2770 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2771 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2774 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2775 (VCVTDQ2PSZrr VR512:$src)>;
2776 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2777 (VCVTDQ2PSZrm addr:$src)>;
2779 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2780 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2782 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2783 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2784 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2785 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2787 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2788 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2791 let Predicates = [HasAVX512] in {
2792 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2793 (VCVTPD2PSZrm addr:$src)>;
2794 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2795 (VCVTPS2PDZrm addr:$src)>;
2798 //===----------------------------------------------------------------------===//
2799 // Half precision conversion instructions
2800 //===----------------------------------------------------------------------===//
2801 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2802 X86MemOperand x86memop, Intrinsic Int> {
2803 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2804 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2805 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2806 let neverHasSideEffects = 1, mayLoad = 1 in
2807 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2808 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2811 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2812 X86MemOperand x86memop, Intrinsic Int> {
2813 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2814 (ins srcRC:$src1, i32i8imm:$src2),
2815 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2816 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2817 let neverHasSideEffects = 1, mayStore = 1 in
2818 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2819 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2820 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2823 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2824 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2825 EVEX_CD8<32, CD8VH>;
2826 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2827 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2828 EVEX_CD8<32, CD8VH>;
2830 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2831 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2832 "ucomiss">, TB, EVEX, VEX_LIG,
2833 EVEX_CD8<32, CD8VT1>;
2834 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2835 "ucomisd">, TB, OpSize, EVEX,
2836 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2837 let Pattern = []<dag> in {
2838 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2839 "comiss">, TB, EVEX, VEX_LIG,
2840 EVEX_CD8<32, CD8VT1>;
2841 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2842 "comisd">, TB, OpSize, EVEX,
2843 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2845 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2846 load, "ucomiss">, TB, EVEX, VEX_LIG,
2847 EVEX_CD8<32, CD8VT1>;
2848 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2849 load, "ucomisd">, TB, OpSize, EVEX,
2850 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2852 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2853 load, "comiss">, TB, EVEX, VEX_LIG,
2854 EVEX_CD8<32, CD8VT1>;
2855 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2856 load, "comisd">, TB, OpSize, EVEX,
2857 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2860 /// avx512_unop_p - AVX-512 unops in packed form.
2861 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2862 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2863 !strconcat(OpcodeStr,
2864 "ps\t{$src, $dst|$dst, $src}"),
2865 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2867 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2868 !strconcat(OpcodeStr,
2869 "ps\t{$src, $dst|$dst, $src}"),
2870 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2871 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2872 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2873 !strconcat(OpcodeStr,
2874 "pd\t{$src, $dst|$dst, $src}"),
2875 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2876 EVEX, EVEX_V512, VEX_W;
2877 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2878 !strconcat(OpcodeStr,
2879 "pd\t{$src, $dst|$dst, $src}"),
2880 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2881 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2884 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2885 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2886 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2887 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2888 !strconcat(OpcodeStr,
2889 "ps\t{$src, $dst|$dst, $src}"),
2890 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2892 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2893 !strconcat(OpcodeStr,
2894 "ps\t{$src, $dst|$dst, $src}"),
2896 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2897 EVEX_V512, EVEX_CD8<32, CD8VF>;
2898 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2899 !strconcat(OpcodeStr,
2900 "pd\t{$src, $dst|$dst, $src}"),
2901 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2902 EVEX, EVEX_V512, VEX_W;
2903 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2904 !strconcat(OpcodeStr,
2905 "pd\t{$src, $dst|$dst, $src}"),
2907 (V8F64Int (memopv8f64 addr:$src)))]>,
2908 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2911 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
2912 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
2913 let hasSideEffects = 0 in {
2914 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2915 (ins FR32X:$src1, FR32X:$src2),
2916 !strconcat(OpcodeStr,
2917 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2919 let mayLoad = 1 in {
2920 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2921 (ins FR32X:$src1, f32mem:$src2),
2922 !strconcat(OpcodeStr,
2923 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2924 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2925 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2926 (ins VR128X:$src1, ssmem:$src2),
2927 !strconcat(OpcodeStr,
2928 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2929 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2931 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2932 (ins FR64X:$src1, FR64X:$src2),
2933 !strconcat(OpcodeStr,
2934 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2936 let mayLoad = 1 in {
2937 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2938 (ins FR64X:$src1, f64mem:$src2),
2939 !strconcat(OpcodeStr,
2940 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2941 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2942 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2943 (ins VR128X:$src1, sdmem:$src2),
2944 !strconcat(OpcodeStr,
2945 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2946 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2951 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
2952 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2953 avx512_fp_unop_p_int<0x4C, "vrcp14",
2954 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2956 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
2957 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2958 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2959 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2961 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2962 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2963 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2965 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2966 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2968 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2969 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2970 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2972 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2973 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2975 let AddedComplexity = 20, Predicates = [HasERI] in {
2976 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2977 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2978 avx512_fp_unop_p_int<0xCA, "vrcp28",
2979 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2981 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2982 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2983 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2984 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2987 let Predicates = [HasERI] in {
2988 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2989 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2990 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2992 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2993 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2995 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2996 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2997 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2999 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
3000 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3002 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3003 Intrinsic V16F32Int, Intrinsic V8F64Int,
3004 OpndItins itins_s, OpndItins itins_d> {
3005 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3006 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3007 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3011 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3012 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3014 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3015 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3017 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3018 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3019 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3023 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3024 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3025 [(set VR512:$dst, (OpNode
3026 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3027 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3029 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3030 !strconcat(OpcodeStr,
3031 "ps\t{$src, $dst|$dst, $src}"),
3032 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3034 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3035 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3037 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3038 EVEX_V512, EVEX_CD8<32, CD8VF>;
3039 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3040 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3041 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3042 EVEX, EVEX_V512, VEX_W;
3043 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3044 !strconcat(OpcodeStr,
3045 "pd\t{$src, $dst|$dst, $src}"),
3046 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3047 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3050 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3051 Intrinsic F32Int, Intrinsic F64Int,
3052 OpndItins itins_s, OpndItins itins_d> {
3053 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3054 (ins FR32X:$src1, FR32X:$src2),
3055 !strconcat(OpcodeStr,
3056 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3057 [], itins_s.rr>, XS, EVEX_4V;
3058 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3059 (ins VR128X:$src1, VR128X:$src2),
3060 !strconcat(OpcodeStr,
3061 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3063 (F32Int VR128X:$src1, VR128X:$src2))],
3064 itins_s.rr>, XS, EVEX_4V;
3065 let mayLoad = 1 in {
3066 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3067 (ins FR32X:$src1, f32mem:$src2),
3068 !strconcat(OpcodeStr,
3069 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3070 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3071 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3072 (ins VR128X:$src1, ssmem:$src2),
3073 !strconcat(OpcodeStr,
3074 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3076 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3077 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3079 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3080 (ins FR64X:$src1, FR64X:$src2),
3081 !strconcat(OpcodeStr,
3082 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3084 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3085 (ins VR128X:$src1, VR128X:$src2),
3086 !strconcat(OpcodeStr,
3087 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3089 (F64Int VR128X:$src1, VR128X:$src2))],
3090 itins_s.rr>, XD, EVEX_4V, VEX_W;
3091 let mayLoad = 1 in {
3092 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3093 (ins FR64X:$src1, f64mem:$src2),
3094 !strconcat(OpcodeStr,
3095 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3096 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3097 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3098 (ins VR128X:$src1, sdmem:$src2),
3099 !strconcat(OpcodeStr,
3100 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3102 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3103 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3108 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3109 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3110 SSE_SQRTSS, SSE_SQRTSD>,
3111 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3112 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3113 SSE_SQRTPS, SSE_SQRTPD>;
3115 let Predicates = [HasAVX512] in {
3116 def : Pat<(f32 (fsqrt FR32X:$src)),
3117 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3118 def : Pat<(f32 (fsqrt (load addr:$src))),
3119 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3120 Requires<[OptForSize]>;
3121 def : Pat<(f64 (fsqrt FR64X:$src)),
3122 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3123 def : Pat<(f64 (fsqrt (load addr:$src))),
3124 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3125 Requires<[OptForSize]>;
3127 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3128 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3129 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3130 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3131 Requires<[OptForSize]>;
3133 def : Pat<(f32 (X86frcp FR32X:$src)),
3134 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3135 def : Pat<(f32 (X86frcp (load addr:$src))),
3136 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3137 Requires<[OptForSize]>;
3139 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3140 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3141 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3143 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3144 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3146 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3147 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3148 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3150 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3151 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3155 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3156 X86MemOperand x86memop, RegisterClass RC,
3157 PatFrag mem_frag32, PatFrag mem_frag64,
3158 Intrinsic V4F32Int, Intrinsic V2F64Int,
3160 let ExeDomain = SSEPackedSingle in {
3161 // Intrinsic operation, reg.
3162 // Vector intrinsic operation, reg
3163 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3164 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3165 !strconcat(OpcodeStr,
3166 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3167 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3169 // Vector intrinsic operation, mem
3170 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3171 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3172 !strconcat(OpcodeStr,
3173 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3175 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3176 EVEX_CD8<32, VForm>;
3177 } // ExeDomain = SSEPackedSingle
3179 let ExeDomain = SSEPackedDouble in {
3180 // Vector intrinsic operation, reg
3181 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3182 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3183 !strconcat(OpcodeStr,
3184 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3185 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3187 // Vector intrinsic operation, mem
3188 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3189 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3190 !strconcat(OpcodeStr,
3191 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3193 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3194 EVEX_CD8<64, VForm>;
3195 } // ExeDomain = SSEPackedDouble
3198 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3202 let ExeDomain = GenericDomain in {
3204 let hasSideEffects = 0 in
3205 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3206 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3207 !strconcat(OpcodeStr,
3208 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3211 // Intrinsic operation, reg.
3212 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3213 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3214 !strconcat(OpcodeStr,
3215 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3216 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3218 // Intrinsic operation, mem.
3219 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3220 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3221 !strconcat(OpcodeStr,
3222 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3223 [(set VR128X:$dst, (F32Int VR128X:$src1,
3224 sse_load_f32:$src2, imm:$src3))]>,
3225 EVEX_CD8<32, CD8VT1>;
3228 let hasSideEffects = 0 in
3229 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3230 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3231 !strconcat(OpcodeStr,
3232 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3235 // Intrinsic operation, reg.
3236 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3237 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3238 !strconcat(OpcodeStr,
3239 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3240 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3243 // Intrinsic operation, mem.
3244 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3245 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3246 !strconcat(OpcodeStr,
3247 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3249 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3250 VEX_W, EVEX_CD8<64, CD8VT1>;
3251 } // ExeDomain = GenericDomain
3254 let Predicates = [HasAVX512] in {
3255 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3256 int_x86_avx512_rndscale_ss,
3257 int_x86_avx512_rndscale_sd>, EVEX_4V;
3259 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3260 memopv16f32, memopv8f64,
3261 int_x86_avx512_rndscale_ps_512,
3262 int_x86_avx512_rndscale_pd_512, CD8VF>,
3266 def : Pat<(ffloor FR32X:$src),
3267 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3268 def : Pat<(f64 (ffloor FR64X:$src)),
3269 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3270 def : Pat<(f32 (fnearbyint FR32X:$src)),
3271 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3272 def : Pat<(f64 (fnearbyint FR64X:$src)),
3273 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3274 def : Pat<(f32 (fceil FR32X:$src)),
3275 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3276 def : Pat<(f64 (fceil FR64X:$src)),
3277 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3278 def : Pat<(f32 (frint FR32X:$src)),
3279 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3280 def : Pat<(f64 (frint FR64X:$src)),
3281 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3282 def : Pat<(f32 (ftrunc FR32X:$src)),
3283 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3284 def : Pat<(f64 (ftrunc FR64X:$src)),
3285 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3287 def : Pat<(v16f32 (ffloor VR512:$src)),
3288 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3289 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3290 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3291 def : Pat<(v16f32 (fceil VR512:$src)),
3292 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3293 def : Pat<(v16f32 (frint VR512:$src)),
3294 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3295 def : Pat<(v16f32 (ftrunc VR512:$src)),
3296 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3298 def : Pat<(v8f64 (ffloor VR512:$src)),
3299 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3300 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3301 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3302 def : Pat<(v8f64 (fceil VR512:$src)),
3303 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3304 def : Pat<(v8f64 (frint VR512:$src)),
3305 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3306 def : Pat<(v8f64 (ftrunc VR512:$src)),
3307 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3309 //-------------------------------------------------
3310 // Integer truncate and extend operations
3311 //-------------------------------------------------
3313 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3314 RegisterClass dstRC, RegisterClass srcRC,
3315 RegisterClass KRC, X86MemOperand x86memop> {
3316 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3318 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3321 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3322 (ins KRC:$mask, srcRC:$src),
3323 !strconcat(OpcodeStr,
3324 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3327 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3328 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3331 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3332 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3333 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3334 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3335 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3336 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3337 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3338 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3339 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3340 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3341 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3342 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3343 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3344 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3345 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3346 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3347 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3348 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3349 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3350 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3351 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3352 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3353 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3354 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3355 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3356 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3357 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3358 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3359 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3360 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3362 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3363 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3364 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3365 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3366 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3368 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3369 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3370 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3371 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3372 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3373 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3374 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3375 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3378 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3379 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3380 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3382 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3384 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3385 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3386 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3387 (ins x86memop:$src),
3388 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3390 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3394 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3395 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3397 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3398 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3400 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3401 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3402 EVEX_CD8<16, CD8VH>;
3403 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3404 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3405 EVEX_CD8<16, CD8VQ>;
3406 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3407 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3408 EVEX_CD8<32, CD8VH>;
3410 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3411 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3413 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3414 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3416 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3417 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3418 EVEX_CD8<16, CD8VH>;
3419 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3420 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3421 EVEX_CD8<16, CD8VQ>;
3422 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3423 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3424 EVEX_CD8<32, CD8VH>;
3426 //===----------------------------------------------------------------------===//
3427 // GATHER - SCATTER Operations
3429 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3430 RegisterClass RC, X86MemOperand memop> {
3432 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3433 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3434 (ins RC:$src1, KRC:$mask, memop:$src2),
3435 !strconcat(OpcodeStr,
3436 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3439 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3440 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3441 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3442 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3444 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3445 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3446 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3447 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3449 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3450 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3451 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3452 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3454 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3455 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3456 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3457 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3459 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3460 RegisterClass RC, X86MemOperand memop> {
3461 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3462 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3463 (ins memop:$dst, KRC:$mask, RC:$src2),
3464 !strconcat(OpcodeStr,
3465 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3469 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3470 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3471 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3472 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3474 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3475 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3476 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3477 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3479 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3480 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3481 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3482 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3484 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3485 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3486 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3487 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3489 //===----------------------------------------------------------------------===//
3490 // VSHUFPS - VSHUFPD Operations
3492 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3493 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3495 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3496 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3497 !strconcat(OpcodeStr,
3498 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3499 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3500 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3501 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3502 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3503 (ins RC:$src1, RC:$src2, i8imm:$src3),
3504 !strconcat(OpcodeStr,
3505 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3506 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3507 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3508 EVEX_4V, Sched<[WriteShuffle]>;
3511 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3512 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3513 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3514 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3516 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3517 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3518 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3519 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3520 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3522 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3523 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3524 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3525 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3526 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3528 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3529 X86MemOperand x86memop> {
3530 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3531 (ins RC:$src1, RC:$src2, i8imm:$src3),
3532 !strconcat(OpcodeStr,
3533 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3536 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3537 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3538 !strconcat(OpcodeStr,
3539 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3542 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3543 EVEX_V512, EVEX_CD8<32, CD8VF>;
3544 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3545 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3547 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3548 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3549 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3550 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3551 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3552 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3553 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3554 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3556 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3557 X86MemOperand x86memop> {
3558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3559 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3561 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3562 (ins x86memop:$src),
3563 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3567 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3568 EVEX_CD8<32, CD8VF>;
3569 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3570 EVEX_CD8<64, CD8VF>;
3572 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3573 RegisterClass RC, RegisterClass KRC,
3574 X86MemOperand x86memop,
3575 X86MemOperand x86scalar_mop, string BrdcstStr> {
3576 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3578 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3580 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3581 (ins x86memop:$src),
3582 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3584 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3585 (ins x86scalar_mop:$src),
3586 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3587 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3589 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3590 (ins KRC:$mask, RC:$src),
3591 !strconcat(OpcodeStr,
3592 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3594 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3595 (ins KRC:$mask, x86memop:$src),
3596 !strconcat(OpcodeStr,
3597 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3599 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3600 (ins KRC:$mask, x86scalar_mop:$src),
3601 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3602 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3604 []>, EVEX, EVEX_KZ, EVEX_B;
3606 let Constraints = "$src1 = $dst" in {
3607 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3608 (ins RC:$src1, KRC:$mask, RC:$src2),
3609 !strconcat(OpcodeStr,
3610 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3612 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3613 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3614 !strconcat(OpcodeStr,
3615 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3617 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3618 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3619 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3620 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3621 []>, EVEX, EVEX_K, EVEX_B;
3625 let Predicates = [HasCDI] in {
3626 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3627 i512mem, i32mem, "{1to16}">,
3628 EVEX_V512, EVEX_CD8<32, CD8VF>;
3631 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3632 i512mem, i64mem, "{1to8}">,
3633 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3637 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3639 (VPCONFLICTDrrk VR512:$src1,
3640 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3642 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3644 (VPCONFLICTQrrk VR512:$src1,
3645 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;