1 //===-- X86InstrArithmetic.td - Integer Arithmetic Instrs --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the integer arithmetic instructions in the X86
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // LEA - Load Effective Address
18 let neverHasSideEffects = 1 in
19 def LEA16r : I<0x8D, MRMSrcMem,
20 (outs GR16:$dst), (ins i32mem:$src),
21 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize;
22 let isReMaterializable = 1 in
23 def LEA32r : I<0x8D, MRMSrcMem,
24 (outs GR32:$dst), (ins i32mem:$src),
25 "lea{l}\t{$src|$dst}, {$dst|$src}",
26 [(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
27 Requires<[In32BitMode]>;
29 def LEA64_32r : I<0x8D, MRMSrcMem,
30 (outs GR32:$dst), (ins lea64_32mem:$src),
31 "lea{l}\t{$src|$dst}, {$dst|$src}",
32 [(set GR32:$dst, lea64_32addr:$src)], IIC_LEA>,
33 Requires<[In64BitMode]>;
35 let isReMaterializable = 1 in
36 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
37 "lea{q}\t{$src|$dst}, {$dst|$src}",
38 [(set GR64:$dst, lea64addr:$src)], IIC_LEA>;
42 //===----------------------------------------------------------------------===//
43 // Fixed-Register Multiplication and Division Instructions.
46 // Extra precision multiplication
48 // AL is really implied by AX, but the registers in Defs must match the
49 // SDNode results (i8, i32).
50 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
51 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
52 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
53 // This probably ought to be moved to a def : Pat<> if the
54 // syntax can be accepted.
55 [(set AL, (mul AL, GR8:$src)),
56 (implicit EFLAGS)], IIC_MUL8>; // AL,AH = AL*GR8
58 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
59 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
61 [], IIC_MUL16_REG>, OpSize; // AX,DX = AX*GR16
63 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
64 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
65 "mul{l}\t$src", // EAX,EDX = EAX*GR32
66 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
68 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
69 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
70 "mul{q}\t$src", // RAX,RDX = RAX*GR64
71 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
74 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
75 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
77 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
78 // This probably ought to be moved to a def : Pat<> if the
79 // syntax can be accepted.
80 [(set AL, (mul AL, (loadi8 addr:$src))),
81 (implicit EFLAGS)], IIC_MUL8>; // AL,AH = AL*[mem8]
83 let mayLoad = 1, neverHasSideEffects = 1 in {
84 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
85 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
87 [], IIC_MUL16_MEM>, OpSize; // AX,DX = AX*[mem16]
89 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
90 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
92 [], IIC_MUL32_MEM>; // EAX,EDX = EAX*[mem32]
93 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
94 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
95 "mul{q}\t$src", [], IIC_MUL64>; // RAX,RDX = RAX*[mem64]
98 let neverHasSideEffects = 1 in {
99 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
100 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
101 IIC_IMUL8>; // AL,AH = AL*GR8
102 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
103 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
104 IIC_IMUL16_RR>, OpSize; // AX,DX = AX*GR16
105 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
106 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
107 IIC_IMUL32_RR>; // EAX,EDX = EAX*GR32
108 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
109 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
110 IIC_IMUL64_RR>; // RAX,RDX = RAX*GR64
113 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
114 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
115 "imul{b}\t$src", [], IIC_IMUL8>; // AL,AH = AL*[mem8]
116 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
117 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
118 "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize;
119 // AX,DX = AX*[mem16]
120 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
121 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
122 "imul{l}\t$src", [], IIC_IMUL32_MEM>; // EAX,EDX = EAX*[mem32]
123 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
124 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
125 "imul{q}\t$src", [], IIC_IMUL64>; // RAX,RDX = RAX*[mem64]
127 } // neverHasSideEffects
130 let Defs = [EFLAGS] in {
131 let Constraints = "$src1 = $dst" in {
133 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
134 // Register-Register Signed Integer Multiply
135 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
136 "imul{w}\t{$src2, $dst|$dst, $src2}",
137 [(set GR16:$dst, EFLAGS,
138 (X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>,
140 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
141 "imul{l}\t{$src2, $dst|$dst, $src2}",
142 [(set GR32:$dst, EFLAGS,
143 (X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,
145 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
146 (ins GR64:$src1, GR64:$src2),
147 "imul{q}\t{$src2, $dst|$dst, $src2}",
148 [(set GR64:$dst, EFLAGS,
149 (X86smul_flag GR64:$src1, GR64:$src2))], IIC_IMUL64_RR>,
153 // Register-Memory Signed Integer Multiply
154 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
155 (ins GR16:$src1, i16mem:$src2),
156 "imul{w}\t{$src2, $dst|$dst, $src2}",
157 [(set GR16:$dst, EFLAGS,
158 (X86smul_flag GR16:$src1, (load addr:$src2)))],
161 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
162 (ins GR32:$src1, i32mem:$src2),
163 "imul{l}\t{$src2, $dst|$dst, $src2}",
164 [(set GR32:$dst, EFLAGS,
165 (X86smul_flag GR32:$src1, (load addr:$src2)))],
168 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
169 (ins GR64:$src1, i64mem:$src2),
170 "imul{q}\t{$src2, $dst|$dst, $src2}",
171 [(set GR64:$dst, EFLAGS,
172 (X86smul_flag GR64:$src1, (load addr:$src2)))],
175 } // Constraints = "$src1 = $dst"
179 // Surprisingly enough, these are not two address instructions!
180 let Defs = [EFLAGS] in {
181 // Register-Integer Signed Integer Multiply
182 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
183 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
184 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
185 [(set GR16:$dst, EFLAGS,
186 (X86smul_flag GR16:$src1, imm:$src2))],
187 IIC_IMUL16_RRI>, OpSize;
188 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
189 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
190 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
191 [(set GR16:$dst, EFLAGS,
192 (X86smul_flag GR16:$src1, i16immSExt8:$src2))],
195 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
196 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
197 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
198 [(set GR32:$dst, EFLAGS,
199 (X86smul_flag GR32:$src1, imm:$src2))],
201 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
202 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
203 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
204 [(set GR32:$dst, EFLAGS,
205 (X86smul_flag GR32:$src1, i32immSExt8:$src2))],
207 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
208 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
209 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
210 [(set GR64:$dst, EFLAGS,
211 (X86smul_flag GR64:$src1, i64immSExt32:$src2))],
213 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
214 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
215 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
216 [(set GR64:$dst, EFLAGS,
217 (X86smul_flag GR64:$src1, i64immSExt8:$src2))],
221 // Memory-Integer Signed Integer Multiply
222 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
223 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
224 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
225 [(set GR16:$dst, EFLAGS,
226 (X86smul_flag (load addr:$src1), imm:$src2))],
229 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
230 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
231 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 [(set GR16:$dst, EFLAGS,
233 (X86smul_flag (load addr:$src1),
234 i16immSExt8:$src2))], IIC_IMUL16_RMI>,
236 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
237 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
238 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 [(set GR32:$dst, EFLAGS,
240 (X86smul_flag (load addr:$src1), imm:$src2))],
242 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
243 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
244 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
245 [(set GR32:$dst, EFLAGS,
246 (X86smul_flag (load addr:$src1),
247 i32immSExt8:$src2))],
249 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
250 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
251 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 [(set GR64:$dst, EFLAGS,
253 (X86smul_flag (load addr:$src1),
254 i64immSExt32:$src2))],
256 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
257 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
258 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
259 [(set GR64:$dst, EFLAGS,
260 (X86smul_flag (load addr:$src1),
261 i64immSExt8:$src2))],
268 // unsigned division/remainder
269 let hasSideEffects = 1 in { // so that we don't speculatively execute
270 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
271 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
272 "div{b}\t$src", [], IIC_DIV8_REG>;
273 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
274 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
275 "div{w}\t$src", [], IIC_DIV16>, OpSize;
276 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
277 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
278 "div{l}\t$src", [], IIC_DIV32>;
279 // RDX:RAX/r64 = RAX,RDX
280 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
281 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
282 "div{q}\t$src", [], IIC_DIV64>;
285 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
286 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
287 "div{b}\t$src", [], IIC_DIV8_MEM>;
288 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
289 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
290 "div{w}\t$src", [], IIC_DIV16>, OpSize;
291 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
292 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
293 "div{l}\t$src", [], IIC_DIV32>;
294 // RDX:RAX/[mem64] = RAX,RDX
295 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
296 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
297 "div{q}\t$src", [], IIC_DIV64>;
300 // Signed division/remainder.
301 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
302 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
303 "idiv{b}\t$src", [], IIC_IDIV8>;
304 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
305 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
306 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
307 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
308 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
309 "idiv{l}\t$src", [], IIC_IDIV32>;
310 // RDX:RAX/r64 = RAX,RDX
311 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
312 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
313 "idiv{q}\t$src", [], IIC_IDIV64>;
316 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
317 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
318 "idiv{b}\t$src", [], IIC_IDIV8>;
319 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
320 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
321 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
322 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
323 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
324 "idiv{l}\t$src", [], IIC_IDIV32>;
325 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
326 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
327 "idiv{q}\t$src", [], IIC_IDIV64>;
329 } // hasSideEffects = 0
331 //===----------------------------------------------------------------------===//
332 // Two address Instructions.
335 // unary instructions
336 let CodeSize = 2 in {
337 let Defs = [EFLAGS] in {
338 let Constraints = "$src1 = $dst" in {
339 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
341 [(set GR8:$dst, (ineg GR8:$src1)),
342 (implicit EFLAGS)], IIC_UNARY_REG>;
343 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
345 [(set GR16:$dst, (ineg GR16:$src1)),
346 (implicit EFLAGS)], IIC_UNARY_REG>, OpSize;
347 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
349 [(set GR32:$dst, (ineg GR32:$src1)),
350 (implicit EFLAGS)], IIC_UNARY_REG>;
351 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
352 [(set GR64:$dst, (ineg GR64:$src1)),
353 (implicit EFLAGS)], IIC_UNARY_REG>;
354 } // Constraints = "$src1 = $dst"
356 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
358 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
359 (implicit EFLAGS)], IIC_UNARY_MEM>;
360 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
362 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
363 (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize;
364 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
366 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
367 (implicit EFLAGS)], IIC_UNARY_MEM>;
368 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
369 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
370 (implicit EFLAGS)], IIC_UNARY_MEM>;
374 // Note: NOT does not set EFLAGS!
376 let Constraints = "$src1 = $dst" in {
377 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
378 let AddedComplexity = 15 in {
379 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
381 [(set GR8:$dst, (not GR8:$src1))], IIC_UNARY_REG>;
382 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
384 [(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize;
385 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
387 [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>;
388 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
389 [(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>;
391 } // Constraints = "$src1 = $dst"
393 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
395 [(store (not (loadi8 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
396 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
398 [(store (not (loadi16 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
400 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
402 [(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
403 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
404 [(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
407 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
408 let Defs = [EFLAGS] in {
409 let Constraints = "$src1 = $dst" in {
411 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
413 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))],
416 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
417 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
419 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], IIC_UNARY_REG>,
420 OpSize, Requires<[In32BitMode]>;
421 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
423 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
425 Requires<[In32BitMode]>;
426 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
427 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
429 } // isConvertibleToThreeAddress = 1, CodeSize = 1
432 // In 64-bit mode, single byte INC and DEC cannot be encoded.
433 let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
434 // Can transform into LEA.
435 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
437 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))],
439 OpSize, Requires<[In64BitMode]>;
440 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
442 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
444 Requires<[In64BitMode]>;
445 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
447 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
449 OpSize, Requires<[In64BitMode]>;
450 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
452 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
454 Requires<[In64BitMode]>;
455 } // isConvertibleToThreeAddress = 1, CodeSize = 2
457 } // Constraints = "$src1 = $dst"
459 let CodeSize = 2 in {
460 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
461 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
462 (implicit EFLAGS)], IIC_UNARY_MEM>;
463 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
464 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
465 (implicit EFLAGS)], IIC_UNARY_MEM>,
466 OpSize, Requires<[In32BitMode]>;
467 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
468 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
469 (implicit EFLAGS)], IIC_UNARY_MEM>,
470 Requires<[In32BitMode]>;
471 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
472 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
473 (implicit EFLAGS)], IIC_UNARY_MEM>;
475 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
476 // how to unfold them.
477 // FIXME: What is this for??
478 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
479 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
480 (implicit EFLAGS)], IIC_UNARY_MEM>,
481 OpSize, Requires<[In64BitMode]>;
482 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
483 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
484 (implicit EFLAGS)], IIC_UNARY_MEM>,
485 Requires<[In64BitMode]>;
486 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
487 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
488 (implicit EFLAGS)], IIC_UNARY_MEM>,
489 OpSize, Requires<[In64BitMode]>;
490 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
491 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
492 (implicit EFLAGS)], IIC_UNARY_MEM>,
493 Requires<[In64BitMode]>;
496 let Constraints = "$src1 = $dst" in {
498 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
500 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))],
502 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
503 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
505 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
507 OpSize, Requires<[In32BitMode]>;
508 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
510 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
512 Requires<[In32BitMode]>;
513 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
514 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
517 } // Constraints = "$src1 = $dst"
520 let CodeSize = 2 in {
521 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
522 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
523 (implicit EFLAGS)], IIC_UNARY_MEM>;
524 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
525 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
526 (implicit EFLAGS)], IIC_UNARY_MEM>,
527 OpSize, Requires<[In32BitMode]>;
528 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
529 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
530 (implicit EFLAGS)], IIC_UNARY_MEM>,
531 Requires<[In32BitMode]>;
532 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
533 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
534 (implicit EFLAGS)], IIC_UNARY_MEM>;
539 /// X86TypeInfo - This is a bunch of information that describes relevant X86
540 /// information about value types. For example, it can tell you what the
541 /// register class and preferred load to use.
542 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
543 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
544 Operand immoperand, SDPatternOperator immoperator,
545 Operand imm8operand, SDPatternOperator imm8operator,
546 bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {
547 /// VT - This is the value type itself.
550 /// InstrSuffix - This is the suffix used on instructions with this type. For
551 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
552 string InstrSuffix = instrsuffix;
554 /// RegClass - This is the register class associated with this type. For
555 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
556 RegisterClass RegClass = regclass;
558 /// LoadNode - This is the load node associated with this type. For
559 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
560 PatFrag LoadNode = loadnode;
562 /// MemOperand - This is the memory operand associated with this type. For
563 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
564 X86MemOperand MemOperand = memoperand;
566 /// ImmEncoding - This is the encoding of an immediate of this type. For
567 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
568 /// since the immediate fields of i64 instructions is a 32-bit sign extended
570 ImmType ImmEncoding = immkind;
572 /// ImmOperand - This is the operand kind of an immediate of this type. For
573 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
574 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
576 Operand ImmOperand = immoperand;
578 /// ImmOperator - This is the operator that should be used to match an
579 /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32).
580 SDPatternOperator ImmOperator = immoperator;
582 /// Imm8Operand - This is the operand kind to use for an imm8 of this type.
583 /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is
584 /// only used for instructions that have a sign-extended imm8 field form.
585 Operand Imm8Operand = imm8operand;
587 /// Imm8Operator - This is the operator that should be used to match an 8-bit
588 /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8).
589 SDPatternOperator Imm8Operator = imm8operator;
591 /// HasOddOpcode - This bit is true if the instruction should have an odd (as
592 /// opposed to even) opcode. Operations on i8 are usually even, operations on
593 /// other datatypes are odd.
594 bit HasOddOpcode = hasOddOpcode;
596 /// HasOpSizePrefix - This bit is set to true if the instruction should have
597 /// the 0x66 operand size prefix. This is set for i16 types.
598 bit HasOpSizePrefix = hasOpSizePrefix;
600 /// HasREX_WPrefix - This bit is set to true if the instruction should have
601 /// the 0x40 REX prefix. This is set for i64 types.
602 bit HasREX_WPrefix = hasREX_WPrefix;
605 def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
608 def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem ,
609 Imm8 , i8imm , imm, i8imm , invalid_node,
611 def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,
612 Imm16, i16imm, imm, i16i8imm, i16immSExt8,
614 def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
615 Imm32, i32imm, imm, i32i8imm, i32immSExt8,
617 def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
618 Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
621 /// ITy - This instruction base class takes the type info for the instruction.
623 /// 1. Concatenates together the instruction mnemonic with the appropriate
624 /// suffix letter, a tab, and the arguments.
625 /// 2. Infers whether the instruction should have a 0x66 prefix byte.
626 /// 3. Infers whether the instruction should have a 0x40 REX_W prefix.
627 /// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
628 /// or 1 (for i16,i32,i64 operations).
629 class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
630 string mnemonic, string args, list<dag> pattern,
631 InstrItinClass itin = IIC_BIN_NONMEM>
632 : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
633 opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
635 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern,
638 // Infer instruction prefixes from type info.
639 let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
640 let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
643 // BinOpRR - Instructions like "add reg, reg, reg".
644 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
645 dag outlist, list<dag> pattern, InstrItinClass itin,
646 Format f = MRMDestReg>
647 : ITy<opcode, f, typeinfo, outlist,
648 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
649 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>;
651 // BinOpRR_R - Instructions like "add reg, reg, reg", where the pattern has
652 // just a regclass (no eflags) as a result.
653 class BinOpRR_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
655 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
656 [(set typeinfo.RegClass:$dst,
657 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
660 // BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
661 // just a EFLAGS as a result.
662 class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
663 SDPatternOperator opnode, Format f = MRMDestReg>
664 : BinOpRR<opcode, mnemonic, typeinfo, (outs),
666 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
669 // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
670 // both a regclass and EFLAGS as a result.
671 class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
673 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
674 [(set typeinfo.RegClass:$dst, EFLAGS,
675 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
678 // BinOpRR_RFF - Instructions like "adc reg, reg, reg", where the pattern has
679 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
680 class BinOpRR_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
682 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
683 [(set typeinfo.RegClass:$dst, EFLAGS,
684 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
685 EFLAGS))], IIC_BIN_NONMEM>;
687 // BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding).
688 class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
689 : ITy<opcode, MRMSrcReg, typeinfo,
690 (outs typeinfo.RegClass:$dst),
691 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
692 mnemonic, "{$src2, $dst|$dst, $src2}", [], IIC_BIN_NONMEM> {
693 // The disassembler should know about this, but not the asmparser.
694 let isCodeGenOnly = 1;
695 let hasSideEffects = 0;
698 // BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding).
699 class BinOpRR_F_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
700 : ITy<opcode, MRMSrcReg, typeinfo, (outs),
701 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
702 mnemonic, "{$src2, $src1|$src1, $src2}", [], IIC_BIN_NONMEM> {
703 // The disassembler should know about this, but not the asmparser.
704 let isCodeGenOnly = 1;
705 let hasSideEffects = 0;
708 // BinOpRM - Instructions like "add reg, reg, [mem]".
709 class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
710 dag outlist, list<dag> pattern>
711 : ITy<opcode, MRMSrcMem, typeinfo, outlist,
712 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
713 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_NONMEM>;
715 // BinOpRM_R - Instructions like "add reg, reg, [mem]".
716 class BinOpRM_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
718 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
719 [(set typeinfo.RegClass:$dst,
720 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
722 // BinOpRM_F - Instructions like "cmp reg, [mem]".
723 class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
724 SDPatternOperator opnode>
725 : BinOpRM<opcode, mnemonic, typeinfo, (outs),
727 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
729 // BinOpRM_RF - Instructions like "add reg, reg, [mem]".
730 class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
732 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
733 [(set typeinfo.RegClass:$dst, EFLAGS,
734 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
736 // BinOpRM_RFF - Instructions like "adc reg, reg, [mem]".
737 class BinOpRM_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
739 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
740 [(set typeinfo.RegClass:$dst, EFLAGS,
741 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2),
744 // BinOpRI - Instructions like "add reg, reg, imm".
745 class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
746 Format f, dag outlist, list<dag> pattern>
747 : ITy<opcode, f, typeinfo, outlist,
748 (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
749 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_NONMEM> {
750 let ImmT = typeinfo.ImmEncoding;
753 // BinOpRI_R - Instructions like "add reg, reg, imm".
754 class BinOpRI_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
755 SDNode opnode, Format f>
756 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
757 [(set typeinfo.RegClass:$dst,
758 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
760 // BinOpRI_F - Instructions like "cmp reg, imm".
761 class BinOpRI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
762 SDPatternOperator opnode, Format f>
763 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs),
765 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
767 // BinOpRI_RF - Instructions like "add reg, reg, imm".
768 class BinOpRI_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
769 SDNode opnode, Format f>
770 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
771 [(set typeinfo.RegClass:$dst, EFLAGS,
772 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
773 // BinOpRI_RFF - Instructions like "adc reg, reg, imm".
774 class BinOpRI_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
775 SDNode opnode, Format f>
776 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
777 [(set typeinfo.RegClass:$dst, EFLAGS,
778 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2,
781 // BinOpRI8 - Instructions like "add reg, reg, imm8".
782 class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
783 Format f, dag outlist, list<dag> pattern>
784 : ITy<opcode, f, typeinfo, outlist,
785 (ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
786 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_NONMEM> {
787 let ImmT = Imm8; // Always 8-bit immediate.
790 // BinOpRI8_R - Instructions like "add reg, reg, imm8".
791 class BinOpRI8_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
792 SDNode opnode, Format f>
793 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
794 [(set typeinfo.RegClass:$dst,
795 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
797 // BinOpRI8_F - Instructions like "cmp reg, imm8".
798 class BinOpRI8_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
799 SDNode opnode, Format f>
800 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs),
802 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
804 // BinOpRI8_RF - Instructions like "add reg, reg, imm8".
805 class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
806 SDNode opnode, Format f>
807 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
808 [(set typeinfo.RegClass:$dst, EFLAGS,
809 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
811 // BinOpRI8_RFF - Instructions like "adc reg, reg, imm8".
812 class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
813 SDNode opnode, Format f>
814 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
815 [(set typeinfo.RegClass:$dst, EFLAGS,
816 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2,
819 // BinOpMR - Instructions like "add [mem], reg".
820 class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
822 : ITy<opcode, MRMDestMem, typeinfo,
823 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src),
824 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM>;
826 // BinOpMR_RMW - Instructions like "add [mem], reg".
827 class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
829 : BinOpMR<opcode, mnemonic, typeinfo,
830 [(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
833 // BinOpMR_RMW_FF - Instructions like "adc [mem], reg".
834 class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
836 : BinOpMR<opcode, mnemonic, typeinfo,
837 [(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS),
841 // BinOpMR_F - Instructions like "cmp [mem], reg".
842 class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
844 : BinOpMR<opcode, mnemonic, typeinfo,
845 [(set EFLAGS, (opnode (load addr:$dst), typeinfo.RegClass:$src))]>;
847 // BinOpMI - Instructions like "add [mem], imm".
848 class BinOpMI<string mnemonic, X86TypeInfo typeinfo,
849 Format f, list<dag> pattern, bits<8> opcode = 0x80>
850 : ITy<opcode, f, typeinfo,
851 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src),
852 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM> {
853 let ImmT = typeinfo.ImmEncoding;
856 // BinOpMI_RMW - Instructions like "add [mem], imm".
857 class BinOpMI_RMW<string mnemonic, X86TypeInfo typeinfo,
858 SDNode opnode, Format f>
859 : BinOpMI<mnemonic, typeinfo, f,
860 [(store (opnode (typeinfo.VT (load addr:$dst)),
861 typeinfo.ImmOperator:$src), addr:$dst),
863 // BinOpMI_RMW_FF - Instructions like "adc [mem], imm".
864 class BinOpMI_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
865 SDNode opnode, Format f>
866 : BinOpMI<mnemonic, typeinfo, f,
867 [(store (opnode (typeinfo.VT (load addr:$dst)),
868 typeinfo.ImmOperator:$src, EFLAGS), addr:$dst),
871 // BinOpMI_F - Instructions like "cmp [mem], imm".
872 class BinOpMI_F<string mnemonic, X86TypeInfo typeinfo,
873 SDPatternOperator opnode, Format f, bits<8> opcode = 0x80>
874 : BinOpMI<mnemonic, typeinfo, f,
875 [(set EFLAGS, (opnode (typeinfo.VT (load addr:$dst)),
876 typeinfo.ImmOperator:$src))],
879 // BinOpMI8 - Instructions like "add [mem], imm8".
880 class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
881 Format f, list<dag> pattern>
882 : ITy<0x82, f, typeinfo,
883 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src),
884 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM> {
885 let ImmT = Imm8; // Always 8-bit immediate.
888 // BinOpMI8_RMW - Instructions like "add [mem], imm8".
889 class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
890 SDNode opnode, Format f>
891 : BinOpMI8<mnemonic, typeinfo, f,
892 [(store (opnode (load addr:$dst),
893 typeinfo.Imm8Operator:$src), addr:$dst),
896 // BinOpMI8_RMW_FF - Instructions like "adc [mem], imm8".
897 class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
898 SDNode opnode, Format f>
899 : BinOpMI8<mnemonic, typeinfo, f,
900 [(store (opnode (load addr:$dst),
901 typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst),
904 // BinOpMI8_F - Instructions like "cmp [mem], imm8".
905 class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
906 SDNode opnode, Format f>
907 : BinOpMI8<mnemonic, typeinfo, f,
908 [(set EFLAGS, (opnode (load addr:$dst),
909 typeinfo.Imm8Operator:$src))]>;
911 // BinOpAI - Instructions like "add %eax, %eax, imm".
912 class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
913 Register areg, string operands>
914 : ITy<opcode, RawFrm, typeinfo,
915 (outs), (ins typeinfo.ImmOperand:$src),
916 mnemonic, operands, []> {
917 let ImmT = typeinfo.ImmEncoding;
920 let hasSideEffects = 0;
923 /// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is
924 /// defined with "(set GPR:$dst, EFLAGS, (...".
926 /// It would be nice to get rid of the second and third argument here, but
927 /// tblgen can't handle dependent type references aggressively enough: PR8330
928 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
929 string mnemonic, Format RegMRM, Format MemMRM,
930 SDNode opnodeflag, SDNode opnode,
931 bit CommutableRR, bit ConvertibleToThreeAddress> {
932 let Defs = [EFLAGS] in {
933 let Constraints = "$src1 = $dst" in {
934 let isCommutable = CommutableRR,
935 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
936 def NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
937 def NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
938 def NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
939 def NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
942 def NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
943 def NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
944 def NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
945 def NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
947 def NAME#8rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi8 , opnodeflag>;
948 def NAME#16rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi16, opnodeflag>;
949 def NAME#32rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, opnodeflag>;
950 def NAME#64rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>;
952 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
953 // NOTE: These are order specific, we want the ri8 forms to be listed
954 // first so that they are slightly preferred to the ri forms.
955 def NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>;
956 def NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
957 def NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
959 def NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
960 def NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
961 def NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
962 def NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
964 } // Constraints = "$src1 = $dst"
966 def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
967 def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
968 def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
969 def NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
971 // NOTE: These are order specific, we want the mi8 forms to be listed
972 // first so that they are slightly preferred to the mi forms.
973 def NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
974 def NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
975 def NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
977 def NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>;
978 def NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>;
979 def NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
980 def NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
982 def NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
983 "{$src, %al|AL, $src}">;
984 def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
985 "{$src, %ax|AX, $src}">;
986 def NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
987 "{$src, %eax|EAX, $src}">;
988 def NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
989 "{$src, %rax|RAX, $src}">;
993 /// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is
994 /// defined with "(set GPR:$dst, EFLAGS, (node LHS, RHS, EFLAGS))" like ADC and
997 /// It would be nice to get rid of the second and third argument here, but
998 /// tblgen can't handle dependent type references aggressively enough: PR8330
999 multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
1000 string mnemonic, Format RegMRM, Format MemMRM,
1001 SDNode opnode, bit CommutableRR,
1002 bit ConvertibleToThreeAddress> {
1003 let Defs = [EFLAGS] in {
1004 let Constraints = "$src1 = $dst" in {
1005 let isCommutable = CommutableRR,
1006 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
1007 def NAME#8rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi8 , opnode>;
1008 def NAME#16rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi16, opnode>;
1009 def NAME#32rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi32, opnode>;
1010 def NAME#64rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi64, opnode>;
1013 def NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
1014 def NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
1015 def NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
1016 def NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
1018 def NAME#8rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi8 , opnode>;
1019 def NAME#16rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi16, opnode>;
1020 def NAME#32rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi32, opnode>;
1021 def NAME#64rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi64, opnode>;
1023 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
1024 // NOTE: These are order specific, we want the ri8 forms to be listed
1025 // first so that they are slightly preferred to the ri forms.
1026 def NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>;
1027 def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>;
1028 def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>;
1030 def NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>;
1031 def NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>;
1032 def NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>;
1033 def NAME#64ri32: BinOpRI_RFF<0x80, mnemonic, Xi64, opnode, RegMRM>;
1035 } // Constraints = "$src1 = $dst"
1037 def NAME#8mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi8 , opnode>;
1038 def NAME#16mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi16, opnode>;
1039 def NAME#32mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi32, opnode>;
1040 def NAME#64mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi64, opnode>;
1042 // NOTE: These are order specific, we want the mi8 forms to be listed
1043 // first so that they are slightly preferred to the mi forms.
1044 def NAME#16mi8 : BinOpMI8_RMW_FF<mnemonic, Xi16, opnode, MemMRM>;
1045 def NAME#32mi8 : BinOpMI8_RMW_FF<mnemonic, Xi32, opnode, MemMRM>;
1046 def NAME#64mi8 : BinOpMI8_RMW_FF<mnemonic, Xi64, opnode, MemMRM>;
1048 def NAME#8mi : BinOpMI_RMW_FF<mnemonic, Xi8 , opnode, MemMRM>;
1049 def NAME#16mi : BinOpMI_RMW_FF<mnemonic, Xi16, opnode, MemMRM>;
1050 def NAME#32mi : BinOpMI_RMW_FF<mnemonic, Xi32, opnode, MemMRM>;
1051 def NAME#64mi32 : BinOpMI_RMW_FF<mnemonic, Xi64, opnode, MemMRM>;
1053 def NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
1054 "{$src, %al|AL, $src}">;
1055 def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
1056 "{$src, %ax|AX, $src}">;
1057 def NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
1058 "{$src, %eax|EAX, $src}">;
1059 def NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
1060 "{$src, %rax|RAX, $src}">;
1064 /// ArithBinOp_F - This is an arithmetic binary operator where the pattern is
1065 /// defined with "(set EFLAGS, (...". It would be really nice to find a way
1066 /// to factor this with the other ArithBinOp_*.
1068 multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
1069 string mnemonic, Format RegMRM, Format MemMRM,
1071 bit CommutableRR, bit ConvertibleToThreeAddress> {
1072 let Defs = [EFLAGS] in {
1073 let isCommutable = CommutableRR,
1074 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
1075 def NAME#8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>;
1076 def NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>;
1077 def NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>;
1078 def NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
1081 def NAME#8rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>;
1082 def NAME#16rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi16>;
1083 def NAME#32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>;
1084 def NAME#64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>;
1086 def NAME#8rm : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>;
1087 def NAME#16rm : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>;
1088 def NAME#32rm : BinOpRM_F<BaseOpc2, mnemonic, Xi32, opnode>;
1089 def NAME#64rm : BinOpRM_F<BaseOpc2, mnemonic, Xi64, opnode>;
1091 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
1092 // NOTE: These are order specific, we want the ri8 forms to be listed
1093 // first so that they are slightly preferred to the ri forms.
1094 def NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>;
1095 def NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>;
1096 def NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>;
1098 def NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>;
1099 def NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>;
1100 def NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>;
1101 def NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>;
1104 def NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>;
1105 def NAME#16mr : BinOpMR_F<BaseOpc, mnemonic, Xi16, opnode>;
1106 def NAME#32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>;
1107 def NAME#64mr : BinOpMR_F<BaseOpc, mnemonic, Xi64, opnode>;
1109 // NOTE: These are order specific, we want the mi8 forms to be listed
1110 // first so that they are slightly preferred to the mi forms.
1111 def NAME#16mi8 : BinOpMI8_F<mnemonic, Xi16, opnode, MemMRM>;
1112 def NAME#32mi8 : BinOpMI8_F<mnemonic, Xi32, opnode, MemMRM>;
1113 def NAME#64mi8 : BinOpMI8_F<mnemonic, Xi64, opnode, MemMRM>;
1115 def NAME#8mi : BinOpMI_F<mnemonic, Xi8 , opnode, MemMRM>;
1116 def NAME#16mi : BinOpMI_F<mnemonic, Xi16, opnode, MemMRM>;
1117 def NAME#32mi : BinOpMI_F<mnemonic, Xi32, opnode, MemMRM>;
1118 def NAME#64mi32 : BinOpMI_F<mnemonic, Xi64, opnode, MemMRM>;
1120 def NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
1121 "{$src, %al|AL, $src}">;
1122 def NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
1123 "{$src, %ax|AX, $src}">;
1124 def NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
1125 "{$src, %eax|EAX, $src}">;
1126 def NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
1127 "{$src, %rax|RAX, $src}">;
1132 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
1133 X86and_flag, and, 1, 0>;
1134 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
1135 X86or_flag, or, 1, 0>;
1136 defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
1137 X86xor_flag, xor, 1, 0>;
1138 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1139 X86add_flag, add, 1, 1>;
1140 let isCompare = 1 in {
1141 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
1142 X86sub_flag, sub, 0, 0>;
1146 let Uses = [EFLAGS] in {
1147 defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag,
1149 defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag,
1153 let isCompare = 1 in {
1154 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
1158 //===----------------------------------------------------------------------===//
1159 // Semantically, test instructions are similar like AND, except they don't
1160 // generate a result. From an encoding perspective, they are very different:
1161 // they don't have all the usual imm8 and REV forms, and are encoded into a
1163 def X86testpat : PatFrag<(ops node:$lhs, node:$rhs),
1164 (X86cmp (and_su node:$lhs, node:$rhs), 0)>;
1166 let isCompare = 1, Defs = [EFLAGS] in {
1167 let isCommutable = 1 in {
1168 def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>;
1169 def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>;
1170 def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>;
1171 def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>;
1174 def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
1175 def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
1176 def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
1177 def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>;
1179 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1180 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1181 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1182 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
1184 def TEST8mi : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m, 0xF6>;
1185 def TEST16mi : BinOpMI_F<"test", Xi16, X86testpat, MRM0m, 0xF6>;
1186 def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>;
1187 def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>;
1189 def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL,
1190 "{$src, %al|AL, $src}">;
1191 def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX,
1192 "{$src, %ax|AX, $src}">;
1193 def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX,
1194 "{$src, %eax|EAX, $src}">;
1195 def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX,
1196 "{$src, %rax|RAX, $src}">;
1198 // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
1199 // register class is constrained to GR8_NOREX.
1201 def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask),
1202 "", [], IIC_BIN_NONMEM>;
1205 //===----------------------------------------------------------------------===//
1208 multiclass bmi_andn<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
1210 def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1211 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1212 [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))],
1214 def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1215 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1216 [(set RC:$dst, EFLAGS,
1217 (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))], IIC_BIN_MEM>;
1220 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1221 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8, VEX_4V;
1222 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8, VEX_4V, VEX_W;
1225 let Predicates = [HasBMI] in {
1226 def : Pat<(and (not GR32:$src1), GR32:$src2),
1227 (ANDN32rr GR32:$src1, GR32:$src2)>;
1228 def : Pat<(and (not GR64:$src1), GR64:$src2),
1229 (ANDN64rr GR64:$src1, GR64:$src2)>;
1230 def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)),
1231 (ANDN32rm GR32:$src1, addr:$src2)>;
1232 def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)),
1233 (ANDN64rm GR64:$src1, addr:$src2)>;
1236 //===----------------------------------------------------------------------===//
1239 multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop> {
1240 let neverHasSideEffects = 1 in {
1241 let isCommutable = 1 in
1242 def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
1243 !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
1244 [], IIC_MUL8>, T8XD, VEX_4V;
1247 def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
1248 !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
1249 [], IIC_MUL8>, T8XD, VEX_4V;
1253 let Predicates = [HasBMI2] in {
1255 defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem>;
1257 defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem>, VEX_W;