1 //===- X86InstrArithmetic.td - Integer Arithmetic Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the integer arithmetic instructions in the X86
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // LEA - Load Effective Address
18 let neverHasSideEffects = 1 in
19 def LEA16r : I<0x8D, MRMSrcMem,
20 (outs GR16:$dst), (ins i32mem:$src),
21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
22 let isReMaterializable = 1 in
23 def LEA32r : I<0x8D, MRMSrcMem,
24 (outs GR32:$dst), (ins i32mem:$src),
25 "lea{l}\t{$src|$dst}, {$dst|$src}",
26 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
28 def LEA64_32r : I<0x8D, MRMSrcMem,
29 (outs GR32:$dst), (ins lea64_32mem:$src),
30 "lea{l}\t{$src|$dst}, {$dst|$src}",
31 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
33 let isReMaterializable = 1 in
34 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
35 "lea{q}\t{$src|$dst}, {$dst|$src}",
36 [(set GR64:$dst, lea64addr:$src)]>;
40 //===----------------------------------------------------------------------===//
41 // Fixed-Register Multiplication and Division Instructions.
44 // Extra precision multiplication
46 // AL is really implied by AX, but the registers in Defs must match the
47 // SDNode results (i8, i32).
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
49 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
50 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
51 // This probably ought to be moved to a def : Pat<> if the
52 // syntax can be accepted.
53 [(set AL, (mul AL, GR8:$src)),
54 (implicit EFLAGS)]>; // AL,AH = AL*GR8
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
57 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
59 []>, OpSize; // AX,DX = AX*GR16
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
62 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
64 []>; // EAX,EDX = EAX*GR32
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
66 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
67 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
69 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
70 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
72 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
73 // This probably ought to be moved to a def : Pat<> if the
74 // syntax can be accepted.
75 [(set AL, (mul AL, (loadi8 addr:$src))),
76 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
78 let mayLoad = 1, neverHasSideEffects = 1 in {
79 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
80 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
82 []>, OpSize; // AX,DX = AX*[mem16]
84 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
85 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
87 []>; // EAX,EDX = EAX*[mem32]
88 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
89 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
90 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
93 let neverHasSideEffects = 1 in {
94 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
95 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
97 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
98 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
99 OpSize; // AX,DX = AX*GR16
100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
101 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
102 // EAX,EDX = EAX*GR32
103 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
104 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
105 // RAX,RDX = RAX*GR64
108 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
109 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
110 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
111 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
112 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
113 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
114 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
115 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
116 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
117 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
118 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
119 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
121 } // neverHasSideEffects
124 let Defs = [EFLAGS] in {
125 let Constraints = "$src1 = $dst" in {
127 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
128 // Register-Register Signed Integer Multiply
129 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
130 "imul{w}\t{$src2, $dst|$dst, $src2}",
131 [(set GR16:$dst, EFLAGS,
132 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
133 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
134 "imul{l}\t{$src2, $dst|$dst, $src2}",
135 [(set GR32:$dst, EFLAGS,
136 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
137 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
138 (ins GR64:$src1, GR64:$src2),
139 "imul{q}\t{$src2, $dst|$dst, $src2}",
140 [(set GR64:$dst, EFLAGS,
141 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
144 // Register-Memory Signed Integer Multiply
145 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
146 (ins GR16:$src1, i16mem:$src2),
147 "imul{w}\t{$src2, $dst|$dst, $src2}",
148 [(set GR16:$dst, EFLAGS,
149 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
151 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
152 (ins GR32:$src1, i32mem:$src2),
153 "imul{l}\t{$src2, $dst|$dst, $src2}",
154 [(set GR32:$dst, EFLAGS,
155 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
156 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
157 (ins GR64:$src1, i64mem:$src2),
158 "imul{q}\t{$src2, $dst|$dst, $src2}",
159 [(set GR64:$dst, EFLAGS,
160 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
161 } // Constraints = "$src1 = $dst"
165 // Suprisingly enough, these are not two address instructions!
166 let Defs = [EFLAGS] in {
167 // Register-Integer Signed Integer Multiply
168 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
169 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
170 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
171 [(set GR16:$dst, EFLAGS,
172 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
173 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
174 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
175 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
176 [(set GR16:$dst, EFLAGS,
177 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
179 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
180 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
181 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
182 [(set GR32:$dst, EFLAGS,
183 (X86smul_flag GR32:$src1, imm:$src2))]>;
184 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
185 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
186 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
187 [(set GR32:$dst, EFLAGS,
188 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
189 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
190 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
191 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
192 [(set GR64:$dst, EFLAGS,
193 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
194 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
195 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
196 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
197 [(set GR64:$dst, EFLAGS,
198 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
201 // Memory-Integer Signed Integer Multiply
202 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
203 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
204 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
205 [(set GR16:$dst, EFLAGS,
206 (X86smul_flag (load addr:$src1), imm:$src2))]>,
208 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
209 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
210 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
211 [(set GR16:$dst, EFLAGS,
212 (X86smul_flag (load addr:$src1),
213 i16immSExt8:$src2))]>, OpSize;
214 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
215 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
216 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217 [(set GR32:$dst, EFLAGS,
218 (X86smul_flag (load addr:$src1), imm:$src2))]>;
219 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
220 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
222 [(set GR32:$dst, EFLAGS,
223 (X86smul_flag (load addr:$src1),
224 i32immSExt8:$src2))]>;
225 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
226 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
227 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 [(set GR64:$dst, EFLAGS,
229 (X86smul_flag (load addr:$src1),
230 i64immSExt32:$src2))]>;
231 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
232 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
234 [(set GR64:$dst, EFLAGS,
235 (X86smul_flag (load addr:$src1),
236 i64immSExt8:$src2))]>;
242 // unsigned division/remainder
243 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
244 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
246 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
247 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
248 "div{w}\t$src", []>, OpSize;
249 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
250 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
252 // RDX:RAX/r64 = RAX,RDX
253 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
254 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
258 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
259 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
261 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
262 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
263 "div{w}\t$src", []>, OpSize;
264 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
265 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
267 // RDX:RAX/[mem64] = RAX,RDX
268 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
269 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
273 // Signed division/remainder.
274 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
275 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
276 "idiv{b}\t$src", []>;
277 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
278 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
279 "idiv{w}\t$src", []>, OpSize;
280 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
281 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
282 "idiv{l}\t$src", []>;
283 // RDX:RAX/r64 = RAX,RDX
284 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
285 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
286 "idiv{q}\t$src", []>;
288 let mayLoad = 1, mayLoad = 1 in {
289 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
290 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
291 "idiv{b}\t$src", []>;
292 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
293 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
294 "idiv{w}\t$src", []>, OpSize;
295 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
296 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
297 "idiv{l}\t$src", []>;
298 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
299 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
300 "idiv{q}\t$src", []>;
303 //===----------------------------------------------------------------------===//
304 // Two address Instructions.
307 // unary instructions
308 let CodeSize = 2 in {
309 let Defs = [EFLAGS] in {
310 let Constraints = "$src1 = $dst" in {
311 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
313 [(set GR8:$dst, (ineg GR8:$src1)),
315 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
317 [(set GR16:$dst, (ineg GR16:$src1)),
318 (implicit EFLAGS)]>, OpSize;
319 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
321 [(set GR32:$dst, (ineg GR32:$src1)),
323 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
324 [(set GR64:$dst, (ineg GR64:$src1)),
326 } // Constraints = "$src1 = $dst"
328 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
330 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
332 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
334 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
335 (implicit EFLAGS)]>, OpSize;
336 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
338 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
340 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
341 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
346 // Note: NOT does not set EFLAGS!
348 let Constraints = "$src1 = $dst" in {
349 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
350 let AddedComplexity = 15 in {
351 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
353 [(set GR8:$dst, (not GR8:$src1))]>;
354 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
356 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
357 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
359 [(set GR32:$dst, (not GR32:$src1))]>;
360 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
361 [(set GR64:$dst, (not GR64:$src1))]>;
363 } // Constraints = "$src1 = $dst"
365 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
367 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
368 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
370 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
371 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
373 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
374 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
375 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
378 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
379 let Defs = [EFLAGS] in {
380 let Constraints = "$src1 = $dst" in {
382 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
384 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
386 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
387 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
389 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
390 OpSize, Requires<[In32BitMode]>;
391 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
393 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
394 Requires<[In32BitMode]>;
395 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
396 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>;
397 } // isConvertibleToThreeAddress = 1, CodeSize = 1
400 // In 64-bit mode, single byte INC and DEC cannot be encoded.
401 let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
402 // Can transform into LEA.
403 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
405 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
406 OpSize, Requires<[In64BitMode]>;
407 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
409 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
410 Requires<[In64BitMode]>;
411 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
413 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
414 OpSize, Requires<[In64BitMode]>;
415 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
417 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
418 Requires<[In64BitMode]>;
419 } // isConvertibleToThreeAddress = 1, CodeSize = 2
421 } // Constraints = "$src1 = $dst"
423 let CodeSize = 2 in {
424 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
425 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
427 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
428 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
430 OpSize, Requires<[In32BitMode]>;
431 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
432 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
434 Requires<[In32BitMode]>;
435 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
436 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
439 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
440 // how to unfold them.
441 // FIXME: What is this for??
442 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
443 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
445 OpSize, Requires<[In64BitMode]>;
446 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
447 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
449 Requires<[In64BitMode]>;
450 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
451 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
453 OpSize, Requires<[In64BitMode]>;
454 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
455 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
457 Requires<[In64BitMode]>;
460 let Constraints = "$src1 = $dst" in {
462 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
464 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
465 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
466 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
468 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
469 OpSize, Requires<[In32BitMode]>;
470 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
472 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
473 Requires<[In32BitMode]>;
474 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
475 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>;
477 } // Constraints = "$src1 = $dst"
480 let CodeSize = 2 in {
481 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
482 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
484 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
485 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
487 OpSize, Requires<[In32BitMode]>;
488 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
489 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
491 Requires<[In32BitMode]>;
492 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
493 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
498 /// X86TypeInfo - This is a bunch of information that describes relevant X86
499 /// information about value types. For example, it can tell you what the
500 /// register class and preferred load to use.
501 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
502 PatFrag loadnode, X86MemOperand memoperand> {
503 /// VT - This is the value type itself.
506 /// InstrSuffix - This is the suffix used on instructions with this type. For
507 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
508 string InstrSuffix = instrsuffix;
510 /// RegClass - This is the register class associated with this type. For
511 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
512 RegisterClass RegClass = regclass;
514 /// LoadNode - This is the load node associated with this type. For
515 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
516 PatFrag LoadNode = loadnode;
518 /// MemOperand - This is the memory operand associated with this type. For
519 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
520 X86MemOperand MemOperand = memoperand;
523 def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem>;
524 def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem>;
525 def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem>;
526 def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem>;
529 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
530 SDNode opnode, Format format>
532 (outs typeinfo.RegClass:$dst),
533 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
534 !strconcat(mnemonic, "{", typeinfo.InstrSuffix,
535 "}\t{$src2, $dst|$dst, $src2}"),
536 [(set typeinfo.RegClass:$dst, EFLAGS,
537 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
540 class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
542 : I<opcode, MRMSrcMem,
543 (outs typeinfo.RegClass:$dst),
544 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
545 !strconcat(mnemonic, "{", typeinfo.InstrSuffix,
546 "}\t{$src2, $dst|$dst, $src2}"),
547 [(set typeinfo.RegClass:$dst, EFLAGS,
548 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
551 // Logical operators.
552 let Defs = [EFLAGS] in {
553 let Constraints = "$src1 = $dst" in {
555 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
556 def AND8rr : BinOpRR<0x20, "and", Xi8 , X86and_flag, MRMDestReg>;
557 def AND16rr : BinOpRR<0x21, "and", Xi16, X86and_flag, MRMDestReg>, OpSize;
558 def AND32rr : BinOpRR<0x21, "and", Xi32, X86and_flag, MRMDestReg>;
559 def AND64rr : BinOpRR<0x21, "and", Xi64, X86and_flag, MRMDestReg>, REX_W;
563 // AND instructions with the destination register in REG and the source register
564 // in R/M. Included for the disassembler.
565 let isCodeGenOnly = 1 in {
566 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
567 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
568 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
569 (ins GR16:$src1, GR16:$src2),
570 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
571 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
572 (ins GR32:$src1, GR32:$src2),
573 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
574 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
575 (ins GR64:$src1, GR64:$src2),
576 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
579 def AND8rm : BinOpRM<0x22, "and", Xi8 , X86and_flag>;
580 def AND16rm : BinOpRM<0x23, "and", Xi16, X86and_flag>, OpSize;
581 def AND32rm : BinOpRM<0x23, "and", Xi32, X86and_flag>;
582 def AND64rm : BinOpRM<0x23, "and", Xi64, X86and_flag>, REX_W;
584 def AND8ri : Ii8<0x80, MRM4r,
585 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
586 "and{b}\t{$src2, $dst|$dst, $src2}",
587 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
589 def AND16ri : Ii16<0x81, MRM4r,
590 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
591 "and{w}\t{$src2, $dst|$dst, $src2}",
592 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
593 imm:$src2))]>, OpSize;
594 def AND32ri : Ii32<0x81, MRM4r,
595 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
596 "and{l}\t{$src2, $dst|$dst, $src2}",
597 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
599 def AND64ri32 : RIi32<0x81, MRM4r,
600 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
601 "and{q}\t{$src2, $dst|$dst, $src2}",
602 [(set GR64:$dst, EFLAGS,
603 (X86and_flag GR64:$src1, i64immSExt32:$src2))]>;
605 def AND16ri8 : Ii8<0x83, MRM4r,
606 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
607 "and{w}\t{$src2, $dst|$dst, $src2}",
608 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
609 i16immSExt8:$src2))]>,
611 def AND32ri8 : Ii8<0x83, MRM4r,
612 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
613 "and{l}\t{$src2, $dst|$dst, $src2}",
614 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
615 i32immSExt8:$src2))]>;
616 def AND64ri8 : RIi8<0x83, MRM4r,
617 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
618 "and{q}\t{$src2, $dst|$dst, $src2}",
619 [(set GR64:$dst, EFLAGS,
620 (X86and_flag GR64:$src1, i64immSExt8:$src2))]>;
621 } // Constraints = "$src1 = $dst"
623 def AND8mr : I<0x20, MRMDestMem,
624 (outs), (ins i8mem :$dst, GR8 :$src),
625 "and{b}\t{$src, $dst|$dst, $src}",
626 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
628 def AND16mr : I<0x21, MRMDestMem,
629 (outs), (ins i16mem:$dst, GR16:$src),
630 "and{w}\t{$src, $dst|$dst, $src}",
631 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
634 def AND32mr : I<0x21, MRMDestMem,
635 (outs), (ins i32mem:$dst, GR32:$src),
636 "and{l}\t{$src, $dst|$dst, $src}",
637 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
639 def AND64mr : RI<0x21, MRMDestMem,
640 (outs), (ins i64mem:$dst, GR64:$src),
641 "and{q}\t{$src, $dst|$dst, $src}",
642 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
645 def AND8mi : Ii8<0x80, MRM4m,
646 (outs), (ins i8mem :$dst, i8imm :$src),
647 "and{b}\t{$src, $dst|$dst, $src}",
648 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
650 def AND16mi : Ii16<0x81, MRM4m,
651 (outs), (ins i16mem:$dst, i16imm:$src),
652 "and{w}\t{$src, $dst|$dst, $src}",
653 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
656 def AND32mi : Ii32<0x81, MRM4m,
657 (outs), (ins i32mem:$dst, i32imm:$src),
658 "and{l}\t{$src, $dst|$dst, $src}",
659 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
661 def AND64mi32 : RIi32<0x81, MRM4m,
662 (outs), (ins i64mem:$dst, i64i32imm:$src),
663 "and{q}\t{$src, $dst|$dst, $src}",
664 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
667 def AND16mi8 : Ii8<0x83, MRM4m,
668 (outs), (ins i16mem:$dst, i16i8imm :$src),
669 "and{w}\t{$src, $dst|$dst, $src}",
670 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
673 def AND32mi8 : Ii8<0x83, MRM4m,
674 (outs), (ins i32mem:$dst, i32i8imm :$src),
675 "and{l}\t{$src, $dst|$dst, $src}",
676 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
678 def AND64mi8 : RIi8<0x83, MRM4m,
679 (outs), (ins i64mem:$dst, i64i8imm :$src),
680 "and{q}\t{$src, $dst|$dst, $src}",
681 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
684 // FIXME: Implicitly modifiers AL.
685 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
686 "and{b}\t{$src, %al|%al, $src}", []>;
687 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
688 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
689 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
690 "and{l}\t{$src, %eax|%eax, $src}", []>;
691 def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i64i32imm:$src),
692 "and{q}\t{$src, %rax|%rax, $src}", []>;
694 let Constraints = "$src1 = $dst" in {
696 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
697 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
698 (ins GR8 :$src1, GR8 :$src2),
699 "or{b}\t{$src2, $dst|$dst, $src2}",
700 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
701 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
702 (ins GR16:$src1, GR16:$src2),
703 "or{w}\t{$src2, $dst|$dst, $src2}",
704 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
706 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
707 (ins GR32:$src1, GR32:$src2),
708 "or{l}\t{$src2, $dst|$dst, $src2}",
709 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
710 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
711 (ins GR64:$src1, GR64:$src2),
712 "or{q}\t{$src2, $dst|$dst, $src2}",
713 [(set GR64:$dst, EFLAGS,
714 (X86or_flag GR64:$src1, GR64:$src2))]>;
717 // OR instructions with the destination register in REG and the source register
718 // in R/M. Included for the disassembler.
719 let isCodeGenOnly = 1 in {
720 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
721 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
722 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
723 (ins GR16:$src1, GR16:$src2),
724 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
725 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
726 (ins GR32:$src1, GR32:$src2),
727 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
728 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
729 (ins GR64:$src1, GR64:$src2),
730 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
733 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
734 (ins GR8 :$src1, i8mem :$src2),
735 "or{b}\t{$src2, $dst|$dst, $src2}",
736 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
737 (load addr:$src2)))]>;
738 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
739 (ins GR16:$src1, i16mem:$src2),
740 "or{w}\t{$src2, $dst|$dst, $src2}",
741 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
742 (load addr:$src2)))]>,
744 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
745 (ins GR32:$src1, i32mem:$src2),
746 "or{l}\t{$src2, $dst|$dst, $src2}",
747 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
748 (load addr:$src2)))]>;
749 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
750 (ins GR64:$src1, i64mem:$src2),
751 "or{q}\t{$src2, $dst|$dst, $src2}",
752 [(set GR64:$dst, EFLAGS,
753 (X86or_flag GR64:$src1, (load addr:$src2)))]>;
755 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
756 (ins GR8 :$src1, i8imm:$src2),
757 "or{b}\t{$src2, $dst|$dst, $src2}",
758 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
759 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
760 (ins GR16:$src1, i16imm:$src2),
761 "or{w}\t{$src2, $dst|$dst, $src2}",
762 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
763 imm:$src2))]>, OpSize;
764 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
765 (ins GR32:$src1, i32imm:$src2),
766 "or{l}\t{$src2, $dst|$dst, $src2}",
767 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
769 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
770 (ins GR64:$src1, i64i32imm:$src2),
771 "or{q}\t{$src2, $dst|$dst, $src2}",
772 [(set GR64:$dst, EFLAGS,
773 (X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
775 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
776 (ins GR16:$src1, i16i8imm:$src2),
777 "or{w}\t{$src2, $dst|$dst, $src2}",
778 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
779 i16immSExt8:$src2))]>, OpSize;
780 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
781 (ins GR32:$src1, i32i8imm:$src2),
782 "or{l}\t{$src2, $dst|$dst, $src2}",
783 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
784 i32immSExt8:$src2))]>;
785 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
786 (ins GR64:$src1, i64i8imm:$src2),
787 "or{q}\t{$src2, $dst|$dst, $src2}",
788 [(set GR64:$dst, EFLAGS,
789 (X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
790 } // Constraints = "$src1 = $dst"
792 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
793 "or{b}\t{$src, $dst|$dst, $src}",
794 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
796 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
797 "or{w}\t{$src, $dst|$dst, $src}",
798 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
799 (implicit EFLAGS)]>, OpSize;
800 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
801 "or{l}\t{$src, $dst|$dst, $src}",
802 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
804 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
805 "or{q}\t{$src, $dst|$dst, $src}",
806 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
809 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
810 "or{b}\t{$src, $dst|$dst, $src}",
811 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
813 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
814 "or{w}\t{$src, $dst|$dst, $src}",
815 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
818 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
819 "or{l}\t{$src, $dst|$dst, $src}",
820 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
822 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
823 "or{q}\t{$src, $dst|$dst, $src}",
824 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
827 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
828 "or{w}\t{$src, $dst|$dst, $src}",
829 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
832 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
833 "or{l}\t{$src, $dst|$dst, $src}",
834 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
836 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
837 "or{q}\t{$src, $dst|$dst, $src}",
838 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
841 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
842 "or{b}\t{$src, %al|%al, $src}", []>;
843 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
844 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
845 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
846 "or{l}\t{$src, %eax|%eax, $src}", []>;
847 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i64i32imm:$src),
848 "or{q}\t{$src, %rax|%rax, $src}", []>;
851 let Constraints = "$src1 = $dst" in {
853 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
854 def XOR8rr : I<0x30, MRMDestReg,
855 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
856 "xor{b}\t{$src2, $dst|$dst, $src2}",
857 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
859 def XOR16rr : I<0x31, MRMDestReg,
860 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
861 "xor{w}\t{$src2, $dst|$dst, $src2}",
862 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
863 GR16:$src2))]>, OpSize;
864 def XOR32rr : I<0x31, MRMDestReg,
865 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
866 "xor{l}\t{$src2, $dst|$dst, $src2}",
867 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
869 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
870 (ins GR64:$src1, GR64:$src2),
871 "xor{q}\t{$src2, $dst|$dst, $src2}",
872 [(set GR64:$dst, EFLAGS,
873 (X86xor_flag GR64:$src1, GR64:$src2))]>;
874 } // isCommutable = 1
876 // XOR instructions with the destination register in REG and the source register
877 // in R/M. Included for the disassembler.
878 let isCodeGenOnly = 1 in {
879 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
880 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
881 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
882 (ins GR16:$src1, GR16:$src2),
883 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
884 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
885 (ins GR32:$src1, GR32:$src2),
886 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
887 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
888 (ins GR64:$src1, GR64:$src2),
889 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
892 def XOR8rm : I<0x32, MRMSrcMem,
893 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
894 "xor{b}\t{$src2, $dst|$dst, $src2}",
895 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
896 (load addr:$src2)))]>;
897 def XOR16rm : I<0x33, MRMSrcMem,
898 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
899 "xor{w}\t{$src2, $dst|$dst, $src2}",
900 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
901 (load addr:$src2)))]>,
903 def XOR32rm : I<0x33, MRMSrcMem,
904 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
905 "xor{l}\t{$src2, $dst|$dst, $src2}",
906 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
907 (load addr:$src2)))]>;
908 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
909 (ins GR64:$src1, i64mem:$src2),
910 "xor{q}\t{$src2, $dst|$dst, $src2}",
911 [(set GR64:$dst, EFLAGS,
912 (X86xor_flag GR64:$src1, (load addr:$src2)))]>;
914 def XOR8ri : Ii8<0x80, MRM6r,
915 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
916 "xor{b}\t{$src2, $dst|$dst, $src2}",
917 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
918 def XOR16ri : Ii16<0x81, MRM6r,
919 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
920 "xor{w}\t{$src2, $dst|$dst, $src2}",
921 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
922 imm:$src2))]>, OpSize;
923 def XOR32ri : Ii32<0x81, MRM6r,
924 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
925 "xor{l}\t{$src2, $dst|$dst, $src2}",
926 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
928 def XOR64ri32 : RIi32<0x81, MRM6r,
929 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
930 "xor{q}\t{$src2, $dst|$dst, $src2}",
931 [(set GR64:$dst, EFLAGS,
932 (X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
934 def XOR16ri8 : Ii8<0x83, MRM6r,
935 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
936 "xor{w}\t{$src2, $dst|$dst, $src2}",
937 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
938 i16immSExt8:$src2))]>,
940 def XOR32ri8 : Ii8<0x83, MRM6r,
941 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
942 "xor{l}\t{$src2, $dst|$dst, $src2}",
943 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
944 i32immSExt8:$src2))]>;
945 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
946 (ins GR64:$src1, i64i8imm:$src2),
947 "xor{q}\t{$src2, $dst|$dst, $src2}",
948 [(set GR64:$dst, EFLAGS,
949 (X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
950 } // Constraints = "$src1 = $dst"
953 def XOR8mr : I<0x30, MRMDestMem,
954 (outs), (ins i8mem :$dst, GR8 :$src),
955 "xor{b}\t{$src, $dst|$dst, $src}",
956 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
958 def XOR16mr : I<0x31, MRMDestMem,
959 (outs), (ins i16mem:$dst, GR16:$src),
960 "xor{w}\t{$src, $dst|$dst, $src}",
961 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
964 def XOR32mr : I<0x31, MRMDestMem,
965 (outs), (ins i32mem:$dst, GR32:$src),
966 "xor{l}\t{$src, $dst|$dst, $src}",
967 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
969 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
970 "xor{q}\t{$src, $dst|$dst, $src}",
971 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
974 def XOR8mi : Ii8<0x80, MRM6m,
975 (outs), (ins i8mem :$dst, i8imm :$src),
976 "xor{b}\t{$src, $dst|$dst, $src}",
977 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
979 def XOR16mi : Ii16<0x81, MRM6m,
980 (outs), (ins i16mem:$dst, i16imm:$src),
981 "xor{w}\t{$src, $dst|$dst, $src}",
982 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
985 def XOR32mi : Ii32<0x81, MRM6m,
986 (outs), (ins i32mem:$dst, i32imm:$src),
987 "xor{l}\t{$src, $dst|$dst, $src}",
988 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
990 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
991 "xor{q}\t{$src, $dst|$dst, $src}",
992 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
995 def XOR16mi8 : Ii8<0x83, MRM6m,
996 (outs), (ins i16mem:$dst, i16i8imm :$src),
997 "xor{w}\t{$src, $dst|$dst, $src}",
998 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1001 def XOR32mi8 : Ii8<0x83, MRM6m,
1002 (outs), (ins i32mem:$dst, i32i8imm :$src),
1003 "xor{l}\t{$src, $dst|$dst, $src}",
1004 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1005 (implicit EFLAGS)]>;
1006 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1007 "xor{q}\t{$src, $dst|$dst, $src}",
1008 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1009 (implicit EFLAGS)]>;
1011 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
1012 "xor{b}\t{$src, %al|%al, $src}", []>;
1013 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
1014 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1015 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
1016 "xor{l}\t{$src, %eax|%eax, $src}", []>;
1017 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i64i32imm:$src),
1018 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1019 } // Defs = [EFLAGS]
1023 let Defs = [EFLAGS] in {
1024 let Constraints = "$src1 = $dst" in {
1025 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1026 // Register-Register Addition
1027 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1028 (ins GR8 :$src1, GR8 :$src2),
1029 "add{b}\t{$src2, $dst|$dst, $src2}",
1030 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
1032 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1033 // Register-Register Addition
1034 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1035 (ins GR16:$src1, GR16:$src2),
1036 "add{w}\t{$src2, $dst|$dst, $src2}",
1037 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1038 GR16:$src2))]>, OpSize;
1039 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1040 (ins GR32:$src1, GR32:$src2),
1041 "add{l}\t{$src2, $dst|$dst, $src2}",
1042 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1044 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
1045 (ins GR64:$src1, GR64:$src2),
1046 "add{q}\t{$src2, $dst|$dst, $src2}",
1047 [(set GR64:$dst, EFLAGS,
1048 (X86add_flag GR64:$src1, GR64:$src2))]>;
1049 } // end isConvertibleToThreeAddress
1050 } // end isCommutable
1052 // These are alternate spellings for use by the disassembler, we mark them as
1053 // code gen only to ensure they aren't matched by the assembler.
1054 let isCodeGenOnly = 1 in {
1055 def ADD8rr_alt: I<0x02, MRMSrcReg,
1056 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1057 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
1058 def ADD16rr_alt: I<0x03, MRMSrcReg,
1059 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1060 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1061 def ADD32rr_alt: I<0x03, MRMSrcReg,
1062 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1063 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1064 def ADD64rr_alt : RI<0x03, MRMSrcReg,
1065 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1066 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1069 // Register-Memory Addition
1070 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1071 (ins GR8 :$src1, i8mem :$src2),
1072 "add{b}\t{$src2, $dst|$dst, $src2}",
1073 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
1074 (load addr:$src2)))]>;
1075 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1076 (ins GR16:$src1, i16mem:$src2),
1077 "add{w}\t{$src2, $dst|$dst, $src2}",
1078 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1079 (load addr:$src2)))]>, OpSize;
1080 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1081 (ins GR32:$src1, i32mem:$src2),
1082 "add{l}\t{$src2, $dst|$dst, $src2}",
1083 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1084 (load addr:$src2)))]>;
1085 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
1086 (ins GR64:$src1, i64mem:$src2),
1087 "add{q}\t{$src2, $dst|$dst, $src2}",
1088 [(set GR64:$dst, EFLAGS,
1089 (X86add_flag GR64:$src1, (load addr:$src2)))]>;
1091 // Register-Integer Addition
1092 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1093 "add{b}\t{$src2, $dst|$dst, $src2}",
1094 [(set GR8:$dst, EFLAGS,
1095 (X86add_flag GR8:$src1, imm:$src2))]>;
1097 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1098 // Register-Integer Addition
1099 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1100 (ins GR16:$src1, i16imm:$src2),
1101 "add{w}\t{$src2, $dst|$dst, $src2}",
1102 [(set GR16:$dst, EFLAGS,
1103 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
1104 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1105 (ins GR32:$src1, i32imm:$src2),
1106 "add{l}\t{$src2, $dst|$dst, $src2}",
1107 [(set GR32:$dst, EFLAGS,
1108 (X86add_flag GR32:$src1, imm:$src2))]>;
1109 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1110 (ins GR16:$src1, i16i8imm:$src2),
1111 "add{w}\t{$src2, $dst|$dst, $src2}",
1112 [(set GR16:$dst, EFLAGS,
1113 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1114 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1115 (ins GR32:$src1, i32i8imm:$src2),
1116 "add{l}\t{$src2, $dst|$dst, $src2}",
1117 [(set GR32:$dst, EFLAGS,
1118 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
1119 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
1120 (ins GR64:$src1, i64i8imm:$src2),
1121 "add{q}\t{$src2, $dst|$dst, $src2}",
1122 [(set GR64:$dst, EFLAGS,
1123 (X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
1124 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
1125 (ins GR64:$src1, i64i32imm:$src2),
1126 "add{q}\t{$src2, $dst|$dst, $src2}",
1127 [(set GR64:$dst, EFLAGS,
1128 (X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
1130 } // Constraints = "$src1 = $dst"
1132 // Memory-Register Addition
1133 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1134 "add{b}\t{$src2, $dst|$dst, $src2}",
1135 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
1136 (implicit EFLAGS)]>;
1137 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1138 "add{w}\t{$src2, $dst|$dst, $src2}",
1139 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
1140 (implicit EFLAGS)]>, OpSize;
1141 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1142 "add{l}\t{$src2, $dst|$dst, $src2}",
1143 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
1144 (implicit EFLAGS)]>;
1145 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1146 "add{q}\t{$src2, $dst|$dst, $src2}",
1147 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
1148 (implicit EFLAGS)]>;
1149 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1150 "add{b}\t{$src2, $dst|$dst, $src2}",
1151 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
1152 (implicit EFLAGS)]>;
1153 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1154 "add{w}\t{$src2, $dst|$dst, $src2}",
1155 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
1156 (implicit EFLAGS)]>, OpSize;
1157 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1158 "add{l}\t{$src2, $dst|$dst, $src2}",
1159 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
1160 (implicit EFLAGS)]>;
1161 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
1162 "add{q}\t{$src2, $dst|$dst, $src2}",
1163 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
1164 (implicit EFLAGS)]>;
1165 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1166 "add{w}\t{$src2, $dst|$dst, $src2}",
1167 [(store (add (load addr:$dst), i16immSExt8:$src2),
1169 (implicit EFLAGS)]>, OpSize;
1170 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1171 "add{l}\t{$src2, $dst|$dst, $src2}",
1172 [(store (add (load addr:$dst), i32immSExt8:$src2),
1174 (implicit EFLAGS)]>;
1175 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1176 "add{q}\t{$src2, $dst|$dst, $src2}",
1177 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
1178 (implicit EFLAGS)]>;
1181 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
1182 "add{b}\t{$src, %al|%al, $src}", []>;
1183 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
1184 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1185 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
1186 "add{l}\t{$src, %eax|%eax, $src}", []>;
1187 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i64i32imm:$src),
1188 "add{q}\t{$src, %rax|%rax, $src}", []>;
1190 let Uses = [EFLAGS] in {
1191 let Constraints = "$src1 = $dst" in {
1192 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1193 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1194 "adc{b}\t{$src2, $dst|$dst, $src2}",
1195 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
1196 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
1197 (ins GR16:$src1, GR16:$src2),
1198 "adc{w}\t{$src2, $dst|$dst, $src2}",
1199 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
1200 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
1201 (ins GR32:$src1, GR32:$src2),
1202 "adc{l}\t{$src2, $dst|$dst, $src2}",
1203 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1204 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
1205 (ins GR64:$src1, GR64:$src2),
1206 "adc{q}\t{$src2, $dst|$dst, $src2}",
1207 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
1210 let isCodeGenOnly = 1 in {
1211 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1212 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
1213 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
1214 (ins GR16:$src1, GR16:$src2),
1215 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1216 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
1217 (ins GR32:$src1, GR32:$src2),
1218 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
1219 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
1220 (ins GR64:$src1, GR64:$src2),
1221 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
1224 def ADC8rm : I<0x12, MRMSrcMem ,
1225 (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1226 "adc{b}\t{$src2, $dst|$dst, $src2}",
1227 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
1228 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
1229 (ins GR16:$src1, i16mem:$src2),
1230 "adc{w}\t{$src2, $dst|$dst, $src2}",
1231 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
1233 def ADC32rm : I<0x13, MRMSrcMem ,
1234 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1235 "adc{l}\t{$src2, $dst|$dst, $src2}",
1236 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1237 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
1238 (ins GR64:$src1, i64mem:$src2),
1239 "adc{q}\t{$src2, $dst|$dst, $src2}",
1240 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
1241 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1242 "adc{b}\t{$src2, $dst|$dst, $src2}",
1243 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
1244 def ADC16ri : Ii16<0x81, MRM2r,
1245 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1246 "adc{w}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
1248 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
1249 (ins GR16:$src1, i16i8imm:$src2),
1250 "adc{w}\t{$src2, $dst|$dst, $src2}",
1251 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
1253 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
1254 (ins GR32:$src1, i32imm:$src2),
1255 "adc{l}\t{$src2, $dst|$dst, $src2}",
1256 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1257 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
1258 (ins GR32:$src1, i32i8imm:$src2),
1259 "adc{l}\t{$src2, $dst|$dst, $src2}",
1260 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1261 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
1262 (ins GR64:$src1, i64i32imm:$src2),
1263 "adc{q}\t{$src2, $dst|$dst, $src2}",
1264 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
1265 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
1266 (ins GR64:$src1, i64i8imm:$src2),
1267 "adc{q}\t{$src2, $dst|$dst, $src2}",
1268 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
1269 } // Constraints = "$src1 = $dst"
1271 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1272 "adc{b}\t{$src2, $dst|$dst, $src2}",
1273 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
1274 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1275 "adc{w}\t{$src2, $dst|$dst, $src2}",
1276 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
1278 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1279 "adc{l}\t{$src2, $dst|$dst, $src2}",
1280 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1281 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1282 "adc{q}\t{$src2, $dst|$dst, $src2}",
1283 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
1284 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
1285 "adc{b}\t{$src2, $dst|$dst, $src2}",
1286 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1287 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
1288 "adc{w}\t{$src2, $dst|$dst, $src2}",
1289 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1291 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1292 "adc{w}\t{$src2, $dst|$dst, $src2}",
1293 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1295 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1296 "adc{l}\t{$src2, $dst|$dst, $src2}",
1297 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1298 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1299 "adc{l}\t{$src2, $dst|$dst, $src2}",
1300 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1302 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1303 "adc{q}\t{$src2, $dst|$dst, $src2}",
1304 [(store (adde (load addr:$dst), i64immSExt32:$src2),
1306 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1307 "adc{q}\t{$src2, $dst|$dst, $src2}",
1308 [(store (adde (load addr:$dst), i64immSExt8:$src2),
1311 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
1312 "adc{b}\t{$src, %al|%al, $src}", []>;
1313 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
1314 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1315 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
1316 "adc{l}\t{$src, %eax|%eax, $src}", []>;
1317 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i64i32imm:$src),
1318 "adc{q}\t{$src, %rax|%rax, $src}", []>;
1319 } // Uses = [EFLAGS]
1321 let Constraints = "$src1 = $dst" in {
1323 // Register-Register Subtraction
1324 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1325 "sub{b}\t{$src2, $dst|$dst, $src2}",
1326 [(set GR8:$dst, EFLAGS,
1327 (X86sub_flag GR8:$src1, GR8:$src2))]>;
1328 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
1329 "sub{w}\t{$src2, $dst|$dst, $src2}",
1330 [(set GR16:$dst, EFLAGS,
1331 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
1332 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
1333 "sub{l}\t{$src2, $dst|$dst, $src2}",
1334 [(set GR32:$dst, EFLAGS,
1335 (X86sub_flag GR32:$src1, GR32:$src2))]>;
1336 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
1337 (ins GR64:$src1, GR64:$src2),
1338 "sub{q}\t{$src2, $dst|$dst, $src2}",
1339 [(set GR64:$dst, EFLAGS,
1340 (X86sub_flag GR64:$src1, GR64:$src2))]>;
1342 let isCodeGenOnly = 1 in {
1343 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1344 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
1345 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
1346 (ins GR16:$src1, GR16:$src2),
1347 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1348 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
1349 (ins GR32:$src1, GR32:$src2),
1350 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
1351 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
1352 (ins GR64:$src1, GR64:$src2),
1353 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
1356 // Register-Memory Subtraction
1357 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
1358 (ins GR8 :$src1, i8mem :$src2),
1359 "sub{b}\t{$src2, $dst|$dst, $src2}",
1360 [(set GR8:$dst, EFLAGS,
1361 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
1362 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
1363 (ins GR16:$src1, i16mem:$src2),
1364 "sub{w}\t{$src2, $dst|$dst, $src2}",
1365 [(set GR16:$dst, EFLAGS,
1366 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
1367 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
1368 (ins GR32:$src1, i32mem:$src2),
1369 "sub{l}\t{$src2, $dst|$dst, $src2}",
1370 [(set GR32:$dst, EFLAGS,
1371 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
1372 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
1373 (ins GR64:$src1, i64mem:$src2),
1374 "sub{q}\t{$src2, $dst|$dst, $src2}",
1375 [(set GR64:$dst, EFLAGS,
1376 (X86sub_flag GR64:$src1, (load addr:$src2)))]>;
1378 // Register-Integer Subtraction
1379 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
1380 (ins GR8:$src1, i8imm:$src2),
1381 "sub{b}\t{$src2, $dst|$dst, $src2}",
1382 [(set GR8:$dst, EFLAGS,
1383 (X86sub_flag GR8:$src1, imm:$src2))]>;
1384 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
1385 (ins GR16:$src1, i16imm:$src2),
1386 "sub{w}\t{$src2, $dst|$dst, $src2}",
1387 [(set GR16:$dst, EFLAGS,
1388 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
1389 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
1390 (ins GR32:$src1, i32imm:$src2),
1391 "sub{l}\t{$src2, $dst|$dst, $src2}",
1392 [(set GR32:$dst, EFLAGS,
1393 (X86sub_flag GR32:$src1, imm:$src2))]>;
1394 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
1395 (ins GR64:$src1, i64i32imm:$src2),
1396 "sub{q}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR64:$dst, EFLAGS,
1398 (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
1399 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
1400 (ins GR16:$src1, i16i8imm:$src2),
1401 "sub{w}\t{$src2, $dst|$dst, $src2}",
1402 [(set GR16:$dst, EFLAGS,
1403 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1404 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
1405 (ins GR32:$src1, i32i8imm:$src2),
1406 "sub{l}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR32:$dst, EFLAGS,
1408 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
1409 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
1410 (ins GR64:$src1, i64i8imm:$src2),
1411 "sub{q}\t{$src2, $dst|$dst, $src2}",
1412 [(set GR64:$dst, EFLAGS,
1413 (X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
1414 } // Constraints = "$src1 = $dst"
1416 // Memory-Register Subtraction
1417 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1418 "sub{b}\t{$src2, $dst|$dst, $src2}",
1419 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
1420 (implicit EFLAGS)]>;
1421 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1422 "sub{w}\t{$src2, $dst|$dst, $src2}",
1423 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
1424 (implicit EFLAGS)]>, OpSize;
1425 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1426 "sub{l}\t{$src2, $dst|$dst, $src2}",
1427 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
1428 (implicit EFLAGS)]>;
1429 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1430 "sub{q}\t{$src2, $dst|$dst, $src2}",
1431 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
1432 (implicit EFLAGS)]>;
1434 // Memory-Integer Subtraction
1435 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1436 "sub{b}\t{$src2, $dst|$dst, $src2}",
1437 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
1438 (implicit EFLAGS)]>;
1439 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1440 "sub{w}\t{$src2, $dst|$dst, $src2}",
1441 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
1442 (implicit EFLAGS)]>, OpSize;
1443 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1444 "sub{l}\t{$src2, $dst|$dst, $src2}",
1445 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
1446 (implicit EFLAGS)]>;
1447 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1448 "sub{q}\t{$src2, $dst|$dst, $src2}",
1449 [(store (sub (load addr:$dst), i64immSExt32:$src2),
1451 (implicit EFLAGS)]>;
1452 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1453 "sub{w}\t{$src2, $dst|$dst, $src2}",
1454 [(store (sub (load addr:$dst), i16immSExt8:$src2),
1456 (implicit EFLAGS)]>, OpSize;
1457 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1458 "sub{l}\t{$src2, $dst|$dst, $src2}",
1459 [(store (sub (load addr:$dst), i32immSExt8:$src2),
1461 (implicit EFLAGS)]>;
1462 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1463 "sub{q}\t{$src2, $dst|$dst, $src2}",
1464 [(store (sub (load addr:$dst), i64immSExt8:$src2),
1466 (implicit EFLAGS)]>;
1468 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
1469 "sub{b}\t{$src, %al|%al, $src}", []>;
1470 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
1471 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1472 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
1473 "sub{l}\t{$src, %eax|%eax, $src}", []>;
1474 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i64i32imm:$src),
1475 "sub{q}\t{$src, %rax|%rax, $src}", []>;
1477 let Uses = [EFLAGS] in {
1478 let Constraints = "$src1 = $dst" in {
1479 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
1480 (ins GR8:$src1, GR8:$src2),
1481 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1482 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
1483 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
1484 (ins GR16:$src1, GR16:$src2),
1485 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1486 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
1487 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
1488 (ins GR32:$src1, GR32:$src2),
1489 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1490 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1491 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
1492 (ins GR64:$src1, GR64:$src2),
1493 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1494 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
1495 } // Constraints = "$src1 = $dst"
1498 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1499 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1500 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
1501 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1502 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1503 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
1505 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1506 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1507 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1508 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1509 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1510 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
1512 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
1513 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1514 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1515 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
1516 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1517 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1519 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1520 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1521 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1523 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
1524 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1525 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1526 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1527 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1528 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1529 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1530 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1531 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
1532 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1533 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1534 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
1536 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
1537 "sbb{b}\t{$src, %al|%al, $src}", []>;
1538 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
1539 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1540 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
1541 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
1542 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i64i32imm:$src),
1543 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
1545 let Constraints = "$src1 = $dst" in {
1547 let isCodeGenOnly = 1 in {
1548 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1549 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
1550 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
1551 (ins GR16:$src1, GR16:$src2),
1552 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1553 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
1554 (ins GR32:$src1, GR32:$src2),
1555 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
1556 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
1557 (ins GR64:$src1, GR64:$src2),
1558 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
1561 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1562 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1563 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
1564 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
1565 (ins GR16:$src1, i16mem:$src2),
1566 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
1569 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
1570 (ins GR32:$src1, i32mem:$src2),
1571 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1572 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
1573 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
1574 (ins GR64:$src1, i64mem:$src2),
1575 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1576 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
1577 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1578 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1579 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
1580 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
1581 (ins GR16:$src1, i16imm:$src2),
1582 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1583 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
1584 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
1585 (ins GR16:$src1, i16i8imm:$src2),
1586 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1587 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
1589 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
1590 (ins GR32:$src1, i32imm:$src2),
1591 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1592 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
1593 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
1594 (ins GR32:$src1, i32i8imm:$src2),
1595 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1596 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
1597 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
1598 (ins GR64:$src1, i64i32imm:$src2),
1599 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1600 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
1601 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
1602 (ins GR64:$src1, i64i8imm:$src2),
1603 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1604 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
1606 } // Constraints = "$src1 = $dst"
1607 } // Uses = [EFLAGS]
1608 } // Defs = [EFLAGS]
1610 //===----------------------------------------------------------------------===//
1611 // Test instructions are just like AND, except they don't generate a result.
1613 let Defs = [EFLAGS] in {
1614 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
1615 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1616 "test{b}\t{$src2, $src1|$src1, $src2}",
1617 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
1618 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1619 "test{w}\t{$src2, $src1|$src1, $src2}",
1620 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
1623 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1624 "test{l}\t{$src2, $src1|$src1, $src2}",
1625 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
1627 def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1628 "test{q}\t{$src2, $src1|$src1, $src2}",
1629 [(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
1632 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
1633 "test{b}\t{$src2, $src1|$src1, $src2}",
1634 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
1636 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
1637 "test{w}\t{$src2, $src1|$src1, $src2}",
1638 [(set EFLAGS, (X86cmp (and GR16:$src1,
1639 (loadi16 addr:$src2)), 0))]>, OpSize;
1640 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
1641 "test{l}\t{$src2, $src1|$src1, $src2}",
1642 [(set EFLAGS, (X86cmp (and GR32:$src1,
1643 (loadi32 addr:$src2)), 0))]>;
1644 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1645 "test{q}\t{$src2, $src1|$src1, $src2}",
1646 [(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
1649 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
1650 (outs), (ins GR8:$src1, i8imm:$src2),
1651 "test{b}\t{$src2, $src1|$src1, $src2}",
1652 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
1653 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
1654 (outs), (ins GR16:$src1, i16imm:$src2),
1655 "test{w}\t{$src2, $src1|$src1, $src2}",
1656 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
1658 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
1659 (outs), (ins GR32:$src1, i32imm:$src2),
1660 "test{l}\t{$src2, $src1|$src1, $src2}",
1661 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
1662 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1663 (ins GR64:$src1, i64i32imm:$src2),
1664 "test{q}\t{$src2, $src1|$src1, $src2}",
1665 [(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
1668 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
1669 (outs), (ins i8mem:$src1, i8imm:$src2),
1670 "test{b}\t{$src2, $src1|$src1, $src2}",
1671 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
1673 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
1674 (outs), (ins i16mem:$src1, i16imm:$src2),
1675 "test{w}\t{$src2, $src1|$src1, $src2}",
1676 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
1678 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
1679 (outs), (ins i32mem:$src1, i32imm:$src2),
1680 "test{l}\t{$src2, $src1|$src1, $src2}",
1681 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
1683 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1684 (ins i64mem:$src1, i64i32imm:$src2),
1685 "test{q}\t{$src2, $src1|$src1, $src2}",
1686 [(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
1687 i64immSExt32:$src2), 0))]>;
1689 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
1690 "test{b}\t{$src, %al|%al, $src}", []>;
1691 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
1692 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1693 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
1694 "test{l}\t{$src, %eax|%eax, $src}", []>;
1695 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
1696 "test{q}\t{$src, %rax|%rax, $src}", []>;
1698 } // Defs = [EFLAGS]
1701 //===----------------------------------------------------------------------===//
1702 // Integer comparisons
1704 let Defs = [EFLAGS] in {
1706 def CMP8rr : I<0x38, MRMDestReg,
1707 (outs), (ins GR8 :$src1, GR8 :$src2),
1708 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1709 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
1710 def CMP16rr : I<0x39, MRMDestReg,
1711 (outs), (ins GR16:$src1, GR16:$src2),
1712 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1713 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
1714 def CMP32rr : I<0x39, MRMDestReg,
1715 (outs), (ins GR32:$src1, GR32:$src2),
1716 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1717 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
1718 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1719 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1720 [(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
1722 def CMP8mr : I<0x38, MRMDestMem,
1723 (outs), (ins i8mem :$src1, GR8 :$src2),
1724 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1725 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
1726 def CMP16mr : I<0x39, MRMDestMem,
1727 (outs), (ins i16mem:$src1, GR16:$src2),
1728 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1729 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
1731 def CMP32mr : I<0x39, MRMDestMem,
1732 (outs), (ins i32mem:$src1, GR32:$src2),
1733 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1734 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
1735 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1736 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1737 [(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
1739 def CMP8rm : I<0x3A, MRMSrcMem,
1740 (outs), (ins GR8 :$src1, i8mem :$src2),
1741 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1742 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
1743 def CMP16rm : I<0x3B, MRMSrcMem,
1744 (outs), (ins GR16:$src1, i16mem:$src2),
1745 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1746 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
1748 def CMP32rm : I<0x3B, MRMSrcMem,
1749 (outs), (ins GR32:$src1, i32mem:$src2),
1750 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1751 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
1752 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1753 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1754 [(set EFLAGS, (X86cmp GR64:$src1, (loadi64 addr:$src2)))]>;
1756 // These are alternate spellings for use by the disassembler, we mark them as
1757 // code gen only to ensure they aren't matched by the assembler.
1758 let isCodeGenOnly = 1 in {
1759 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1760 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
1761 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1762 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
1763 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1764 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
1765 def CMP64rr_alt : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1766 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1769 def CMP8ri : Ii8<0x80, MRM7r,
1770 (outs), (ins GR8:$src1, i8imm:$src2),
1771 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1772 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
1773 def CMP16ri : Ii16<0x81, MRM7r,
1774 (outs), (ins GR16:$src1, i16imm:$src2),
1775 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1776 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
1777 def CMP32ri : Ii32<0x81, MRM7r,
1778 (outs), (ins GR32:$src1, i32imm:$src2),
1779 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1780 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
1781 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1782 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1783 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt32:$src2))]>;
1785 def CMP8mi : Ii8 <0x80, MRM7m,
1786 (outs), (ins i8mem :$src1, i8imm :$src2),
1787 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1788 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
1789 def CMP16mi : Ii16<0x81, MRM7m,
1790 (outs), (ins i16mem:$src1, i16imm:$src2),
1791 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1792 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
1794 def CMP32mi : Ii32<0x81, MRM7m,
1795 (outs), (ins i32mem:$src1, i32imm:$src2),
1796 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1797 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
1798 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1799 (ins i64mem:$src1, i64i32imm:$src2),
1800 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1801 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1802 i64immSExt32:$src2))]>;
1804 def CMP16ri8 : Ii8<0x83, MRM7r,
1805 (outs), (ins GR16:$src1, i16i8imm:$src2),
1806 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1807 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
1809 def CMP32ri8 : Ii8<0x83, MRM7r,
1810 (outs), (ins GR32:$src1, i32i8imm:$src2),
1811 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1812 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
1813 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1814 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1815 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt8:$src2))]>;
1817 def CMP16mi8 : Ii8<0x83, MRM7m,
1818 (outs), (ins i16mem:$src1, i16i8imm:$src2),
1819 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1820 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
1821 i16immSExt8:$src2))]>, OpSize;
1822 def CMP32mi8 : Ii8<0x83, MRM7m,
1823 (outs), (ins i32mem:$src1, i32i8imm:$src2),
1824 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1825 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
1826 i32immSExt8:$src2))]>;
1827 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1828 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1829 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1830 i64immSExt8:$src2))]>;
1832 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
1833 "cmp{b}\t{$src, %al|%al, $src}", []>;
1834 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
1835 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1836 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
1837 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
1838 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i64i32imm:$src),
1839 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1841 } // Defs = [EFLAGS]