1 //===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file exposes functions that may be used with BuildMI from the
11 // MachineInstrBuilder.h file to handle X86'isms in a clean way.
13 // The BuildMem function may be used with the BuildMI function to add entire
14 // memory references in a single, typed, function call. X86 memory references
15 // can be very complex expressions (described in the README), so wrapping them
16 // up behind an easier to use interface makes sense. Descriptions of the
17 // functions are included below.
19 // For reference, the order of operands for memory references is:
20 // (Operand), Base, Scale, Index, Displacement.
22 //===----------------------------------------------------------------------===//
24 #ifndef X86INSTRBUILDER_H
25 #define X86INSTRBUILDER_H
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineMemOperand.h"
30 #include "llvm/CodeGen/PseudoSourceValue.h"
34 /// X86AddressMode - This struct holds a generalized full x86 address mode.
35 /// The base register can be a frame index, which will eventually be replaced
36 /// with BP or SP and Disp being offsetted accordingly. The displacement may
37 /// also include the offset of a global value.
38 struct X86AddressMode {
56 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
61 /// addDirectMem - This function is used to add a direct memory reference to the
62 /// current instruction -- that is, a dereference of an address in a register,
63 /// with no scale, index or displacement. An example is: DWORD PTR [EAX].
65 static inline const MachineInstrBuilder &
66 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
67 // Because memory references are always represented with four
68 // values, this adds: Reg, [1, NoReg, 0] to the instruction.
69 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
72 static inline const MachineInstrBuilder &
73 addLeaOffset(const MachineInstrBuilder &MIB, int Offset) {
74 return MIB.addImm(1).addReg(0).addImm(Offset);
77 static inline const MachineInstrBuilder &
78 addOffset(const MachineInstrBuilder &MIB, int Offset) {
79 return addLeaOffset(MIB, Offset).addReg(0);
82 /// addRegOffset - This function is used to add a memory reference of the form
83 /// [Reg + Offset], i.e., one with no scale or index, but with a
84 /// displacement. An example is: DWORD PTR [EAX + 4].
86 static inline const MachineInstrBuilder &
87 addRegOffset(const MachineInstrBuilder &MIB,
88 unsigned Reg, bool isKill, int Offset) {
89 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
92 static inline const MachineInstrBuilder &
93 addLeaRegOffset(const MachineInstrBuilder &MIB,
94 unsigned Reg, bool isKill, int Offset) {
95 return addLeaOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
98 /// addRegReg - This function is used to add a memory reference of the form:
100 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
101 unsigned Reg1, bool isKill1,
102 unsigned Reg2, bool isKill2) {
103 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
104 .addReg(Reg2, getKillRegState(isKill2)).addImm(0);
107 static inline const MachineInstrBuilder &
108 addLeaAddress(const MachineInstrBuilder &MIB, const X86AddressMode &AM) {
109 assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
111 if (AM.BaseType == X86AddressMode::RegBase)
112 MIB.addReg(AM.Base.Reg);
113 else if (AM.BaseType == X86AddressMode::FrameIndexBase)
114 MIB.addFrameIndex(AM.Base.FrameIndex);
117 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
119 return MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
121 return MIB.addImm(AM.Disp);
124 static inline const MachineInstrBuilder &
125 addFullAddress(const MachineInstrBuilder &MIB,
126 const X86AddressMode &AM) {
127 return addLeaAddress(MIB, AM).addReg(0);
130 /// addFrameReference - This function is used to add a reference to the base of
131 /// an abstract object on the stack frame of the current function. This
132 /// reference has base register as the FrameIndex offset until it is resolved.
133 /// This allows a constant offset to be specified as well...
135 static inline const MachineInstrBuilder &
136 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
137 MachineInstr *MI = MIB;
138 MachineFunction &MF = *MI->getParent()->getParent();
139 MachineFrameInfo &MFI = *MF.getFrameInfo();
140 const TargetInstrDesc &TID = MI->getDesc();
143 Flags |= MachineMemOperand::MOLoad;
145 Flags |= MachineMemOperand::MOStore;
146 MachineMemOperand *MMO =
147 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
149 MFI.getObjectSize(FI),
150 MFI.getObjectAlignment(FI));
151 return addOffset(MIB.addFrameIndex(FI), Offset)
155 /// addConstantPoolReference - This function is used to add a reference to the
156 /// base of a constant value spilled to the per-function constant pool. The
157 /// reference uses the abstract ConstantPoolIndex which is retained until
158 /// either machine code emission or assembly output. In PIC mode on x86-32,
159 /// the GlobalBaseReg parameter can be used to make this a
160 /// GlobalBaseReg-relative reference.
162 static inline const MachineInstrBuilder &
163 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
164 unsigned GlobalBaseReg, unsigned char OpFlags) {
166 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
167 .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
170 } // End llvm namespace