1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
55 def : Pat<(X86callseq_start timm:$amt1),
56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
59 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
60 // a stack adjustment and the codegen must know that they may modify the stack
61 // pointer before prolog-epilog rewriting occurs.
62 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
63 // sub / add which can clobber EFLAGS.
64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
71 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
74 def : Pat<(X86callseq_start timm:$amt1),
75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
78 // x86-64 va_start lowering magic.
79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
83 i64imm:$regsavefi, i64imm:$offset,
85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
86 [(X86vastart_save_xmm_regs GR8:$al,
91 // The VAARG_64 pseudo-instruction takes the address of the va_list,
92 // and places the address of the next argument into a register.
93 let Defs = [EFLAGS] in
94 def VAARG_64 : I<0, Pseudo,
96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
97 "#VAARG_64 $dst, $ap, $size, $mode, $align",
99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
102 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
103 // targets. These calls are needed to probe the stack when allocating more than
104 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
105 // ensure that the guard pages used by the OS virtual memory manager are
106 // allocated in correct sequence.
107 // The main point of having separate instruction are extra unmodelled effects
108 // (compared to ordinary calls) like stack pointer change.
110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
112 "# dynamic stack allocation",
115 // When using segmented stacks these are lowered into instructions which first
116 // check if the current stacklet has enough free memory. If it does, memory is
117 // allocated by bumping the stack pointer. Otherwise memory is allocated from
120 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
121 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
122 "# variable sized alloca for segmented stacks",
124 (X86SegAlloca GR32:$size))]>,
127 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
128 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
129 "# variable sized alloca for segmented stacks",
131 (X86SegAlloca GR64:$size))]>,
132 Requires<[In64BitMode]>;
135 //===----------------------------------------------------------------------===//
136 // EH Pseudo Instructions
138 let SchedRW = [WriteSystem] in {
139 let isTerminator = 1, isReturn = 1, isBarrier = 1,
140 hasCtrlDep = 1, isCodeGenOnly = 1 in {
141 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
142 "ret\t#eh_return, addr: $addr",
143 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
147 let isTerminator = 1, isReturn = 1, isBarrier = 1,
148 hasCtrlDep = 1, isCodeGenOnly = 1 in {
149 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
150 "ret\t#eh_return, addr: $addr",
151 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
155 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
156 usesCustomInserter = 1 in {
157 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
159 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
160 Requires<[Not64BitMode]>;
161 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
163 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
164 Requires<[In64BitMode]>;
165 let isTerminator = 1 in {
166 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
167 "#EH_SJLJ_LONGJMP32",
168 [(X86eh_sjlj_longjmp addr:$buf)]>,
169 Requires<[Not64BitMode]>;
170 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
171 "#EH_SJLJ_LONGJMP64",
172 [(X86eh_sjlj_longjmp addr:$buf)]>,
173 Requires<[In64BitMode]>;
178 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
179 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
180 "#EH_SjLj_Setup\t$dst", []>;
183 //===----------------------------------------------------------------------===//
184 // Pseudo instructions used by unwind info.
186 let isPseudo = 1 in {
187 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
188 "#SEH_PushReg $reg", []>;
189 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
190 "#SEH_SaveReg $reg, $dst", []>;
191 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
192 "#SEH_SaveXMM $reg, $dst", []>;
193 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
194 "#SEH_StackAlloc $size", []>;
195 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
196 "#SEH_SetFrame $reg, $offset", []>;
197 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
198 "#SEH_PushFrame $mode", []>;
199 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
200 "#SEH_EndPrologue", []>;
201 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
202 "#SEH_Epilogue", []>;
205 //===----------------------------------------------------------------------===//
206 // Pseudo instructions used by segmented stacks.
209 // This is lowered into a RET instruction by MCInstLower. We need
210 // this so that we don't have to have a MachineBasicBlock which ends
211 // with a RET and also has successors.
212 let isPseudo = 1 in {
213 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
216 // This instruction is lowered to a RET followed by a MOV. The two
217 // instructions are not generated on a higher level since then the
218 // verifier sees a MachineBasicBlock ending with a non-terminator.
219 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
223 //===----------------------------------------------------------------------===//
224 // Alias Instructions
225 //===----------------------------------------------------------------------===//
227 // Alias instruction mapping movr0 to xor.
228 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
229 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
231 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
232 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
234 // Other widths can also make use of the 32-bit xor, which may have a smaller
235 // encoding and avoid partial register updates.
236 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
237 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
238 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
239 let AddedComplexity = 20;
242 // Materialize i64 constant where top 32-bits are zero. This could theoretically
243 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
244 // that would make it more difficult to rematerialize.
245 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
246 isCodeGenOnly = 1, hasSideEffects = 0 in
247 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
248 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
250 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
251 // actually the zero-extension of a 32-bit constant, and for labels in the
252 // x86-64 small code model.
253 def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>;
255 let AddedComplexity = 1 in
256 def : Pat<(i64 mov64imm32:$src),
257 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
259 // Use sbb to materialize carry bit.
260 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
261 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
262 // However, Pat<> can't replicate the destination reg into the inputs of the
264 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
265 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
266 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
267 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
268 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
269 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
270 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
271 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
275 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
277 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
279 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
282 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
284 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
286 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
289 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
290 // will be eliminated and that the sbb can be extended up to a wider type. When
291 // this happens, it is great. However, if we are left with an 8-bit sbb and an
292 // and, we might as well just match it as a setb.
293 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
296 // (add OP, SETB) -> (adc OP, 0)
297 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
298 (ADC8ri GR8:$op, 0)>;
299 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
300 (ADC32ri8 GR32:$op, 0)>;
301 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
302 (ADC64ri8 GR64:$op, 0)>;
304 // (sub OP, SETB) -> (sbb OP, 0)
305 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
306 (SBB8ri GR8:$op, 0)>;
307 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
308 (SBB32ri8 GR32:$op, 0)>;
309 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
310 (SBB64ri8 GR64:$op, 0)>;
312 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
313 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
314 (ADC8ri GR8:$op, 0)>;
315 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
316 (ADC32ri8 GR32:$op, 0)>;
317 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
318 (ADC64ri8 GR64:$op, 0)>;
320 //===----------------------------------------------------------------------===//
321 // String Pseudo Instructions
323 let SchedRW = [WriteMicrocoded] in {
324 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
325 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
326 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
327 Requires<[Not64BitMode]>;
328 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
329 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
330 Requires<[Not64BitMode]>;
331 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
332 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
333 Requires<[Not64BitMode]>;
336 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
337 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
338 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
339 Requires<[In64BitMode]>;
340 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
341 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
342 Requires<[In64BitMode]>;
343 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
344 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
345 Requires<[In64BitMode]>;
346 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
347 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
348 Requires<[In64BitMode]>;
351 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
352 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
353 let Uses = [AL,ECX,EDI] in
354 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
355 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
356 Requires<[Not64BitMode]>;
357 let Uses = [AX,ECX,EDI] in
358 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
359 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
360 Requires<[Not64BitMode]>;
361 let Uses = [EAX,ECX,EDI] in
362 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
363 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
364 Requires<[Not64BitMode]>;
367 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
368 let Uses = [AL,RCX,RDI] in
369 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
370 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
371 Requires<[In64BitMode]>;
372 let Uses = [AX,RCX,RDI] in
373 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
374 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
375 Requires<[In64BitMode]>;
376 let Uses = [RAX,RCX,RDI] in
377 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
378 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
379 Requires<[In64BitMode]>;
381 let Uses = [RAX,RCX,RDI] in
382 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
383 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
384 Requires<[In64BitMode]>;
388 //===----------------------------------------------------------------------===//
389 // Thread Local Storage Instructions
393 // All calls clobber the non-callee saved registers. ESP is marked as
394 // a use to prevent stack-pointer assignments that appear immediately
395 // before calls from potentially appearing dead.
396 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
397 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
398 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
399 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
400 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
402 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
404 [(X86tlsaddr tls32addr:$sym)]>,
405 Requires<[Not64BitMode]>;
406 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
408 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
409 Requires<[Not64BitMode]>;
412 // All calls clobber the non-callee saved registers. RSP is marked as
413 // a use to prevent stack-pointer assignments that appear immediately
414 // before calls from potentially appearing dead.
415 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
416 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
417 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
418 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
419 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
420 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
422 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
424 [(X86tlsaddr tls64addr:$sym)]>,
425 Requires<[In64BitMode]>;
426 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
428 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
429 Requires<[In64BitMode]>;
432 // Darwin TLS Support
433 // For i386, the address of the thunk is passed on the stack, on return the
434 // address of the variable is in %eax. %ecx is trashed during the function
435 // call. All other registers are preserved.
436 let Defs = [EAX, ECX, EFLAGS],
438 usesCustomInserter = 1 in
439 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
441 [(X86TLSCall addr:$sym)]>,
442 Requires<[Not64BitMode]>;
444 // For x86_64, the address of the thunk is passed in %rdi, on return
445 // the address of the variable is in %rax. All other registers are preserved.
446 let Defs = [RAX, EFLAGS],
448 usesCustomInserter = 1 in
449 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
451 [(X86TLSCall addr:$sym)]>,
452 Requires<[In64BitMode]>;
455 //===----------------------------------------------------------------------===//
456 // Conditional Move Pseudo Instructions
458 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
459 // instruction selection into a branch sequence.
460 multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
461 def CMOV#NAME : I<0, Pseudo,
462 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
463 "#CMOV_"#NAME#" PSEUDO!",
464 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond,
468 let usesCustomInserter = 1, Uses = [EFLAGS] in {
469 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
470 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
471 // however that requires promoting the operands, and can induce additional
472 // i8 register pressure.
473 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
475 let Predicates = [NoCMov] in {
476 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
477 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
478 } // Predicates = [NoCMov]
480 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
482 let Predicates = [FPStackf32] in
483 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
485 let Predicates = [FPStackf64] in
486 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
488 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
490 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;
491 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;
492 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>;
493 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>;
494 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>;
495 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>;
496 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
497 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>;
498 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
499 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
500 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
501 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
502 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
503 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
504 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
505 } // usesCustomInserter = 1, Uses = [EFLAGS]
507 //===----------------------------------------------------------------------===//
508 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
509 //===----------------------------------------------------------------------===//
511 // FIXME: Use normal instructions and add lock prefix dynamically.
515 // TODO: Get this to fold the constant into the instruction.
516 let isCodeGenOnly = 1, Defs = [EFLAGS] in
517 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
518 "or{l}\t{$zero, $dst|$dst, $zero}",
519 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
520 Sched<[WriteALULd, WriteRMW]>;
522 let hasSideEffects = 1 in
523 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
525 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
527 // RegOpc corresponds to the mr version of the instruction
528 // ImmOpc corresponds to the mi version of the instruction
529 // ImmOpc8 corresponds to the mi8 version of the instruction
530 // ImmMod corresponds to the instruction format of the mi and mi8 versions
531 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
532 Format ImmMod, string mnemonic> {
533 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
534 SchedRW = [WriteALULd, WriteRMW] in {
536 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
537 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
538 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
539 !strconcat(mnemonic, "{b}\t",
540 "{$src2, $dst|$dst, $src2}"),
541 [], IIC_ALU_NONMEM>, LOCK;
542 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
543 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
544 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
545 !strconcat(mnemonic, "{w}\t",
546 "{$src2, $dst|$dst, $src2}"),
547 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
548 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
549 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
550 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
551 !strconcat(mnemonic, "{l}\t",
552 "{$src2, $dst|$dst, $src2}"),
553 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
554 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
555 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
556 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
557 !strconcat(mnemonic, "{q}\t",
558 "{$src2, $dst|$dst, $src2}"),
559 [], IIC_ALU_NONMEM>, LOCK;
561 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
562 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
563 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
564 !strconcat(mnemonic, "{b}\t",
565 "{$src2, $dst|$dst, $src2}"),
566 [], IIC_ALU_MEM>, LOCK;
568 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
569 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
570 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
571 !strconcat(mnemonic, "{w}\t",
572 "{$src2, $dst|$dst, $src2}"),
573 [], IIC_ALU_MEM>, OpSize16, LOCK;
575 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
576 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
577 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
578 !strconcat(mnemonic, "{l}\t",
579 "{$src2, $dst|$dst, $src2}"),
580 [], IIC_ALU_MEM>, OpSize32, LOCK;
582 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
583 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
584 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
585 !strconcat(mnemonic, "{q}\t",
586 "{$src2, $dst|$dst, $src2}"),
587 [], IIC_ALU_MEM>, LOCK;
589 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
590 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
591 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
592 !strconcat(mnemonic, "{w}\t",
593 "{$src2, $dst|$dst, $src2}"),
594 [], IIC_ALU_MEM>, OpSize16, LOCK;
595 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
596 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
597 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
598 !strconcat(mnemonic, "{l}\t",
599 "{$src2, $dst|$dst, $src2}"),
600 [], IIC_ALU_MEM>, OpSize32, LOCK;
601 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
602 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
603 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
604 !strconcat(mnemonic, "{q}\t",
605 "{$src2, $dst|$dst, $src2}"),
606 [], IIC_ALU_MEM>, LOCK;
612 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
613 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
614 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
615 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
616 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
618 // Optimized codegen when the non-memory output is not used.
619 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
621 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
622 SchedRW = [WriteALULd, WriteRMW] in {
624 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
625 !strconcat(mnemonic, "{b}\t$dst"),
626 [], IIC_UNARY_MEM>, LOCK;
627 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
628 !strconcat(mnemonic, "{w}\t$dst"),
629 [], IIC_UNARY_MEM>, OpSize16, LOCK;
630 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
631 !strconcat(mnemonic, "{l}\t$dst"),
632 [], IIC_UNARY_MEM>, OpSize32, LOCK;
633 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
634 !strconcat(mnemonic, "{q}\t$dst"),
635 [], IIC_UNARY_MEM>, LOCK;
639 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
640 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
642 // Atomic compare and swap.
643 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
644 SDPatternOperator frag, X86MemOperand x86memop,
645 InstrItinClass itin> {
646 let isCodeGenOnly = 1 in {
647 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
648 !strconcat(mnemonic, "\t$ptr"),
649 [(frag addr:$ptr)], itin>, TB, LOCK;
653 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
654 string mnemonic, SDPatternOperator frag,
655 InstrItinClass itin8, InstrItinClass itin> {
656 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
657 let Defs = [AL, EFLAGS], Uses = [AL] in
658 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
659 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
660 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
661 let Defs = [AX, EFLAGS], Uses = [AX] in
662 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
663 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
664 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
665 let Defs = [EAX, EFLAGS], Uses = [EAX] in
666 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
667 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
668 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
669 let Defs = [RAX, EFLAGS], Uses = [RAX] in
670 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
671 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
672 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
676 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
677 SchedRW = [WriteALULd, WriteRMW] in {
678 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
683 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
684 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
685 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
687 IIC_CMPX_LOCK_16B>, REX_W;
690 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
691 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
693 // Atomic exchange and add
694 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
696 InstrItinClass itin8, InstrItinClass itin> {
697 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
698 SchedRW = [WriteALULd, WriteRMW] in {
699 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
700 (ins GR8:$val, i8mem:$ptr),
701 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
703 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
705 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
706 (ins GR16:$val, i16mem:$ptr),
707 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
710 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
712 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
713 (ins GR32:$val, i32mem:$ptr),
714 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
717 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
719 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
720 (ins GR64:$val, i64mem:$ptr),
721 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
724 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
729 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
730 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
733 /* The following multiclass tries to make sure that in code like
734 * x.store (immediate op x.load(acquire), release)
736 * x.store (register op x.load(acquire), release)
737 * an operation directly on memory is generated instead of wasting a register.
738 * It is not automatic as atomic_store/load are only lowered to MOV instructions
739 * extremely late to prevent them from being accidentally reordered in the backend
740 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
742 multiclass RELEASE_BINOP_MI<SDNode op> {
743 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
744 "#BINOP "#NAME#"8mi PSEUDO!",
745 [(atomic_store_8 addr:$dst, (op
746 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
747 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src),
748 "#BINOP "#NAME#"8mr PSEUDO!",
749 [(atomic_store_8 addr:$dst, (op
750 (atomic_load_8 addr:$dst), GR8:$src))]>;
751 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
752 // costly and avoided as far as possible by this backend anyway
753 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
754 "#BINOP "#NAME#"32mi PSEUDO!",
755 [(atomic_store_32 addr:$dst, (op
756 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
757 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
758 "#BINOP "#NAME#"32mr PSEUDO!",
759 [(atomic_store_32 addr:$dst, (op
760 (atomic_load_32 addr:$dst), GR32:$src))]>;
761 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
762 "#BINOP "#NAME#"64mi32 PSEUDO!",
763 [(atomic_store_64 addr:$dst, (op
764 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
765 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
766 "#BINOP "#NAME#"64mr PSEUDO!",
767 [(atomic_store_64 addr:$dst, (op
768 (atomic_load_64 addr:$dst), GR64:$src))]>;
770 defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
771 defm RELEASE_AND : RELEASE_BINOP_MI<and>;
772 defm RELEASE_OR : RELEASE_BINOP_MI<or>;
773 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>;
774 // Note: we don't deal with sub, because substractions of constants are
775 // optimized into additions before this code can run
777 // Same as above, but for floating-point.
778 // FIXME: imm version.
779 // FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
780 // FIXME: This could also handle SIMD operations with *ps and *pd instructions.
781 let usesCustomInserter = 1 in {
782 multiclass RELEASE_FP_BINOP_MI<SDNode op> {
783 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
784 "#BINOP "#NAME#"32mr PSEUDO!",
785 [(atomic_store_32 addr:$dst,
787 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))),
788 FR32:$src))))]>, Requires<[HasSSE1]>;
789 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src),
790 "#BINOP "#NAME#"64mr PSEUDO!",
791 [(atomic_store_64 addr:$dst,
793 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))),
794 FR64:$src))))]>, Requires<[HasSSE2]>;
796 defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>;
797 // FIXME: Add fsub, fmul, fdiv, ...
800 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
801 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
802 "#UNOP "#NAME#"8m PSEUDO!",
803 [(atomic_store_8 addr:$dst, dag8)]>;
804 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
805 "#UNOP "#NAME#"16m PSEUDO!",
806 [(atomic_store_16 addr:$dst, dag16)]>;
807 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
808 "#UNOP "#NAME#"32m PSEUDO!",
809 [(atomic_store_32 addr:$dst, dag32)]>;
810 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
811 "#UNOP "#NAME#"64m PSEUDO!",
812 [(atomic_store_64 addr:$dst, dag64)]>;
815 defm RELEASE_INC : RELEASE_UNOP<
816 (add (atomic_load_8 addr:$dst), (i8 1)),
817 (add (atomic_load_16 addr:$dst), (i16 1)),
818 (add (atomic_load_32 addr:$dst), (i32 1)),
819 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>;
820 defm RELEASE_DEC : RELEASE_UNOP<
821 (add (atomic_load_8 addr:$dst), (i8 -1)),
822 (add (atomic_load_16 addr:$dst), (i16 -1)),
823 (add (atomic_load_32 addr:$dst), (i32 -1)),
824 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>;
826 TODO: These don't work because the type inference of TableGen fails.
827 TODO: find a way to fix it.
828 defm RELEASE_NEG : RELEASE_UNOP<
829 (ineg (atomic_load_8 addr:$dst)),
830 (ineg (atomic_load_16 addr:$dst)),
831 (ineg (atomic_load_32 addr:$dst)),
832 (ineg (atomic_load_64 addr:$dst))>;
833 defm RELEASE_NOT : RELEASE_UNOP<
834 (not (atomic_load_8 addr:$dst)),
835 (not (atomic_load_16 addr:$dst)),
836 (not (atomic_load_32 addr:$dst)),
837 (not (atomic_load_64 addr:$dst))>;
840 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
841 "#RELEASE_MOV8mi PSEUDO!",
842 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
843 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
844 "#RELEASE_MOV16mi PSEUDO!",
845 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
846 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
847 "#RELEASE_MOV32mi PSEUDO!",
848 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
849 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
850 "#RELEASE_MOV64mi32 PSEUDO!",
851 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
853 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
854 "#RELEASE_MOV8mr PSEUDO!",
855 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
856 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
857 "#RELEASE_MOV16mr PSEUDO!",
858 [(atomic_store_16 addr:$dst, GR16:$src)]>;
859 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
860 "#RELEASE_MOV32mr PSEUDO!",
861 [(atomic_store_32 addr:$dst, GR32:$src)]>;
862 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
863 "#RELEASE_MOV64mr PSEUDO!",
864 [(atomic_store_64 addr:$dst, GR64:$src)]>;
866 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
867 "#ACQUIRE_MOV8rm PSEUDO!",
868 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
869 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
870 "#ACQUIRE_MOV16rm PSEUDO!",
871 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
872 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
873 "#ACQUIRE_MOV32rm PSEUDO!",
874 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
875 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
876 "#ACQUIRE_MOV64rm PSEUDO!",
877 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
879 //===----------------------------------------------------------------------===//
880 // DAG Pattern Matching Rules
881 //===----------------------------------------------------------------------===//
883 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
884 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
885 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
886 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
887 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
888 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
889 def : Pat<(i32 (X86Wrapper mcsym:$dst)), (MOV32ri mcsym:$dst)>;
890 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
892 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
893 (ADD32ri GR32:$src1, tconstpool:$src2)>;
894 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
895 (ADD32ri GR32:$src1, tjumptable:$src2)>;
896 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
897 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
898 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
899 (ADD32ri GR32:$src1, texternalsym:$src2)>;
900 def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)),
901 (ADD32ri GR32:$src1, mcsym:$src2)>;
902 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
903 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
905 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
906 (MOV32mi addr:$dst, tglobaladdr:$src)>;
907 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
908 (MOV32mi addr:$dst, texternalsym:$src)>;
909 def : Pat<(store (i32 (X86Wrapper mcsym:$src)), addr:$dst),
910 (MOV32mi addr:$dst, mcsym:$src)>;
911 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
912 (MOV32mi addr:$dst, tblockaddress:$src)>;
914 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
915 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
916 // 'movabs' predicate should handle this sort of thing.
917 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
918 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
919 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
920 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
921 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
922 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
923 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
924 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
925 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
926 (MOV64ri mcsym:$dst)>, Requires<[FarData]>;
927 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
928 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
930 // In kernel code model, we can get the address of a label
931 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
932 // the MOV64ri32 should accept these.
933 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
934 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
935 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
936 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
937 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
938 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
939 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
940 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
941 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
942 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;
943 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
944 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
946 // If we have small model and -static mode, it is safe to store global addresses
947 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
948 // for MOV64mi32 should handle this sort of thing.
949 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
950 (MOV64mi32 addr:$dst, tconstpool:$src)>,
951 Requires<[NearData, IsStatic]>;
952 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
953 (MOV64mi32 addr:$dst, tjumptable:$src)>,
954 Requires<[NearData, IsStatic]>;
955 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
956 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
957 Requires<[NearData, IsStatic]>;
958 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
959 (MOV64mi32 addr:$dst, texternalsym:$src)>,
960 Requires<[NearData, IsStatic]>;
961 def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),
962 (MOV64mi32 addr:$dst, mcsym:$src)>,
963 Requires<[NearData, IsStatic]>;
964 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
965 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
966 Requires<[NearData, IsStatic]>;
968 def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;
969 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
973 // tls has some funny stuff here...
974 // This corresponds to movabs $foo@tpoff, %rax
975 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
976 (MOV64ri32 tglobaltlsaddr :$dst)>;
977 // This corresponds to add $foo@tpoff, %rax
978 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
979 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
982 // Direct PC relative function call for small code model. 32-bit displacement
983 // sign extended to 64-bit.
984 def : Pat<(X86call (i64 tglobaladdr:$dst)),
985 (CALL64pcrel32 tglobaladdr:$dst)>;
986 def : Pat<(X86call (i64 texternalsym:$dst)),
987 (CALL64pcrel32 texternalsym:$dst)>;
989 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
990 // can never use callee-saved registers. That is the purpose of the GR64_TC
993 // The only volatile register that is never used by the calling convention is
994 // %r11. This happens when calling a vararg function with 6 arguments.
996 // Match an X86tcret that uses less than 7 volatile registers.
997 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
998 (X86tcret node:$ptr, node:$off), [{
999 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1000 unsigned NumRegs = 0;
1001 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1002 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1007 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1008 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1009 Requires<[Not64BitMode]>;
1011 // FIXME: This is disabled for 32-bit PIC mode because the global base
1012 // register which is part of the address mode may be assigned a
1013 // callee-saved register.
1014 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1015 (TCRETURNmi addr:$dst, imm:$off)>,
1016 Requires<[Not64BitMode, IsNotPIC]>;
1018 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1019 (TCRETURNdi tglobaladdr:$dst, imm:$off)>,
1020 Requires<[NotLP64]>;
1022 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1023 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1024 Requires<[NotLP64]>;
1026 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1027 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1028 Requires<[In64BitMode]>;
1030 // Don't fold loads into X86tcret requiring more than 6 regs.
1031 // There wouldn't be enough scratch registers for base+index.
1032 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1033 (TCRETURNmi64 addr:$dst, imm:$off)>,
1034 Requires<[In64BitMode]>;
1036 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1037 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1040 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1041 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1044 // Normal calls, with various flavors of addresses.
1045 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1046 (CALLpcrel32 tglobaladdr:$dst)>;
1047 def : Pat<(X86call (i32 texternalsym:$dst)),
1048 (CALLpcrel32 texternalsym:$dst)>;
1049 def : Pat<(X86call (i32 imm:$dst)),
1050 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1054 // TEST R,R is smaller than CMP R,0
1055 def : Pat<(X86cmp GR8:$src1, 0),
1056 (TEST8rr GR8:$src1, GR8:$src1)>;
1057 def : Pat<(X86cmp GR16:$src1, 0),
1058 (TEST16rr GR16:$src1, GR16:$src1)>;
1059 def : Pat<(X86cmp GR32:$src1, 0),
1060 (TEST32rr GR32:$src1, GR32:$src1)>;
1061 def : Pat<(X86cmp GR64:$src1, 0),
1062 (TEST64rr GR64:$src1, GR64:$src1)>;
1064 // Conditional moves with folded loads with operands swapped and conditions
1066 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1067 Instruction Inst64> {
1068 let Predicates = [HasCMov] in {
1069 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1070 (Inst16 GR16:$src2, addr:$src1)>;
1071 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1072 (Inst32 GR32:$src2, addr:$src1)>;
1073 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1074 (Inst64 GR64:$src2, addr:$src1)>;
1078 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1079 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1080 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1081 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1082 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1083 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1084 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1085 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1086 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1087 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1088 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1089 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1090 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1091 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1092 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1093 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1095 // zextload bool -> zextload byte
1096 def : Pat<(zextloadi8i1 addr:$src), (AND8ri (MOV8rm addr:$src), (i8 1))>;
1097 def : Pat<(zextloadi16i1 addr:$src), (AND16ri8 (MOVZX16rm8 addr:$src), (i16 1))>;
1098 def : Pat<(zextloadi32i1 addr:$src), (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1))>;
1099 def : Pat<(zextloadi64i1 addr:$src),
1100 (SUBREG_TO_REG (i64 0),
1101 (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), sub_32bit)>;
1103 // extload bool -> extload byte
1104 // When extloading from 16-bit and smaller memory locations into 64-bit
1105 // registers, use zero-extending loads so that the entire 64-bit register is
1106 // defined, avoiding partial-register updates.
1108 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1109 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1110 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1111 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1112 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1113 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1115 // For other extloads, use subregs, since the high contents of the register are
1116 // defined after an extload.
1117 def : Pat<(extloadi64i1 addr:$src),
1118 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1119 def : Pat<(extloadi64i8 addr:$src),
1120 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1121 def : Pat<(extloadi64i16 addr:$src),
1122 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1123 def : Pat<(extloadi64i32 addr:$src),
1124 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1126 // anyext. Define these to do an explicit zero-extend to
1127 // avoid partial-register updates.
1128 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1129 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1130 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1132 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1133 def : Pat<(i32 (anyext GR16:$src)),
1134 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1136 def : Pat<(i64 (anyext GR8 :$src)),
1137 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1138 def : Pat<(i64 (anyext GR16:$src)),
1139 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1140 def : Pat<(i64 (anyext GR32:$src)),
1141 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1144 // Any instruction that defines a 32-bit result leaves the high half of the
1145 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1146 // be copying from a truncate. And x86's cmov doesn't do anything if the
1147 // condition is false. But any other 32-bit operation will zero-extend
1149 def def32 : PatLeaf<(i32 GR32:$src), [{
1150 return N->getOpcode() != ISD::TRUNCATE &&
1151 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1152 N->getOpcode() != ISD::CopyFromReg &&
1153 N->getOpcode() != ISD::AssertSext &&
1154 N->getOpcode() != X86ISD::CMOV;
1157 // In the case of a 32-bit def that is known to implicitly zero-extend,
1158 // we can use a SUBREG_TO_REG.
1159 def : Pat<(i64 (zext def32:$src)),
1160 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1162 //===----------------------------------------------------------------------===//
1163 // Pattern match OR as ADD
1164 //===----------------------------------------------------------------------===//
1166 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1167 // 3-addressified into an LEA instruction to avoid copies. However, we also
1168 // want to finally emit these instructions as an or at the end of the code
1169 // generator to make the generated code easier to read. To do this, we select
1170 // into "disjoint bits" pseudo ops.
1172 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1173 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1174 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1175 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1177 APInt KnownZero0, KnownOne0;
1178 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1179 APInt KnownZero1, KnownOne1;
1180 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1181 return (~KnownZero0 & ~KnownZero1) == 0;
1185 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1186 // Try this before the selecting to OR.
1187 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1189 let isConvertibleToThreeAddress = 1,
1190 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1191 let isCommutable = 1 in {
1192 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1193 "", // orw/addw REG, REG
1194 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1195 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1196 "", // orl/addl REG, REG
1197 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1198 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1199 "", // orq/addq REG, REG
1200 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1203 // NOTE: These are order specific, we want the ri8 forms to be listed
1204 // first so that they are slightly preferred to the ri forms.
1206 def ADD16ri8_DB : I<0, Pseudo,
1207 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1208 "", // orw/addw REG, imm8
1209 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1210 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1211 "", // orw/addw REG, imm
1212 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1214 def ADD32ri8_DB : I<0, Pseudo,
1215 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1216 "", // orl/addl REG, imm8
1217 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1218 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1219 "", // orl/addl REG, imm
1220 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1223 def ADD64ri8_DB : I<0, Pseudo,
1224 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1225 "", // orq/addq REG, imm8
1226 [(set GR64:$dst, (or_is_add GR64:$src1,
1227 i64immSExt8:$src2))]>;
1228 def ADD64ri32_DB : I<0, Pseudo,
1229 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1230 "", // orq/addq REG, imm
1231 [(set GR64:$dst, (or_is_add GR64:$src1,
1232 i64immSExt32:$src2))]>;
1234 } // AddedComplexity, SchedRW
1237 //===----------------------------------------------------------------------===//
1239 //===----------------------------------------------------------------------===//
1241 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1242 // +128 doesn't, so in this special case use a sub instead of an add.
1243 def : Pat<(add GR16:$src1, 128),
1244 (SUB16ri8 GR16:$src1, -128)>;
1245 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1246 (SUB16mi8 addr:$dst, -128)>;
1248 def : Pat<(add GR32:$src1, 128),
1249 (SUB32ri8 GR32:$src1, -128)>;
1250 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1251 (SUB32mi8 addr:$dst, -128)>;
1253 def : Pat<(add GR64:$src1, 128),
1254 (SUB64ri8 GR64:$src1, -128)>;
1255 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1256 (SUB64mi8 addr:$dst, -128)>;
1258 // The same trick applies for 32-bit immediate fields in 64-bit
1260 def : Pat<(add GR64:$src1, 0x0000000080000000),
1261 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1262 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1263 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1265 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1266 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1267 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1268 // represented with a sign extension of a 8 bit constant, use that.
1269 // This can also reduce instruction size by eliminating the need for the REX
1272 // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.
1273 let AddedComplexity = 1 in {
1274 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1278 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1279 (i32 (GetLo8XForm imm:$imm))),
1282 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1286 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1287 (i32 (GetLo32XForm imm:$imm))),
1289 } // AddedComplexity = 1
1292 // AddedComplexity is needed due to the increased complexity on the
1293 // i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all
1294 // the MOVZX patterns keeps thems together in DAGIsel tables.
1295 let AddedComplexity = 1 in {
1296 // r & (2^16-1) ==> movz
1297 def : Pat<(and GR32:$src1, 0xffff),
1298 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1299 // r & (2^8-1) ==> movz
1300 def : Pat<(and GR32:$src1, 0xff),
1301 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1304 Requires<[Not64BitMode]>;
1305 // r & (2^8-1) ==> movz
1306 def : Pat<(and GR16:$src1, 0xff),
1307 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1308 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1310 Requires<[Not64BitMode]>;
1312 // r & (2^32-1) ==> movz
1313 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1314 (SUBREG_TO_REG (i64 0),
1315 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1317 // r & (2^16-1) ==> movz
1318 let AddedComplexity = 1 in // Give priority over i64immZExt32.
1319 def : Pat<(and GR64:$src, 0xffff),
1320 (SUBREG_TO_REG (i64 0),
1321 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1323 // r & (2^8-1) ==> movz
1324 def : Pat<(and GR64:$src, 0xff),
1325 (SUBREG_TO_REG (i64 0),
1326 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1328 // r & (2^8-1) ==> movz
1329 def : Pat<(and GR32:$src1, 0xff),
1330 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1331 Requires<[In64BitMode]>;
1332 // r & (2^8-1) ==> movz
1333 def : Pat<(and GR16:$src1, 0xff),
1334 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1335 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1336 Requires<[In64BitMode]>;
1337 } // AddedComplexity = 1
1340 // sext_inreg patterns
1341 def : Pat<(sext_inreg GR32:$src, i16),
1342 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1343 def : Pat<(sext_inreg GR32:$src, i8),
1344 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1347 Requires<[Not64BitMode]>;
1349 def : Pat<(sext_inreg GR16:$src, i8),
1350 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1351 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1353 Requires<[Not64BitMode]>;
1355 def : Pat<(sext_inreg GR64:$src, i32),
1356 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1357 def : Pat<(sext_inreg GR64:$src, i16),
1358 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1359 def : Pat<(sext_inreg GR64:$src, i8),
1360 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1361 def : Pat<(sext_inreg GR32:$src, i8),
1362 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1363 Requires<[In64BitMode]>;
1364 def : Pat<(sext_inreg GR16:$src, i8),
1365 (EXTRACT_SUBREG (MOVSX32rr8
1366 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1367 Requires<[In64BitMode]>;
1369 // sext, sext_load, zext, zext_load
1370 def: Pat<(i16 (sext GR8:$src)),
1371 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1372 def: Pat<(sextloadi16i8 addr:$src),
1373 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1374 def: Pat<(i16 (zext GR8:$src)),
1375 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1376 def: Pat<(zextloadi16i8 addr:$src),
1377 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1380 def : Pat<(i16 (trunc GR32:$src)),
1381 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1382 def : Pat<(i8 (trunc GR32:$src)),
1383 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1385 Requires<[Not64BitMode]>;
1386 def : Pat<(i8 (trunc GR16:$src)),
1387 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1389 Requires<[Not64BitMode]>;
1390 def : Pat<(i32 (trunc GR64:$src)),
1391 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1392 def : Pat<(i16 (trunc GR64:$src)),
1393 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1394 def : Pat<(i8 (trunc GR64:$src)),
1395 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1396 def : Pat<(i8 (trunc GR32:$src)),
1397 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1398 Requires<[In64BitMode]>;
1399 def : Pat<(i8 (trunc GR16:$src)),
1400 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1401 Requires<[In64BitMode]>;
1403 // h-register tricks
1404 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1405 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1407 Requires<[Not64BitMode]>;
1408 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1409 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1411 Requires<[Not64BitMode]>;
1412 def : Pat<(srl GR16:$src, (i8 8)),
1415 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1418 Requires<[Not64BitMode]>;
1419 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1420 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1423 Requires<[Not64BitMode]>;
1424 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1425 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1428 Requires<[Not64BitMode]>;
1429 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1430 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1433 Requires<[Not64BitMode]>;
1434 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1435 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1438 Requires<[Not64BitMode]>;
1440 // h-register tricks.
1441 // For now, be conservative on x86-64 and use an h-register extract only if the
1442 // value is immediately zero-extended or stored, which are somewhat common
1443 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1444 // from being allocated in the same instruction as the h register, as there's
1445 // currently no way to describe this requirement to the register allocator.
1447 // h-register extract and zero-extend.
1448 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1452 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1455 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1457 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1459 Requires<[In64BitMode]>;
1460 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1461 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1464 Requires<[In64BitMode]>;
1465 def : Pat<(srl GR16:$src, (i8 8)),
1468 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1471 Requires<[In64BitMode]>;
1472 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1474 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1476 Requires<[In64BitMode]>;
1477 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1479 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1481 Requires<[In64BitMode]>;
1482 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1486 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1489 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1493 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1497 // h-register extract and store.
1498 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1501 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1503 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1506 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1508 Requires<[In64BitMode]>;
1509 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1512 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1514 Requires<[In64BitMode]>;
1517 // (shl x, 1) ==> (add x, x)
1518 // Note that if x is undef (immediate or otherwise), we could theoretically
1519 // end up with the two uses of x getting different values, producing a result
1520 // where the least significant bit is not 0. However, the probability of this
1521 // happening is considered low enough that this is officially not a
1523 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1524 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1525 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1526 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1528 // Helper imms that check if a mask doesn't change significant shift bits.
1529 def immShift32 : ImmLeaf<i8, [{
1530 return countTrailingOnes<uint64_t>(Imm) >= 5;
1532 def immShift64 : ImmLeaf<i8, [{
1533 return countTrailingOnes<uint64_t>(Imm) >= 6;
1536 // Shift amount is implicitly masked.
1537 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1538 // (shift x (and y, 31)) ==> (shift x, y)
1539 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1540 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1541 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1542 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1543 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1544 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1545 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1546 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1547 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1548 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1549 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1550 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1552 // (shift x (and y, 63)) ==> (shift x, y)
1553 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1554 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1555 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1556 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1559 defm : MaskedShiftAmountPats<shl, "SHL">;
1560 defm : MaskedShiftAmountPats<srl, "SHR">;
1561 defm : MaskedShiftAmountPats<sra, "SAR">;
1562 defm : MaskedShiftAmountPats<rotl, "ROL">;
1563 defm : MaskedShiftAmountPats<rotr, "ROR">;
1565 // (anyext (setcc_carry)) -> (setcc_carry)
1566 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1568 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1570 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1576 //===----------------------------------------------------------------------===//
1577 // EFLAGS-defining Patterns
1578 //===----------------------------------------------------------------------===//
1581 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1582 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1583 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1586 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1587 (ADD8rm GR8:$src1, addr:$src2)>;
1588 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1589 (ADD16rm GR16:$src1, addr:$src2)>;
1590 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1591 (ADD32rm GR32:$src1, addr:$src2)>;
1594 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1595 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1596 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1597 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1598 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1599 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1600 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1603 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1604 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1605 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1608 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1609 (SUB8rm GR8:$src1, addr:$src2)>;
1610 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1611 (SUB16rm GR16:$src1, addr:$src2)>;
1612 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1613 (SUB32rm GR32:$src1, addr:$src2)>;
1616 def : Pat<(sub GR8:$src1, imm:$src2),
1617 (SUB8ri GR8:$src1, imm:$src2)>;
1618 def : Pat<(sub GR16:$src1, imm:$src2),
1619 (SUB16ri GR16:$src1, imm:$src2)>;
1620 def : Pat<(sub GR32:$src1, imm:$src2),
1621 (SUB32ri GR32:$src1, imm:$src2)>;
1622 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1623 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1624 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1625 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1628 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1629 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1630 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1631 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1634 def : Pat<(mul GR16:$src1, GR16:$src2),
1635 (IMUL16rr GR16:$src1, GR16:$src2)>;
1636 def : Pat<(mul GR32:$src1, GR32:$src2),
1637 (IMUL32rr GR32:$src1, GR32:$src2)>;
1640 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1641 (IMUL16rm GR16:$src1, addr:$src2)>;
1642 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1643 (IMUL32rm GR32:$src1, addr:$src2)>;
1646 def : Pat<(mul GR16:$src1, imm:$src2),
1647 (IMUL16rri GR16:$src1, imm:$src2)>;
1648 def : Pat<(mul GR32:$src1, imm:$src2),
1649 (IMUL32rri GR32:$src1, imm:$src2)>;
1650 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1651 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1652 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1653 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1655 // reg = mul mem, imm
1656 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1657 (IMUL16rmi addr:$src1, imm:$src2)>;
1658 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1659 (IMUL32rmi addr:$src1, imm:$src2)>;
1660 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1661 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1662 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1663 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1665 // Patterns for nodes that do not produce flags, for instructions that do.
1668 def : Pat<(add GR64:$src1, GR64:$src2),
1669 (ADD64rr GR64:$src1, GR64:$src2)>;
1670 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1671 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1672 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1673 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1674 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1675 (ADD64rm GR64:$src1, addr:$src2)>;
1678 def : Pat<(sub GR64:$src1, GR64:$src2),
1679 (SUB64rr GR64:$src1, GR64:$src2)>;
1680 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1681 (SUB64rm GR64:$src1, addr:$src2)>;
1682 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1683 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1684 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1685 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1688 def : Pat<(mul GR64:$src1, GR64:$src2),
1689 (IMUL64rr GR64:$src1, GR64:$src2)>;
1690 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1691 (IMUL64rm GR64:$src1, addr:$src2)>;
1692 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1693 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1694 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1695 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1696 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1697 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1698 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1699 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1701 // Increment/Decrement reg.
1702 // Do not make INC/DEC if it is slow
1703 let Predicates = [NotSlowIncDec] in {
1704 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
1705 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
1706 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
1707 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1708 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
1709 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
1710 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
1711 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1715 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1716 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1717 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1718 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1721 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1722 (OR8rm GR8:$src1, addr:$src2)>;
1723 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1724 (OR16rm GR16:$src1, addr:$src2)>;
1725 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1726 (OR32rm GR32:$src1, addr:$src2)>;
1727 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1728 (OR64rm GR64:$src1, addr:$src2)>;
1731 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1732 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1733 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1734 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1735 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1736 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1737 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1738 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1739 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1740 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1741 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1744 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1745 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1746 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1747 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1750 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1751 (XOR8rm GR8:$src1, addr:$src2)>;
1752 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1753 (XOR16rm GR16:$src1, addr:$src2)>;
1754 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1755 (XOR32rm GR32:$src1, addr:$src2)>;
1756 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1757 (XOR64rm GR64:$src1, addr:$src2)>;
1760 def : Pat<(xor GR8:$src1, imm:$src2),
1761 (XOR8ri GR8:$src1, imm:$src2)>;
1762 def : Pat<(xor GR16:$src1, imm:$src2),
1763 (XOR16ri GR16:$src1, imm:$src2)>;
1764 def : Pat<(xor GR32:$src1, imm:$src2),
1765 (XOR32ri GR32:$src1, imm:$src2)>;
1766 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1767 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1768 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1769 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1770 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1771 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1772 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1773 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1776 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1777 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1778 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1779 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1782 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1783 (AND8rm GR8:$src1, addr:$src2)>;
1784 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1785 (AND16rm GR16:$src1, addr:$src2)>;
1786 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1787 (AND32rm GR32:$src1, addr:$src2)>;
1788 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1789 (AND64rm GR64:$src1, addr:$src2)>;
1792 def : Pat<(and GR8:$src1, imm:$src2),
1793 (AND8ri GR8:$src1, imm:$src2)>;
1794 def : Pat<(and GR16:$src1, imm:$src2),
1795 (AND16ri GR16:$src1, imm:$src2)>;
1796 def : Pat<(and GR32:$src1, imm:$src2),
1797 (AND32ri GR32:$src1, imm:$src2)>;
1798 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1799 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1800 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1801 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1802 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1803 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1804 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1805 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1807 // Bit scan instruction patterns to match explicit zero-undef behavior.
1808 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1809 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1810 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1811 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1812 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1813 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1815 // When HasMOVBE is enabled it is possible to get a non-legalized
1816 // register-register 16 bit bswap. This maps it to a ROL instruction.
1817 let Predicates = [HasMOVBE] in {
1818 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;