1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[Not64BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[Not64BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1, Defs = [EFLAGS] in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
87 // The VAARG_64 pseudo-instruction takes the address of the va_list,
88 // and places the address of the next argument into a register.
89 let Defs = [EFLAGS] in
90 def VAARG_64 : I<0, Pseudo,
92 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
93 "#VAARG_64 $dst, $ap, $size, $mode, $align",
95 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
98 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
99 // targets. These calls are needed to probe the stack when allocating more than
100 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
101 // ensure that the guard pages used by the OS virtual memory manager are
102 // allocated in correct sequence.
103 // The main point of having separate instruction are extra unmodelled effects
104 // (compared to ordinary calls) like stack pointer change.
106 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
107 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
108 "# dynamic stack allocation",
111 // When using segmented stacks these are lowered into instructions which first
112 // check if the current stacklet has enough free memory. If it does, memory is
113 // allocated by bumping the stack pointer. Otherwise memory is allocated from
116 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
117 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
118 "# variable sized alloca for segmented stacks",
120 (X86SegAlloca GR32:$size))]>,
121 Requires<[Not64BitMode]>;
123 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
124 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
125 "# variable sized alloca for segmented stacks",
127 (X86SegAlloca GR64:$size))]>,
128 Requires<[In64BitMode]>;
131 // The MSVC runtime contains an _ftol2 routine for converting floating-point
132 // to integer values. It has a strange calling convention: the input is
133 // popped from the x87 stack, and the return value is given in EDX:EAX. ECX is
134 // used as a temporary register. No other registers (aside from flags) are
136 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
137 // variant is unnecessary.
139 let Defs = [EAX, EDX, ECX, EFLAGS], FPForm = SpecialFP in {
140 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
142 [(X86WinFTOL RFP32:$src)]>,
143 Requires<[Not64BitMode]>;
145 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
147 [(X86WinFTOL RFP64:$src)]>,
148 Requires<[Not64BitMode]>;
151 //===----------------------------------------------------------------------===//
152 // EH Pseudo Instructions
154 let SchedRW = [WriteSystem] in {
155 let isTerminator = 1, isReturn = 1, isBarrier = 1,
156 hasCtrlDep = 1, isCodeGenOnly = 1 in {
157 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
158 "ret\t#eh_return, addr: $addr",
159 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
163 let isTerminator = 1, isReturn = 1, isBarrier = 1,
164 hasCtrlDep = 1, isCodeGenOnly = 1 in {
165 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
166 "ret\t#eh_return, addr: $addr",
167 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
171 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
172 usesCustomInserter = 1 in {
173 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
175 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
176 Requires<[Not64BitMode]>;
177 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
179 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
180 Requires<[In64BitMode]>;
181 let isTerminator = 1 in {
182 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
183 "#EH_SJLJ_LONGJMP32",
184 [(X86eh_sjlj_longjmp addr:$buf)]>,
185 Requires<[Not64BitMode]>;
186 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
187 "#EH_SJLJ_LONGJMP64",
188 [(X86eh_sjlj_longjmp addr:$buf)]>,
189 Requires<[In64BitMode]>;
194 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
195 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
196 "#EH_SjLj_Setup\t$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // Pseudo instructions used by unwind info.
202 let isPseudo = 1 in {
203 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
204 "#SEH_PushReg $reg", []>;
205 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
206 "#SEH_SaveReg $reg, $dst", []>;
207 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
208 "#SEH_SaveXMM $reg, $dst", []>;
209 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
210 "#SEH_StackAlloc $size", []>;
211 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
212 "#SEH_SetFrame $reg, $offset", []>;
213 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
214 "#SEH_PushFrame $mode", []>;
215 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
216 "#SEH_EndPrologue", []>;
217 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
218 "#SEH_Epilogue", []>;
221 //===----------------------------------------------------------------------===//
222 // Pseudo instructions used by segmented stacks.
225 // This is lowered into a RET instruction by MCInstLower. We need
226 // this so that we don't have to have a MachineBasicBlock which ends
227 // with a RET and also has successors.
228 let isPseudo = 1 in {
229 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
232 // This instruction is lowered to a RET followed by a MOV. The two
233 // instructions are not generated on a higher level since then the
234 // verifier sees a MachineBasicBlock ending with a non-terminator.
235 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
239 //===----------------------------------------------------------------------===//
240 // Alias Instructions
241 //===----------------------------------------------------------------------===//
243 // Alias instruction mapping movr0 to xor.
244 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
245 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
247 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
248 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
250 // Other widths can also make use of the 32-bit xor, which may have a smaller
251 // encoding and avoid partial register updates.
252 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
253 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
254 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
255 let AddedComplexity = 20;
258 // Materialize i64 constant where top 32-bits are zero. This could theoretically
259 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
260 // that would make it more difficult to rematerialize.
261 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
262 isCodeGenOnly = 1, neverHasSideEffects = 1 in
263 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
264 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
266 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
267 // actually the zero-extension of a 32-bit constant, and for labels in the
268 // x86-64 small code model.
269 def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>;
271 let AddedComplexity = 1 in
272 def : Pat<(i64 mov64imm32:$src),
273 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
275 // Use sbb to materialize carry bit.
276 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
277 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
278 // However, Pat<> can't replicate the destination reg into the inputs of the
280 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
281 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
282 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
283 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
284 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
285 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
286 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
287 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
291 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
293 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
295 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
298 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
300 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
302 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
305 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
306 // will be eliminated and that the sbb can be extended up to a wider type. When
307 // this happens, it is great. However, if we are left with an 8-bit sbb and an
308 // and, we might as well just match it as a setb.
309 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
312 // (add OP, SETB) -> (adc OP, 0)
313 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
314 (ADC8ri GR8:$op, 0)>;
315 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
316 (ADC32ri8 GR32:$op, 0)>;
317 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
318 (ADC64ri8 GR64:$op, 0)>;
320 // (sub OP, SETB) -> (sbb OP, 0)
321 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
322 (SBB8ri GR8:$op, 0)>;
323 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
324 (SBB32ri8 GR32:$op, 0)>;
325 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
326 (SBB64ri8 GR64:$op, 0)>;
328 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
329 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
330 (ADC8ri GR8:$op, 0)>;
331 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
332 (ADC32ri8 GR32:$op, 0)>;
333 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
334 (ADC64ri8 GR64:$op, 0)>;
336 //===----------------------------------------------------------------------===//
337 // String Pseudo Instructions
339 let SchedRW = [WriteMicrocoded] in {
340 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
341 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
342 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
343 Requires<[Not64BitMode]>;
344 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
345 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
346 Requires<[Not64BitMode]>;
347 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
348 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
349 Requires<[Not64BitMode]>;
352 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
353 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
354 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
355 Requires<[In64BitMode]>;
356 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
357 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
358 Requires<[In64BitMode]>;
359 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
360 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
361 Requires<[In64BitMode]>;
362 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
363 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
364 Requires<[In64BitMode]>;
367 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
368 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
369 let Uses = [AL,ECX,EDI] in
370 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
371 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
372 Requires<[Not64BitMode]>;
373 let Uses = [AX,ECX,EDI] in
374 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
375 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
376 Requires<[Not64BitMode]>;
377 let Uses = [EAX,ECX,EDI] in
378 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
379 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
380 Requires<[Not64BitMode]>;
383 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
384 let Uses = [AL,RCX,RDI] in
385 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
386 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
387 Requires<[In64BitMode]>;
388 let Uses = [AX,RCX,RDI] in
389 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
390 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
391 Requires<[In64BitMode]>;
392 let Uses = [RAX,RCX,RDI] in
393 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
394 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
395 Requires<[In64BitMode]>;
397 let Uses = [RAX,RCX,RDI] in
398 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
399 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
400 Requires<[In64BitMode]>;
404 //===----------------------------------------------------------------------===//
405 // Thread Local Storage Instructions
409 // All calls clobber the non-callee saved registers. ESP is marked as
410 // a use to prevent stack-pointer assignments that appear immediately
411 // before calls from potentially appearing dead.
412 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
413 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
414 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
415 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
416 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
418 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
420 [(X86tlsaddr tls32addr:$sym)]>,
421 Requires<[Not64BitMode]>;
422 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
424 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
425 Requires<[Not64BitMode]>;
428 // All calls clobber the non-callee saved registers. RSP is marked as
429 // a use to prevent stack-pointer assignments that appear immediately
430 // before calls from potentially appearing dead.
431 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
432 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
433 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
434 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
435 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
436 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
438 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
440 [(X86tlsaddr tls64addr:$sym)]>,
441 Requires<[In64BitMode]>;
442 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
444 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
445 Requires<[In64BitMode]>;
448 // Darwin TLS Support
449 // For i386, the address of the thunk is passed on the stack, on return the
450 // address of the variable is in %eax. %ecx is trashed during the function
451 // call. All other registers are preserved.
452 let Defs = [EAX, ECX, EFLAGS],
454 usesCustomInserter = 1 in
455 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
457 [(X86TLSCall addr:$sym)]>,
458 Requires<[Not64BitMode]>;
460 // For x86_64, the address of the thunk is passed in %rdi, on return
461 // the address of the variable is in %rax. All other registers are preserved.
462 let Defs = [RAX, EFLAGS],
464 usesCustomInserter = 1 in
465 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
467 [(X86TLSCall addr:$sym)]>,
468 Requires<[In64BitMode]>;
471 //===----------------------------------------------------------------------===//
472 // Conditional Move Pseudo Instructions
474 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
475 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
476 // however that requires promoting the operands, and can induce additional
477 // i8 register pressure.
478 let usesCustomInserter = 1, Uses = [EFLAGS] in {
479 def CMOV_GR8 : I<0, Pseudo,
480 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
482 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
483 imm:$cond, EFLAGS))]>;
485 let Predicates = [NoCMov] in {
486 def CMOV_GR32 : I<0, Pseudo,
487 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
488 "#CMOV_GR32* PSEUDO!",
490 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
491 def CMOV_GR16 : I<0, Pseudo,
492 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
493 "#CMOV_GR16* PSEUDO!",
495 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
496 } // Predicates = [NoCMov]
498 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
500 let Predicates = [FPStackf32] in
501 def CMOV_RFP32 : I<0, Pseudo,
503 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
504 "#CMOV_RFP32 PSEUDO!",
506 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
508 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
510 let Predicates = [FPStackf64] in
511 def CMOV_RFP64 : I<0, Pseudo,
513 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
514 "#CMOV_RFP64 PSEUDO!",
516 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
518 def CMOV_RFP80 : I<0, Pseudo,
520 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
521 "#CMOV_RFP80 PSEUDO!",
523 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
525 } // UsesCustomInserter = 1, Uses = [EFLAGS]
528 //===----------------------------------------------------------------------===//
529 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
530 //===----------------------------------------------------------------------===//
532 // FIXME: Use normal instructions and add lock prefix dynamically.
536 // TODO: Get this to fold the constant into the instruction.
537 let isCodeGenOnly = 1, Defs = [EFLAGS] in
538 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
539 "or{l}\t{$zero, $dst|$dst, $zero}",
540 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
541 Sched<[WriteALULd, WriteRMW]>;
543 let hasSideEffects = 1 in
544 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
546 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
548 // RegOpc corresponds to the mr version of the instruction
549 // ImmOpc corresponds to the mi version of the instruction
550 // ImmOpc8 corresponds to the mi8 version of the instruction
551 // ImmMod corresponds to the instruction format of the mi and mi8 versions
552 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
553 Format ImmMod, string mnemonic> {
554 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
555 SchedRW = [WriteALULd, WriteRMW] in {
557 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
558 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
559 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
560 !strconcat(mnemonic, "{b}\t",
561 "{$src2, $dst|$dst, $src2}"),
562 [], IIC_ALU_NONMEM>, LOCK;
563 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
564 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
565 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
566 !strconcat(mnemonic, "{w}\t",
567 "{$src2, $dst|$dst, $src2}"),
568 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
569 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
570 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
571 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
572 !strconcat(mnemonic, "{l}\t",
573 "{$src2, $dst|$dst, $src2}"),
574 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
575 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
576 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
577 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
578 !strconcat(mnemonic, "{q}\t",
579 "{$src2, $dst|$dst, $src2}"),
580 [], IIC_ALU_NONMEM>, LOCK;
582 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
583 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
584 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
585 !strconcat(mnemonic, "{b}\t",
586 "{$src2, $dst|$dst, $src2}"),
587 [], IIC_ALU_MEM>, LOCK;
589 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
590 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
591 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
592 !strconcat(mnemonic, "{w}\t",
593 "{$src2, $dst|$dst, $src2}"),
594 [], IIC_ALU_MEM>, OpSize16, LOCK;
596 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
597 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
598 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
599 !strconcat(mnemonic, "{l}\t",
600 "{$src2, $dst|$dst, $src2}"),
601 [], IIC_ALU_MEM>, OpSize32, LOCK;
603 def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
604 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
605 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
606 !strconcat(mnemonic, "{q}\t",
607 "{$src2, $dst|$dst, $src2}"),
608 [], IIC_ALU_MEM>, LOCK;
610 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
611 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
612 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
613 !strconcat(mnemonic, "{w}\t",
614 "{$src2, $dst|$dst, $src2}"),
615 [], IIC_ALU_MEM>, OpSize16, LOCK;
616 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
617 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
618 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
619 !strconcat(mnemonic, "{l}\t",
620 "{$src2, $dst|$dst, $src2}"),
621 [], IIC_ALU_MEM>, OpSize32, LOCK;
622 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
623 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
624 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
625 !strconcat(mnemonic, "{q}\t",
626 "{$src2, $dst|$dst, $src2}"),
627 [], IIC_ALU_MEM>, LOCK;
633 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
634 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
635 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
636 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
637 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
639 // Optimized codegen when the non-memory output is not used.
640 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
642 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
643 SchedRW = [WriteALULd, WriteRMW] in {
645 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
646 !strconcat(mnemonic, "{b}\t$dst"),
647 [], IIC_UNARY_MEM>, LOCK;
648 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
649 !strconcat(mnemonic, "{w}\t$dst"),
650 [], IIC_UNARY_MEM>, OpSize16, LOCK;
651 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
652 !strconcat(mnemonic, "{l}\t$dst"),
653 [], IIC_UNARY_MEM>, OpSize32, LOCK;
654 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
655 !strconcat(mnemonic, "{q}\t$dst"),
656 [], IIC_UNARY_MEM>, LOCK;
660 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
661 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
663 // Atomic compare and swap.
664 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
665 SDPatternOperator frag, X86MemOperand x86memop,
666 InstrItinClass itin> {
667 let isCodeGenOnly = 1 in {
668 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
669 !strconcat(mnemonic, "\t$ptr"),
670 [(frag addr:$ptr)], itin>, TB, LOCK;
674 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
675 string mnemonic, SDPatternOperator frag,
676 InstrItinClass itin8, InstrItinClass itin> {
677 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
678 let Defs = [AL, EFLAGS], Uses = [AL] in
679 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
680 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
681 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
682 let Defs = [AX, EFLAGS], Uses = [AX] in
683 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
684 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
685 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
686 let Defs = [EAX, EFLAGS], Uses = [EAX] in
687 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
688 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
689 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
690 let Defs = [RAX, EFLAGS], Uses = [RAX] in
691 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
692 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
693 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
697 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
698 SchedRW = [WriteALULd, WriteRMW] in {
699 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
704 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
705 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
706 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
708 IIC_CMPX_LOCK_16B>, REX_W;
711 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
712 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
714 // Atomic exchange and add
715 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
717 InstrItinClass itin8, InstrItinClass itin> {
718 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
719 SchedRW = [WriteALULd, WriteRMW] in {
720 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
721 (ins GR8:$val, i8mem:$ptr),
722 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
724 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
726 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
727 (ins GR16:$val, i16mem:$ptr),
728 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
731 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
733 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
734 (ins GR32:$val, i32mem:$ptr),
735 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
738 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
740 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
741 (ins GR64:$val, i64mem:$ptr),
742 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
745 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
750 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
751 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
754 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
755 "#ACQUIRE_MOV PSEUDO!",
756 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
757 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
758 "#ACQUIRE_MOV PSEUDO!",
759 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
760 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
761 "#ACQUIRE_MOV PSEUDO!",
762 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
763 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
764 "#ACQUIRE_MOV PSEUDO!",
765 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
767 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
768 "#RELEASE_MOV PSEUDO!",
769 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
770 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
771 "#RELEASE_MOV PSEUDO!",
772 [(atomic_store_16 addr:$dst, GR16:$src)]>;
773 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
774 "#RELEASE_MOV PSEUDO!",
775 [(atomic_store_32 addr:$dst, GR32:$src)]>;
776 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
777 "#RELEASE_MOV PSEUDO!",
778 [(atomic_store_64 addr:$dst, GR64:$src)]>;
780 //===----------------------------------------------------------------------===//
781 // Conditional Move Pseudo Instructions.
782 //===----------------------------------------------------------------------===//
785 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
786 // instruction selection into a branch sequence.
787 let Uses = [EFLAGS], usesCustomInserter = 1 in {
788 def CMOV_FR32 : I<0, Pseudo,
789 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
790 "#CMOV_FR32 PSEUDO!",
791 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
793 def CMOV_FR64 : I<0, Pseudo,
794 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
795 "#CMOV_FR64 PSEUDO!",
796 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
798 def CMOV_V4F32 : I<0, Pseudo,
799 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
800 "#CMOV_V4F32 PSEUDO!",
802 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
804 def CMOV_V2F64 : I<0, Pseudo,
805 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
806 "#CMOV_V2F64 PSEUDO!",
808 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
810 def CMOV_V2I64 : I<0, Pseudo,
811 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
812 "#CMOV_V2I64 PSEUDO!",
814 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
816 def CMOV_V8F32 : I<0, Pseudo,
817 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
818 "#CMOV_V8F32 PSEUDO!",
820 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
822 def CMOV_V4F64 : I<0, Pseudo,
823 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
824 "#CMOV_V4F64 PSEUDO!",
826 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
828 def CMOV_V4I64 : I<0, Pseudo,
829 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
830 "#CMOV_V4I64 PSEUDO!",
832 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
834 def CMOV_V8I64 : I<0, Pseudo,
835 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
836 "#CMOV_V8I64 PSEUDO!",
838 (v8i64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
840 def CMOV_V8F64 : I<0, Pseudo,
841 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
842 "#CMOV_V8F64 PSEUDO!",
844 (v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
846 def CMOV_V16F32 : I<0, Pseudo,
847 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
848 "#CMOV_V16F32 PSEUDO!",
850 (v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond,
855 //===----------------------------------------------------------------------===//
856 // DAG Pattern Matching Rules
857 //===----------------------------------------------------------------------===//
859 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
860 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
861 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
862 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
863 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
864 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
865 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
867 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
868 (ADD32ri GR32:$src1, tconstpool:$src2)>;
869 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
870 (ADD32ri GR32:$src1, tjumptable:$src2)>;
871 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
872 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
873 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
874 (ADD32ri GR32:$src1, texternalsym:$src2)>;
875 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
876 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
878 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
879 (MOV32mi addr:$dst, tglobaladdr:$src)>;
880 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
881 (MOV32mi addr:$dst, texternalsym:$src)>;
882 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
883 (MOV32mi addr:$dst, tblockaddress:$src)>;
885 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
886 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
887 // 'movabs' predicate should handle this sort of thing.
888 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
889 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
890 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
891 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
892 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
893 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
894 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
895 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
896 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
897 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
899 // In kernel code model, we can get the address of a label
900 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
901 // the MOV64ri32 should accept these.
902 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
903 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
904 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
905 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
906 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
907 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
908 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
909 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
910 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
911 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
913 // If we have small model and -static mode, it is safe to store global addresses
914 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
915 // for MOV64mi32 should handle this sort of thing.
916 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
917 (MOV64mi32 addr:$dst, tconstpool:$src)>,
918 Requires<[NearData, IsStatic]>;
919 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
920 (MOV64mi32 addr:$dst, tjumptable:$src)>,
921 Requires<[NearData, IsStatic]>;
922 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
923 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
924 Requires<[NearData, IsStatic]>;
925 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
926 (MOV64mi32 addr:$dst, texternalsym:$src)>,
927 Requires<[NearData, IsStatic]>;
928 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
929 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
930 Requires<[NearData, IsStatic]>;
934 // tls has some funny stuff here...
935 // This corresponds to movabs $foo@tpoff, %rax
936 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
937 (MOV64ri32 tglobaltlsaddr :$dst)>;
938 // This corresponds to add $foo@tpoff, %rax
939 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
940 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
943 // Direct PC relative function call for small code model. 32-bit displacement
944 // sign extended to 64-bit.
945 def : Pat<(X86call (i64 tglobaladdr:$dst)),
946 (CALL64pcrel32 tglobaladdr:$dst)>;
947 def : Pat<(X86call (i64 texternalsym:$dst)),
948 (CALL64pcrel32 texternalsym:$dst)>;
950 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
951 // can never use callee-saved registers. That is the purpose of the GR64_TC
954 // The only volatile register that is never used by the calling convention is
955 // %r11. This happens when calling a vararg function with 6 arguments.
957 // Match an X86tcret that uses less than 7 volatile registers.
958 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
959 (X86tcret node:$ptr, node:$off), [{
960 // X86tcret args: (*chain, ptr, imm, regs..., glue)
961 unsigned NumRegs = 0;
962 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
963 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
968 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
969 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
970 Requires<[Not64BitMode]>;
972 // FIXME: This is disabled for 32-bit PIC mode because the global base
973 // register which is part of the address mode may be assigned a
974 // callee-saved register.
975 def : Pat<(X86tcret (load addr:$dst), imm:$off),
976 (TCRETURNmi addr:$dst, imm:$off)>,
977 Requires<[Not64BitMode, IsNotPIC]>;
979 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
980 (TCRETURNdi texternalsym:$dst, imm:$off)>,
981 Requires<[Not64BitMode]>;
983 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
984 (TCRETURNdi texternalsym:$dst, imm:$off)>,
985 Requires<[Not64BitMode]>;
987 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
988 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
989 Requires<[In64BitMode]>;
991 // Don't fold loads into X86tcret requiring more than 6 regs.
992 // There wouldn't be enough scratch registers for base+index.
993 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
994 (TCRETURNmi64 addr:$dst, imm:$off)>,
995 Requires<[In64BitMode]>;
997 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
998 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
999 Requires<[In64BitMode]>;
1001 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1002 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1003 Requires<[In64BitMode]>;
1005 // Normal calls, with various flavors of addresses.
1006 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1007 (CALLpcrel32 tglobaladdr:$dst)>;
1008 def : Pat<(X86call (i32 texternalsym:$dst)),
1009 (CALLpcrel32 texternalsym:$dst)>;
1010 def : Pat<(X86call (i32 imm:$dst)),
1011 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1015 // TEST R,R is smaller than CMP R,0
1016 def : Pat<(X86cmp GR8:$src1, 0),
1017 (TEST8rr GR8:$src1, GR8:$src1)>;
1018 def : Pat<(X86cmp GR16:$src1, 0),
1019 (TEST16rr GR16:$src1, GR16:$src1)>;
1020 def : Pat<(X86cmp GR32:$src1, 0),
1021 (TEST32rr GR32:$src1, GR32:$src1)>;
1022 def : Pat<(X86cmp GR64:$src1, 0),
1023 (TEST64rr GR64:$src1, GR64:$src1)>;
1025 // Conditional moves with folded loads with operands swapped and conditions
1027 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1028 Instruction Inst64> {
1029 let Predicates = [HasCMov] in {
1030 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1031 (Inst16 GR16:$src2, addr:$src1)>;
1032 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1033 (Inst32 GR32:$src2, addr:$src1)>;
1034 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1035 (Inst64 GR64:$src2, addr:$src1)>;
1039 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1040 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1041 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1042 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1043 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1044 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1045 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1046 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1047 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1048 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1049 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1050 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1051 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1052 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1053 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1054 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1056 // zextload bool -> zextload byte
1057 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1058 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1059 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1060 def : Pat<(zextloadi64i1 addr:$src),
1061 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1063 // extload bool -> extload byte
1064 // When extloading from 16-bit and smaller memory locations into 64-bit
1065 // registers, use zero-extending loads so that the entire 64-bit register is
1066 // defined, avoiding partial-register updates.
1068 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1069 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1070 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1071 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1072 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1073 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1075 // For other extloads, use subregs, since the high contents of the register are
1076 // defined after an extload.
1077 def : Pat<(extloadi64i1 addr:$src),
1078 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1079 def : Pat<(extloadi64i8 addr:$src),
1080 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1081 def : Pat<(extloadi64i16 addr:$src),
1082 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1083 def : Pat<(extloadi64i32 addr:$src),
1084 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1086 // anyext. Define these to do an explicit zero-extend to
1087 // avoid partial-register updates.
1088 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1089 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1090 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1092 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1093 def : Pat<(i32 (anyext GR16:$src)),
1094 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1096 def : Pat<(i64 (anyext GR8 :$src)),
1097 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1098 def : Pat<(i64 (anyext GR16:$src)),
1099 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1100 def : Pat<(i64 (anyext GR32:$src)),
1101 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1104 // Any instruction that defines a 32-bit result leaves the high half of the
1105 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1106 // be copying from a truncate. And x86's cmov doesn't do anything if the
1107 // condition is false. But any other 32-bit operation will zero-extend
1109 def def32 : PatLeaf<(i32 GR32:$src), [{
1110 return N->getOpcode() != ISD::TRUNCATE &&
1111 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1112 N->getOpcode() != ISD::CopyFromReg &&
1113 N->getOpcode() != X86ISD::CMOV;
1116 // In the case of a 32-bit def that is known to implicitly zero-extend,
1117 // we can use a SUBREG_TO_REG.
1118 def : Pat<(i64 (zext def32:$src)),
1119 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1121 //===----------------------------------------------------------------------===//
1122 // Pattern match OR as ADD
1123 //===----------------------------------------------------------------------===//
1125 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1126 // 3-addressified into an LEA instruction to avoid copies. However, we also
1127 // want to finally emit these instructions as an or at the end of the code
1128 // generator to make the generated code easier to read. To do this, we select
1129 // into "disjoint bits" pseudo ops.
1131 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1132 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1133 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1134 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1136 APInt KnownZero0, KnownOne0;
1137 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1138 APInt KnownZero1, KnownOne1;
1139 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1140 return (~KnownZero0 & ~KnownZero1) == 0;
1144 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1145 // Try this before the selecting to OR.
1146 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1148 let isConvertibleToThreeAddress = 1,
1149 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1150 let isCommutable = 1 in {
1151 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1152 "", // orw/addw REG, REG
1153 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1154 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1155 "", // orl/addl REG, REG
1156 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1157 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1158 "", // orq/addq REG, REG
1159 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1162 // NOTE: These are order specific, we want the ri8 forms to be listed
1163 // first so that they are slightly preferred to the ri forms.
1165 def ADD16ri8_DB : I<0, Pseudo,
1166 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1167 "", // orw/addw REG, imm8
1168 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1169 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1170 "", // orw/addw REG, imm
1171 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1173 def ADD32ri8_DB : I<0, Pseudo,
1174 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1175 "", // orl/addl REG, imm8
1176 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1177 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1178 "", // orl/addl REG, imm
1179 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1182 def ADD64ri8_DB : I<0, Pseudo,
1183 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1184 "", // orq/addq REG, imm8
1185 [(set GR64:$dst, (or_is_add GR64:$src1,
1186 i64immSExt8:$src2))]>;
1187 def ADD64ri32_DB : I<0, Pseudo,
1188 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1189 "", // orq/addq REG, imm
1190 [(set GR64:$dst, (or_is_add GR64:$src1,
1191 i64immSExt32:$src2))]>;
1193 } // AddedComplexity, SchedRW
1196 //===----------------------------------------------------------------------===//
1198 //===----------------------------------------------------------------------===//
1200 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1201 // +128 doesn't, so in this special case use a sub instead of an add.
1202 def : Pat<(add GR16:$src1, 128),
1203 (SUB16ri8 GR16:$src1, -128)>;
1204 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1205 (SUB16mi8 addr:$dst, -128)>;
1207 def : Pat<(add GR32:$src1, 128),
1208 (SUB32ri8 GR32:$src1, -128)>;
1209 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1210 (SUB32mi8 addr:$dst, -128)>;
1212 def : Pat<(add GR64:$src1, 128),
1213 (SUB64ri8 GR64:$src1, -128)>;
1214 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1215 (SUB64mi8 addr:$dst, -128)>;
1217 // The same trick applies for 32-bit immediate fields in 64-bit
1219 def : Pat<(add GR64:$src1, 0x0000000080000000),
1220 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1221 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1222 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1224 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1225 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1226 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1227 // represented with a sign extension of a 8 bit constant, use that.
1229 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1233 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1234 (i32 (GetLo8XForm imm:$imm))),
1237 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1241 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1242 (i32 (GetLo32XForm imm:$imm))),
1246 // r & (2^16-1) ==> movz
1247 def : Pat<(and GR32:$src1, 0xffff),
1248 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1249 // r & (2^8-1) ==> movz
1250 def : Pat<(and GR32:$src1, 0xff),
1251 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1254 Requires<[Not64BitMode]>;
1255 // r & (2^8-1) ==> movz
1256 def : Pat<(and GR16:$src1, 0xff),
1257 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1258 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1260 Requires<[Not64BitMode]>;
1262 // r & (2^32-1) ==> movz
1263 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1264 (SUBREG_TO_REG (i64 0),
1265 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1267 // r & (2^16-1) ==> movz
1268 def : Pat<(and GR64:$src, 0xffff),
1269 (SUBREG_TO_REG (i64 0),
1270 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1272 // r & (2^8-1) ==> movz
1273 def : Pat<(and GR64:$src, 0xff),
1274 (SUBREG_TO_REG (i64 0),
1275 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1277 // r & (2^8-1) ==> movz
1278 def : Pat<(and GR32:$src1, 0xff),
1279 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1280 Requires<[In64BitMode]>;
1281 // r & (2^8-1) ==> movz
1282 def : Pat<(and GR16:$src1, 0xff),
1283 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1284 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1285 Requires<[In64BitMode]>;
1288 // sext_inreg patterns
1289 def : Pat<(sext_inreg GR32:$src, i16),
1290 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1291 def : Pat<(sext_inreg GR32:$src, i8),
1292 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1295 Requires<[Not64BitMode]>;
1297 def : Pat<(sext_inreg GR16:$src, i8),
1298 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1299 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1301 Requires<[Not64BitMode]>;
1303 def : Pat<(sext_inreg GR64:$src, i32),
1304 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1305 def : Pat<(sext_inreg GR64:$src, i16),
1306 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1307 def : Pat<(sext_inreg GR64:$src, i8),
1308 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1309 def : Pat<(sext_inreg GR32:$src, i8),
1310 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1311 Requires<[In64BitMode]>;
1312 def : Pat<(sext_inreg GR16:$src, i8),
1313 (EXTRACT_SUBREG (MOVSX32rr8
1314 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1315 Requires<[In64BitMode]>;
1317 // sext, sext_load, zext, zext_load
1318 def: Pat<(i16 (sext GR8:$src)),
1319 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1320 def: Pat<(sextloadi16i8 addr:$src),
1321 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1322 def: Pat<(i16 (zext GR8:$src)),
1323 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1324 def: Pat<(zextloadi16i8 addr:$src),
1325 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1328 def : Pat<(i16 (trunc GR32:$src)),
1329 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1330 def : Pat<(i8 (trunc GR32:$src)),
1331 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1333 Requires<[Not64BitMode]>;
1334 def : Pat<(i8 (trunc GR16:$src)),
1335 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1337 Requires<[Not64BitMode]>;
1338 def : Pat<(i32 (trunc GR64:$src)),
1339 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1340 def : Pat<(i16 (trunc GR64:$src)),
1341 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1342 def : Pat<(i8 (trunc GR64:$src)),
1343 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1344 def : Pat<(i8 (trunc GR32:$src)),
1345 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1346 Requires<[In64BitMode]>;
1347 def : Pat<(i8 (trunc GR16:$src)),
1348 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1349 Requires<[In64BitMode]>;
1351 // h-register tricks
1352 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1353 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1355 Requires<[Not64BitMode]>;
1356 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1357 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1359 Requires<[Not64BitMode]>;
1360 def : Pat<(srl GR16:$src, (i8 8)),
1363 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1366 Requires<[Not64BitMode]>;
1367 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1368 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1371 Requires<[Not64BitMode]>;
1372 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1373 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1376 Requires<[Not64BitMode]>;
1377 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1378 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1381 Requires<[Not64BitMode]>;
1382 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1383 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1386 Requires<[Not64BitMode]>;
1388 // h-register tricks.
1389 // For now, be conservative on x86-64 and use an h-register extract only if the
1390 // value is immediately zero-extended or stored, which are somewhat common
1391 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1392 // from being allocated in the same instruction as the h register, as there's
1393 // currently no way to describe this requirement to the register allocator.
1395 // h-register extract and zero-extend.
1396 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1400 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1403 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1405 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1407 Requires<[In64BitMode]>;
1408 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1409 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1412 Requires<[In64BitMode]>;
1413 def : Pat<(srl GR16:$src, (i8 8)),
1416 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1419 Requires<[In64BitMode]>;
1420 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1422 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1424 Requires<[In64BitMode]>;
1425 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1427 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1429 Requires<[In64BitMode]>;
1430 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1434 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1437 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1441 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1445 // h-register extract and store.
1446 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1449 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1451 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1454 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1456 Requires<[In64BitMode]>;
1457 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1460 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1462 Requires<[In64BitMode]>;
1465 // (shl x, 1) ==> (add x, x)
1466 // Note that if x is undef (immediate or otherwise), we could theoretically
1467 // end up with the two uses of x getting different values, producing a result
1468 // where the least significant bit is not 0. However, the probability of this
1469 // happening is considered low enough that this is officially not a
1471 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1472 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1473 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1474 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1476 // Helper imms that check if a mask doesn't change significant shift bits.
1477 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1478 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1480 // Shift amount is implicitly masked.
1481 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1482 // (shift x (and y, 31)) ==> (shift x, y)
1483 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1484 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1485 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1486 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1487 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1488 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1489 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1490 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1491 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1492 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1493 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1494 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1496 // (shift x (and y, 63)) ==> (shift x, y)
1497 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1498 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1499 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1500 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1503 defm : MaskedShiftAmountPats<shl, "SHL">;
1504 defm : MaskedShiftAmountPats<srl, "SHR">;
1505 defm : MaskedShiftAmountPats<sra, "SAR">;
1506 defm : MaskedShiftAmountPats<rotl, "ROL">;
1507 defm : MaskedShiftAmountPats<rotr, "ROR">;
1509 // (anyext (setcc_carry)) -> (setcc_carry)
1510 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1512 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1514 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1520 //===----------------------------------------------------------------------===//
1521 // EFLAGS-defining Patterns
1522 //===----------------------------------------------------------------------===//
1525 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1526 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1527 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1530 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1531 (ADD8rm GR8:$src1, addr:$src2)>;
1532 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1533 (ADD16rm GR16:$src1, addr:$src2)>;
1534 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1535 (ADD32rm GR32:$src1, addr:$src2)>;
1538 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1539 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1540 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1541 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1542 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1543 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1544 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1547 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1548 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1549 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1552 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1553 (SUB8rm GR8:$src1, addr:$src2)>;
1554 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1555 (SUB16rm GR16:$src1, addr:$src2)>;
1556 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1557 (SUB32rm GR32:$src1, addr:$src2)>;
1560 def : Pat<(sub GR8:$src1, imm:$src2),
1561 (SUB8ri GR8:$src1, imm:$src2)>;
1562 def : Pat<(sub GR16:$src1, imm:$src2),
1563 (SUB16ri GR16:$src1, imm:$src2)>;
1564 def : Pat<(sub GR32:$src1, imm:$src2),
1565 (SUB32ri GR32:$src1, imm:$src2)>;
1566 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1567 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1568 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1569 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1572 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1573 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1574 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1575 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1578 def : Pat<(mul GR16:$src1, GR16:$src2),
1579 (IMUL16rr GR16:$src1, GR16:$src2)>;
1580 def : Pat<(mul GR32:$src1, GR32:$src2),
1581 (IMUL32rr GR32:$src1, GR32:$src2)>;
1584 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1585 (IMUL16rm GR16:$src1, addr:$src2)>;
1586 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1587 (IMUL32rm GR32:$src1, addr:$src2)>;
1590 def : Pat<(mul GR16:$src1, imm:$src2),
1591 (IMUL16rri GR16:$src1, imm:$src2)>;
1592 def : Pat<(mul GR32:$src1, imm:$src2),
1593 (IMUL32rri GR32:$src1, imm:$src2)>;
1594 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1595 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1596 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1597 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1599 // reg = mul mem, imm
1600 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1601 (IMUL16rmi addr:$src1, imm:$src2)>;
1602 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1603 (IMUL32rmi addr:$src1, imm:$src2)>;
1604 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1605 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1606 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1607 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1609 // Patterns for nodes that do not produce flags, for instructions that do.
1612 def : Pat<(add GR64:$src1, GR64:$src2),
1613 (ADD64rr GR64:$src1, GR64:$src2)>;
1614 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1615 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1616 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1617 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1618 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1619 (ADD64rm GR64:$src1, addr:$src2)>;
1622 def : Pat<(sub GR64:$src1, GR64:$src2),
1623 (SUB64rr GR64:$src1, GR64:$src2)>;
1624 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1625 (SUB64rm GR64:$src1, addr:$src2)>;
1626 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1627 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1628 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1629 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1632 def : Pat<(mul GR64:$src1, GR64:$src2),
1633 (IMUL64rr GR64:$src1, GR64:$src2)>;
1634 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1635 (IMUL64rm GR64:$src1, addr:$src2)>;
1636 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1637 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1638 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1639 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1640 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1641 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1642 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1643 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1646 // Do not make INC if it is slow
1647 def : Pat<(add GR8:$src, 1),
1648 (INC8r GR8:$src)>, Requires<[NotSlowIncDec]>;
1649 def : Pat<(add GR16:$src, 1),
1650 (INC16r GR16:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1651 def : Pat<(add GR16:$src, 1),
1652 (INC64_16r GR16:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1653 def : Pat<(add GR32:$src, 1),
1654 (INC32r GR32:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1655 def : Pat<(add GR32:$src, 1),
1656 (INC64_32r GR32:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1657 def : Pat<(add GR64:$src, 1),
1658 (INC64r GR64:$src)>, Requires<[NotSlowIncDec]>;
1661 // Do not make DEC if it is slow
1662 def : Pat<(add GR8:$src, -1),
1663 (DEC8r GR8:$src)>, Requires<[NotSlowIncDec]>;
1664 def : Pat<(add GR16:$src, -1),
1665 (DEC16r GR16:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1666 def : Pat<(add GR16:$src, -1),
1667 (DEC64_16r GR16:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1668 def : Pat<(add GR32:$src, -1),
1669 (DEC32r GR32:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1670 def : Pat<(add GR32:$src, -1),
1671 (DEC64_32r GR32:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1672 def : Pat<(add GR64:$src, -1),
1673 (DEC64r GR64:$src)>, Requires<[NotSlowIncDec]>;
1676 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1677 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1678 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1679 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1682 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1683 (OR8rm GR8:$src1, addr:$src2)>;
1684 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1685 (OR16rm GR16:$src1, addr:$src2)>;
1686 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1687 (OR32rm GR32:$src1, addr:$src2)>;
1688 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1689 (OR64rm GR64:$src1, addr:$src2)>;
1692 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1693 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1694 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1695 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1696 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1697 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1698 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1699 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1700 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1701 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1702 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1705 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1706 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1707 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1708 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1711 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1712 (XOR8rm GR8:$src1, addr:$src2)>;
1713 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1714 (XOR16rm GR16:$src1, addr:$src2)>;
1715 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1716 (XOR32rm GR32:$src1, addr:$src2)>;
1717 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1718 (XOR64rm GR64:$src1, addr:$src2)>;
1721 def : Pat<(xor GR8:$src1, imm:$src2),
1722 (XOR8ri GR8:$src1, imm:$src2)>;
1723 def : Pat<(xor GR16:$src1, imm:$src2),
1724 (XOR16ri GR16:$src1, imm:$src2)>;
1725 def : Pat<(xor GR32:$src1, imm:$src2),
1726 (XOR32ri GR32:$src1, imm:$src2)>;
1727 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1728 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1729 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1730 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1731 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1732 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1733 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1734 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1737 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1738 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1739 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1740 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1743 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1744 (AND8rm GR8:$src1, addr:$src2)>;
1745 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1746 (AND16rm GR16:$src1, addr:$src2)>;
1747 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1748 (AND32rm GR32:$src1, addr:$src2)>;
1749 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1750 (AND64rm GR64:$src1, addr:$src2)>;
1753 def : Pat<(and GR8:$src1, imm:$src2),
1754 (AND8ri GR8:$src1, imm:$src2)>;
1755 def : Pat<(and GR16:$src1, imm:$src2),
1756 (AND16ri GR16:$src1, imm:$src2)>;
1757 def : Pat<(and GR32:$src1, imm:$src2),
1758 (AND32ri GR32:$src1, imm:$src2)>;
1759 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1760 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1761 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1762 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1763 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1764 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1765 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1766 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1768 // Bit scan instruction patterns to match explicit zero-undef behavior.
1769 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1770 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1771 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1772 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1773 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1774 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1776 // When HasMOVBE is enabled it is possible to get a non-legalized
1777 // register-register 16 bit bswap. This maps it to a ROL instruction.
1778 let Predicates = [HasMOVBE] in {
1779 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;