1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[Not64BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[Not64BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1, Defs = [EFLAGS] in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
87 // The VAARG_64 pseudo-instruction takes the address of the va_list,
88 // and places the address of the next argument into a register.
89 let Defs = [EFLAGS] in
90 def VAARG_64 : I<0, Pseudo,
92 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
93 "#VAARG_64 $dst, $ap, $size, $mode, $align",
95 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
98 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
99 // targets. These calls are needed to probe the stack when allocating more than
100 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
101 // ensure that the guard pages used by the OS virtual memory manager are
102 // allocated in correct sequence.
103 // The main point of having separate instruction are extra unmodelled effects
104 // (compared to ordinary calls) like stack pointer change.
106 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
107 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
108 "# dynamic stack allocation",
111 // When using segmented stacks these are lowered into instructions which first
112 // check if the current stacklet has enough free memory. If it does, memory is
113 // allocated by bumping the stack pointer. Otherwise memory is allocated from
116 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
117 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
118 "# variable sized alloca for segmented stacks",
120 (X86SegAlloca GR32:$size))]>,
121 Requires<[Not64BitMode]>;
123 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
124 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
125 "# variable sized alloca for segmented stacks",
127 (X86SegAlloca GR64:$size))]>,
128 Requires<[In64BitMode]>;
131 // The MSVC runtime contains an _ftol2 routine for converting floating-point
132 // to integer values. It has a strange calling convention: the input is
133 // popped from the x87 stack, and the return value is given in EDX:EAX. ECX is
134 // used as a temporary register. No other registers (aside from flags) are
136 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
137 // variant is unnecessary.
139 let Defs = [EAX, EDX, ECX, EFLAGS], FPForm = SpecialFP in {
140 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
142 [(X86WinFTOL RFP32:$src)]>,
143 Requires<[Not64BitMode]>;
145 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
147 [(X86WinFTOL RFP64:$src)]>,
148 Requires<[Not64BitMode]>;
151 //===----------------------------------------------------------------------===//
152 // EH Pseudo Instructions
154 let SchedRW = [WriteSystem] in {
155 let isTerminator = 1, isReturn = 1, isBarrier = 1,
156 hasCtrlDep = 1, isCodeGenOnly = 1 in {
157 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
158 "ret\t#eh_return, addr: $addr",
159 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
163 let isTerminator = 1, isReturn = 1, isBarrier = 1,
164 hasCtrlDep = 1, isCodeGenOnly = 1 in {
165 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
166 "ret\t#eh_return, addr: $addr",
167 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
171 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
172 usesCustomInserter = 1 in {
173 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
175 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
176 Requires<[Not64BitMode]>;
177 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
179 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
180 Requires<[In64BitMode]>;
181 let isTerminator = 1 in {
182 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
183 "#EH_SJLJ_LONGJMP32",
184 [(X86eh_sjlj_longjmp addr:$buf)]>,
185 Requires<[Not64BitMode]>;
186 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
187 "#EH_SJLJ_LONGJMP64",
188 [(X86eh_sjlj_longjmp addr:$buf)]>,
189 Requires<[In64BitMode]>;
194 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
195 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
196 "#EH_SjLj_Setup\t$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // Pseudo instructions used by unwind info.
202 let isPseudo = 1 in {
203 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
204 "#SEH_PushReg $reg", []>;
205 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
206 "#SEH_SaveReg $reg, $dst", []>;
207 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
208 "#SEH_SaveXMM $reg, $dst", []>;
209 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
210 "#SEH_StackAlloc $size", []>;
211 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
212 "#SEH_SetFrame $reg, $offset", []>;
213 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
214 "#SEH_PushFrame $mode", []>;
215 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
216 "#SEH_EndPrologue", []>;
217 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
218 "#SEH_Epilogue", []>;
221 //===----------------------------------------------------------------------===//
222 // Pseudo instructions used by segmented stacks.
225 // This is lowered into a RET instruction by MCInstLower. We need
226 // this so that we don't have to have a MachineBasicBlock which ends
227 // with a RET and also has successors.
228 let isPseudo = 1 in {
229 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
232 // This instruction is lowered to a RET followed by a MOV. The two
233 // instructions are not generated on a higher level since then the
234 // verifier sees a MachineBasicBlock ending with a non-terminator.
235 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
239 //===----------------------------------------------------------------------===//
240 // Alias Instructions
241 //===----------------------------------------------------------------------===//
243 // Alias instruction mapping movr0 to xor.
244 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
245 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
247 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
248 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
250 // Other widths can also make use of the 32-bit xor, which may have a smaller
251 // encoding and avoid partial register updates.
252 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
253 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
254 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
255 let AddedComplexity = 20;
258 // Materialize i64 constant where top 32-bits are zero. This could theoretically
259 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
260 // that would make it more difficult to rematerialize.
261 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
262 isCodeGenOnly = 1, neverHasSideEffects = 1 in
263 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
264 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
266 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
267 // actually the zero-extension of a 32-bit constant, and for labels in the
268 // x86-64 small code model.
269 def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>;
271 let AddedComplexity = 1 in
272 def : Pat<(i64 mov64imm32:$src),
273 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
275 // Use sbb to materialize carry bit.
276 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
277 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
278 // However, Pat<> can't replicate the destination reg into the inputs of the
280 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
281 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
282 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
283 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
284 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
285 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
286 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
287 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
291 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
293 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
295 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
298 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
300 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
302 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
305 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
306 // will be eliminated and that the sbb can be extended up to a wider type. When
307 // this happens, it is great. However, if we are left with an 8-bit sbb and an
308 // and, we might as well just match it as a setb.
309 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
312 // (add OP, SETB) -> (adc OP, 0)
313 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
314 (ADC8ri GR8:$op, 0)>;
315 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
316 (ADC32ri8 GR32:$op, 0)>;
317 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
318 (ADC64ri8 GR64:$op, 0)>;
320 // (sub OP, SETB) -> (sbb OP, 0)
321 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
322 (SBB8ri GR8:$op, 0)>;
323 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
324 (SBB32ri8 GR32:$op, 0)>;
325 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
326 (SBB64ri8 GR64:$op, 0)>;
328 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
329 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
330 (ADC8ri GR8:$op, 0)>;
331 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
332 (ADC32ri8 GR32:$op, 0)>;
333 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
334 (ADC64ri8 GR64:$op, 0)>;
336 //===----------------------------------------------------------------------===//
337 // String Pseudo Instructions
339 let SchedRW = [WriteMicrocoded] in {
340 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
341 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
342 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
343 Requires<[Not64BitMode]>;
344 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
345 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
346 Requires<[Not64BitMode]>;
347 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
348 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
349 Requires<[Not64BitMode]>;
352 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
353 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
354 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
355 Requires<[In64BitMode]>;
356 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
357 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
358 Requires<[In64BitMode]>;
359 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
360 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
361 Requires<[In64BitMode]>;
362 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
363 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
364 Requires<[In64BitMode]>;
367 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
368 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
369 let Uses = [AL,ECX,EDI] in
370 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
371 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
372 Requires<[Not64BitMode]>;
373 let Uses = [AX,ECX,EDI] in
374 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
375 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
376 Requires<[Not64BitMode]>;
377 let Uses = [EAX,ECX,EDI] in
378 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
379 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
380 Requires<[Not64BitMode]>;
383 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
384 let Uses = [AL,RCX,RDI] in
385 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
386 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
387 Requires<[In64BitMode]>;
388 let Uses = [AX,RCX,RDI] in
389 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
390 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
391 Requires<[In64BitMode]>;
392 let Uses = [RAX,RCX,RDI] in
393 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
394 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
395 Requires<[In64BitMode]>;
397 let Uses = [RAX,RCX,RDI] in
398 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
399 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
400 Requires<[In64BitMode]>;
404 //===----------------------------------------------------------------------===//
405 // Thread Local Storage Instructions
409 // All calls clobber the non-callee saved registers. ESP is marked as
410 // a use to prevent stack-pointer assignments that appear immediately
411 // before calls from potentially appearing dead.
412 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
413 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
414 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
415 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
416 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
418 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
420 [(X86tlsaddr tls32addr:$sym)]>,
421 Requires<[Not64BitMode]>;
422 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
424 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
425 Requires<[Not64BitMode]>;
428 // All calls clobber the non-callee saved registers. RSP is marked as
429 // a use to prevent stack-pointer assignments that appear immediately
430 // before calls from potentially appearing dead.
431 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
432 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
433 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
434 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
435 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
436 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
438 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
440 [(X86tlsaddr tls64addr:$sym)]>,
441 Requires<[In64BitMode]>;
442 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
444 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
445 Requires<[In64BitMode]>;
448 // Darwin TLS Support
449 // For i386, the address of the thunk is passed on the stack, on return the
450 // address of the variable is in %eax. %ecx is trashed during the function
451 // call. All other registers are preserved.
452 let Defs = [EAX, ECX, EFLAGS],
454 usesCustomInserter = 1 in
455 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
457 [(X86TLSCall addr:$sym)]>,
458 Requires<[Not64BitMode]>;
460 // For x86_64, the address of the thunk is passed in %rdi, on return
461 // the address of the variable is in %rax. All other registers are preserved.
462 let Defs = [RAX, EFLAGS],
464 usesCustomInserter = 1 in
465 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
467 [(X86TLSCall addr:$sym)]>,
468 Requires<[In64BitMode]>;
471 //===----------------------------------------------------------------------===//
472 // Conditional Move Pseudo Instructions
474 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
475 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
476 // however that requires promoting the operands, and can induce additional
477 // i8 register pressure.
478 let usesCustomInserter = 1, Uses = [EFLAGS] in {
479 def CMOV_GR8 : I<0, Pseudo,
480 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
482 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
483 imm:$cond, EFLAGS))]>;
485 let Predicates = [NoCMov] in {
486 def CMOV_GR32 : I<0, Pseudo,
487 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
488 "#CMOV_GR32* PSEUDO!",
490 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
491 def CMOV_GR16 : I<0, Pseudo,
492 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
493 "#CMOV_GR16* PSEUDO!",
495 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
496 } // Predicates = [NoCMov]
498 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
500 let Predicates = [FPStackf32] in
501 def CMOV_RFP32 : I<0, Pseudo,
503 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
504 "#CMOV_RFP32 PSEUDO!",
506 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
508 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
510 let Predicates = [FPStackf64] in
511 def CMOV_RFP64 : I<0, Pseudo,
513 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
514 "#CMOV_RFP64 PSEUDO!",
516 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
518 def CMOV_RFP80 : I<0, Pseudo,
520 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
521 "#CMOV_RFP80 PSEUDO!",
523 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
525 } // UsesCustomInserter = 1, Uses = [EFLAGS]
528 //===----------------------------------------------------------------------===//
529 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
530 //===----------------------------------------------------------------------===//
532 // FIXME: Use normal instructions and add lock prefix dynamically.
536 // TODO: Get this to fold the constant into the instruction.
537 let isCodeGenOnly = 1, Defs = [EFLAGS] in
538 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
539 "or{l}\t{$zero, $dst|$dst, $zero}",
540 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
541 Sched<[WriteALULd, WriteRMW]>;
543 let hasSideEffects = 1 in
544 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
546 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
548 // RegOpc corresponds to the mr version of the instruction
549 // ImmOpc corresponds to the mi version of the instruction
550 // ImmOpc8 corresponds to the mi8 version of the instruction
551 // ImmMod corresponds to the instruction format of the mi and mi8 versions
552 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
553 Format ImmMod, string mnemonic> {
554 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
555 SchedRW = [WriteALULd, WriteRMW] in {
557 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
558 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
559 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
560 !strconcat(mnemonic, "{b}\t",
561 "{$src2, $dst|$dst, $src2}"),
562 [], IIC_ALU_NONMEM>, LOCK;
563 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
564 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
565 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
566 !strconcat(mnemonic, "{w}\t",
567 "{$src2, $dst|$dst, $src2}"),
568 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
569 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
570 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
571 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
572 !strconcat(mnemonic, "{l}\t",
573 "{$src2, $dst|$dst, $src2}"),
574 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
575 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
576 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
577 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
578 !strconcat(mnemonic, "{q}\t",
579 "{$src2, $dst|$dst, $src2}"),
580 [], IIC_ALU_NONMEM>, LOCK;
582 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
583 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
584 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
585 !strconcat(mnemonic, "{b}\t",
586 "{$src2, $dst|$dst, $src2}"),
587 [], IIC_ALU_MEM>, LOCK;
589 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
590 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
591 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
592 !strconcat(mnemonic, "{w}\t",
593 "{$src2, $dst|$dst, $src2}"),
594 [], IIC_ALU_MEM>, OpSize16, LOCK;
596 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
597 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
598 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
599 !strconcat(mnemonic, "{l}\t",
600 "{$src2, $dst|$dst, $src2}"),
601 [], IIC_ALU_MEM>, OpSize32, LOCK;
603 def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
604 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
605 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
606 !strconcat(mnemonic, "{q}\t",
607 "{$src2, $dst|$dst, $src2}"),
608 [], IIC_ALU_MEM>, LOCK;
610 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
611 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
612 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
613 !strconcat(mnemonic, "{w}\t",
614 "{$src2, $dst|$dst, $src2}"),
615 [], IIC_ALU_MEM>, OpSize16, LOCK;
616 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
617 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
618 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
619 !strconcat(mnemonic, "{l}\t",
620 "{$src2, $dst|$dst, $src2}"),
621 [], IIC_ALU_MEM>, OpSize32, LOCK;
622 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
623 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
624 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
625 !strconcat(mnemonic, "{q}\t",
626 "{$src2, $dst|$dst, $src2}"),
627 [], IIC_ALU_MEM>, LOCK;
633 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
634 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
635 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
636 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
637 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
639 // Optimized codegen when the non-memory output is not used.
640 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
642 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
643 SchedRW = [WriteALULd, WriteRMW] in {
645 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
646 !strconcat(mnemonic, "{b}\t$dst"),
647 [], IIC_UNARY_MEM>, LOCK;
648 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
649 !strconcat(mnemonic, "{w}\t$dst"),
650 [], IIC_UNARY_MEM>, OpSize16, LOCK;
651 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
652 !strconcat(mnemonic, "{l}\t$dst"),
653 [], IIC_UNARY_MEM>, OpSize32, LOCK;
654 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
655 !strconcat(mnemonic, "{q}\t$dst"),
656 [], IIC_UNARY_MEM>, LOCK;
660 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
661 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
663 // Atomic compare and swap.
664 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
665 SDPatternOperator frag, X86MemOperand x86memop,
666 InstrItinClass itin> {
667 let isCodeGenOnly = 1 in {
668 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
669 !strconcat(mnemonic, "\t$ptr"),
670 [(frag addr:$ptr)], itin>, TB, LOCK;
674 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
675 string mnemonic, SDPatternOperator frag,
676 InstrItinClass itin8, InstrItinClass itin> {
677 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
678 let Defs = [AL, EFLAGS], Uses = [AL] in
679 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
680 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
681 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
682 let Defs = [AX, EFLAGS], Uses = [AX] in
683 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
684 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
685 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
686 let Defs = [EAX, EFLAGS], Uses = [EAX] in
687 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
688 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
689 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
690 let Defs = [RAX, EFLAGS], Uses = [RAX] in
691 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
692 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
693 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
697 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
698 SchedRW = [WriteALULd, WriteRMW] in {
699 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
704 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
705 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
706 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
708 IIC_CMPX_LOCK_16B>, REX_W;
711 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
712 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
714 // Atomic exchange and add
715 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
717 InstrItinClass itin8, InstrItinClass itin> {
718 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
719 SchedRW = [WriteALULd, WriteRMW] in {
720 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
721 (ins GR8:$val, i8mem:$ptr),
722 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
724 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
726 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
727 (ins GR16:$val, i16mem:$ptr),
728 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
731 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
733 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
734 (ins GR32:$val, i32mem:$ptr),
735 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
738 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
740 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
741 (ins GR64:$val, i64mem:$ptr),
742 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
745 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
750 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
751 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
754 /* The following multiclass tries to make sure that in code like
755 * x.store (immediate op x.load(acquire), release)
756 * an operation directly on memory is generated instead of wasting a register.
757 * It is not automatic as atomic_store/load are only lowered to MOV instructions
758 * extremely late to prevent them from being accidentally reordered in the backend
759 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
761 multiclass RELEASE_BINOP_MI<string op> {
762 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
763 "#RELEASE_BINOP PSEUDO!",
764 [(atomic_store_8 addr:$dst, (!cast<PatFrag>(op)
765 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
766 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
767 // costly and avoided as far as possible by this backend anyway
768 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
769 "#RELEASE_BINOP PSEUDO!",
770 [(atomic_store_32 addr:$dst, (!cast<PatFrag>(op)
771 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
772 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
773 "#RELEASE_BINOP PSEUDO!",
774 [(atomic_store_64 addr:$dst, (!cast<PatFrag>(op)
775 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
777 defm RELEASE_ADD : RELEASE_BINOP_MI<"add">;
778 defm RELEASE_AND : RELEASE_BINOP_MI<"and">;
779 defm RELEASE_OR : RELEASE_BINOP_MI<"or">;
780 defm RELEASE_XOR : RELEASE_BINOP_MI<"xor">;
781 // Note: we don't deal with sub, because substractions of constants are
782 // optimized into additions before this code can run
784 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
785 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
786 "#RELEASE_UNOP PSEUDO!",
787 [(atomic_store_8 addr:$dst, dag8)]>;
788 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
789 "#RELEASE_UNOP PSEUDO!",
790 [(atomic_store_16 addr:$dst, dag16)]>;
791 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
792 "#RELEASE_UNOP PSEUDO!",
793 [(atomic_store_32 addr:$dst, dag32)]>;
794 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
795 "#RELEASE_UNOP PSEUDO!",
796 [(atomic_store_64 addr:$dst, dag64)]>;
799 defm RELEASE_INC : RELEASE_UNOP<
800 (add (atomic_load_8 addr:$dst), (i8 1)),
801 (add (atomic_load_16 addr:$dst), (i16 1)),
802 (add (atomic_load_32 addr:$dst), (i32 1)),
803 (add (atomic_load_64 addr:$dst), (i64 1))>;
804 defm RELEASE_DEC : RELEASE_UNOP<
805 (add (atomic_load_8 addr:$dst), (i8 -1)),
806 (add (atomic_load_16 addr:$dst), (i16 -1)),
807 (add (atomic_load_32 addr:$dst), (i32 -1)),
808 (add (atomic_load_64 addr:$dst), (i64 -1))>;
810 TODO: These don't work because the type inference of TableGen fails.
811 TODO: find a way to fix it.
812 defm RELEASE_NEG : RELEASE_UNOP<
813 (ineg (atomic_load_8 addr:$dst)),
814 (ineg (atomic_load_16 addr:$dst)),
815 (ineg (atomic_load_32 addr:$dst)),
816 (ineg (atomic_load_64 addr:$dst))>;
817 defm RELEASE_NOT : RELEASE_UNOP<
818 (not (atomic_load_8 addr:$dst)),
819 (not (atomic_load_16 addr:$dst)),
820 (not (atomic_load_32 addr:$dst)),
821 (not (atomic_load_64 addr:$dst))>;
824 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
825 "#RELEASE_MOV PSEUDO !",
826 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
827 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
828 "#RELEASE_MOV PSEUDO !",
829 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
830 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
831 "#RELEASE_MOV PSEUDO !",
832 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
833 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
834 "#RELEASE_MOV PSEUDO !",
835 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
837 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
838 "#RELEASE_MOV PSEUDO!",
839 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
840 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
841 "#RELEASE_MOV PSEUDO!",
842 [(atomic_store_16 addr:$dst, GR16:$src)]>;
843 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
844 "#RELEASE_MOV PSEUDO!",
845 [(atomic_store_32 addr:$dst, GR32:$src)]>;
846 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
847 "#RELEASE_MOV PSEUDO!",
848 [(atomic_store_64 addr:$dst, GR64:$src)]>;
850 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
851 "#ACQUIRE_MOV PSEUDO!",
852 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
853 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
854 "#ACQUIRE_MOV PSEUDO!",
855 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
856 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
857 "#ACQUIRE_MOV PSEUDO!",
858 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
859 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
860 "#ACQUIRE_MOV PSEUDO!",
861 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
862 //===----------------------------------------------------------------------===//
863 // Conditional Move Pseudo Instructions.
864 //===----------------------------------------------------------------------===//
866 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
867 // instruction selection into a branch sequence.
868 let Uses = [EFLAGS], usesCustomInserter = 1 in {
869 def CMOV_FR32 : I<0, Pseudo,
870 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
871 "#CMOV_FR32 PSEUDO!",
872 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
874 def CMOV_FR64 : I<0, Pseudo,
875 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
876 "#CMOV_FR64 PSEUDO!",
877 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
879 def CMOV_V4F32 : I<0, Pseudo,
880 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
881 "#CMOV_V4F32 PSEUDO!",
883 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
885 def CMOV_V2F64 : I<0, Pseudo,
886 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
887 "#CMOV_V2F64 PSEUDO!",
889 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
891 def CMOV_V2I64 : I<0, Pseudo,
892 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
893 "#CMOV_V2I64 PSEUDO!",
895 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
897 def CMOV_V8F32 : I<0, Pseudo,
898 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
899 "#CMOV_V8F32 PSEUDO!",
901 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
903 def CMOV_V4F64 : I<0, Pseudo,
904 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
905 "#CMOV_V4F64 PSEUDO!",
907 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
909 def CMOV_V4I64 : I<0, Pseudo,
910 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
911 "#CMOV_V4I64 PSEUDO!",
913 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
915 def CMOV_V8I64 : I<0, Pseudo,
916 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
917 "#CMOV_V8I64 PSEUDO!",
919 (v8i64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
921 def CMOV_V8F64 : I<0, Pseudo,
922 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
923 "#CMOV_V8F64 PSEUDO!",
925 (v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
927 def CMOV_V16F32 : I<0, Pseudo,
928 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
929 "#CMOV_V16F32 PSEUDO!",
931 (v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond,
936 //===----------------------------------------------------------------------===//
937 // DAG Pattern Matching Rules
938 //===----------------------------------------------------------------------===//
940 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
941 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
942 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
943 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
944 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
945 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
946 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
948 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
949 (ADD32ri GR32:$src1, tconstpool:$src2)>;
950 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
951 (ADD32ri GR32:$src1, tjumptable:$src2)>;
952 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
953 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
954 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
955 (ADD32ri GR32:$src1, texternalsym:$src2)>;
956 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
957 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
959 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
960 (MOV32mi addr:$dst, tglobaladdr:$src)>;
961 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
962 (MOV32mi addr:$dst, texternalsym:$src)>;
963 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
964 (MOV32mi addr:$dst, tblockaddress:$src)>;
966 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
967 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
968 // 'movabs' predicate should handle this sort of thing.
969 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
970 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
971 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
972 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
973 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
974 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
975 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
976 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
977 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
978 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
980 // In kernel code model, we can get the address of a label
981 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
982 // the MOV64ri32 should accept these.
983 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
984 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
985 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
986 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
987 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
988 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
989 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
990 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
991 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
992 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
994 // If we have small model and -static mode, it is safe to store global addresses
995 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
996 // for MOV64mi32 should handle this sort of thing.
997 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
998 (MOV64mi32 addr:$dst, tconstpool:$src)>,
999 Requires<[NearData, IsStatic]>;
1000 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1001 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1002 Requires<[NearData, IsStatic]>;
1003 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1004 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1005 Requires<[NearData, IsStatic]>;
1006 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1007 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1008 Requires<[NearData, IsStatic]>;
1009 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1010 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1011 Requires<[NearData, IsStatic]>;
1015 // tls has some funny stuff here...
1016 // This corresponds to movabs $foo@tpoff, %rax
1017 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
1018 (MOV64ri32 tglobaltlsaddr :$dst)>;
1019 // This corresponds to add $foo@tpoff, %rax
1020 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1021 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1024 // Direct PC relative function call for small code model. 32-bit displacement
1025 // sign extended to 64-bit.
1026 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1027 (CALL64pcrel32 tglobaladdr:$dst)>;
1028 def : Pat<(X86call (i64 texternalsym:$dst)),
1029 (CALL64pcrel32 texternalsym:$dst)>;
1031 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1032 // can never use callee-saved registers. That is the purpose of the GR64_TC
1033 // register classes.
1035 // The only volatile register that is never used by the calling convention is
1036 // %r11. This happens when calling a vararg function with 6 arguments.
1038 // Match an X86tcret that uses less than 7 volatile registers.
1039 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1040 (X86tcret node:$ptr, node:$off), [{
1041 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1042 unsigned NumRegs = 0;
1043 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1044 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1049 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1050 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1051 Requires<[Not64BitMode]>;
1053 // FIXME: This is disabled for 32-bit PIC mode because the global base
1054 // register which is part of the address mode may be assigned a
1055 // callee-saved register.
1056 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1057 (TCRETURNmi addr:$dst, imm:$off)>,
1058 Requires<[Not64BitMode, IsNotPIC]>;
1060 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1061 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1062 Requires<[Not64BitMode]>;
1064 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1065 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1066 Requires<[Not64BitMode]>;
1068 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1069 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1070 Requires<[In64BitMode]>;
1072 // Don't fold loads into X86tcret requiring more than 6 regs.
1073 // There wouldn't be enough scratch registers for base+index.
1074 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1075 (TCRETURNmi64 addr:$dst, imm:$off)>,
1076 Requires<[In64BitMode]>;
1078 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1079 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1080 Requires<[In64BitMode]>;
1082 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1083 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1084 Requires<[In64BitMode]>;
1086 // Normal calls, with various flavors of addresses.
1087 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1088 (CALLpcrel32 tglobaladdr:$dst)>;
1089 def : Pat<(X86call (i32 texternalsym:$dst)),
1090 (CALLpcrel32 texternalsym:$dst)>;
1091 def : Pat<(X86call (i32 imm:$dst)),
1092 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1096 // TEST R,R is smaller than CMP R,0
1097 def : Pat<(X86cmp GR8:$src1, 0),
1098 (TEST8rr GR8:$src1, GR8:$src1)>;
1099 def : Pat<(X86cmp GR16:$src1, 0),
1100 (TEST16rr GR16:$src1, GR16:$src1)>;
1101 def : Pat<(X86cmp GR32:$src1, 0),
1102 (TEST32rr GR32:$src1, GR32:$src1)>;
1103 def : Pat<(X86cmp GR64:$src1, 0),
1104 (TEST64rr GR64:$src1, GR64:$src1)>;
1106 // Conditional moves with folded loads with operands swapped and conditions
1108 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1109 Instruction Inst64> {
1110 let Predicates = [HasCMov] in {
1111 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1112 (Inst16 GR16:$src2, addr:$src1)>;
1113 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1114 (Inst32 GR32:$src2, addr:$src1)>;
1115 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1116 (Inst64 GR64:$src2, addr:$src1)>;
1120 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1121 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1122 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1123 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1124 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1125 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1126 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1127 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1128 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1129 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1130 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1131 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1132 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1133 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1134 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1135 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1137 // zextload bool -> zextload byte
1138 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1139 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1140 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1141 def : Pat<(zextloadi64i1 addr:$src),
1142 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1144 // extload bool -> extload byte
1145 // When extloading from 16-bit and smaller memory locations into 64-bit
1146 // registers, use zero-extending loads so that the entire 64-bit register is
1147 // defined, avoiding partial-register updates.
1149 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1150 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1151 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1152 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1153 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1154 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1156 // For other extloads, use subregs, since the high contents of the register are
1157 // defined after an extload.
1158 def : Pat<(extloadi64i1 addr:$src),
1159 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1160 def : Pat<(extloadi64i8 addr:$src),
1161 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1162 def : Pat<(extloadi64i16 addr:$src),
1163 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1164 def : Pat<(extloadi64i32 addr:$src),
1165 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1167 // anyext. Define these to do an explicit zero-extend to
1168 // avoid partial-register updates.
1169 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1170 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1171 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1173 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1174 def : Pat<(i32 (anyext GR16:$src)),
1175 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1177 def : Pat<(i64 (anyext GR8 :$src)),
1178 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1179 def : Pat<(i64 (anyext GR16:$src)),
1180 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1181 def : Pat<(i64 (anyext GR32:$src)),
1182 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1185 // Any instruction that defines a 32-bit result leaves the high half of the
1186 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1187 // be copying from a truncate. And x86's cmov doesn't do anything if the
1188 // condition is false. But any other 32-bit operation will zero-extend
1190 def def32 : PatLeaf<(i32 GR32:$src), [{
1191 return N->getOpcode() != ISD::TRUNCATE &&
1192 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1193 N->getOpcode() != ISD::CopyFromReg &&
1194 N->getOpcode() != X86ISD::CMOV;
1197 // In the case of a 32-bit def that is known to implicitly zero-extend,
1198 // we can use a SUBREG_TO_REG.
1199 def : Pat<(i64 (zext def32:$src)),
1200 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1202 //===----------------------------------------------------------------------===//
1203 // Pattern match OR as ADD
1204 //===----------------------------------------------------------------------===//
1206 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1207 // 3-addressified into an LEA instruction to avoid copies. However, we also
1208 // want to finally emit these instructions as an or at the end of the code
1209 // generator to make the generated code easier to read. To do this, we select
1210 // into "disjoint bits" pseudo ops.
1212 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1213 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1214 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1215 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1217 APInt KnownZero0, KnownOne0;
1218 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1219 APInt KnownZero1, KnownOne1;
1220 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1221 return (~KnownZero0 & ~KnownZero1) == 0;
1225 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1226 // Try this before the selecting to OR.
1227 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1229 let isConvertibleToThreeAddress = 1,
1230 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1231 let isCommutable = 1 in {
1232 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1233 "", // orw/addw REG, REG
1234 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1235 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1236 "", // orl/addl REG, REG
1237 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1238 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1239 "", // orq/addq REG, REG
1240 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1243 // NOTE: These are order specific, we want the ri8 forms to be listed
1244 // first so that they are slightly preferred to the ri forms.
1246 def ADD16ri8_DB : I<0, Pseudo,
1247 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1248 "", // orw/addw REG, imm8
1249 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1250 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1251 "", // orw/addw REG, imm
1252 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1254 def ADD32ri8_DB : I<0, Pseudo,
1255 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1256 "", // orl/addl REG, imm8
1257 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1258 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1259 "", // orl/addl REG, imm
1260 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1263 def ADD64ri8_DB : I<0, Pseudo,
1264 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1265 "", // orq/addq REG, imm8
1266 [(set GR64:$dst, (or_is_add GR64:$src1,
1267 i64immSExt8:$src2))]>;
1268 def ADD64ri32_DB : I<0, Pseudo,
1269 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1270 "", // orq/addq REG, imm
1271 [(set GR64:$dst, (or_is_add GR64:$src1,
1272 i64immSExt32:$src2))]>;
1274 } // AddedComplexity, SchedRW
1277 //===----------------------------------------------------------------------===//
1279 //===----------------------------------------------------------------------===//
1281 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1282 // +128 doesn't, so in this special case use a sub instead of an add.
1283 def : Pat<(add GR16:$src1, 128),
1284 (SUB16ri8 GR16:$src1, -128)>;
1285 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1286 (SUB16mi8 addr:$dst, -128)>;
1288 def : Pat<(add GR32:$src1, 128),
1289 (SUB32ri8 GR32:$src1, -128)>;
1290 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1291 (SUB32mi8 addr:$dst, -128)>;
1293 def : Pat<(add GR64:$src1, 128),
1294 (SUB64ri8 GR64:$src1, -128)>;
1295 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1296 (SUB64mi8 addr:$dst, -128)>;
1298 // The same trick applies for 32-bit immediate fields in 64-bit
1300 def : Pat<(add GR64:$src1, 0x0000000080000000),
1301 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1302 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1303 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1305 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1306 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1307 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1308 // represented with a sign extension of a 8 bit constant, use that.
1310 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1314 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1315 (i32 (GetLo8XForm imm:$imm))),
1318 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1322 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1323 (i32 (GetLo32XForm imm:$imm))),
1327 // r & (2^16-1) ==> movz
1328 def : Pat<(and GR32:$src1, 0xffff),
1329 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1330 // r & (2^8-1) ==> movz
1331 def : Pat<(and GR32:$src1, 0xff),
1332 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1335 Requires<[Not64BitMode]>;
1336 // r & (2^8-1) ==> movz
1337 def : Pat<(and GR16:$src1, 0xff),
1338 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1339 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1341 Requires<[Not64BitMode]>;
1343 // r & (2^32-1) ==> movz
1344 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1345 (SUBREG_TO_REG (i64 0),
1346 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1348 // r & (2^16-1) ==> movz
1349 def : Pat<(and GR64:$src, 0xffff),
1350 (SUBREG_TO_REG (i64 0),
1351 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1353 // r & (2^8-1) ==> movz
1354 def : Pat<(and GR64:$src, 0xff),
1355 (SUBREG_TO_REG (i64 0),
1356 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1358 // r & (2^8-1) ==> movz
1359 def : Pat<(and GR32:$src1, 0xff),
1360 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1361 Requires<[In64BitMode]>;
1362 // r & (2^8-1) ==> movz
1363 def : Pat<(and GR16:$src1, 0xff),
1364 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1365 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1366 Requires<[In64BitMode]>;
1369 // sext_inreg patterns
1370 def : Pat<(sext_inreg GR32:$src, i16),
1371 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1372 def : Pat<(sext_inreg GR32:$src, i8),
1373 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1376 Requires<[Not64BitMode]>;
1378 def : Pat<(sext_inreg GR16:$src, i8),
1379 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1380 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1382 Requires<[Not64BitMode]>;
1384 def : Pat<(sext_inreg GR64:$src, i32),
1385 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1386 def : Pat<(sext_inreg GR64:$src, i16),
1387 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1388 def : Pat<(sext_inreg GR64:$src, i8),
1389 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1390 def : Pat<(sext_inreg GR32:$src, i8),
1391 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1392 Requires<[In64BitMode]>;
1393 def : Pat<(sext_inreg GR16:$src, i8),
1394 (EXTRACT_SUBREG (MOVSX32rr8
1395 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1396 Requires<[In64BitMode]>;
1398 // sext, sext_load, zext, zext_load
1399 def: Pat<(i16 (sext GR8:$src)),
1400 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1401 def: Pat<(sextloadi16i8 addr:$src),
1402 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1403 def: Pat<(i16 (zext GR8:$src)),
1404 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1405 def: Pat<(zextloadi16i8 addr:$src),
1406 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1409 def : Pat<(i16 (trunc GR32:$src)),
1410 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1411 def : Pat<(i8 (trunc GR32:$src)),
1412 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1414 Requires<[Not64BitMode]>;
1415 def : Pat<(i8 (trunc GR16:$src)),
1416 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1418 Requires<[Not64BitMode]>;
1419 def : Pat<(i32 (trunc GR64:$src)),
1420 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1421 def : Pat<(i16 (trunc GR64:$src)),
1422 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1423 def : Pat<(i8 (trunc GR64:$src)),
1424 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1425 def : Pat<(i8 (trunc GR32:$src)),
1426 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1427 Requires<[In64BitMode]>;
1428 def : Pat<(i8 (trunc GR16:$src)),
1429 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1430 Requires<[In64BitMode]>;
1432 // h-register tricks
1433 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1434 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1436 Requires<[Not64BitMode]>;
1437 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1438 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1440 Requires<[Not64BitMode]>;
1441 def : Pat<(srl GR16:$src, (i8 8)),
1444 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1447 Requires<[Not64BitMode]>;
1448 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1449 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1452 Requires<[Not64BitMode]>;
1453 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1454 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1457 Requires<[Not64BitMode]>;
1458 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1459 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1462 Requires<[Not64BitMode]>;
1463 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1464 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1467 Requires<[Not64BitMode]>;
1469 // h-register tricks.
1470 // For now, be conservative on x86-64 and use an h-register extract only if the
1471 // value is immediately zero-extended or stored, which are somewhat common
1472 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1473 // from being allocated in the same instruction as the h register, as there's
1474 // currently no way to describe this requirement to the register allocator.
1476 // h-register extract and zero-extend.
1477 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1481 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1484 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1486 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1488 Requires<[In64BitMode]>;
1489 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1490 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1493 Requires<[In64BitMode]>;
1494 def : Pat<(srl GR16:$src, (i8 8)),
1497 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1500 Requires<[In64BitMode]>;
1501 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1503 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1505 Requires<[In64BitMode]>;
1506 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1508 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1510 Requires<[In64BitMode]>;
1511 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1515 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1518 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1522 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1526 // h-register extract and store.
1527 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1530 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1532 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1535 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1537 Requires<[In64BitMode]>;
1538 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1541 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1543 Requires<[In64BitMode]>;
1546 // (shl x, 1) ==> (add x, x)
1547 // Note that if x is undef (immediate or otherwise), we could theoretically
1548 // end up with the two uses of x getting different values, producing a result
1549 // where the least significant bit is not 0. However, the probability of this
1550 // happening is considered low enough that this is officially not a
1552 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1553 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1554 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1555 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1557 // Helper imms that check if a mask doesn't change significant shift bits.
1558 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1559 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1561 // Shift amount is implicitly masked.
1562 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1563 // (shift x (and y, 31)) ==> (shift x, y)
1564 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1565 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1566 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1567 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1568 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1569 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1570 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1571 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1572 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1573 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1574 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1575 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1577 // (shift x (and y, 63)) ==> (shift x, y)
1578 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1579 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1580 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1581 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1584 defm : MaskedShiftAmountPats<shl, "SHL">;
1585 defm : MaskedShiftAmountPats<srl, "SHR">;
1586 defm : MaskedShiftAmountPats<sra, "SAR">;
1587 defm : MaskedShiftAmountPats<rotl, "ROL">;
1588 defm : MaskedShiftAmountPats<rotr, "ROR">;
1590 // (anyext (setcc_carry)) -> (setcc_carry)
1591 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1593 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1595 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1601 //===----------------------------------------------------------------------===//
1602 // EFLAGS-defining Patterns
1603 //===----------------------------------------------------------------------===//
1606 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1607 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1608 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1611 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1612 (ADD8rm GR8:$src1, addr:$src2)>;
1613 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1614 (ADD16rm GR16:$src1, addr:$src2)>;
1615 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1616 (ADD32rm GR32:$src1, addr:$src2)>;
1619 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1620 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1621 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1622 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1623 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1624 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1625 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1628 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1629 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1630 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1633 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1634 (SUB8rm GR8:$src1, addr:$src2)>;
1635 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1636 (SUB16rm GR16:$src1, addr:$src2)>;
1637 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1638 (SUB32rm GR32:$src1, addr:$src2)>;
1641 def : Pat<(sub GR8:$src1, imm:$src2),
1642 (SUB8ri GR8:$src1, imm:$src2)>;
1643 def : Pat<(sub GR16:$src1, imm:$src2),
1644 (SUB16ri GR16:$src1, imm:$src2)>;
1645 def : Pat<(sub GR32:$src1, imm:$src2),
1646 (SUB32ri GR32:$src1, imm:$src2)>;
1647 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1648 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1649 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1650 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1653 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1654 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1655 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1656 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1659 def : Pat<(mul GR16:$src1, GR16:$src2),
1660 (IMUL16rr GR16:$src1, GR16:$src2)>;
1661 def : Pat<(mul GR32:$src1, GR32:$src2),
1662 (IMUL32rr GR32:$src1, GR32:$src2)>;
1665 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1666 (IMUL16rm GR16:$src1, addr:$src2)>;
1667 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1668 (IMUL32rm GR32:$src1, addr:$src2)>;
1671 def : Pat<(mul GR16:$src1, imm:$src2),
1672 (IMUL16rri GR16:$src1, imm:$src2)>;
1673 def : Pat<(mul GR32:$src1, imm:$src2),
1674 (IMUL32rri GR32:$src1, imm:$src2)>;
1675 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1676 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1677 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1678 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1680 // reg = mul mem, imm
1681 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1682 (IMUL16rmi addr:$src1, imm:$src2)>;
1683 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1684 (IMUL32rmi addr:$src1, imm:$src2)>;
1685 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1686 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1687 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1688 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1690 // Patterns for nodes that do not produce flags, for instructions that do.
1693 def : Pat<(add GR64:$src1, GR64:$src2),
1694 (ADD64rr GR64:$src1, GR64:$src2)>;
1695 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1696 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1697 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1698 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1699 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1700 (ADD64rm GR64:$src1, addr:$src2)>;
1703 def : Pat<(sub GR64:$src1, GR64:$src2),
1704 (SUB64rr GR64:$src1, GR64:$src2)>;
1705 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1706 (SUB64rm GR64:$src1, addr:$src2)>;
1707 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1708 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1709 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1710 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1713 def : Pat<(mul GR64:$src1, GR64:$src2),
1714 (IMUL64rr GR64:$src1, GR64:$src2)>;
1715 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1716 (IMUL64rm GR64:$src1, addr:$src2)>;
1717 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1718 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1719 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1720 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1721 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1722 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1723 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1724 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1727 // Do not make INC if it is slow
1728 def : Pat<(add GR8:$src, 1),
1729 (INC8r GR8:$src)>, Requires<[NotSlowIncDec]>;
1730 def : Pat<(add GR16:$src, 1),
1731 (INC16r GR16:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1732 def : Pat<(add GR16:$src, 1),
1733 (INC64_16r GR16:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1734 def : Pat<(add GR32:$src, 1),
1735 (INC32r GR32:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1736 def : Pat<(add GR32:$src, 1),
1737 (INC64_32r GR32:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1738 def : Pat<(add GR64:$src, 1),
1739 (INC64r GR64:$src)>, Requires<[NotSlowIncDec]>;
1742 // Do not make DEC if it is slow
1743 def : Pat<(add GR8:$src, -1),
1744 (DEC8r GR8:$src)>, Requires<[NotSlowIncDec]>;
1745 def : Pat<(add GR16:$src, -1),
1746 (DEC16r GR16:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1747 def : Pat<(add GR16:$src, -1),
1748 (DEC64_16r GR16:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1749 def : Pat<(add GR32:$src, -1),
1750 (DEC32r GR32:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1751 def : Pat<(add GR32:$src, -1),
1752 (DEC64_32r GR32:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1753 def : Pat<(add GR64:$src, -1),
1754 (DEC64r GR64:$src)>, Requires<[NotSlowIncDec]>;
1757 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1758 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1759 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1760 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1763 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1764 (OR8rm GR8:$src1, addr:$src2)>;
1765 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1766 (OR16rm GR16:$src1, addr:$src2)>;
1767 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1768 (OR32rm GR32:$src1, addr:$src2)>;
1769 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1770 (OR64rm GR64:$src1, addr:$src2)>;
1773 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1774 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1775 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1776 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1777 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1778 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1779 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1780 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1781 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1782 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1783 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1786 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1787 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1788 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1789 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1792 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1793 (XOR8rm GR8:$src1, addr:$src2)>;
1794 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1795 (XOR16rm GR16:$src1, addr:$src2)>;
1796 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1797 (XOR32rm GR32:$src1, addr:$src2)>;
1798 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1799 (XOR64rm GR64:$src1, addr:$src2)>;
1802 def : Pat<(xor GR8:$src1, imm:$src2),
1803 (XOR8ri GR8:$src1, imm:$src2)>;
1804 def : Pat<(xor GR16:$src1, imm:$src2),
1805 (XOR16ri GR16:$src1, imm:$src2)>;
1806 def : Pat<(xor GR32:$src1, imm:$src2),
1807 (XOR32ri GR32:$src1, imm:$src2)>;
1808 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1809 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1810 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1811 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1812 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1813 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1814 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1815 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1818 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1819 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1820 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1821 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1824 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1825 (AND8rm GR8:$src1, addr:$src2)>;
1826 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1827 (AND16rm GR16:$src1, addr:$src2)>;
1828 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1829 (AND32rm GR32:$src1, addr:$src2)>;
1830 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1831 (AND64rm GR64:$src1, addr:$src2)>;
1834 def : Pat<(and GR8:$src1, imm:$src2),
1835 (AND8ri GR8:$src1, imm:$src2)>;
1836 def : Pat<(and GR16:$src1, imm:$src2),
1837 (AND16ri GR16:$src1, imm:$src2)>;
1838 def : Pat<(and GR32:$src1, imm:$src2),
1839 (AND32ri GR32:$src1, imm:$src2)>;
1840 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1841 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1842 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1843 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1844 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1845 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1846 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1847 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1849 // Bit scan instruction patterns to match explicit zero-undef behavior.
1850 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1851 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1852 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1853 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1854 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1855 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1857 // When HasMOVBE is enabled it is possible to get a non-legalized
1858 // register-register 16 bit bswap. This maps it to a ROL instruction.
1859 let Predicates = [HasMOVBE] in {
1860 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;