1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1 in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
87 // and places the address of the next argument into a register.
88 let Defs = [EFLAGS] in
89 def VAARG_64 : I<0, Pseudo,
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
98 // targets. These calls are needed to probe the stack when allocating more than
99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
100 // ensure that the guard pages used by the OS virtual memory manager are
101 // allocated in correct sequence.
102 // The main point of having separate instruction are extra unmodelled effects
103 // (compared to ordinary calls) like stack pointer change.
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
107 "# dynamic stack allocation",
110 // When using segmented stacks these are lowered into instructions which first
111 // check if the current stacklet has enough free memory. If it does, memory is
112 // allocated by bumping the stack pointer. Otherwise memory is allocated from
115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
117 "# variable sized alloca for segmented stacks",
119 (X86SegAlloca GR32:$size))]>,
120 Requires<[In32BitMode]>;
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
123 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
124 "# variable sized alloca for segmented stacks",
126 (X86SegAlloca GR64:$size))]>,
127 Requires<[In64BitMode]>;
130 // The MSVC runtime contains an _ftol2 routine for converting floating-point
131 // to integer values. It has a strange calling convention: the input is
132 // popped from the x87 stack, and the return value is given in EDX:EAX. No
133 // other registers (aside from flags) are touched.
134 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
135 // variant is unnecessary.
137 let Defs = [EAX, EDX, EFLAGS], FPForm = SpecialFP in {
138 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
140 [(X86WinFTOL RFP32:$src)]>,
141 Requires<[In32BitMode]>;
143 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
145 [(X86WinFTOL RFP64:$src)]>,
146 Requires<[In32BitMode]>;
149 //===----------------------------------------------------------------------===//
150 // EH Pseudo Instructions
152 let isTerminator = 1, isReturn = 1, isBarrier = 1,
153 hasCtrlDep = 1, isCodeGenOnly = 1 in {
154 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
155 "ret\t#eh_return, addr: $addr",
156 [(X86ehret GR32:$addr)], IIC_RET>;
160 let isTerminator = 1, isReturn = 1, isBarrier = 1,
161 hasCtrlDep = 1, isCodeGenOnly = 1 in {
162 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
163 "ret\t#eh_return, addr: $addr",
164 [(X86ehret GR64:$addr)], IIC_RET>;
168 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
169 usesCustomInserter = 1 in {
170 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
172 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
173 Requires<[In32BitMode]>;
174 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
176 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
177 Requires<[In64BitMode]>;
178 let isTerminator = 1 in {
179 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
180 "#EH_SJLJ_LONGJMP32",
181 [(X86eh_sjlj_longjmp addr:$buf)]>,
182 Requires<[In32BitMode]>;
183 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
184 "#EH_SJLJ_LONGJMP64",
185 [(X86eh_sjlj_longjmp addr:$buf)]>,
186 Requires<[In64BitMode]>;
190 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
191 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
192 "#EH_SjLj_Setup\t$dst", []>;
195 //===----------------------------------------------------------------------===//
196 // Pseudo instructions used by segmented stacks.
199 // This is lowered into a RET instruction by MCInstLower. We need
200 // this so that we don't have to have a MachineBasicBlock which ends
201 // with a RET and also has successors.
202 let isPseudo = 1 in {
203 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
206 // This instruction is lowered to a RET followed by a MOV. The two
207 // instructions are not generated on a higher level since then the
208 // verifier sees a MachineBasicBlock ending with a non-terminator.
209 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
213 //===----------------------------------------------------------------------===//
214 // Alias Instructions
215 //===----------------------------------------------------------------------===//
217 // Alias instructions that map movr0 to xor.
218 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
219 // FIXME: Set encoding to pseudo.
220 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
221 isCodeGenOnly = 1 in {
222 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
223 [(set GR8:$dst, 0)], IIC_ALU_NONMEM>;
225 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
226 // encoding and avoids a partial-register update sometimes, but doing so
227 // at isel time interferes with rematerialization in the current register
228 // allocator. For now, this is rewritten when the instruction is lowered
230 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
232 [(set GR16:$dst, 0)], IIC_ALU_NONMEM>, OpSize;
234 // FIXME: Set encoding to pseudo.
235 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
236 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>;
239 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
240 // smaller encoding, but doing so at isel time interferes with rematerialization
241 // in the current register allocator. For now, this is rewritten when the
242 // instruction is lowered to an MCInst.
243 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
244 // when we have a better way to specify isel priority.
245 let Defs = [EFLAGS], isCodeGenOnly=1,
246 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
247 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
248 [(set GR64:$dst, 0)], IIC_ALU_NONMEM>;
250 // Materialize i64 constant where top 32-bits are zero. This could theoretically
251 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
252 // that would make it more difficult to rematerialize.
253 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
255 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
256 "", [(set GR64:$dst, i64immZExt32:$src)],
259 // Use sbb to materialize carry bit.
260 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1 in {
261 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
262 // However, Pat<> can't replicate the destination reg into the inputs of the
264 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
265 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
266 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
267 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
268 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
269 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
270 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
271 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
275 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
277 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
279 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
282 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
284 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
286 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
289 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
290 // will be eliminated and that the sbb can be extended up to a wider type. When
291 // this happens, it is great. However, if we are left with an 8-bit sbb and an
292 // and, we might as well just match it as a setb.
293 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
296 // (add OP, SETB) -> (adc OP, 0)
297 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
298 (ADC8ri GR8:$op, 0)>;
299 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
300 (ADC32ri8 GR32:$op, 0)>;
301 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
302 (ADC64ri8 GR64:$op, 0)>;
304 // (sub OP, SETB) -> (sbb OP, 0)
305 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
306 (SBB8ri GR8:$op, 0)>;
307 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
308 (SBB32ri8 GR32:$op, 0)>;
309 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
310 (SBB64ri8 GR64:$op, 0)>;
312 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
313 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
314 (ADC8ri GR8:$op, 0)>;
315 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
316 (ADC32ri8 GR32:$op, 0)>;
317 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
318 (ADC64ri8 GR64:$op, 0)>;
320 //===----------------------------------------------------------------------===//
321 // String Pseudo Instructions
323 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
324 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
325 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
326 Requires<[In32BitMode]>;
327 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
328 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
329 Requires<[In32BitMode]>;
330 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
331 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
332 Requires<[In32BitMode]>;
335 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
336 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
337 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
338 Requires<[In64BitMode]>;
339 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
340 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
341 Requires<[In64BitMode]>;
342 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
343 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
344 Requires<[In64BitMode]>;
345 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
346 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
347 Requires<[In64BitMode]>;
350 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
351 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
352 let Uses = [AL,ECX,EDI] in
353 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
354 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
355 Requires<[In32BitMode]>;
356 let Uses = [AX,ECX,EDI] in
357 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
358 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
359 Requires<[In32BitMode]>;
360 let Uses = [EAX,ECX,EDI] in
361 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
362 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
363 Requires<[In32BitMode]>;
366 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
367 let Uses = [AL,RCX,RDI] in
368 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
369 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
370 Requires<[In64BitMode]>;
371 let Uses = [AX,RCX,RDI] in
372 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
373 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
374 Requires<[In64BitMode]>;
375 let Uses = [RAX,RCX,RDI] in
376 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
377 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
378 Requires<[In64BitMode]>;
380 let Uses = [RAX,RCX,RDI] in
381 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
382 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
383 Requires<[In64BitMode]>;
386 //===----------------------------------------------------------------------===//
387 // Thread Local Storage Instructions
391 // All calls clobber the non-callee saved registers. ESP is marked as
392 // a use to prevent stack-pointer assignments that appear immediately
393 // before calls from potentially appearing dead.
394 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
395 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
396 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
397 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
399 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
401 [(X86tlsaddr tls32addr:$sym)]>,
402 Requires<[In32BitMode]>;
403 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
405 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
406 Requires<[In32BitMode]>;
409 // All calls clobber the non-callee saved registers. RSP is marked as
410 // a use to prevent stack-pointer assignments that appear immediately
411 // before calls from potentially appearing dead.
412 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
413 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
414 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
415 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
416 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
418 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
420 [(X86tlsaddr tls64addr:$sym)]>,
421 Requires<[In64BitMode]>;
422 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
424 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
425 Requires<[In64BitMode]>;
428 // Darwin TLS Support
429 // For i386, the address of the thunk is passed on the stack, on return the
430 // address of the variable is in %eax. %ecx is trashed during the function
431 // call. All other registers are preserved.
432 let Defs = [EAX, ECX, EFLAGS],
434 usesCustomInserter = 1 in
435 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
437 [(X86TLSCall addr:$sym)]>,
438 Requires<[In32BitMode]>;
440 // For x86_64, the address of the thunk is passed in %rdi, on return
441 // the address of the variable is in %rax. All other registers are preserved.
442 let Defs = [RAX, EFLAGS],
444 usesCustomInserter = 1 in
445 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
447 [(X86TLSCall addr:$sym)]>,
448 Requires<[In64BitMode]>;
451 //===----------------------------------------------------------------------===//
452 // Conditional Move Pseudo Instructions
454 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
455 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
456 // however that requires promoting the operands, and can induce additional
457 // i8 register pressure.
458 let usesCustomInserter = 1, Uses = [EFLAGS] in {
459 def CMOV_GR8 : I<0, Pseudo,
460 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
462 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
463 imm:$cond, EFLAGS))]>;
465 let Predicates = [NoCMov] in {
466 def CMOV_GR32 : I<0, Pseudo,
467 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
468 "#CMOV_GR32* PSEUDO!",
470 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
471 def CMOV_GR16 : I<0, Pseudo,
472 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
473 "#CMOV_GR16* PSEUDO!",
475 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
476 } // Predicates = [NoCMov]
478 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
480 let Predicates = [FPStackf32] in
481 def CMOV_RFP32 : I<0, Pseudo,
483 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
484 "#CMOV_RFP32 PSEUDO!",
486 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
488 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
490 let Predicates = [FPStackf64] in
491 def CMOV_RFP64 : I<0, Pseudo,
493 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
494 "#CMOV_RFP64 PSEUDO!",
496 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
498 def CMOV_RFP80 : I<0, Pseudo,
500 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
501 "#CMOV_RFP80 PSEUDO!",
503 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
505 } // UsesCustomInserter = 1, Uses = [EFLAGS]
508 //===----------------------------------------------------------------------===//
509 // Atomic Instruction Pseudo Instructions
510 //===----------------------------------------------------------------------===//
512 // Pseudo atomic instructions
514 multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> {
515 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in {
516 def #NAME#8 : I<0, Pseudo, (outs GR8:$dst),
517 (ins i8mem:$ptr, GR8:$val),
518 !strconcat(mnemonic, "8 PSEUDO!"), []>;
519 def #NAME#16 : I<0, Pseudo,(outs GR16:$dst),
520 (ins i16mem:$ptr, GR16:$val),
521 !strconcat(mnemonic, "16 PSEUDO!"), []>;
522 def #NAME#32 : I<0, Pseudo, (outs GR32:$dst),
523 (ins i32mem:$ptr, GR32:$val),
524 !strconcat(mnemonic, "32 PSEUDO!"), []>;
525 def #NAME#64 : I<0, Pseudo, (outs GR64:$dst),
526 (ins i64mem:$ptr, GR64:$val),
527 !strconcat(mnemonic, "64 PSEUDO!"), []>;
531 multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> {
532 def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val),
533 (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>;
534 def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val),
535 (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>;
536 def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val),
537 (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>;
538 def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val),
539 (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>;
542 // Atomic exchange, and, or, xor
543 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">;
544 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">;
545 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">;
546 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">;
547 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">;
548 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">;
549 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">;
550 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">;
552 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">;
553 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">;
554 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">;
555 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">;
556 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">;
557 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">;
558 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">;
559 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">;
561 multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> {
562 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in
563 def #NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
564 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
565 !strconcat(mnemonic, "6432 PSEUDO!"), []>;
568 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMAND">;
569 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMOR">;
570 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMXOR">;
571 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMNAND">;
572 defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMADD">;
573 defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSUB">;
574 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMAX">;
575 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMIN">;
576 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMAX">;
577 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMIN">;
578 defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSWAP">;
580 //===----------------------------------------------------------------------===//
581 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
582 //===----------------------------------------------------------------------===//
584 // FIXME: Use normal instructions and add lock prefix dynamically.
588 // TODO: Get this to fold the constant into the instruction.
589 let isCodeGenOnly = 1, Defs = [EFLAGS] in
590 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
591 "or{l}\t{$zero, $dst|$dst, $zero}",
592 [], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK;
594 let hasSideEffects = 1 in
595 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
599 // RegOpc corresponds to the mr version of the instruction
600 // ImmOpc corresponds to the mi version of the instruction
601 // ImmOpc8 corresponds to the mi8 version of the instruction
602 // ImmMod corresponds to the instruction format of the mi and mi8 versions
603 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
604 Format ImmMod, string mnemonic> {
605 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
607 def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
608 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
609 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
610 !strconcat(mnemonic, "{b}\t",
611 "{$src2, $dst|$dst, $src2}"),
612 [], IIC_ALU_NONMEM>, LOCK;
613 def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
614 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
615 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
616 !strconcat(mnemonic, "{w}\t",
617 "{$src2, $dst|$dst, $src2}"),
618 [], IIC_ALU_NONMEM>, OpSize, LOCK;
619 def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
620 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
621 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
622 !strconcat(mnemonic, "{l}\t",
623 "{$src2, $dst|$dst, $src2}"),
624 [], IIC_ALU_NONMEM>, LOCK;
625 def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
626 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
627 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
628 !strconcat(mnemonic, "{q}\t",
629 "{$src2, $dst|$dst, $src2}"),
630 [], IIC_ALU_NONMEM>, LOCK;
632 def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
633 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
634 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
635 !strconcat(mnemonic, "{b}\t",
636 "{$src2, $dst|$dst, $src2}"),
637 [], IIC_ALU_MEM>, LOCK;
639 def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
640 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
641 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
642 !strconcat(mnemonic, "{w}\t",
643 "{$src2, $dst|$dst, $src2}"),
644 [], IIC_ALU_MEM>, OpSize, LOCK;
646 def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
647 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
648 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
649 !strconcat(mnemonic, "{l}\t",
650 "{$src2, $dst|$dst, $src2}"),
651 [], IIC_ALU_MEM>, LOCK;
653 def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
654 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
655 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
656 !strconcat(mnemonic, "{q}\t",
657 "{$src2, $dst|$dst, $src2}"),
658 [], IIC_ALU_MEM>, LOCK;
660 def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
661 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
662 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
663 !strconcat(mnemonic, "{w}\t",
664 "{$src2, $dst|$dst, $src2}"),
665 [], IIC_ALU_MEM>, OpSize, LOCK;
666 def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
667 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
668 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
669 !strconcat(mnemonic, "{l}\t",
670 "{$src2, $dst|$dst, $src2}"),
671 [], IIC_ALU_MEM>, LOCK;
672 def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
673 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
674 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
675 !strconcat(mnemonic, "{q}\t",
676 "{$src2, $dst|$dst, $src2}"),
677 [], IIC_ALU_MEM>, LOCK;
683 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
684 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
685 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
686 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
687 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
689 // Optimized codegen when the non-memory output is not used.
690 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
692 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
694 def #NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
695 !strconcat(mnemonic, "{b}\t$dst"),
696 [], IIC_UNARY_MEM>, LOCK;
697 def #NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
698 !strconcat(mnemonic, "{w}\t$dst"),
699 [], IIC_UNARY_MEM>, OpSize, LOCK;
700 def #NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
701 !strconcat(mnemonic, "{l}\t$dst"),
702 [], IIC_UNARY_MEM>, LOCK;
703 def #NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
704 !strconcat(mnemonic, "{q}\t$dst"),
705 [], IIC_UNARY_MEM>, LOCK;
709 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
710 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
712 // Atomic compare and swap.
713 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
714 SDPatternOperator frag, X86MemOperand x86memop,
715 InstrItinClass itin> {
716 let isCodeGenOnly = 1 in {
717 def #NAME# : I<Opc, Form, (outs), (ins x86memop:$ptr),
718 !strconcat(mnemonic, "\t$ptr"),
719 [(frag addr:$ptr)], itin>, TB, LOCK;
723 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
724 string mnemonic, SDPatternOperator frag,
725 InstrItinClass itin8, InstrItinClass itin> {
726 let isCodeGenOnly = 1 in {
727 let Defs = [AL, EFLAGS], Uses = [AL] in
728 def #NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
729 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
730 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
731 let Defs = [AX, EFLAGS], Uses = [AX] in
732 def #NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
733 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
734 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;
735 let Defs = [EAX, EFLAGS], Uses = [EAX] in
736 def #NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
737 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
738 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;
739 let Defs = [RAX, EFLAGS], Uses = [RAX] in
740 def #NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
741 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
742 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
746 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
747 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
752 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
753 Predicates = [HasCmpxchg16b] in {
754 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
756 IIC_CMPX_LOCK_16B>, REX_W;
759 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
760 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
762 // Atomic exchange and add
763 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
765 InstrItinClass itin8, InstrItinClass itin> {
766 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
767 def #NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
768 (ins GR8:$val, i8mem:$ptr),
769 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
771 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
773 def #NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
774 (ins GR16:$val, i16mem:$ptr),
775 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
778 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
780 def #NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
781 (ins GR32:$val, i32mem:$ptr),
782 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
785 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
787 def #NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
788 (ins GR64:$val, i64mem:$ptr),
789 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
792 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
797 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
798 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
801 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
802 "#ACQUIRE_MOV PSEUDO!",
803 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
804 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
805 "#ACQUIRE_MOV PSEUDO!",
806 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
807 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
808 "#ACQUIRE_MOV PSEUDO!",
809 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
810 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
811 "#ACQUIRE_MOV PSEUDO!",
812 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
814 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
815 "#RELEASE_MOV PSEUDO!",
816 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
817 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
818 "#RELEASE_MOV PSEUDO!",
819 [(atomic_store_16 addr:$dst, GR16:$src)]>;
820 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
821 "#RELEASE_MOV PSEUDO!",
822 [(atomic_store_32 addr:$dst, GR32:$src)]>;
823 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
824 "#RELEASE_MOV PSEUDO!",
825 [(atomic_store_64 addr:$dst, GR64:$src)]>;
827 //===----------------------------------------------------------------------===//
828 // Conditional Move Pseudo Instructions.
829 //===----------------------------------------------------------------------===//
832 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
833 // instruction selection into a branch sequence.
834 let Uses = [EFLAGS], usesCustomInserter = 1 in {
835 def CMOV_FR32 : I<0, Pseudo,
836 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
837 "#CMOV_FR32 PSEUDO!",
838 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
840 def CMOV_FR64 : I<0, Pseudo,
841 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
842 "#CMOV_FR64 PSEUDO!",
843 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
845 def CMOV_V4F32 : I<0, Pseudo,
846 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
847 "#CMOV_V4F32 PSEUDO!",
849 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
851 def CMOV_V2F64 : I<0, Pseudo,
852 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
853 "#CMOV_V2F64 PSEUDO!",
855 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
857 def CMOV_V2I64 : I<0, Pseudo,
858 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
859 "#CMOV_V2I64 PSEUDO!",
861 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
863 def CMOV_V8F32 : I<0, Pseudo,
864 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
865 "#CMOV_V8F32 PSEUDO!",
867 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
869 def CMOV_V4F64 : I<0, Pseudo,
870 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
871 "#CMOV_V4F64 PSEUDO!",
873 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
875 def CMOV_V4I64 : I<0, Pseudo,
876 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
877 "#CMOV_V4I64 PSEUDO!",
879 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
884 //===----------------------------------------------------------------------===//
885 // DAG Pattern Matching Rules
886 //===----------------------------------------------------------------------===//
888 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
889 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
890 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
891 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
892 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
893 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
894 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
896 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
897 (ADD32ri GR32:$src1, tconstpool:$src2)>;
898 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
899 (ADD32ri GR32:$src1, tjumptable:$src2)>;
900 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
901 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
902 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
903 (ADD32ri GR32:$src1, texternalsym:$src2)>;
904 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
905 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
907 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
908 (MOV32mi addr:$dst, tglobaladdr:$src)>;
909 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
910 (MOV32mi addr:$dst, texternalsym:$src)>;
911 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
912 (MOV32mi addr:$dst, tblockaddress:$src)>;
916 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
917 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
918 // 'movabs' predicate should handle this sort of thing.
919 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
920 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
921 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
922 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
923 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
924 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
925 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
926 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
927 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
928 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
930 // In static codegen with small code model, we can get the address of a label
931 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
932 // the MOV64ri64i32 should accept these.
933 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
934 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
935 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
936 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
937 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
938 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
939 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
940 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
941 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
942 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
944 // In kernel code model, we can get the address of a label
945 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
946 // the MOV64ri32 should accept these.
947 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
948 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
949 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
950 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
951 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
952 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
953 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
954 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
955 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
956 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
958 // If we have small model and -static mode, it is safe to store global addresses
959 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
960 // for MOV64mi32 should handle this sort of thing.
961 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
962 (MOV64mi32 addr:$dst, tconstpool:$src)>,
963 Requires<[NearData, IsStatic]>;
964 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
965 (MOV64mi32 addr:$dst, tjumptable:$src)>,
966 Requires<[NearData, IsStatic]>;
967 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
968 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
969 Requires<[NearData, IsStatic]>;
970 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
971 (MOV64mi32 addr:$dst, texternalsym:$src)>,
972 Requires<[NearData, IsStatic]>;
973 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
974 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
975 Requires<[NearData, IsStatic]>;
981 // tls has some funny stuff here...
982 // This corresponds to movabs $foo@tpoff, %rax
983 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
984 (MOV64ri tglobaltlsaddr :$dst)>;
985 // This corresponds to add $foo@tpoff, %rax
986 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
987 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
988 // This corresponds to mov foo@tpoff(%rbx), %eax
989 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
990 (MOV64rm tglobaltlsaddr :$dst)>;
993 // Direct PC relative function call for small code model. 32-bit displacement
994 // sign extended to 64-bit.
995 def : Pat<(X86call (i64 tglobaladdr:$dst)),
996 (CALL64pcrel32 tglobaladdr:$dst)>;
997 def : Pat<(X86call (i64 texternalsym:$dst)),
998 (CALL64pcrel32 texternalsym:$dst)>;
1000 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1001 // can never use callee-saved registers. That is the purpose of the GR64_TC
1002 // register classes.
1004 // The only volatile register that is never used by the calling convention is
1005 // %r11. This happens when calling a vararg function with 6 arguments.
1007 // Match an X86tcret that uses less than 7 volatile registers.
1008 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1009 (X86tcret node:$ptr, node:$off), [{
1010 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1011 unsigned NumRegs = 0;
1012 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1013 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1018 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1019 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1020 Requires<[In32BitMode]>;
1022 // FIXME: This is disabled for 32-bit PIC mode because the global base
1023 // register which is part of the address mode may be assigned a
1024 // callee-saved register.
1025 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1026 (TCRETURNmi addr:$dst, imm:$off)>,
1027 Requires<[In32BitMode, IsNotPIC]>;
1029 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1030 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1031 Requires<[In32BitMode]>;
1033 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1034 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1035 Requires<[In32BitMode]>;
1037 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1038 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1039 Requires<[In64BitMode]>;
1041 // Don't fold loads into X86tcret requiring more than 6 regs.
1042 // There wouldn't be enough scratch registers for base+index.
1043 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1044 (TCRETURNmi64 addr:$dst, imm:$off)>,
1045 Requires<[In64BitMode]>;
1047 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1048 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1049 Requires<[In64BitMode]>;
1051 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1052 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1053 Requires<[In64BitMode]>;
1055 // Normal calls, with various flavors of addresses.
1056 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1057 (CALLpcrel32 tglobaladdr:$dst)>;
1058 def : Pat<(X86call (i32 texternalsym:$dst)),
1059 (CALLpcrel32 texternalsym:$dst)>;
1060 def : Pat<(X86call (i32 imm:$dst)),
1061 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1065 // TEST R,R is smaller than CMP R,0
1066 def : Pat<(X86cmp GR8:$src1, 0),
1067 (TEST8rr GR8:$src1, GR8:$src1)>;
1068 def : Pat<(X86cmp GR16:$src1, 0),
1069 (TEST16rr GR16:$src1, GR16:$src1)>;
1070 def : Pat<(X86cmp GR32:$src1, 0),
1071 (TEST32rr GR32:$src1, GR32:$src1)>;
1072 def : Pat<(X86cmp GR64:$src1, 0),
1073 (TEST64rr GR64:$src1, GR64:$src1)>;
1075 // Conditional moves with folded loads with operands swapped and conditions
1077 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1078 Instruction Inst64> {
1079 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1080 (Inst16 GR16:$src2, addr:$src1)>;
1081 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1082 (Inst32 GR32:$src2, addr:$src1)>;
1083 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1084 (Inst64 GR64:$src2, addr:$src1)>;
1087 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1088 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1089 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1090 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1091 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1092 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1093 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1094 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1095 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1096 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1097 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1098 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1099 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1100 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1101 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1102 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1104 // zextload bool -> zextload byte
1105 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1106 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1107 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1108 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1110 // extload bool -> extload byte
1111 // When extloading from 16-bit and smaller memory locations into 64-bit
1112 // registers, use zero-extending loads so that the entire 64-bit register is
1113 // defined, avoiding partial-register updates.
1115 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1116 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1117 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1118 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1119 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1120 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1122 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1123 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1124 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1125 // For other extloads, use subregs, since the high contents of the register are
1126 // defined after an extload.
1127 def : Pat<(extloadi64i32 addr:$src),
1128 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1131 // anyext. Define these to do an explicit zero-extend to
1132 // avoid partial-register updates.
1133 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1134 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1135 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1137 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1138 def : Pat<(i32 (anyext GR16:$src)),
1139 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1141 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1142 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1143 def : Pat<(i64 (anyext GR32:$src)),
1144 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1147 // Any instruction that defines a 32-bit result leaves the high half of the
1148 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1149 // be copying from a truncate. And x86's cmov doesn't do anything if the
1150 // condition is false. But any other 32-bit operation will zero-extend
1152 def def32 : PatLeaf<(i32 GR32:$src), [{
1153 return N->getOpcode() != ISD::TRUNCATE &&
1154 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1155 N->getOpcode() != ISD::CopyFromReg &&
1156 N->getOpcode() != X86ISD::CMOV;
1159 // In the case of a 32-bit def that is known to implicitly zero-extend,
1160 // we can use a SUBREG_TO_REG.
1161 def : Pat<(i64 (zext def32:$src)),
1162 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1164 //===----------------------------------------------------------------------===//
1165 // Pattern match OR as ADD
1166 //===----------------------------------------------------------------------===//
1168 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1169 // 3-addressified into an LEA instruction to avoid copies. However, we also
1170 // want to finally emit these instructions as an or at the end of the code
1171 // generator to make the generated code easier to read. To do this, we select
1172 // into "disjoint bits" pseudo ops.
1174 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1175 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1176 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1177 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1179 APInt KnownZero0, KnownOne0;
1180 CurDAG->ComputeMaskedBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1181 APInt KnownZero1, KnownOne1;
1182 CurDAG->ComputeMaskedBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1183 return (~KnownZero0 & ~KnownZero1) == 0;
1187 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1188 let AddedComplexity = 5 in { // Try this before the selecting to OR
1190 let isConvertibleToThreeAddress = 1,
1191 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1192 let isCommutable = 1 in {
1193 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1194 "", // orw/addw REG, REG
1195 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1196 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1197 "", // orl/addl REG, REG
1198 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1199 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1200 "", // orq/addq REG, REG
1201 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1204 // NOTE: These are order specific, we want the ri8 forms to be listed
1205 // first so that they are slightly preferred to the ri forms.
1207 def ADD16ri8_DB : I<0, Pseudo,
1208 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1209 "", // orw/addw REG, imm8
1210 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1211 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1212 "", // orw/addw REG, imm
1213 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1215 def ADD32ri8_DB : I<0, Pseudo,
1216 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1217 "", // orl/addl REG, imm8
1218 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1219 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1220 "", // orl/addl REG, imm
1221 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1224 def ADD64ri8_DB : I<0, Pseudo,
1225 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1226 "", // orq/addq REG, imm8
1227 [(set GR64:$dst, (or_is_add GR64:$src1,
1228 i64immSExt8:$src2))]>;
1229 def ADD64ri32_DB : I<0, Pseudo,
1230 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1231 "", // orq/addq REG, imm
1232 [(set GR64:$dst, (or_is_add GR64:$src1,
1233 i64immSExt32:$src2))]>;
1235 } // AddedComplexity
1238 //===----------------------------------------------------------------------===//
1240 //===----------------------------------------------------------------------===//
1242 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1243 // +128 doesn't, so in this special case use a sub instead of an add.
1244 def : Pat<(add GR16:$src1, 128),
1245 (SUB16ri8 GR16:$src1, -128)>;
1246 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1247 (SUB16mi8 addr:$dst, -128)>;
1249 def : Pat<(add GR32:$src1, 128),
1250 (SUB32ri8 GR32:$src1, -128)>;
1251 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1252 (SUB32mi8 addr:$dst, -128)>;
1254 def : Pat<(add GR64:$src1, 128),
1255 (SUB64ri8 GR64:$src1, -128)>;
1256 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1257 (SUB64mi8 addr:$dst, -128)>;
1259 // The same trick applies for 32-bit immediate fields in 64-bit
1261 def : Pat<(add GR64:$src1, 0x0000000080000000),
1262 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1263 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1264 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1266 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1267 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1268 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1269 // represented with a sign extension of a 8 bit constant, use that.
1271 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1275 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1276 (i32 (GetLo8XForm imm:$imm))),
1279 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1283 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1284 (i32 (GetLo32XForm imm:$imm))),
1288 // r & (2^16-1) ==> movz
1289 def : Pat<(and GR32:$src1, 0xffff),
1290 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1291 // r & (2^8-1) ==> movz
1292 def : Pat<(and GR32:$src1, 0xff),
1293 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1296 Requires<[In32BitMode]>;
1297 // r & (2^8-1) ==> movz
1298 def : Pat<(and GR16:$src1, 0xff),
1299 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1300 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1302 Requires<[In32BitMode]>;
1304 // r & (2^32-1) ==> movz
1305 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1306 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1307 // r & (2^16-1) ==> movz
1308 def : Pat<(and GR64:$src, 0xffff),
1309 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1310 // r & (2^8-1) ==> movz
1311 def : Pat<(and GR64:$src, 0xff),
1312 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1313 // r & (2^8-1) ==> movz
1314 def : Pat<(and GR32:$src1, 0xff),
1315 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1316 Requires<[In64BitMode]>;
1317 // r & (2^8-1) ==> movz
1318 def : Pat<(and GR16:$src1, 0xff),
1319 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1320 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1321 Requires<[In64BitMode]>;
1324 // sext_inreg patterns
1325 def : Pat<(sext_inreg GR32:$src, i16),
1326 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1327 def : Pat<(sext_inreg GR32:$src, i8),
1328 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1331 Requires<[In32BitMode]>;
1333 def : Pat<(sext_inreg GR16:$src, i8),
1334 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1335 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1337 Requires<[In32BitMode]>;
1339 def : Pat<(sext_inreg GR64:$src, i32),
1340 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1341 def : Pat<(sext_inreg GR64:$src, i16),
1342 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1343 def : Pat<(sext_inreg GR64:$src, i8),
1344 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1345 def : Pat<(sext_inreg GR32:$src, i8),
1346 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1347 Requires<[In64BitMode]>;
1348 def : Pat<(sext_inreg GR16:$src, i8),
1349 (EXTRACT_SUBREG (MOVSX32rr8
1350 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1351 Requires<[In64BitMode]>;
1353 // sext, sext_load, zext, zext_load
1354 def: Pat<(i16 (sext GR8:$src)),
1355 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1356 def: Pat<(sextloadi16i8 addr:$src),
1357 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1358 def: Pat<(i16 (zext GR8:$src)),
1359 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1360 def: Pat<(zextloadi16i8 addr:$src),
1361 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1364 def : Pat<(i16 (trunc GR32:$src)),
1365 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1366 def : Pat<(i8 (trunc GR32:$src)),
1367 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1369 Requires<[In32BitMode]>;
1370 def : Pat<(i8 (trunc GR16:$src)),
1371 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1373 Requires<[In32BitMode]>;
1374 def : Pat<(i32 (trunc GR64:$src)),
1375 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1376 def : Pat<(i16 (trunc GR64:$src)),
1377 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1378 def : Pat<(i8 (trunc GR64:$src)),
1379 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1380 def : Pat<(i8 (trunc GR32:$src)),
1381 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1382 Requires<[In64BitMode]>;
1383 def : Pat<(i8 (trunc GR16:$src)),
1384 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1385 Requires<[In64BitMode]>;
1387 // h-register tricks
1388 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1389 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1391 Requires<[In32BitMode]>;
1392 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1393 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1395 Requires<[In32BitMode]>;
1396 def : Pat<(srl GR16:$src, (i8 8)),
1399 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1402 Requires<[In32BitMode]>;
1403 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1404 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1407 Requires<[In32BitMode]>;
1408 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1409 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1412 Requires<[In32BitMode]>;
1413 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1414 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1417 Requires<[In32BitMode]>;
1418 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1419 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1422 Requires<[In32BitMode]>;
1424 // h-register tricks.
1425 // For now, be conservative on x86-64 and use an h-register extract only if the
1426 // value is immediately zero-extended or stored, which are somewhat common
1427 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1428 // from being allocated in the same instruction as the h register, as there's
1429 // currently no way to describe this requirement to the register allocator.
1431 // h-register extract and zero-extend.
1432 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1436 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1439 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1441 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1443 Requires<[In64BitMode]>;
1444 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1445 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1448 Requires<[In64BitMode]>;
1449 def : Pat<(srl GR16:$src, (i8 8)),
1452 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1455 Requires<[In64BitMode]>;
1456 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1458 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1460 Requires<[In64BitMode]>;
1461 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1463 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1465 Requires<[In64BitMode]>;
1466 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1470 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1473 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1477 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1481 // h-register extract and store.
1482 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1485 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1487 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1490 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1492 Requires<[In64BitMode]>;
1493 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1496 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1498 Requires<[In64BitMode]>;
1501 // (shl x, 1) ==> (add x, x)
1502 // Note that if x is undef (immediate or otherwise), we could theoretically
1503 // end up with the two uses of x getting different values, producing a result
1504 // where the least significant bit is not 0. However, the probability of this
1505 // happening is considered low enough that this is officially not a
1507 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1508 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1509 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1510 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1512 // Helper imms that check if a mask doesn't change significant shift bits.
1513 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1514 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1516 // (shl x (and y, 31)) ==> (shl x, y)
1517 def : Pat<(shl GR8:$src1, (and CL, immShift32)),
1518 (SHL8rCL GR8:$src1)>;
1519 def : Pat<(shl GR16:$src1, (and CL, immShift32)),
1520 (SHL16rCL GR16:$src1)>;
1521 def : Pat<(shl GR32:$src1, (and CL, immShift32)),
1522 (SHL32rCL GR32:$src1)>;
1523 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1524 (SHL8mCL addr:$dst)>;
1525 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1526 (SHL16mCL addr:$dst)>;
1527 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1528 (SHL32mCL addr:$dst)>;
1530 def : Pat<(srl GR8:$src1, (and CL, immShift32)),
1531 (SHR8rCL GR8:$src1)>;
1532 def : Pat<(srl GR16:$src1, (and CL, immShift32)),
1533 (SHR16rCL GR16:$src1)>;
1534 def : Pat<(srl GR32:$src1, (and CL, immShift32)),
1535 (SHR32rCL GR32:$src1)>;
1536 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1537 (SHR8mCL addr:$dst)>;
1538 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1539 (SHR16mCL addr:$dst)>;
1540 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1541 (SHR32mCL addr:$dst)>;
1543 def : Pat<(sra GR8:$src1, (and CL, immShift32)),
1544 (SAR8rCL GR8:$src1)>;
1545 def : Pat<(sra GR16:$src1, (and CL, immShift32)),
1546 (SAR16rCL GR16:$src1)>;
1547 def : Pat<(sra GR32:$src1, (and CL, immShift32)),
1548 (SAR32rCL GR32:$src1)>;
1549 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1550 (SAR8mCL addr:$dst)>;
1551 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1552 (SAR16mCL addr:$dst)>;
1553 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1554 (SAR32mCL addr:$dst)>;
1556 // (shl x (and y, 63)) ==> (shl x, y)
1557 def : Pat<(shl GR64:$src1, (and CL, immShift64)),
1558 (SHL64rCL GR64:$src1)>;
1559 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1560 (SHL64mCL addr:$dst)>;
1562 def : Pat<(srl GR64:$src1, (and CL, immShift64)),
1563 (SHR64rCL GR64:$src1)>;
1564 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1565 (SHR64mCL addr:$dst)>;
1567 def : Pat<(sra GR64:$src1, (and CL, immShift64)),
1568 (SAR64rCL GR64:$src1)>;
1569 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1570 (SAR64mCL addr:$dst)>;
1573 // (anyext (setcc_carry)) -> (setcc_carry)
1574 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1576 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1578 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1584 //===----------------------------------------------------------------------===//
1585 // EFLAGS-defining Patterns
1586 //===----------------------------------------------------------------------===//
1589 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1590 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1591 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1594 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1595 (ADD8rm GR8:$src1, addr:$src2)>;
1596 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1597 (ADD16rm GR16:$src1, addr:$src2)>;
1598 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1599 (ADD32rm GR32:$src1, addr:$src2)>;
1602 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1603 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1604 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1605 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1606 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1607 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1608 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1611 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1612 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1613 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1616 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1617 (SUB8rm GR8:$src1, addr:$src2)>;
1618 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1619 (SUB16rm GR16:$src1, addr:$src2)>;
1620 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1621 (SUB32rm GR32:$src1, addr:$src2)>;
1624 def : Pat<(sub GR8:$src1, imm:$src2),
1625 (SUB8ri GR8:$src1, imm:$src2)>;
1626 def : Pat<(sub GR16:$src1, imm:$src2),
1627 (SUB16ri GR16:$src1, imm:$src2)>;
1628 def : Pat<(sub GR32:$src1, imm:$src2),
1629 (SUB32ri GR32:$src1, imm:$src2)>;
1630 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1631 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1632 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1633 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1636 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1637 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1638 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1639 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1642 def : Pat<(mul GR16:$src1, GR16:$src2),
1643 (IMUL16rr GR16:$src1, GR16:$src2)>;
1644 def : Pat<(mul GR32:$src1, GR32:$src2),
1645 (IMUL32rr GR32:$src1, GR32:$src2)>;
1648 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1649 (IMUL16rm GR16:$src1, addr:$src2)>;
1650 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1651 (IMUL32rm GR32:$src1, addr:$src2)>;
1654 def : Pat<(mul GR16:$src1, imm:$src2),
1655 (IMUL16rri GR16:$src1, imm:$src2)>;
1656 def : Pat<(mul GR32:$src1, imm:$src2),
1657 (IMUL32rri GR32:$src1, imm:$src2)>;
1658 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1659 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1660 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1661 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1663 // reg = mul mem, imm
1664 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1665 (IMUL16rmi addr:$src1, imm:$src2)>;
1666 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1667 (IMUL32rmi addr:$src1, imm:$src2)>;
1668 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1669 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1670 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1671 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1673 // Patterns for nodes that do not produce flags, for instructions that do.
1676 def : Pat<(add GR64:$src1, GR64:$src2),
1677 (ADD64rr GR64:$src1, GR64:$src2)>;
1678 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1679 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1680 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1681 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1682 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1683 (ADD64rm GR64:$src1, addr:$src2)>;
1686 def : Pat<(sub GR64:$src1, GR64:$src2),
1687 (SUB64rr GR64:$src1, GR64:$src2)>;
1688 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1689 (SUB64rm GR64:$src1, addr:$src2)>;
1690 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1691 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1692 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1693 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1696 def : Pat<(mul GR64:$src1, GR64:$src2),
1697 (IMUL64rr GR64:$src1, GR64:$src2)>;
1698 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1699 (IMUL64rm GR64:$src1, addr:$src2)>;
1700 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1701 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1702 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1703 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1704 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1705 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1706 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1707 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1710 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1711 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1712 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1713 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1714 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1715 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1718 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1719 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1720 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1721 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1722 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1723 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1726 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1727 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1728 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1729 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1732 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1733 (OR8rm GR8:$src1, addr:$src2)>;
1734 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1735 (OR16rm GR16:$src1, addr:$src2)>;
1736 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1737 (OR32rm GR32:$src1, addr:$src2)>;
1738 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1739 (OR64rm GR64:$src1, addr:$src2)>;
1742 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1743 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1744 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1745 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1746 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1747 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1748 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1749 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1750 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1751 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1752 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1755 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1756 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1757 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1758 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1761 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1762 (XOR8rm GR8:$src1, addr:$src2)>;
1763 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1764 (XOR16rm GR16:$src1, addr:$src2)>;
1765 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1766 (XOR32rm GR32:$src1, addr:$src2)>;
1767 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1768 (XOR64rm GR64:$src1, addr:$src2)>;
1771 def : Pat<(xor GR8:$src1, imm:$src2),
1772 (XOR8ri GR8:$src1, imm:$src2)>;
1773 def : Pat<(xor GR16:$src1, imm:$src2),
1774 (XOR16ri GR16:$src1, imm:$src2)>;
1775 def : Pat<(xor GR32:$src1, imm:$src2),
1776 (XOR32ri GR32:$src1, imm:$src2)>;
1777 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1778 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1779 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1780 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1781 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1782 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1783 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1784 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1787 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1788 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1789 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1790 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1793 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1794 (AND8rm GR8:$src1, addr:$src2)>;
1795 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1796 (AND16rm GR16:$src1, addr:$src2)>;
1797 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1798 (AND32rm GR32:$src1, addr:$src2)>;
1799 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1800 (AND64rm GR64:$src1, addr:$src2)>;
1803 def : Pat<(and GR8:$src1, imm:$src2),
1804 (AND8ri GR8:$src1, imm:$src2)>;
1805 def : Pat<(and GR16:$src1, imm:$src2),
1806 (AND16ri GR16:$src1, imm:$src2)>;
1807 def : Pat<(and GR32:$src1, imm:$src2),
1808 (AND32ri GR32:$src1, imm:$src2)>;
1809 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1810 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1811 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1812 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1813 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1814 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1815 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1816 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1818 // Bit scan instruction patterns to match explicit zero-undef behavior.
1819 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1820 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1821 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1822 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1823 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1824 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;