1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
55 def : Pat<(X86callseq_start timm:$amt1),
56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
59 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
60 // a stack adjustment and the codegen must know that they may modify the stack
61 // pointer before prolog-epilog rewriting occurs.
62 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
63 // sub / add which can clobber EFLAGS.
64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
71 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
74 def : Pat<(X86callseq_start timm:$amt1),
75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
78 // x86-64 va_start lowering magic.
79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
83 i64imm:$regsavefi, i64imm:$offset,
85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
86 [(X86vastart_save_xmm_regs GR8:$al,
91 // The VAARG_64 pseudo-instruction takes the address of the va_list,
92 // and places the address of the next argument into a register.
93 let Defs = [EFLAGS] in
94 def VAARG_64 : I<0, Pseudo,
96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
97 "#VAARG_64 $dst, $ap, $size, $mode, $align",
99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
102 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
103 // targets. These calls are needed to probe the stack when allocating more than
104 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
105 // ensure that the guard pages used by the OS virtual memory manager are
106 // allocated in correct sequence.
107 // The main point of having separate instruction are extra unmodelled effects
108 // (compared to ordinary calls) like stack pointer change.
110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
112 "# dynamic stack allocation",
115 // When using segmented stacks these are lowered into instructions which first
116 // check if the current stacklet has enough free memory. If it does, memory is
117 // allocated by bumping the stack pointer. Otherwise memory is allocated from
120 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
121 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
122 "# variable sized alloca for segmented stacks",
124 (X86SegAlloca GR32:$size))]>,
127 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
128 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
129 "# variable sized alloca for segmented stacks",
131 (X86SegAlloca GR64:$size))]>,
132 Requires<[In64BitMode]>;
135 // The MSVC runtime contains an _ftol2 routine for converting floating-point
136 // to integer values. It has a strange calling convention: the input is
137 // popped from the x87 stack, and the return value is given in EDX:EAX. ECX is
138 // used as a temporary register. No other registers (aside from flags) are
140 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
141 // variant is unnecessary.
143 let Defs = [EAX, EDX, ECX, EFLAGS], FPForm = SpecialFP in {
144 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
146 [(X86WinFTOL RFP32:$src)]>,
147 Requires<[Not64BitMode]>;
149 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
151 [(X86WinFTOL RFP64:$src)]>,
152 Requires<[Not64BitMode]>;
155 //===----------------------------------------------------------------------===//
156 // EH Pseudo Instructions
158 let SchedRW = [WriteSystem] in {
159 let isTerminator = 1, isReturn = 1, isBarrier = 1,
160 hasCtrlDep = 1, isCodeGenOnly = 1 in {
161 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
162 "ret\t#eh_return, addr: $addr",
163 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
167 let isTerminator = 1, isReturn = 1, isBarrier = 1,
168 hasCtrlDep = 1, isCodeGenOnly = 1 in {
169 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
170 "ret\t#eh_return, addr: $addr",
171 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
175 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
176 usesCustomInserter = 1 in {
177 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
179 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
180 Requires<[Not64BitMode]>;
181 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
183 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
184 Requires<[In64BitMode]>;
185 let isTerminator = 1 in {
186 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
187 "#EH_SJLJ_LONGJMP32",
188 [(X86eh_sjlj_longjmp addr:$buf)]>,
189 Requires<[Not64BitMode]>;
190 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
191 "#EH_SJLJ_LONGJMP64",
192 [(X86eh_sjlj_longjmp addr:$buf)]>,
193 Requires<[In64BitMode]>;
198 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
199 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
200 "#EH_SjLj_Setup\t$dst", []>;
203 //===----------------------------------------------------------------------===//
204 // Pseudo instructions used by unwind info.
206 let isPseudo = 1 in {
207 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
208 "#SEH_PushReg $reg", []>;
209 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
210 "#SEH_SaveReg $reg, $dst", []>;
211 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
212 "#SEH_SaveXMM $reg, $dst", []>;
213 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
214 "#SEH_StackAlloc $size", []>;
215 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
216 "#SEH_SetFrame $reg, $offset", []>;
217 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
218 "#SEH_PushFrame $mode", []>;
219 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
220 "#SEH_EndPrologue", []>;
221 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
222 "#SEH_Epilogue", []>;
225 //===----------------------------------------------------------------------===//
226 // Pseudo instructions used by segmented stacks.
229 // This is lowered into a RET instruction by MCInstLower. We need
230 // this so that we don't have to have a MachineBasicBlock which ends
231 // with a RET and also has successors.
232 let isPseudo = 1 in {
233 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
236 // This instruction is lowered to a RET followed by a MOV. The two
237 // instructions are not generated on a higher level since then the
238 // verifier sees a MachineBasicBlock ending with a non-terminator.
239 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
243 //===----------------------------------------------------------------------===//
244 // Alias Instructions
245 //===----------------------------------------------------------------------===//
247 // Alias instruction mapping movr0 to xor.
248 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
249 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
251 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
252 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
254 // Other widths can also make use of the 32-bit xor, which may have a smaller
255 // encoding and avoid partial register updates.
256 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
257 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
258 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
259 let AddedComplexity = 20;
262 // Materialize i64 constant where top 32-bits are zero. This could theoretically
263 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
264 // that would make it more difficult to rematerialize.
265 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
266 isCodeGenOnly = 1, hasSideEffects = 0 in
267 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
268 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
270 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
271 // actually the zero-extension of a 32-bit constant, and for labels in the
272 // x86-64 small code model.
273 def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>;
275 let AddedComplexity = 1 in
276 def : Pat<(i64 mov64imm32:$src),
277 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
279 // Use sbb to materialize carry bit.
280 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
281 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
282 // However, Pat<> can't replicate the destination reg into the inputs of the
284 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
285 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
286 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
287 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
288 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
289 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
290 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
291 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
295 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
297 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
299 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
302 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
304 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
306 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
309 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
310 // will be eliminated and that the sbb can be extended up to a wider type. When
311 // this happens, it is great. However, if we are left with an 8-bit sbb and an
312 // and, we might as well just match it as a setb.
313 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
316 // (add OP, SETB) -> (adc OP, 0)
317 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
318 (ADC8ri GR8:$op, 0)>;
319 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
320 (ADC32ri8 GR32:$op, 0)>;
321 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
322 (ADC64ri8 GR64:$op, 0)>;
324 // (sub OP, SETB) -> (sbb OP, 0)
325 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
326 (SBB8ri GR8:$op, 0)>;
327 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
328 (SBB32ri8 GR32:$op, 0)>;
329 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
330 (SBB64ri8 GR64:$op, 0)>;
332 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
333 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
334 (ADC8ri GR8:$op, 0)>;
335 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
336 (ADC32ri8 GR32:$op, 0)>;
337 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
338 (ADC64ri8 GR64:$op, 0)>;
340 //===----------------------------------------------------------------------===//
341 // String Pseudo Instructions
343 let SchedRW = [WriteMicrocoded] in {
344 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
345 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
346 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
347 Requires<[Not64BitMode]>;
348 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
349 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
350 Requires<[Not64BitMode]>;
351 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
352 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
353 Requires<[Not64BitMode]>;
356 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
357 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
358 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
359 Requires<[In64BitMode]>;
360 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
361 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
362 Requires<[In64BitMode]>;
363 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
364 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
365 Requires<[In64BitMode]>;
366 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
367 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
368 Requires<[In64BitMode]>;
371 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
372 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
373 let Uses = [AL,ECX,EDI] in
374 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
375 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
376 Requires<[Not64BitMode]>;
377 let Uses = [AX,ECX,EDI] in
378 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
379 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
380 Requires<[Not64BitMode]>;
381 let Uses = [EAX,ECX,EDI] in
382 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
383 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
384 Requires<[Not64BitMode]>;
387 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
388 let Uses = [AL,RCX,RDI] in
389 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
390 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
391 Requires<[In64BitMode]>;
392 let Uses = [AX,RCX,RDI] in
393 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
394 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
395 Requires<[In64BitMode]>;
396 let Uses = [RAX,RCX,RDI] in
397 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
398 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
399 Requires<[In64BitMode]>;
401 let Uses = [RAX,RCX,RDI] in
402 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
403 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
404 Requires<[In64BitMode]>;
408 //===----------------------------------------------------------------------===//
409 // Thread Local Storage Instructions
413 // All calls clobber the non-callee saved registers. ESP is marked as
414 // a use to prevent stack-pointer assignments that appear immediately
415 // before calls from potentially appearing dead.
416 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
417 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
418 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
419 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
420 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
422 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
424 [(X86tlsaddr tls32addr:$sym)]>,
425 Requires<[Not64BitMode]>;
426 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
428 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
429 Requires<[Not64BitMode]>;
432 // All calls clobber the non-callee saved registers. RSP is marked as
433 // a use to prevent stack-pointer assignments that appear immediately
434 // before calls from potentially appearing dead.
435 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
436 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
437 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
438 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
439 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
440 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
442 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
444 [(X86tlsaddr tls64addr:$sym)]>,
445 Requires<[In64BitMode]>;
446 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
448 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
449 Requires<[In64BitMode]>;
452 // Darwin TLS Support
453 // For i386, the address of the thunk is passed on the stack, on return the
454 // address of the variable is in %eax. %ecx is trashed during the function
455 // call. All other registers are preserved.
456 let Defs = [EAX, ECX, EFLAGS],
458 usesCustomInserter = 1 in
459 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
461 [(X86TLSCall addr:$sym)]>,
462 Requires<[Not64BitMode]>;
464 // For x86_64, the address of the thunk is passed in %rdi, on return
465 // the address of the variable is in %rax. All other registers are preserved.
466 let Defs = [RAX, EFLAGS],
468 usesCustomInserter = 1 in
469 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
471 [(X86TLSCall addr:$sym)]>,
472 Requires<[In64BitMode]>;
475 //===----------------------------------------------------------------------===//
476 // Conditional Move Pseudo Instructions
478 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
479 // instruction selection into a branch sequence.
480 multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
481 def CMOV#NAME : I<0, Pseudo,
482 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
483 "#CMOV_"#NAME#" PSEUDO!",
484 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond,
488 let usesCustomInserter = 1, Uses = [EFLAGS] in {
489 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
490 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
491 // however that requires promoting the operands, and can induce additional
492 // i8 register pressure.
493 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
495 let Predicates = [NoCMov] in {
496 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
497 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
498 } // Predicates = [NoCMov]
500 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
502 let Predicates = [FPStackf32] in
503 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
505 let Predicates = [FPStackf64] in
506 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
508 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
510 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;
511 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;
512 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>;
513 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>;
514 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>;
515 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>;
516 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
517 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>;
518 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
519 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
520 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
521 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
522 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
523 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
524 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
525 } // usesCustomInserter = 1, Uses = [EFLAGS]
527 //===----------------------------------------------------------------------===//
528 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
529 //===----------------------------------------------------------------------===//
531 // FIXME: Use normal instructions and add lock prefix dynamically.
535 // TODO: Get this to fold the constant into the instruction.
536 let isCodeGenOnly = 1, Defs = [EFLAGS] in
537 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
538 "or{l}\t{$zero, $dst|$dst, $zero}",
539 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
540 Sched<[WriteALULd, WriteRMW]>;
542 let hasSideEffects = 1 in
543 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
545 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
547 // RegOpc corresponds to the mr version of the instruction
548 // ImmOpc corresponds to the mi version of the instruction
549 // ImmOpc8 corresponds to the mi8 version of the instruction
550 // ImmMod corresponds to the instruction format of the mi and mi8 versions
551 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
552 Format ImmMod, string mnemonic> {
553 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
554 SchedRW = [WriteALULd, WriteRMW] in {
556 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
557 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
558 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
559 !strconcat(mnemonic, "{b}\t",
560 "{$src2, $dst|$dst, $src2}"),
561 [], IIC_ALU_NONMEM>, LOCK;
562 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
563 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
564 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
565 !strconcat(mnemonic, "{w}\t",
566 "{$src2, $dst|$dst, $src2}"),
567 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
568 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
569 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
570 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
571 !strconcat(mnemonic, "{l}\t",
572 "{$src2, $dst|$dst, $src2}"),
573 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
574 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
575 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
576 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
577 !strconcat(mnemonic, "{q}\t",
578 "{$src2, $dst|$dst, $src2}"),
579 [], IIC_ALU_NONMEM>, LOCK;
581 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
582 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
583 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
584 !strconcat(mnemonic, "{b}\t",
585 "{$src2, $dst|$dst, $src2}"),
586 [], IIC_ALU_MEM>, LOCK;
588 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
589 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
590 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
591 !strconcat(mnemonic, "{w}\t",
592 "{$src2, $dst|$dst, $src2}"),
593 [], IIC_ALU_MEM>, OpSize16, LOCK;
595 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
596 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
597 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
598 !strconcat(mnemonic, "{l}\t",
599 "{$src2, $dst|$dst, $src2}"),
600 [], IIC_ALU_MEM>, OpSize32, LOCK;
602 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
603 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
604 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
605 !strconcat(mnemonic, "{q}\t",
606 "{$src2, $dst|$dst, $src2}"),
607 [], IIC_ALU_MEM>, LOCK;
609 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
610 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
611 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
612 !strconcat(mnemonic, "{w}\t",
613 "{$src2, $dst|$dst, $src2}"),
614 [], IIC_ALU_MEM>, OpSize16, LOCK;
615 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
616 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
617 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
618 !strconcat(mnemonic, "{l}\t",
619 "{$src2, $dst|$dst, $src2}"),
620 [], IIC_ALU_MEM>, OpSize32, LOCK;
621 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
622 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
623 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
624 !strconcat(mnemonic, "{q}\t",
625 "{$src2, $dst|$dst, $src2}"),
626 [], IIC_ALU_MEM>, LOCK;
632 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
633 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
634 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
635 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
636 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
638 // Optimized codegen when the non-memory output is not used.
639 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
641 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
642 SchedRW = [WriteALULd, WriteRMW] in {
644 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
645 !strconcat(mnemonic, "{b}\t$dst"),
646 [], IIC_UNARY_MEM>, LOCK;
647 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
648 !strconcat(mnemonic, "{w}\t$dst"),
649 [], IIC_UNARY_MEM>, OpSize16, LOCK;
650 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
651 !strconcat(mnemonic, "{l}\t$dst"),
652 [], IIC_UNARY_MEM>, OpSize32, LOCK;
653 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
654 !strconcat(mnemonic, "{q}\t$dst"),
655 [], IIC_UNARY_MEM>, LOCK;
659 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
660 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
662 // Atomic compare and swap.
663 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
664 SDPatternOperator frag, X86MemOperand x86memop,
665 InstrItinClass itin> {
666 let isCodeGenOnly = 1 in {
667 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
668 !strconcat(mnemonic, "\t$ptr"),
669 [(frag addr:$ptr)], itin>, TB, LOCK;
673 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
674 string mnemonic, SDPatternOperator frag,
675 InstrItinClass itin8, InstrItinClass itin> {
676 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
677 let Defs = [AL, EFLAGS], Uses = [AL] in
678 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
679 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
680 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
681 let Defs = [AX, EFLAGS], Uses = [AX] in
682 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
683 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
684 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
685 let Defs = [EAX, EFLAGS], Uses = [EAX] in
686 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
687 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
688 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
689 let Defs = [RAX, EFLAGS], Uses = [RAX] in
690 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
691 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
692 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
696 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
697 SchedRW = [WriteALULd, WriteRMW] in {
698 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
703 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
704 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
705 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
707 IIC_CMPX_LOCK_16B>, REX_W;
710 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
711 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
713 // Atomic exchange and add
714 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
716 InstrItinClass itin8, InstrItinClass itin> {
717 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
718 SchedRW = [WriteALULd, WriteRMW] in {
719 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
720 (ins GR8:$val, i8mem:$ptr),
721 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
723 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
725 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
726 (ins GR16:$val, i16mem:$ptr),
727 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
730 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
732 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
733 (ins GR32:$val, i32mem:$ptr),
734 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
737 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
739 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
740 (ins GR64:$val, i64mem:$ptr),
741 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
744 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
749 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
750 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
753 /* The following multiclass tries to make sure that in code like
754 * x.store (immediate op x.load(acquire), release)
756 * x.store (register op x.load(acquire), release)
757 * an operation directly on memory is generated instead of wasting a register.
758 * It is not automatic as atomic_store/load are only lowered to MOV instructions
759 * extremely late to prevent them from being accidentally reordered in the backend
760 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
762 multiclass RELEASE_BINOP_MI<SDNode op> {
763 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
764 "#BINOP "#NAME#"8mi PSEUDO!",
765 [(atomic_store_8 addr:$dst, (op
766 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
767 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src),
768 "#BINOP "#NAME#"8mr PSEUDO!",
769 [(atomic_store_8 addr:$dst, (op
770 (atomic_load_8 addr:$dst), GR8:$src))]>;
771 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
772 // costly and avoided as far as possible by this backend anyway
773 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
774 "#BINOP "#NAME#"32mi PSEUDO!",
775 [(atomic_store_32 addr:$dst, (op
776 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
777 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
778 "#BINOP "#NAME#"32mr PSEUDO!",
779 [(atomic_store_32 addr:$dst, (op
780 (atomic_load_32 addr:$dst), GR32:$src))]>;
781 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
782 "#BINOP "#NAME#"64mi32 PSEUDO!",
783 [(atomic_store_64 addr:$dst, (op
784 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
785 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
786 "#BINOP "#NAME#"64mr PSEUDO!",
787 [(atomic_store_64 addr:$dst, (op
788 (atomic_load_64 addr:$dst), GR64:$src))]>;
790 defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
791 defm RELEASE_AND : RELEASE_BINOP_MI<and>;
792 defm RELEASE_OR : RELEASE_BINOP_MI<or>;
793 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>;
794 // Note: we don't deal with sub, because substractions of constants are
795 // optimized into additions before this code can run
797 // Same as above, but for floating-point.
798 // FIXME: imm version.
799 // FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
800 // FIXME: This could also handle SIMD operations with *ps and *pd instructions.
801 let usesCustomInserter = 1 in {
802 multiclass RELEASE_FP_BINOP_MI<SDNode op> {
803 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
804 "#BINOP "#NAME#"32mr PSEUDO!",
805 [(atomic_store_32 addr:$dst,
807 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))),
808 FR32:$src))))]>, Requires<[HasSSE1]>;
809 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src),
810 "#BINOP "#NAME#"64mr PSEUDO!",
811 [(atomic_store_64 addr:$dst,
813 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))),
814 FR64:$src))))]>, Requires<[HasSSE2]>;
816 defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>;
817 // FIXME: Add fsub, fmul, fdiv, ...
820 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
821 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
822 "#UNOP "#NAME#"8m PSEUDO!",
823 [(atomic_store_8 addr:$dst, dag8)]>;
824 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
825 "#UNOP "#NAME#"16m PSEUDO!",
826 [(atomic_store_16 addr:$dst, dag16)]>;
827 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
828 "#UNOP "#NAME#"32m PSEUDO!",
829 [(atomic_store_32 addr:$dst, dag32)]>;
830 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
831 "#UNOP "#NAME#"64m PSEUDO!",
832 [(atomic_store_64 addr:$dst, dag64)]>;
835 defm RELEASE_INC : RELEASE_UNOP<
836 (add (atomic_load_8 addr:$dst), (i8 1)),
837 (add (atomic_load_16 addr:$dst), (i16 1)),
838 (add (atomic_load_32 addr:$dst), (i32 1)),
839 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>;
840 defm RELEASE_DEC : RELEASE_UNOP<
841 (add (atomic_load_8 addr:$dst), (i8 -1)),
842 (add (atomic_load_16 addr:$dst), (i16 -1)),
843 (add (atomic_load_32 addr:$dst), (i32 -1)),
844 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>;
846 TODO: These don't work because the type inference of TableGen fails.
847 TODO: find a way to fix it.
848 defm RELEASE_NEG : RELEASE_UNOP<
849 (ineg (atomic_load_8 addr:$dst)),
850 (ineg (atomic_load_16 addr:$dst)),
851 (ineg (atomic_load_32 addr:$dst)),
852 (ineg (atomic_load_64 addr:$dst))>;
853 defm RELEASE_NOT : RELEASE_UNOP<
854 (not (atomic_load_8 addr:$dst)),
855 (not (atomic_load_16 addr:$dst)),
856 (not (atomic_load_32 addr:$dst)),
857 (not (atomic_load_64 addr:$dst))>;
860 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
861 "#RELEASE_MOV8mi PSEUDO!",
862 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
863 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
864 "#RELEASE_MOV16mi PSEUDO!",
865 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
866 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
867 "#RELEASE_MOV32mi PSEUDO!",
868 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
869 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
870 "#RELEASE_MOV64mi32 PSEUDO!",
871 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
873 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
874 "#RELEASE_MOV8mr PSEUDO!",
875 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
876 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
877 "#RELEASE_MOV16mr PSEUDO!",
878 [(atomic_store_16 addr:$dst, GR16:$src)]>;
879 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
880 "#RELEASE_MOV32mr PSEUDO!",
881 [(atomic_store_32 addr:$dst, GR32:$src)]>;
882 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
883 "#RELEASE_MOV64mr PSEUDO!",
884 [(atomic_store_64 addr:$dst, GR64:$src)]>;
886 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
887 "#ACQUIRE_MOV8rm PSEUDO!",
888 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
889 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
890 "#ACQUIRE_MOV16rm PSEUDO!",
891 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
892 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
893 "#ACQUIRE_MOV32rm PSEUDO!",
894 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
895 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
896 "#ACQUIRE_MOV64rm PSEUDO!",
897 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
899 //===----------------------------------------------------------------------===//
900 // DAG Pattern Matching Rules
901 //===----------------------------------------------------------------------===//
903 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
904 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
905 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
906 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
907 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
908 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
909 def : Pat<(i32 (X86Wrapper mcsym:$dst)), (MOV32ri mcsym:$dst)>;
910 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
912 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
913 (ADD32ri GR32:$src1, tconstpool:$src2)>;
914 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
915 (ADD32ri GR32:$src1, tjumptable:$src2)>;
916 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
917 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
918 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
919 (ADD32ri GR32:$src1, texternalsym:$src2)>;
920 def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)),
921 (ADD32ri GR32:$src1, mcsym:$src2)>;
922 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
923 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
925 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
926 (MOV32mi addr:$dst, tglobaladdr:$src)>;
927 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
928 (MOV32mi addr:$dst, texternalsym:$src)>;
929 def : Pat<(store (i32 (X86Wrapper mcsym:$src)), addr:$dst),
930 (MOV32mi addr:$dst, mcsym:$src)>;
931 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
932 (MOV32mi addr:$dst, tblockaddress:$src)>;
934 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
935 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
936 // 'movabs' predicate should handle this sort of thing.
937 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
938 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
939 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
940 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
941 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
942 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
943 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
944 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
945 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
946 (MOV64ri mcsym:$dst)>, Requires<[FarData]>;
947 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
948 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
950 // In kernel code model, we can get the address of a label
951 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
952 // the MOV64ri32 should accept these.
953 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
954 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
955 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
956 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
957 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
958 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
959 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
960 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
961 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
962 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;
963 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
964 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
966 // If we have small model and -static mode, it is safe to store global addresses
967 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
968 // for MOV64mi32 should handle this sort of thing.
969 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
970 (MOV64mi32 addr:$dst, tconstpool:$src)>,
971 Requires<[NearData, IsStatic]>;
972 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
973 (MOV64mi32 addr:$dst, tjumptable:$src)>,
974 Requires<[NearData, IsStatic]>;
975 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
976 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
977 Requires<[NearData, IsStatic]>;
978 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
979 (MOV64mi32 addr:$dst, texternalsym:$src)>,
980 Requires<[NearData, IsStatic]>;
981 def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),
982 (MOV64mi32 addr:$dst, mcsym:$src)>,
983 Requires<[NearData, IsStatic]>;
984 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
985 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
986 Requires<[NearData, IsStatic]>;
988 def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;
989 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
993 // tls has some funny stuff here...
994 // This corresponds to movabs $foo@tpoff, %rax
995 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
996 (MOV64ri32 tglobaltlsaddr :$dst)>;
997 // This corresponds to add $foo@tpoff, %rax
998 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
999 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1002 // Direct PC relative function call for small code model. 32-bit displacement
1003 // sign extended to 64-bit.
1004 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1005 (CALL64pcrel32 tglobaladdr:$dst)>;
1006 def : Pat<(X86call (i64 texternalsym:$dst)),
1007 (CALL64pcrel32 texternalsym:$dst)>;
1009 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1010 // can never use callee-saved registers. That is the purpose of the GR64_TC
1011 // register classes.
1013 // The only volatile register that is never used by the calling convention is
1014 // %r11. This happens when calling a vararg function with 6 arguments.
1016 // Match an X86tcret that uses less than 7 volatile registers.
1017 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1018 (X86tcret node:$ptr, node:$off), [{
1019 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1020 unsigned NumRegs = 0;
1021 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1022 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1027 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1028 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1029 Requires<[Not64BitMode]>;
1031 // FIXME: This is disabled for 32-bit PIC mode because the global base
1032 // register which is part of the address mode may be assigned a
1033 // callee-saved register.
1034 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1035 (TCRETURNmi addr:$dst, imm:$off)>,
1036 Requires<[Not64BitMode, IsNotPIC]>;
1038 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1039 (TCRETURNdi tglobaladdr:$dst, imm:$off)>,
1040 Requires<[NotLP64]>;
1042 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1043 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1044 Requires<[NotLP64]>;
1046 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1047 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1048 Requires<[In64BitMode]>;
1050 // Don't fold loads into X86tcret requiring more than 6 regs.
1051 // There wouldn't be enough scratch registers for base+index.
1052 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1053 (TCRETURNmi64 addr:$dst, imm:$off)>,
1054 Requires<[In64BitMode]>;
1056 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1057 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1060 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1061 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1064 // Normal calls, with various flavors of addresses.
1065 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1066 (CALLpcrel32 tglobaladdr:$dst)>;
1067 def : Pat<(X86call (i32 texternalsym:$dst)),
1068 (CALLpcrel32 texternalsym:$dst)>;
1069 def : Pat<(X86call (i32 imm:$dst)),
1070 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1074 // TEST R,R is smaller than CMP R,0
1075 def : Pat<(X86cmp GR8:$src1, 0),
1076 (TEST8rr GR8:$src1, GR8:$src1)>;
1077 def : Pat<(X86cmp GR16:$src1, 0),
1078 (TEST16rr GR16:$src1, GR16:$src1)>;
1079 def : Pat<(X86cmp GR32:$src1, 0),
1080 (TEST32rr GR32:$src1, GR32:$src1)>;
1081 def : Pat<(X86cmp GR64:$src1, 0),
1082 (TEST64rr GR64:$src1, GR64:$src1)>;
1084 // Conditional moves with folded loads with operands swapped and conditions
1086 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1087 Instruction Inst64> {
1088 let Predicates = [HasCMov] in {
1089 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1090 (Inst16 GR16:$src2, addr:$src1)>;
1091 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1092 (Inst32 GR32:$src2, addr:$src1)>;
1093 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1094 (Inst64 GR64:$src2, addr:$src1)>;
1098 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1099 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1100 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1101 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1102 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1103 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1104 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1105 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1106 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1107 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1108 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1109 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1110 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1111 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1112 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1113 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1115 // zextload bool -> zextload byte
1116 def : Pat<(zextloadi8i1 addr:$src), (AND8ri (MOV8rm addr:$src), (i8 1))>;
1117 def : Pat<(zextloadi16i1 addr:$src), (AND16ri8 (MOVZX16rm8 addr:$src), (i16 1))>;
1118 def : Pat<(zextloadi32i1 addr:$src), (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1))>;
1119 def : Pat<(zextloadi64i1 addr:$src),
1120 (SUBREG_TO_REG (i64 0),
1121 (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), sub_32bit)>;
1123 // extload bool -> extload byte
1124 // When extloading from 16-bit and smaller memory locations into 64-bit
1125 // registers, use zero-extending loads so that the entire 64-bit register is
1126 // defined, avoiding partial-register updates.
1128 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1129 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1130 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1131 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1132 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1133 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1135 // For other extloads, use subregs, since the high contents of the register are
1136 // defined after an extload.
1137 def : Pat<(extloadi64i1 addr:$src),
1138 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1139 def : Pat<(extloadi64i8 addr:$src),
1140 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1141 def : Pat<(extloadi64i16 addr:$src),
1142 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1143 def : Pat<(extloadi64i32 addr:$src),
1144 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1146 // anyext. Define these to do an explicit zero-extend to
1147 // avoid partial-register updates.
1148 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1149 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1150 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1152 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1153 def : Pat<(i32 (anyext GR16:$src)),
1154 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1156 def : Pat<(i64 (anyext GR8 :$src)),
1157 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1158 def : Pat<(i64 (anyext GR16:$src)),
1159 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1160 def : Pat<(i64 (anyext GR32:$src)),
1161 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1164 // Any instruction that defines a 32-bit result leaves the high half of the
1165 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1166 // be copying from a truncate. And x86's cmov doesn't do anything if the
1167 // condition is false. But any other 32-bit operation will zero-extend
1169 def def32 : PatLeaf<(i32 GR32:$src), [{
1170 return N->getOpcode() != ISD::TRUNCATE &&
1171 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1172 N->getOpcode() != ISD::CopyFromReg &&
1173 N->getOpcode() != ISD::AssertSext &&
1174 N->getOpcode() != X86ISD::CMOV;
1177 // In the case of a 32-bit def that is known to implicitly zero-extend,
1178 // we can use a SUBREG_TO_REG.
1179 def : Pat<(i64 (zext def32:$src)),
1180 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1182 //===----------------------------------------------------------------------===//
1183 // Pattern match OR as ADD
1184 //===----------------------------------------------------------------------===//
1186 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1187 // 3-addressified into an LEA instruction to avoid copies. However, we also
1188 // want to finally emit these instructions as an or at the end of the code
1189 // generator to make the generated code easier to read. To do this, we select
1190 // into "disjoint bits" pseudo ops.
1192 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1193 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1194 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1195 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1197 APInt KnownZero0, KnownOne0;
1198 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1199 APInt KnownZero1, KnownOne1;
1200 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1201 return (~KnownZero0 & ~KnownZero1) == 0;
1205 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1206 // Try this before the selecting to OR.
1207 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1209 let isConvertibleToThreeAddress = 1,
1210 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1211 let isCommutable = 1 in {
1212 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1213 "", // orw/addw REG, REG
1214 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1215 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1216 "", // orl/addl REG, REG
1217 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1218 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1219 "", // orq/addq REG, REG
1220 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1223 // NOTE: These are order specific, we want the ri8 forms to be listed
1224 // first so that they are slightly preferred to the ri forms.
1226 def ADD16ri8_DB : I<0, Pseudo,
1227 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1228 "", // orw/addw REG, imm8
1229 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1230 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1231 "", // orw/addw REG, imm
1232 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1234 def ADD32ri8_DB : I<0, Pseudo,
1235 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1236 "", // orl/addl REG, imm8
1237 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1238 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1239 "", // orl/addl REG, imm
1240 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1243 def ADD64ri8_DB : I<0, Pseudo,
1244 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1245 "", // orq/addq REG, imm8
1246 [(set GR64:$dst, (or_is_add GR64:$src1,
1247 i64immSExt8:$src2))]>;
1248 def ADD64ri32_DB : I<0, Pseudo,
1249 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1250 "", // orq/addq REG, imm
1251 [(set GR64:$dst, (or_is_add GR64:$src1,
1252 i64immSExt32:$src2))]>;
1254 } // AddedComplexity, SchedRW
1257 //===----------------------------------------------------------------------===//
1259 //===----------------------------------------------------------------------===//
1261 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1262 // +128 doesn't, so in this special case use a sub instead of an add.
1263 def : Pat<(add GR16:$src1, 128),
1264 (SUB16ri8 GR16:$src1, -128)>;
1265 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1266 (SUB16mi8 addr:$dst, -128)>;
1268 def : Pat<(add GR32:$src1, 128),
1269 (SUB32ri8 GR32:$src1, -128)>;
1270 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1271 (SUB32mi8 addr:$dst, -128)>;
1273 def : Pat<(add GR64:$src1, 128),
1274 (SUB64ri8 GR64:$src1, -128)>;
1275 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1276 (SUB64mi8 addr:$dst, -128)>;
1278 // The same trick applies for 32-bit immediate fields in 64-bit
1280 def : Pat<(add GR64:$src1, 0x0000000080000000),
1281 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1282 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1283 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1285 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1286 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1287 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1288 // represented with a sign extension of a 8 bit constant, use that.
1289 // This can also reduce instruction size by eliminating the need for the REX
1292 // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.
1293 let AddedComplexity = 1 in {
1294 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1298 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1299 (i32 (GetLo8XForm imm:$imm))),
1302 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1306 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1307 (i32 (GetLo32XForm imm:$imm))),
1309 } // AddedComplexity = 1
1312 // AddedComplexity is needed due to the increased complexity on the
1313 // i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all
1314 // the MOVZX patterns keeps thems together in DAGIsel tables.
1315 let AddedComplexity = 1 in {
1316 // r & (2^16-1) ==> movz
1317 def : Pat<(and GR32:$src1, 0xffff),
1318 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1319 // r & (2^8-1) ==> movz
1320 def : Pat<(and GR32:$src1, 0xff),
1321 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1324 Requires<[Not64BitMode]>;
1325 // r & (2^8-1) ==> movz
1326 def : Pat<(and GR16:$src1, 0xff),
1327 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1328 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1330 Requires<[Not64BitMode]>;
1332 // r & (2^32-1) ==> movz
1333 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1334 (SUBREG_TO_REG (i64 0),
1335 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1337 // r & (2^16-1) ==> movz
1338 let AddedComplexity = 1 in // Give priority over i64immZExt32.
1339 def : Pat<(and GR64:$src, 0xffff),
1340 (SUBREG_TO_REG (i64 0),
1341 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1343 // r & (2^8-1) ==> movz
1344 def : Pat<(and GR64:$src, 0xff),
1345 (SUBREG_TO_REG (i64 0),
1346 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1348 // r & (2^8-1) ==> movz
1349 def : Pat<(and GR32:$src1, 0xff),
1350 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1351 Requires<[In64BitMode]>;
1352 // r & (2^8-1) ==> movz
1353 def : Pat<(and GR16:$src1, 0xff),
1354 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1355 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1356 Requires<[In64BitMode]>;
1357 } // AddedComplexity = 1
1360 // sext_inreg patterns
1361 def : Pat<(sext_inreg GR32:$src, i16),
1362 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1363 def : Pat<(sext_inreg GR32:$src, i8),
1364 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1367 Requires<[Not64BitMode]>;
1369 def : Pat<(sext_inreg GR16:$src, i8),
1370 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1371 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1373 Requires<[Not64BitMode]>;
1375 def : Pat<(sext_inreg GR64:$src, i32),
1376 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1377 def : Pat<(sext_inreg GR64:$src, i16),
1378 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1379 def : Pat<(sext_inreg GR64:$src, i8),
1380 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1381 def : Pat<(sext_inreg GR32:$src, i8),
1382 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1383 Requires<[In64BitMode]>;
1384 def : Pat<(sext_inreg GR16:$src, i8),
1385 (EXTRACT_SUBREG (MOVSX32rr8
1386 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1387 Requires<[In64BitMode]>;
1389 // sext, sext_load, zext, zext_load
1390 def: Pat<(i16 (sext GR8:$src)),
1391 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1392 def: Pat<(sextloadi16i8 addr:$src),
1393 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1394 def: Pat<(i16 (zext GR8:$src)),
1395 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1396 def: Pat<(zextloadi16i8 addr:$src),
1397 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1400 def : Pat<(i16 (trunc GR32:$src)),
1401 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1402 def : Pat<(i8 (trunc GR32:$src)),
1403 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1405 Requires<[Not64BitMode]>;
1406 def : Pat<(i8 (trunc GR16:$src)),
1407 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1409 Requires<[Not64BitMode]>;
1410 def : Pat<(i32 (trunc GR64:$src)),
1411 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1412 def : Pat<(i16 (trunc GR64:$src)),
1413 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1414 def : Pat<(i8 (trunc GR64:$src)),
1415 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1416 def : Pat<(i8 (trunc GR32:$src)),
1417 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1418 Requires<[In64BitMode]>;
1419 def : Pat<(i8 (trunc GR16:$src)),
1420 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1421 Requires<[In64BitMode]>;
1423 // h-register tricks
1424 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1425 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1427 Requires<[Not64BitMode]>;
1428 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1429 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1431 Requires<[Not64BitMode]>;
1432 def : Pat<(srl GR16:$src, (i8 8)),
1435 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1438 Requires<[Not64BitMode]>;
1439 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1440 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1443 Requires<[Not64BitMode]>;
1444 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1445 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1448 Requires<[Not64BitMode]>;
1449 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1450 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1453 Requires<[Not64BitMode]>;
1454 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1455 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1458 Requires<[Not64BitMode]>;
1460 // h-register tricks.
1461 // For now, be conservative on x86-64 and use an h-register extract only if the
1462 // value is immediately zero-extended or stored, which are somewhat common
1463 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1464 // from being allocated in the same instruction as the h register, as there's
1465 // currently no way to describe this requirement to the register allocator.
1467 // h-register extract and zero-extend.
1468 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1472 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1475 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1477 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1479 Requires<[In64BitMode]>;
1480 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1481 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1484 Requires<[In64BitMode]>;
1485 def : Pat<(srl GR16:$src, (i8 8)),
1488 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1491 Requires<[In64BitMode]>;
1492 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1494 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1496 Requires<[In64BitMode]>;
1497 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1499 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1501 Requires<[In64BitMode]>;
1502 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1506 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1509 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1513 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1517 // h-register extract and store.
1518 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1521 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1523 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1526 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1528 Requires<[In64BitMode]>;
1529 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1532 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1534 Requires<[In64BitMode]>;
1537 // (shl x, 1) ==> (add x, x)
1538 // Note that if x is undef (immediate or otherwise), we could theoretically
1539 // end up with the two uses of x getting different values, producing a result
1540 // where the least significant bit is not 0. However, the probability of this
1541 // happening is considered low enough that this is officially not a
1543 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1544 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1545 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1546 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1548 // Helper imms that check if a mask doesn't change significant shift bits.
1549 def immShift32 : ImmLeaf<i8, [{
1550 return countTrailingOnes<uint64_t>(Imm) >= 5;
1552 def immShift64 : ImmLeaf<i8, [{
1553 return countTrailingOnes<uint64_t>(Imm) >= 6;
1556 // Shift amount is implicitly masked.
1557 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1558 // (shift x (and y, 31)) ==> (shift x, y)
1559 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1560 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1561 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1562 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1563 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1564 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1565 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1566 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1567 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1568 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1569 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1570 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1572 // (shift x (and y, 63)) ==> (shift x, y)
1573 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1574 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1575 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1576 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1579 defm : MaskedShiftAmountPats<shl, "SHL">;
1580 defm : MaskedShiftAmountPats<srl, "SHR">;
1581 defm : MaskedShiftAmountPats<sra, "SAR">;
1582 defm : MaskedShiftAmountPats<rotl, "ROL">;
1583 defm : MaskedShiftAmountPats<rotr, "ROR">;
1585 // (anyext (setcc_carry)) -> (setcc_carry)
1586 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1588 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1590 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1596 //===----------------------------------------------------------------------===//
1597 // EFLAGS-defining Patterns
1598 //===----------------------------------------------------------------------===//
1601 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1602 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1603 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1606 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1607 (ADD8rm GR8:$src1, addr:$src2)>;
1608 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1609 (ADD16rm GR16:$src1, addr:$src2)>;
1610 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1611 (ADD32rm GR32:$src1, addr:$src2)>;
1614 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1615 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1616 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1617 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1618 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1619 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1620 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1623 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1624 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1625 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1628 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1629 (SUB8rm GR8:$src1, addr:$src2)>;
1630 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1631 (SUB16rm GR16:$src1, addr:$src2)>;
1632 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1633 (SUB32rm GR32:$src1, addr:$src2)>;
1636 def : Pat<(sub GR8:$src1, imm:$src2),
1637 (SUB8ri GR8:$src1, imm:$src2)>;
1638 def : Pat<(sub GR16:$src1, imm:$src2),
1639 (SUB16ri GR16:$src1, imm:$src2)>;
1640 def : Pat<(sub GR32:$src1, imm:$src2),
1641 (SUB32ri GR32:$src1, imm:$src2)>;
1642 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1643 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1644 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1645 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1648 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1649 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1650 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1651 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1654 def : Pat<(mul GR16:$src1, GR16:$src2),
1655 (IMUL16rr GR16:$src1, GR16:$src2)>;
1656 def : Pat<(mul GR32:$src1, GR32:$src2),
1657 (IMUL32rr GR32:$src1, GR32:$src2)>;
1660 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1661 (IMUL16rm GR16:$src1, addr:$src2)>;
1662 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1663 (IMUL32rm GR32:$src1, addr:$src2)>;
1666 def : Pat<(mul GR16:$src1, imm:$src2),
1667 (IMUL16rri GR16:$src1, imm:$src2)>;
1668 def : Pat<(mul GR32:$src1, imm:$src2),
1669 (IMUL32rri GR32:$src1, imm:$src2)>;
1670 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1671 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1672 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1673 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1675 // reg = mul mem, imm
1676 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1677 (IMUL16rmi addr:$src1, imm:$src2)>;
1678 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1679 (IMUL32rmi addr:$src1, imm:$src2)>;
1680 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1681 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1682 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1683 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1685 // Patterns for nodes that do not produce flags, for instructions that do.
1688 def : Pat<(add GR64:$src1, GR64:$src2),
1689 (ADD64rr GR64:$src1, GR64:$src2)>;
1690 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1691 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1692 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1693 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1694 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1695 (ADD64rm GR64:$src1, addr:$src2)>;
1698 def : Pat<(sub GR64:$src1, GR64:$src2),
1699 (SUB64rr GR64:$src1, GR64:$src2)>;
1700 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1701 (SUB64rm GR64:$src1, addr:$src2)>;
1702 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1703 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1704 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1705 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1708 def : Pat<(mul GR64:$src1, GR64:$src2),
1709 (IMUL64rr GR64:$src1, GR64:$src2)>;
1710 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1711 (IMUL64rm GR64:$src1, addr:$src2)>;
1712 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1713 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1714 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1715 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1716 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1717 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1718 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1719 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1721 // Increment/Decrement reg.
1722 // Do not make INC/DEC if it is slow
1723 let Predicates = [NotSlowIncDec] in {
1724 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
1725 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
1726 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
1727 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1728 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
1729 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
1730 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
1731 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1735 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1736 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1737 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1738 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1741 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1742 (OR8rm GR8:$src1, addr:$src2)>;
1743 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1744 (OR16rm GR16:$src1, addr:$src2)>;
1745 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1746 (OR32rm GR32:$src1, addr:$src2)>;
1747 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1748 (OR64rm GR64:$src1, addr:$src2)>;
1751 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1752 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1753 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1754 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1755 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1756 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1757 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1758 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1759 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1760 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1761 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1764 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1765 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1766 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1767 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1770 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1771 (XOR8rm GR8:$src1, addr:$src2)>;
1772 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1773 (XOR16rm GR16:$src1, addr:$src2)>;
1774 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1775 (XOR32rm GR32:$src1, addr:$src2)>;
1776 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1777 (XOR64rm GR64:$src1, addr:$src2)>;
1780 def : Pat<(xor GR8:$src1, imm:$src2),
1781 (XOR8ri GR8:$src1, imm:$src2)>;
1782 def : Pat<(xor GR16:$src1, imm:$src2),
1783 (XOR16ri GR16:$src1, imm:$src2)>;
1784 def : Pat<(xor GR32:$src1, imm:$src2),
1785 (XOR32ri GR32:$src1, imm:$src2)>;
1786 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1787 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1788 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1789 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1790 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1791 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1792 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1793 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1796 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1797 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1798 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1799 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1802 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1803 (AND8rm GR8:$src1, addr:$src2)>;
1804 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1805 (AND16rm GR16:$src1, addr:$src2)>;
1806 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1807 (AND32rm GR32:$src1, addr:$src2)>;
1808 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1809 (AND64rm GR64:$src1, addr:$src2)>;
1812 def : Pat<(and GR8:$src1, imm:$src2),
1813 (AND8ri GR8:$src1, imm:$src2)>;
1814 def : Pat<(and GR16:$src1, imm:$src2),
1815 (AND16ri GR16:$src1, imm:$src2)>;
1816 def : Pat<(and GR32:$src1, imm:$src2),
1817 (AND32ri GR32:$src1, imm:$src2)>;
1818 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1819 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1820 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1821 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1822 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1823 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1824 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1825 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1827 // Bit scan instruction patterns to match explicit zero-undef behavior.
1828 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1829 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1830 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1831 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1832 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1833 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1835 // When HasMOVBE is enabled it is possible to get a non-legalized
1836 // register-register 16 bit bswap. This maps it to a ROL instruction.
1837 let Predicates = [HasMOVBE] in {
1838 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;