1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
55 def : Pat<(X86callseq_start timm:$amt1),
56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
59 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
60 // a stack adjustment and the codegen must know that they may modify the stack
61 // pointer before prolog-epilog rewriting occurs.
62 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
63 // sub / add which can clobber EFLAGS.
64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
71 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
74 def : Pat<(X86callseq_start timm:$amt1),
75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
78 // x86-64 va_start lowering magic.
79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
83 i64imm:$regsavefi, i64imm:$offset,
85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
86 [(X86vastart_save_xmm_regs GR8:$al,
91 // The VAARG_64 pseudo-instruction takes the address of the va_list,
92 // and places the address of the next argument into a register.
93 let Defs = [EFLAGS] in
94 def VAARG_64 : I<0, Pseudo,
96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
97 "#VAARG_64 $dst, $ap, $size, $mode, $align",
99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
102 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
103 // targets. These calls are needed to probe the stack when allocating more than
104 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
105 // ensure that the guard pages used by the OS virtual memory manager are
106 // allocated in correct sequence.
107 // The main point of having separate instruction are extra unmodelled effects
108 // (compared to ordinary calls) like stack pointer change.
110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
112 "# dynamic stack allocation",
115 // When using segmented stacks these are lowered into instructions which first
116 // check if the current stacklet has enough free memory. If it does, memory is
117 // allocated by bumping the stack pointer. Otherwise memory is allocated from
120 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
121 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
122 "# variable sized alloca for segmented stacks",
124 (X86SegAlloca GR32:$size))]>,
127 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
128 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
129 "# variable sized alloca for segmented stacks",
131 (X86SegAlloca GR64:$size))]>,
132 Requires<[In64BitMode]>;
135 //===----------------------------------------------------------------------===//
136 // EH Pseudo Instructions
138 let SchedRW = [WriteSystem] in {
139 let isTerminator = 1, isReturn = 1, isBarrier = 1,
140 hasCtrlDep = 1, isCodeGenOnly = 1 in {
141 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
142 "ret\t#eh_return, addr: $addr",
143 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
147 let isTerminator = 1, isReturn = 1, isBarrier = 1,
148 hasCtrlDep = 1, isCodeGenOnly = 1 in {
149 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
150 "ret\t#eh_return, addr: $addr",
151 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
155 let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
156 isCodeGenOnly = 1, isReturn = 1 in {
157 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>;
159 // CATCHRET needs a custom inserter for SEH.
160 let usesCustomInserter = 1 in
161 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from),
163 [(catchret bb:$dst, bb:$from)]>;
166 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1,
167 usesCustomInserter = 1 in
168 def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>;
170 // This instruction is responsible for re-establishing stack pointers after an
171 // exception has been caught and we are rejoining normal control flow in the
172 // parent function or funclet. It generally sets ESP and EBP, and optionally
173 // ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us
175 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in
176 def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>;
178 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
179 usesCustomInserter = 1 in {
180 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
182 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
183 Requires<[Not64BitMode]>;
184 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
186 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
187 Requires<[In64BitMode]>;
188 let isTerminator = 1 in {
189 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
190 "#EH_SJLJ_LONGJMP32",
191 [(X86eh_sjlj_longjmp addr:$buf)]>,
192 Requires<[Not64BitMode]>;
193 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
194 "#EH_SJLJ_LONGJMP64",
195 [(X86eh_sjlj_longjmp addr:$buf)]>,
196 Requires<[In64BitMode]>;
201 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
202 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
203 "#EH_SjLj_Setup\t$dst", []>;
206 //===----------------------------------------------------------------------===//
207 // Pseudo instructions used by unwind info.
209 let isPseudo = 1 in {
210 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
211 "#SEH_PushReg $reg", []>;
212 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
213 "#SEH_SaveReg $reg, $dst", []>;
214 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
215 "#SEH_SaveXMM $reg, $dst", []>;
216 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
217 "#SEH_StackAlloc $size", []>;
218 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
219 "#SEH_SetFrame $reg, $offset", []>;
220 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
221 "#SEH_PushFrame $mode", []>;
222 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
223 "#SEH_EndPrologue", []>;
224 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
225 "#SEH_Epilogue", []>;
228 //===----------------------------------------------------------------------===//
229 // Pseudo instructions used by segmented stacks.
232 // This is lowered into a RET instruction by MCInstLower. We need
233 // this so that we don't have to have a MachineBasicBlock which ends
234 // with a RET and also has successors.
235 let isPseudo = 1 in {
236 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
239 // This instruction is lowered to a RET followed by a MOV. The two
240 // instructions are not generated on a higher level since then the
241 // verifier sees a MachineBasicBlock ending with a non-terminator.
242 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
246 //===----------------------------------------------------------------------===//
247 // Alias Instructions
248 //===----------------------------------------------------------------------===//
250 // Alias instruction mapping movr0 to xor.
251 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
252 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
254 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
255 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
257 // Other widths can also make use of the 32-bit xor, which may have a smaller
258 // encoding and avoid partial register updates.
259 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
260 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
261 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
262 let AddedComplexity = 20;
265 // Materialize i64 constant where top 32-bits are zero. This could theoretically
266 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
267 // that would make it more difficult to rematerialize.
268 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
269 isCodeGenOnly = 1, hasSideEffects = 0 in
270 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
271 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
273 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
274 // actually the zero-extension of a 32-bit constant and for labels in the
275 // x86-64 small code model.
276 def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>;
278 let AddedComplexity = 1 in
279 def : Pat<(i64 mov64imm32:$src),
280 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
282 // Use sbb to materialize carry bit.
283 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
284 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
285 // However, Pat<> can't replicate the destination reg into the inputs of the
287 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
288 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
289 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
290 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
291 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
292 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
293 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
294 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
298 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
300 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
302 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
305 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
307 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
309 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
312 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
313 // will be eliminated and that the sbb can be extended up to a wider type. When
314 // this happens, it is great. However, if we are left with an 8-bit sbb and an
315 // and, we might as well just match it as a setb.
316 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
319 // (add OP, SETB) -> (adc OP, 0)
320 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
321 (ADC8ri GR8:$op, 0)>;
322 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
323 (ADC32ri8 GR32:$op, 0)>;
324 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
325 (ADC64ri8 GR64:$op, 0)>;
327 // (sub OP, SETB) -> (sbb OP, 0)
328 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
329 (SBB8ri GR8:$op, 0)>;
330 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
331 (SBB32ri8 GR32:$op, 0)>;
332 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
333 (SBB64ri8 GR64:$op, 0)>;
335 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
336 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
337 (ADC8ri GR8:$op, 0)>;
338 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
339 (ADC32ri8 GR32:$op, 0)>;
340 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
341 (ADC64ri8 GR64:$op, 0)>;
343 //===----------------------------------------------------------------------===//
344 // String Pseudo Instructions
346 let SchedRW = [WriteMicrocoded] in {
347 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
348 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
349 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
350 Requires<[Not64BitMode]>;
351 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
352 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
353 Requires<[Not64BitMode]>;
354 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
355 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
356 Requires<[Not64BitMode]>;
359 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
360 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
361 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
362 Requires<[In64BitMode]>;
363 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
364 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
365 Requires<[In64BitMode]>;
366 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
367 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
368 Requires<[In64BitMode]>;
369 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
370 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
371 Requires<[In64BitMode]>;
374 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
375 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
376 let Uses = [AL,ECX,EDI] in
377 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
378 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
379 Requires<[Not64BitMode]>;
380 let Uses = [AX,ECX,EDI] in
381 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
382 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
383 Requires<[Not64BitMode]>;
384 let Uses = [EAX,ECX,EDI] in
385 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
386 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
387 Requires<[Not64BitMode]>;
390 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
391 let Uses = [AL,RCX,RDI] in
392 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
393 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
394 Requires<[In64BitMode]>;
395 let Uses = [AX,RCX,RDI] in
396 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
397 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
398 Requires<[In64BitMode]>;
399 let Uses = [RAX,RCX,RDI] in
400 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
401 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
402 Requires<[In64BitMode]>;
404 let Uses = [RAX,RCX,RDI] in
405 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
406 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
407 Requires<[In64BitMode]>;
411 //===----------------------------------------------------------------------===//
412 // Thread Local Storage Instructions
416 // All calls clobber the non-callee saved registers. ESP is marked as
417 // a use to prevent stack-pointer assignments that appear immediately
418 // before calls from potentially appearing dead.
419 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
420 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
421 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
422 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
423 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
425 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
427 [(X86tlsaddr tls32addr:$sym)]>,
428 Requires<[Not64BitMode]>;
429 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
431 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
432 Requires<[Not64BitMode]>;
435 // All calls clobber the non-callee saved registers. RSP is marked as
436 // a use to prevent stack-pointer assignments that appear immediately
437 // before calls from potentially appearing dead.
438 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
439 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
440 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
441 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
442 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
443 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
445 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
447 [(X86tlsaddr tls64addr:$sym)]>,
448 Requires<[In64BitMode]>;
449 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
451 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
452 Requires<[In64BitMode]>;
455 // Darwin TLS Support
456 // For i386, the address of the thunk is passed on the stack, on return the
457 // address of the variable is in %eax. %ecx is trashed during the function
458 // call. All other registers are preserved.
459 let Defs = [EAX, ECX, EFLAGS],
461 usesCustomInserter = 1 in
462 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
464 [(X86TLSCall addr:$sym)]>,
465 Requires<[Not64BitMode]>;
467 // For x86_64, the address of the thunk is passed in %rdi, on return
468 // the address of the variable is in %rax. All other registers are preserved.
469 let Defs = [RAX, EFLAGS],
471 usesCustomInserter = 1 in
472 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
474 [(X86TLSCall addr:$sym)]>,
475 Requires<[In64BitMode]>;
478 //===----------------------------------------------------------------------===//
479 // Conditional Move Pseudo Instructions
481 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
482 // instruction selection into a branch sequence.
483 multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
484 def CMOV#NAME : I<0, Pseudo,
485 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
486 "#CMOV_"#NAME#" PSEUDO!",
487 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond,
491 let usesCustomInserter = 1, Uses = [EFLAGS] in {
492 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
493 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
494 // however that requires promoting the operands, and can induce additional
495 // i8 register pressure.
496 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
498 let Predicates = [NoCMov] in {
499 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
500 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
501 } // Predicates = [NoCMov]
503 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
505 let Predicates = [FPStackf32] in
506 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
508 let Predicates = [FPStackf64] in
509 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
511 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
513 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;
514 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;
515 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>;
516 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>;
517 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>;
518 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>;
519 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
520 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>;
521 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
522 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
523 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
524 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
525 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
526 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
527 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
528 } // usesCustomInserter = 1, Uses = [EFLAGS]
530 //===----------------------------------------------------------------------===//
531 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
532 //===----------------------------------------------------------------------===//
534 // FIXME: Use normal instructions and add lock prefix dynamically.
538 // TODO: Get this to fold the constant into the instruction.
539 let isCodeGenOnly = 1, Defs = [EFLAGS] in
540 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
541 "or{l}\t{$zero, $dst|$dst, $zero}",
542 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
543 Sched<[WriteALULd, WriteRMW]>;
545 let hasSideEffects = 1 in
546 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
548 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
550 // RegOpc corresponds to the mr version of the instruction
551 // ImmOpc corresponds to the mi version of the instruction
552 // ImmOpc8 corresponds to the mi8 version of the instruction
553 // ImmMod corresponds to the instruction format of the mi and mi8 versions
554 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
555 Format ImmMod, string mnemonic> {
556 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
557 SchedRW = [WriteALULd, WriteRMW] in {
559 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
560 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
561 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
562 !strconcat(mnemonic, "{b}\t",
563 "{$src2, $dst|$dst, $src2}"),
564 [], IIC_ALU_NONMEM>, LOCK;
565 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
566 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
567 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
568 !strconcat(mnemonic, "{w}\t",
569 "{$src2, $dst|$dst, $src2}"),
570 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
571 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
572 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
573 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
574 !strconcat(mnemonic, "{l}\t",
575 "{$src2, $dst|$dst, $src2}"),
576 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
577 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
578 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
579 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
580 !strconcat(mnemonic, "{q}\t",
581 "{$src2, $dst|$dst, $src2}"),
582 [], IIC_ALU_NONMEM>, LOCK;
584 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
585 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
586 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
587 !strconcat(mnemonic, "{b}\t",
588 "{$src2, $dst|$dst, $src2}"),
589 [], IIC_ALU_MEM>, LOCK;
591 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
592 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
593 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
594 !strconcat(mnemonic, "{w}\t",
595 "{$src2, $dst|$dst, $src2}"),
596 [], IIC_ALU_MEM>, OpSize16, LOCK;
598 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
599 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
600 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
601 !strconcat(mnemonic, "{l}\t",
602 "{$src2, $dst|$dst, $src2}"),
603 [], IIC_ALU_MEM>, OpSize32, LOCK;
605 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
606 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
607 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
608 !strconcat(mnemonic, "{q}\t",
609 "{$src2, $dst|$dst, $src2}"),
610 [], IIC_ALU_MEM>, LOCK;
612 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
613 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
614 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
615 !strconcat(mnemonic, "{w}\t",
616 "{$src2, $dst|$dst, $src2}"),
617 [], IIC_ALU_MEM>, OpSize16, LOCK;
618 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
619 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
620 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
621 !strconcat(mnemonic, "{l}\t",
622 "{$src2, $dst|$dst, $src2}"),
623 [], IIC_ALU_MEM>, OpSize32, LOCK;
624 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
625 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
626 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
627 !strconcat(mnemonic, "{q}\t",
628 "{$src2, $dst|$dst, $src2}"),
629 [], IIC_ALU_MEM>, LOCK;
635 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
636 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
637 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
638 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
639 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
641 // Optimized codegen when the non-memory output is not used.
642 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
644 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
645 SchedRW = [WriteALULd, WriteRMW] in {
647 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
648 !strconcat(mnemonic, "{b}\t$dst"),
649 [], IIC_UNARY_MEM>, LOCK;
650 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
651 !strconcat(mnemonic, "{w}\t$dst"),
652 [], IIC_UNARY_MEM>, OpSize16, LOCK;
653 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
654 !strconcat(mnemonic, "{l}\t$dst"),
655 [], IIC_UNARY_MEM>, OpSize32, LOCK;
656 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
657 !strconcat(mnemonic, "{q}\t$dst"),
658 [], IIC_UNARY_MEM>, LOCK;
662 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
663 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
665 // Atomic compare and swap.
666 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
667 SDPatternOperator frag, X86MemOperand x86memop,
668 InstrItinClass itin> {
669 let isCodeGenOnly = 1 in {
670 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
671 !strconcat(mnemonic, "\t$ptr"),
672 [(frag addr:$ptr)], itin>, TB, LOCK;
676 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
677 string mnemonic, SDPatternOperator frag,
678 InstrItinClass itin8, InstrItinClass itin> {
679 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
680 let Defs = [AL, EFLAGS], Uses = [AL] in
681 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
682 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
683 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
684 let Defs = [AX, EFLAGS], Uses = [AX] in
685 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
686 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
687 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
688 let Defs = [EAX, EFLAGS], Uses = [EAX] in
689 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
690 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
691 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
692 let Defs = [RAX, EFLAGS], Uses = [RAX] in
693 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
694 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
695 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
699 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
700 SchedRW = [WriteALULd, WriteRMW] in {
701 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
706 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
707 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
708 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
710 IIC_CMPX_LOCK_16B>, REX_W;
713 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
714 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
716 // Atomic exchange and add
717 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
719 InstrItinClass itin8, InstrItinClass itin> {
720 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
721 SchedRW = [WriteALULd, WriteRMW] in {
722 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
723 (ins GR8:$val, i8mem:$ptr),
724 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
726 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
728 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
729 (ins GR16:$val, i16mem:$ptr),
730 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
733 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
735 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
736 (ins GR32:$val, i32mem:$ptr),
737 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
740 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
742 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
743 (ins GR64:$val, i64mem:$ptr),
744 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
747 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
752 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
753 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
756 /* The following multiclass tries to make sure that in code like
757 * x.store (immediate op x.load(acquire), release)
759 * x.store (register op x.load(acquire), release)
760 * an operation directly on memory is generated instead of wasting a register.
761 * It is not automatic as atomic_store/load are only lowered to MOV instructions
762 * extremely late to prevent them from being accidentally reordered in the backend
763 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
765 multiclass RELEASE_BINOP_MI<SDNode op> {
766 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
767 "#BINOP "#NAME#"8mi PSEUDO!",
768 [(atomic_store_8 addr:$dst, (op
769 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
770 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src),
771 "#BINOP "#NAME#"8mr PSEUDO!",
772 [(atomic_store_8 addr:$dst, (op
773 (atomic_load_8 addr:$dst), GR8:$src))]>;
774 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
775 // costly and avoided as far as possible by this backend anyway
776 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
777 "#BINOP "#NAME#"32mi PSEUDO!",
778 [(atomic_store_32 addr:$dst, (op
779 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
780 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
781 "#BINOP "#NAME#"32mr PSEUDO!",
782 [(atomic_store_32 addr:$dst, (op
783 (atomic_load_32 addr:$dst), GR32:$src))]>;
784 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
785 "#BINOP "#NAME#"64mi32 PSEUDO!",
786 [(atomic_store_64 addr:$dst, (op
787 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
788 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
789 "#BINOP "#NAME#"64mr PSEUDO!",
790 [(atomic_store_64 addr:$dst, (op
791 (atomic_load_64 addr:$dst), GR64:$src))]>;
793 let Defs = [EFLAGS] in {
794 defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
795 defm RELEASE_AND : RELEASE_BINOP_MI<and>;
796 defm RELEASE_OR : RELEASE_BINOP_MI<or>;
797 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>;
798 // Note: we don't deal with sub, because substractions of constants are
799 // optimized into additions before this code can run.
802 // Same as above, but for floating-point.
803 // FIXME: imm version.
804 // FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
805 // FIXME: This could also handle SIMD operations with *ps and *pd instructions.
806 let usesCustomInserter = 1 in {
807 multiclass RELEASE_FP_BINOP_MI<SDNode op> {
808 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
809 "#BINOP "#NAME#"32mr PSEUDO!",
810 [(atomic_store_32 addr:$dst,
812 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))),
813 FR32:$src))))]>, Requires<[HasSSE1]>;
814 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src),
815 "#BINOP "#NAME#"64mr PSEUDO!",
816 [(atomic_store_64 addr:$dst,
818 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))),
819 FR64:$src))))]>, Requires<[HasSSE2]>;
821 defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>;
822 // FIXME: Add fsub, fmul, fdiv, ...
825 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
826 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
827 "#UNOP "#NAME#"8m PSEUDO!",
828 [(atomic_store_8 addr:$dst, dag8)]>;
829 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
830 "#UNOP "#NAME#"16m PSEUDO!",
831 [(atomic_store_16 addr:$dst, dag16)]>;
832 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
833 "#UNOP "#NAME#"32m PSEUDO!",
834 [(atomic_store_32 addr:$dst, dag32)]>;
835 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
836 "#UNOP "#NAME#"64m PSEUDO!",
837 [(atomic_store_64 addr:$dst, dag64)]>;
840 let Defs = [EFLAGS] in {
841 defm RELEASE_INC : RELEASE_UNOP<
842 (add (atomic_load_8 addr:$dst), (i8 1)),
843 (add (atomic_load_16 addr:$dst), (i16 1)),
844 (add (atomic_load_32 addr:$dst), (i32 1)),
845 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>;
846 defm RELEASE_DEC : RELEASE_UNOP<
847 (add (atomic_load_8 addr:$dst), (i8 -1)),
848 (add (atomic_load_16 addr:$dst), (i16 -1)),
849 (add (atomic_load_32 addr:$dst), (i32 -1)),
850 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>;
853 TODO: These don't work because the type inference of TableGen fails.
854 TODO: find a way to fix it.
855 let Defs = [EFLAGS] in {
856 defm RELEASE_NEG : RELEASE_UNOP<
857 (ineg (atomic_load_8 addr:$dst)),
858 (ineg (atomic_load_16 addr:$dst)),
859 (ineg (atomic_load_32 addr:$dst)),
860 (ineg (atomic_load_64 addr:$dst))>;
862 // NOT doesn't set flags.
863 defm RELEASE_NOT : RELEASE_UNOP<
864 (not (atomic_load_8 addr:$dst)),
865 (not (atomic_load_16 addr:$dst)),
866 (not (atomic_load_32 addr:$dst)),
867 (not (atomic_load_64 addr:$dst))>;
870 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
871 "#RELEASE_MOV8mi PSEUDO!",
872 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
873 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
874 "#RELEASE_MOV16mi PSEUDO!",
875 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
876 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
877 "#RELEASE_MOV32mi PSEUDO!",
878 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
879 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
880 "#RELEASE_MOV64mi32 PSEUDO!",
881 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
883 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
884 "#RELEASE_MOV8mr PSEUDO!",
885 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
886 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
887 "#RELEASE_MOV16mr PSEUDO!",
888 [(atomic_store_16 addr:$dst, GR16:$src)]>;
889 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
890 "#RELEASE_MOV32mr PSEUDO!",
891 [(atomic_store_32 addr:$dst, GR32:$src)]>;
892 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
893 "#RELEASE_MOV64mr PSEUDO!",
894 [(atomic_store_64 addr:$dst, GR64:$src)]>;
896 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
897 "#ACQUIRE_MOV8rm PSEUDO!",
898 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
899 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
900 "#ACQUIRE_MOV16rm PSEUDO!",
901 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
902 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
903 "#ACQUIRE_MOV32rm PSEUDO!",
904 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
905 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
906 "#ACQUIRE_MOV64rm PSEUDO!",
907 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
909 //===----------------------------------------------------------------------===//
910 // DAG Pattern Matching Rules
911 //===----------------------------------------------------------------------===//
913 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
914 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
915 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
916 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
917 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
918 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
919 def : Pat<(i32 (X86Wrapper mcsym:$dst)), (MOV32ri mcsym:$dst)>;
920 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
922 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
923 (ADD32ri GR32:$src1, tconstpool:$src2)>;
924 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
925 (ADD32ri GR32:$src1, tjumptable:$src2)>;
926 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
927 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
928 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
929 (ADD32ri GR32:$src1, texternalsym:$src2)>;
930 def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)),
931 (ADD32ri GR32:$src1, mcsym:$src2)>;
932 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
933 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
935 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
936 (MOV32mi addr:$dst, tglobaladdr:$src)>;
937 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
938 (MOV32mi addr:$dst, texternalsym:$src)>;
939 def : Pat<(store (i32 (X86Wrapper mcsym:$src)), addr:$dst),
940 (MOV32mi addr:$dst, mcsym:$src)>;
941 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
942 (MOV32mi addr:$dst, tblockaddress:$src)>;
944 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
945 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
946 // 'movabs' predicate should handle this sort of thing.
947 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
948 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
949 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
950 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
951 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
952 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
953 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
954 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
955 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
956 (MOV64ri mcsym:$dst)>, Requires<[FarData]>;
957 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
958 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
960 // In kernel code model, we can get the address of a label
961 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
962 // the MOV64ri32 should accept these.
963 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
964 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
965 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
966 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
967 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
968 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
969 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
970 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
971 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
972 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;
973 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
974 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
976 // If we have small model and -static mode, it is safe to store global addresses
977 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
978 // for MOV64mi32 should handle this sort of thing.
979 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
980 (MOV64mi32 addr:$dst, tconstpool:$src)>,
981 Requires<[NearData, IsStatic]>;
982 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
983 (MOV64mi32 addr:$dst, tjumptable:$src)>,
984 Requires<[NearData, IsStatic]>;
985 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
986 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
987 Requires<[NearData, IsStatic]>;
988 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
989 (MOV64mi32 addr:$dst, texternalsym:$src)>,
990 Requires<[NearData, IsStatic]>;
991 def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),
992 (MOV64mi32 addr:$dst, mcsym:$src)>,
993 Requires<[NearData, IsStatic]>;
994 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
995 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
996 Requires<[NearData, IsStatic]>;
998 def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;
999 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
1003 // tls has some funny stuff here...
1004 // This corresponds to movabs $foo@tpoff, %rax
1005 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
1006 (MOV64ri32 tglobaltlsaddr :$dst)>;
1007 // This corresponds to add $foo@tpoff, %rax
1008 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1009 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1012 // Direct PC relative function call for small code model. 32-bit displacement
1013 // sign extended to 64-bit.
1014 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1015 (CALL64pcrel32 tglobaladdr:$dst)>;
1016 def : Pat<(X86call (i64 texternalsym:$dst)),
1017 (CALL64pcrel32 texternalsym:$dst)>;
1019 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1020 // can never use callee-saved registers. That is the purpose of the GR64_TC
1021 // register classes.
1023 // The only volatile register that is never used by the calling convention is
1024 // %r11. This happens when calling a vararg function with 6 arguments.
1026 // Match an X86tcret that uses less than 7 volatile registers.
1027 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1028 (X86tcret node:$ptr, node:$off), [{
1029 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1030 unsigned NumRegs = 0;
1031 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1032 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1037 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1038 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1039 Requires<[Not64BitMode]>;
1041 // FIXME: This is disabled for 32-bit PIC mode because the global base
1042 // register which is part of the address mode may be assigned a
1043 // callee-saved register.
1044 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1045 (TCRETURNmi addr:$dst, imm:$off)>,
1046 Requires<[Not64BitMode, IsNotPIC]>;
1048 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1049 (TCRETURNdi tglobaladdr:$dst, imm:$off)>,
1050 Requires<[NotLP64]>;
1052 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1053 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1054 Requires<[NotLP64]>;
1056 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1057 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1058 Requires<[In64BitMode]>;
1060 // Don't fold loads into X86tcret requiring more than 6 regs.
1061 // There wouldn't be enough scratch registers for base+index.
1062 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1063 (TCRETURNmi64 addr:$dst, imm:$off)>,
1064 Requires<[In64BitMode]>;
1066 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1067 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1070 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1071 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1074 // Normal calls, with various flavors of addresses.
1075 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1076 (CALLpcrel32 tglobaladdr:$dst)>;
1077 def : Pat<(X86call (i32 texternalsym:$dst)),
1078 (CALLpcrel32 texternalsym:$dst)>;
1079 def : Pat<(X86call (i32 imm:$dst)),
1080 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1084 // TEST R,R is smaller than CMP R,0
1085 def : Pat<(X86cmp GR8:$src1, 0),
1086 (TEST8rr GR8:$src1, GR8:$src1)>;
1087 def : Pat<(X86cmp GR16:$src1, 0),
1088 (TEST16rr GR16:$src1, GR16:$src1)>;
1089 def : Pat<(X86cmp GR32:$src1, 0),
1090 (TEST32rr GR32:$src1, GR32:$src1)>;
1091 def : Pat<(X86cmp GR64:$src1, 0),
1092 (TEST64rr GR64:$src1, GR64:$src1)>;
1094 // Conditional moves with folded loads with operands swapped and conditions
1096 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1097 Instruction Inst64> {
1098 let Predicates = [HasCMov] in {
1099 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1100 (Inst16 GR16:$src2, addr:$src1)>;
1101 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1102 (Inst32 GR32:$src2, addr:$src1)>;
1103 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1104 (Inst64 GR64:$src2, addr:$src1)>;
1108 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1109 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1110 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1111 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1112 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1113 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1114 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1115 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1116 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1117 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1118 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1119 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1120 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1121 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1122 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1123 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1125 // zextload bool -> zextload byte
1126 def : Pat<(zextloadi8i1 addr:$src), (AND8ri (MOV8rm addr:$src), (i8 1))>;
1127 def : Pat<(zextloadi16i1 addr:$src), (AND16ri8 (MOVZX16rm8 addr:$src), (i16 1))>;
1128 def : Pat<(zextloadi32i1 addr:$src), (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1))>;
1129 def : Pat<(zextloadi64i1 addr:$src),
1130 (SUBREG_TO_REG (i64 0),
1131 (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), sub_32bit)>;
1133 // extload bool -> extload byte
1134 // When extloading from 16-bit and smaller memory locations into 64-bit
1135 // registers, use zero-extending loads so that the entire 64-bit register is
1136 // defined, avoiding partial-register updates.
1138 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1139 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1140 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1141 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1142 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1143 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1145 // For other extloads, use subregs, since the high contents of the register are
1146 // defined after an extload.
1147 def : Pat<(extloadi64i1 addr:$src),
1148 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1149 def : Pat<(extloadi64i8 addr:$src),
1150 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1151 def : Pat<(extloadi64i16 addr:$src),
1152 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1153 def : Pat<(extloadi64i32 addr:$src),
1154 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1156 // anyext. Define these to do an explicit zero-extend to
1157 // avoid partial-register updates.
1158 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1159 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1160 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1162 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1163 def : Pat<(i32 (anyext GR16:$src)),
1164 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1166 def : Pat<(i64 (anyext GR8 :$src)),
1167 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1168 def : Pat<(i64 (anyext GR16:$src)),
1169 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1170 def : Pat<(i64 (anyext GR32:$src)),
1171 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1174 // Any instruction that defines a 32-bit result leaves the high half of the
1175 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1176 // be copying from a truncate. And x86's cmov doesn't do anything if the
1177 // condition is false. But any other 32-bit operation will zero-extend
1179 def def32 : PatLeaf<(i32 GR32:$src), [{
1180 return N->getOpcode() != ISD::TRUNCATE &&
1181 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1182 N->getOpcode() != ISD::CopyFromReg &&
1183 N->getOpcode() != ISD::AssertSext &&
1184 N->getOpcode() != X86ISD::CMOV;
1187 // In the case of a 32-bit def that is known to implicitly zero-extend,
1188 // we can use a SUBREG_TO_REG.
1189 def : Pat<(i64 (zext def32:$src)),
1190 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1192 //===----------------------------------------------------------------------===//
1193 // Pattern match OR as ADD
1194 //===----------------------------------------------------------------------===//
1196 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1197 // 3-addressified into an LEA instruction to avoid copies. However, we also
1198 // want to finally emit these instructions as an or at the end of the code
1199 // generator to make the generated code easier to read. To do this, we select
1200 // into "disjoint bits" pseudo ops.
1202 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1203 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1204 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1205 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1207 APInt KnownZero0, KnownOne0;
1208 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1209 APInt KnownZero1, KnownOne1;
1210 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1211 return (~KnownZero0 & ~KnownZero1) == 0;
1215 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1216 // Try this before the selecting to OR.
1217 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1219 let isConvertibleToThreeAddress = 1,
1220 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1221 let isCommutable = 1 in {
1222 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1223 "", // orw/addw REG, REG
1224 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1225 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1226 "", // orl/addl REG, REG
1227 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1228 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1229 "", // orq/addq REG, REG
1230 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1233 // NOTE: These are order specific, we want the ri8 forms to be listed
1234 // first so that they are slightly preferred to the ri forms.
1236 def ADD16ri8_DB : I<0, Pseudo,
1237 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1238 "", // orw/addw REG, imm8
1239 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1240 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1241 "", // orw/addw REG, imm
1242 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1244 def ADD32ri8_DB : I<0, Pseudo,
1245 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1246 "", // orl/addl REG, imm8
1247 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1248 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1249 "", // orl/addl REG, imm
1250 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1253 def ADD64ri8_DB : I<0, Pseudo,
1254 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1255 "", // orq/addq REG, imm8
1256 [(set GR64:$dst, (or_is_add GR64:$src1,
1257 i64immSExt8:$src2))]>;
1258 def ADD64ri32_DB : I<0, Pseudo,
1259 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1260 "", // orq/addq REG, imm
1261 [(set GR64:$dst, (or_is_add GR64:$src1,
1262 i64immSExt32:$src2))]>;
1264 } // AddedComplexity, SchedRW
1267 //===----------------------------------------------------------------------===//
1269 //===----------------------------------------------------------------------===//
1271 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1272 // +128 doesn't, so in this special case use a sub instead of an add.
1273 def : Pat<(add GR16:$src1, 128),
1274 (SUB16ri8 GR16:$src1, -128)>;
1275 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1276 (SUB16mi8 addr:$dst, -128)>;
1278 def : Pat<(add GR32:$src1, 128),
1279 (SUB32ri8 GR32:$src1, -128)>;
1280 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1281 (SUB32mi8 addr:$dst, -128)>;
1283 def : Pat<(add GR64:$src1, 128),
1284 (SUB64ri8 GR64:$src1, -128)>;
1285 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1286 (SUB64mi8 addr:$dst, -128)>;
1288 // The same trick applies for 32-bit immediate fields in 64-bit
1290 def : Pat<(add GR64:$src1, 0x0000000080000000),
1291 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1292 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1293 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1295 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1296 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1297 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1298 // represented with a sign extension of a 8 bit constant, use that.
1299 // This can also reduce instruction size by eliminating the need for the REX
1302 // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.
1303 let AddedComplexity = 1 in {
1304 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1308 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1309 (i32 (GetLo8XForm imm:$imm))),
1312 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1316 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1317 (i32 (GetLo32XForm imm:$imm))),
1319 } // AddedComplexity = 1
1322 // AddedComplexity is needed due to the increased complexity on the
1323 // i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all
1324 // the MOVZX patterns keeps thems together in DAGIsel tables.
1325 let AddedComplexity = 1 in {
1326 // r & (2^16-1) ==> movz
1327 def : Pat<(and GR32:$src1, 0xffff),
1328 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1329 // r & (2^8-1) ==> movz
1330 def : Pat<(and GR32:$src1, 0xff),
1331 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1334 Requires<[Not64BitMode]>;
1335 // r & (2^8-1) ==> movz
1336 def : Pat<(and GR16:$src1, 0xff),
1337 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1338 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1340 Requires<[Not64BitMode]>;
1342 // r & (2^32-1) ==> movz
1343 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1344 (SUBREG_TO_REG (i64 0),
1345 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1347 // r & (2^16-1) ==> movz
1348 def : Pat<(and GR64:$src, 0xffff),
1349 (SUBREG_TO_REG (i64 0),
1350 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1352 // r & (2^8-1) ==> movz
1353 def : Pat<(and GR64:$src, 0xff),
1354 (SUBREG_TO_REG (i64 0),
1355 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1357 // r & (2^8-1) ==> movz
1358 def : Pat<(and GR32:$src1, 0xff),
1359 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1360 Requires<[In64BitMode]>;
1361 // r & (2^8-1) ==> movz
1362 def : Pat<(and GR16:$src1, 0xff),
1363 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1364 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1365 Requires<[In64BitMode]>;
1366 } // AddedComplexity = 1
1369 // sext_inreg patterns
1370 def : Pat<(sext_inreg GR32:$src, i16),
1371 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1372 def : Pat<(sext_inreg GR32:$src, i8),
1373 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1376 Requires<[Not64BitMode]>;
1378 def : Pat<(sext_inreg GR16:$src, i8),
1379 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1380 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1382 Requires<[Not64BitMode]>;
1384 def : Pat<(sext_inreg GR64:$src, i32),
1385 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1386 def : Pat<(sext_inreg GR64:$src, i16),
1387 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1388 def : Pat<(sext_inreg GR64:$src, i8),
1389 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1390 def : Pat<(sext_inreg GR32:$src, i8),
1391 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1392 Requires<[In64BitMode]>;
1393 def : Pat<(sext_inreg GR16:$src, i8),
1394 (EXTRACT_SUBREG (MOVSX32rr8
1395 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1396 Requires<[In64BitMode]>;
1398 // sext, sext_load, zext, zext_load
1399 def: Pat<(i16 (sext GR8:$src)),
1400 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1401 def: Pat<(sextloadi16i8 addr:$src),
1402 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1403 def: Pat<(i16 (zext GR8:$src)),
1404 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1405 def: Pat<(zextloadi16i8 addr:$src),
1406 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1409 def : Pat<(i16 (trunc GR32:$src)),
1410 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1411 def : Pat<(i8 (trunc GR32:$src)),
1412 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1414 Requires<[Not64BitMode]>;
1415 def : Pat<(i8 (trunc GR16:$src)),
1416 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1418 Requires<[Not64BitMode]>;
1419 def : Pat<(i32 (trunc GR64:$src)),
1420 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1421 def : Pat<(i16 (trunc GR64:$src)),
1422 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1423 def : Pat<(i8 (trunc GR64:$src)),
1424 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1425 def : Pat<(i8 (trunc GR32:$src)),
1426 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1427 Requires<[In64BitMode]>;
1428 def : Pat<(i8 (trunc GR16:$src)),
1429 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1430 Requires<[In64BitMode]>;
1432 // h-register tricks
1433 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1434 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1436 Requires<[Not64BitMode]>;
1437 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1438 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1440 Requires<[Not64BitMode]>;
1441 def : Pat<(srl GR16:$src, (i8 8)),
1444 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1447 Requires<[Not64BitMode]>;
1448 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1449 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1452 Requires<[Not64BitMode]>;
1453 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1454 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1457 Requires<[Not64BitMode]>;
1458 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1459 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1462 Requires<[Not64BitMode]>;
1463 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1464 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1467 Requires<[Not64BitMode]>;
1469 // h-register tricks.
1470 // For now, be conservative on x86-64 and use an h-register extract only if the
1471 // value is immediately zero-extended or stored, which are somewhat common
1472 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1473 // from being allocated in the same instruction as the h register, as there's
1474 // currently no way to describe this requirement to the register allocator.
1476 // h-register extract and zero-extend.
1477 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1481 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1484 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1486 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1488 Requires<[In64BitMode]>;
1489 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1490 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1493 Requires<[In64BitMode]>;
1494 def : Pat<(srl GR16:$src, (i8 8)),
1497 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1500 Requires<[In64BitMode]>;
1501 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1503 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1505 Requires<[In64BitMode]>;
1506 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1508 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1510 Requires<[In64BitMode]>;
1511 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1515 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1518 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1522 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1526 // h-register extract and store.
1527 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1530 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1532 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1535 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1537 Requires<[In64BitMode]>;
1538 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1541 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1543 Requires<[In64BitMode]>;
1546 // (shl x, 1) ==> (add x, x)
1547 // Note that if x is undef (immediate or otherwise), we could theoretically
1548 // end up with the two uses of x getting different values, producing a result
1549 // where the least significant bit is not 0. However, the probability of this
1550 // happening is considered low enough that this is officially not a
1552 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1553 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1554 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1555 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1557 // Helper imms that check if a mask doesn't change significant shift bits.
1558 def immShift32 : ImmLeaf<i8, [{
1559 return countTrailingOnes<uint64_t>(Imm) >= 5;
1561 def immShift64 : ImmLeaf<i8, [{
1562 return countTrailingOnes<uint64_t>(Imm) >= 6;
1565 // Shift amount is implicitly masked.
1566 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1567 // (shift x (and y, 31)) ==> (shift x, y)
1568 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1569 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1570 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1571 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1572 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1573 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1574 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1575 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1576 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1577 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1578 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1579 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1581 // (shift x (and y, 63)) ==> (shift x, y)
1582 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1583 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1584 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1585 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1588 defm : MaskedShiftAmountPats<shl, "SHL">;
1589 defm : MaskedShiftAmountPats<srl, "SHR">;
1590 defm : MaskedShiftAmountPats<sra, "SAR">;
1591 defm : MaskedShiftAmountPats<rotl, "ROL">;
1592 defm : MaskedShiftAmountPats<rotr, "ROR">;
1594 // (anyext (setcc_carry)) -> (setcc_carry)
1595 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1597 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1599 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1605 //===----------------------------------------------------------------------===//
1606 // EFLAGS-defining Patterns
1607 //===----------------------------------------------------------------------===//
1610 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1611 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1612 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1615 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1616 (ADD8rm GR8:$src1, addr:$src2)>;
1617 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1618 (ADD16rm GR16:$src1, addr:$src2)>;
1619 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1620 (ADD32rm GR32:$src1, addr:$src2)>;
1623 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1624 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1625 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1626 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1627 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1628 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1629 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1632 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1633 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1634 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1637 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1638 (SUB8rm GR8:$src1, addr:$src2)>;
1639 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1640 (SUB16rm GR16:$src1, addr:$src2)>;
1641 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1642 (SUB32rm GR32:$src1, addr:$src2)>;
1645 def : Pat<(sub GR8:$src1, imm:$src2),
1646 (SUB8ri GR8:$src1, imm:$src2)>;
1647 def : Pat<(sub GR16:$src1, imm:$src2),
1648 (SUB16ri GR16:$src1, imm:$src2)>;
1649 def : Pat<(sub GR32:$src1, imm:$src2),
1650 (SUB32ri GR32:$src1, imm:$src2)>;
1651 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1652 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1653 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1654 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1657 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1658 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1659 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1660 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1663 def : Pat<(mul GR16:$src1, GR16:$src2),
1664 (IMUL16rr GR16:$src1, GR16:$src2)>;
1665 def : Pat<(mul GR32:$src1, GR32:$src2),
1666 (IMUL32rr GR32:$src1, GR32:$src2)>;
1669 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1670 (IMUL16rm GR16:$src1, addr:$src2)>;
1671 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1672 (IMUL32rm GR32:$src1, addr:$src2)>;
1675 def : Pat<(mul GR16:$src1, imm:$src2),
1676 (IMUL16rri GR16:$src1, imm:$src2)>;
1677 def : Pat<(mul GR32:$src1, imm:$src2),
1678 (IMUL32rri GR32:$src1, imm:$src2)>;
1679 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1680 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1681 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1682 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1684 // reg = mul mem, imm
1685 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1686 (IMUL16rmi addr:$src1, imm:$src2)>;
1687 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1688 (IMUL32rmi addr:$src1, imm:$src2)>;
1689 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1690 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1691 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1692 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1694 // Patterns for nodes that do not produce flags, for instructions that do.
1697 def : Pat<(add GR64:$src1, GR64:$src2),
1698 (ADD64rr GR64:$src1, GR64:$src2)>;
1699 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1700 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1701 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1702 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1703 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1704 (ADD64rm GR64:$src1, addr:$src2)>;
1707 def : Pat<(sub GR64:$src1, GR64:$src2),
1708 (SUB64rr GR64:$src1, GR64:$src2)>;
1709 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1710 (SUB64rm GR64:$src1, addr:$src2)>;
1711 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1712 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1713 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1714 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1717 def : Pat<(mul GR64:$src1, GR64:$src2),
1718 (IMUL64rr GR64:$src1, GR64:$src2)>;
1719 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1720 (IMUL64rm GR64:$src1, addr:$src2)>;
1721 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1722 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1723 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1724 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1725 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1726 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1727 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1728 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1730 // Increment/Decrement reg.
1731 // Do not make INC/DEC if it is slow
1732 let Predicates = [NotSlowIncDec] in {
1733 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
1734 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
1735 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
1736 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1737 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
1738 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
1739 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
1740 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1744 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1745 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1746 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1747 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1750 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1751 (OR8rm GR8:$src1, addr:$src2)>;
1752 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1753 (OR16rm GR16:$src1, addr:$src2)>;
1754 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1755 (OR32rm GR32:$src1, addr:$src2)>;
1756 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1757 (OR64rm GR64:$src1, addr:$src2)>;
1760 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1761 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1762 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1763 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1764 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1765 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1766 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1767 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1768 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1769 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1770 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1773 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1774 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1775 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1776 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1779 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1780 (XOR8rm GR8:$src1, addr:$src2)>;
1781 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1782 (XOR16rm GR16:$src1, addr:$src2)>;
1783 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1784 (XOR32rm GR32:$src1, addr:$src2)>;
1785 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1786 (XOR64rm GR64:$src1, addr:$src2)>;
1789 def : Pat<(xor GR8:$src1, imm:$src2),
1790 (XOR8ri GR8:$src1, imm:$src2)>;
1791 def : Pat<(xor GR16:$src1, imm:$src2),
1792 (XOR16ri GR16:$src1, imm:$src2)>;
1793 def : Pat<(xor GR32:$src1, imm:$src2),
1794 (XOR32ri GR32:$src1, imm:$src2)>;
1795 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1796 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1797 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1798 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1799 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1800 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1801 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1802 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1805 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1806 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1807 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1808 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1811 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1812 (AND8rm GR8:$src1, addr:$src2)>;
1813 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1814 (AND16rm GR16:$src1, addr:$src2)>;
1815 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1816 (AND32rm GR32:$src1, addr:$src2)>;
1817 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1818 (AND64rm GR64:$src1, addr:$src2)>;
1821 def : Pat<(and GR8:$src1, imm:$src2),
1822 (AND8ri GR8:$src1, imm:$src2)>;
1823 def : Pat<(and GR16:$src1, imm:$src2),
1824 (AND16ri GR16:$src1, imm:$src2)>;
1825 def : Pat<(and GR32:$src1, imm:$src2),
1826 (AND32ri GR32:$src1, imm:$src2)>;
1827 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1828 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1829 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1830 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1831 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1832 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1833 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1834 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1836 // Bit scan instruction patterns to match explicit zero-undef behavior.
1837 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1838 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1839 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1840 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1841 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1842 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1844 // When HasMOVBE is enabled it is possible to get a non-legalized
1845 // register-register 16 bit bswap. This maps it to a ROL instruction.
1846 let Predicates = [HasMOVBE] in {
1847 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;