1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1 in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
87 // and places the address of the next argument into a register.
88 let Defs = [EFLAGS] in
89 def VAARG_64 : I<0, Pseudo,
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
98 // targets. These calls are needed to probe the stack when allocating more than
99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
100 // ensure that the guard pages used by the OS virtual memory manager are
101 // allocated in correct sequence.
102 // The main point of having separate instruction are extra unmodelled effects
103 // (compared to ordinary calls) like stack pointer change.
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
107 "# dynamic stack allocation",
110 // When using segmented stacks these are lowered into instructions which first
111 // check if the current stacklet has enough free memory. If it does, memory is
112 // allocated by bumping the stack pointer. Otherwise memory is allocated from
115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
117 "# variable sized alloca for segmented stacks",
119 (X86SegAlloca GR32:$size))]>,
120 Requires<[In32BitMode]>;
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
123 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
124 "# variable sized alloca for segmented stacks",
126 (X86SegAlloca GR64:$size))]>,
127 Requires<[In64BitMode]>;
130 // The MSVC runtime contains an _ftol2 routine for converting floating-point
131 // to integer values. It has a strange calling convention: the input is
132 // popped from the x87 stack, and the return value is given in EDX:EAX. No
133 // other registers (aside from flags) are touched.
134 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
135 // variant is unnecessary.
137 let Defs = [EAX, EDX, EFLAGS], FPForm = SpecialFP in {
138 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
140 [(X86WinFTOL RFP32:$src)]>,
141 Requires<[In32BitMode]>;
143 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
145 [(X86WinFTOL RFP64:$src)]>,
146 Requires<[In32BitMode]>;
149 //===----------------------------------------------------------------------===//
150 // EH Pseudo Instructions
152 let SchedRW = [WriteSystem] in {
153 let isTerminator = 1, isReturn = 1, isBarrier = 1,
154 hasCtrlDep = 1, isCodeGenOnly = 1 in {
155 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
156 "ret\t#eh_return, addr: $addr",
157 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
161 let isTerminator = 1, isReturn = 1, isBarrier = 1,
162 hasCtrlDep = 1, isCodeGenOnly = 1 in {
163 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
164 "ret\t#eh_return, addr: $addr",
165 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
169 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
170 usesCustomInserter = 1 in {
171 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
173 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
174 Requires<[In32BitMode]>;
175 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
177 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
178 Requires<[In64BitMode]>;
179 let isTerminator = 1 in {
180 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
181 "#EH_SJLJ_LONGJMP32",
182 [(X86eh_sjlj_longjmp addr:$buf)]>,
183 Requires<[In32BitMode]>;
184 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
185 "#EH_SJLJ_LONGJMP64",
186 [(X86eh_sjlj_longjmp addr:$buf)]>,
187 Requires<[In64BitMode]>;
192 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
193 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
194 "#EH_SjLj_Setup\t$dst", []>;
197 //===----------------------------------------------------------------------===//
198 // Pseudo instructions used by segmented stacks.
201 // This is lowered into a RET instruction by MCInstLower. We need
202 // this so that we don't have to have a MachineBasicBlock which ends
203 // with a RET and also has successors.
204 let isPseudo = 1 in {
205 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
208 // This instruction is lowered to a RET followed by a MOV. The two
209 // instructions are not generated on a higher level since then the
210 // verifier sees a MachineBasicBlock ending with a non-terminator.
211 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
215 //===----------------------------------------------------------------------===//
216 // Alias Instructions
217 //===----------------------------------------------------------------------===//
219 // Alias instruction mapping movr0 to xor.
220 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
221 // FIXME: Set encoding to pseudo.
222 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
224 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
225 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
227 // Other widths can also make use of the 32-bit xor, which may have a smaller
228 // encoding and avoid partial register updates.
229 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
230 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
231 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
232 let AddedComplexity = 20;
235 // Materialize i64 constant where top 32-bits are zero. This could theoretically
236 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
237 // that would make it more difficult to rematerialize.
238 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
240 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
241 "", [(set GR64:$dst, i64immZExt32:$src)],
242 IIC_ALU_NONMEM>, Sched<[WriteALU]>;
244 // Use sbb to materialize carry bit.
245 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
246 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
247 // However, Pat<> can't replicate the destination reg into the inputs of the
249 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
250 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
251 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
252 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
253 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
254 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
255 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
256 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
260 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
262 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
264 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
267 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
269 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
271 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
274 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
275 // will be eliminated and that the sbb can be extended up to a wider type. When
276 // this happens, it is great. However, if we are left with an 8-bit sbb and an
277 // and, we might as well just match it as a setb.
278 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
281 // (add OP, SETB) -> (adc OP, 0)
282 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
283 (ADC8ri GR8:$op, 0)>;
284 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
285 (ADC32ri8 GR32:$op, 0)>;
286 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
287 (ADC64ri8 GR64:$op, 0)>;
289 // (sub OP, SETB) -> (sbb OP, 0)
290 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
291 (SBB8ri GR8:$op, 0)>;
292 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
293 (SBB32ri8 GR32:$op, 0)>;
294 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
295 (SBB64ri8 GR64:$op, 0)>;
297 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
298 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
299 (ADC8ri GR8:$op, 0)>;
300 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
301 (ADC32ri8 GR32:$op, 0)>;
302 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
303 (ADC64ri8 GR64:$op, 0)>;
305 //===----------------------------------------------------------------------===//
306 // String Pseudo Instructions
308 let SchedRW = [WriteMicrocoded] in {
309 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
310 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
311 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
312 Requires<[In32BitMode]>;
313 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
314 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
315 Requires<[In32BitMode]>;
316 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
317 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
318 Requires<[In32BitMode]>;
321 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
322 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
323 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
324 Requires<[In64BitMode]>;
325 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
326 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
327 Requires<[In64BitMode]>;
328 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
329 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
330 Requires<[In64BitMode]>;
331 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
332 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
333 Requires<[In64BitMode]>;
336 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
337 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
338 let Uses = [AL,ECX,EDI] in
339 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
340 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
341 Requires<[In32BitMode]>;
342 let Uses = [AX,ECX,EDI] in
343 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
344 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
345 Requires<[In32BitMode]>;
346 let Uses = [EAX,ECX,EDI] in
347 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
348 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
349 Requires<[In32BitMode]>;
352 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
353 let Uses = [AL,RCX,RDI] in
354 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
355 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
356 Requires<[In64BitMode]>;
357 let Uses = [AX,RCX,RDI] in
358 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
359 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
360 Requires<[In64BitMode]>;
361 let Uses = [RAX,RCX,RDI] in
362 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
363 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
364 Requires<[In64BitMode]>;
366 let Uses = [RAX,RCX,RDI] in
367 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
368 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
369 Requires<[In64BitMode]>;
373 //===----------------------------------------------------------------------===//
374 // Thread Local Storage Instructions
378 // All calls clobber the non-callee saved registers. ESP is marked as
379 // a use to prevent stack-pointer assignments that appear immediately
380 // before calls from potentially appearing dead.
381 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
382 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
383 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
384 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
386 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
388 [(X86tlsaddr tls32addr:$sym)]>,
389 Requires<[In32BitMode]>;
390 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
392 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
393 Requires<[In32BitMode]>;
396 // All calls clobber the non-callee saved registers. RSP is marked as
397 // a use to prevent stack-pointer assignments that appear immediately
398 // before calls from potentially appearing dead.
399 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
400 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
401 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
402 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
403 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
405 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
407 [(X86tlsaddr tls64addr:$sym)]>,
408 Requires<[In64BitMode]>;
409 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
411 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
412 Requires<[In64BitMode]>;
415 // Darwin TLS Support
416 // For i386, the address of the thunk is passed on the stack, on return the
417 // address of the variable is in %eax. %ecx is trashed during the function
418 // call. All other registers are preserved.
419 let Defs = [EAX, ECX, EFLAGS],
421 usesCustomInserter = 1 in
422 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
424 [(X86TLSCall addr:$sym)]>,
425 Requires<[In32BitMode]>;
427 // For x86_64, the address of the thunk is passed in %rdi, on return
428 // the address of the variable is in %rax. All other registers are preserved.
429 let Defs = [RAX, EFLAGS],
431 usesCustomInserter = 1 in
432 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
434 [(X86TLSCall addr:$sym)]>,
435 Requires<[In64BitMode]>;
438 //===----------------------------------------------------------------------===//
439 // Conditional Move Pseudo Instructions
441 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
442 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
443 // however that requires promoting the operands, and can induce additional
444 // i8 register pressure.
445 let usesCustomInserter = 1, Uses = [EFLAGS] in {
446 def CMOV_GR8 : I<0, Pseudo,
447 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
449 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
450 imm:$cond, EFLAGS))]>;
452 let Predicates = [NoCMov] in {
453 def CMOV_GR32 : I<0, Pseudo,
454 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
455 "#CMOV_GR32* PSEUDO!",
457 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
458 def CMOV_GR16 : I<0, Pseudo,
459 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
460 "#CMOV_GR16* PSEUDO!",
462 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
463 } // Predicates = [NoCMov]
465 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
467 let Predicates = [FPStackf32] in
468 def CMOV_RFP32 : I<0, Pseudo,
470 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
471 "#CMOV_RFP32 PSEUDO!",
473 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
475 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
477 let Predicates = [FPStackf64] in
478 def CMOV_RFP64 : I<0, Pseudo,
480 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
481 "#CMOV_RFP64 PSEUDO!",
483 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
485 def CMOV_RFP80 : I<0, Pseudo,
487 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
488 "#CMOV_RFP80 PSEUDO!",
490 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
492 } // UsesCustomInserter = 1, Uses = [EFLAGS]
495 //===----------------------------------------------------------------------===//
496 // Atomic Instruction Pseudo Instructions
497 //===----------------------------------------------------------------------===//
499 // Pseudo atomic instructions
501 multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> {
502 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in {
503 let Defs = [EFLAGS, AL] in
504 def NAME#8 : I<0, Pseudo, (outs GR8:$dst),
505 (ins i8mem:$ptr, GR8:$val),
506 !strconcat(mnemonic, "8 PSEUDO!"), []>;
507 let Defs = [EFLAGS, AX] in
508 def NAME#16 : I<0, Pseudo,(outs GR16:$dst),
509 (ins i16mem:$ptr, GR16:$val),
510 !strconcat(mnemonic, "16 PSEUDO!"), []>;
511 let Defs = [EFLAGS, EAX] in
512 def NAME#32 : I<0, Pseudo, (outs GR32:$dst),
513 (ins i32mem:$ptr, GR32:$val),
514 !strconcat(mnemonic, "32 PSEUDO!"), []>;
515 let Defs = [EFLAGS, RAX] in
516 def NAME#64 : I<0, Pseudo, (outs GR64:$dst),
517 (ins i64mem:$ptr, GR64:$val),
518 !strconcat(mnemonic, "64 PSEUDO!"), []>;
522 multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> {
523 def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val),
524 (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>;
525 def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val),
526 (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>;
527 def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val),
528 (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>;
529 def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val),
530 (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>;
533 // Atomic exchange, and, or, xor
534 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">;
535 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">;
536 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">;
537 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">;
538 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">;
539 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">;
540 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">;
541 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">;
543 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">;
544 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">;
545 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">;
546 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">;
547 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">;
548 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">;
549 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">;
550 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">;
552 multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> {
553 let usesCustomInserter = 1, Defs = [EFLAGS, EAX, EDX],
554 mayLoad = 1, mayStore = 1, hasSideEffects = 0 in
555 def NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
556 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
557 !strconcat(mnemonic, "6432 PSEUDO!"), []>;
560 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMAND">;
561 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMOR">;
562 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMXOR">;
563 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMNAND">;
564 defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMADD">;
565 defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSUB">;
566 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMAX">;
567 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMIN">;
568 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMAX">;
569 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMIN">;
570 defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSWAP">;
572 //===----------------------------------------------------------------------===//
573 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
574 //===----------------------------------------------------------------------===//
576 // FIXME: Use normal instructions and add lock prefix dynamically.
580 // TODO: Get this to fold the constant into the instruction.
581 let isCodeGenOnly = 1, Defs = [EFLAGS] in
582 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
583 "or{l}\t{$zero, $dst|$dst, $zero}",
584 [], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK,
585 Sched<[WriteALULd, WriteRMW]>;
587 let hasSideEffects = 1 in
588 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
590 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
592 // RegOpc corresponds to the mr version of the instruction
593 // ImmOpc corresponds to the mi version of the instruction
594 // ImmOpc8 corresponds to the mi8 version of the instruction
595 // ImmMod corresponds to the instruction format of the mi and mi8 versions
596 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
597 Format ImmMod, string mnemonic> {
598 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
599 SchedRW = [WriteALULd, WriteRMW] in {
601 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
602 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
603 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
604 !strconcat(mnemonic, "{b}\t",
605 "{$src2, $dst|$dst, $src2}"),
606 [], IIC_ALU_NONMEM>, LOCK;
607 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
608 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
609 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
610 !strconcat(mnemonic, "{w}\t",
611 "{$src2, $dst|$dst, $src2}"),
612 [], IIC_ALU_NONMEM>, OpSize, LOCK;
613 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
614 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
615 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
616 !strconcat(mnemonic, "{l}\t",
617 "{$src2, $dst|$dst, $src2}"),
618 [], IIC_ALU_NONMEM>, LOCK;
619 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
620 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
621 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
622 !strconcat(mnemonic, "{q}\t",
623 "{$src2, $dst|$dst, $src2}"),
624 [], IIC_ALU_NONMEM>, LOCK;
626 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
627 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
628 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
629 !strconcat(mnemonic, "{b}\t",
630 "{$src2, $dst|$dst, $src2}"),
631 [], IIC_ALU_MEM>, LOCK;
633 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
634 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
635 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
636 !strconcat(mnemonic, "{w}\t",
637 "{$src2, $dst|$dst, $src2}"),
638 [], IIC_ALU_MEM>, OpSize, LOCK;
640 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
641 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
642 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
643 !strconcat(mnemonic, "{l}\t",
644 "{$src2, $dst|$dst, $src2}"),
645 [], IIC_ALU_MEM>, LOCK;
647 def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
648 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
649 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
650 !strconcat(mnemonic, "{q}\t",
651 "{$src2, $dst|$dst, $src2}"),
652 [], IIC_ALU_MEM>, LOCK;
654 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
655 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
656 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
657 !strconcat(mnemonic, "{w}\t",
658 "{$src2, $dst|$dst, $src2}"),
659 [], IIC_ALU_MEM>, OpSize, LOCK;
660 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
661 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
662 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
663 !strconcat(mnemonic, "{l}\t",
664 "{$src2, $dst|$dst, $src2}"),
665 [], IIC_ALU_MEM>, LOCK;
666 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
667 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
668 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
669 !strconcat(mnemonic, "{q}\t",
670 "{$src2, $dst|$dst, $src2}"),
671 [], IIC_ALU_MEM>, LOCK;
677 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
678 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
679 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
680 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
681 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
683 // Optimized codegen when the non-memory output is not used.
684 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
686 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
687 SchedRW = [WriteALULd, WriteRMW] in {
689 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
690 !strconcat(mnemonic, "{b}\t$dst"),
691 [], IIC_UNARY_MEM>, LOCK;
692 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
693 !strconcat(mnemonic, "{w}\t$dst"),
694 [], IIC_UNARY_MEM>, OpSize, LOCK;
695 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
696 !strconcat(mnemonic, "{l}\t$dst"),
697 [], IIC_UNARY_MEM>, LOCK;
698 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
699 !strconcat(mnemonic, "{q}\t$dst"),
700 [], IIC_UNARY_MEM>, LOCK;
704 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
705 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
707 // Atomic compare and swap.
708 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
709 SDPatternOperator frag, X86MemOperand x86memop,
710 InstrItinClass itin> {
711 let isCodeGenOnly = 1 in {
712 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
713 !strconcat(mnemonic, "\t$ptr"),
714 [(frag addr:$ptr)], itin>, TB, LOCK;
718 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
719 string mnemonic, SDPatternOperator frag,
720 InstrItinClass itin8, InstrItinClass itin> {
721 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
722 let Defs = [AL, EFLAGS], Uses = [AL] in
723 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
724 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
725 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
726 let Defs = [AX, EFLAGS], Uses = [AX] in
727 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
728 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
729 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;
730 let Defs = [EAX, EFLAGS], Uses = [EAX] in
731 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
732 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
733 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;
734 let Defs = [RAX, EFLAGS], Uses = [RAX] in
735 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
736 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
737 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
741 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
742 SchedRW = [WriteALULd, WriteRMW] in {
743 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
748 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
749 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
750 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
752 IIC_CMPX_LOCK_16B>, REX_W;
755 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
756 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
758 // Atomic exchange and add
759 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
761 InstrItinClass itin8, InstrItinClass itin> {
762 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
763 SchedRW = [WriteALULd, WriteRMW] in {
764 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
765 (ins GR8:$val, i8mem:$ptr),
766 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
768 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
770 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
771 (ins GR16:$val, i16mem:$ptr),
772 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
775 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
777 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
778 (ins GR32:$val, i32mem:$ptr),
779 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
782 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
784 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
785 (ins GR64:$val, i64mem:$ptr),
786 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
789 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
794 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
795 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
798 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
799 "#ACQUIRE_MOV PSEUDO!",
800 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
801 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
802 "#ACQUIRE_MOV PSEUDO!",
803 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
804 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
805 "#ACQUIRE_MOV PSEUDO!",
806 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
807 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
808 "#ACQUIRE_MOV PSEUDO!",
809 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
811 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
812 "#RELEASE_MOV PSEUDO!",
813 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
814 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
815 "#RELEASE_MOV PSEUDO!",
816 [(atomic_store_16 addr:$dst, GR16:$src)]>;
817 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
818 "#RELEASE_MOV PSEUDO!",
819 [(atomic_store_32 addr:$dst, GR32:$src)]>;
820 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
821 "#RELEASE_MOV PSEUDO!",
822 [(atomic_store_64 addr:$dst, GR64:$src)]>;
824 //===----------------------------------------------------------------------===//
825 // Conditional Move Pseudo Instructions.
826 //===----------------------------------------------------------------------===//
829 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
830 // instruction selection into a branch sequence.
831 let Uses = [EFLAGS], usesCustomInserter = 1 in {
832 def CMOV_FR32 : I<0, Pseudo,
833 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
834 "#CMOV_FR32 PSEUDO!",
835 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
837 def CMOV_FR64 : I<0, Pseudo,
838 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
839 "#CMOV_FR64 PSEUDO!",
840 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
842 def CMOV_V4F32 : I<0, Pseudo,
843 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
844 "#CMOV_V4F32 PSEUDO!",
846 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
848 def CMOV_V2F64 : I<0, Pseudo,
849 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
850 "#CMOV_V2F64 PSEUDO!",
852 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
854 def CMOV_V2I64 : I<0, Pseudo,
855 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
856 "#CMOV_V2I64 PSEUDO!",
858 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
860 def CMOV_V8F32 : I<0, Pseudo,
861 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
862 "#CMOV_V8F32 PSEUDO!",
864 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
866 def CMOV_V4F64 : I<0, Pseudo,
867 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
868 "#CMOV_V4F64 PSEUDO!",
870 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
872 def CMOV_V4I64 : I<0, Pseudo,
873 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
874 "#CMOV_V4I64 PSEUDO!",
876 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
881 //===----------------------------------------------------------------------===//
882 // DAG Pattern Matching Rules
883 //===----------------------------------------------------------------------===//
885 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
886 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
887 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
888 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
889 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
890 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
891 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
893 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
894 (ADD32ri GR32:$src1, tconstpool:$src2)>;
895 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
896 (ADD32ri GR32:$src1, tjumptable:$src2)>;
897 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
898 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
899 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
900 (ADD32ri GR32:$src1, texternalsym:$src2)>;
901 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
902 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
904 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
905 (MOV32mi addr:$dst, tglobaladdr:$src)>;
906 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
907 (MOV32mi addr:$dst, texternalsym:$src)>;
908 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
909 (MOV32mi addr:$dst, tblockaddress:$src)>;
913 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
914 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
915 // 'movabs' predicate should handle this sort of thing.
916 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
917 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
918 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
919 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
920 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
921 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
922 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
923 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
924 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
925 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
927 // In static codegen with small code model, we can get the address of a label
928 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
929 // the MOV64ri64i32 should accept these.
930 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
931 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
932 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
933 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
934 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
935 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
936 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
937 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
938 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
939 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
941 // In kernel code model, we can get the address of a label
942 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
943 // the MOV64ri32 should accept these.
944 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
945 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
946 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
947 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
948 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
949 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
950 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
951 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
952 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
953 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
955 // If we have small model and -static mode, it is safe to store global addresses
956 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
957 // for MOV64mi32 should handle this sort of thing.
958 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
959 (MOV64mi32 addr:$dst, tconstpool:$src)>,
960 Requires<[NearData, IsStatic]>;
961 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
962 (MOV64mi32 addr:$dst, tjumptable:$src)>,
963 Requires<[NearData, IsStatic]>;
964 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
965 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
966 Requires<[NearData, IsStatic]>;
967 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
968 (MOV64mi32 addr:$dst, texternalsym:$src)>,
969 Requires<[NearData, IsStatic]>;
970 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
971 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
972 Requires<[NearData, IsStatic]>;
978 // tls has some funny stuff here...
979 // This corresponds to movabs $foo@tpoff, %rax
980 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
981 (MOV64ri tglobaltlsaddr :$dst)>;
982 // This corresponds to add $foo@tpoff, %rax
983 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
984 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
987 // Direct PC relative function call for small code model. 32-bit displacement
988 // sign extended to 64-bit.
989 def : Pat<(X86call (i64 tglobaladdr:$dst)),
990 (CALL64pcrel32 tglobaladdr:$dst)>;
991 def : Pat<(X86call (i64 texternalsym:$dst)),
992 (CALL64pcrel32 texternalsym:$dst)>;
994 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
995 // can never use callee-saved registers. That is the purpose of the GR64_TC
998 // The only volatile register that is never used by the calling convention is
999 // %r11. This happens when calling a vararg function with 6 arguments.
1001 // Match an X86tcret that uses less than 7 volatile registers.
1002 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1003 (X86tcret node:$ptr, node:$off), [{
1004 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1005 unsigned NumRegs = 0;
1006 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1007 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1012 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1013 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1014 Requires<[In32BitMode]>;
1016 // FIXME: This is disabled for 32-bit PIC mode because the global base
1017 // register which is part of the address mode may be assigned a
1018 // callee-saved register.
1019 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1020 (TCRETURNmi addr:$dst, imm:$off)>,
1021 Requires<[In32BitMode, IsNotPIC]>;
1023 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1024 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1025 Requires<[In32BitMode]>;
1027 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1028 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1029 Requires<[In32BitMode]>;
1031 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1032 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1033 Requires<[In64BitMode]>;
1035 // Don't fold loads into X86tcret requiring more than 6 regs.
1036 // There wouldn't be enough scratch registers for base+index.
1037 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1038 (TCRETURNmi64 addr:$dst, imm:$off)>,
1039 Requires<[In64BitMode]>;
1041 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1042 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1043 Requires<[In64BitMode]>;
1045 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1046 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1047 Requires<[In64BitMode]>;
1049 // Normal calls, with various flavors of addresses.
1050 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1051 (CALLpcrel32 tglobaladdr:$dst)>;
1052 def : Pat<(X86call (i32 texternalsym:$dst)),
1053 (CALLpcrel32 texternalsym:$dst)>;
1054 def : Pat<(X86call (i32 imm:$dst)),
1055 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1059 // TEST R,R is smaller than CMP R,0
1060 def : Pat<(X86cmp GR8:$src1, 0),
1061 (TEST8rr GR8:$src1, GR8:$src1)>;
1062 def : Pat<(X86cmp GR16:$src1, 0),
1063 (TEST16rr GR16:$src1, GR16:$src1)>;
1064 def : Pat<(X86cmp GR32:$src1, 0),
1065 (TEST32rr GR32:$src1, GR32:$src1)>;
1066 def : Pat<(X86cmp GR64:$src1, 0),
1067 (TEST64rr GR64:$src1, GR64:$src1)>;
1069 // Conditional moves with folded loads with operands swapped and conditions
1071 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1072 Instruction Inst64> {
1073 let Predicates = [HasCMov] in {
1074 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1075 (Inst16 GR16:$src2, addr:$src1)>;
1076 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1077 (Inst32 GR32:$src2, addr:$src1)>;
1078 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1079 (Inst64 GR64:$src2, addr:$src1)>;
1083 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1084 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1085 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1086 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1087 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1088 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1089 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1090 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1091 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1092 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1093 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1094 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1095 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1096 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1097 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1098 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1100 // zextload bool -> zextload byte
1101 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1102 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1103 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1104 def : Pat<(zextloadi64i1 addr:$src),
1105 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1107 // extload bool -> extload byte
1108 // When extloading from 16-bit and smaller memory locations into 64-bit
1109 // registers, use zero-extending loads so that the entire 64-bit register is
1110 // defined, avoiding partial-register updates.
1112 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1113 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1114 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1115 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1116 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1117 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1119 // For other extloads, use subregs, since the high contents of the register are
1120 // defined after an extload.
1121 def : Pat<(extloadi64i1 addr:$src),
1122 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1123 def : Pat<(extloadi64i8 addr:$src),
1124 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1125 def : Pat<(extloadi64i16 addr:$src),
1126 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1127 def : Pat<(extloadi64i32 addr:$src),
1128 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1130 // anyext. Define these to do an explicit zero-extend to
1131 // avoid partial-register updates.
1132 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1133 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1134 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1136 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1137 def : Pat<(i32 (anyext GR16:$src)),
1138 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1140 def : Pat<(i64 (anyext GR8 :$src)),
1141 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1142 def : Pat<(i64 (anyext GR16:$src)),
1143 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1144 def : Pat<(i64 (anyext GR32:$src)),
1145 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1148 // Any instruction that defines a 32-bit result leaves the high half of the
1149 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1150 // be copying from a truncate. And x86's cmov doesn't do anything if the
1151 // condition is false. But any other 32-bit operation will zero-extend
1153 def def32 : PatLeaf<(i32 GR32:$src), [{
1154 return N->getOpcode() != ISD::TRUNCATE &&
1155 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1156 N->getOpcode() != ISD::CopyFromReg &&
1157 N->getOpcode() != X86ISD::CMOV;
1160 // In the case of a 32-bit def that is known to implicitly zero-extend,
1161 // we can use a SUBREG_TO_REG.
1162 def : Pat<(i64 (zext def32:$src)),
1163 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1165 //===----------------------------------------------------------------------===//
1166 // Pattern match OR as ADD
1167 //===----------------------------------------------------------------------===//
1169 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1170 // 3-addressified into an LEA instruction to avoid copies. However, we also
1171 // want to finally emit these instructions as an or at the end of the code
1172 // generator to make the generated code easier to read. To do this, we select
1173 // into "disjoint bits" pseudo ops.
1175 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1176 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1177 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1178 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1180 APInt KnownZero0, KnownOne0;
1181 CurDAG->ComputeMaskedBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1182 APInt KnownZero1, KnownOne1;
1183 CurDAG->ComputeMaskedBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1184 return (~KnownZero0 & ~KnownZero1) == 0;
1188 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1189 // Try this before the selecting to OR.
1190 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1192 let isConvertibleToThreeAddress = 1,
1193 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1194 let isCommutable = 1 in {
1195 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1196 "", // orw/addw REG, REG
1197 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1198 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1199 "", // orl/addl REG, REG
1200 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1201 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1202 "", // orq/addq REG, REG
1203 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1206 // NOTE: These are order specific, we want the ri8 forms to be listed
1207 // first so that they are slightly preferred to the ri forms.
1209 def ADD16ri8_DB : I<0, Pseudo,
1210 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1211 "", // orw/addw REG, imm8
1212 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1213 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1214 "", // orw/addw REG, imm
1215 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1217 def ADD32ri8_DB : I<0, Pseudo,
1218 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1219 "", // orl/addl REG, imm8
1220 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1221 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1222 "", // orl/addl REG, imm
1223 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1226 def ADD64ri8_DB : I<0, Pseudo,
1227 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1228 "", // orq/addq REG, imm8
1229 [(set GR64:$dst, (or_is_add GR64:$src1,
1230 i64immSExt8:$src2))]>;
1231 def ADD64ri32_DB : I<0, Pseudo,
1232 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1233 "", // orq/addq REG, imm
1234 [(set GR64:$dst, (or_is_add GR64:$src1,
1235 i64immSExt32:$src2))]>;
1237 } // AddedComplexity, SchedRW
1240 //===----------------------------------------------------------------------===//
1242 //===----------------------------------------------------------------------===//
1244 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1245 // +128 doesn't, so in this special case use a sub instead of an add.
1246 def : Pat<(add GR16:$src1, 128),
1247 (SUB16ri8 GR16:$src1, -128)>;
1248 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1249 (SUB16mi8 addr:$dst, -128)>;
1251 def : Pat<(add GR32:$src1, 128),
1252 (SUB32ri8 GR32:$src1, -128)>;
1253 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1254 (SUB32mi8 addr:$dst, -128)>;
1256 def : Pat<(add GR64:$src1, 128),
1257 (SUB64ri8 GR64:$src1, -128)>;
1258 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1259 (SUB64mi8 addr:$dst, -128)>;
1261 // The same trick applies for 32-bit immediate fields in 64-bit
1263 def : Pat<(add GR64:$src1, 0x0000000080000000),
1264 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1265 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1266 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1268 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1269 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1270 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1271 // represented with a sign extension of a 8 bit constant, use that.
1273 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1277 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1278 (i32 (GetLo8XForm imm:$imm))),
1281 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1285 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1286 (i32 (GetLo32XForm imm:$imm))),
1290 // r & (2^16-1) ==> movz
1291 def : Pat<(and GR32:$src1, 0xffff),
1292 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1293 // r & (2^8-1) ==> movz
1294 def : Pat<(and GR32:$src1, 0xff),
1295 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1298 Requires<[In32BitMode]>;
1299 // r & (2^8-1) ==> movz
1300 def : Pat<(and GR16:$src1, 0xff),
1301 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1302 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1304 Requires<[In32BitMode]>;
1306 // r & (2^32-1) ==> movz
1307 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1308 (SUBREG_TO_REG (i64 0),
1309 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1311 // r & (2^16-1) ==> movz
1312 def : Pat<(and GR64:$src, 0xffff),
1313 (SUBREG_TO_REG (i64 0),
1314 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1316 // r & (2^8-1) ==> movz
1317 def : Pat<(and GR64:$src, 0xff),
1318 (SUBREG_TO_REG (i64 0),
1319 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1321 // r & (2^8-1) ==> movz
1322 def : Pat<(and GR32:$src1, 0xff),
1323 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1324 Requires<[In64BitMode]>;
1325 // r & (2^8-1) ==> movz
1326 def : Pat<(and GR16:$src1, 0xff),
1327 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1328 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1329 Requires<[In64BitMode]>;
1332 // sext_inreg patterns
1333 def : Pat<(sext_inreg GR32:$src, i16),
1334 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1335 def : Pat<(sext_inreg GR32:$src, i8),
1336 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1339 Requires<[In32BitMode]>;
1341 def : Pat<(sext_inreg GR16:$src, i8),
1342 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1343 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1345 Requires<[In32BitMode]>;
1347 def : Pat<(sext_inreg GR64:$src, i32),
1348 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1349 def : Pat<(sext_inreg GR64:$src, i16),
1350 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1351 def : Pat<(sext_inreg GR64:$src, i8),
1352 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1353 def : Pat<(sext_inreg GR32:$src, i8),
1354 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1355 Requires<[In64BitMode]>;
1356 def : Pat<(sext_inreg GR16:$src, i8),
1357 (EXTRACT_SUBREG (MOVSX32rr8
1358 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1359 Requires<[In64BitMode]>;
1361 // sext, sext_load, zext, zext_load
1362 def: Pat<(i16 (sext GR8:$src)),
1363 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1364 def: Pat<(sextloadi16i8 addr:$src),
1365 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1366 def: Pat<(i16 (zext GR8:$src)),
1367 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1368 def: Pat<(zextloadi16i8 addr:$src),
1369 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1372 def : Pat<(i16 (trunc GR32:$src)),
1373 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1374 def : Pat<(i8 (trunc GR32:$src)),
1375 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1377 Requires<[In32BitMode]>;
1378 def : Pat<(i8 (trunc GR16:$src)),
1379 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1381 Requires<[In32BitMode]>;
1382 def : Pat<(i32 (trunc GR64:$src)),
1383 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1384 def : Pat<(i16 (trunc GR64:$src)),
1385 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1386 def : Pat<(i8 (trunc GR64:$src)),
1387 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1388 def : Pat<(i8 (trunc GR32:$src)),
1389 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1390 Requires<[In64BitMode]>;
1391 def : Pat<(i8 (trunc GR16:$src)),
1392 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1393 Requires<[In64BitMode]>;
1395 // h-register tricks
1396 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1397 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1399 Requires<[In32BitMode]>;
1400 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1401 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1403 Requires<[In32BitMode]>;
1404 def : Pat<(srl GR16:$src, (i8 8)),
1407 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1410 Requires<[In32BitMode]>;
1411 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1412 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1415 Requires<[In32BitMode]>;
1416 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1417 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1420 Requires<[In32BitMode]>;
1421 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1422 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1425 Requires<[In32BitMode]>;
1426 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1427 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1430 Requires<[In32BitMode]>;
1432 // h-register tricks.
1433 // For now, be conservative on x86-64 and use an h-register extract only if the
1434 // value is immediately zero-extended or stored, which are somewhat common
1435 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1436 // from being allocated in the same instruction as the h register, as there's
1437 // currently no way to describe this requirement to the register allocator.
1439 // h-register extract and zero-extend.
1440 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1444 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1447 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1449 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1451 Requires<[In64BitMode]>;
1452 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1453 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1456 Requires<[In64BitMode]>;
1457 def : Pat<(srl GR16:$src, (i8 8)),
1460 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1463 Requires<[In64BitMode]>;
1464 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1466 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1468 Requires<[In64BitMode]>;
1469 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1471 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1473 Requires<[In64BitMode]>;
1474 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1478 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1481 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1485 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1489 // h-register extract and store.
1490 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1493 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1495 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1498 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1500 Requires<[In64BitMode]>;
1501 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1504 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1506 Requires<[In64BitMode]>;
1509 // (shl x, 1) ==> (add x, x)
1510 // Note that if x is undef (immediate or otherwise), we could theoretically
1511 // end up with the two uses of x getting different values, producing a result
1512 // where the least significant bit is not 0. However, the probability of this
1513 // happening is considered low enough that this is officially not a
1515 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1516 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1517 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1518 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1520 // Helper imms that check if a mask doesn't change significant shift bits.
1521 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1522 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1524 // (shl x (and y, 31)) ==> (shl x, y)
1525 def : Pat<(shl GR8:$src1, (and CL, immShift32)),
1526 (SHL8rCL GR8:$src1)>;
1527 def : Pat<(shl GR16:$src1, (and CL, immShift32)),
1528 (SHL16rCL GR16:$src1)>;
1529 def : Pat<(shl GR32:$src1, (and CL, immShift32)),
1530 (SHL32rCL GR32:$src1)>;
1531 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1532 (SHL8mCL addr:$dst)>;
1533 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1534 (SHL16mCL addr:$dst)>;
1535 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1536 (SHL32mCL addr:$dst)>;
1538 def : Pat<(srl GR8:$src1, (and CL, immShift32)),
1539 (SHR8rCL GR8:$src1)>;
1540 def : Pat<(srl GR16:$src1, (and CL, immShift32)),
1541 (SHR16rCL GR16:$src1)>;
1542 def : Pat<(srl GR32:$src1, (and CL, immShift32)),
1543 (SHR32rCL GR32:$src1)>;
1544 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1545 (SHR8mCL addr:$dst)>;
1546 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1547 (SHR16mCL addr:$dst)>;
1548 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1549 (SHR32mCL addr:$dst)>;
1551 def : Pat<(sra GR8:$src1, (and CL, immShift32)),
1552 (SAR8rCL GR8:$src1)>;
1553 def : Pat<(sra GR16:$src1, (and CL, immShift32)),
1554 (SAR16rCL GR16:$src1)>;
1555 def : Pat<(sra GR32:$src1, (and CL, immShift32)),
1556 (SAR32rCL GR32:$src1)>;
1557 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1558 (SAR8mCL addr:$dst)>;
1559 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1560 (SAR16mCL addr:$dst)>;
1561 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1562 (SAR32mCL addr:$dst)>;
1564 // (shl x (and y, 63)) ==> (shl x, y)
1565 def : Pat<(shl GR64:$src1, (and CL, immShift64)),
1566 (SHL64rCL GR64:$src1)>;
1567 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1568 (SHL64mCL addr:$dst)>;
1570 def : Pat<(srl GR64:$src1, (and CL, immShift64)),
1571 (SHR64rCL GR64:$src1)>;
1572 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1573 (SHR64mCL addr:$dst)>;
1575 def : Pat<(sra GR64:$src1, (and CL, immShift64)),
1576 (SAR64rCL GR64:$src1)>;
1577 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1578 (SAR64mCL addr:$dst)>;
1581 // (anyext (setcc_carry)) -> (setcc_carry)
1582 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1584 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1586 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1592 //===----------------------------------------------------------------------===//
1593 // EFLAGS-defining Patterns
1594 //===----------------------------------------------------------------------===//
1597 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1598 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1599 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1602 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1603 (ADD8rm GR8:$src1, addr:$src2)>;
1604 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1605 (ADD16rm GR16:$src1, addr:$src2)>;
1606 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1607 (ADD32rm GR32:$src1, addr:$src2)>;
1610 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1611 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1612 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1613 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1614 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1615 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1616 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1619 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1620 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1621 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1624 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1625 (SUB8rm GR8:$src1, addr:$src2)>;
1626 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1627 (SUB16rm GR16:$src1, addr:$src2)>;
1628 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1629 (SUB32rm GR32:$src1, addr:$src2)>;
1632 def : Pat<(sub GR8:$src1, imm:$src2),
1633 (SUB8ri GR8:$src1, imm:$src2)>;
1634 def : Pat<(sub GR16:$src1, imm:$src2),
1635 (SUB16ri GR16:$src1, imm:$src2)>;
1636 def : Pat<(sub GR32:$src1, imm:$src2),
1637 (SUB32ri GR32:$src1, imm:$src2)>;
1638 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1639 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1640 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1641 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1644 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1645 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1646 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1647 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1650 def : Pat<(mul GR16:$src1, GR16:$src2),
1651 (IMUL16rr GR16:$src1, GR16:$src2)>;
1652 def : Pat<(mul GR32:$src1, GR32:$src2),
1653 (IMUL32rr GR32:$src1, GR32:$src2)>;
1656 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1657 (IMUL16rm GR16:$src1, addr:$src2)>;
1658 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1659 (IMUL32rm GR32:$src1, addr:$src2)>;
1662 def : Pat<(mul GR16:$src1, imm:$src2),
1663 (IMUL16rri GR16:$src1, imm:$src2)>;
1664 def : Pat<(mul GR32:$src1, imm:$src2),
1665 (IMUL32rri GR32:$src1, imm:$src2)>;
1666 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1667 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1668 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1669 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1671 // reg = mul mem, imm
1672 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1673 (IMUL16rmi addr:$src1, imm:$src2)>;
1674 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1675 (IMUL32rmi addr:$src1, imm:$src2)>;
1676 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1677 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1678 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1679 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1681 // Patterns for nodes that do not produce flags, for instructions that do.
1684 def : Pat<(add GR64:$src1, GR64:$src2),
1685 (ADD64rr GR64:$src1, GR64:$src2)>;
1686 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1687 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1688 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1689 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1690 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1691 (ADD64rm GR64:$src1, addr:$src2)>;
1694 def : Pat<(sub GR64:$src1, GR64:$src2),
1695 (SUB64rr GR64:$src1, GR64:$src2)>;
1696 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1697 (SUB64rm GR64:$src1, addr:$src2)>;
1698 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1699 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1700 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1701 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1704 def : Pat<(mul GR64:$src1, GR64:$src2),
1705 (IMUL64rr GR64:$src1, GR64:$src2)>;
1706 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1707 (IMUL64rm GR64:$src1, addr:$src2)>;
1708 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1709 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1710 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1711 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1712 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1713 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1714 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1715 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1718 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1719 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1720 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1721 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1722 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1723 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1726 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1727 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1728 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1729 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1730 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1731 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1734 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1735 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1736 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1737 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1740 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1741 (OR8rm GR8:$src1, addr:$src2)>;
1742 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1743 (OR16rm GR16:$src1, addr:$src2)>;
1744 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1745 (OR32rm GR32:$src1, addr:$src2)>;
1746 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1747 (OR64rm GR64:$src1, addr:$src2)>;
1750 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1751 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1752 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1753 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1754 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1755 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1756 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1757 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1758 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1759 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1760 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1763 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1764 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1765 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1766 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1769 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1770 (XOR8rm GR8:$src1, addr:$src2)>;
1771 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1772 (XOR16rm GR16:$src1, addr:$src2)>;
1773 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1774 (XOR32rm GR32:$src1, addr:$src2)>;
1775 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1776 (XOR64rm GR64:$src1, addr:$src2)>;
1779 def : Pat<(xor GR8:$src1, imm:$src2),
1780 (XOR8ri GR8:$src1, imm:$src2)>;
1781 def : Pat<(xor GR16:$src1, imm:$src2),
1782 (XOR16ri GR16:$src1, imm:$src2)>;
1783 def : Pat<(xor GR32:$src1, imm:$src2),
1784 (XOR32ri GR32:$src1, imm:$src2)>;
1785 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1786 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1787 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1788 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1789 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1790 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1791 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1792 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1795 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1796 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1797 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1798 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1801 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1802 (AND8rm GR8:$src1, addr:$src2)>;
1803 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1804 (AND16rm GR16:$src1, addr:$src2)>;
1805 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1806 (AND32rm GR32:$src1, addr:$src2)>;
1807 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1808 (AND64rm GR64:$src1, addr:$src2)>;
1811 def : Pat<(and GR8:$src1, imm:$src2),
1812 (AND8ri GR8:$src1, imm:$src2)>;
1813 def : Pat<(and GR16:$src1, imm:$src2),
1814 (AND16ri GR16:$src1, imm:$src2)>;
1815 def : Pat<(and GR32:$src1, imm:$src2),
1816 (AND32ri GR32:$src1, imm:$src2)>;
1817 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1818 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1819 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1820 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1821 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1822 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1823 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1824 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1826 // Bit scan instruction patterns to match explicit zero-undef behavior.
1827 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1828 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1829 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1830 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1831 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1832 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;