1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 // PIC base construction. This expands to code that looks like this:
18 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
19 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
23 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
24 // a stack adjustment and the codegen must know that they may modify the stack
25 // pointer before prolog-epilog rewriting occurs.
26 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
27 // sub / add which can clobber EFLAGS.
28 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
29 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
31 [(X86callseq_start timm:$amt)]>,
32 Requires<[In32BitMode]>;
33 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
35 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
36 Requires<[In32BitMode]>;
39 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
40 // a stack adjustment and the codegen must know that they may modify the stack
41 // pointer before prolog-epilog rewriting occurs.
42 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
43 // sub / add which can clobber EFLAGS.
44 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
45 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
47 [(X86callseq_start timm:$amt)]>,
48 Requires<[In64BitMode]>;
49 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
51 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
52 Requires<[In64BitMode]>;
57 // x86-64 va_start lowering magic.
58 let usesCustomInserter = 1 in {
59 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
62 i64imm:$regsavefi, i64imm:$offset,
64 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
65 [(X86vastart_save_xmm_regs GR8:$al,
69 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
70 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
71 // one go. Touching the stack at 4K increments is necessary to ensure that the
72 // guard pages used by the OS virtual memory manager are allocated in correct
74 // The main point of having separate instruction are extra unmodelled effects
75 // (compared to ordinary calls) like stack pointer change.
77 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
78 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
79 "# dynamic stack allocation",
85 //===----------------------------------------------------------------------===//
86 // EH Pseudo Instructions
88 let isTerminator = 1, isReturn = 1, isBarrier = 1,
89 hasCtrlDep = 1, isCodeGenOnly = 1 in {
90 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
91 "ret\t#eh_return, addr: $addr",
92 [(X86ehret GR32:$addr)]>;
96 let isTerminator = 1, isReturn = 1, isBarrier = 1,
97 hasCtrlDep = 1, isCodeGenOnly = 1 in {
98 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
99 "ret\t#eh_return, addr: $addr",
100 [(X86ehret GR64:$addr)]>;
104 //===----------------------------------------------------------------------===//
105 // Alias Instructions
106 //===----------------------------------------------------------------------===//
108 // Alias instructions that map movr0 to xor.
109 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
110 // FIXME: Set encoding to pseudo.
111 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
112 isCodeGenOnly = 1 in {
113 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
114 [(set GR8:$dst, 0)]>;
116 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
117 // encoding and avoids a partial-register update sometimes, but doing so
118 // at isel time interferes with rematerialization in the current register
119 // allocator. For now, this is rewritten when the instruction is lowered
121 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
123 [(set GR16:$dst, 0)]>, OpSize;
125 // FIXME: Set encoding to pseudo.
126 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
127 [(set GR32:$dst, 0)]>;
130 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
131 // smaller encoding, but doing so at isel time interferes with rematerialization
132 // in the current register allocator. For now, this is rewritten when the
133 // instruction is lowered to an MCInst.
134 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
135 // when we have a better way to specify isel priority.
137 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
138 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
139 [(set GR64:$dst, 0)]>;
141 // Materialize i64 constant where top 32-bits are zero. This could theoretically
142 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
143 // that would make it more difficult to rematerialize.
144 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
145 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
146 "", [(set GR64:$dst, i64immZExt32:$src)]>;
149 // Use sbb to materialize carry flag into a GPR.
150 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
151 // However, Pat<> can't replicate the destination reg into the inputs of the
153 // FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
155 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
156 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
157 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
159 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
163 //===----------------------------------------------------------------------===//
164 // String Pseudo Instructions
166 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
167 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
168 [(X86rep_movs i8)]>, REP;
169 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
170 [(X86rep_movs i16)]>, REP, OpSize;
171 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
172 [(X86rep_movs i32)]>, REP;
175 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
176 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
177 [(X86rep_movs i64)]>, REP;
180 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
181 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
182 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
183 [(X86rep_stos i8)]>, REP;
184 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
185 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
186 [(X86rep_stos i16)]>, REP, OpSize;
187 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
188 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
189 [(X86rep_stos i32)]>, REP;
191 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
192 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
193 [(X86rep_stos i64)]>, REP;
196 //===----------------------------------------------------------------------===//
197 // Thread Local Storage Instructions
201 // All calls clobber the non-callee saved registers. ESP is marked as
202 // a use to prevent stack-pointer assignments that appear immediately
203 // before calls from potentially appearing dead.
204 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
205 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
206 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
207 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
209 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
211 "call\t___tls_get_addr@PLT",
212 [(X86tlsaddr tls32addr:$sym)]>,
213 Requires<[In32BitMode]>;
215 // All calls clobber the non-callee saved registers. RSP is marked as
216 // a use to prevent stack-pointer assignments that appear immediately
217 // before calls from potentially appearing dead.
218 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
219 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
220 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
221 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
222 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
224 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
226 "leaq\t$sym(%rip), %rdi; "
229 "call\t__tls_get_addr@PLT",
230 [(X86tlsaddr tls64addr:$sym)]>,
231 Requires<[In64BitMode]>;
233 // Darwin TLS Support
234 // For i386, the address of the thunk is passed on the stack, on return the
235 // address of the variable is in %eax. %ecx is trashed during the function
236 // call. All other registers are preserved.
237 let Defs = [EAX, ECX],
239 usesCustomInserter = 1 in
240 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
242 [(X86TLSCall addr:$sym)]>,
243 Requires<[In32BitMode]>;
245 // For x86_64, the address of the thunk is passed in %rdi, on return
246 // the address of the variable is in %rax. All other registers are preserved.
249 usesCustomInserter = 1 in
250 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
252 [(X86TLSCall addr:$sym)]>,
253 Requires<[In64BitMode]>;
255 //===----------------------------------------------------------------------===//
256 // Atomic Instruction Pseudo Instructions
257 //===----------------------------------------------------------------------===//
259 // Atomic exchange, and, or, xor
260 let Constraints = "$val = $dst", Defs = [EFLAGS],
261 usesCustomInserter = 1 in {
263 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
265 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
266 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
268 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
269 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
271 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
272 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
273 "#ATOMNAND8 PSEUDO!",
274 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
276 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
277 "#ATOMAND16 PSEUDO!",
278 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
279 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
281 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
282 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
283 "#ATOMXOR16 PSEUDO!",
284 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
285 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
286 "#ATOMNAND16 PSEUDO!",
287 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
288 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
289 "#ATOMMIN16 PSEUDO!",
290 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
291 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
292 "#ATOMMAX16 PSEUDO!",
293 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
294 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
295 "#ATOMUMIN16 PSEUDO!",
296 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
297 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
298 "#ATOMUMAX16 PSEUDO!",
299 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
302 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
303 "#ATOMAND32 PSEUDO!",
304 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
305 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
307 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
308 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
309 "#ATOMXOR32 PSEUDO!",
310 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
311 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
312 "#ATOMNAND32 PSEUDO!",
313 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
314 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
315 "#ATOMMIN32 PSEUDO!",
316 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
317 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
318 "#ATOMMAX32 PSEUDO!",
319 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
320 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
321 "#ATOMUMIN32 PSEUDO!",
322 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
323 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
324 "#ATOMUMAX32 PSEUDO!",
325 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
329 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
330 "#ATOMAND64 PSEUDO!",
331 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
332 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
334 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
335 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
336 "#ATOMXOR64 PSEUDO!",
337 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
338 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
339 "#ATOMNAND64 PSEUDO!",
340 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
341 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
342 "#ATOMMIN64 PSEUDO!",
343 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
344 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
345 "#ATOMMAX64 PSEUDO!",
346 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
347 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
348 "#ATOMUMIN64 PSEUDO!",
349 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
350 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
351 "#ATOMUMAX64 PSEUDO!",
352 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
355 let Constraints = "$val1 = $dst1, $val2 = $dst2",
356 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
357 Uses = [EAX, EBX, ECX, EDX],
358 mayLoad = 1, mayStore = 1,
359 usesCustomInserter = 1 in {
360 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
361 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
362 "#ATOMAND6432 PSEUDO!", []>;
363 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
364 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
365 "#ATOMOR6432 PSEUDO!", []>;
366 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
367 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
368 "#ATOMXOR6432 PSEUDO!", []>;
369 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
370 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
371 "#ATOMNAND6432 PSEUDO!", []>;
372 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
373 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
374 "#ATOMADD6432 PSEUDO!", []>;
375 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
376 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
377 "#ATOMSUB6432 PSEUDO!", []>;
378 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
379 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
380 "#ATOMSWAP6432 PSEUDO!", []>;
383 //===----------------------------------------------------------------------===//
384 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
385 //===----------------------------------------------------------------------===//
387 // FIXME: Use normal instructions and add lock prefix dynamically.
391 // TODO: Get this to fold the constant into the instruction.
392 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
394 "or{l}\t{$zero, $dst|$dst, $zero}",
395 []>, Requires<[In32BitMode]>, LOCK;
397 let hasSideEffects = 1 in
398 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
400 [(X86MemBarrier)]>, Requires<[HasSSE2]>;
402 // TODO: Get this to fold the constant into the instruction.
403 let hasSideEffects = 1, Defs = [ESP] in
404 def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
406 "or{q}\t{$zero, (%rsp)|(%rsp), $zero}",
407 [(X86MemBarrierNoSSE GR64:$zero)]>,
408 Requires<[In64BitMode]>, LOCK;
411 // Optimized codegen when the non-memory output is not used.
412 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
413 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
415 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
416 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
418 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
419 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
421 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
422 def LOCK_ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
424 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
426 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
428 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
429 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
431 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
432 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
434 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
435 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
436 (ins i64mem:$dst, i64i32imm :$src2),
438 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
440 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
442 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
443 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
445 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
446 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
447 (ins i64mem:$dst, i64i8imm :$src2),
449 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
451 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
453 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
454 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
456 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
457 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
459 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
460 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
462 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
465 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
467 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
468 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
470 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
471 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
473 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
474 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
475 (ins i64mem:$dst, i64i32imm:$src2),
477 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
480 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
482 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
483 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
485 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
486 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
487 (ins i64mem:$dst, i64i8imm :$src2),
489 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
491 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
493 "inc{b}\t$dst", []>, LOCK;
494 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
496 "inc{w}\t$dst", []>, OpSize, LOCK;
497 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
499 "inc{l}\t$dst", []>, LOCK;
500 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
502 "inc{q}\t$dst", []>, LOCK;
504 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
506 "dec{b}\t$dst", []>, LOCK;
507 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
509 "dec{w}\t$dst", []>, OpSize, LOCK;
510 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
512 "dec{l}\t$dst", []>, LOCK;
513 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
515 "dec{q}\t$dst", []>, LOCK;
518 // Atomic compare and swap.
519 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
520 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
523 [(X86cas8 addr:$ptr)]>, TB, LOCK;
525 let Defs = [AL, EFLAGS], Uses = [AL] in {
526 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
528 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
529 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
532 let Defs = [AX, EFLAGS], Uses = [AX] in {
533 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
535 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
536 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
539 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
540 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
542 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
543 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
546 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
547 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
549 "cmpxchgq\t$swap,$ptr",
550 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
553 // Atomic exchange and add
554 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
555 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
557 "xadd{b}\t{$val, $ptr|$ptr, $val}",
558 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
560 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
562 "xadd{w}\t{$val, $ptr|$ptr, $val}",
563 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
565 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
567 "xadd{l}\t{$val, $ptr|$ptr, $val}",
568 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
570 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
573 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
578 //===----------------------------------------------------------------------===//
579 // DAG Pattern Matching Rules
580 //===----------------------------------------------------------------------===//
582 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
583 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
584 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
585 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
586 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
587 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
588 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
590 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
591 (ADD32ri GR32:$src1, tconstpool:$src2)>;
592 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
593 (ADD32ri GR32:$src1, tjumptable:$src2)>;
594 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
595 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
596 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
597 (ADD32ri GR32:$src1, texternalsym:$src2)>;
598 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
599 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
601 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
602 (MOV32mi addr:$dst, tglobaladdr:$src)>;
603 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
604 (MOV32mi addr:$dst, texternalsym:$src)>;
605 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
606 (MOV32mi addr:$dst, tblockaddress:$src)>;
610 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
611 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
612 // 'movabs' predicate should handle this sort of thing.
613 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
614 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
615 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
616 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
617 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
618 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
619 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
620 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
621 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
622 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
624 // In static codegen with small code model, we can get the address of a label
625 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
626 // the MOV64ri64i32 should accept these.
627 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
628 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
629 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
630 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
631 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
632 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
633 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
634 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
635 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
636 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
638 // In kernel code model, we can get the address of a label
639 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
640 // the MOV64ri32 should accept these.
641 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
642 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
643 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
644 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
645 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
646 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
647 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
648 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
649 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
650 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
652 // If we have small model and -static mode, it is safe to store global addresses
653 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
654 // for MOV64mi32 should handle this sort of thing.
655 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
656 (MOV64mi32 addr:$dst, tconstpool:$src)>,
657 Requires<[NearData, IsStatic]>;
658 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
659 (MOV64mi32 addr:$dst, tjumptable:$src)>,
660 Requires<[NearData, IsStatic]>;
661 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
662 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
663 Requires<[NearData, IsStatic]>;
664 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
665 (MOV64mi32 addr:$dst, texternalsym:$src)>,
666 Requires<[NearData, IsStatic]>;
667 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
668 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
669 Requires<[NearData, IsStatic]>;
675 // tls has some funny stuff here...
676 // This corresponds to movabs $foo@tpoff, %rax
677 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
678 (MOV64ri tglobaltlsaddr :$dst)>;
679 // This corresponds to add $foo@tpoff, %rax
680 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
681 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
682 // This corresponds to mov foo@tpoff(%rbx), %eax
683 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
684 (MOV64rm tglobaltlsaddr :$dst)>;
687 // Direct PC relative function call for small code model. 32-bit displacement
688 // sign extended to 64-bit.
689 def : Pat<(X86call (i64 tglobaladdr:$dst)),
690 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
691 def : Pat<(X86call (i64 texternalsym:$dst)),
692 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
694 def : Pat<(X86call (i64 tglobaladdr:$dst)),
695 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
696 def : Pat<(X86call (i64 texternalsym:$dst)),
697 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
700 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
701 (TCRETURNri GR32_TC:$dst, imm:$off)>,
702 Requires<[In32BitMode]>;
704 // FIXME: This is disabled for 32-bit PIC mode because the global base
705 // register which is part of the address mode may be assigned a
706 // callee-saved register.
707 def : Pat<(X86tcret (load addr:$dst), imm:$off),
708 (TCRETURNmi addr:$dst, imm:$off)>,
709 Requires<[In32BitMode, IsNotPIC]>;
711 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
712 (TCRETURNdi texternalsym:$dst, imm:$off)>,
713 Requires<[In32BitMode]>;
715 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
716 (TCRETURNdi texternalsym:$dst, imm:$off)>,
717 Requires<[In32BitMode]>;
719 def : Pat<(X86tcret GR64_TC:$dst, imm:$off),
720 (TCRETURNri64 GR64_TC:$dst, imm:$off)>,
721 Requires<[In64BitMode]>;
723 def : Pat<(X86tcret (load addr:$dst), imm:$off),
724 (TCRETURNmi64 addr:$dst, imm:$off)>,
725 Requires<[In64BitMode]>;
727 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
728 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
729 Requires<[In64BitMode]>;
731 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
732 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
733 Requires<[In64BitMode]>;
735 // Normal calls, with various flavors of addresses.
736 def : Pat<(X86call (i32 tglobaladdr:$dst)),
737 (CALLpcrel32 tglobaladdr:$dst)>;
738 def : Pat<(X86call (i32 texternalsym:$dst)),
739 (CALLpcrel32 texternalsym:$dst)>;
740 def : Pat<(X86call (i32 imm:$dst)),
741 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
743 // X86 specific add which produces a flag.
744 def : Pat<(addc GR32:$src1, GR32:$src2),
745 (ADD32rr GR32:$src1, GR32:$src2)>;
746 def : Pat<(addc GR32:$src1, (load addr:$src2)),
747 (ADD32rm GR32:$src1, addr:$src2)>;
748 def : Pat<(addc GR32:$src1, imm:$src2),
749 (ADD32ri GR32:$src1, imm:$src2)>;
750 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
751 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
753 def : Pat<(addc GR64:$src1, GR64:$src2),
754 (ADD64rr GR64:$src1, GR64:$src2)>;
755 def : Pat<(addc GR64:$src1, (load addr:$src2)),
756 (ADD64rm GR64:$src1, addr:$src2)>;
757 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
758 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
759 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
760 (ADD64ri32 GR64:$src1, imm:$src2)>;
762 def : Pat<(subc GR32:$src1, GR32:$src2),
763 (SUB32rr GR32:$src1, GR32:$src2)>;
764 def : Pat<(subc GR32:$src1, (load addr:$src2)),
765 (SUB32rm GR32:$src1, addr:$src2)>;
766 def : Pat<(subc GR32:$src1, imm:$src2),
767 (SUB32ri GR32:$src1, imm:$src2)>;
768 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
769 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
771 def : Pat<(subc GR64:$src1, GR64:$src2),
772 (SUB64rr GR64:$src1, GR64:$src2)>;
773 def : Pat<(subc GR64:$src1, (load addr:$src2)),
774 (SUB64rm GR64:$src1, addr:$src2)>;
775 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
776 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
777 def : Pat<(subc GR64:$src1, imm:$src2),
778 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
782 // TEST R,R is smaller than CMP R,0
783 def : Pat<(X86cmp GR8:$src1, 0),
784 (TEST8rr GR8:$src1, GR8:$src1)>;
785 def : Pat<(X86cmp GR16:$src1, 0),
786 (TEST16rr GR16:$src1, GR16:$src1)>;
787 def : Pat<(X86cmp GR32:$src1, 0),
788 (TEST32rr GR32:$src1, GR32:$src1)>;
789 def : Pat<(X86cmp GR64:$src1, 0),
790 (TEST64rr GR64:$src1, GR64:$src1)>;
792 // Conditional moves with folded loads with operands swapped and conditions
794 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
795 (CMOVAE16rm GR16:$src2, addr:$src1)>;
796 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
797 (CMOVAE32rm GR32:$src2, addr:$src1)>;
798 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
799 (CMOVB16rm GR16:$src2, addr:$src1)>;
800 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
801 (CMOVB32rm GR32:$src2, addr:$src1)>;
802 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
803 (CMOVNE16rm GR16:$src2, addr:$src1)>;
804 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
805 (CMOVNE32rm GR32:$src2, addr:$src1)>;
806 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
807 (CMOVE16rm GR16:$src2, addr:$src1)>;
808 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
809 (CMOVE32rm GR32:$src2, addr:$src1)>;
810 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
811 (CMOVA16rm GR16:$src2, addr:$src1)>;
812 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
813 (CMOVA32rm GR32:$src2, addr:$src1)>;
814 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
815 (CMOVBE16rm GR16:$src2, addr:$src1)>;
816 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
817 (CMOVBE32rm GR32:$src2, addr:$src1)>;
818 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
819 (CMOVGE16rm GR16:$src2, addr:$src1)>;
820 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
821 (CMOVGE32rm GR32:$src2, addr:$src1)>;
822 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
823 (CMOVL16rm GR16:$src2, addr:$src1)>;
824 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
825 (CMOVL32rm GR32:$src2, addr:$src1)>;
826 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
827 (CMOVG16rm GR16:$src2, addr:$src1)>;
828 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
829 (CMOVG32rm GR32:$src2, addr:$src1)>;
830 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
831 (CMOVLE16rm GR16:$src2, addr:$src1)>;
832 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
833 (CMOVLE32rm GR32:$src2, addr:$src1)>;
834 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
835 (CMOVNP16rm GR16:$src2, addr:$src1)>;
836 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
837 (CMOVNP32rm GR32:$src2, addr:$src1)>;
838 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
839 (CMOVP16rm GR16:$src2, addr:$src1)>;
840 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
841 (CMOVP32rm GR32:$src2, addr:$src1)>;
842 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
843 (CMOVNS16rm GR16:$src2, addr:$src1)>;
844 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
845 (CMOVNS32rm GR32:$src2, addr:$src1)>;
846 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
847 (CMOVS16rm GR16:$src2, addr:$src1)>;
848 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
849 (CMOVS32rm GR32:$src2, addr:$src1)>;
850 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
851 (CMOVNO16rm GR16:$src2, addr:$src1)>;
852 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
853 (CMOVNO32rm GR32:$src2, addr:$src1)>;
854 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
855 (CMOVO16rm GR16:$src2, addr:$src1)>;
856 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
857 (CMOVO32rm GR32:$src2, addr:$src1)>;
859 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
860 (CMOVAE64rm GR64:$src2, addr:$src1)>;
861 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
862 (CMOVB64rm GR64:$src2, addr:$src1)>;
863 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
864 (CMOVNE64rm GR64:$src2, addr:$src1)>;
865 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
866 (CMOVE64rm GR64:$src2, addr:$src1)>;
867 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
868 (CMOVA64rm GR64:$src2, addr:$src1)>;
869 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
870 (CMOVBE64rm GR64:$src2, addr:$src1)>;
871 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
872 (CMOVGE64rm GR64:$src2, addr:$src1)>;
873 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
874 (CMOVL64rm GR64:$src2, addr:$src1)>;
875 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
876 (CMOVG64rm GR64:$src2, addr:$src1)>;
877 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
878 (CMOVLE64rm GR64:$src2, addr:$src1)>;
879 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
880 (CMOVNP64rm GR64:$src2, addr:$src1)>;
881 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
882 (CMOVP64rm GR64:$src2, addr:$src1)>;
883 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
884 (CMOVNS64rm GR64:$src2, addr:$src1)>;
885 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
886 (CMOVS64rm GR64:$src2, addr:$src1)>;
887 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
888 (CMOVNO64rm GR64:$src2, addr:$src1)>;
889 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
890 (CMOVO64rm GR64:$src2, addr:$src1)>;
893 // zextload bool -> zextload byte
894 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
895 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
896 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
897 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
899 // extload bool -> extload byte
900 // When extloading from 16-bit and smaller memory locations into 64-bit
901 // registers, use zero-extending loads so that the entire 64-bit register is
902 // defined, avoiding partial-register updates.
904 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
905 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
906 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
907 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
908 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
909 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
911 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
912 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
913 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
914 // For other extloads, use subregs, since the high contents of the register are
915 // defined after an extload.
916 def : Pat<(extloadi64i32 addr:$src),
917 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
920 // anyext. Define these to do an explicit zero-extend to
921 // avoid partial-register updates.
922 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
923 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
925 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
926 def : Pat<(i32 (anyext GR16:$src)),
927 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
929 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
930 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
931 def : Pat<(i64 (anyext GR32:$src)),
932 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
934 //===----------------------------------------------------------------------===//
936 //===----------------------------------------------------------------------===//
938 // Odd encoding trick: -128 fits into an 8-bit immediate field while
939 // +128 doesn't, so in this special case use a sub instead of an add.
940 def : Pat<(add GR16:$src1, 128),
941 (SUB16ri8 GR16:$src1, -128)>;
942 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
943 (SUB16mi8 addr:$dst, -128)>;
945 def : Pat<(add GR32:$src1, 128),
946 (SUB32ri8 GR32:$src1, -128)>;
947 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
948 (SUB32mi8 addr:$dst, -128)>;
950 def : Pat<(add GR64:$src1, 128),
951 (SUB64ri8 GR64:$src1, -128)>;
952 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
953 (SUB64mi8 addr:$dst, -128)>;
955 // The same trick applies for 32-bit immediate fields in 64-bit
957 def : Pat<(add GR64:$src1, 0x0000000080000000),
958 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
959 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
960 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
962 // Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
963 // has an immediate with at least 32 bits of leading zeros, to avoid needing to
964 // materialize that immediate in a register first.
965 def : Pat<(and GR64:$src, i64immZExt32:$imm),
969 (EXTRACT_SUBREG GR64:$src, sub_32bit),
970 (i32 (GetLo32XForm imm:$imm))),
974 // r & (2^16-1) ==> movz
975 def : Pat<(and GR32:$src1, 0xffff),
976 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
977 // r & (2^8-1) ==> movz
978 def : Pat<(and GR32:$src1, 0xff),
979 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
982 Requires<[In32BitMode]>;
983 // r & (2^8-1) ==> movz
984 def : Pat<(and GR16:$src1, 0xff),
985 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
988 Requires<[In32BitMode]>;
990 // r & (2^32-1) ==> movz
991 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
992 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
993 // r & (2^16-1) ==> movz
994 def : Pat<(and GR64:$src, 0xffff),
995 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
996 // r & (2^8-1) ==> movz
997 def : Pat<(and GR64:$src, 0xff),
998 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
999 // r & (2^8-1) ==> movz
1000 def : Pat<(and GR32:$src1, 0xff),
1001 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1002 Requires<[In64BitMode]>;
1003 // r & (2^8-1) ==> movz
1004 def : Pat<(and GR16:$src1, 0xff),
1005 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>,
1006 Requires<[In64BitMode]>;
1009 // sext_inreg patterns
1010 def : Pat<(sext_inreg GR32:$src, i16),
1011 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1012 def : Pat<(sext_inreg GR32:$src, i8),
1013 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1016 Requires<[In32BitMode]>;
1017 def : Pat<(sext_inreg GR16:$src, i8),
1018 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1021 Requires<[In32BitMode]>;
1023 def : Pat<(sext_inreg GR64:$src, i32),
1024 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1025 def : Pat<(sext_inreg GR64:$src, i16),
1026 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1027 def : Pat<(sext_inreg GR64:$src, i8),
1028 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1029 def : Pat<(sext_inreg GR32:$src, i8),
1030 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1031 Requires<[In64BitMode]>;
1032 def : Pat<(sext_inreg GR16:$src, i8),
1033 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>,
1034 Requires<[In64BitMode]>;
1038 def : Pat<(i16 (trunc GR32:$src)),
1039 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1040 def : Pat<(i8 (trunc GR32:$src)),
1041 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1043 Requires<[In32BitMode]>;
1044 def : Pat<(i8 (trunc GR16:$src)),
1045 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1047 Requires<[In32BitMode]>;
1048 def : Pat<(i32 (trunc GR64:$src)),
1049 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1050 def : Pat<(i16 (trunc GR64:$src)),
1051 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1052 def : Pat<(i8 (trunc GR64:$src)),
1053 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1054 def : Pat<(i8 (trunc GR32:$src)),
1055 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1056 Requires<[In64BitMode]>;
1057 def : Pat<(i8 (trunc GR16:$src)),
1058 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1059 Requires<[In64BitMode]>;
1061 // h-register tricks
1062 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1063 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1065 Requires<[In32BitMode]>;
1066 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1067 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1069 Requires<[In32BitMode]>;
1070 def : Pat<(srl GR16:$src, (i8 8)),
1073 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1076 Requires<[In32BitMode]>;
1077 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1078 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1081 Requires<[In32BitMode]>;
1082 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1083 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1086 Requires<[In32BitMode]>;
1087 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1088 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1091 Requires<[In32BitMode]>;
1092 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1093 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1096 Requires<[In32BitMode]>;
1098 // h-register tricks.
1099 // For now, be conservative on x86-64 and use an h-register extract only if the
1100 // value is immediately zero-extended or stored, which are somewhat common
1101 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1102 // from being allocated in the same instruction as the h register, as there's
1103 // currently no way to describe this requirement to the register allocator.
1105 // h-register extract and zero-extend.
1106 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1110 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1113 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1115 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1117 Requires<[In64BitMode]>;
1118 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1119 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1122 Requires<[In64BitMode]>;
1123 def : Pat<(srl GR16:$src, (i8 8)),
1126 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1129 Requires<[In64BitMode]>;
1130 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1132 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1134 Requires<[In64BitMode]>;
1135 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1137 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1139 Requires<[In64BitMode]>;
1140 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1144 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1147 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1151 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1155 // h-register extract and store.
1156 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1159 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1161 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1164 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1166 Requires<[In64BitMode]>;
1167 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1170 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1172 Requires<[In64BitMode]>;
1175 // (shl x, 1) ==> (add x, x)
1176 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1177 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1178 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1179 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1181 // (shl x (and y, 31)) ==> (shl x, y)
1182 def : Pat<(shl GR8:$src1, (and CL, 31)),
1183 (SHL8rCL GR8:$src1)>;
1184 def : Pat<(shl GR16:$src1, (and CL, 31)),
1185 (SHL16rCL GR16:$src1)>;
1186 def : Pat<(shl GR32:$src1, (and CL, 31)),
1187 (SHL32rCL GR32:$src1)>;
1188 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1189 (SHL8mCL addr:$dst)>;
1190 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1191 (SHL16mCL addr:$dst)>;
1192 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1193 (SHL32mCL addr:$dst)>;
1195 def : Pat<(srl GR8:$src1, (and CL, 31)),
1196 (SHR8rCL GR8:$src1)>;
1197 def : Pat<(srl GR16:$src1, (and CL, 31)),
1198 (SHR16rCL GR16:$src1)>;
1199 def : Pat<(srl GR32:$src1, (and CL, 31)),
1200 (SHR32rCL GR32:$src1)>;
1201 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1202 (SHR8mCL addr:$dst)>;
1203 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1204 (SHR16mCL addr:$dst)>;
1205 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1206 (SHR32mCL addr:$dst)>;
1208 def : Pat<(sra GR8:$src1, (and CL, 31)),
1209 (SAR8rCL GR8:$src1)>;
1210 def : Pat<(sra GR16:$src1, (and CL, 31)),
1211 (SAR16rCL GR16:$src1)>;
1212 def : Pat<(sra GR32:$src1, (and CL, 31)),
1213 (SAR32rCL GR32:$src1)>;
1214 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1215 (SAR8mCL addr:$dst)>;
1216 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1217 (SAR16mCL addr:$dst)>;
1218 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1219 (SAR32mCL addr:$dst)>;
1221 // (shl x (and y, 63)) ==> (shl x, y)
1222 def : Pat<(shl GR64:$src1, (and CL, 63)),
1223 (SHL64rCL GR64:$src1)>;
1224 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1225 (SHL64mCL addr:$dst)>;
1227 def : Pat<(srl GR64:$src1, (and CL, 63)),
1228 (SHR64rCL GR64:$src1)>;
1229 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1230 (SHR64mCL addr:$dst)>;
1232 def : Pat<(sra GR64:$src1, (and CL, 63)),
1233 (SAR64rCL GR64:$src1)>;
1234 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1235 (SAR64mCL addr:$dst)>;
1238 // (anyext (setcc_carry)) -> (setcc_carry)
1239 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1241 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1243 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1246 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1247 let AddedComplexity = 5 in { // Try this before the selecting to OR
1248 def : Pat<(or_is_add GR16:$src1, imm:$src2),
1249 (ADD16ri GR16:$src1, imm:$src2)>;
1250 def : Pat<(or_is_add GR32:$src1, imm:$src2),
1251 (ADD32ri GR32:$src1, imm:$src2)>;
1252 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
1253 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1254 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
1255 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1256 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
1257 (ADD16rr GR16:$src1, GR16:$src2)>;
1258 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
1259 (ADD32rr GR32:$src1, GR32:$src2)>;
1260 def : Pat<(or_is_add GR64:$src1, i64immSExt8:$src2),
1261 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1262 def : Pat<(or_is_add GR64:$src1, i64immSExt32:$src2),
1263 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1264 def : Pat<(or_is_add GR64:$src1, GR64:$src2),
1265 (ADD64rr GR64:$src1, GR64:$src2)>;
1266 } // AddedComplexity
1268 //===----------------------------------------------------------------------===//
1269 // EFLAGS-defining Patterns
1270 //===----------------------------------------------------------------------===//
1273 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1274 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1275 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1278 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1279 (ADD8rm GR8:$src1, addr:$src2)>;
1280 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1281 (ADD16rm GR16:$src1, addr:$src2)>;
1282 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1283 (ADD32rm GR32:$src1, addr:$src2)>;
1286 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1287 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1288 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1289 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1290 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1291 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1292 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1295 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1296 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1297 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1300 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1301 (SUB8rm GR8:$src1, addr:$src2)>;
1302 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1303 (SUB16rm GR16:$src1, addr:$src2)>;
1304 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1305 (SUB32rm GR32:$src1, addr:$src2)>;
1308 def : Pat<(sub GR8:$src1, imm:$src2),
1309 (SUB8ri GR8:$src1, imm:$src2)>;
1310 def : Pat<(sub GR16:$src1, imm:$src2),
1311 (SUB16ri GR16:$src1, imm:$src2)>;
1312 def : Pat<(sub GR32:$src1, imm:$src2),
1313 (SUB32ri GR32:$src1, imm:$src2)>;
1314 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1315 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1316 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1317 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1320 def : Pat<(mul GR16:$src1, GR16:$src2),
1321 (IMUL16rr GR16:$src1, GR16:$src2)>;
1322 def : Pat<(mul GR32:$src1, GR32:$src2),
1323 (IMUL32rr GR32:$src1, GR32:$src2)>;
1326 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1327 (IMUL16rm GR16:$src1, addr:$src2)>;
1328 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1329 (IMUL32rm GR32:$src1, addr:$src2)>;
1332 def : Pat<(mul GR16:$src1, imm:$src2),
1333 (IMUL16rri GR16:$src1, imm:$src2)>;
1334 def : Pat<(mul GR32:$src1, imm:$src2),
1335 (IMUL32rri GR32:$src1, imm:$src2)>;
1336 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1337 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1338 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1339 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1341 // reg = mul mem, imm
1342 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1343 (IMUL16rmi addr:$src1, imm:$src2)>;
1344 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1345 (IMUL32rmi addr:$src1, imm:$src2)>;
1346 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1347 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1348 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1349 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1351 // Optimize multiply by 2 with EFLAGS result.
1352 let AddedComplexity = 2 in {
1353 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
1354 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
1357 // Patterns for nodes that do not produce flags, for instructions that do.
1360 def : Pat<(add GR64:$src1, GR64:$src2),
1361 (ADD64rr GR64:$src1, GR64:$src2)>;
1362 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1363 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1364 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1365 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1366 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1367 (ADD64rm GR64:$src1, addr:$src2)>;
1370 def : Pat<(sub GR64:$src1, GR64:$src2),
1371 (SUB64rr GR64:$src1, GR64:$src2)>;
1372 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1373 (SUB64rm GR64:$src1, addr:$src2)>;
1374 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1375 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1376 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1377 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1380 def : Pat<(mul GR64:$src1, GR64:$src2),
1381 (IMUL64rr GR64:$src1, GR64:$src2)>;
1382 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1383 (IMUL64rm GR64:$src1, addr:$src2)>;
1384 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1385 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1386 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1387 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1388 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1389 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1390 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1391 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1394 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1395 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1396 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1397 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1398 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1399 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1402 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1403 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1404 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1405 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1406 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1407 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1410 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1411 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1412 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1413 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1416 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1417 (OR8rm GR8:$src1, addr:$src2)>;
1418 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1419 (OR16rm GR16:$src1, addr:$src2)>;
1420 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1421 (OR32rm GR32:$src1, addr:$src2)>;
1422 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1423 (OR64rm GR64:$src1, addr:$src2)>;
1426 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1427 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1428 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1429 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1430 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1431 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1432 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1433 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1434 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1435 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1436 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1439 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1440 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1441 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1442 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1445 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1446 (XOR8rm GR8:$src1, addr:$src2)>;
1447 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1448 (XOR16rm GR16:$src1, addr:$src2)>;
1449 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1450 (XOR32rm GR32:$src1, addr:$src2)>;
1451 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1452 (XOR64rm GR64:$src1, addr:$src2)>;
1455 def : Pat<(xor GR8:$src1, imm:$src2),
1456 (XOR8ri GR8:$src1, imm:$src2)>;
1457 def : Pat<(xor GR16:$src1, imm:$src2),
1458 (XOR16ri GR16:$src1, imm:$src2)>;
1459 def : Pat<(xor GR32:$src1, imm:$src2),
1460 (XOR32ri GR32:$src1, imm:$src2)>;
1461 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1462 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1463 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1464 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1465 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1466 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1467 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1468 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1471 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1472 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1473 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1474 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1477 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1478 (AND8rm GR8:$src1, addr:$src2)>;
1479 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1480 (AND16rm GR16:$src1, addr:$src2)>;
1481 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1482 (AND32rm GR32:$src1, addr:$src2)>;
1483 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1484 (AND64rm GR64:$src1, addr:$src2)>;
1487 def : Pat<(and GR8:$src1, imm:$src2),
1488 (AND8ri GR8:$src1, imm:$src2)>;
1489 def : Pat<(and GR16:$src1, imm:$src2),
1490 (AND16ri GR16:$src1, imm:$src2)>;
1491 def : Pat<(and GR32:$src1, imm:$src2),
1492 (AND32ri GR32:$src1, imm:$src2)>;
1493 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1494 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1495 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1496 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1497 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1498 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1499 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1500 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;