1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
55 def : Pat<(X86callseq_start timm:$amt1),
56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
59 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
60 // a stack adjustment and the codegen must know that they may modify the stack
61 // pointer before prolog-epilog rewriting occurs.
62 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
63 // sub / add which can clobber EFLAGS.
64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
71 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
74 def : Pat<(X86callseq_start timm:$amt1),
75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
78 // x86-64 va_start lowering magic.
79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
83 i64imm:$regsavefi, i64imm:$offset,
85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
86 [(X86vastart_save_xmm_regs GR8:$al,
91 // The VAARG_64 pseudo-instruction takes the address of the va_list,
92 // and places the address of the next argument into a register.
93 let Defs = [EFLAGS] in
94 def VAARG_64 : I<0, Pseudo,
96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
97 "#VAARG_64 $dst, $ap, $size, $mode, $align",
99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
102 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
103 // targets. These calls are needed to probe the stack when allocating more than
104 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
105 // ensure that the guard pages used by the OS virtual memory manager are
106 // allocated in correct sequence.
107 // The main point of having separate instruction are extra unmodelled effects
108 // (compared to ordinary calls) like stack pointer change.
110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
112 "# dynamic stack allocation",
115 // When using segmented stacks these are lowered into instructions which first
116 // check if the current stacklet has enough free memory. If it does, memory is
117 // allocated by bumping the stack pointer. Otherwise memory is allocated from
120 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
121 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
122 "# variable sized alloca for segmented stacks",
124 (X86SegAlloca GR32:$size))]>,
127 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
128 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
129 "# variable sized alloca for segmented stacks",
131 (X86SegAlloca GR64:$size))]>,
132 Requires<[In64BitMode]>;
135 //===----------------------------------------------------------------------===//
136 // EH Pseudo Instructions
138 let SchedRW = [WriteSystem] in {
139 let isTerminator = 1, isReturn = 1, isBarrier = 1,
140 hasCtrlDep = 1, isCodeGenOnly = 1 in {
141 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
142 "ret\t#eh_return, addr: $addr",
143 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
147 let isTerminator = 1, isReturn = 1, isBarrier = 1,
148 hasCtrlDep = 1, isCodeGenOnly = 1 in {
149 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
150 "ret\t#eh_return, addr: $addr",
151 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
155 let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
156 isCodeGenOnly = 1, isReturn = 1 in {
157 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>;
159 // CATCHRET needs a custom inserter for SEH.
160 let usesCustomInserter = 1 in
161 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from),
163 [(catchret bb:$dst, bb:$from)]>;
166 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1,
167 usesCustomInserter = 1 in
168 def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>;
170 // This instruction is responsible for re-establishing stack pointers after an
171 // exception has been caught and we are rejoining normal control flow in the
172 // parent function or funclet. It generally sets ESP and EBP, and optionally
173 // ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us
175 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in
176 def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>;
178 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
179 usesCustomInserter = 1 in {
180 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
182 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
183 Requires<[Not64BitMode]>;
184 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
186 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
187 Requires<[In64BitMode]>;
188 let isTerminator = 1 in {
189 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
190 "#EH_SJLJ_LONGJMP32",
191 [(X86eh_sjlj_longjmp addr:$buf)]>,
192 Requires<[Not64BitMode]>;
193 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
194 "#EH_SJLJ_LONGJMP64",
195 [(X86eh_sjlj_longjmp addr:$buf)]>,
196 Requires<[In64BitMode]>;
201 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
202 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
203 "#EH_SjLj_Setup\t$dst", []>;
206 //===----------------------------------------------------------------------===//
207 // Pseudo instructions used by unwind info.
209 let isPseudo = 1 in {
210 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
211 "#SEH_PushReg $reg", []>;
212 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
213 "#SEH_SaveReg $reg, $dst", []>;
214 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
215 "#SEH_SaveXMM $reg, $dst", []>;
216 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
217 "#SEH_StackAlloc $size", []>;
218 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
219 "#SEH_SetFrame $reg, $offset", []>;
220 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
221 "#SEH_PushFrame $mode", []>;
222 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
223 "#SEH_EndPrologue", []>;
224 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
225 "#SEH_Epilogue", []>;
228 //===----------------------------------------------------------------------===//
229 // Pseudo instructions used by segmented stacks.
232 // This is lowered into a RET instruction by MCInstLower. We need
233 // this so that we don't have to have a MachineBasicBlock which ends
234 // with a RET and also has successors.
235 let isPseudo = 1 in {
236 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
239 // This instruction is lowered to a RET followed by a MOV. The two
240 // instructions are not generated on a higher level since then the
241 // verifier sees a MachineBasicBlock ending with a non-terminator.
242 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
246 //===----------------------------------------------------------------------===//
247 // Alias Instructions
248 //===----------------------------------------------------------------------===//
250 // Alias instruction mapping movr0 to xor.
251 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
252 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
254 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
255 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
257 // Other widths can also make use of the 32-bit xor, which may have a smaller
258 // encoding and avoid partial register updates.
259 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
260 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
261 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
262 let AddedComplexity = 20;
265 // Materialize i64 constant where top 32-bits are zero. This could theoretically
266 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
267 // that would make it more difficult to rematerialize.
268 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
269 isCodeGenOnly = 1, hasSideEffects = 0 in
270 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
271 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
273 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
274 // actually the zero-extension of a 32-bit constant and for labels in the
275 // x86-64 small code model.
276 def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>;
278 let AddedComplexity = 1 in
279 def : Pat<(i64 mov64imm32:$src),
280 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
282 // Use sbb to materialize carry bit.
283 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
284 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
285 // However, Pat<> can't replicate the destination reg into the inputs of the
287 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
288 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
289 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
290 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
291 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
292 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
293 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
294 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
298 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
300 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
302 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
305 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
307 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
309 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
312 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
313 // will be eliminated and that the sbb can be extended up to a wider type. When
314 // this happens, it is great. However, if we are left with an 8-bit sbb and an
315 // and, we might as well just match it as a setb.
316 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
319 // (add OP, SETB) -> (adc OP, 0)
320 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
321 (ADC8ri GR8:$op, 0)>;
322 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
323 (ADC32ri8 GR32:$op, 0)>;
324 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
325 (ADC64ri8 GR64:$op, 0)>;
327 // (sub OP, SETB) -> (sbb OP, 0)
328 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
329 (SBB8ri GR8:$op, 0)>;
330 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
331 (SBB32ri8 GR32:$op, 0)>;
332 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
333 (SBB64ri8 GR64:$op, 0)>;
335 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
336 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
337 (ADC8ri GR8:$op, 0)>;
338 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
339 (ADC32ri8 GR32:$op, 0)>;
340 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
341 (ADC64ri8 GR64:$op, 0)>;
343 //===----------------------------------------------------------------------===//
344 // String Pseudo Instructions
346 let SchedRW = [WriteMicrocoded] in {
347 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
348 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
349 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
350 Requires<[Not64BitMode]>;
351 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
352 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
353 Requires<[Not64BitMode]>;
354 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
355 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
356 Requires<[Not64BitMode]>;
359 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
360 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
361 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
362 Requires<[In64BitMode]>;
363 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
364 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
365 Requires<[In64BitMode]>;
366 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
367 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
368 Requires<[In64BitMode]>;
369 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
370 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
371 Requires<[In64BitMode]>;
374 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
375 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
376 let Uses = [AL,ECX,EDI] in
377 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
378 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
379 Requires<[Not64BitMode]>;
380 let Uses = [AX,ECX,EDI] in
381 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
382 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
383 Requires<[Not64BitMode]>;
384 let Uses = [EAX,ECX,EDI] in
385 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
386 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
387 Requires<[Not64BitMode]>;
390 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
391 let Uses = [AL,RCX,RDI] in
392 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
393 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
394 Requires<[In64BitMode]>;
395 let Uses = [AX,RCX,RDI] in
396 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
397 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
398 Requires<[In64BitMode]>;
399 let Uses = [RAX,RCX,RDI] in
400 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
401 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
402 Requires<[In64BitMode]>;
404 let Uses = [RAX,RCX,RDI] in
405 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
406 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
407 Requires<[In64BitMode]>;
411 //===----------------------------------------------------------------------===//
412 // Thread Local Storage Instructions
416 // All calls clobber the non-callee saved registers. ESP is marked as
417 // a use to prevent stack-pointer assignments that appear immediately
418 // before calls from potentially appearing dead.
419 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
420 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
421 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
422 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
423 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
425 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
427 [(X86tlsaddr tls32addr:$sym)]>,
428 Requires<[Not64BitMode]>;
429 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
431 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
432 Requires<[Not64BitMode]>;
435 // All calls clobber the non-callee saved registers. RSP is marked as
436 // a use to prevent stack-pointer assignments that appear immediately
437 // before calls from potentially appearing dead.
438 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
439 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
440 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
441 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
442 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
443 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
445 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
447 [(X86tlsaddr tls64addr:$sym)]>,
448 Requires<[In64BitMode]>;
449 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
451 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
452 Requires<[In64BitMode]>;
455 // Darwin TLS Support
456 // For i386, the address of the thunk is passed on the stack, on return the
457 // address of the variable is in %eax. %ecx is trashed during the function
458 // call. All other registers are preserved.
459 let Defs = [EAX, ECX, EFLAGS],
461 usesCustomInserter = 1 in
462 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
464 [(X86TLSCall addr:$sym)]>,
465 Requires<[Not64BitMode]>;
467 // For x86_64, the address of the thunk is passed in %rdi, on return
468 // the address of the variable is in %rax. All other registers are preserved.
469 let Defs = [RAX, EFLAGS],
471 usesCustomInserter = 1 in
472 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
474 [(X86TLSCall addr:$sym)]>,
475 Requires<[In64BitMode]>;
478 //===----------------------------------------------------------------------===//
479 // Conditional Move Pseudo Instructions
481 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
482 // instruction selection into a branch sequence.
483 multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
484 def CMOV#NAME : I<0, Pseudo,
485 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
486 "#CMOV_"#NAME#" PSEUDO!",
487 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond,
491 let usesCustomInserter = 1, Uses = [EFLAGS] in {
492 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
493 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
494 // however that requires promoting the operands, and can induce additional
495 // i8 register pressure.
496 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
498 let Predicates = [NoCMov] in {
499 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
500 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
501 } // Predicates = [NoCMov]
503 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
505 let Predicates = [FPStackf32] in
506 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
508 let Predicates = [FPStackf64] in
509 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
511 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
513 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;
514 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;
515 defm _FR128 : CMOVrr_PSEUDO<FR128, f128>;
516 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>;
517 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>;
518 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>;
519 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>;
520 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
521 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>;
522 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
523 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
524 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
525 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
526 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
527 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
528 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
529 } // usesCustomInserter = 1, Uses = [EFLAGS]
531 //===----------------------------------------------------------------------===//
532 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
533 //===----------------------------------------------------------------------===//
535 // FIXME: Use normal instructions and add lock prefix dynamically.
539 // TODO: Get this to fold the constant into the instruction.
540 let isCodeGenOnly = 1, Defs = [EFLAGS] in
541 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
542 "or{l}\t{$zero, $dst|$dst, $zero}",
543 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
544 Sched<[WriteALULd, WriteRMW]>;
546 let hasSideEffects = 1 in
547 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
549 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
551 // RegOpc corresponds to the mr version of the instruction
552 // ImmOpc corresponds to the mi version of the instruction
553 // ImmOpc8 corresponds to the mi8 version of the instruction
554 // ImmMod corresponds to the instruction format of the mi and mi8 versions
555 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
556 Format ImmMod, string mnemonic> {
557 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
558 SchedRW = [WriteALULd, WriteRMW] in {
560 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
561 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
562 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
563 !strconcat(mnemonic, "{b}\t",
564 "{$src2, $dst|$dst, $src2}"),
565 [], IIC_ALU_NONMEM>, LOCK;
566 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
567 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
568 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
569 !strconcat(mnemonic, "{w}\t",
570 "{$src2, $dst|$dst, $src2}"),
571 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
572 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
573 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
574 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
575 !strconcat(mnemonic, "{l}\t",
576 "{$src2, $dst|$dst, $src2}"),
577 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
578 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
579 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
580 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
581 !strconcat(mnemonic, "{q}\t",
582 "{$src2, $dst|$dst, $src2}"),
583 [], IIC_ALU_NONMEM>, LOCK;
585 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
586 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
587 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
588 !strconcat(mnemonic, "{b}\t",
589 "{$src2, $dst|$dst, $src2}"),
590 [], IIC_ALU_MEM>, LOCK;
592 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
593 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
594 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
595 !strconcat(mnemonic, "{w}\t",
596 "{$src2, $dst|$dst, $src2}"),
597 [], IIC_ALU_MEM>, OpSize16, LOCK;
599 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
600 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
601 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
602 !strconcat(mnemonic, "{l}\t",
603 "{$src2, $dst|$dst, $src2}"),
604 [], IIC_ALU_MEM>, OpSize32, LOCK;
606 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
607 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
608 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
609 !strconcat(mnemonic, "{q}\t",
610 "{$src2, $dst|$dst, $src2}"),
611 [], IIC_ALU_MEM>, LOCK;
613 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
614 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
615 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
616 !strconcat(mnemonic, "{w}\t",
617 "{$src2, $dst|$dst, $src2}"),
618 [], IIC_ALU_MEM>, OpSize16, LOCK;
619 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
620 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
621 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
622 !strconcat(mnemonic, "{l}\t",
623 "{$src2, $dst|$dst, $src2}"),
624 [], IIC_ALU_MEM>, OpSize32, LOCK;
625 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
626 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
627 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
628 !strconcat(mnemonic, "{q}\t",
629 "{$src2, $dst|$dst, $src2}"),
630 [], IIC_ALU_MEM>, LOCK;
636 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
637 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
638 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
639 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
640 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
642 // Optimized codegen when the non-memory output is not used.
643 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
645 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
646 SchedRW = [WriteALULd, WriteRMW] in {
648 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
649 !strconcat(mnemonic, "{b}\t$dst"),
650 [], IIC_UNARY_MEM>, LOCK;
651 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
652 !strconcat(mnemonic, "{w}\t$dst"),
653 [], IIC_UNARY_MEM>, OpSize16, LOCK;
654 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
655 !strconcat(mnemonic, "{l}\t$dst"),
656 [], IIC_UNARY_MEM>, OpSize32, LOCK;
657 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
658 !strconcat(mnemonic, "{q}\t$dst"),
659 [], IIC_UNARY_MEM>, LOCK;
663 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
664 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
666 // Atomic compare and swap.
667 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
668 SDPatternOperator frag, X86MemOperand x86memop,
669 InstrItinClass itin> {
670 let isCodeGenOnly = 1 in {
671 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
672 !strconcat(mnemonic, "\t$ptr"),
673 [(frag addr:$ptr)], itin>, TB, LOCK;
677 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
678 string mnemonic, SDPatternOperator frag,
679 InstrItinClass itin8, InstrItinClass itin> {
680 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
681 let Defs = [AL, EFLAGS], Uses = [AL] in
682 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
683 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
684 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
685 let Defs = [AX, EFLAGS], Uses = [AX] in
686 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
687 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
688 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
689 let Defs = [EAX, EFLAGS], Uses = [EAX] in
690 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
691 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
692 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
693 let Defs = [RAX, EFLAGS], Uses = [RAX] in
694 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
695 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
696 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
700 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
701 SchedRW = [WriteALULd, WriteRMW] in {
702 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
707 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
708 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
709 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
711 IIC_CMPX_LOCK_16B>, REX_W;
714 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
715 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
717 // Atomic exchange and add
718 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
720 InstrItinClass itin8, InstrItinClass itin> {
721 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
722 SchedRW = [WriteALULd, WriteRMW] in {
723 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
724 (ins GR8:$val, i8mem:$ptr),
725 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
727 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
729 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
730 (ins GR16:$val, i16mem:$ptr),
731 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
734 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
736 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
737 (ins GR32:$val, i32mem:$ptr),
738 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
741 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
743 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
744 (ins GR64:$val, i64mem:$ptr),
745 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
748 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
753 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
754 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
757 /* The following multiclass tries to make sure that in code like
758 * x.store (immediate op x.load(acquire), release)
760 * x.store (register op x.load(acquire), release)
761 * an operation directly on memory is generated instead of wasting a register.
762 * It is not automatic as atomic_store/load are only lowered to MOV instructions
763 * extremely late to prevent them from being accidentally reordered in the backend
764 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
766 multiclass RELEASE_BINOP_MI<SDNode op> {
767 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
768 "#BINOP "#NAME#"8mi PSEUDO!",
769 [(atomic_store_8 addr:$dst, (op
770 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
771 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src),
772 "#BINOP "#NAME#"8mr PSEUDO!",
773 [(atomic_store_8 addr:$dst, (op
774 (atomic_load_8 addr:$dst), GR8:$src))]>;
775 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
776 // costly and avoided as far as possible by this backend anyway
777 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
778 "#BINOP "#NAME#"32mi PSEUDO!",
779 [(atomic_store_32 addr:$dst, (op
780 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
781 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
782 "#BINOP "#NAME#"32mr PSEUDO!",
783 [(atomic_store_32 addr:$dst, (op
784 (atomic_load_32 addr:$dst), GR32:$src))]>;
785 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
786 "#BINOP "#NAME#"64mi32 PSEUDO!",
787 [(atomic_store_64 addr:$dst, (op
788 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
789 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
790 "#BINOP "#NAME#"64mr PSEUDO!",
791 [(atomic_store_64 addr:$dst, (op
792 (atomic_load_64 addr:$dst), GR64:$src))]>;
794 let Defs = [EFLAGS] in {
795 defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
796 defm RELEASE_AND : RELEASE_BINOP_MI<and>;
797 defm RELEASE_OR : RELEASE_BINOP_MI<or>;
798 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>;
799 // Note: we don't deal with sub, because substractions of constants are
800 // optimized into additions before this code can run.
803 // Same as above, but for floating-point.
804 // FIXME: imm version.
805 // FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
806 // FIXME: This could also handle SIMD operations with *ps and *pd instructions.
807 let usesCustomInserter = 1 in {
808 multiclass RELEASE_FP_BINOP_MI<SDNode op> {
809 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
810 "#BINOP "#NAME#"32mr PSEUDO!",
811 [(atomic_store_32 addr:$dst,
813 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))),
814 FR32:$src))))]>, Requires<[HasSSE1]>;
815 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src),
816 "#BINOP "#NAME#"64mr PSEUDO!",
817 [(atomic_store_64 addr:$dst,
819 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))),
820 FR64:$src))))]>, Requires<[HasSSE2]>;
822 defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>;
823 // FIXME: Add fsub, fmul, fdiv, ...
826 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
827 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
828 "#UNOP "#NAME#"8m PSEUDO!",
829 [(atomic_store_8 addr:$dst, dag8)]>;
830 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
831 "#UNOP "#NAME#"16m PSEUDO!",
832 [(atomic_store_16 addr:$dst, dag16)]>;
833 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
834 "#UNOP "#NAME#"32m PSEUDO!",
835 [(atomic_store_32 addr:$dst, dag32)]>;
836 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
837 "#UNOP "#NAME#"64m PSEUDO!",
838 [(atomic_store_64 addr:$dst, dag64)]>;
841 let Defs = [EFLAGS] in {
842 defm RELEASE_INC : RELEASE_UNOP<
843 (add (atomic_load_8 addr:$dst), (i8 1)),
844 (add (atomic_load_16 addr:$dst), (i16 1)),
845 (add (atomic_load_32 addr:$dst), (i32 1)),
846 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>;
847 defm RELEASE_DEC : RELEASE_UNOP<
848 (add (atomic_load_8 addr:$dst), (i8 -1)),
849 (add (atomic_load_16 addr:$dst), (i16 -1)),
850 (add (atomic_load_32 addr:$dst), (i32 -1)),
851 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>;
854 TODO: These don't work because the type inference of TableGen fails.
855 TODO: find a way to fix it.
856 let Defs = [EFLAGS] in {
857 defm RELEASE_NEG : RELEASE_UNOP<
858 (ineg (atomic_load_8 addr:$dst)),
859 (ineg (atomic_load_16 addr:$dst)),
860 (ineg (atomic_load_32 addr:$dst)),
861 (ineg (atomic_load_64 addr:$dst))>;
863 // NOT doesn't set flags.
864 defm RELEASE_NOT : RELEASE_UNOP<
865 (not (atomic_load_8 addr:$dst)),
866 (not (atomic_load_16 addr:$dst)),
867 (not (atomic_load_32 addr:$dst)),
868 (not (atomic_load_64 addr:$dst))>;
871 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
872 "#RELEASE_MOV8mi PSEUDO!",
873 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
874 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
875 "#RELEASE_MOV16mi PSEUDO!",
876 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
877 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
878 "#RELEASE_MOV32mi PSEUDO!",
879 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
880 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
881 "#RELEASE_MOV64mi32 PSEUDO!",
882 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
884 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
885 "#RELEASE_MOV8mr PSEUDO!",
886 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
887 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
888 "#RELEASE_MOV16mr PSEUDO!",
889 [(atomic_store_16 addr:$dst, GR16:$src)]>;
890 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
891 "#RELEASE_MOV32mr PSEUDO!",
892 [(atomic_store_32 addr:$dst, GR32:$src)]>;
893 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
894 "#RELEASE_MOV64mr PSEUDO!",
895 [(atomic_store_64 addr:$dst, GR64:$src)]>;
897 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
898 "#ACQUIRE_MOV8rm PSEUDO!",
899 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
900 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
901 "#ACQUIRE_MOV16rm PSEUDO!",
902 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
903 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
904 "#ACQUIRE_MOV32rm PSEUDO!",
905 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
906 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
907 "#ACQUIRE_MOV64rm PSEUDO!",
908 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
910 //===----------------------------------------------------------------------===//
911 // DAG Pattern Matching Rules
912 //===----------------------------------------------------------------------===//
914 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
915 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
916 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
917 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
918 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
919 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
920 def : Pat<(i32 (X86Wrapper mcsym:$dst)), (MOV32ri mcsym:$dst)>;
921 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
923 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
924 (ADD32ri GR32:$src1, tconstpool:$src2)>;
925 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
926 (ADD32ri GR32:$src1, tjumptable:$src2)>;
927 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
928 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
929 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
930 (ADD32ri GR32:$src1, texternalsym:$src2)>;
931 def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)),
932 (ADD32ri GR32:$src1, mcsym:$src2)>;
933 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
934 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
936 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
937 (MOV32mi addr:$dst, tglobaladdr:$src)>;
938 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
939 (MOV32mi addr:$dst, texternalsym:$src)>;
940 def : Pat<(store (i32 (X86Wrapper mcsym:$src)), addr:$dst),
941 (MOV32mi addr:$dst, mcsym:$src)>;
942 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
943 (MOV32mi addr:$dst, tblockaddress:$src)>;
945 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
946 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
947 // 'movabs' predicate should handle this sort of thing.
948 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
949 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
950 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
951 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
952 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
953 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
954 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
955 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
956 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
957 (MOV64ri mcsym:$dst)>, Requires<[FarData]>;
958 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
959 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
961 // In kernel code model, we can get the address of a label
962 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
963 // the MOV64ri32 should accept these.
964 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
965 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
966 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
967 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
968 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
969 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
970 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
971 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
972 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
973 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;
974 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
975 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
977 // If we have small model and -static mode, it is safe to store global addresses
978 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
979 // for MOV64mi32 should handle this sort of thing.
980 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
981 (MOV64mi32 addr:$dst, tconstpool:$src)>,
982 Requires<[NearData, IsStatic]>;
983 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
984 (MOV64mi32 addr:$dst, tjumptable:$src)>,
985 Requires<[NearData, IsStatic]>;
986 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
987 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
988 Requires<[NearData, IsStatic]>;
989 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
990 (MOV64mi32 addr:$dst, texternalsym:$src)>,
991 Requires<[NearData, IsStatic]>;
992 def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),
993 (MOV64mi32 addr:$dst, mcsym:$src)>,
994 Requires<[NearData, IsStatic]>;
995 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
996 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
997 Requires<[NearData, IsStatic]>;
999 def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;
1000 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
1004 // tls has some funny stuff here...
1005 // This corresponds to movabs $foo@tpoff, %rax
1006 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
1007 (MOV64ri32 tglobaltlsaddr :$dst)>;
1008 // This corresponds to add $foo@tpoff, %rax
1009 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1010 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1013 // Direct PC relative function call for small code model. 32-bit displacement
1014 // sign extended to 64-bit.
1015 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1016 (CALL64pcrel32 tglobaladdr:$dst)>;
1017 def : Pat<(X86call (i64 texternalsym:$dst)),
1018 (CALL64pcrel32 texternalsym:$dst)>;
1020 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1021 // can never use callee-saved registers. That is the purpose of the GR64_TC
1022 // register classes.
1024 // The only volatile register that is never used by the calling convention is
1025 // %r11. This happens when calling a vararg function with 6 arguments.
1027 // Match an X86tcret that uses less than 7 volatile registers.
1028 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1029 (X86tcret node:$ptr, node:$off), [{
1030 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1031 unsigned NumRegs = 0;
1032 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1033 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1038 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1039 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1040 Requires<[Not64BitMode]>;
1042 // FIXME: This is disabled for 32-bit PIC mode because the global base
1043 // register which is part of the address mode may be assigned a
1044 // callee-saved register.
1045 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1046 (TCRETURNmi addr:$dst, imm:$off)>,
1047 Requires<[Not64BitMode, IsNotPIC]>;
1049 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1050 (TCRETURNdi tglobaladdr:$dst, imm:$off)>,
1051 Requires<[NotLP64]>;
1053 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1054 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1055 Requires<[NotLP64]>;
1057 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1058 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1059 Requires<[In64BitMode]>;
1061 // Don't fold loads into X86tcret requiring more than 6 regs.
1062 // There wouldn't be enough scratch registers for base+index.
1063 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1064 (TCRETURNmi64 addr:$dst, imm:$off)>,
1065 Requires<[In64BitMode]>;
1067 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1068 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1071 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1072 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1075 // Normal calls, with various flavors of addresses.
1076 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1077 (CALLpcrel32 tglobaladdr:$dst)>;
1078 def : Pat<(X86call (i32 texternalsym:$dst)),
1079 (CALLpcrel32 texternalsym:$dst)>;
1080 def : Pat<(X86call (i32 imm:$dst)),
1081 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1085 // TEST R,R is smaller than CMP R,0
1086 def : Pat<(X86cmp GR8:$src1, 0),
1087 (TEST8rr GR8:$src1, GR8:$src1)>;
1088 def : Pat<(X86cmp GR16:$src1, 0),
1089 (TEST16rr GR16:$src1, GR16:$src1)>;
1090 def : Pat<(X86cmp GR32:$src1, 0),
1091 (TEST32rr GR32:$src1, GR32:$src1)>;
1092 def : Pat<(X86cmp GR64:$src1, 0),
1093 (TEST64rr GR64:$src1, GR64:$src1)>;
1095 // Conditional moves with folded loads with operands swapped and conditions
1097 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1098 Instruction Inst64> {
1099 let Predicates = [HasCMov] in {
1100 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1101 (Inst16 GR16:$src2, addr:$src1)>;
1102 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1103 (Inst32 GR32:$src2, addr:$src1)>;
1104 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1105 (Inst64 GR64:$src2, addr:$src1)>;
1109 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1110 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1111 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1112 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1113 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1114 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1115 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1116 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1117 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1118 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1119 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1120 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1121 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1122 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1123 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1124 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1126 // zextload bool -> zextload byte
1127 def : Pat<(zextloadi8i1 addr:$src), (AND8ri (MOV8rm addr:$src), (i8 1))>;
1128 def : Pat<(zextloadi16i1 addr:$src), (AND16ri8 (MOVZX16rm8 addr:$src), (i16 1))>;
1129 def : Pat<(zextloadi32i1 addr:$src), (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1))>;
1130 def : Pat<(zextloadi64i1 addr:$src),
1131 (SUBREG_TO_REG (i64 0),
1132 (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), sub_32bit)>;
1134 // extload bool -> extload byte
1135 // When extloading from 16-bit and smaller memory locations into 64-bit
1136 // registers, use zero-extending loads so that the entire 64-bit register is
1137 // defined, avoiding partial-register updates.
1139 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1140 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1141 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1142 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1143 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1144 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1146 // For other extloads, use subregs, since the high contents of the register are
1147 // defined after an extload.
1148 def : Pat<(extloadi64i1 addr:$src),
1149 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1150 def : Pat<(extloadi64i8 addr:$src),
1151 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1152 def : Pat<(extloadi64i16 addr:$src),
1153 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1154 def : Pat<(extloadi64i32 addr:$src),
1155 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1157 // anyext. Define these to do an explicit zero-extend to
1158 // avoid partial-register updates.
1159 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1160 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1161 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1163 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1164 def : Pat<(i32 (anyext GR16:$src)),
1165 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1167 def : Pat<(i64 (anyext GR8 :$src)),
1168 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1169 def : Pat<(i64 (anyext GR16:$src)),
1170 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1171 def : Pat<(i64 (anyext GR32:$src)),
1172 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1175 // Any instruction that defines a 32-bit result leaves the high half of the
1176 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1177 // be copying from a truncate. And x86's cmov doesn't do anything if the
1178 // condition is false. But any other 32-bit operation will zero-extend
1180 def def32 : PatLeaf<(i32 GR32:$src), [{
1181 return N->getOpcode() != ISD::TRUNCATE &&
1182 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1183 N->getOpcode() != ISD::CopyFromReg &&
1184 N->getOpcode() != ISD::AssertSext &&
1185 N->getOpcode() != X86ISD::CMOV;
1188 // In the case of a 32-bit def that is known to implicitly zero-extend,
1189 // we can use a SUBREG_TO_REG.
1190 def : Pat<(i64 (zext def32:$src)),
1191 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1193 //===----------------------------------------------------------------------===//
1194 // Pattern match OR as ADD
1195 //===----------------------------------------------------------------------===//
1197 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1198 // 3-addressified into an LEA instruction to avoid copies. However, we also
1199 // want to finally emit these instructions as an or at the end of the code
1200 // generator to make the generated code easier to read. To do this, we select
1201 // into "disjoint bits" pseudo ops.
1203 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1204 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1205 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1206 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1208 APInt KnownZero0, KnownOne0;
1209 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1210 APInt KnownZero1, KnownOne1;
1211 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1212 return (~KnownZero0 & ~KnownZero1) == 0;
1216 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1217 // Try this before the selecting to OR.
1218 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1220 let isConvertibleToThreeAddress = 1,
1221 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1222 let isCommutable = 1 in {
1223 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1224 "", // orw/addw REG, REG
1225 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1226 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1227 "", // orl/addl REG, REG
1228 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1229 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1230 "", // orq/addq REG, REG
1231 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1234 // NOTE: These are order specific, we want the ri8 forms to be listed
1235 // first so that they are slightly preferred to the ri forms.
1237 def ADD16ri8_DB : I<0, Pseudo,
1238 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1239 "", // orw/addw REG, imm8
1240 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1241 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1242 "", // orw/addw REG, imm
1243 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1245 def ADD32ri8_DB : I<0, Pseudo,
1246 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1247 "", // orl/addl REG, imm8
1248 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1249 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1250 "", // orl/addl REG, imm
1251 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1254 def ADD64ri8_DB : I<0, Pseudo,
1255 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1256 "", // orq/addq REG, imm8
1257 [(set GR64:$dst, (or_is_add GR64:$src1,
1258 i64immSExt8:$src2))]>;
1259 def ADD64ri32_DB : I<0, Pseudo,
1260 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1261 "", // orq/addq REG, imm
1262 [(set GR64:$dst, (or_is_add GR64:$src1,
1263 i64immSExt32:$src2))]>;
1265 } // AddedComplexity, SchedRW
1268 //===----------------------------------------------------------------------===//
1270 //===----------------------------------------------------------------------===//
1272 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1273 // +128 doesn't, so in this special case use a sub instead of an add.
1274 def : Pat<(add GR16:$src1, 128),
1275 (SUB16ri8 GR16:$src1, -128)>;
1276 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1277 (SUB16mi8 addr:$dst, -128)>;
1279 def : Pat<(add GR32:$src1, 128),
1280 (SUB32ri8 GR32:$src1, -128)>;
1281 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1282 (SUB32mi8 addr:$dst, -128)>;
1284 def : Pat<(add GR64:$src1, 128),
1285 (SUB64ri8 GR64:$src1, -128)>;
1286 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1287 (SUB64mi8 addr:$dst, -128)>;
1289 // The same trick applies for 32-bit immediate fields in 64-bit
1291 def : Pat<(add GR64:$src1, 0x0000000080000000),
1292 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1293 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1294 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1296 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1297 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1298 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1299 // represented with a sign extension of a 8 bit constant, use that.
1300 // This can also reduce instruction size by eliminating the need for the REX
1303 // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.
1304 let AddedComplexity = 1 in {
1305 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1309 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1310 (i32 (GetLo8XForm imm:$imm))),
1313 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1317 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1318 (i32 (GetLo32XForm imm:$imm))),
1320 } // AddedComplexity = 1
1323 // AddedComplexity is needed due to the increased complexity on the
1324 // i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all
1325 // the MOVZX patterns keeps thems together in DAGIsel tables.
1326 let AddedComplexity = 1 in {
1327 // r & (2^16-1) ==> movz
1328 def : Pat<(and GR32:$src1, 0xffff),
1329 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1330 // r & (2^8-1) ==> movz
1331 def : Pat<(and GR32:$src1, 0xff),
1332 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1335 Requires<[Not64BitMode]>;
1336 // r & (2^8-1) ==> movz
1337 def : Pat<(and GR16:$src1, 0xff),
1338 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1339 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1341 Requires<[Not64BitMode]>;
1343 // r & (2^32-1) ==> movz
1344 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1345 (SUBREG_TO_REG (i64 0),
1346 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1348 // r & (2^16-1) ==> movz
1349 def : Pat<(and GR64:$src, 0xffff),
1350 (SUBREG_TO_REG (i64 0),
1351 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1353 // r & (2^8-1) ==> movz
1354 def : Pat<(and GR64:$src, 0xff),
1355 (SUBREG_TO_REG (i64 0),
1356 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1358 // r & (2^8-1) ==> movz
1359 def : Pat<(and GR32:$src1, 0xff),
1360 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1361 Requires<[In64BitMode]>;
1362 // r & (2^8-1) ==> movz
1363 def : Pat<(and GR16:$src1, 0xff),
1364 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1365 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1366 Requires<[In64BitMode]>;
1367 } // AddedComplexity = 1
1370 // sext_inreg patterns
1371 def : Pat<(sext_inreg GR32:$src, i16),
1372 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1373 def : Pat<(sext_inreg GR32:$src, i8),
1374 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1377 Requires<[Not64BitMode]>;
1379 def : Pat<(sext_inreg GR16:$src, i8),
1380 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1381 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1383 Requires<[Not64BitMode]>;
1385 def : Pat<(sext_inreg GR64:$src, i32),
1386 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1387 def : Pat<(sext_inreg GR64:$src, i16),
1388 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1389 def : Pat<(sext_inreg GR64:$src, i8),
1390 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1391 def : Pat<(sext_inreg GR32:$src, i8),
1392 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1393 Requires<[In64BitMode]>;
1394 def : Pat<(sext_inreg GR16:$src, i8),
1395 (EXTRACT_SUBREG (MOVSX32rr8
1396 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1397 Requires<[In64BitMode]>;
1399 // sext, sext_load, zext, zext_load
1400 def: Pat<(i16 (sext GR8:$src)),
1401 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1402 def: Pat<(sextloadi16i8 addr:$src),
1403 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1404 def: Pat<(i16 (zext GR8:$src)),
1405 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1406 def: Pat<(zextloadi16i8 addr:$src),
1407 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1410 def : Pat<(i16 (trunc GR32:$src)),
1411 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1412 def : Pat<(i8 (trunc GR32:$src)),
1413 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1415 Requires<[Not64BitMode]>;
1416 def : Pat<(i8 (trunc GR16:$src)),
1417 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1419 Requires<[Not64BitMode]>;
1420 def : Pat<(i32 (trunc GR64:$src)),
1421 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1422 def : Pat<(i16 (trunc GR64:$src)),
1423 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1424 def : Pat<(i8 (trunc GR64:$src)),
1425 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1426 def : Pat<(i8 (trunc GR32:$src)),
1427 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1428 Requires<[In64BitMode]>;
1429 def : Pat<(i8 (trunc GR16:$src)),
1430 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1431 Requires<[In64BitMode]>;
1433 // h-register tricks
1434 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1435 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1437 Requires<[Not64BitMode]>;
1438 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1439 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1441 Requires<[Not64BitMode]>;
1442 def : Pat<(srl GR16:$src, (i8 8)),
1445 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1448 Requires<[Not64BitMode]>;
1449 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1450 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1453 Requires<[Not64BitMode]>;
1454 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1455 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1458 Requires<[Not64BitMode]>;
1459 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1460 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1463 Requires<[Not64BitMode]>;
1464 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1465 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1468 Requires<[Not64BitMode]>;
1470 // h-register tricks.
1471 // For now, be conservative on x86-64 and use an h-register extract only if the
1472 // value is immediately zero-extended or stored, which are somewhat common
1473 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1474 // from being allocated in the same instruction as the h register, as there's
1475 // currently no way to describe this requirement to the register allocator.
1477 // h-register extract and zero-extend.
1478 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1482 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1485 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1487 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1489 Requires<[In64BitMode]>;
1490 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1491 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1494 Requires<[In64BitMode]>;
1495 def : Pat<(srl GR16:$src, (i8 8)),
1498 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1501 Requires<[In64BitMode]>;
1502 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1504 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1506 Requires<[In64BitMode]>;
1507 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1509 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1511 Requires<[In64BitMode]>;
1512 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1516 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1519 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1523 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1527 // h-register extract and store.
1528 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1531 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1533 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1536 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1538 Requires<[In64BitMode]>;
1539 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1542 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1544 Requires<[In64BitMode]>;
1547 // (shl x, 1) ==> (add x, x)
1548 // Note that if x is undef (immediate or otherwise), we could theoretically
1549 // end up with the two uses of x getting different values, producing a result
1550 // where the least significant bit is not 0. However, the probability of this
1551 // happening is considered low enough that this is officially not a
1553 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1554 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1555 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1556 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1558 // Helper imms that check if a mask doesn't change significant shift bits.
1559 def immShift32 : ImmLeaf<i8, [{
1560 return countTrailingOnes<uint64_t>(Imm) >= 5;
1562 def immShift64 : ImmLeaf<i8, [{
1563 return countTrailingOnes<uint64_t>(Imm) >= 6;
1566 // Shift amount is implicitly masked.
1567 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1568 // (shift x (and y, 31)) ==> (shift x, y)
1569 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1570 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1571 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1572 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1573 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1574 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1575 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1576 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1577 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1578 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1579 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1580 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1582 // (shift x (and y, 63)) ==> (shift x, y)
1583 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1584 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1585 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1586 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1589 defm : MaskedShiftAmountPats<shl, "SHL">;
1590 defm : MaskedShiftAmountPats<srl, "SHR">;
1591 defm : MaskedShiftAmountPats<sra, "SAR">;
1592 defm : MaskedShiftAmountPats<rotl, "ROL">;
1593 defm : MaskedShiftAmountPats<rotr, "ROR">;
1595 // (anyext (setcc_carry)) -> (setcc_carry)
1596 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1598 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1600 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1606 //===----------------------------------------------------------------------===//
1607 // EFLAGS-defining Patterns
1608 //===----------------------------------------------------------------------===//
1611 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1612 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1613 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1616 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1617 (ADD8rm GR8:$src1, addr:$src2)>;
1618 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1619 (ADD16rm GR16:$src1, addr:$src2)>;
1620 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1621 (ADD32rm GR32:$src1, addr:$src2)>;
1624 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1625 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1626 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1627 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1628 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1629 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1630 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1633 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1634 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1635 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1638 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1639 (SUB8rm GR8:$src1, addr:$src2)>;
1640 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1641 (SUB16rm GR16:$src1, addr:$src2)>;
1642 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1643 (SUB32rm GR32:$src1, addr:$src2)>;
1646 def : Pat<(sub GR8:$src1, imm:$src2),
1647 (SUB8ri GR8:$src1, imm:$src2)>;
1648 def : Pat<(sub GR16:$src1, imm:$src2),
1649 (SUB16ri GR16:$src1, imm:$src2)>;
1650 def : Pat<(sub GR32:$src1, imm:$src2),
1651 (SUB32ri GR32:$src1, imm:$src2)>;
1652 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1653 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1654 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1655 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1658 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1659 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1660 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1661 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1664 def : Pat<(mul GR16:$src1, GR16:$src2),
1665 (IMUL16rr GR16:$src1, GR16:$src2)>;
1666 def : Pat<(mul GR32:$src1, GR32:$src2),
1667 (IMUL32rr GR32:$src1, GR32:$src2)>;
1670 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1671 (IMUL16rm GR16:$src1, addr:$src2)>;
1672 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1673 (IMUL32rm GR32:$src1, addr:$src2)>;
1676 def : Pat<(mul GR16:$src1, imm:$src2),
1677 (IMUL16rri GR16:$src1, imm:$src2)>;
1678 def : Pat<(mul GR32:$src1, imm:$src2),
1679 (IMUL32rri GR32:$src1, imm:$src2)>;
1680 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1681 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1682 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1683 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1685 // reg = mul mem, imm
1686 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1687 (IMUL16rmi addr:$src1, imm:$src2)>;
1688 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1689 (IMUL32rmi addr:$src1, imm:$src2)>;
1690 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1691 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1692 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1693 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1695 // Patterns for nodes that do not produce flags, for instructions that do.
1698 def : Pat<(add GR64:$src1, GR64:$src2),
1699 (ADD64rr GR64:$src1, GR64:$src2)>;
1700 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1701 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1702 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1703 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1704 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1705 (ADD64rm GR64:$src1, addr:$src2)>;
1708 def : Pat<(sub GR64:$src1, GR64:$src2),
1709 (SUB64rr GR64:$src1, GR64:$src2)>;
1710 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1711 (SUB64rm GR64:$src1, addr:$src2)>;
1712 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1713 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1714 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1715 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1718 def : Pat<(mul GR64:$src1, GR64:$src2),
1719 (IMUL64rr GR64:$src1, GR64:$src2)>;
1720 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1721 (IMUL64rm GR64:$src1, addr:$src2)>;
1722 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1723 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1724 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1725 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1726 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1727 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1728 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1729 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1731 // Increment/Decrement reg.
1732 // Do not make INC/DEC if it is slow
1733 let Predicates = [NotSlowIncDec] in {
1734 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
1735 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
1736 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
1737 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1738 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
1739 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
1740 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
1741 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1745 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1746 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1747 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1748 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1751 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1752 (OR8rm GR8:$src1, addr:$src2)>;
1753 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1754 (OR16rm GR16:$src1, addr:$src2)>;
1755 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1756 (OR32rm GR32:$src1, addr:$src2)>;
1757 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1758 (OR64rm GR64:$src1, addr:$src2)>;
1761 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1762 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1763 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1764 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1765 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1766 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1767 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1768 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1769 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1770 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1771 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1774 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1775 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1776 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1777 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1780 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1781 (XOR8rm GR8:$src1, addr:$src2)>;
1782 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1783 (XOR16rm GR16:$src1, addr:$src2)>;
1784 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1785 (XOR32rm GR32:$src1, addr:$src2)>;
1786 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1787 (XOR64rm GR64:$src1, addr:$src2)>;
1790 def : Pat<(xor GR8:$src1, imm:$src2),
1791 (XOR8ri GR8:$src1, imm:$src2)>;
1792 def : Pat<(xor GR16:$src1, imm:$src2),
1793 (XOR16ri GR16:$src1, imm:$src2)>;
1794 def : Pat<(xor GR32:$src1, imm:$src2),
1795 (XOR32ri GR32:$src1, imm:$src2)>;
1796 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1797 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1798 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1799 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1800 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1801 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1802 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1803 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1806 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1807 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1808 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1809 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1812 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1813 (AND8rm GR8:$src1, addr:$src2)>;
1814 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1815 (AND16rm GR16:$src1, addr:$src2)>;
1816 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1817 (AND32rm GR32:$src1, addr:$src2)>;
1818 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1819 (AND64rm GR64:$src1, addr:$src2)>;
1822 def : Pat<(and GR8:$src1, imm:$src2),
1823 (AND8ri GR8:$src1, imm:$src2)>;
1824 def : Pat<(and GR16:$src1, imm:$src2),
1825 (AND16ri GR16:$src1, imm:$src2)>;
1826 def : Pat<(and GR32:$src1, imm:$src2),
1827 (AND32ri GR32:$src1, imm:$src2)>;
1828 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1829 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1830 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1831 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1832 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1833 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1834 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1835 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1837 // Bit scan instruction patterns to match explicit zero-undef behavior.
1838 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1839 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1840 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1841 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1842 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1843 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1845 // When HasMOVBE is enabled it is possible to get a non-legalized
1846 // register-register 16 bit bswap. This maps it to a ROL instruction.
1847 let Predicates = [HasMOVBE] in {
1848 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;