1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[Not64BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[Not64BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1, Defs = [EFLAGS] in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
87 // The VAARG_64 pseudo-instruction takes the address of the va_list,
88 // and places the address of the next argument into a register.
89 let Defs = [EFLAGS] in
90 def VAARG_64 : I<0, Pseudo,
92 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
93 "#VAARG_64 $dst, $ap, $size, $mode, $align",
95 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
98 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
99 // targets. These calls are needed to probe the stack when allocating more than
100 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
101 // ensure that the guard pages used by the OS virtual memory manager are
102 // allocated in correct sequence.
103 // The main point of having separate instruction are extra unmodelled effects
104 // (compared to ordinary calls) like stack pointer change.
106 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
107 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
108 "# dynamic stack allocation",
111 // When using segmented stacks these are lowered into instructions which first
112 // check if the current stacklet has enough free memory. If it does, memory is
113 // allocated by bumping the stack pointer. Otherwise memory is allocated from
116 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
117 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
118 "# variable sized alloca for segmented stacks",
120 (X86SegAlloca GR32:$size))]>,
121 Requires<[Not64BitMode]>;
123 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
124 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
125 "# variable sized alloca for segmented stacks",
127 (X86SegAlloca GR64:$size))]>,
128 Requires<[In64BitMode]>;
131 // The MSVC runtime contains an _ftol2 routine for converting floating-point
132 // to integer values. It has a strange calling convention: the input is
133 // popped from the x87 stack, and the return value is given in EDX:EAX. ECX is
134 // used as a temporary register. No other registers (aside from flags) are
136 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
137 // variant is unnecessary.
139 let Defs = [EAX, EDX, ECX, EFLAGS], FPForm = SpecialFP in {
140 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
142 [(X86WinFTOL RFP32:$src)]>,
143 Requires<[Not64BitMode]>;
145 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
147 [(X86WinFTOL RFP64:$src)]>,
148 Requires<[Not64BitMode]>;
151 //===----------------------------------------------------------------------===//
152 // EH Pseudo Instructions
154 let SchedRW = [WriteSystem] in {
155 let isTerminator = 1, isReturn = 1, isBarrier = 1,
156 hasCtrlDep = 1, isCodeGenOnly = 1 in {
157 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
158 "ret\t#eh_return, addr: $addr",
159 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
163 let isTerminator = 1, isReturn = 1, isBarrier = 1,
164 hasCtrlDep = 1, isCodeGenOnly = 1 in {
165 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
166 "ret\t#eh_return, addr: $addr",
167 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
171 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
172 usesCustomInserter = 1 in {
173 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
175 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
176 Requires<[Not64BitMode]>;
177 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
179 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
180 Requires<[In64BitMode]>;
181 let isTerminator = 1 in {
182 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
183 "#EH_SJLJ_LONGJMP32",
184 [(X86eh_sjlj_longjmp addr:$buf)]>,
185 Requires<[Not64BitMode]>;
186 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
187 "#EH_SJLJ_LONGJMP64",
188 [(X86eh_sjlj_longjmp addr:$buf)]>,
189 Requires<[In64BitMode]>;
194 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
195 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
196 "#EH_SjLj_Setup\t$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // Pseudo instructions used by unwind info.
202 let isPseudo = 1 in {
203 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
204 "#SEH_PushReg $reg", []>;
205 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
206 "#SEH_SaveReg $reg, $dst", []>;
207 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
208 "#SEH_SaveXMM $reg, $dst", []>;
209 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
210 "#SEH_StackAlloc $size", []>;
211 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
212 "#SEH_SetFrame $reg, $offset", []>;
213 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
214 "#SEH_PushFrame $mode", []>;
215 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
216 "#SEH_EndPrologue", []>;
219 //===----------------------------------------------------------------------===//
220 // Pseudo instructions used by segmented stacks.
223 // This is lowered into a RET instruction by MCInstLower. We need
224 // this so that we don't have to have a MachineBasicBlock which ends
225 // with a RET and also has successors.
226 let isPseudo = 1 in {
227 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
230 // This instruction is lowered to a RET followed by a MOV. The two
231 // instructions are not generated on a higher level since then the
232 // verifier sees a MachineBasicBlock ending with a non-terminator.
233 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
237 //===----------------------------------------------------------------------===//
238 // Alias Instructions
239 //===----------------------------------------------------------------------===//
241 // Alias instruction mapping movr0 to xor.
242 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
243 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
245 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
246 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
248 // Other widths can also make use of the 32-bit xor, which may have a smaller
249 // encoding and avoid partial register updates.
250 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
251 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
252 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
253 let AddedComplexity = 20;
256 // Materialize i64 constant where top 32-bits are zero. This could theoretically
257 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
258 // that would make it more difficult to rematerialize.
259 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
260 isCodeGenOnly = 1, neverHasSideEffects = 1 in
261 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
262 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
264 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
265 // actually the zero-extension of a 32-bit constant, and for labels in the
266 // x86-64 small code model.
267 def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>;
269 let AddedComplexity = 1 in
270 def : Pat<(i64 mov64imm32:$src),
271 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
273 // Use sbb to materialize carry bit.
274 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
275 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
276 // However, Pat<> can't replicate the destination reg into the inputs of the
278 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
279 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
280 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
281 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
282 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
283 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
284 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
285 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
289 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
291 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
293 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
296 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
298 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
300 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
303 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
304 // will be eliminated and that the sbb can be extended up to a wider type. When
305 // this happens, it is great. However, if we are left with an 8-bit sbb and an
306 // and, we might as well just match it as a setb.
307 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
310 // (add OP, SETB) -> (adc OP, 0)
311 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
312 (ADC8ri GR8:$op, 0)>;
313 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
314 (ADC32ri8 GR32:$op, 0)>;
315 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
316 (ADC64ri8 GR64:$op, 0)>;
318 // (sub OP, SETB) -> (sbb OP, 0)
319 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
320 (SBB8ri GR8:$op, 0)>;
321 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
322 (SBB32ri8 GR32:$op, 0)>;
323 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
324 (SBB64ri8 GR64:$op, 0)>;
326 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
327 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
328 (ADC8ri GR8:$op, 0)>;
329 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
330 (ADC32ri8 GR32:$op, 0)>;
331 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
332 (ADC64ri8 GR64:$op, 0)>;
334 //===----------------------------------------------------------------------===//
335 // String Pseudo Instructions
337 let SchedRW = [WriteMicrocoded] in {
338 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
339 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
340 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
341 Requires<[Not64BitMode]>;
342 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
343 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
344 Requires<[Not64BitMode]>;
345 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
346 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
347 Requires<[Not64BitMode]>;
350 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
351 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
352 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
353 Requires<[In64BitMode]>;
354 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
355 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
356 Requires<[In64BitMode]>;
357 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
358 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
359 Requires<[In64BitMode]>;
360 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
361 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
362 Requires<[In64BitMode]>;
365 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
366 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
367 let Uses = [AL,ECX,EDI] in
368 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
369 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
370 Requires<[Not64BitMode]>;
371 let Uses = [AX,ECX,EDI] in
372 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
373 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
374 Requires<[Not64BitMode]>;
375 let Uses = [EAX,ECX,EDI] in
376 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
377 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
378 Requires<[Not64BitMode]>;
381 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
382 let Uses = [AL,RCX,RDI] in
383 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
384 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
385 Requires<[In64BitMode]>;
386 let Uses = [AX,RCX,RDI] in
387 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
388 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
389 Requires<[In64BitMode]>;
390 let Uses = [RAX,RCX,RDI] in
391 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
392 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
393 Requires<[In64BitMode]>;
395 let Uses = [RAX,RCX,RDI] in
396 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
397 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
398 Requires<[In64BitMode]>;
402 //===----------------------------------------------------------------------===//
403 // Thread Local Storage Instructions
407 // All calls clobber the non-callee saved registers. ESP is marked as
408 // a use to prevent stack-pointer assignments that appear immediately
409 // before calls from potentially appearing dead.
410 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
411 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
412 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
413 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
415 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
417 [(X86tlsaddr tls32addr:$sym)]>,
418 Requires<[Not64BitMode]>;
419 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
421 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
422 Requires<[Not64BitMode]>;
425 // All calls clobber the non-callee saved registers. RSP is marked as
426 // a use to prevent stack-pointer assignments that appear immediately
427 // before calls from potentially appearing dead.
428 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
429 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
430 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
431 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
432 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
434 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
436 [(X86tlsaddr tls64addr:$sym)]>,
437 Requires<[In64BitMode]>;
438 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
440 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
441 Requires<[In64BitMode]>;
444 // Darwin TLS Support
445 // For i386, the address of the thunk is passed on the stack, on return the
446 // address of the variable is in %eax. %ecx is trashed during the function
447 // call. All other registers are preserved.
448 let Defs = [EAX, ECX, EFLAGS],
450 usesCustomInserter = 1 in
451 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
453 [(X86TLSCall addr:$sym)]>,
454 Requires<[Not64BitMode]>;
456 // For x86_64, the address of the thunk is passed in %rdi, on return
457 // the address of the variable is in %rax. All other registers are preserved.
458 let Defs = [RAX, EFLAGS],
460 usesCustomInserter = 1 in
461 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
463 [(X86TLSCall addr:$sym)]>,
464 Requires<[In64BitMode]>;
467 //===----------------------------------------------------------------------===//
468 // Conditional Move Pseudo Instructions
470 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
471 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
472 // however that requires promoting the operands, and can induce additional
473 // i8 register pressure.
474 let usesCustomInserter = 1, Uses = [EFLAGS] in {
475 def CMOV_GR8 : I<0, Pseudo,
476 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
478 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
479 imm:$cond, EFLAGS))]>;
481 let Predicates = [NoCMov] in {
482 def CMOV_GR32 : I<0, Pseudo,
483 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
484 "#CMOV_GR32* PSEUDO!",
486 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
487 def CMOV_GR16 : I<0, Pseudo,
488 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
489 "#CMOV_GR16* PSEUDO!",
491 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
492 } // Predicates = [NoCMov]
494 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
496 let Predicates = [FPStackf32] in
497 def CMOV_RFP32 : I<0, Pseudo,
499 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
500 "#CMOV_RFP32 PSEUDO!",
502 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
504 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
506 let Predicates = [FPStackf64] in
507 def CMOV_RFP64 : I<0, Pseudo,
509 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
510 "#CMOV_RFP64 PSEUDO!",
512 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
514 def CMOV_RFP80 : I<0, Pseudo,
516 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
517 "#CMOV_RFP80 PSEUDO!",
519 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
521 } // UsesCustomInserter = 1, Uses = [EFLAGS]
524 //===----------------------------------------------------------------------===//
525 // Atomic Instruction Pseudo Instructions
526 //===----------------------------------------------------------------------===//
528 // Pseudo atomic instructions
530 multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> {
531 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in {
532 let Defs = [EFLAGS, AL] in
533 def NAME#8 : I<0, Pseudo, (outs GR8:$dst),
534 (ins i8mem:$ptr, GR8:$val),
535 !strconcat(mnemonic, "8 PSEUDO!"), []>;
536 let Defs = [EFLAGS, AX] in
537 def NAME#16 : I<0, Pseudo,(outs GR16:$dst),
538 (ins i16mem:$ptr, GR16:$val),
539 !strconcat(mnemonic, "16 PSEUDO!"), []>;
540 let Defs = [EFLAGS, EAX] in
541 def NAME#32 : I<0, Pseudo, (outs GR32:$dst),
542 (ins i32mem:$ptr, GR32:$val),
543 !strconcat(mnemonic, "32 PSEUDO!"), []>;
544 let Defs = [EFLAGS, RAX] in
545 def NAME#64 : I<0, Pseudo, (outs GR64:$dst),
546 (ins i64mem:$ptr, GR64:$val),
547 !strconcat(mnemonic, "64 PSEUDO!"), []>;
551 multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> {
552 def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val),
553 (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>;
554 def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val),
555 (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>;
556 def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val),
557 (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>;
558 def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val),
559 (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>;
562 // Atomic exchange, and, or, xor
563 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">;
564 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">;
565 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">;
566 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">;
567 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">;
568 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">;
569 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">;
570 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">;
572 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">;
573 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">;
574 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">;
575 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">;
576 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">;
577 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">;
578 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">;
579 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">;
581 multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> {
582 let usesCustomInserter = 1, Defs = [EFLAGS, EAX, EDX],
583 mayLoad = 1, mayStore = 1, hasSideEffects = 0 in
584 def NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
585 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
586 !strconcat(mnemonic, "6432 PSEUDO!"), []>;
589 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMAND">;
590 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMOR">;
591 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMXOR">;
592 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMNAND">;
593 defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMADD">;
594 defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSUB">;
595 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMAX">;
596 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMIN">;
597 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMAX">;
598 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMIN">;
599 defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSWAP">;
601 //===----------------------------------------------------------------------===//
602 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
603 //===----------------------------------------------------------------------===//
605 // FIXME: Use normal instructions and add lock prefix dynamically.
609 // TODO: Get this to fold the constant into the instruction.
610 let isCodeGenOnly = 1, Defs = [EFLAGS] in
611 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
612 "or{l}\t{$zero, $dst|$dst, $zero}",
613 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
614 Sched<[WriteALULd, WriteRMW]>;
616 let hasSideEffects = 1 in
617 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
619 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
621 // RegOpc corresponds to the mr version of the instruction
622 // ImmOpc corresponds to the mi version of the instruction
623 // ImmOpc8 corresponds to the mi8 version of the instruction
624 // ImmMod corresponds to the instruction format of the mi and mi8 versions
625 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
626 Format ImmMod, string mnemonic> {
627 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
628 SchedRW = [WriteALULd, WriteRMW] in {
630 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
631 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
632 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
633 !strconcat(mnemonic, "{b}\t",
634 "{$src2, $dst|$dst, $src2}"),
635 [], IIC_ALU_NONMEM>, LOCK;
636 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
637 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
638 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
639 !strconcat(mnemonic, "{w}\t",
640 "{$src2, $dst|$dst, $src2}"),
641 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
642 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
643 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
644 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
645 !strconcat(mnemonic, "{l}\t",
646 "{$src2, $dst|$dst, $src2}"),
647 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
648 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
649 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
650 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
651 !strconcat(mnemonic, "{q}\t",
652 "{$src2, $dst|$dst, $src2}"),
653 [], IIC_ALU_NONMEM>, LOCK;
655 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
656 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
657 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
658 !strconcat(mnemonic, "{b}\t",
659 "{$src2, $dst|$dst, $src2}"),
660 [], IIC_ALU_MEM>, LOCK;
662 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
663 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
664 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
665 !strconcat(mnemonic, "{w}\t",
666 "{$src2, $dst|$dst, $src2}"),
667 [], IIC_ALU_MEM>, OpSize16, LOCK;
669 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
670 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
671 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
672 !strconcat(mnemonic, "{l}\t",
673 "{$src2, $dst|$dst, $src2}"),
674 [], IIC_ALU_MEM>, OpSize32, LOCK;
676 def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
677 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
678 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
679 !strconcat(mnemonic, "{q}\t",
680 "{$src2, $dst|$dst, $src2}"),
681 [], IIC_ALU_MEM>, LOCK;
683 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
684 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
685 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
686 !strconcat(mnemonic, "{w}\t",
687 "{$src2, $dst|$dst, $src2}"),
688 [], IIC_ALU_MEM>, OpSize16, LOCK;
689 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
690 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
691 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
692 !strconcat(mnemonic, "{l}\t",
693 "{$src2, $dst|$dst, $src2}"),
694 [], IIC_ALU_MEM>, OpSize32, LOCK;
695 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
696 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
697 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
698 !strconcat(mnemonic, "{q}\t",
699 "{$src2, $dst|$dst, $src2}"),
700 [], IIC_ALU_MEM>, LOCK;
706 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
707 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
708 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
709 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
710 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
712 // Optimized codegen when the non-memory output is not used.
713 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
715 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
716 SchedRW = [WriteALULd, WriteRMW] in {
718 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
719 !strconcat(mnemonic, "{b}\t$dst"),
720 [], IIC_UNARY_MEM>, LOCK;
721 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
722 !strconcat(mnemonic, "{w}\t$dst"),
723 [], IIC_UNARY_MEM>, OpSize16, LOCK;
724 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
725 !strconcat(mnemonic, "{l}\t$dst"),
726 [], IIC_UNARY_MEM>, OpSize32, LOCK;
727 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
728 !strconcat(mnemonic, "{q}\t$dst"),
729 [], IIC_UNARY_MEM>, LOCK;
733 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
734 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
736 // Atomic compare and swap.
737 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
738 SDPatternOperator frag, X86MemOperand x86memop,
739 InstrItinClass itin> {
740 let isCodeGenOnly = 1 in {
741 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
742 !strconcat(mnemonic, "\t$ptr"),
743 [(frag addr:$ptr)], itin>, TB, LOCK;
747 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
748 string mnemonic, SDPatternOperator frag,
749 InstrItinClass itin8, InstrItinClass itin> {
750 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
751 let Defs = [AL, EFLAGS], Uses = [AL] in
752 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
753 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
754 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
755 let Defs = [AX, EFLAGS], Uses = [AX] in
756 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
757 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
758 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
759 let Defs = [EAX, EFLAGS], Uses = [EAX] in
760 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
761 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
762 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
763 let Defs = [RAX, EFLAGS], Uses = [RAX] in
764 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
765 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
766 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
770 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
771 SchedRW = [WriteALULd, WriteRMW] in {
772 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
777 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
778 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
779 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
781 IIC_CMPX_LOCK_16B>, REX_W;
784 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
785 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
787 // Atomic exchange and add
788 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
790 InstrItinClass itin8, InstrItinClass itin> {
791 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
792 SchedRW = [WriteALULd, WriteRMW] in {
793 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
794 (ins GR8:$val, i8mem:$ptr),
795 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
797 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
799 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
800 (ins GR16:$val, i16mem:$ptr),
801 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
804 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
806 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
807 (ins GR32:$val, i32mem:$ptr),
808 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
811 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
813 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
814 (ins GR64:$val, i64mem:$ptr),
815 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
818 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
823 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
824 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
827 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
828 "#ACQUIRE_MOV PSEUDO!",
829 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
830 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
831 "#ACQUIRE_MOV PSEUDO!",
832 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
833 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
834 "#ACQUIRE_MOV PSEUDO!",
835 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
836 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
837 "#ACQUIRE_MOV PSEUDO!",
838 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
840 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
841 "#RELEASE_MOV PSEUDO!",
842 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
843 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
844 "#RELEASE_MOV PSEUDO!",
845 [(atomic_store_16 addr:$dst, GR16:$src)]>;
846 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
847 "#RELEASE_MOV PSEUDO!",
848 [(atomic_store_32 addr:$dst, GR32:$src)]>;
849 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
850 "#RELEASE_MOV PSEUDO!",
851 [(atomic_store_64 addr:$dst, GR64:$src)]>;
853 //===----------------------------------------------------------------------===//
854 // Conditional Move Pseudo Instructions.
855 //===----------------------------------------------------------------------===//
858 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
859 // instruction selection into a branch sequence.
860 let Uses = [EFLAGS], usesCustomInserter = 1 in {
861 def CMOV_FR32 : I<0, Pseudo,
862 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
863 "#CMOV_FR32 PSEUDO!",
864 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
866 def CMOV_FR64 : I<0, Pseudo,
867 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
868 "#CMOV_FR64 PSEUDO!",
869 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
871 def CMOV_V4F32 : I<0, Pseudo,
872 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
873 "#CMOV_V4F32 PSEUDO!",
875 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
877 def CMOV_V2F64 : I<0, Pseudo,
878 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
879 "#CMOV_V2F64 PSEUDO!",
881 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
883 def CMOV_V2I64 : I<0, Pseudo,
884 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
885 "#CMOV_V2I64 PSEUDO!",
887 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
889 def CMOV_V8F32 : I<0, Pseudo,
890 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
891 "#CMOV_V8F32 PSEUDO!",
893 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
895 def CMOV_V4F64 : I<0, Pseudo,
896 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
897 "#CMOV_V4F64 PSEUDO!",
899 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
901 def CMOV_V4I64 : I<0, Pseudo,
902 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
903 "#CMOV_V4I64 PSEUDO!",
905 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
907 def CMOV_V8I64 : I<0, Pseudo,
908 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
909 "#CMOV_V8I64 PSEUDO!",
911 (v8i64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
913 def CMOV_V8F64 : I<0, Pseudo,
914 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
915 "#CMOV_V8F64 PSEUDO!",
917 (v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
919 def CMOV_V16F32 : I<0, Pseudo,
920 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
921 "#CMOV_V16F32 PSEUDO!",
923 (v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond,
928 //===----------------------------------------------------------------------===//
929 // DAG Pattern Matching Rules
930 //===----------------------------------------------------------------------===//
932 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
933 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
934 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
935 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
936 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
937 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
938 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
940 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
941 (ADD32ri GR32:$src1, tconstpool:$src2)>;
942 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
943 (ADD32ri GR32:$src1, tjumptable:$src2)>;
944 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
945 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
946 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
947 (ADD32ri GR32:$src1, texternalsym:$src2)>;
948 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
949 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
951 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
952 (MOV32mi addr:$dst, tglobaladdr:$src)>;
953 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
954 (MOV32mi addr:$dst, texternalsym:$src)>;
955 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
956 (MOV32mi addr:$dst, tblockaddress:$src)>;
958 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
959 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
960 // 'movabs' predicate should handle this sort of thing.
961 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
962 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
963 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
964 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
965 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
966 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
967 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
968 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
969 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
970 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
972 // In kernel code model, we can get the address of a label
973 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
974 // the MOV64ri32 should accept these.
975 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
976 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
977 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
978 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
979 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
980 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
981 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
982 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
983 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
984 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
986 // If we have small model and -static mode, it is safe to store global addresses
987 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
988 // for MOV64mi32 should handle this sort of thing.
989 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
990 (MOV64mi32 addr:$dst, tconstpool:$src)>,
991 Requires<[NearData, IsStatic]>;
992 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
993 (MOV64mi32 addr:$dst, tjumptable:$src)>,
994 Requires<[NearData, IsStatic]>;
995 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
996 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
997 Requires<[NearData, IsStatic]>;
998 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
999 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1000 Requires<[NearData, IsStatic]>;
1001 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1002 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1003 Requires<[NearData, IsStatic]>;
1007 // tls has some funny stuff here...
1008 // This corresponds to movabs $foo@tpoff, %rax
1009 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
1010 (MOV64ri32 tglobaltlsaddr :$dst)>;
1011 // This corresponds to add $foo@tpoff, %rax
1012 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1013 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1016 // Direct PC relative function call for small code model. 32-bit displacement
1017 // sign extended to 64-bit.
1018 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1019 (CALL64pcrel32 tglobaladdr:$dst)>;
1020 def : Pat<(X86call (i64 texternalsym:$dst)),
1021 (CALL64pcrel32 texternalsym:$dst)>;
1023 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1024 // can never use callee-saved registers. That is the purpose of the GR64_TC
1025 // register classes.
1027 // The only volatile register that is never used by the calling convention is
1028 // %r11. This happens when calling a vararg function with 6 arguments.
1030 // Match an X86tcret that uses less than 7 volatile registers.
1031 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1032 (X86tcret node:$ptr, node:$off), [{
1033 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1034 unsigned NumRegs = 0;
1035 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1036 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1041 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1042 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1043 Requires<[Not64BitMode]>;
1045 // FIXME: This is disabled for 32-bit PIC mode because the global base
1046 // register which is part of the address mode may be assigned a
1047 // callee-saved register.
1048 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1049 (TCRETURNmi addr:$dst, imm:$off)>,
1050 Requires<[Not64BitMode, IsNotPIC]>;
1052 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1053 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1054 Requires<[Not64BitMode]>;
1056 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1057 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1058 Requires<[Not64BitMode]>;
1060 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1061 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1062 Requires<[In64BitMode]>;
1064 // Don't fold loads into X86tcret requiring more than 6 regs.
1065 // There wouldn't be enough scratch registers for base+index.
1066 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1067 (TCRETURNmi64 addr:$dst, imm:$off)>,
1068 Requires<[In64BitMode]>;
1070 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1071 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1072 Requires<[In64BitMode]>;
1074 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1075 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1076 Requires<[In64BitMode]>;
1078 // Normal calls, with various flavors of addresses.
1079 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1080 (CALLpcrel32 tglobaladdr:$dst)>;
1081 def : Pat<(X86call (i32 texternalsym:$dst)),
1082 (CALLpcrel32 texternalsym:$dst)>;
1083 def : Pat<(X86call (i32 imm:$dst)),
1084 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1088 // TEST R,R is smaller than CMP R,0
1089 def : Pat<(X86cmp GR8:$src1, 0),
1090 (TEST8rr GR8:$src1, GR8:$src1)>;
1091 def : Pat<(X86cmp GR16:$src1, 0),
1092 (TEST16rr GR16:$src1, GR16:$src1)>;
1093 def : Pat<(X86cmp GR32:$src1, 0),
1094 (TEST32rr GR32:$src1, GR32:$src1)>;
1095 def : Pat<(X86cmp GR64:$src1, 0),
1096 (TEST64rr GR64:$src1, GR64:$src1)>;
1098 // Conditional moves with folded loads with operands swapped and conditions
1100 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1101 Instruction Inst64> {
1102 let Predicates = [HasCMov] in {
1103 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1104 (Inst16 GR16:$src2, addr:$src1)>;
1105 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1106 (Inst32 GR32:$src2, addr:$src1)>;
1107 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1108 (Inst64 GR64:$src2, addr:$src1)>;
1112 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1113 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1114 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1115 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1116 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1117 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1118 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1119 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1120 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1121 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1122 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1123 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1124 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1125 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1126 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1127 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1129 // zextload bool -> zextload byte
1130 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1131 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1132 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1133 def : Pat<(zextloadi64i1 addr:$src),
1134 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1136 // extload bool -> extload byte
1137 // When extloading from 16-bit and smaller memory locations into 64-bit
1138 // registers, use zero-extending loads so that the entire 64-bit register is
1139 // defined, avoiding partial-register updates.
1141 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1142 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1143 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1144 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1145 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1146 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1148 // For other extloads, use subregs, since the high contents of the register are
1149 // defined after an extload.
1150 def : Pat<(extloadi64i1 addr:$src),
1151 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1152 def : Pat<(extloadi64i8 addr:$src),
1153 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1154 def : Pat<(extloadi64i16 addr:$src),
1155 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1156 def : Pat<(extloadi64i32 addr:$src),
1157 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1159 // anyext. Define these to do an explicit zero-extend to
1160 // avoid partial-register updates.
1161 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1162 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1163 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1165 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1166 def : Pat<(i32 (anyext GR16:$src)),
1167 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1169 def : Pat<(i64 (anyext GR8 :$src)),
1170 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1171 def : Pat<(i64 (anyext GR16:$src)),
1172 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1173 def : Pat<(i64 (anyext GR32:$src)),
1174 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1177 // Any instruction that defines a 32-bit result leaves the high half of the
1178 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1179 // be copying from a truncate. And x86's cmov doesn't do anything if the
1180 // condition is false. But any other 32-bit operation will zero-extend
1182 def def32 : PatLeaf<(i32 GR32:$src), [{
1183 return N->getOpcode() != ISD::TRUNCATE &&
1184 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1185 N->getOpcode() != ISD::CopyFromReg &&
1186 N->getOpcode() != X86ISD::CMOV;
1189 // In the case of a 32-bit def that is known to implicitly zero-extend,
1190 // we can use a SUBREG_TO_REG.
1191 def : Pat<(i64 (zext def32:$src)),
1192 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1194 //===----------------------------------------------------------------------===//
1195 // Pattern match OR as ADD
1196 //===----------------------------------------------------------------------===//
1198 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1199 // 3-addressified into an LEA instruction to avoid copies. However, we also
1200 // want to finally emit these instructions as an or at the end of the code
1201 // generator to make the generated code easier to read. To do this, we select
1202 // into "disjoint bits" pseudo ops.
1204 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1205 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1206 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1207 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1209 APInt KnownZero0, KnownOne0;
1210 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1211 APInt KnownZero1, KnownOne1;
1212 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1213 return (~KnownZero0 & ~KnownZero1) == 0;
1217 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1218 // Try this before the selecting to OR.
1219 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1221 let isConvertibleToThreeAddress = 1,
1222 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1223 let isCommutable = 1 in {
1224 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1225 "", // orw/addw REG, REG
1226 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1227 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1228 "", // orl/addl REG, REG
1229 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1230 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1231 "", // orq/addq REG, REG
1232 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1235 // NOTE: These are order specific, we want the ri8 forms to be listed
1236 // first so that they are slightly preferred to the ri forms.
1238 def ADD16ri8_DB : I<0, Pseudo,
1239 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1240 "", // orw/addw REG, imm8
1241 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1242 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1243 "", // orw/addw REG, imm
1244 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1246 def ADD32ri8_DB : I<0, Pseudo,
1247 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1248 "", // orl/addl REG, imm8
1249 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1250 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1251 "", // orl/addl REG, imm
1252 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1255 def ADD64ri8_DB : I<0, Pseudo,
1256 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1257 "", // orq/addq REG, imm8
1258 [(set GR64:$dst, (or_is_add GR64:$src1,
1259 i64immSExt8:$src2))]>;
1260 def ADD64ri32_DB : I<0, Pseudo,
1261 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1262 "", // orq/addq REG, imm
1263 [(set GR64:$dst, (or_is_add GR64:$src1,
1264 i64immSExt32:$src2))]>;
1266 } // AddedComplexity, SchedRW
1269 //===----------------------------------------------------------------------===//
1271 //===----------------------------------------------------------------------===//
1273 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1274 // +128 doesn't, so in this special case use a sub instead of an add.
1275 def : Pat<(add GR16:$src1, 128),
1276 (SUB16ri8 GR16:$src1, -128)>;
1277 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1278 (SUB16mi8 addr:$dst, -128)>;
1280 def : Pat<(add GR32:$src1, 128),
1281 (SUB32ri8 GR32:$src1, -128)>;
1282 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1283 (SUB32mi8 addr:$dst, -128)>;
1285 def : Pat<(add GR64:$src1, 128),
1286 (SUB64ri8 GR64:$src1, -128)>;
1287 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1288 (SUB64mi8 addr:$dst, -128)>;
1290 // The same trick applies for 32-bit immediate fields in 64-bit
1292 def : Pat<(add GR64:$src1, 0x0000000080000000),
1293 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1294 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1295 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1297 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1298 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1299 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1300 // represented with a sign extension of a 8 bit constant, use that.
1302 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1306 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1307 (i32 (GetLo8XForm imm:$imm))),
1310 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1314 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1315 (i32 (GetLo32XForm imm:$imm))),
1319 // r & (2^16-1) ==> movz
1320 def : Pat<(and GR32:$src1, 0xffff),
1321 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1322 // r & (2^8-1) ==> movz
1323 def : Pat<(and GR32:$src1, 0xff),
1324 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1327 Requires<[Not64BitMode]>;
1328 // r & (2^8-1) ==> movz
1329 def : Pat<(and GR16:$src1, 0xff),
1330 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1331 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1333 Requires<[Not64BitMode]>;
1335 // r & (2^32-1) ==> movz
1336 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1337 (SUBREG_TO_REG (i64 0),
1338 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1340 // r & (2^16-1) ==> movz
1341 def : Pat<(and GR64:$src, 0xffff),
1342 (SUBREG_TO_REG (i64 0),
1343 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1345 // r & (2^8-1) ==> movz
1346 def : Pat<(and GR64:$src, 0xff),
1347 (SUBREG_TO_REG (i64 0),
1348 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1350 // r & (2^8-1) ==> movz
1351 def : Pat<(and GR32:$src1, 0xff),
1352 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1353 Requires<[In64BitMode]>;
1354 // r & (2^8-1) ==> movz
1355 def : Pat<(and GR16:$src1, 0xff),
1356 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1357 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1358 Requires<[In64BitMode]>;
1361 // sext_inreg patterns
1362 def : Pat<(sext_inreg GR32:$src, i16),
1363 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1364 def : Pat<(sext_inreg GR32:$src, i8),
1365 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1368 Requires<[Not64BitMode]>;
1370 def : Pat<(sext_inreg GR16:$src, i8),
1371 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1372 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1374 Requires<[Not64BitMode]>;
1376 def : Pat<(sext_inreg GR64:$src, i32),
1377 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1378 def : Pat<(sext_inreg GR64:$src, i16),
1379 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1380 def : Pat<(sext_inreg GR64:$src, i8),
1381 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1382 def : Pat<(sext_inreg GR32:$src, i8),
1383 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1384 Requires<[In64BitMode]>;
1385 def : Pat<(sext_inreg GR16:$src, i8),
1386 (EXTRACT_SUBREG (MOVSX32rr8
1387 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1388 Requires<[In64BitMode]>;
1390 // sext, sext_load, zext, zext_load
1391 def: Pat<(i16 (sext GR8:$src)),
1392 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1393 def: Pat<(sextloadi16i8 addr:$src),
1394 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1395 def: Pat<(i16 (zext GR8:$src)),
1396 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1397 def: Pat<(zextloadi16i8 addr:$src),
1398 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1401 def : Pat<(i16 (trunc GR32:$src)),
1402 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1403 def : Pat<(i8 (trunc GR32:$src)),
1404 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1406 Requires<[Not64BitMode]>;
1407 def : Pat<(i8 (trunc GR16:$src)),
1408 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1410 Requires<[Not64BitMode]>;
1411 def : Pat<(i32 (trunc GR64:$src)),
1412 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1413 def : Pat<(i16 (trunc GR64:$src)),
1414 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1415 def : Pat<(i8 (trunc GR64:$src)),
1416 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1417 def : Pat<(i8 (trunc GR32:$src)),
1418 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1419 Requires<[In64BitMode]>;
1420 def : Pat<(i8 (trunc GR16:$src)),
1421 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1422 Requires<[In64BitMode]>;
1424 // h-register tricks
1425 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1426 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1428 Requires<[Not64BitMode]>;
1429 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1430 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1432 Requires<[Not64BitMode]>;
1433 def : Pat<(srl GR16:$src, (i8 8)),
1436 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1439 Requires<[Not64BitMode]>;
1440 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1441 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1444 Requires<[Not64BitMode]>;
1445 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1446 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1449 Requires<[Not64BitMode]>;
1450 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1451 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1454 Requires<[Not64BitMode]>;
1455 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1456 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1459 Requires<[Not64BitMode]>;
1461 // h-register tricks.
1462 // For now, be conservative on x86-64 and use an h-register extract only if the
1463 // value is immediately zero-extended or stored, which are somewhat common
1464 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1465 // from being allocated in the same instruction as the h register, as there's
1466 // currently no way to describe this requirement to the register allocator.
1468 // h-register extract and zero-extend.
1469 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1473 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1476 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1478 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1480 Requires<[In64BitMode]>;
1481 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1482 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1485 Requires<[In64BitMode]>;
1486 def : Pat<(srl GR16:$src, (i8 8)),
1489 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1492 Requires<[In64BitMode]>;
1493 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1495 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1497 Requires<[In64BitMode]>;
1498 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1500 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1502 Requires<[In64BitMode]>;
1503 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1507 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1510 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1514 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1518 // h-register extract and store.
1519 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1522 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1524 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1527 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1529 Requires<[In64BitMode]>;
1530 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1533 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1535 Requires<[In64BitMode]>;
1538 // (shl x, 1) ==> (add x, x)
1539 // Note that if x is undef (immediate or otherwise), we could theoretically
1540 // end up with the two uses of x getting different values, producing a result
1541 // where the least significant bit is not 0. However, the probability of this
1542 // happening is considered low enough that this is officially not a
1544 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1545 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1546 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1547 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1549 // Helper imms that check if a mask doesn't change significant shift bits.
1550 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1551 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1553 // Shift amount is implicitly masked.
1554 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1555 // (shift x (and y, 31)) ==> (shift x, y)
1556 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1557 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1558 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1559 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1560 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1561 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1562 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1563 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1564 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1565 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1566 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1567 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1569 // (shift x (and y, 63)) ==> (shift x, y)
1570 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1571 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1572 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1573 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1576 defm : MaskedShiftAmountPats<shl, "SHL">;
1577 defm : MaskedShiftAmountPats<srl, "SHR">;
1578 defm : MaskedShiftAmountPats<sra, "SAR">;
1579 defm : MaskedShiftAmountPats<rotl, "ROL">;
1580 defm : MaskedShiftAmountPats<rotr, "ROR">;
1582 // (anyext (setcc_carry)) -> (setcc_carry)
1583 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1585 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1587 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1593 //===----------------------------------------------------------------------===//
1594 // EFLAGS-defining Patterns
1595 //===----------------------------------------------------------------------===//
1598 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1599 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1600 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1603 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1604 (ADD8rm GR8:$src1, addr:$src2)>;
1605 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1606 (ADD16rm GR16:$src1, addr:$src2)>;
1607 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1608 (ADD32rm GR32:$src1, addr:$src2)>;
1611 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1612 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1613 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1614 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1615 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1616 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1617 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1620 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1621 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1622 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1625 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1626 (SUB8rm GR8:$src1, addr:$src2)>;
1627 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1628 (SUB16rm GR16:$src1, addr:$src2)>;
1629 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1630 (SUB32rm GR32:$src1, addr:$src2)>;
1633 def : Pat<(sub GR8:$src1, imm:$src2),
1634 (SUB8ri GR8:$src1, imm:$src2)>;
1635 def : Pat<(sub GR16:$src1, imm:$src2),
1636 (SUB16ri GR16:$src1, imm:$src2)>;
1637 def : Pat<(sub GR32:$src1, imm:$src2),
1638 (SUB32ri GR32:$src1, imm:$src2)>;
1639 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1640 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1641 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1642 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1645 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1646 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1647 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1648 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1651 def : Pat<(mul GR16:$src1, GR16:$src2),
1652 (IMUL16rr GR16:$src1, GR16:$src2)>;
1653 def : Pat<(mul GR32:$src1, GR32:$src2),
1654 (IMUL32rr GR32:$src1, GR32:$src2)>;
1657 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1658 (IMUL16rm GR16:$src1, addr:$src2)>;
1659 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1660 (IMUL32rm GR32:$src1, addr:$src2)>;
1663 def : Pat<(mul GR16:$src1, imm:$src2),
1664 (IMUL16rri GR16:$src1, imm:$src2)>;
1665 def : Pat<(mul GR32:$src1, imm:$src2),
1666 (IMUL32rri GR32:$src1, imm:$src2)>;
1667 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1668 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1669 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1670 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1672 // reg = mul mem, imm
1673 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1674 (IMUL16rmi addr:$src1, imm:$src2)>;
1675 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1676 (IMUL32rmi addr:$src1, imm:$src2)>;
1677 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1678 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1679 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1680 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1682 // Patterns for nodes that do not produce flags, for instructions that do.
1685 def : Pat<(add GR64:$src1, GR64:$src2),
1686 (ADD64rr GR64:$src1, GR64:$src2)>;
1687 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1688 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1689 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1690 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1691 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1692 (ADD64rm GR64:$src1, addr:$src2)>;
1695 def : Pat<(sub GR64:$src1, GR64:$src2),
1696 (SUB64rr GR64:$src1, GR64:$src2)>;
1697 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1698 (SUB64rm GR64:$src1, addr:$src2)>;
1699 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1700 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1701 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1702 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1705 def : Pat<(mul GR64:$src1, GR64:$src2),
1706 (IMUL64rr GR64:$src1, GR64:$src2)>;
1707 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1708 (IMUL64rm GR64:$src1, addr:$src2)>;
1709 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1710 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1711 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1712 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1713 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1714 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1715 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1716 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1719 // Do not make INC if it is slow
1720 def : Pat<(add GR8:$src, 1),
1721 (INC8r GR8:$src)>, Requires<[NotSlowIncDec]>;
1722 def : Pat<(add GR16:$src, 1),
1723 (INC16r GR16:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1724 def : Pat<(add GR16:$src, 1),
1725 (INC64_16r GR16:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1726 def : Pat<(add GR32:$src, 1),
1727 (INC32r GR32:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1728 def : Pat<(add GR32:$src, 1),
1729 (INC64_32r GR32:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1730 def : Pat<(add GR64:$src, 1),
1731 (INC64r GR64:$src)>, Requires<[NotSlowIncDec]>;
1734 // Do not make DEC if it is slow
1735 def : Pat<(add GR8:$src, -1),
1736 (DEC8r GR8:$src)>, Requires<[NotSlowIncDec]>;
1737 def : Pat<(add GR16:$src, -1),
1738 (DEC16r GR16:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1739 def : Pat<(add GR16:$src, -1),
1740 (DEC64_16r GR16:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1741 def : Pat<(add GR32:$src, -1),
1742 (DEC32r GR32:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1743 def : Pat<(add GR32:$src, -1),
1744 (DEC64_32r GR32:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1745 def : Pat<(add GR64:$src, -1),
1746 (DEC64r GR64:$src)>, Requires<[NotSlowIncDec]>;
1749 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1750 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1751 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1752 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1755 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1756 (OR8rm GR8:$src1, addr:$src2)>;
1757 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1758 (OR16rm GR16:$src1, addr:$src2)>;
1759 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1760 (OR32rm GR32:$src1, addr:$src2)>;
1761 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1762 (OR64rm GR64:$src1, addr:$src2)>;
1765 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1766 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1767 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1768 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1769 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1770 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1771 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1772 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1773 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1774 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1775 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1778 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1779 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1780 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1781 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1784 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1785 (XOR8rm GR8:$src1, addr:$src2)>;
1786 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1787 (XOR16rm GR16:$src1, addr:$src2)>;
1788 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1789 (XOR32rm GR32:$src1, addr:$src2)>;
1790 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1791 (XOR64rm GR64:$src1, addr:$src2)>;
1794 def : Pat<(xor GR8:$src1, imm:$src2),
1795 (XOR8ri GR8:$src1, imm:$src2)>;
1796 def : Pat<(xor GR16:$src1, imm:$src2),
1797 (XOR16ri GR16:$src1, imm:$src2)>;
1798 def : Pat<(xor GR32:$src1, imm:$src2),
1799 (XOR32ri GR32:$src1, imm:$src2)>;
1800 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1801 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1802 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1803 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1804 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1805 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1806 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1807 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1810 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1811 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1812 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1813 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1816 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1817 (AND8rm GR8:$src1, addr:$src2)>;
1818 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1819 (AND16rm GR16:$src1, addr:$src2)>;
1820 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1821 (AND32rm GR32:$src1, addr:$src2)>;
1822 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1823 (AND64rm GR64:$src1, addr:$src2)>;
1826 def : Pat<(and GR8:$src1, imm:$src2),
1827 (AND8ri GR8:$src1, imm:$src2)>;
1828 def : Pat<(and GR16:$src1, imm:$src2),
1829 (AND16ri GR16:$src1, imm:$src2)>;
1830 def : Pat<(and GR32:$src1, imm:$src2),
1831 (AND32ri GR32:$src1, imm:$src2)>;
1832 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1833 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1834 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1835 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1836 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1837 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1838 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1839 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1841 // Bit scan instruction patterns to match explicit zero-undef behavior.
1842 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1843 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1844 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1845 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1846 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1847 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1849 // When HasMOVBE is enabled it is possible to get a non-legalized
1850 // register-register 16 bit bswap. This maps it to a ROL instruction.
1851 let Predicates = [HasMOVBE] in {
1852 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;