1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
24 //===----------------------------------------------------------------------===//
25 // Random Pseudo Instructions.
27 // PIC base construction. This expands to code that looks like this:
30 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
35 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
36 // a stack adjustment and the codegen must know that they may modify the stack
37 // pointer before prolog-epilog rewriting occurs.
38 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
39 // sub / add which can clobber EFLAGS.
40 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
41 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
43 [(X86callseq_start timm:$amt)]>,
44 Requires<[In32BitMode]>;
45 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
47 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
48 Requires<[In32BitMode]>;
51 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
52 // a stack adjustment and the codegen must know that they may modify the stack
53 // pointer before prolog-epilog rewriting occurs.
54 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
55 // sub / add which can clobber EFLAGS.
56 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
57 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
59 [(X86callseq_start timm:$amt)]>,
60 Requires<[In64BitMode]>;
61 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
63 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
64 Requires<[In64BitMode]>;
69 // x86-64 va_start lowering magic.
70 let usesCustomInserter = 1 in {
71 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
74 i64imm:$regsavefi, i64imm:$offset,
76 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
77 [(X86vastart_save_xmm_regs GR8:$al,
81 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
82 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
83 // one go. Touching the stack at 4K increments is necessary to ensure that the
84 // guard pages used by the OS virtual memory manager are allocated in correct
86 // The main point of having separate instruction are extra unmodelled effects
87 // (compared to ordinary calls) like stack pointer change.
89 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
90 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
91 "# dynamic stack allocation",
97 //===----------------------------------------------------------------------===//
98 // EH Pseudo Instructions
100 let isTerminator = 1, isReturn = 1, isBarrier = 1,
101 hasCtrlDep = 1, isCodeGenOnly = 1 in {
102 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
103 "ret\t#eh_return, addr: $addr",
104 [(X86ehret GR32:$addr)]>;
108 let isTerminator = 1, isReturn = 1, isBarrier = 1,
109 hasCtrlDep = 1, isCodeGenOnly = 1 in {
110 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
111 "ret\t#eh_return, addr: $addr",
112 [(X86ehret GR64:$addr)]>;
116 //===----------------------------------------------------------------------===//
117 // Alias Instructions
118 //===----------------------------------------------------------------------===//
120 // Alias instructions that map movr0 to xor.
121 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
122 // FIXME: Set encoding to pseudo.
123 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
124 isCodeGenOnly = 1 in {
125 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
126 [(set GR8:$dst, 0)]>;
128 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
129 // encoding and avoids a partial-register update sometimes, but doing so
130 // at isel time interferes with rematerialization in the current register
131 // allocator. For now, this is rewritten when the instruction is lowered
133 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
135 [(set GR16:$dst, 0)]>, OpSize;
137 // FIXME: Set encoding to pseudo.
138 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
139 [(set GR32:$dst, 0)]>;
142 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
143 // smaller encoding, but doing so at isel time interferes with rematerialization
144 // in the current register allocator. For now, this is rewritten when the
145 // instruction is lowered to an MCInst.
146 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
147 // when we have a better way to specify isel priority.
149 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
150 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
151 [(set GR64:$dst, 0)]>;
153 // Materialize i64 constant where top 32-bits are zero. This could theoretically
154 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
155 // that would make it more difficult to rematerialize.
156 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
157 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
158 "", [(set GR64:$dst, i64immZExt32:$src)]>;
161 // Use sbb to materialize carry flag into a GPR.
162 // FIXME: This are pseudo ops that should be replaced with Pat<> patterns.
163 // However, Pat<> can't replicate the destination reg into the inputs of the
165 // FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces
167 let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
168 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
169 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
171 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
175 //===----------------------------------------------------------------------===//
176 // String Pseudo Instructions
178 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
179 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
180 [(X86rep_movs i8)]>, REP;
181 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
182 [(X86rep_movs i16)]>, REP, OpSize;
183 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
184 [(X86rep_movs i32)]>, REP;
187 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
188 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
189 [(X86rep_movs i64)]>, REP;
192 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
193 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
194 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
195 [(X86rep_stos i8)]>, REP;
196 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
197 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
198 [(X86rep_stos i16)]>, REP, OpSize;
199 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
200 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
201 [(X86rep_stos i32)]>, REP;
203 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
204 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
205 [(X86rep_stos i64)]>, REP;
208 //===----------------------------------------------------------------------===//
209 // Thread Local Storage Instructions
213 // All calls clobber the non-callee saved registers. ESP is marked as
214 // a use to prevent stack-pointer assignments that appear immediately
215 // before calls from potentially appearing dead.
216 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
217 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
218 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
219 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
221 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
223 "call\t___tls_get_addr@PLT",
224 [(X86tlsaddr tls32addr:$sym)]>,
225 Requires<[In32BitMode]>;
227 // All calls clobber the non-callee saved registers. RSP is marked as
228 // a use to prevent stack-pointer assignments that appear immediately
229 // before calls from potentially appearing dead.
230 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
231 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
232 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
233 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
234 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
236 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
238 "leaq\t$sym(%rip), %rdi; "
241 "call\t__tls_get_addr@PLT",
242 [(X86tlsaddr tls64addr:$sym)]>,
243 Requires<[In64BitMode]>;
245 // Darwin TLS Support
246 // For i386, the address of the thunk is passed on the stack, on return the
247 // address of the variable is in %eax. %ecx is trashed during the function
248 // call. All other registers are preserved.
249 let Defs = [EAX, ECX],
251 usesCustomInserter = 1 in
252 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
254 [(X86TLSCall addr:$sym)]>,
255 Requires<[In32BitMode]>;
257 // For x86_64, the address of the thunk is passed in %rdi, on return
258 // the address of the variable is in %rax. All other registers are preserved.
261 usesCustomInserter = 1 in
262 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
264 [(X86TLSCall addr:$sym)]>,
265 Requires<[In64BitMode]>;
267 //===----------------------------------------------------------------------===//
268 // Atomic Instruction Pseudo Instructions
269 //===----------------------------------------------------------------------===//
271 // Atomic exchange, and, or, xor
272 let Constraints = "$val = $dst", Defs = [EFLAGS],
273 usesCustomInserter = 1 in {
275 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
277 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
278 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
280 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
281 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
283 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
284 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
285 "#ATOMNAND8 PSEUDO!",
286 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
288 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
289 "#ATOMAND16 PSEUDO!",
290 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
291 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
293 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
294 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
295 "#ATOMXOR16 PSEUDO!",
296 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
297 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
298 "#ATOMNAND16 PSEUDO!",
299 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
300 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
301 "#ATOMMIN16 PSEUDO!",
302 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
303 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
304 "#ATOMMAX16 PSEUDO!",
305 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
306 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
307 "#ATOMUMIN16 PSEUDO!",
308 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
309 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
310 "#ATOMUMAX16 PSEUDO!",
311 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
314 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
315 "#ATOMAND32 PSEUDO!",
316 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
317 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
319 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
320 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
321 "#ATOMXOR32 PSEUDO!",
322 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
323 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
324 "#ATOMNAND32 PSEUDO!",
325 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
326 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
327 "#ATOMMIN32 PSEUDO!",
328 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
329 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
330 "#ATOMMAX32 PSEUDO!",
331 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
332 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
333 "#ATOMUMIN32 PSEUDO!",
334 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
335 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
336 "#ATOMUMAX32 PSEUDO!",
337 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
341 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
342 "#ATOMAND64 PSEUDO!",
343 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
344 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
346 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
347 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
348 "#ATOMXOR64 PSEUDO!",
349 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
350 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
351 "#ATOMNAND64 PSEUDO!",
352 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
353 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
354 "#ATOMMIN64 PSEUDO!",
355 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
356 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
357 "#ATOMMAX64 PSEUDO!",
358 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
359 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
360 "#ATOMUMIN64 PSEUDO!",
361 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
362 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
363 "#ATOMUMAX64 PSEUDO!",
364 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
367 let Constraints = "$val1 = $dst1, $val2 = $dst2",
368 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
369 Uses = [EAX, EBX, ECX, EDX],
370 mayLoad = 1, mayStore = 1,
371 usesCustomInserter = 1 in {
372 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
373 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
374 "#ATOMAND6432 PSEUDO!", []>;
375 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
376 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
377 "#ATOMOR6432 PSEUDO!", []>;
378 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
379 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
380 "#ATOMXOR6432 PSEUDO!", []>;
381 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
382 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
383 "#ATOMNAND6432 PSEUDO!", []>;
384 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
385 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
386 "#ATOMADD6432 PSEUDO!", []>;
387 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
388 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
389 "#ATOMSUB6432 PSEUDO!", []>;
390 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
391 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
392 "#ATOMSWAP6432 PSEUDO!", []>;
395 //===----------------------------------------------------------------------===//
396 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
397 //===----------------------------------------------------------------------===//
399 // FIXME: Use normal instructions and add lock prefix dynamically.
403 // TODO: Get this to fold the constant into the instruction.
404 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
406 "or{l}\t{$zero, $dst|$dst, $zero}",
407 []>, Requires<[In32BitMode]>, LOCK;
409 let hasSideEffects = 1 in
410 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
412 [(X86MemBarrier)]>, Requires<[HasSSE2]>;
414 // TODO: Get this to fold the constant into the instruction.
415 let hasSideEffects = 1, Defs = [ESP] in
416 def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
418 "or{q}\t{$zero, (%rsp)|(%rsp), $zero}",
419 [(X86MemBarrierNoSSE GR64:$zero)]>,
420 Requires<[In64BitMode]>, LOCK;
423 // Optimized codegen when the non-memory output is not used.
424 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
425 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
427 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
428 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
430 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
431 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
433 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
434 def LOCK_ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
436 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
438 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
440 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
441 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
443 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
444 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
446 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
447 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
448 (ins i64mem:$dst, i64i32imm :$src2),
450 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
452 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
454 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
455 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
457 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
458 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
459 (ins i64mem:$dst, i64i8imm :$src2),
461 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
463 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
465 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
466 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
468 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
469 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
471 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
472 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
474 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
477 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
479 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
480 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
482 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
483 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
485 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
486 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
487 (ins i64mem:$dst, i64i32imm:$src2),
489 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
492 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
494 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
495 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
497 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
498 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
499 (ins i64mem:$dst, i64i8imm :$src2),
501 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
503 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
505 "inc{b}\t$dst", []>, LOCK;
506 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
508 "inc{w}\t$dst", []>, OpSize, LOCK;
509 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
511 "inc{l}\t$dst", []>, LOCK;
512 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
514 "inc{q}\t$dst", []>, LOCK;
516 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
518 "dec{b}\t$dst", []>, LOCK;
519 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
521 "dec{w}\t$dst", []>, OpSize, LOCK;
522 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
524 "dec{l}\t$dst", []>, LOCK;
525 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
527 "dec{q}\t$dst", []>, LOCK;
530 // Atomic compare and swap.
531 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
532 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
535 [(X86cas8 addr:$ptr)]>, TB, LOCK;
537 let Defs = [AL, EFLAGS], Uses = [AL] in {
538 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
540 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
541 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
544 let Defs = [AX, EFLAGS], Uses = [AX] in {
545 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
547 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
548 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
551 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
552 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
554 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
555 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
558 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
559 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
561 "cmpxchgq\t$swap,$ptr",
562 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
565 // Atomic exchange and add
566 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
567 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
569 "xadd{b}\t{$val, $ptr|$ptr, $val}",
570 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
572 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
574 "xadd{w}\t{$val, $ptr|$ptr, $val}",
575 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
577 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
579 "xadd{l}\t{$val, $ptr|$ptr, $val}",
580 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
582 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
585 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
589 //===----------------------------------------------------------------------===//
590 // Conditional Move Pseudo Instructions.
591 //===----------------------------------------------------------------------===//
594 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
595 // instruction selection into a branch sequence.
596 let Uses = [EFLAGS], usesCustomInserter = 1 in {
597 def CMOV_FR32 : I<0, Pseudo,
598 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
599 "#CMOV_FR32 PSEUDO!",
600 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
602 def CMOV_FR64 : I<0, Pseudo,
603 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
604 "#CMOV_FR64 PSEUDO!",
605 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
607 def CMOV_V4F32 : I<0, Pseudo,
608 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
609 "#CMOV_V4F32 PSEUDO!",
611 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
613 def CMOV_V2F64 : I<0, Pseudo,
614 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
615 "#CMOV_V2F64 PSEUDO!",
617 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
619 def CMOV_V2I64 : I<0, Pseudo,
620 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
621 "#CMOV_V2I64 PSEUDO!",
623 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
628 //===----------------------------------------------------------------------===//
629 // DAG Pattern Matching Rules
630 //===----------------------------------------------------------------------===//
632 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
633 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
634 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
635 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
636 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
637 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
638 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
640 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
641 (ADD32ri GR32:$src1, tconstpool:$src2)>;
642 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
643 (ADD32ri GR32:$src1, tjumptable:$src2)>;
644 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
645 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
646 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
647 (ADD32ri GR32:$src1, texternalsym:$src2)>;
648 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
649 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
651 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
652 (MOV32mi addr:$dst, tglobaladdr:$src)>;
653 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
654 (MOV32mi addr:$dst, texternalsym:$src)>;
655 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
656 (MOV32mi addr:$dst, tblockaddress:$src)>;
660 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
661 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
662 // 'movabs' predicate should handle this sort of thing.
663 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
664 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
665 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
666 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
667 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
668 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
669 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
670 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
671 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
672 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
674 // In static codegen with small code model, we can get the address of a label
675 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
676 // the MOV64ri64i32 should accept these.
677 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
678 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
679 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
680 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
681 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
682 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
683 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
684 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
685 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
686 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
688 // In kernel code model, we can get the address of a label
689 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
690 // the MOV64ri32 should accept these.
691 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
692 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
693 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
694 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
695 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
696 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
697 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
698 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
699 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
700 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
702 // If we have small model and -static mode, it is safe to store global addresses
703 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
704 // for MOV64mi32 should handle this sort of thing.
705 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
706 (MOV64mi32 addr:$dst, tconstpool:$src)>,
707 Requires<[NearData, IsStatic]>;
708 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
709 (MOV64mi32 addr:$dst, tjumptable:$src)>,
710 Requires<[NearData, IsStatic]>;
711 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
712 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
713 Requires<[NearData, IsStatic]>;
714 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
715 (MOV64mi32 addr:$dst, texternalsym:$src)>,
716 Requires<[NearData, IsStatic]>;
717 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
718 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
719 Requires<[NearData, IsStatic]>;
725 // tls has some funny stuff here...
726 // This corresponds to movabs $foo@tpoff, %rax
727 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
728 (MOV64ri tglobaltlsaddr :$dst)>;
729 // This corresponds to add $foo@tpoff, %rax
730 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
731 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
732 // This corresponds to mov foo@tpoff(%rbx), %eax
733 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
734 (MOV64rm tglobaltlsaddr :$dst)>;
737 // Direct PC relative function call for small code model. 32-bit displacement
738 // sign extended to 64-bit.
739 def : Pat<(X86call (i64 tglobaladdr:$dst)),
740 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
741 def : Pat<(X86call (i64 texternalsym:$dst)),
742 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
744 def : Pat<(X86call (i64 tglobaladdr:$dst)),
745 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
746 def : Pat<(X86call (i64 texternalsym:$dst)),
747 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
750 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
751 (TCRETURNri GR32_TC:$dst, imm:$off)>,
752 Requires<[In32BitMode]>;
754 // FIXME: This is disabled for 32-bit PIC mode because the global base
755 // register which is part of the address mode may be assigned a
756 // callee-saved register.
757 def : Pat<(X86tcret (load addr:$dst), imm:$off),
758 (TCRETURNmi addr:$dst, imm:$off)>,
759 Requires<[In32BitMode, IsNotPIC]>;
761 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
762 (TCRETURNdi texternalsym:$dst, imm:$off)>,
763 Requires<[In32BitMode]>;
765 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
766 (TCRETURNdi texternalsym:$dst, imm:$off)>,
767 Requires<[In32BitMode]>;
769 def : Pat<(X86tcret GR64_TC:$dst, imm:$off),
770 (TCRETURNri64 GR64_TC:$dst, imm:$off)>,
771 Requires<[In64BitMode]>;
773 def : Pat<(X86tcret (load addr:$dst), imm:$off),
774 (TCRETURNmi64 addr:$dst, imm:$off)>,
775 Requires<[In64BitMode]>;
777 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
778 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
779 Requires<[In64BitMode]>;
781 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
782 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
783 Requires<[In64BitMode]>;
785 // Normal calls, with various flavors of addresses.
786 def : Pat<(X86call (i32 tglobaladdr:$dst)),
787 (CALLpcrel32 tglobaladdr:$dst)>;
788 def : Pat<(X86call (i32 texternalsym:$dst)),
789 (CALLpcrel32 texternalsym:$dst)>;
790 def : Pat<(X86call (i32 imm:$dst)),
791 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
793 // X86 specific add which produces a flag.
794 def : Pat<(addc GR32:$src1, GR32:$src2),
795 (ADD32rr GR32:$src1, GR32:$src2)>;
796 def : Pat<(addc GR32:$src1, (load addr:$src2)),
797 (ADD32rm GR32:$src1, addr:$src2)>;
798 def : Pat<(addc GR32:$src1, imm:$src2),
799 (ADD32ri GR32:$src1, imm:$src2)>;
800 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
801 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
803 def : Pat<(addc GR64:$src1, GR64:$src2),
804 (ADD64rr GR64:$src1, GR64:$src2)>;
805 def : Pat<(addc GR64:$src1, (load addr:$src2)),
806 (ADD64rm GR64:$src1, addr:$src2)>;
807 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
808 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
809 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
810 (ADD64ri32 GR64:$src1, imm:$src2)>;
812 def : Pat<(subc GR32:$src1, GR32:$src2),
813 (SUB32rr GR32:$src1, GR32:$src2)>;
814 def : Pat<(subc GR32:$src1, (load addr:$src2)),
815 (SUB32rm GR32:$src1, addr:$src2)>;
816 def : Pat<(subc GR32:$src1, imm:$src2),
817 (SUB32ri GR32:$src1, imm:$src2)>;
818 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
819 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
821 def : Pat<(subc GR64:$src1, GR64:$src2),
822 (SUB64rr GR64:$src1, GR64:$src2)>;
823 def : Pat<(subc GR64:$src1, (load addr:$src2)),
824 (SUB64rm GR64:$src1, addr:$src2)>;
825 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
826 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
827 def : Pat<(subc GR64:$src1, imm:$src2),
828 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
832 // TEST R,R is smaller than CMP R,0
833 def : Pat<(X86cmp GR8:$src1, 0),
834 (TEST8rr GR8:$src1, GR8:$src1)>;
835 def : Pat<(X86cmp GR16:$src1, 0),
836 (TEST16rr GR16:$src1, GR16:$src1)>;
837 def : Pat<(X86cmp GR32:$src1, 0),
838 (TEST32rr GR32:$src1, GR32:$src1)>;
839 def : Pat<(X86cmp GR64:$src1, 0),
840 (TEST64rr GR64:$src1, GR64:$src1)>;
842 // Conditional moves with folded loads with operands swapped and conditions
844 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
845 (CMOVAE16rm GR16:$src2, addr:$src1)>;
846 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
847 (CMOVAE32rm GR32:$src2, addr:$src1)>;
848 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
849 (CMOVB16rm GR16:$src2, addr:$src1)>;
850 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
851 (CMOVB32rm GR32:$src2, addr:$src1)>;
852 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
853 (CMOVNE16rm GR16:$src2, addr:$src1)>;
854 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
855 (CMOVNE32rm GR32:$src2, addr:$src1)>;
856 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
857 (CMOVE16rm GR16:$src2, addr:$src1)>;
858 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
859 (CMOVE32rm GR32:$src2, addr:$src1)>;
860 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
861 (CMOVA16rm GR16:$src2, addr:$src1)>;
862 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
863 (CMOVA32rm GR32:$src2, addr:$src1)>;
864 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
865 (CMOVBE16rm GR16:$src2, addr:$src1)>;
866 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
867 (CMOVBE32rm GR32:$src2, addr:$src1)>;
868 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
869 (CMOVGE16rm GR16:$src2, addr:$src1)>;
870 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
871 (CMOVGE32rm GR32:$src2, addr:$src1)>;
872 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
873 (CMOVL16rm GR16:$src2, addr:$src1)>;
874 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
875 (CMOVL32rm GR32:$src2, addr:$src1)>;
876 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
877 (CMOVG16rm GR16:$src2, addr:$src1)>;
878 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
879 (CMOVG32rm GR32:$src2, addr:$src1)>;
880 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
881 (CMOVLE16rm GR16:$src2, addr:$src1)>;
882 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
883 (CMOVLE32rm GR32:$src2, addr:$src1)>;
884 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
885 (CMOVNP16rm GR16:$src2, addr:$src1)>;
886 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
887 (CMOVNP32rm GR32:$src2, addr:$src1)>;
888 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
889 (CMOVP16rm GR16:$src2, addr:$src1)>;
890 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
891 (CMOVP32rm GR32:$src2, addr:$src1)>;
892 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
893 (CMOVNS16rm GR16:$src2, addr:$src1)>;
894 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
895 (CMOVNS32rm GR32:$src2, addr:$src1)>;
896 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
897 (CMOVS16rm GR16:$src2, addr:$src1)>;
898 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
899 (CMOVS32rm GR32:$src2, addr:$src1)>;
900 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
901 (CMOVNO16rm GR16:$src2, addr:$src1)>;
902 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
903 (CMOVNO32rm GR32:$src2, addr:$src1)>;
904 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
905 (CMOVO16rm GR16:$src2, addr:$src1)>;
906 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
907 (CMOVO32rm GR32:$src2, addr:$src1)>;
909 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
910 (CMOVAE64rm GR64:$src2, addr:$src1)>;
911 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
912 (CMOVB64rm GR64:$src2, addr:$src1)>;
913 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
914 (CMOVNE64rm GR64:$src2, addr:$src1)>;
915 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
916 (CMOVE64rm GR64:$src2, addr:$src1)>;
917 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
918 (CMOVA64rm GR64:$src2, addr:$src1)>;
919 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
920 (CMOVBE64rm GR64:$src2, addr:$src1)>;
921 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
922 (CMOVGE64rm GR64:$src2, addr:$src1)>;
923 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
924 (CMOVL64rm GR64:$src2, addr:$src1)>;
925 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
926 (CMOVG64rm GR64:$src2, addr:$src1)>;
927 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
928 (CMOVLE64rm GR64:$src2, addr:$src1)>;
929 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
930 (CMOVNP64rm GR64:$src2, addr:$src1)>;
931 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
932 (CMOVP64rm GR64:$src2, addr:$src1)>;
933 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
934 (CMOVNS64rm GR64:$src2, addr:$src1)>;
935 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
936 (CMOVS64rm GR64:$src2, addr:$src1)>;
937 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
938 (CMOVNO64rm GR64:$src2, addr:$src1)>;
939 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
940 (CMOVO64rm GR64:$src2, addr:$src1)>;
943 // zextload bool -> zextload byte
944 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
945 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
946 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
947 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
949 // extload bool -> extload byte
950 // When extloading from 16-bit and smaller memory locations into 64-bit
951 // registers, use zero-extending loads so that the entire 64-bit register is
952 // defined, avoiding partial-register updates.
954 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
955 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
956 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
957 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
958 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
959 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
961 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
962 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
963 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
964 // For other extloads, use subregs, since the high contents of the register are
965 // defined after an extload.
966 def : Pat<(extloadi64i32 addr:$src),
967 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
970 // anyext. Define these to do an explicit zero-extend to
971 // avoid partial-register updates.
972 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
973 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
975 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
976 def : Pat<(i32 (anyext GR16:$src)),
977 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
979 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
980 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
981 def : Pat<(i64 (anyext GR32:$src)),
982 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
985 // Any instruction that defines a 32-bit result leaves the high half of the
986 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
987 // be copying from a truncate. And x86's cmov doesn't do anything if the
988 // condition is false. But any other 32-bit operation will zero-extend
990 def def32 : PatLeaf<(i32 GR32:$src), [{
991 return N->getOpcode() != ISD::TRUNCATE &&
992 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
993 N->getOpcode() != ISD::CopyFromReg &&
994 N->getOpcode() != X86ISD::CMOV;
997 // In the case of a 32-bit def that is known to implicitly zero-extend,
998 // we can use a SUBREG_TO_REG.
999 def : Pat<(i64 (zext def32:$src)),
1000 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1002 //===----------------------------------------------------------------------===//
1004 //===----------------------------------------------------------------------===//
1006 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1007 // +128 doesn't, so in this special case use a sub instead of an add.
1008 def : Pat<(add GR16:$src1, 128),
1009 (SUB16ri8 GR16:$src1, -128)>;
1010 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1011 (SUB16mi8 addr:$dst, -128)>;
1013 def : Pat<(add GR32:$src1, 128),
1014 (SUB32ri8 GR32:$src1, -128)>;
1015 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1016 (SUB32mi8 addr:$dst, -128)>;
1018 def : Pat<(add GR64:$src1, 128),
1019 (SUB64ri8 GR64:$src1, -128)>;
1020 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1021 (SUB64mi8 addr:$dst, -128)>;
1023 // The same trick applies for 32-bit immediate fields in 64-bit
1025 def : Pat<(add GR64:$src1, 0x0000000080000000),
1026 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1027 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1028 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1030 // Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
1031 // has an immediate with at least 32 bits of leading zeros, to avoid needing to
1032 // materialize that immediate in a register first.
1033 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1037 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1038 (i32 (GetLo32XForm imm:$imm))),
1042 // r & (2^16-1) ==> movz
1043 def : Pat<(and GR32:$src1, 0xffff),
1044 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1045 // r & (2^8-1) ==> movz
1046 def : Pat<(and GR32:$src1, 0xff),
1047 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1050 Requires<[In32BitMode]>;
1051 // r & (2^8-1) ==> movz
1052 def : Pat<(and GR16:$src1, 0xff),
1053 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
1056 Requires<[In32BitMode]>;
1058 // r & (2^32-1) ==> movz
1059 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1060 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1061 // r & (2^16-1) ==> movz
1062 def : Pat<(and GR64:$src, 0xffff),
1063 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1064 // r & (2^8-1) ==> movz
1065 def : Pat<(and GR64:$src, 0xff),
1066 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1067 // r & (2^8-1) ==> movz
1068 def : Pat<(and GR32:$src1, 0xff),
1069 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1070 Requires<[In64BitMode]>;
1071 // r & (2^8-1) ==> movz
1072 def : Pat<(and GR16:$src1, 0xff),
1073 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>,
1074 Requires<[In64BitMode]>;
1077 // sext_inreg patterns
1078 def : Pat<(sext_inreg GR32:$src, i16),
1079 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1080 def : Pat<(sext_inreg GR32:$src, i8),
1081 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1084 Requires<[In32BitMode]>;
1085 def : Pat<(sext_inreg GR16:$src, i8),
1086 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1089 Requires<[In32BitMode]>;
1091 def : Pat<(sext_inreg GR64:$src, i32),
1092 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1093 def : Pat<(sext_inreg GR64:$src, i16),
1094 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1095 def : Pat<(sext_inreg GR64:$src, i8),
1096 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1097 def : Pat<(sext_inreg GR32:$src, i8),
1098 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1099 Requires<[In64BitMode]>;
1100 def : Pat<(sext_inreg GR16:$src, i8),
1101 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>,
1102 Requires<[In64BitMode]>;
1106 def : Pat<(i16 (trunc GR32:$src)),
1107 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1108 def : Pat<(i8 (trunc GR32:$src)),
1109 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1111 Requires<[In32BitMode]>;
1112 def : Pat<(i8 (trunc GR16:$src)),
1113 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1115 Requires<[In32BitMode]>;
1116 def : Pat<(i32 (trunc GR64:$src)),
1117 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1118 def : Pat<(i16 (trunc GR64:$src)),
1119 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1120 def : Pat<(i8 (trunc GR64:$src)),
1121 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1122 def : Pat<(i8 (trunc GR32:$src)),
1123 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1124 Requires<[In64BitMode]>;
1125 def : Pat<(i8 (trunc GR16:$src)),
1126 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1127 Requires<[In64BitMode]>;
1129 // h-register tricks
1130 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1131 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1133 Requires<[In32BitMode]>;
1134 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1135 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1137 Requires<[In32BitMode]>;
1138 def : Pat<(srl GR16:$src, (i8 8)),
1141 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1144 Requires<[In32BitMode]>;
1145 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1146 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1149 Requires<[In32BitMode]>;
1150 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1151 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1154 Requires<[In32BitMode]>;
1155 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1156 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1159 Requires<[In32BitMode]>;
1160 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1161 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1164 Requires<[In32BitMode]>;
1166 // h-register tricks.
1167 // For now, be conservative on x86-64 and use an h-register extract only if the
1168 // value is immediately zero-extended or stored, which are somewhat common
1169 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1170 // from being allocated in the same instruction as the h register, as there's
1171 // currently no way to describe this requirement to the register allocator.
1173 // h-register extract and zero-extend.
1174 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1178 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1181 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1183 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1185 Requires<[In64BitMode]>;
1186 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1187 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1190 Requires<[In64BitMode]>;
1191 def : Pat<(srl GR16:$src, (i8 8)),
1194 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1197 Requires<[In64BitMode]>;
1198 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1200 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1202 Requires<[In64BitMode]>;
1203 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1205 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1207 Requires<[In64BitMode]>;
1208 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1212 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1215 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1219 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1223 // h-register extract and store.
1224 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1227 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1229 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1232 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1234 Requires<[In64BitMode]>;
1235 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1238 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1240 Requires<[In64BitMode]>;
1243 // (shl x, 1) ==> (add x, x)
1244 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1245 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1246 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1247 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1249 // (shl x (and y, 31)) ==> (shl x, y)
1250 def : Pat<(shl GR8:$src1, (and CL, 31)),
1251 (SHL8rCL GR8:$src1)>;
1252 def : Pat<(shl GR16:$src1, (and CL, 31)),
1253 (SHL16rCL GR16:$src1)>;
1254 def : Pat<(shl GR32:$src1, (and CL, 31)),
1255 (SHL32rCL GR32:$src1)>;
1256 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1257 (SHL8mCL addr:$dst)>;
1258 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1259 (SHL16mCL addr:$dst)>;
1260 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1261 (SHL32mCL addr:$dst)>;
1263 def : Pat<(srl GR8:$src1, (and CL, 31)),
1264 (SHR8rCL GR8:$src1)>;
1265 def : Pat<(srl GR16:$src1, (and CL, 31)),
1266 (SHR16rCL GR16:$src1)>;
1267 def : Pat<(srl GR32:$src1, (and CL, 31)),
1268 (SHR32rCL GR32:$src1)>;
1269 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1270 (SHR8mCL addr:$dst)>;
1271 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1272 (SHR16mCL addr:$dst)>;
1273 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1274 (SHR32mCL addr:$dst)>;
1276 def : Pat<(sra GR8:$src1, (and CL, 31)),
1277 (SAR8rCL GR8:$src1)>;
1278 def : Pat<(sra GR16:$src1, (and CL, 31)),
1279 (SAR16rCL GR16:$src1)>;
1280 def : Pat<(sra GR32:$src1, (and CL, 31)),
1281 (SAR32rCL GR32:$src1)>;
1282 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1283 (SAR8mCL addr:$dst)>;
1284 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1285 (SAR16mCL addr:$dst)>;
1286 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1287 (SAR32mCL addr:$dst)>;
1289 // (shl x (and y, 63)) ==> (shl x, y)
1290 def : Pat<(shl GR64:$src1, (and CL, 63)),
1291 (SHL64rCL GR64:$src1)>;
1292 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1293 (SHL64mCL addr:$dst)>;
1295 def : Pat<(srl GR64:$src1, (and CL, 63)),
1296 (SHR64rCL GR64:$src1)>;
1297 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1298 (SHR64mCL addr:$dst)>;
1300 def : Pat<(sra GR64:$src1, (and CL, 63)),
1301 (SAR64rCL GR64:$src1)>;
1302 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1303 (SAR64mCL addr:$dst)>;
1306 // (anyext (setcc_carry)) -> (setcc_carry)
1307 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1309 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1311 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1314 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1315 let AddedComplexity = 5 in { // Try this before the selecting to OR
1316 def : Pat<(or_is_add GR16:$src1, imm:$src2),
1317 (ADD16ri GR16:$src1, imm:$src2)>;
1318 def : Pat<(or_is_add GR32:$src1, imm:$src2),
1319 (ADD32ri GR32:$src1, imm:$src2)>;
1320 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
1321 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1322 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
1323 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1324 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
1325 (ADD16rr GR16:$src1, GR16:$src2)>;
1326 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
1327 (ADD32rr GR32:$src1, GR32:$src2)>;
1328 def : Pat<(or_is_add GR64:$src1, i64immSExt8:$src2),
1329 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1330 def : Pat<(or_is_add GR64:$src1, i64immSExt32:$src2),
1331 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1332 def : Pat<(or_is_add GR64:$src1, GR64:$src2),
1333 (ADD64rr GR64:$src1, GR64:$src2)>;
1334 } // AddedComplexity
1336 //===----------------------------------------------------------------------===//
1337 // EFLAGS-defining Patterns
1338 //===----------------------------------------------------------------------===//
1341 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1342 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1343 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1346 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1347 (ADD8rm GR8:$src1, addr:$src2)>;
1348 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1349 (ADD16rm GR16:$src1, addr:$src2)>;
1350 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1351 (ADD32rm GR32:$src1, addr:$src2)>;
1354 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1355 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1356 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1357 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1358 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1359 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1360 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1363 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1364 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1365 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1368 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1369 (SUB8rm GR8:$src1, addr:$src2)>;
1370 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1371 (SUB16rm GR16:$src1, addr:$src2)>;
1372 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1373 (SUB32rm GR32:$src1, addr:$src2)>;
1376 def : Pat<(sub GR8:$src1, imm:$src2),
1377 (SUB8ri GR8:$src1, imm:$src2)>;
1378 def : Pat<(sub GR16:$src1, imm:$src2),
1379 (SUB16ri GR16:$src1, imm:$src2)>;
1380 def : Pat<(sub GR32:$src1, imm:$src2),
1381 (SUB32ri GR32:$src1, imm:$src2)>;
1382 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1383 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1384 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1385 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1388 def : Pat<(mul GR16:$src1, GR16:$src2),
1389 (IMUL16rr GR16:$src1, GR16:$src2)>;
1390 def : Pat<(mul GR32:$src1, GR32:$src2),
1391 (IMUL32rr GR32:$src1, GR32:$src2)>;
1394 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1395 (IMUL16rm GR16:$src1, addr:$src2)>;
1396 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1397 (IMUL32rm GR32:$src1, addr:$src2)>;
1400 def : Pat<(mul GR16:$src1, imm:$src2),
1401 (IMUL16rri GR16:$src1, imm:$src2)>;
1402 def : Pat<(mul GR32:$src1, imm:$src2),
1403 (IMUL32rri GR32:$src1, imm:$src2)>;
1404 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1405 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1406 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1407 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1409 // reg = mul mem, imm
1410 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1411 (IMUL16rmi addr:$src1, imm:$src2)>;
1412 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1413 (IMUL32rmi addr:$src1, imm:$src2)>;
1414 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1415 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1416 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1417 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1419 // Optimize multiply by 2 with EFLAGS result.
1420 let AddedComplexity = 2 in {
1421 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
1422 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
1425 // Patterns for nodes that do not produce flags, for instructions that do.
1428 def : Pat<(add GR64:$src1, GR64:$src2),
1429 (ADD64rr GR64:$src1, GR64:$src2)>;
1430 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1431 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1432 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1433 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1434 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1435 (ADD64rm GR64:$src1, addr:$src2)>;
1438 def : Pat<(sub GR64:$src1, GR64:$src2),
1439 (SUB64rr GR64:$src1, GR64:$src2)>;
1440 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1441 (SUB64rm GR64:$src1, addr:$src2)>;
1442 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1443 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1444 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1445 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1448 def : Pat<(mul GR64:$src1, GR64:$src2),
1449 (IMUL64rr GR64:$src1, GR64:$src2)>;
1450 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1451 (IMUL64rm GR64:$src1, addr:$src2)>;
1452 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1453 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1454 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1455 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1456 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1457 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1458 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1459 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1462 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1463 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1464 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1465 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1466 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1467 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1470 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1471 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1472 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1473 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1474 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1475 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1478 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1479 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1480 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1481 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1484 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1485 (OR8rm GR8:$src1, addr:$src2)>;
1486 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1487 (OR16rm GR16:$src1, addr:$src2)>;
1488 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1489 (OR32rm GR32:$src1, addr:$src2)>;
1490 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1491 (OR64rm GR64:$src1, addr:$src2)>;
1494 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1495 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1496 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1497 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1498 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1499 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1500 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1501 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1502 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1503 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1504 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1507 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1508 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1509 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1510 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1513 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1514 (XOR8rm GR8:$src1, addr:$src2)>;
1515 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1516 (XOR16rm GR16:$src1, addr:$src2)>;
1517 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1518 (XOR32rm GR32:$src1, addr:$src2)>;
1519 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1520 (XOR64rm GR64:$src1, addr:$src2)>;
1523 def : Pat<(xor GR8:$src1, imm:$src2),
1524 (XOR8ri GR8:$src1, imm:$src2)>;
1525 def : Pat<(xor GR16:$src1, imm:$src2),
1526 (XOR16ri GR16:$src1, imm:$src2)>;
1527 def : Pat<(xor GR32:$src1, imm:$src2),
1528 (XOR32ri GR32:$src1, imm:$src2)>;
1529 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1530 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1531 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1532 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1533 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1534 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1535 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1536 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1539 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1540 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1541 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1542 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1545 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1546 (AND8rm GR8:$src1, addr:$src2)>;
1547 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1548 (AND16rm GR16:$src1, addr:$src2)>;
1549 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1550 (AND32rm GR32:$src1, addr:$src2)>;
1551 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1552 (AND64rm GR64:$src1, addr:$src2)>;
1555 def : Pat<(and GR8:$src1, imm:$src2),
1556 (AND8ri GR8:$src1, imm:$src2)>;
1557 def : Pat<(and GR16:$src1, imm:$src2),
1558 (AND16ri GR16:$src1, imm:$src2)>;
1559 def : Pat<(and GR32:$src1, imm:$src2),
1560 (AND32ri GR32:$src1, imm:$src2)>;
1561 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1562 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1563 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1564 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1565 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1566 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1567 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1568 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;