1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1 in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
87 // and places the address of the next argument into a register.
88 let Defs = [EFLAGS] in
89 def VAARG_64 : I<0, Pseudo,
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
98 // targets. These calls are needed to probe the stack when allocating more than
99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
100 // ensure that the guard pages used by the OS virtual memory manager are
101 // allocated in correct sequence.
102 // The main point of having separate instruction are extra unmodelled effects
103 // (compared to ordinary calls) like stack pointer change.
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
107 "# dynamic stack allocation",
110 // When using segmented stacks these are lowered into instructions which first
111 // check if the current stacklet has enough free memory. If it does, memory is
112 // allocated by bumping the stack pointer. Otherwise memory is allocated from
115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
117 "# variable sized alloca for segmented stacks",
119 (X86SegAlloca GR32:$size))]>,
120 Requires<[In32BitMode]>;
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
123 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
124 "# variable sized alloca for segmented stacks",
126 (X86SegAlloca GR64:$size))]>,
127 Requires<[In64BitMode]>;
130 // The MSVC runtime contains an _ftol2 routine for converting floating-point
131 // to integer values. It has a strange calling convention: the input is
132 // popped from the x87 stack, and the return value is given in EDX:EAX. No
133 // other registers (aside from flags) are touched.
134 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
135 // variant is unnecessary.
137 let Defs = [EAX, EDX, EFLAGS], FPForm = SpecialFP in {
138 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
140 [(X86WinFTOL RFP32:$src)]>,
141 Requires<[In32BitMode]>;
143 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
145 [(X86WinFTOL RFP64:$src)]>,
146 Requires<[In32BitMode]>;
149 //===----------------------------------------------------------------------===//
150 // EH Pseudo Instructions
152 let SchedRW = [WriteSystem] in {
153 let isTerminator = 1, isReturn = 1, isBarrier = 1,
154 hasCtrlDep = 1, isCodeGenOnly = 1 in {
155 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
156 "ret\t#eh_return, addr: $addr",
157 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
161 let isTerminator = 1, isReturn = 1, isBarrier = 1,
162 hasCtrlDep = 1, isCodeGenOnly = 1 in {
163 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
164 "ret\t#eh_return, addr: $addr",
165 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
169 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
170 usesCustomInserter = 1 in {
171 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
173 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
174 Requires<[In32BitMode]>;
175 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
177 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
178 Requires<[In64BitMode]>;
179 let isTerminator = 1 in {
180 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
181 "#EH_SJLJ_LONGJMP32",
182 [(X86eh_sjlj_longjmp addr:$buf)]>,
183 Requires<[In32BitMode]>;
184 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
185 "#EH_SJLJ_LONGJMP64",
186 [(X86eh_sjlj_longjmp addr:$buf)]>,
187 Requires<[In64BitMode]>;
192 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
193 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
194 "#EH_SjLj_Setup\t$dst", []>;
197 //===----------------------------------------------------------------------===//
198 // Pseudo instructions used by segmented stacks.
201 // This is lowered into a RET instruction by MCInstLower. We need
202 // this so that we don't have to have a MachineBasicBlock which ends
203 // with a RET and also has successors.
204 let isPseudo = 1 in {
205 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
208 // This instruction is lowered to a RET followed by a MOV. The two
209 // instructions are not generated on a higher level since then the
210 // verifier sees a MachineBasicBlock ending with a non-terminator.
211 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
215 //===----------------------------------------------------------------------===//
216 // Alias Instructions
217 //===----------------------------------------------------------------------===//
219 // Alias instructions that map movr0 to xor.
220 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
221 // FIXME: Set encoding to pseudo.
222 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
223 isCodeGenOnly = 1 in {
224 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
225 [(set GR8:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
227 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
228 // encoding and avoids a partial-register update sometimes, but doing so
229 // at isel time interferes with rematerialization in the current register
230 // allocator. For now, this is rewritten when the instruction is lowered
232 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
234 [(set GR16:$dst, 0)], IIC_ALU_NONMEM>, OpSize,
237 // FIXME: Set encoding to pseudo.
238 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
239 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
242 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
243 // smaller encoding, but doing so at isel time interferes with rematerialization
244 // in the current register allocator. For now, this is rewritten when the
245 // instruction is lowered to an MCInst.
246 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
247 // when we have a better way to specify isel priority.
248 let Defs = [EFLAGS], isCodeGenOnly=1,
249 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
250 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
251 [(set GR64:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
253 // Materialize i64 constant where top 32-bits are zero. This could theoretically
254 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
255 // that would make it more difficult to rematerialize.
256 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
258 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
259 "", [(set GR64:$dst, i64immZExt32:$src)],
260 IIC_ALU_NONMEM>, Sched<[WriteALU]>;
262 // Use sbb to materialize carry bit.
263 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
264 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
265 // However, Pat<> can't replicate the destination reg into the inputs of the
267 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
268 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
269 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
270 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
271 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
272 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
273 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
274 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
278 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
280 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
282 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
285 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
287 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
289 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
292 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
293 // will be eliminated and that the sbb can be extended up to a wider type. When
294 // this happens, it is great. However, if we are left with an 8-bit sbb and an
295 // and, we might as well just match it as a setb.
296 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
299 // (add OP, SETB) -> (adc OP, 0)
300 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
301 (ADC8ri GR8:$op, 0)>;
302 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
303 (ADC32ri8 GR32:$op, 0)>;
304 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
305 (ADC64ri8 GR64:$op, 0)>;
307 // (sub OP, SETB) -> (sbb OP, 0)
308 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
309 (SBB8ri GR8:$op, 0)>;
310 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
311 (SBB32ri8 GR32:$op, 0)>;
312 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
313 (SBB64ri8 GR64:$op, 0)>;
315 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
316 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
317 (ADC8ri GR8:$op, 0)>;
318 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
319 (ADC32ri8 GR32:$op, 0)>;
320 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
321 (ADC64ri8 GR64:$op, 0)>;
323 //===----------------------------------------------------------------------===//
324 // String Pseudo Instructions
326 let SchedRW = [WriteMicrocoded] in {
327 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
328 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
329 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
330 Requires<[In32BitMode]>;
331 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
332 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
333 Requires<[In32BitMode]>;
334 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
335 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
336 Requires<[In32BitMode]>;
339 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
340 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
341 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
342 Requires<[In64BitMode]>;
343 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
344 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
345 Requires<[In64BitMode]>;
346 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
347 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
348 Requires<[In64BitMode]>;
349 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
350 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
351 Requires<[In64BitMode]>;
354 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
355 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
356 let Uses = [AL,ECX,EDI] in
357 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
358 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
359 Requires<[In32BitMode]>;
360 let Uses = [AX,ECX,EDI] in
361 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
362 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
363 Requires<[In32BitMode]>;
364 let Uses = [EAX,ECX,EDI] in
365 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
366 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
367 Requires<[In32BitMode]>;
370 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
371 let Uses = [AL,RCX,RDI] in
372 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
373 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
374 Requires<[In64BitMode]>;
375 let Uses = [AX,RCX,RDI] in
376 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
377 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
378 Requires<[In64BitMode]>;
379 let Uses = [RAX,RCX,RDI] in
380 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
381 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
382 Requires<[In64BitMode]>;
384 let Uses = [RAX,RCX,RDI] in
385 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
386 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
387 Requires<[In64BitMode]>;
391 //===----------------------------------------------------------------------===//
392 // Thread Local Storage Instructions
396 // All calls clobber the non-callee saved registers. ESP is marked as
397 // a use to prevent stack-pointer assignments that appear immediately
398 // before calls from potentially appearing dead.
399 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
400 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
401 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
402 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
404 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
406 [(X86tlsaddr tls32addr:$sym)]>,
407 Requires<[In32BitMode]>;
408 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
410 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
411 Requires<[In32BitMode]>;
414 // All calls clobber the non-callee saved registers. RSP is marked as
415 // a use to prevent stack-pointer assignments that appear immediately
416 // before calls from potentially appearing dead.
417 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
418 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
419 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
420 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
421 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
423 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
425 [(X86tlsaddr tls64addr:$sym)]>,
426 Requires<[In64BitMode]>;
427 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
429 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
430 Requires<[In64BitMode]>;
433 // Darwin TLS Support
434 // For i386, the address of the thunk is passed on the stack, on return the
435 // address of the variable is in %eax. %ecx is trashed during the function
436 // call. All other registers are preserved.
437 let Defs = [EAX, ECX, EFLAGS],
439 usesCustomInserter = 1 in
440 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
442 [(X86TLSCall addr:$sym)]>,
443 Requires<[In32BitMode]>;
445 // For x86_64, the address of the thunk is passed in %rdi, on return
446 // the address of the variable is in %rax. All other registers are preserved.
447 let Defs = [RAX, EFLAGS],
449 usesCustomInserter = 1 in
450 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
452 [(X86TLSCall addr:$sym)]>,
453 Requires<[In64BitMode]>;
456 //===----------------------------------------------------------------------===//
457 // Conditional Move Pseudo Instructions
459 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
460 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
461 // however that requires promoting the operands, and can induce additional
462 // i8 register pressure.
463 let usesCustomInserter = 1, Uses = [EFLAGS] in {
464 def CMOV_GR8 : I<0, Pseudo,
465 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
467 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
468 imm:$cond, EFLAGS))]>;
470 let Predicates = [NoCMov] in {
471 def CMOV_GR32 : I<0, Pseudo,
472 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
473 "#CMOV_GR32* PSEUDO!",
475 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
476 def CMOV_GR16 : I<0, Pseudo,
477 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
478 "#CMOV_GR16* PSEUDO!",
480 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
481 } // Predicates = [NoCMov]
483 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
485 let Predicates = [FPStackf32] in
486 def CMOV_RFP32 : I<0, Pseudo,
488 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
489 "#CMOV_RFP32 PSEUDO!",
491 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
493 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
495 let Predicates = [FPStackf64] in
496 def CMOV_RFP64 : I<0, Pseudo,
498 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
499 "#CMOV_RFP64 PSEUDO!",
501 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
503 def CMOV_RFP80 : I<0, Pseudo,
505 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
506 "#CMOV_RFP80 PSEUDO!",
508 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
510 } // UsesCustomInserter = 1, Uses = [EFLAGS]
513 //===----------------------------------------------------------------------===//
514 // Atomic Instruction Pseudo Instructions
515 //===----------------------------------------------------------------------===//
517 // Pseudo atomic instructions
519 multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> {
520 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in {
521 let Defs = [EFLAGS, AL] in
522 def NAME#8 : I<0, Pseudo, (outs GR8:$dst),
523 (ins i8mem:$ptr, GR8:$val),
524 !strconcat(mnemonic, "8 PSEUDO!"), []>;
525 let Defs = [EFLAGS, AX] in
526 def NAME#16 : I<0, Pseudo,(outs GR16:$dst),
527 (ins i16mem:$ptr, GR16:$val),
528 !strconcat(mnemonic, "16 PSEUDO!"), []>;
529 let Defs = [EFLAGS, EAX] in
530 def NAME#32 : I<0, Pseudo, (outs GR32:$dst),
531 (ins i32mem:$ptr, GR32:$val),
532 !strconcat(mnemonic, "32 PSEUDO!"), []>;
533 let Defs = [EFLAGS, RAX] in
534 def NAME#64 : I<0, Pseudo, (outs GR64:$dst),
535 (ins i64mem:$ptr, GR64:$val),
536 !strconcat(mnemonic, "64 PSEUDO!"), []>;
540 multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> {
541 def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val),
542 (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>;
543 def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val),
544 (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>;
545 def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val),
546 (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>;
547 def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val),
548 (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>;
551 // Atomic exchange, and, or, xor
552 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">;
553 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">;
554 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">;
555 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">;
556 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">;
557 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">;
558 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">;
559 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">;
561 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">;
562 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">;
563 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">;
564 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">;
565 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">;
566 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">;
567 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">;
568 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">;
570 multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> {
571 let usesCustomInserter = 1, Defs = [EFLAGS, EAX, EDX],
572 mayLoad = 1, mayStore = 1, hasSideEffects = 0 in
573 def NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
574 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
575 !strconcat(mnemonic, "6432 PSEUDO!"), []>;
578 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMAND">;
579 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMOR">;
580 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMXOR">;
581 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMNAND">;
582 defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMADD">;
583 defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSUB">;
584 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMAX">;
585 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMMIN">;
586 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMAX">;
587 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMUMIN">;
588 defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"#ATOMSWAP">;
590 //===----------------------------------------------------------------------===//
591 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
592 //===----------------------------------------------------------------------===//
594 // FIXME: Use normal instructions and add lock prefix dynamically.
598 // TODO: Get this to fold the constant into the instruction.
599 let isCodeGenOnly = 1, Defs = [EFLAGS] in
600 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
601 "or{l}\t{$zero, $dst|$dst, $zero}",
602 [], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK,
603 Sched<[WriteALULd, WriteRMW]>;
605 let hasSideEffects = 1 in
606 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
608 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
610 // RegOpc corresponds to the mr version of the instruction
611 // ImmOpc corresponds to the mi version of the instruction
612 // ImmOpc8 corresponds to the mi8 version of the instruction
613 // ImmMod corresponds to the instruction format of the mi and mi8 versions
614 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
615 Format ImmMod, string mnemonic> {
616 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
617 SchedRW = [WriteALULd, WriteRMW] in {
619 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
620 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
621 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
622 !strconcat(mnemonic, "{b}\t",
623 "{$src2, $dst|$dst, $src2}"),
624 [], IIC_ALU_NONMEM>, LOCK;
625 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
626 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
627 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
628 !strconcat(mnemonic, "{w}\t",
629 "{$src2, $dst|$dst, $src2}"),
630 [], IIC_ALU_NONMEM>, OpSize, LOCK;
631 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
632 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
633 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
634 !strconcat(mnemonic, "{l}\t",
635 "{$src2, $dst|$dst, $src2}"),
636 [], IIC_ALU_NONMEM>, LOCK;
637 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
638 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
639 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
640 !strconcat(mnemonic, "{q}\t",
641 "{$src2, $dst|$dst, $src2}"),
642 [], IIC_ALU_NONMEM>, LOCK;
644 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
645 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
646 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
647 !strconcat(mnemonic, "{b}\t",
648 "{$src2, $dst|$dst, $src2}"),
649 [], IIC_ALU_MEM>, LOCK;
651 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
652 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
653 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
654 !strconcat(mnemonic, "{w}\t",
655 "{$src2, $dst|$dst, $src2}"),
656 [], IIC_ALU_MEM>, OpSize, LOCK;
658 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
659 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
660 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
661 !strconcat(mnemonic, "{l}\t",
662 "{$src2, $dst|$dst, $src2}"),
663 [], IIC_ALU_MEM>, LOCK;
665 def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
666 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
667 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
668 !strconcat(mnemonic, "{q}\t",
669 "{$src2, $dst|$dst, $src2}"),
670 [], IIC_ALU_MEM>, LOCK;
672 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
673 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
674 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
675 !strconcat(mnemonic, "{w}\t",
676 "{$src2, $dst|$dst, $src2}"),
677 [], IIC_ALU_MEM>, OpSize, LOCK;
678 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
679 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
680 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
681 !strconcat(mnemonic, "{l}\t",
682 "{$src2, $dst|$dst, $src2}"),
683 [], IIC_ALU_MEM>, LOCK;
684 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
685 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
686 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
687 !strconcat(mnemonic, "{q}\t",
688 "{$src2, $dst|$dst, $src2}"),
689 [], IIC_ALU_MEM>, LOCK;
695 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
696 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
697 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
698 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
699 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
701 // Optimized codegen when the non-memory output is not used.
702 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
704 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
705 SchedRW = [WriteALULd, WriteRMW] in {
707 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
708 !strconcat(mnemonic, "{b}\t$dst"),
709 [], IIC_UNARY_MEM>, LOCK;
710 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
711 !strconcat(mnemonic, "{w}\t$dst"),
712 [], IIC_UNARY_MEM>, OpSize, LOCK;
713 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
714 !strconcat(mnemonic, "{l}\t$dst"),
715 [], IIC_UNARY_MEM>, LOCK;
716 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
717 !strconcat(mnemonic, "{q}\t$dst"),
718 [], IIC_UNARY_MEM>, LOCK;
722 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
723 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
725 // Atomic compare and swap.
726 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
727 SDPatternOperator frag, X86MemOperand x86memop,
728 InstrItinClass itin> {
729 let isCodeGenOnly = 1 in {
730 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
731 !strconcat(mnemonic, "\t$ptr"),
732 [(frag addr:$ptr)], itin>, TB, LOCK;
736 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
737 string mnemonic, SDPatternOperator frag,
738 InstrItinClass itin8, InstrItinClass itin> {
739 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
740 let Defs = [AL, EFLAGS], Uses = [AL] in
741 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
742 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
743 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
744 let Defs = [AX, EFLAGS], Uses = [AX] in
745 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
746 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
747 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;
748 let Defs = [EAX, EFLAGS], Uses = [EAX] in
749 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
750 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
751 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;
752 let Defs = [RAX, EFLAGS], Uses = [RAX] in
753 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
754 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
755 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
759 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
760 SchedRW = [WriteALULd, WriteRMW] in {
761 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
766 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
767 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
768 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
770 IIC_CMPX_LOCK_16B>, REX_W;
773 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
774 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
776 // Atomic exchange and add
777 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
779 InstrItinClass itin8, InstrItinClass itin> {
780 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
781 SchedRW = [WriteALULd, WriteRMW] in {
782 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
783 (ins GR8:$val, i8mem:$ptr),
784 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
786 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
788 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
789 (ins GR16:$val, i16mem:$ptr),
790 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
793 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
795 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
796 (ins GR32:$val, i32mem:$ptr),
797 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
800 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
802 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
803 (ins GR64:$val, i64mem:$ptr),
804 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
807 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
812 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
813 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
816 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
817 "#ACQUIRE_MOV PSEUDO!",
818 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
819 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
820 "#ACQUIRE_MOV PSEUDO!",
821 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
822 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
823 "#ACQUIRE_MOV PSEUDO!",
824 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
825 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
826 "#ACQUIRE_MOV PSEUDO!",
827 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
829 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
830 "#RELEASE_MOV PSEUDO!",
831 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
832 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
833 "#RELEASE_MOV PSEUDO!",
834 [(atomic_store_16 addr:$dst, GR16:$src)]>;
835 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
836 "#RELEASE_MOV PSEUDO!",
837 [(atomic_store_32 addr:$dst, GR32:$src)]>;
838 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
839 "#RELEASE_MOV PSEUDO!",
840 [(atomic_store_64 addr:$dst, GR64:$src)]>;
842 //===----------------------------------------------------------------------===//
843 // Conditional Move Pseudo Instructions.
844 //===----------------------------------------------------------------------===//
847 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
848 // instruction selection into a branch sequence.
849 let Uses = [EFLAGS], usesCustomInserter = 1 in {
850 def CMOV_FR32 : I<0, Pseudo,
851 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
852 "#CMOV_FR32 PSEUDO!",
853 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
855 def CMOV_FR64 : I<0, Pseudo,
856 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
857 "#CMOV_FR64 PSEUDO!",
858 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
860 def CMOV_V4F32 : I<0, Pseudo,
861 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
862 "#CMOV_V4F32 PSEUDO!",
864 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
866 def CMOV_V2F64 : I<0, Pseudo,
867 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
868 "#CMOV_V2F64 PSEUDO!",
870 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
872 def CMOV_V2I64 : I<0, Pseudo,
873 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
874 "#CMOV_V2I64 PSEUDO!",
876 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
878 def CMOV_V8F32 : I<0, Pseudo,
879 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
880 "#CMOV_V8F32 PSEUDO!",
882 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
884 def CMOV_V4F64 : I<0, Pseudo,
885 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
886 "#CMOV_V4F64 PSEUDO!",
888 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
890 def CMOV_V4I64 : I<0, Pseudo,
891 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
892 "#CMOV_V4I64 PSEUDO!",
894 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
899 //===----------------------------------------------------------------------===//
900 // DAG Pattern Matching Rules
901 //===----------------------------------------------------------------------===//
903 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
904 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
905 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
906 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
907 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
908 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
909 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
911 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
912 (ADD32ri GR32:$src1, tconstpool:$src2)>;
913 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
914 (ADD32ri GR32:$src1, tjumptable:$src2)>;
915 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
916 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
917 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
918 (ADD32ri GR32:$src1, texternalsym:$src2)>;
919 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
920 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
922 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
923 (MOV32mi addr:$dst, tglobaladdr:$src)>;
924 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
925 (MOV32mi addr:$dst, texternalsym:$src)>;
926 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
927 (MOV32mi addr:$dst, tblockaddress:$src)>;
931 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
932 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
933 // 'movabs' predicate should handle this sort of thing.
934 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
935 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
936 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
937 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
938 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
939 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
940 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
941 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
942 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
943 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
945 // In static codegen with small code model, we can get the address of a label
946 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
947 // the MOV64ri64i32 should accept these.
948 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
949 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
950 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
951 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
952 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
953 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
954 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
955 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
956 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
957 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
959 // In kernel code model, we can get the address of a label
960 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
961 // the MOV64ri32 should accept these.
962 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
963 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
964 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
965 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
966 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
967 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
968 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
969 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
970 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
971 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
973 // If we have small model and -static mode, it is safe to store global addresses
974 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
975 // for MOV64mi32 should handle this sort of thing.
976 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
977 (MOV64mi32 addr:$dst, tconstpool:$src)>,
978 Requires<[NearData, IsStatic]>;
979 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
980 (MOV64mi32 addr:$dst, tjumptable:$src)>,
981 Requires<[NearData, IsStatic]>;
982 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
983 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
984 Requires<[NearData, IsStatic]>;
985 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
986 (MOV64mi32 addr:$dst, texternalsym:$src)>,
987 Requires<[NearData, IsStatic]>;
988 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
989 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
990 Requires<[NearData, IsStatic]>;
996 // tls has some funny stuff here...
997 // This corresponds to movabs $foo@tpoff, %rax
998 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
999 (MOV64ri tglobaltlsaddr :$dst)>;
1000 // This corresponds to add $foo@tpoff, %rax
1001 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1002 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1005 // Direct PC relative function call for small code model. 32-bit displacement
1006 // sign extended to 64-bit.
1007 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1008 (CALL64pcrel32 tglobaladdr:$dst)>;
1009 def : Pat<(X86call (i64 texternalsym:$dst)),
1010 (CALL64pcrel32 texternalsym:$dst)>;
1012 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1013 // can never use callee-saved registers. That is the purpose of the GR64_TC
1014 // register classes.
1016 // The only volatile register that is never used by the calling convention is
1017 // %r11. This happens when calling a vararg function with 6 arguments.
1019 // Match an X86tcret that uses less than 7 volatile registers.
1020 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1021 (X86tcret node:$ptr, node:$off), [{
1022 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1023 unsigned NumRegs = 0;
1024 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1025 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1030 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1031 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1032 Requires<[In32BitMode]>;
1034 // FIXME: This is disabled for 32-bit PIC mode because the global base
1035 // register which is part of the address mode may be assigned a
1036 // callee-saved register.
1037 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1038 (TCRETURNmi addr:$dst, imm:$off)>,
1039 Requires<[In32BitMode, IsNotPIC]>;
1041 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1042 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1043 Requires<[In32BitMode]>;
1045 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1046 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1047 Requires<[In32BitMode]>;
1049 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1050 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1051 Requires<[In64BitMode]>;
1053 // Don't fold loads into X86tcret requiring more than 6 regs.
1054 // There wouldn't be enough scratch registers for base+index.
1055 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1056 (TCRETURNmi64 addr:$dst, imm:$off)>,
1057 Requires<[In64BitMode]>;
1059 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1060 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1061 Requires<[In64BitMode]>;
1063 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1064 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1065 Requires<[In64BitMode]>;
1067 // Normal calls, with various flavors of addresses.
1068 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1069 (CALLpcrel32 tglobaladdr:$dst)>;
1070 def : Pat<(X86call (i32 texternalsym:$dst)),
1071 (CALLpcrel32 texternalsym:$dst)>;
1072 def : Pat<(X86call (i32 imm:$dst)),
1073 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1077 // TEST R,R is smaller than CMP R,0
1078 def : Pat<(X86cmp GR8:$src1, 0),
1079 (TEST8rr GR8:$src1, GR8:$src1)>;
1080 def : Pat<(X86cmp GR16:$src1, 0),
1081 (TEST16rr GR16:$src1, GR16:$src1)>;
1082 def : Pat<(X86cmp GR32:$src1, 0),
1083 (TEST32rr GR32:$src1, GR32:$src1)>;
1084 def : Pat<(X86cmp GR64:$src1, 0),
1085 (TEST64rr GR64:$src1, GR64:$src1)>;
1087 // Conditional moves with folded loads with operands swapped and conditions
1089 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1090 Instruction Inst64> {
1091 let Predicates = [HasCMov] in {
1092 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1093 (Inst16 GR16:$src2, addr:$src1)>;
1094 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1095 (Inst32 GR32:$src2, addr:$src1)>;
1096 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1097 (Inst64 GR64:$src2, addr:$src1)>;
1101 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1102 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1103 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1104 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1105 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1106 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1107 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1108 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1109 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1110 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1111 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1112 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1113 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1114 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1115 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1116 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1118 // zextload bool -> zextload byte
1119 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1120 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1121 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1122 def : Pat<(zextloadi64i1 addr:$src),
1123 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1125 // extload bool -> extload byte
1126 // When extloading from 16-bit and smaller memory locations into 64-bit
1127 // registers, use zero-extending loads so that the entire 64-bit register is
1128 // defined, avoiding partial-register updates.
1130 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1131 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1132 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1133 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1134 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1135 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1137 // For other extloads, use subregs, since the high contents of the register are
1138 // defined after an extload.
1139 def : Pat<(extloadi64i1 addr:$src),
1140 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1141 def : Pat<(extloadi64i8 addr:$src),
1142 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1143 def : Pat<(extloadi64i16 addr:$src),
1144 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1145 def : Pat<(extloadi64i32 addr:$src),
1146 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1148 // anyext. Define these to do an explicit zero-extend to
1149 // avoid partial-register updates.
1150 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1151 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1152 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1154 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1155 def : Pat<(i32 (anyext GR16:$src)),
1156 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1158 def : Pat<(i64 (anyext GR8 :$src)),
1159 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1160 def : Pat<(i64 (anyext GR16:$src)),
1161 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1162 def : Pat<(i64 (anyext GR32:$src)),
1163 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1166 // Any instruction that defines a 32-bit result leaves the high half of the
1167 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1168 // be copying from a truncate. And x86's cmov doesn't do anything if the
1169 // condition is false. But any other 32-bit operation will zero-extend
1171 def def32 : PatLeaf<(i32 GR32:$src), [{
1172 return N->getOpcode() != ISD::TRUNCATE &&
1173 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1174 N->getOpcode() != ISD::CopyFromReg &&
1175 N->getOpcode() != X86ISD::CMOV;
1178 // In the case of a 32-bit def that is known to implicitly zero-extend,
1179 // we can use a SUBREG_TO_REG.
1180 def : Pat<(i64 (zext def32:$src)),
1181 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1183 //===----------------------------------------------------------------------===//
1184 // Pattern match OR as ADD
1185 //===----------------------------------------------------------------------===//
1187 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1188 // 3-addressified into an LEA instruction to avoid copies. However, we also
1189 // want to finally emit these instructions as an or at the end of the code
1190 // generator to make the generated code easier to read. To do this, we select
1191 // into "disjoint bits" pseudo ops.
1193 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1194 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1195 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1196 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1198 APInt KnownZero0, KnownOne0;
1199 CurDAG->ComputeMaskedBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1200 APInt KnownZero1, KnownOne1;
1201 CurDAG->ComputeMaskedBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1202 return (~KnownZero0 & ~KnownZero1) == 0;
1206 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1207 // Try this before the selecting to OR.
1208 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1210 let isConvertibleToThreeAddress = 1,
1211 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1212 let isCommutable = 1 in {
1213 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1214 "", // orw/addw REG, REG
1215 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1216 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1217 "", // orl/addl REG, REG
1218 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1219 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1220 "", // orq/addq REG, REG
1221 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1224 // NOTE: These are order specific, we want the ri8 forms to be listed
1225 // first so that they are slightly preferred to the ri forms.
1227 def ADD16ri8_DB : I<0, Pseudo,
1228 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1229 "", // orw/addw REG, imm8
1230 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1231 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1232 "", // orw/addw REG, imm
1233 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1235 def ADD32ri8_DB : I<0, Pseudo,
1236 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1237 "", // orl/addl REG, imm8
1238 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1239 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1240 "", // orl/addl REG, imm
1241 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1244 def ADD64ri8_DB : I<0, Pseudo,
1245 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1246 "", // orq/addq REG, imm8
1247 [(set GR64:$dst, (or_is_add GR64:$src1,
1248 i64immSExt8:$src2))]>;
1249 def ADD64ri32_DB : I<0, Pseudo,
1250 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1251 "", // orq/addq REG, imm
1252 [(set GR64:$dst, (or_is_add GR64:$src1,
1253 i64immSExt32:$src2))]>;
1255 } // AddedComplexity, SchedRW
1258 //===----------------------------------------------------------------------===//
1260 //===----------------------------------------------------------------------===//
1262 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1263 // +128 doesn't, so in this special case use a sub instead of an add.
1264 def : Pat<(add GR16:$src1, 128),
1265 (SUB16ri8 GR16:$src1, -128)>;
1266 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1267 (SUB16mi8 addr:$dst, -128)>;
1269 def : Pat<(add GR32:$src1, 128),
1270 (SUB32ri8 GR32:$src1, -128)>;
1271 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1272 (SUB32mi8 addr:$dst, -128)>;
1274 def : Pat<(add GR64:$src1, 128),
1275 (SUB64ri8 GR64:$src1, -128)>;
1276 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1277 (SUB64mi8 addr:$dst, -128)>;
1279 // The same trick applies for 32-bit immediate fields in 64-bit
1281 def : Pat<(add GR64:$src1, 0x0000000080000000),
1282 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1283 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1284 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1286 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1287 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1288 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1289 // represented with a sign extension of a 8 bit constant, use that.
1291 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1295 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1296 (i32 (GetLo8XForm imm:$imm))),
1299 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1303 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1304 (i32 (GetLo32XForm imm:$imm))),
1308 // r & (2^16-1) ==> movz
1309 def : Pat<(and GR32:$src1, 0xffff),
1310 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1311 // r & (2^8-1) ==> movz
1312 def : Pat<(and GR32:$src1, 0xff),
1313 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1316 Requires<[In32BitMode]>;
1317 // r & (2^8-1) ==> movz
1318 def : Pat<(and GR16:$src1, 0xff),
1319 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1320 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1322 Requires<[In32BitMode]>;
1324 // r & (2^32-1) ==> movz
1325 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1326 (SUBREG_TO_REG (i64 0),
1327 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1329 // r & (2^16-1) ==> movz
1330 def : Pat<(and GR64:$src, 0xffff),
1331 (SUBREG_TO_REG (i64 0),
1332 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1334 // r & (2^8-1) ==> movz
1335 def : Pat<(and GR64:$src, 0xff),
1336 (SUBREG_TO_REG (i64 0),
1337 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1339 // r & (2^8-1) ==> movz
1340 def : Pat<(and GR32:$src1, 0xff),
1341 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1342 Requires<[In64BitMode]>;
1343 // r & (2^8-1) ==> movz
1344 def : Pat<(and GR16:$src1, 0xff),
1345 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1346 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1347 Requires<[In64BitMode]>;
1350 // sext_inreg patterns
1351 def : Pat<(sext_inreg GR32:$src, i16),
1352 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1353 def : Pat<(sext_inreg GR32:$src, i8),
1354 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1357 Requires<[In32BitMode]>;
1359 def : Pat<(sext_inreg GR16:$src, i8),
1360 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1361 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1363 Requires<[In32BitMode]>;
1365 def : Pat<(sext_inreg GR64:$src, i32),
1366 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1367 def : Pat<(sext_inreg GR64:$src, i16),
1368 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1369 def : Pat<(sext_inreg GR64:$src, i8),
1370 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1371 def : Pat<(sext_inreg GR32:$src, i8),
1372 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1373 Requires<[In64BitMode]>;
1374 def : Pat<(sext_inreg GR16:$src, i8),
1375 (EXTRACT_SUBREG (MOVSX32rr8
1376 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1377 Requires<[In64BitMode]>;
1379 // sext, sext_load, zext, zext_load
1380 def: Pat<(i16 (sext GR8:$src)),
1381 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1382 def: Pat<(sextloadi16i8 addr:$src),
1383 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1384 def: Pat<(i16 (zext GR8:$src)),
1385 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1386 def: Pat<(zextloadi16i8 addr:$src),
1387 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1390 def : Pat<(i16 (trunc GR32:$src)),
1391 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1392 def : Pat<(i8 (trunc GR32:$src)),
1393 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1395 Requires<[In32BitMode]>;
1396 def : Pat<(i8 (trunc GR16:$src)),
1397 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1399 Requires<[In32BitMode]>;
1400 def : Pat<(i32 (trunc GR64:$src)),
1401 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1402 def : Pat<(i16 (trunc GR64:$src)),
1403 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1404 def : Pat<(i8 (trunc GR64:$src)),
1405 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1406 def : Pat<(i8 (trunc GR32:$src)),
1407 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1408 Requires<[In64BitMode]>;
1409 def : Pat<(i8 (trunc GR16:$src)),
1410 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1411 Requires<[In64BitMode]>;
1413 // h-register tricks
1414 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1415 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1417 Requires<[In32BitMode]>;
1418 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1419 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1421 Requires<[In32BitMode]>;
1422 def : Pat<(srl GR16:$src, (i8 8)),
1425 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1428 Requires<[In32BitMode]>;
1429 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1430 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1433 Requires<[In32BitMode]>;
1434 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1435 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1438 Requires<[In32BitMode]>;
1439 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1440 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1443 Requires<[In32BitMode]>;
1444 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1445 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1448 Requires<[In32BitMode]>;
1450 // h-register tricks.
1451 // For now, be conservative on x86-64 and use an h-register extract only if the
1452 // value is immediately zero-extended or stored, which are somewhat common
1453 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1454 // from being allocated in the same instruction as the h register, as there's
1455 // currently no way to describe this requirement to the register allocator.
1457 // h-register extract and zero-extend.
1458 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1462 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1465 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1467 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1469 Requires<[In64BitMode]>;
1470 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1471 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1474 Requires<[In64BitMode]>;
1475 def : Pat<(srl GR16:$src, (i8 8)),
1478 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1481 Requires<[In64BitMode]>;
1482 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1484 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1486 Requires<[In64BitMode]>;
1487 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1489 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1491 Requires<[In64BitMode]>;
1492 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1496 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1499 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1503 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1507 // h-register extract and store.
1508 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1511 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1513 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1516 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1518 Requires<[In64BitMode]>;
1519 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1522 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1524 Requires<[In64BitMode]>;
1527 // (shl x, 1) ==> (add x, x)
1528 // Note that if x is undef (immediate or otherwise), we could theoretically
1529 // end up with the two uses of x getting different values, producing a result
1530 // where the least significant bit is not 0. However, the probability of this
1531 // happening is considered low enough that this is officially not a
1533 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1534 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1535 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1536 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1538 // Helper imms that check if a mask doesn't change significant shift bits.
1539 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1540 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1542 // (shl x (and y, 31)) ==> (shl x, y)
1543 def : Pat<(shl GR8:$src1, (and CL, immShift32)),
1544 (SHL8rCL GR8:$src1)>;
1545 def : Pat<(shl GR16:$src1, (and CL, immShift32)),
1546 (SHL16rCL GR16:$src1)>;
1547 def : Pat<(shl GR32:$src1, (and CL, immShift32)),
1548 (SHL32rCL GR32:$src1)>;
1549 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1550 (SHL8mCL addr:$dst)>;
1551 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1552 (SHL16mCL addr:$dst)>;
1553 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1554 (SHL32mCL addr:$dst)>;
1556 def : Pat<(srl GR8:$src1, (and CL, immShift32)),
1557 (SHR8rCL GR8:$src1)>;
1558 def : Pat<(srl GR16:$src1, (and CL, immShift32)),
1559 (SHR16rCL GR16:$src1)>;
1560 def : Pat<(srl GR32:$src1, (and CL, immShift32)),
1561 (SHR32rCL GR32:$src1)>;
1562 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1563 (SHR8mCL addr:$dst)>;
1564 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1565 (SHR16mCL addr:$dst)>;
1566 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1567 (SHR32mCL addr:$dst)>;
1569 def : Pat<(sra GR8:$src1, (and CL, immShift32)),
1570 (SAR8rCL GR8:$src1)>;
1571 def : Pat<(sra GR16:$src1, (and CL, immShift32)),
1572 (SAR16rCL GR16:$src1)>;
1573 def : Pat<(sra GR32:$src1, (and CL, immShift32)),
1574 (SAR32rCL GR32:$src1)>;
1575 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1576 (SAR8mCL addr:$dst)>;
1577 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1578 (SAR16mCL addr:$dst)>;
1579 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1580 (SAR32mCL addr:$dst)>;
1582 // (shl x (and y, 63)) ==> (shl x, y)
1583 def : Pat<(shl GR64:$src1, (and CL, immShift64)),
1584 (SHL64rCL GR64:$src1)>;
1585 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1586 (SHL64mCL addr:$dst)>;
1588 def : Pat<(srl GR64:$src1, (and CL, immShift64)),
1589 (SHR64rCL GR64:$src1)>;
1590 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1591 (SHR64mCL addr:$dst)>;
1593 def : Pat<(sra GR64:$src1, (and CL, immShift64)),
1594 (SAR64rCL GR64:$src1)>;
1595 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1596 (SAR64mCL addr:$dst)>;
1599 // (anyext (setcc_carry)) -> (setcc_carry)
1600 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1602 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1604 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1610 //===----------------------------------------------------------------------===//
1611 // EFLAGS-defining Patterns
1612 //===----------------------------------------------------------------------===//
1615 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1616 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1617 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1620 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1621 (ADD8rm GR8:$src1, addr:$src2)>;
1622 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1623 (ADD16rm GR16:$src1, addr:$src2)>;
1624 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1625 (ADD32rm GR32:$src1, addr:$src2)>;
1628 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1629 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1630 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1631 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1632 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1633 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1634 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1637 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1638 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1639 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1642 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1643 (SUB8rm GR8:$src1, addr:$src2)>;
1644 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1645 (SUB16rm GR16:$src1, addr:$src2)>;
1646 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1647 (SUB32rm GR32:$src1, addr:$src2)>;
1650 def : Pat<(sub GR8:$src1, imm:$src2),
1651 (SUB8ri GR8:$src1, imm:$src2)>;
1652 def : Pat<(sub GR16:$src1, imm:$src2),
1653 (SUB16ri GR16:$src1, imm:$src2)>;
1654 def : Pat<(sub GR32:$src1, imm:$src2),
1655 (SUB32ri GR32:$src1, imm:$src2)>;
1656 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1657 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1658 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1659 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1662 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1663 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1664 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1665 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1668 def : Pat<(mul GR16:$src1, GR16:$src2),
1669 (IMUL16rr GR16:$src1, GR16:$src2)>;
1670 def : Pat<(mul GR32:$src1, GR32:$src2),
1671 (IMUL32rr GR32:$src1, GR32:$src2)>;
1674 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1675 (IMUL16rm GR16:$src1, addr:$src2)>;
1676 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1677 (IMUL32rm GR32:$src1, addr:$src2)>;
1680 def : Pat<(mul GR16:$src1, imm:$src2),
1681 (IMUL16rri GR16:$src1, imm:$src2)>;
1682 def : Pat<(mul GR32:$src1, imm:$src2),
1683 (IMUL32rri GR32:$src1, imm:$src2)>;
1684 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1685 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1686 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1687 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1689 // reg = mul mem, imm
1690 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1691 (IMUL16rmi addr:$src1, imm:$src2)>;
1692 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1693 (IMUL32rmi addr:$src1, imm:$src2)>;
1694 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1695 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1696 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1697 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1699 // Patterns for nodes that do not produce flags, for instructions that do.
1702 def : Pat<(add GR64:$src1, GR64:$src2),
1703 (ADD64rr GR64:$src1, GR64:$src2)>;
1704 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1705 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1706 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1707 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1708 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1709 (ADD64rm GR64:$src1, addr:$src2)>;
1712 def : Pat<(sub GR64:$src1, GR64:$src2),
1713 (SUB64rr GR64:$src1, GR64:$src2)>;
1714 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1715 (SUB64rm GR64:$src1, addr:$src2)>;
1716 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1717 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1718 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1719 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1722 def : Pat<(mul GR64:$src1, GR64:$src2),
1723 (IMUL64rr GR64:$src1, GR64:$src2)>;
1724 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1725 (IMUL64rm GR64:$src1, addr:$src2)>;
1726 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1727 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1728 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1729 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1730 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1731 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1732 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1733 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1736 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1737 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1738 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1739 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1740 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1741 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1744 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1745 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1746 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1747 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1748 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1749 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1752 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1753 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1754 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1755 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1758 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1759 (OR8rm GR8:$src1, addr:$src2)>;
1760 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1761 (OR16rm GR16:$src1, addr:$src2)>;
1762 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1763 (OR32rm GR32:$src1, addr:$src2)>;
1764 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1765 (OR64rm GR64:$src1, addr:$src2)>;
1768 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1769 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1770 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1771 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1772 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1773 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1774 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1775 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1776 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1777 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1778 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1781 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1782 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1783 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1784 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1787 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1788 (XOR8rm GR8:$src1, addr:$src2)>;
1789 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1790 (XOR16rm GR16:$src1, addr:$src2)>;
1791 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1792 (XOR32rm GR32:$src1, addr:$src2)>;
1793 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1794 (XOR64rm GR64:$src1, addr:$src2)>;
1797 def : Pat<(xor GR8:$src1, imm:$src2),
1798 (XOR8ri GR8:$src1, imm:$src2)>;
1799 def : Pat<(xor GR16:$src1, imm:$src2),
1800 (XOR16ri GR16:$src1, imm:$src2)>;
1801 def : Pat<(xor GR32:$src1, imm:$src2),
1802 (XOR32ri GR32:$src1, imm:$src2)>;
1803 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1804 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1805 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1806 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1807 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1808 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1809 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1810 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1813 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1814 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1815 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1816 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1819 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1820 (AND8rm GR8:$src1, addr:$src2)>;
1821 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1822 (AND16rm GR16:$src1, addr:$src2)>;
1823 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1824 (AND32rm GR32:$src1, addr:$src2)>;
1825 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1826 (AND64rm GR64:$src1, addr:$src2)>;
1829 def : Pat<(and GR8:$src1, imm:$src2),
1830 (AND8ri GR8:$src1, imm:$src2)>;
1831 def : Pat<(and GR16:$src1, imm:$src2),
1832 (AND16ri GR16:$src1, imm:$src2)>;
1833 def : Pat<(and GR32:$src1, imm:$src2),
1834 (AND32ri GR32:$src1, imm:$src2)>;
1835 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1836 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1837 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1838 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1839 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1840 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1841 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1842 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1844 // Bit scan instruction patterns to match explicit zero-undef behavior.
1845 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1846 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1847 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1848 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1849 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1850 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;