1 //===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 jump, return, call, and related instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Control Flow Instructions.
18 // Return instructions.
20 // The X86retflag return instructions are variadic because we may add ST0 and
21 // ST1 arguments when returning values on the x87 stack.
22 let isTerminator = 1, isReturn = 1, isBarrier = 1,
23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
24 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
25 "ret{l}", [(X86retflag 0)], IIC_RET>, OpSize32,
26 Requires<[Not64BitMode]>;
27 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
28 "ret{q}", [(X86retflag 0)], IIC_RET>, OpSize32,
29 Requires<[In64BitMode]>;
30 def RETW : I <0xC3, RawFrm, (outs), (ins),
32 [], IIC_RET>, OpSize16;
33 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
35 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32,
36 Requires<[Not64BitMode]>;
37 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
39 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32,
40 Requires<[In64BitMode]>;
41 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
43 [], IIC_RET_IMM>, OpSize16;
44 def LRETL : I <0xCB, RawFrm, (outs), (ins),
45 "{l}ret{l|f}", [], IIC_RET>, OpSize32;
46 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
47 "{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>;
48 def LRETW : I <0xCB, RawFrm, (outs), (ins),
49 "{l}ret{w|f}", [], IIC_RET>, OpSize16;
50 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
51 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32;
52 def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
53 "{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>;
54 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
55 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16;
58 // Unconditional branches.
59 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
60 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
61 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize32;
62 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
63 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize16,
64 Requires<[In16BitMode]>;
65 let hasSideEffects = 0 in
66 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
67 "jmp\t$dst", [], IIC_JMP_REL>;
70 // Conditional Branches.
71 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
72 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
73 let hasSideEffects = 0 in
74 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
76 def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
77 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, OpSize16,
78 TB, Requires<[In16BitMode]>;
79 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
80 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB,
85 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
86 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
87 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
88 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
89 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
90 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
91 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
92 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
93 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
94 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
95 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
96 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
97 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
98 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
99 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
100 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
102 // jcx/jecx/jrcx instructions.
103 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
104 // These are the 32-bit versions of this instruction for the asmparser. In
105 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
108 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
109 "jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[Not64BitMode]>;
111 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
112 "jecxz\t$dst", [], IIC_JCXZ>, Requires<[Not64BitMode]>;
114 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
115 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version
118 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
119 "jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>;
121 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
122 "jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>;
126 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
127 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
128 [(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
129 OpSize16, Sched<[WriteJump]>;
130 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
131 [(brind (loadi16 addr:$dst))], IIC_JMP_MEM>,
132 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
134 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
135 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
136 OpSize32, Sched<[WriteJump]>;
137 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
138 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
139 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>;
141 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
142 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
144 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
145 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>,
146 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
148 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
149 (ins i16imm:$off, i16imm:$seg),
150 "ljmp{w}\t{$seg, $off|$off, $seg}", [],
151 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
152 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
153 (ins i32imm:$off, i16imm:$seg),
154 "ljmp{l}\t{$seg, $off|$off, $seg}", [],
155 IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
156 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
157 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
160 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
161 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
162 Sched<[WriteJumpLd]>;
163 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
164 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize32,
165 Sched<[WriteJumpLd]>;
170 let SchedRW = [WriteJump] in {
171 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
172 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
173 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
176 //===----------------------------------------------------------------------===//
177 // Call Instructions...
180 // All calls clobber the non-callee saved registers. ESP is marked as
181 // a use to prevent stack-pointer assignments that appear immediately
182 // before calls from potentially appearing dead. Uses for argument
183 // registers are added manually.
184 let Uses = [ESP] in {
185 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
186 (outs), (ins i32imm_pcrel:$dst),
187 "call{l}\t$dst", [], IIC_CALL_RI>, OpSize32,
188 Requires<[Not64BitMode]>, Sched<[WriteJump]>;
189 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
190 (outs), (ins i16imm_pcrel:$dst),
191 "call{w}\t$dst", [], IIC_CALL_RI>, OpSize16,
193 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
194 "call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>,
195 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
196 def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
197 "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))],
198 IIC_CALL_MEM>, OpSize16,
199 Requires<[Not64BitMode,FavorMemIndirectCall]>,
200 Sched<[WriteJumpLd]>;
201 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
202 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
203 OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
204 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
205 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
206 IIC_CALL_MEM>, OpSize32,
207 Requires<[Not64BitMode,FavorMemIndirectCall]>,
208 Sched<[WriteJumpLd]>;
210 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
211 (ins i16imm:$off, i16imm:$seg),
212 "lcall{w}\t{$seg, $off|$off, $seg}", [],
213 IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
214 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
215 (ins i32imm:$off, i16imm:$seg),
216 "lcall{l}\t{$seg, $off|$off, $seg}", [],
217 IIC_CALL_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
219 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
220 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
221 Sched<[WriteJumpLd]>;
222 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
223 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize32,
224 Sched<[WriteJumpLd]>;
230 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
231 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
232 let Uses = [ESP] in {
233 def TCRETURNdi : PseudoI<(outs),
234 (ins i32imm_pcrel:$dst, i32imm:$offset), []>;
235 def TCRETURNri : PseudoI<(outs),
236 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
238 def TCRETURNmi : PseudoI<(outs),
239 (ins i32mem_TC:$dst, i32imm:$offset), []>;
241 // FIXME: The should be pseudo instructions that are lowered when going to
243 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
244 (ins i32imm_pcrel:$dst),
245 "jmp\t$dst # TAILCALL",
247 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
248 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
250 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
251 "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
255 //===----------------------------------------------------------------------===//
256 // Call Instructions...
259 // RSP is marked as a use to prevent stack-pointer assignments that appear
260 // immediately before calls from potentially appearing dead. Uses for argument
261 // registers are added manually.
262 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
263 // NOTE: this pattern doesn't match "X86call imm", because we do not know
264 // that the offset between an arbitrary immediate and the call will fit in
265 // the 32-bit pcrel field that we have.
266 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
267 (outs), (ins i64i32imm_pcrel:$dst),
268 "call{q}\t$dst", [], IIC_CALL_RI>, OpSize32,
269 Requires<[In64BitMode]>;
270 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
271 "call{q}\t{*}$dst", [(X86call GR64:$dst)],
273 Requires<[In64BitMode]>;
274 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
275 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
277 Requires<[In64BitMode,FavorMemIndirectCall]>;
279 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
280 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
283 let isCall = 1, isCodeGenOnly = 1 in
284 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
285 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
286 let Defs = [RAX, R10, R11, RSP, EFLAGS],
288 def W64ALLOCA : Ii32PCRel<0xE8, RawFrm,
289 (outs), (ins i64i32imm_pcrel:$dst),
290 "call{q}\t$dst", [], IIC_CALL_RI>,
291 Requires<[IsWin64]>, Sched<[WriteJump]>;
294 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
295 isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1,
296 SchedRW = [WriteJump] in {
297 def TCRETURNdi64 : PseudoI<(outs),
298 (ins i64i32imm_pcrel:$dst, i32imm:$offset),
300 def TCRETURNri64 : PseudoI<(outs),
301 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
303 def TCRETURNmi64 : PseudoI<(outs),
304 (ins i64mem_TC:$dst, i32imm:$offset), []>;
306 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
307 (ins i64i32imm_pcrel:$dst),
308 "jmp\t$dst # TAILCALL", [], IIC_JMP_REL>;
309 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
310 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
313 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
314 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;