1 //===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 jump, return, call, and related instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Control Flow Instructions.
18 // Return instructions.
20 // The X86retflag return instructions are variadic because we may add ST0 and
21 // ST1 arguments when returning values on the x87 stack.
22 let isTerminator = 1, isReturn = 1, isBarrier = 1,
23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
24 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
25 "ret{l}", [(X86retflag 0)], IIC_RET>, OpSize32,
26 Requires<[Not64BitMode]>;
27 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
28 "ret{q}", [(X86retflag 0)], IIC_RET>, OpSize32,
29 Requires<[In64BitMode]>;
30 def RETW : I <0xC3, RawFrm, (outs), (ins),
32 [], IIC_RET>, OpSize16;
33 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
35 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32,
36 Requires<[Not64BitMode]>;
37 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
39 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32,
40 Requires<[In64BitMode]>;
41 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
43 [], IIC_RET_IMM>, OpSize16;
44 def LRETL : I <0xCB, RawFrm, (outs), (ins),
45 "{l}ret{l|f}", [], IIC_RET>, OpSize32;
46 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
47 "{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>;
48 def LRETW : I <0xCB, RawFrm, (outs), (ins),
49 "{l}ret{w|f}", [], IIC_RET>, OpSize16;
50 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
51 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32;
52 def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
53 "{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>;
54 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
55 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16;
57 // The machine return from interrupt instruction, but sometimes we need to
58 // perform a post-epilogue stack adjustment. Codegen emits the pseudo form
59 // which expands to include an SP adjustment if necessary.
60 def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>,
62 def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", [],
64 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", [],
65 IIC_IRET>, Requires<[In64BitMode]>;
66 let isCodeGenOnly = 1 in
67 def IRET : PseudoI<(outs), (ins i16imm:$adj), [(X86iret timm:$adj)]>;
71 // Unconditional branches.
72 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
73 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
74 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
75 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
76 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst),
77 "jmp\t$dst", [], IIC_JMP_REL>, OpSize16;
78 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst),
79 "jmp\t$dst", [], IIC_JMP_REL>, OpSize32;
83 // Conditional Branches.
84 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
85 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
86 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
87 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>;
88 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
89 def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget16:$dst), asm,
90 [], IIC_Jcc>, OpSize16, TB;
91 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget32:$dst), asm,
92 [], IIC_Jcc>, TB, OpSize32;
97 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
98 defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>;
99 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
100 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
101 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
102 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
103 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
104 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
105 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
106 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
107 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
108 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
109 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
110 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
111 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
112 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
114 // jcx/jecx/jrcx instructions.
115 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
116 // These are the 32-bit versions of this instruction for the asmparser. In
117 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
120 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
121 "jcxz\t$dst", [], IIC_JCXZ>, AdSize16,
122 Requires<[Not64BitMode]>;
124 def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
125 "jecxz\t$dst", [], IIC_JCXZ>, AdSize32;
128 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
129 "jrcxz\t$dst", [], IIC_JCXZ>, AdSize64,
130 Requires<[In64BitMode]>;
134 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
135 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
136 [(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
137 OpSize16, Sched<[WriteJump]>;
138 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
139 [(brind (loadi16 addr:$dst))], IIC_JMP_MEM>,
140 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
142 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
143 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
144 OpSize32, Sched<[WriteJump]>;
145 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
146 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
147 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>;
149 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
150 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
152 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
153 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>,
154 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
156 let Predicates = [Not64BitMode] in {
157 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
158 (ins i16imm:$off, i16imm:$seg),
159 "ljmp{w}\t$seg, $off", [],
160 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
161 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
162 (ins i32imm:$off, i16imm:$seg),
163 "ljmp{l}\t$seg, $off", [],
164 IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
166 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
167 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
170 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
171 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
172 Sched<[WriteJumpLd]>;
173 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
174 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize32,
175 Sched<[WriteJumpLd]>;
180 let SchedRW = [WriteJump] in {
181 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
182 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
183 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
186 //===----------------------------------------------------------------------===//
187 // Call Instructions...
190 // All calls clobber the non-callee saved registers. ESP is marked as
191 // a use to prevent stack-pointer assignments that appear immediately
192 // before calls from potentially appearing dead. Uses for argument
193 // registers are added manually.
194 let Uses = [ESP] in {
195 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
196 (outs), (ins i32imm_pcrel:$dst),
197 "call{l}\t$dst", [], IIC_CALL_RI>, OpSize32,
198 Requires<[Not64BitMode]>, Sched<[WriteJump]>;
199 let hasSideEffects = 0 in
200 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
201 (outs), (ins i16imm_pcrel:$dst),
202 "call{w}\t$dst", [], IIC_CALL_RI>, OpSize16,
204 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
205 "call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>,
206 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
207 def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
208 "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))],
209 IIC_CALL_MEM>, OpSize16,
210 Requires<[Not64BitMode,FavorMemIndirectCall]>,
211 Sched<[WriteJumpLd]>;
212 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
213 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
214 OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
215 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
216 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
217 IIC_CALL_MEM>, OpSize32,
218 Requires<[Not64BitMode,FavorMemIndirectCall]>,
219 Sched<[WriteJumpLd]>;
221 let Predicates = [Not64BitMode] in {
222 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
223 (ins i16imm:$off, i16imm:$seg),
224 "lcall{w}\t$seg, $off", [],
225 IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
226 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
227 (ins i32imm:$off, i16imm:$seg),
228 "lcall{l}\t$seg, $off", [],
229 IIC_CALL_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
232 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
233 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
234 Sched<[WriteJumpLd]>;
235 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
236 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize32,
237 Sched<[WriteJumpLd]>;
243 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
244 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
245 let Uses = [ESP] in {
246 def TCRETURNdi : PseudoI<(outs),
247 (ins i32imm_pcrel:$dst, i32imm:$offset), []>;
248 def TCRETURNri : PseudoI<(outs),
249 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
251 def TCRETURNmi : PseudoI<(outs),
252 (ins i32mem_TC:$dst, i32imm:$offset), []>;
254 // FIXME: The should be pseudo instructions that are lowered when going to
256 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
257 (ins i32imm_pcrel:$dst),
260 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
261 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
263 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
264 "jmp{l}\t{*}$dst", [], IIC_JMP_MEM>;
268 //===----------------------------------------------------------------------===//
269 // Call Instructions...
272 // RSP is marked as a use to prevent stack-pointer assignments that appear
273 // immediately before calls from potentially appearing dead. Uses for argument
274 // registers are added manually.
275 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
276 // NOTE: this pattern doesn't match "X86call imm", because we do not know
277 // that the offset between an arbitrary immediate and the call will fit in
278 // the 32-bit pcrel field that we have.
279 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
280 (outs), (ins i64i32imm_pcrel:$dst),
281 "call{q}\t$dst", [], IIC_CALL_RI>, OpSize32,
282 Requires<[In64BitMode]>;
283 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
284 "call{q}\t{*}$dst", [(X86call GR64:$dst)],
286 Requires<[In64BitMode]>;
287 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
288 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
290 Requires<[In64BitMode,FavorMemIndirectCall]>;
292 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
293 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
296 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
297 isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1,
298 SchedRW = [WriteJump] in {
299 def TCRETURNdi64 : PseudoI<(outs),
300 (ins i64i32imm_pcrel:$dst, i32imm:$offset),
302 def TCRETURNri64 : PseudoI<(outs),
303 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
305 def TCRETURNmi64 : PseudoI<(outs),
306 (ins i64mem_TC:$dst, i32imm:$offset), []>;
308 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst),
309 "jmp\t$dst", [], IIC_JMP_REL>;
310 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
311 "jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
314 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
315 "jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
317 // Win64 wants jumps leaving the function to have a REX_W prefix.
318 let hasREX_WPrefix = 1 in {
319 def TAILJMPd64_REX : Ii32PCRel<0xE9, RawFrm, (outs),
320 (ins i64i32imm_pcrel:$dst),
321 "rex64 jmp\t$dst", [], IIC_JMP_REL>;
322 def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
323 "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;
326 def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
327 "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>;