1 //===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 jump, return, call, and related instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Control Flow Instructions.
18 // Return instructions.
19 let isTerminator = 1, isReturn = 1, isBarrier = 1,
20 hasCtrlDep = 1, FPForm = SpecialFP in {
21 def RET : I <0xC3, RawFrm, (outs), (ins),
23 [(X86retflag 0)], IIC_RET>;
24 def RETW : I <0xC3, RawFrm, (outs), (ins),
27 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
29 [(X86retflag timm:$amt)], IIC_RET_IMM>;
30 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
32 [], IIC_RET_IMM>, OpSize;
33 def LRETL : I <0xCB, RawFrm, (outs), (ins),
34 "{l}ret{l|f}", [], IIC_RET>;
35 def LRETW : I <0xCB, RawFrm, (outs), (ins),
36 "{l}ret{w|f}", [], IIC_RET>, OpSize;
37 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
38 "{l}ret{q|f}", [], IIC_RET>;
39 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
40 "{l}ret{l|f}\t$amt", [], IIC_RET>;
41 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
42 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
45 // Unconditional branches.
46 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
47 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
48 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
49 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
50 "jmp\t$dst", [], IIC_JMP_REL>;
51 // FIXME : Intel syntax for JMP64pcrel32 such that it is not ambiguious
53 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
54 "jmpq\t$dst", [], IIC_JMP_REL>;
57 // Conditional Branches.
58 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
59 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
60 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
62 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
63 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB;
67 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
68 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
69 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
70 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
71 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
72 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
73 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
74 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
75 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
76 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
77 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
78 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
79 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
80 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
81 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
82 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
84 // jcx/jecx/jrcx instructions.
85 let isBranch = 1, isTerminator = 1 in {
86 // These are the 32-bit versions of this instruction for the asmparser. In
87 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
90 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
91 "jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In32BitMode]>;
93 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
94 "jecxz\t$dst", [], IIC_JCXZ>, Requires<[In32BitMode]>;
96 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
97 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version
100 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
101 "jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>;
103 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
104 "jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>;
108 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
109 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
110 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>;
111 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
112 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, Requires<[In32BitMode]>;
114 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
115 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>;
116 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
117 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, Requires<[In64BitMode]>;
119 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
120 (ins i16imm:$off, i16imm:$seg),
121 "ljmp{w}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>, OpSize;
122 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
123 (ins i32imm:$off, i16imm:$seg),
124 "ljmp{l}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>;
125 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
126 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
128 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
129 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize;
130 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
131 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
137 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
138 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
139 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
141 //===----------------------------------------------------------------------===//
142 // Call Instructions...
145 // All calls clobber the non-callee saved registers. ESP is marked as
146 // a use to prevent stack-pointer assignments that appear immediately
147 // before calls from potentially appearing dead. Uses for argument
148 // registers are added manually.
149 let Uses = [ESP] in {
150 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
151 (outs), (ins i32imm_pcrel:$dst),
152 "call{l}\t$dst", [], IIC_CALL_RI>, Requires<[In32BitMode]>;
153 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
154 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
155 Requires<[In32BitMode]>;
156 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
157 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], IIC_CALL_MEM>,
158 Requires<[In32BitMode]>;
160 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
161 (ins i16imm:$off, i16imm:$seg),
162 "lcall{w}\t{$seg, $off|$off, $seg}", [],
163 IIC_CALL_FAR_PTR>, OpSize;
164 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
165 (ins i32imm:$off, i16imm:$seg),
166 "lcall{l}\t{$seg, $off|$off, $seg}", [],
169 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
170 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize;
171 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
172 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
174 // callw for 16 bit code for the assembler.
175 let isAsmParserOnly = 1 in
176 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
177 (outs), (ins i16imm_pcrel:$dst),
178 "callw\t$dst", []>, OpSize;
184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
186 let Uses = [ESP] in {
187 def TCRETURNdi : PseudoI<(outs),
188 (ins i32imm_pcrel:$dst, i32imm:$offset), []>;
189 def TCRETURNri : PseudoI<(outs),
190 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
192 def TCRETURNmi : PseudoI<(outs),
193 (ins i32mem_TC:$dst, i32imm:$offset), []>;
195 // FIXME: The should be pseudo instructions that are lowered when going to
197 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
198 (ins i32imm_pcrel:$dst),
199 "jmp\t$dst # TAILCALL",
201 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
202 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
204 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
205 "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
209 //===----------------------------------------------------------------------===//
210 // Call Instructions...
213 // RSP is marked as a use to prevent stack-pointer assignments that appear
214 // immediately before calls from potentially appearing dead. Uses for argument
215 // registers are added manually.
216 let isCall = 1, Uses = [RSP] in {
217 // NOTE: this pattern doesn't match "X86call imm", because we do not know
218 // that the offset between an arbitrary immediate and the call will fit in
219 // the 32-bit pcrel field that we have.
220 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
221 (outs), (ins i64i32imm_pcrel:$dst),
222 "call{q}\t$dst", [], IIC_CALL_RI>,
223 Requires<[In64BitMode]>;
224 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
225 "call{q}\t{*}$dst", [(X86call GR64:$dst)],
227 Requires<[In64BitMode]>;
228 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
229 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
231 Requires<[In64BitMode]>;
233 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
234 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
237 let isCall = 1, isCodeGenOnly = 1 in
238 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
239 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
240 let Defs = [RAX, R10, R11, RSP, EFLAGS],
242 def W64ALLOCA : Ii32PCRel<0xE8, RawFrm,
243 (outs), (ins i64i32imm_pcrel:$dst),
244 "call{q}\t$dst", [], IIC_CALL_RI>,
248 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
251 usesCustomInserter = 1 in {
252 def TCRETURNdi64 : PseudoI<(outs),
253 (ins i64i32imm_pcrel:$dst, i32imm:$offset),
255 def TCRETURNri64 : PseudoI<(outs),
256 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
258 def TCRETURNmi64 : PseudoI<(outs),
259 (ins i64mem_TC:$dst, i32imm:$offset), []>;
261 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
262 (ins i64i32imm_pcrel:$dst),
263 "jmp\t$dst # TAILCALL", [], IIC_JMP_REL>;
264 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
265 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
268 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
269 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;