1 //===- X86InstrControl.td - Control Flow Instructions ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 jump, return, call, and related instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Control Flow Instructions.
18 // Return instructions.
19 let isTerminator = 1, isReturn = 1, isBarrier = 1,
20 hasCtrlDep = 1, FPForm = SpecialFP in {
21 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
24 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
26 [(X86retflag timm:$amt)]>;
27 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
29 [(X86retflag timm:$amt)]>, OpSize;
30 def LRETL : I <0xCB, RawFrm, (outs), (ins),
32 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
34 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
36 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
37 "lretw\t$amt", []>, OpSize;
40 // Unconditional branches.
41 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
42 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
43 "jmp\t$dst", [(br bb:$dst)]>;
44 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
46 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
50 // Conditional Branches.
51 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
52 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
53 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
54 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
55 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
59 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
60 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
61 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
62 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
63 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
64 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
65 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
66 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
67 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
68 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
69 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
70 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
71 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
72 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
73 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
74 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
76 // jcx/jecx/jrcx instructions.
77 let isAsmParserOnly = 1, isBranch = 1, isTerminator = 1 in {
78 // These are the 32-bit versions of this instruction for the asmparser. In
79 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
82 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
83 "jcxz\t$dst", []>, AdSize, Requires<[In32BitMode]>;
85 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
86 "jecxz\t$dst", []>, Requires<[In32BitMode]>;
88 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
89 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version
92 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
93 "jecxz\t$dst", []>, AdSize, Requires<[In64BitMode]>;
95 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
96 "jrcxz\t$dst", []>, Requires<[In64BitMode]>;
100 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
101 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
102 [(brind GR32:$dst)]>, Requires<[In32BitMode]>;
103 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
104 [(brind (loadi32 addr:$dst))]>, Requires<[In32BitMode]>;
106 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
107 [(brind GR64:$dst)]>, Requires<[In64BitMode]>;
108 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
109 [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>;
111 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
112 (ins i16imm:$off, i16imm:$seg),
113 "ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
114 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
115 (ins i32imm:$off, i16imm:$seg),
116 "ljmp{l}\t{$seg, $off|$off, $seg}", []>;
117 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
118 "ljmp{q}\t{*}$dst", []>;
120 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
121 "ljmp{w}\t{*}$dst", []>, OpSize;
122 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
123 "ljmp{l}\t{*}$dst", []>;
129 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
130 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
131 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
133 //===----------------------------------------------------------------------===//
134 // Call Instructions...
137 // All calls clobber the non-callee saved registers. ESP is marked as
138 // a use to prevent stack-pointer assignments that appear immediately
139 // before calls from potentially appearing dead. Uses for argument
140 // registers are added manually.
141 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
142 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
143 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
144 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
146 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
147 (outs), (ins i32imm_pcrel:$dst,variable_ops),
148 "call{l}\t$dst", []>, Requires<[In32BitMode]>;
149 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
150 "call{l}\t{*}$dst", [(X86call GR32:$dst)]>,
151 Requires<[In32BitMode]>;
152 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
153 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>,
154 Requires<[In32BitMode]>;
156 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
157 (ins i16imm:$off, i16imm:$seg),
158 "lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
159 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
160 (ins i32imm:$off, i16imm:$seg),
161 "lcall{l}\t{$seg, $off|$off, $seg}", []>;
163 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
164 "lcall{w}\t{*}$dst", []>, OpSize;
165 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
166 "lcall{l}\t{*}$dst", []>;
168 // callw for 16 bit code for the assembler.
169 let isAsmParserOnly = 1 in
170 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
171 (outs), (ins i16imm_pcrel:$dst, variable_ops),
172 "callw\t$dst", []>, OpSize;
178 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
180 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
181 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
182 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
183 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
185 def TCRETURNdi : I<0, Pseudo, (outs),
186 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
187 "#TC_RETURN $dst $offset", []>;
188 def TCRETURNri : I<0, Pseudo, (outs),
189 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
190 "#TC_RETURN $dst $offset", []>;
192 def TCRETURNmi : I<0, Pseudo, (outs),
193 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
194 "#TC_RETURN $dst $offset", []>;
196 // FIXME: The should be pseudo instructions that are lowered when going to
198 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
199 (ins i32imm_pcrel:$dst, variable_ops),
200 "jmp\t$dst # TAILCALL",
202 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
203 "", []>; // FIXME: Remove encoding when JIT is dead.
205 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
206 "jmp{l}\t{*}$dst # TAILCALL", []>;
210 //===----------------------------------------------------------------------===//
211 // Call Instructions...
214 // All calls clobber the non-callee saved registers. RSP is marked as
215 // a use to prevent stack-pointer assignments that appear immediately
216 // before calls from potentially appearing dead. Uses for argument
217 // registers are added manually.
218 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
219 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
220 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
221 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
222 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
225 // NOTE: this pattern doesn't match "X86call imm", because we do not know
226 // that the offset between an arbitrary immediate and the call will fit in
227 // the 32-bit pcrel field that we have.
228 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
229 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
230 "call{q}\t$dst", []>,
231 Requires<[In64BitMode, NotWin64]>;
232 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
233 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
234 Requires<[In64BitMode, NotWin64]>;
235 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
236 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
237 Requires<[In64BitMode, NotWin64]>;
239 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
240 "lcall{q}\t{*}$dst", []>;
243 // FIXME: We need to teach codegen about single list of call-clobbered
245 let isCall = 1, isCodeGenOnly = 1 in
246 // All calls clobber the non-callee saved registers. RSP is marked as
247 // a use to prevent stack-pointer assignments that appear immediately
248 // before calls from potentially appearing dead. Uses for argument
249 // registers are added manually.
250 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
251 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
252 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
253 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
255 def WINCALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
256 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
257 "call{q}\t$dst", []>,
259 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
261 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
262 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst,variable_ops),
264 [(X86call (loadi64 addr:$dst))]>,
269 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
271 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
272 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
273 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
274 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
275 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
277 def TCRETURNdi64 : I<0, Pseudo, (outs),
278 (ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
279 "#TC_RETURN $dst $offset", []>;
280 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64_TC:$dst, i32imm:$offset,
282 "#TC_RETURN $dst $offset", []>;
284 def TCRETURNmi64 : I<0, Pseudo, (outs),
285 (ins i64mem_TC:$dst, i32imm:$offset, variable_ops),
286 "#TC_RETURN $dst $offset", []>;
288 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
289 (ins i64i32imm_pcrel:$dst, variable_ops),
290 "jmp\t$dst # TAILCALL", []>;
291 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64_TC:$dst, variable_ops),
292 "jmp{q}\t{*}$dst # TAILCALL", []>;
295 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
296 "jmp{q}\t{*}$dst # TAILCALL", []>;