1 //===- X86InstrControl.td - Control Flow Instructions ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 jump, return, call, and related instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Control Flow Instructions.
18 // Return instructions.
19 let isTerminator = 1, isReturn = 1, isBarrier = 1,
20 hasCtrlDep = 1, FPForm = SpecialFP in {
21 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
24 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
26 [(X86retflag timm:$amt)]>;
27 def LRET : I <0xCB, RawFrm, (outs), (ins),
29 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
33 // Unconditional branches.
34 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
35 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
36 "jmp\t$dst", [(br bb:$dst)]>;
37 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
39 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
43 // Conditional Branches.
44 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
45 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
46 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
47 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
48 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
52 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
53 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
54 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
55 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
56 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
57 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
58 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
59 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
60 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
61 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
62 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
63 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
64 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
65 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
66 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
67 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
69 // jcx/jecx/jrcx instructions.
70 let isAsmParserOnly = 1, isBranch = 1, isTerminator = 1 in {
71 // These are the 32-bit versions of this instruction for the asmparser. In
72 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
75 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
76 "jcxz\t$dst", []>, AdSize, Requires<[In32BitMode]>;
78 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
79 "jecxz\t$dst", []>, Requires<[In32BitMode]>;
81 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
82 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version
85 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
86 "jecxz\t$dst", []>, AdSize, Requires<[In64BitMode]>;
88 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
89 "jrcxz\t$dst", []>, Requires<[In64BitMode]>;
93 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
94 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
95 [(brind GR32:$dst)]>, Requires<[In32BitMode]>;
96 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
97 [(brind (loadi32 addr:$dst))]>, Requires<[In32BitMode]>;
99 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
100 [(brind GR64:$dst)]>, Requires<[In64BitMode]>;
101 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
102 [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>;
104 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
105 (ins i16imm:$off, i16imm:$seg),
106 "ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
107 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
108 (ins i32imm:$off, i16imm:$seg),
109 "ljmp{l}\t{$seg, $off|$off, $seg}", []>;
110 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
111 "ljmp{q}\t{*}$dst", []>;
113 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
114 "ljmp{w}\t{*}$dst", []>, OpSize;
115 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
116 "ljmp{l}\t{*}$dst", []>;
122 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
123 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
124 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
126 //===----------------------------------------------------------------------===//
127 // Call Instructions...
130 // All calls clobber the non-callee saved registers. ESP is marked as
131 // a use to prevent stack-pointer assignments that appear immediately
132 // before calls from potentially appearing dead. Uses for argument
133 // registers are added manually.
134 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
135 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
136 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
137 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
139 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
140 (outs), (ins i32imm_pcrel:$dst,variable_ops),
141 "call{l}\t$dst", []>, Requires<[In32BitMode]>;
142 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
143 "call{l}\t{*}$dst", [(X86call GR32:$dst)]>,
144 Requires<[In32BitMode]>;
145 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
146 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>,
147 Requires<[In32BitMode]>;
149 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
150 (ins i16imm:$off, i16imm:$seg),
151 "lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
152 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
153 (ins i32imm:$off, i16imm:$seg),
154 "lcall{l}\t{$seg, $off|$off, $seg}", []>;
156 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
157 "lcall{w}\t{*}$dst", []>, OpSize;
158 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
159 "lcall{l}\t{*}$dst", []>;
161 // callw for 16 bit code for the assembler.
162 let isAsmParserOnly = 1 in
163 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
164 (outs), (ins i16imm_pcrel:$dst, variable_ops),
165 "callw\t$dst", []>, OpSize;
171 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
173 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
174 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
175 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
176 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
178 def TCRETURNdi : I<0, Pseudo, (outs),
179 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
180 "#TC_RETURN $dst $offset", []>;
181 def TCRETURNri : I<0, Pseudo, (outs),
182 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
183 "#TC_RETURN $dst $offset", []>;
185 def TCRETURNmi : I<0, Pseudo, (outs),
186 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
187 "#TC_RETURN $dst $offset", []>;
189 // FIXME: The should be pseudo instructions that are lowered when going to
191 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
192 (ins i32imm_pcrel:$dst, variable_ops),
193 "jmp\t$dst # TAILCALL",
195 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
196 "", []>; // FIXME: Remove encoding when JIT is dead.
198 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
199 "jmp{l}\t{*}$dst # TAILCALL", []>;
203 //===----------------------------------------------------------------------===//
204 // Call Instructions...
207 // All calls clobber the non-callee saved registers. RSP is marked as
208 // a use to prevent stack-pointer assignments that appear immediately
209 // before calls from potentially appearing dead. Uses for argument
210 // registers are added manually.
211 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
212 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
213 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
214 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
215 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
218 // NOTE: this pattern doesn't match "X86call imm", because we do not know
219 // that the offset between an arbitrary immediate and the call will fit in
220 // the 32-bit pcrel field that we have.
221 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
222 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
223 "call{q}\t$dst", []>,
224 Requires<[In64BitMode, NotWin64]>;
225 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
226 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
227 Requires<[In64BitMode, NotWin64]>;
228 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
229 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
230 Requires<[In64BitMode, NotWin64]>;
232 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
233 "lcall{q}\t{*}$dst", []>;
236 // FIXME: We need to teach codegen about single list of call-clobbered
238 let isCall = 1, isCodeGenOnly = 1 in
239 // All calls clobber the non-callee saved registers. RSP is marked as
240 // a use to prevent stack-pointer assignments that appear immediately
241 // before calls from potentially appearing dead. Uses for argument
242 // registers are added manually.
243 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
244 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
245 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
246 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
248 def WINCALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
249 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
250 "call{q}\t$dst", []>,
252 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
254 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
255 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst,variable_ops),
257 [(X86call (loadi64 addr:$dst))]>,
262 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
264 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
265 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
266 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
267 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
268 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
270 def TCRETURNdi64 : I<0, Pseudo, (outs),
271 (ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
272 "#TC_RETURN $dst $offset", []>;
273 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64_TC:$dst, i32imm:$offset,
275 "#TC_RETURN $dst $offset", []>;
277 def TCRETURNmi64 : I<0, Pseudo, (outs),
278 (ins i64mem_TC:$dst, i32imm:$offset, variable_ops),
279 "#TC_RETURN $dst $offset", []>;
281 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
282 (ins i64i32imm_pcrel:$dst, variable_ops),
283 "jmp\t$dst # TAILCALL", []>;
284 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64_TC:$dst, variable_ops),
285 "jmp{q}\t{*}$dst # TAILCALL", []>;
288 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
289 "jmp{q}\t{*}$dst # TAILCALL", []>;