1 //===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the sign and zero extension operations.
12 //===----------------------------------------------------------------------===//
14 let neverHasSideEffects = 1 in {
15 let Defs = [AX], Uses = [AL] in
16 def CBW : I<0x98, RawFrm, (outs), (ins),
17 "{cbtw|cbw}", [], IIC_CBW>, OpSize16; // AX = signext(AL)
18 let Defs = [EAX], Uses = [AX] in
19 def CWDE : I<0x98, RawFrm, (outs), (ins),
20 "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
22 let Defs = [AX,DX], Uses = [AX] in
23 def CWD : I<0x99, RawFrm, (outs), (ins),
24 "{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX)
25 let Defs = [EAX,EDX], Uses = [EAX] in
26 def CDQ : I<0x99, RawFrm, (outs), (ins),
27 "{cltd|cdq}", [], IIC_CBW>, OpSize32; // EDX:EAX = signext(EAX)
30 let Defs = [RAX], Uses = [EAX] in
31 def CDQE : RI<0x98, RawFrm, (outs), (ins),
32 "{cltq|cdqe}", [], IIC_CBW>; // RAX = signext(EAX)
34 let Defs = [RAX,RDX], Uses = [RAX] in
35 def CQO : RI<0x99, RawFrm, (outs), (ins),
36 "{cqto|cqo}", [], IIC_CBW>; // RDX:RAX = signext(RAX)
41 // Sign/Zero extenders
42 let neverHasSideEffects = 1 in {
43 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
44 "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>,
45 TB, OpSize16, Sched<[WriteALU]>;
47 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
48 "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_M8>,
49 TB, OpSize16, Sched<[WriteALULd]>;
50 } // neverHasSideEffects = 1
51 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
52 "movs{bl|x}\t{$src, $dst|$dst, $src}",
53 [(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB,
54 OpSize32, Sched<[WriteALU]>;
55 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
56 "movs{bl|x}\t{$src, $dst|$dst, $src}",
57 [(set GR32:$dst, (sextloadi32i8 addr:$src))], IIC_MOVSX>, TB,
58 OpSize32, Sched<[WriteALULd]>;
59 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
60 "movs{wl|x}\t{$src, $dst|$dst, $src}",
61 [(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB,
62 OpSize32, Sched<[WriteALU]>;
63 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
64 "movs{wl|x}\t{$src, $dst|$dst, $src}",
65 [(set GR32:$dst, (sextloadi32i16 addr:$src))], IIC_MOVSX>,
66 OpSize32, TB, Sched<[WriteALULd]>;
68 let neverHasSideEffects = 1 in {
69 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
70 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_R8>,
71 TB, OpSize16, Sched<[WriteALU]>;
73 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
74 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_M8>,
75 TB, OpSize16, Sched<[WriteALULd]>;
76 } // neverHasSideEffects = 1
77 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
78 "movz{bl|x}\t{$src, $dst|$dst, $src}",
79 [(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB,
80 OpSize32, Sched<[WriteALU]>;
81 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
82 "movz{bl|x}\t{$src, $dst|$dst, $src}",
83 [(set GR32:$dst, (zextloadi32i8 addr:$src))], IIC_MOVZX>, TB,
84 OpSize32, Sched<[WriteALULd]>;
85 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
86 "movz{wl|x}\t{$src, $dst|$dst, $src}",
87 [(set GR32:$dst, (zext GR16:$src))], IIC_MOVZX>, TB,
88 OpSize32, Sched<[WriteALU]>;
89 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
90 "movz{wl|x}\t{$src, $dst|$dst, $src}",
91 [(set GR32:$dst, (zextloadi32i16 addr:$src))], IIC_MOVZX>,
92 TB, OpSize32, Sched<[WriteALULd]>;
94 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
95 // except that they use GR32_NOREX for the output operand register class
96 // instead of GR32. This allows them to operate on h registers on x86-64.
97 let neverHasSideEffects = 1, isCodeGenOnly = 1 in {
98 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
99 (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src),
100 "movz{bl|x}\t{$src, $dst|$dst, $src}",
101 [], IIC_MOVZX>, TB, Sched<[WriteALU]>;
103 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
104 (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src),
105 "movz{bl|x}\t{$src, $dst|$dst, $src}",
106 [], IIC_MOVZX>, TB, Sched<[WriteALULd]>;
109 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
110 // operand, which makes it a rare instruction with an 8-bit register
111 // operand that can never access an h register. If support for h registers
112 // were generalized, this would require a special register class.
113 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
114 "movs{bq|x}\t{$src, $dst|$dst, $src}",
115 [(set GR64:$dst, (sext GR8:$src))], IIC_MOVSX>, TB,
117 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
118 "movs{bq|x}\t{$src, $dst|$dst, $src}",
119 [(set GR64:$dst, (sextloadi64i8 addr:$src))], IIC_MOVSX>,
120 TB, Sched<[WriteALULd]>;
121 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
122 "movs{wq|x}\t{$src, $dst|$dst, $src}",
123 [(set GR64:$dst, (sext GR16:$src))], IIC_MOVSX>, TB,
125 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
126 "movs{wq|x}\t{$src, $dst|$dst, $src}",
127 [(set GR64:$dst, (sextloadi64i16 addr:$src))], IIC_MOVSX>,
128 TB, Sched<[WriteALULd]>;
129 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
130 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
131 [(set GR64:$dst, (sext GR32:$src))], IIC_MOVSX>,
133 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
134 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
135 [(set GR64:$dst, (sextloadi64i32 addr:$src))], IIC_MOVSX>,
138 // movzbq and movzwq encodings for the disassembler
139 def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
140 "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
141 TB, Sched<[WriteALU]>;
142 def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src),
143 "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
144 TB, Sched<[WriteALULd]>;
145 def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
146 "movz{wq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
147 TB, Sched<[WriteALU]>;
148 def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
149 "movz{wq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
150 TB, Sched<[WriteALULd]>;
152 // 64-bit zero-extension patterns use SUBREG_TO_REG and an operation writing a
154 def : Pat<(i64 (zext GR8:$src)),
155 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8:$src), sub_32bit)>;
156 def : Pat<(zextloadi64i8 addr:$src),
157 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
159 def : Pat<(i64 (zext GR16:$src)),
160 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16:$src), sub_32bit)>;
161 def : Pat<(zextloadi64i16 addr:$src),
162 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
164 // The preferred way to do 32-bit-to-64-bit zero extension on x86-64 is to use a
165 // SUBREG_TO_REG to utilize implicit zero-extension, however this isn't possible
166 // when the 32-bit value is defined by a truncate or is copied from something
167 // where the high bits aren't necessarily all zero. In such cases, we fall back
168 // to these explicit zext instructions.
169 def : Pat<(i64 (zext GR32:$src)),
170 (SUBREG_TO_REG (i64 0), (MOV32rr GR32:$src), sub_32bit)>;
171 def : Pat<(i64 (zextloadi64i32 addr:$src)),
172 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;