1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 let Constraints = "$src1 = $dst" in {
19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr> {
20 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
21 (ins VR128:$src1, VR128:$src2, VR128:$src3),
22 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
25 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
26 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
27 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
29 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
30 (ins VR256:$src1, VR256:$src2, VR256:$src3),
31 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
34 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
35 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
36 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
40 // Intrinsic for 132 pattern
41 multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
42 PatFrag MemFrag128, PatFrag MemFrag256,
43 Intrinsic Int128, Intrinsic Int256> {
44 def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
45 (ins VR128:$src1, VR128:$src2, VR128:$src3),
46 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
47 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src3, VR128:$src2))]>;
48 def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
49 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
50 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
52 (Int128 VR128:$src1, (MemFrag128 addr:$src3), VR128:$src2))]>;
53 def rY_Int : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
54 (ins VR256:$src1, VR256:$src2, VR256:$src3),
55 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
56 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src3, VR256:$src2))]>;
57 def mY_Int : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
58 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
59 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
61 (Int256 VR256:$src1, (MemFrag256 addr:$src3), VR256:$src2))]>;
65 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
66 string OpcodeStr, string PackTy,
67 PatFrag MemFrag128, PatFrag MemFrag256,
68 Intrinsic Int128, Intrinsic Int256> {
69 defm r132 : fma3p_rm_int <opc132, !strconcat(OpcodeStr,
70 !strconcat("132", PackTy)), MemFrag128, MemFrag256,
72 defm r132 : fma3p_rm <opc132, !strconcat(OpcodeStr, !strconcat("132", PackTy))>;
73 defm r213 : fma3p_rm <opc213, !strconcat(OpcodeStr, !strconcat("213", PackTy))>;
74 defm r231 : fma3p_rm <opc231, !strconcat(OpcodeStr, !strconcat("231", PackTy))>;
78 let ExeDomain = SSEPackedSingle in {
79 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", memopv4f32,
80 memopv8f32, int_x86_fma4_vfmadd_ps, int_x86_fma4_vfmadd_ps_256>;
81 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", memopv4f32,
82 memopv8f32, int_x86_fma4_vfmsub_ps, int_x86_fma4_vfmsub_ps_256>;
83 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
84 memopv4f32, memopv8f32, int_x86_fma4_vfmaddsub_ps,
85 int_x86_fma4_vfmaddsub_ps_256>;
86 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
87 memopv4f32, memopv8f32, int_x86_fma4_vfmsubadd_ps,
88 int_x86_fma4_vfmaddsub_ps_256>;
91 let ExeDomain = SSEPackedDouble in {
92 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", memopv2f64,
93 memopv4f64, int_x86_fma4_vfmadd_pd, int_x86_fma4_vfmadd_pd_256>, VEX_W;
94 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", memopv2f64,
95 memopv4f64, int_x86_fma4_vfmsub_pd, int_x86_fma4_vfmsub_pd_256>, VEX_W;
96 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", memopv2f64,
97 memopv4f64, int_x86_fma4_vfmaddsub_pd, int_x86_fma4_vfmaddsub_pd_256>, VEX_W;
98 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", memopv2f64,
99 memopv4f64, int_x86_fma4_vfmsubadd_pd, int_x86_fma4_vfmsubadd_pd_256>, VEX_W;
102 // Fused Negative Multiply-Add
103 let ExeDomain = SSEPackedSingle in {
104 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", memopv4f32,
105 memopv8f32, int_x86_fma4_vfnmadd_ps, int_x86_fma4_vfnmadd_ps_256>;
106 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", memopv4f32,
107 memopv8f32, int_x86_fma4_vfnmsub_ps, int_x86_fma4_vfnmsub_ps_256>;
109 let ExeDomain = SSEPackedDouble in {
110 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", memopv2f64,
111 memopv4f64, int_x86_fma4_vfnmadd_pd, int_x86_fma4_vfnmadd_pd_256>, VEX_W;
112 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", memopv2f64,
113 memopv4f64, int_x86_fma4_vfnmsub_pd, int_x86_fma4_vfnmsub_pd_256>, VEX_W;
116 let Predicates = [HasFMA3], AddedComplexity = 20 in {
118 // FP double precision ADD - 256
121 // FMA231: src1 = src2*src3 + src1
122 def : Pat<(v4f64 (fadd (fmul VR256:$src2, (memopv4f64 addr:$src3)), VR256:$src1)),
123 (VFMADDPDr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
125 // FMA231: src1 = src2*src3 + src1
126 def : Pat<(v4f64 (fadd (fmul VR256:$src2, VR256:$src3), VR256:$src1)),
127 (VFMADDPDr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
131 // FP double precision ADD - 128
135 // FMA231: src1 = src2*src3 + src1
136 def : Pat<(v2f64 (fadd (fmul VR128:$src2, (memopv2f64 addr:$src3)), VR128:$src1)),
137 (VFMADDPDr231m VR128:$src1, VR128:$src2, addr:$src3)>;
139 // FMA231: src1 = src2*src3 + src1
140 def : Pat<(v2f64 (fadd (fmul VR128:$src2, VR128:$src3), VR128:$src1)),
141 (VFMADDPDr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
144 // FP double precision SUB - 256
146 // FMA231: src1 = src2*src3 - src1
147 def : Pat<(v4f64 (fsub (fmul VR256:$src2, (memopv4f64 addr:$src3)), VR256:$src1)),
148 (VFMSUBPDr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
150 // FMA231: src1 = src2*src3 - src1
151 def : Pat<(v4f64 (fsub (fmul VR256:$src2, VR256:$src3), VR256:$src1)),
152 (VFMSUBPDr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
156 // FP double precision SUB - 128
159 // FMA231: src1 = src2*src3 - src1
160 def : Pat<(v2f64 (fsub (fmul VR128:$src2, (memopv2f64 addr:$src3)), VR128:$src1)),
161 (VFMSUBPDr231m VR128:$src1, VR128:$src2, addr:$src3)>;
163 // FMA231: src1 = src2*src3 - src1
164 def : Pat<(v2f64 (fsub (fmul VR128:$src2, VR128:$src3), VR128:$src1)),
165 (VFMSUBPDr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
168 // FP double precision FNMADD - 256
170 // FMA231: src1 = - src2*src3 + src1
171 def : Pat<(v4f64 (fsub VR256:$src1, (fmul VR256:$src2, (memopv4f64 addr:$src3)))),
172 (VFNMADDPDr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
174 // FMA231: src1 = - src2*src3 + src1
175 def : Pat<(v4f64 (fsub VR256:$src1, (fmul VR256:$src2, VR256:$src3))),
176 (VFNMADDPDr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
179 // FP double precision FNMADD - 128
182 // FMA231: src1 = - src2*src3 + src1
183 def : Pat<(v2f64 (fsub VR128:$src1, (fmul VR128:$src2, (memopv2f64 addr:$src3)))),
184 (VFNMADDPDr231m VR128:$src1, VR128:$src2, addr:$src3)>;
186 // FMA231: src1 = - src2*src3 + src1
187 def : Pat<(v2f64 (fsub VR128:$src1, (fmul VR128:$src2, VR128:$src3))),
188 (VFNMADDPDr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
191 // FP single precision ADD - 256
194 // FMA231: src1 = src2*src3 + src1
195 def : Pat<(v8f32 (fadd (fmul VR256:$src2, VR256:$src3), VR256:$src1)),
196 (VFMADDPSr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
198 // FMA213 : src1 = src2*src1 + src3
199 def : Pat<(v8f32 (fadd (fmul VR256:$src1, VR256:$src2), (memopv8f32 addr:$src3))),
200 (VFMADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
202 // FMA231: src1 = src2*src3 + src1
203 def : Pat<(v8f32 (fadd (fmul (memopv8f32 addr:$src3), VR256:$src2), VR256:$src1)),
204 (VFMADDPSr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
206 // FMA213: src1 = src2*src1 + src3
207 def : Pat<(v8f32 (fadd (fmul VR256:$src2, VR256:$src1), VR256:$src3)),
208 (VFMADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
211 // FP single precision ADD - 128
214 // FMA231 : src1 = src2*src3 + src1
215 def : Pat<(v4f32 (fadd (fmul VR128:$src2, (memopv4f32 addr:$src3)), VR128:$src1)),
216 (VFMADDPSr231m VR128:$src1, VR128:$src2, addr:$src3)>;
218 // FMA231 : src1 = src2*src3 + src1
219 def : Pat<(v4f32 (fadd (fmul VR128:$src2, VR128:$src3), VR128:$src1)),
220 (VFMADDPSr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
223 // FP single precision SUB - 256
225 // FMA231: src1 = src2*src3 - src1
226 def : Pat<(v8f32 (fsub (fmul VR256:$src2, (memopv8f32 addr:$src3)), VR256:$src1)),
227 (VFMSUBPSr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
229 // FMA231: src1 = src2*src3 - src1
230 def : Pat<(v8f32 (fsub (fmul VR256:$src2, VR256:$src3), VR256:$src1)),
231 (VFMSUBPSr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
234 // FP single precision SUB - 128
236 // FMA231 : src1 = src2*src3 - src1
237 def : Pat<(v4f32 (fsub (fmul VR128:$src2, (memopv4f32 addr:$src3)), VR128:$src1)),
238 (VFMSUBPSr231m VR128:$src1, VR128:$src2, addr:$src3)>;
240 // FMA231 : src1 = src2*src3 - src1
241 def : Pat<(v4f32 (fsub (fmul VR128:$src2, VR128:$src3), VR128:$src1)),
242 (VFMSUBPSr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
245 // FP single precision FNMADD - 256
247 // FMA231: src1 = - src2*src3 + src1
248 def : Pat<(v8f32 (fsub VR256:$src1, (fmul VR256:$src2, (memopv8f32 addr:$src3)))),
249 (VFNMADDPSr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
251 // FMA231: src1 = - src2*src3 + src1
252 def : Pat<(v8f32 (fsub VR256:$src1, (fmul VR256:$src2, VR256:$src3))),
253 (VFNMADDPSr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
256 // FP single precision FNMADD - 128
259 // FMA231 : src1 = src2*src3 - src1
260 def : Pat<(v4f32 (fsub VR128:$src1, (fmul VR128:$src2, (memopv4f32 addr:$src3)))),
261 (VFNMADDPSr231m VR128:$src1, VR128:$src2, addr:$src3)>;
263 // FMA231 : src1 = src2*src3 - src1
264 def : Pat<(v4f32 (fsub VR128:$src1, (fmul VR128:$src2, VR128:$src3))),
265 (VFNMADDPSr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
269 //------------------------------
271 //------------------------------
273 let Constraints = "$src1 = $dst" in {
274 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
276 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
277 (ins RC:$src1, RC:$src2, RC:$src3),
278 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
280 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
281 (ins RC:$src1, RC:$src2, x86memop:$src3),
282 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
286 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
287 RegisterClass RC, Intrinsic IntId> {
288 def r_Int : FMA3<opc, MRMSrcReg, (outs RC:$dst),
289 (ins RC:$src1, RC:$src2, RC:$src3),
290 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
291 [(set RC:$dst, (IntId RC:$src1, RC:$src3, RC:$src2))]>;
292 def m_Int : FMA3<opc, MRMSrcMem, (outs RC:$dst),
293 (ins RC:$src1, VR128:$src2, x86memop:$src3),
294 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
295 [(set RC:$dst, (IntId RC:$src1, (load addr:$src3), RC:$src2))]>;
299 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
300 string OpcodeStr, string PackTy, X86MemOperand MemOp,
301 RegisterClass RC, Intrinsic IntId> {
302 defm r132 : fma3s_rm <opc132, !strconcat(OpcodeStr,
303 !strconcat("132", PackTy)), MemOp, RC>;
304 defm r213 : fma3s_rm <opc213, !strconcat(OpcodeStr,
305 !strconcat("213", PackTy)), MemOp, RC>;
306 defm r231 : fma3s_rm <opc231, !strconcat(OpcodeStr,
307 !strconcat("231", PackTy)), MemOp, RC>;
308 defm r132_Int : fma3s_rm_int <opc132, !strconcat(OpcodeStr,
309 !strconcat("132", PackTy)), MemOp, VR128, IntId>;
312 defm VFMADDSS : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd", "ss", f32mem, FR32,
313 int_x86_fma4_vfmadd_ss>, VEX_LIG;
314 defm VFMADDSD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd", "sd", f64mem, FR64,
315 int_x86_fma4_vfmadd_sd>, VEX_W, VEX_LIG;
316 defm VFMSUBSS : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub", "ss", f32mem, FR32,
317 int_x86_fma4_vfmsub_ss>, VEX_LIG;
318 defm VFMSUBSD : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub", "sd", f64mem, FR64,
319 int_x86_fma4_vfmsub_sd>, VEX_W, VEX_LIG;
321 defm VFNMADDSS : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd", "ss", f32mem, FR32,
322 int_x86_fma4_vfnmadd_ss>, VEX_LIG;
323 defm VFNMADDSD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd", "sd", f64mem, FR64,
324 int_x86_fma4_vfnmadd_sd>, VEX_W, VEX_LIG;
325 defm VFNMSUBSS : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub", "ss", f32mem, FR32,
326 int_x86_fma4_vfnmsub_ss>, VEX_LIG;
327 defm VFNMSUBSD : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub", "sd", f64mem, FR64,
328 int_x86_fma4_vfnmsub_sd>, VEX_W, VEX_LIG;
331 let Predicates = [HasFMA3], AddedComplexity = 20 in {
338 // FMADD231 : src1 = src2*src3 + src1
339 def : Pat<(f32 (fadd (fmul FR32:$src2, FR32:$src3), FR32:$src1)),
340 (VFMADDSSr231r FR32:$src1, FR32:$src2, FR32:$src3)>;
342 def : Pat<(f32 (fadd (fmul FR32:$src2, (loadf32 addr:$src3)), FR32:$src1)),
343 (VFMADDSSr231m FR32:$src1, FR32:$src2, addr:$src3)>;
345 def : Pat<(f64 (fadd (fmul FR64:$src2, FR64:$src3), FR64:$src1)),
346 (VFMADDSDr231r FR64:$src1, FR64:$src2, FR64:$src3)>;
348 def : Pat<(f64 (fadd (fmul FR64:$src2, (loadf64 addr:$src3)), FR64:$src1)),
349 (VFMADDSDr231m FR64:$src1, FR64:$src2, addr:$src3)>;
354 // FP scalar SUB src2*src3 - src1
357 def : Pat<(f32 (fsub (fmul FR32:$src2, FR32:$src3), FR32:$src1)),
358 (VFMSUBSSr231r FR32:$src1, FR32:$src2, FR32:$src3)>;
360 def : Pat<(f32 (fsub (fmul FR32:$src2, (loadf32 addr:$src3)), FR32:$src1)),
361 (VFMSUBSSr231m FR32:$src1, FR32:$src2, addr:$src3)>;
363 def : Pat<(f64 (fsub (fmul FR64:$src2, FR64:$src3), FR64:$src1)),
364 (VFMSUBSDr231r FR64:$src1, FR64:$src2, FR64:$src3)>;
366 def : Pat<(f64 (fsub (fmul FR64:$src2, (loadf64 addr:$src3)), FR64:$src1)),
367 (VFMSUBSDr231m FR64:$src1, FR64:$src2, addr:$src3)>;
370 // FP scalar NADD src1 - src2*src3
373 def : Pat<(f32 (fsub FR32:$src1, (fmul FR32:$src2, FR32:$src3))),
374 (VFNMADDSSr231r FR32:$src1, FR32:$src2, FR32:$src3)>;
376 def : Pat<(f32 (fsub FR32:$src1, (fmul FR32:$src2, (loadf32 addr:$src3)))),
377 (VFNMADDSSr231m FR32:$src1, FR32:$src2, addr:$src3)>;
379 def : Pat<(f64 (fsub FR64:$src1, (fmul FR64:$src2, FR64:$src3))),
380 (VFNMADDSDr231r FR64:$src1, FR64:$src2, FR64:$src3)>;
382 def : Pat<(f64 (fsub FR64:$src1, (fmul FR64:$src2, (loadf64 addr:$src3)))),
383 (VFNMADDSDr231m FR64:$src1, FR64:$src2, addr:$src3)>;
387 //===----------------------------------------------------------------------===//
388 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
389 //===----------------------------------------------------------------------===//
392 multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop,
393 ComplexPattern mem_cpat, Intrinsic Int> {
394 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
395 (ins VR128:$src1, VR128:$src2, VR128:$src3),
396 !strconcat(OpcodeStr,
397 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
399 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
400 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
401 (ins VR128:$src1, VR128:$src2, memop:$src3),
402 !strconcat(OpcodeStr,
403 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
405 (Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, VEX_W, MemOp4;
406 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
407 (ins VR128:$src1, memop:$src2, VR128:$src3),
408 !strconcat(OpcodeStr,
409 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
411 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>;
413 let isCodeGenOnly = 1 in
414 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
415 (ins VR128:$src1, VR128:$src2, VR128:$src3),
416 !strconcat(OpcodeStr,
417 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
420 multiclass fma4p<bits<8> opc, string OpcodeStr,
421 Intrinsic Int128, Intrinsic Int256,
422 PatFrag ld_frag128, PatFrag ld_frag256> {
423 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
424 (ins VR128:$src1, VR128:$src2, VR128:$src3),
425 !strconcat(OpcodeStr,
426 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
428 (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
429 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
430 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
431 !strconcat(OpcodeStr,
432 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
433 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
434 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
435 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
436 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
437 !strconcat(OpcodeStr,
438 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
440 (Int128 VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
441 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
442 (ins VR256:$src1, VR256:$src2, VR256:$src3),
443 !strconcat(OpcodeStr,
444 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
446 (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, VEX_W, MemOp4;
447 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
448 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
449 !strconcat(OpcodeStr,
450 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
451 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
452 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4;
453 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
454 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
455 !strconcat(OpcodeStr,
456 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
458 (Int256 VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>;
460 let isCodeGenOnly = 1 in {
461 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
462 (ins VR128:$src1, VR128:$src2, VR128:$src3),
463 !strconcat(OpcodeStr,
464 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
465 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
466 (ins VR256:$src1, VR256:$src2, VR256:$src3),
467 !strconcat(OpcodeStr,
468 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
469 } // isCodeGenOnly = 1
472 let Predicates = [HasFMA4] in {
474 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem, sse_load_f32,
475 int_x86_fma4_vfmadd_ss>;
476 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem, sse_load_f64,
477 int_x86_fma4_vfmadd_sd>;
478 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", int_x86_fma4_vfmadd_ps,
479 int_x86_fma4_vfmadd_ps_256, memopv4f32, memopv8f32>;
480 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", int_x86_fma4_vfmadd_pd,
481 int_x86_fma4_vfmadd_pd_256, memopv2f64, memopv4f64>;
482 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem, sse_load_f32,
483 int_x86_fma4_vfmsub_ss>;
484 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem, sse_load_f64,
485 int_x86_fma4_vfmsub_sd>;
486 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", int_x86_fma4_vfmsub_ps,
487 int_x86_fma4_vfmsub_ps_256, memopv4f32, memopv8f32>;
488 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", int_x86_fma4_vfmsub_pd,
489 int_x86_fma4_vfmsub_pd_256, memopv2f64, memopv4f64>;
490 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem, sse_load_f32,
491 int_x86_fma4_vfnmadd_ss>;
492 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
493 int_x86_fma4_vfnmadd_sd>;
494 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", int_x86_fma4_vfnmadd_ps,
495 int_x86_fma4_vfnmadd_ps_256, memopv4f32, memopv8f32>;
496 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", int_x86_fma4_vfnmadd_pd,
497 int_x86_fma4_vfnmadd_pd_256, memopv2f64, memopv4f64>;
498 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem, sse_load_f32,
499 int_x86_fma4_vfnmsub_ss>;
500 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
501 int_x86_fma4_vfnmsub_sd>;
502 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", int_x86_fma4_vfnmsub_ps,
503 int_x86_fma4_vfnmsub_ps_256, memopv4f32, memopv8f32>;
504 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", int_x86_fma4_vfnmsub_pd,
505 int_x86_fma4_vfnmsub_pd_256, memopv2f64, memopv4f64>;
506 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", int_x86_fma4_vfmaddsub_ps,
507 int_x86_fma4_vfmaddsub_ps_256, memopv4f32, memopv8f32>;
508 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", int_x86_fma4_vfmaddsub_pd,
509 int_x86_fma4_vfmaddsub_pd_256, memopv2f64, memopv4f64>;
510 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", int_x86_fma4_vfmsubadd_ps,
511 int_x86_fma4_vfmsubadd_ps_256, memopv4f32, memopv8f32>;
512 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", int_x86_fma4_vfmsubadd_pd,
513 int_x86_fma4_vfmsubadd_pd_256, memopv2f64, memopv4f64>;